1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstPrinter.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/MCAsmInfo.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define DEBUG_TYPE "asm-printer"
27 #include "ARMGenAsmWriter.inc"
29 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
31 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
32 static unsigned translateShiftImm(unsigned imm) {
33 // lsr #32 and asr #32 exist, but should be encoded as a 0.
34 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
41 /// Prints the shift value with an immediate value.
42 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
43 unsigned ShImm, bool UseMarkup) {
44 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
48 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
49 O << getShiftOpcStr(ShOpc);
51 if (ShOpc != ARM_AM::rrx) {
55 O << "#" << translateShiftImm(ShImm);
61 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
62 const MCInstrInfo &MII,
63 const MCRegisterInfo &MRI,
64 const MCSubtargetInfo &STI) :
65 MCInstPrinter(MAI, MII, MRI) {
66 // Initialize the set of available features.
67 setAvailableFeatures(STI.getFeatureBits());
70 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
72 << getRegisterName(RegNo)
76 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
78 unsigned Opcode = MI->getOpcode();
82 // Check for HINT instructions w/ canonical names.
86 switch (MI->getOperand(0).getImm()) {
87 case 0: O << "\tnop"; break;
88 case 1: O << "\tyield"; break;
89 case 2: O << "\twfe"; break;
90 case 3: O << "\twfi"; break;
91 case 4: O << "\tsev"; break;
93 if ((getAvailableFeatures() & ARM::HasV8Ops)) {
96 } // Fallthrough for non-v8
98 // Anything else should just print normally.
99 printInstruction(MI, O);
100 printAnnotation(O, Annot);
103 printPredicateOperand(MI, 1, O);
104 if (Opcode == ARM::t2HINT)
106 printAnnotation(O, Annot);
109 // Check for MOVs and print canonical forms, instead.
111 // FIXME: Thumb variants?
112 const MCOperand &Dst = MI->getOperand(0);
113 const MCOperand &MO1 = MI->getOperand(1);
114 const MCOperand &MO2 = MI->getOperand(2);
115 const MCOperand &MO3 = MI->getOperand(3);
117 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
118 printSBitModifierOperand(MI, 6, O);
119 printPredicateOperand(MI, 4, O);
122 printRegName(O, Dst.getReg());
124 printRegName(O, MO1.getReg());
127 printRegName(O, MO2.getReg());
128 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
129 printAnnotation(O, Annot);
134 // FIXME: Thumb variants?
135 const MCOperand &Dst = MI->getOperand(0);
136 const MCOperand &MO1 = MI->getOperand(1);
137 const MCOperand &MO2 = MI->getOperand(2);
139 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
140 printSBitModifierOperand(MI, 5, O);
141 printPredicateOperand(MI, 3, O);
144 printRegName(O, Dst.getReg());
146 printRegName(O, MO1.getReg());
148 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
149 printAnnotation(O, Annot);
155 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
157 printAnnotation(O, Annot);
163 case ARM::t2STMDB_UPD:
164 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
165 // Should only print PUSH if there are at least two registers in the list.
167 printPredicateOperand(MI, 2, O);
168 if (Opcode == ARM::t2STMDB_UPD)
171 printRegisterList(MI, 4, O);
172 printAnnotation(O, Annot);
177 case ARM::STR_PRE_IMM:
178 if (MI->getOperand(2).getReg() == ARM::SP &&
179 MI->getOperand(3).getImm() == -4) {
181 printPredicateOperand(MI, 4, O);
183 printRegName(O, MI->getOperand(1).getReg());
185 printAnnotation(O, Annot);
192 case ARM::t2LDMIA_UPD:
193 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) {
194 // Should only print POP if there are at least two registers in the list.
196 printPredicateOperand(MI, 2, O);
197 if (Opcode == ARM::t2LDMIA_UPD)
200 printRegisterList(MI, 4, O);
201 printAnnotation(O, Annot);
206 case ARM::LDR_POST_IMM:
207 if (MI->getOperand(2).getReg() == ARM::SP &&
208 MI->getOperand(4).getImm() == 4) {
210 printPredicateOperand(MI, 5, O);
212 printRegName(O, MI->getOperand(0).getReg());
214 printAnnotation(O, Annot);
220 case ARM::VSTMSDB_UPD:
221 case ARM::VSTMDDB_UPD:
222 if (MI->getOperand(0).getReg() == ARM::SP) {
223 O << '\t' << "vpush";
224 printPredicateOperand(MI, 2, O);
226 printRegisterList(MI, 4, O);
227 printAnnotation(O, Annot);
233 case ARM::VLDMSIA_UPD:
234 case ARM::VLDMDIA_UPD:
235 if (MI->getOperand(0).getReg() == ARM::SP) {
237 printPredicateOperand(MI, 2, O);
239 printRegisterList(MI, 4, O);
240 printAnnotation(O, Annot);
246 bool Writeback = true;
247 unsigned BaseReg = MI->getOperand(0).getReg();
248 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
249 if (MI->getOperand(i).getReg() == BaseReg)
255 printPredicateOperand(MI, 1, O);
257 printRegName(O, BaseReg);
258 if (Writeback) O << "!";
260 printRegisterList(MI, 3, O);
261 printAnnotation(O, Annot);
265 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
266 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
267 // a single GPRPair reg operand is used in the .td file to replace the two
268 // GPRs. However, when decoding them, the two GRPs cannot be automatically
269 // expressed as a GPRPair, so we have to manually merge them.
270 // FIXME: We would really like to be able to tablegen'erate this.
271 case ARM::LDREXD: case ARM::STREXD:
272 case ARM::LDAEXD: case ARM::STLEXD: {
273 const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
274 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
275 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
276 if (MRC.contains(Reg)) {
279 NewMI.setOpcode(Opcode);
282 NewMI.addOperand(MI->getOperand(0));
283 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
284 &MRI.getRegClass(ARM::GPRPairRegClassID)));
285 NewMI.addOperand(NewReg);
287 // Copy the rest operands into NewMI.
288 for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
289 NewMI.addOperand(MI->getOperand(i));
290 printInstruction(&NewMI, O);
295 // B9.3.3 ERET (Thumb)
296 // For a target that has Virtualization Extensions, ERET is the preferred
297 // disassembly of SUBS PC, LR, #0
298 case ARM::t2SUBS_PC_LR: {
299 if (MI->getNumOperands() == 3 &&
300 MI->getOperand(0).isImm() &&
301 MI->getOperand(0).getImm() == 0 &&
302 (getAvailableFeatures() & ARM::FeatureVirtualization)) {
304 printPredicateOperand(MI, 1, O);
305 printAnnotation(O, Annot);
312 printInstruction(MI, O);
313 printAnnotation(O, Annot);
316 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
318 const MCOperand &Op = MI->getOperand(OpNo);
320 unsigned Reg = Op.getReg();
321 printRegName(O, Reg);
322 } else if (Op.isImm()) {
324 << '#' << formatImm(Op.getImm())
327 assert(Op.isExpr() && "unknown operand kind in printOperand");
328 const MCExpr *Expr = Op.getExpr();
329 switch (Expr->getKind()) {
333 case MCExpr::Constant: {
334 // If a symbolic branch target was added as a constant expression then
335 // print that address in hex. And only print 32 unsigned bits for the
337 const MCConstantExpr *Constant = cast<MCConstantExpr>(Expr);
338 int64_t TargetAddress;
339 if (!Constant->EvaluateAsAbsolute(TargetAddress)) {
343 O.write_hex(static_cast<uint32_t>(TargetAddress));
348 // FIXME: Should we always treat this as if it is a constant literal and
349 // prefix it with '#'?
356 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
358 const MCOperand &MO1 = MI->getOperand(OpNum);
364 O << markup("<mem:") << "[pc, ";
366 int32_t OffImm = (int32_t)MO1.getImm();
367 bool isSub = OffImm < 0;
369 // Special value for #-0. All others are normal.
370 if (OffImm == INT32_MIN)
374 << "#-" << formatImm(-OffImm)
378 << "#" << formatImm(OffImm)
381 O << "]" << markup(">");
384 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
385 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
387 // REG REG 0,SH_OPC - e.g. R5, ROR R3
388 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
389 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
391 const MCOperand &MO1 = MI->getOperand(OpNum);
392 const MCOperand &MO2 = MI->getOperand(OpNum+1);
393 const MCOperand &MO3 = MI->getOperand(OpNum+2);
395 printRegName(O, MO1.getReg());
397 // Print the shift opc.
398 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
399 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
400 if (ShOpc == ARM_AM::rrx)
404 printRegName(O, MO2.getReg());
405 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
408 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
410 const MCOperand &MO1 = MI->getOperand(OpNum);
411 const MCOperand &MO2 = MI->getOperand(OpNum+1);
413 printRegName(O, MO1.getReg());
415 // Print the shift opc.
416 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
417 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
421 //===--------------------------------------------------------------------===//
422 // Addressing Mode #2
423 //===--------------------------------------------------------------------===//
425 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
427 const MCOperand &MO1 = MI->getOperand(Op);
428 const MCOperand &MO2 = MI->getOperand(Op+1);
429 const MCOperand &MO3 = MI->getOperand(Op+2);
431 O << markup("<mem:") << "[";
432 printRegName(O, MO1.getReg());
435 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
439 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
440 << ARM_AM::getAM2Offset(MO3.getImm())
443 O << "]" << markup(">");
448 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
449 printRegName(O, MO2.getReg());
451 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
452 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
453 O << "]" << markup(">");
456 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
458 const MCOperand &MO1 = MI->getOperand(Op);
459 const MCOperand &MO2 = MI->getOperand(Op+1);
460 O << markup("<mem:") << "[";
461 printRegName(O, MO1.getReg());
463 printRegName(O, MO2.getReg());
464 O << "]" << markup(">");
467 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
469 const MCOperand &MO1 = MI->getOperand(Op);
470 const MCOperand &MO2 = MI->getOperand(Op+1);
471 O << markup("<mem:") << "[";
472 printRegName(O, MO1.getReg());
474 printRegName(O, MO2.getReg());
475 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
478 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
480 const MCOperand &MO1 = MI->getOperand(Op);
482 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
483 printOperand(MI, Op, O);
488 const MCOperand &MO3 = MI->getOperand(Op+2);
489 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
490 assert(IdxMode != ARMII::IndexModePost &&
491 "Should be pre or offset index op");
494 printAM2PreOrOffsetIndexOp(MI, Op, O);
497 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
500 const MCOperand &MO1 = MI->getOperand(OpNum);
501 const MCOperand &MO2 = MI->getOperand(OpNum+1);
504 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
506 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
512 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
513 printRegName(O, MO1.getReg());
515 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
516 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
519 //===--------------------------------------------------------------------===//
520 // Addressing Mode #3
521 //===--------------------------------------------------------------------===//
523 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
525 bool AlwaysPrintImm0) {
526 const MCOperand &MO1 = MI->getOperand(Op);
527 const MCOperand &MO2 = MI->getOperand(Op+1);
528 const MCOperand &MO3 = MI->getOperand(Op+2);
530 O << markup("<mem:") << '[';
531 printRegName(O, MO1.getReg());
534 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
535 printRegName(O, MO2.getReg());
536 O << ']' << markup(">");
540 //If the op is sub we have to print the immediate even if it is 0
541 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
542 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
544 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
548 << ARM_AM::getAddrOpcStr(op)
552 O << ']' << markup(">");
555 template <bool AlwaysPrintImm0>
556 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
558 const MCOperand &MO1 = MI->getOperand(Op);
559 if (!MO1.isReg()) { // For label symbolic references.
560 printOperand(MI, Op, O);
564 assert(ARM_AM::getAM3IdxMode(MI->getOperand(Op + 2).getImm()) !=
565 ARMII::IndexModePost &&
566 "unexpected idxmode");
567 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
570 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
573 const MCOperand &MO1 = MI->getOperand(OpNum);
574 const MCOperand &MO2 = MI->getOperand(OpNum+1);
577 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
578 printRegName(O, MO1.getReg());
582 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
584 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
588 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
591 const MCOperand &MO = MI->getOperand(OpNum);
592 unsigned Imm = MO.getImm();
594 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
598 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
600 const MCOperand &MO1 = MI->getOperand(OpNum);
601 const MCOperand &MO2 = MI->getOperand(OpNum+1);
603 O << (MO2.getImm() ? "" : "-");
604 printRegName(O, MO1.getReg());
607 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
610 const MCOperand &MO = MI->getOperand(OpNum);
611 unsigned Imm = MO.getImm();
613 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
618 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
620 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
622 O << ARM_AM::getAMSubModeStr(Mode);
625 template <bool AlwaysPrintImm0>
626 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
628 const MCOperand &MO1 = MI->getOperand(OpNum);
629 const MCOperand &MO2 = MI->getOperand(OpNum+1);
631 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
632 printOperand(MI, OpNum, O);
636 O << markup("<mem:") << "[";
637 printRegName(O, MO1.getReg());
639 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
640 ARM_AM::AddrOpc Op = ARM_AM::getAM5Op(MO2.getImm());
641 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
645 << ARM_AM::getAddrOpcStr(Op)
649 O << "]" << markup(">");
652 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
654 const MCOperand &MO1 = MI->getOperand(OpNum);
655 const MCOperand &MO2 = MI->getOperand(OpNum+1);
657 O << markup("<mem:") << "[";
658 printRegName(O, MO1.getReg());
660 O << ":" << (MO2.getImm() << 3);
662 O << "]" << markup(">");
665 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
667 const MCOperand &MO1 = MI->getOperand(OpNum);
668 O << markup("<mem:") << "[";
669 printRegName(O, MO1.getReg());
670 O << "]" << markup(">");
673 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
676 const MCOperand &MO = MI->getOperand(OpNum);
677 if (MO.getReg() == 0)
681 printRegName(O, MO.getReg());
685 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
688 const MCOperand &MO = MI->getOperand(OpNum);
689 uint32_t v = ~MO.getImm();
690 int32_t lsb = countTrailingZeros(v);
691 int32_t width = (32 - countLeadingZeros (v)) - lsb;
692 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
693 O << markup("<imm:") << '#' << lsb << markup(">")
695 << markup("<imm:") << '#' << width << markup(">");
698 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
700 unsigned val = MI->getOperand(OpNum).getImm();
701 O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops));
704 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
706 unsigned val = MI->getOperand(OpNum).getImm();
707 O << ARM_ISB::InstSyncBOptToString(val);
710 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
712 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
713 bool isASR = (ShiftOp & (1 << 5)) != 0;
714 unsigned Amt = ShiftOp & 0x1f;
718 << "#" << (Amt == 0 ? 32 : Amt)
729 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
731 unsigned Imm = MI->getOperand(OpNum).getImm();
734 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
735 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
738 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
740 unsigned Imm = MI->getOperand(OpNum).getImm();
741 // A shift amount of 32 is encoded as 0.
744 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
745 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
748 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
751 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
752 if (i != OpNum) O << ", ";
753 printRegName(O, MI->getOperand(i).getReg());
758 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
760 unsigned Reg = MI->getOperand(OpNum).getReg();
761 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
763 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
767 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
769 const MCOperand &Op = MI->getOperand(OpNum);
776 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
778 const MCOperand &Op = MI->getOperand(OpNum);
779 O << ARM_PROC::IModToString(Op.getImm());
782 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
784 const MCOperand &Op = MI->getOperand(OpNum);
785 unsigned IFlags = Op.getImm();
786 for (int i=2; i >= 0; --i)
787 if (IFlags & (1 << i))
788 O << ARM_PROC::IFlagsToString(1 << i);
794 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
796 const MCOperand &Op = MI->getOperand(OpNum);
797 unsigned SpecRegRBit = Op.getImm() >> 4;
798 unsigned Mask = Op.getImm() & 0xf;
799 uint64_t FeatureBits = getAvailableFeatures();
801 if (FeatureBits & ARM::FeatureMClass) {
802 unsigned SYSm = Op.getImm();
803 unsigned Opcode = MI->getOpcode();
805 // For writes, handle extended mask bits if the DSP extension is present.
806 if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::FeatureDSPThumb2)) {
808 case 0x400: O << "apsr_g"; return;
809 case 0xc00: O << "apsr_nzcvqg"; return;
810 case 0x401: O << "iapsr_g"; return;
811 case 0xc01: O << "iapsr_nzcvqg"; return;
812 case 0x402: O << "eapsr_g"; return;
813 case 0xc02: O << "eapsr_nzcvqg"; return;
814 case 0x403: O << "xpsr_g"; return;
815 case 0xc03: O << "xpsr_nzcvqg"; return;
819 // Handle the basic 8-bit mask.
822 if (Opcode == ARM::t2MSR_M && (FeatureBits & ARM::HasV7Ops)) {
823 // ARMv7-M deprecates using MSR APSR without a _<bits> qualifier as an
824 // alias for MSR APSR_nzcvq.
826 case 0: O << "apsr_nzcvq"; return;
827 case 1: O << "iapsr_nzcvq"; return;
828 case 2: O << "eapsr_nzcvq"; return;
829 case 3: O << "xpsr_nzcvq"; return;
834 default: llvm_unreachable("Unexpected mask value!");
835 case 0: O << "apsr"; return;
836 case 1: O << "iapsr"; return;
837 case 2: O << "eapsr"; return;
838 case 3: O << "xpsr"; return;
839 case 5: O << "ipsr"; return;
840 case 6: O << "epsr"; return;
841 case 7: O << "iepsr"; return;
842 case 8: O << "msp"; return;
843 case 9: O << "psp"; return;
844 case 16: O << "primask"; return;
845 case 17: O << "basepri"; return;
846 case 18: O << "basepri_max"; return;
847 case 19: O << "faultmask"; return;
848 case 20: O << "control"; return;
852 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
853 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
854 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
857 default: llvm_unreachable("Unexpected mask value!");
858 case 4: O << "g"; return;
859 case 8: O << "nzcvq"; return;
860 case 12: O << "nzcvqg"; return;
871 if (Mask & 8) O << 'f';
872 if (Mask & 4) O << 's';
873 if (Mask & 2) O << 'x';
874 if (Mask & 1) O << 'c';
878 void ARMInstPrinter::printBankedRegOperand(const MCInst *MI, unsigned OpNum,
880 uint32_t Banked = MI->getOperand(OpNum).getImm();
881 uint32_t R = (Banked & 0x20) >> 5;
882 uint32_t SysM = Banked & 0x1f;
884 // Nothing much we can do about this, the encodings are specified in B9.2.3 of
885 // the ARM ARM v7C, and are all over the shop.
890 case 0x0e: O << "fiq"; return;
891 case 0x10: O << "irq"; return;
892 case 0x12: O << "svc"; return;
893 case 0x14: O << "abt"; return;
894 case 0x16: O << "und"; return;
895 case 0x1c: O << "mon"; return;
896 case 0x1e: O << "hyp"; return;
897 default: llvm_unreachable("Invalid banked SPSR register");
901 assert(!R && "should have dealt with SPSR regs");
902 const char *RegNames[] = {
903 "r8_usr", "r9_usr", "r10_usr", "r11_usr", "r12_usr", "sp_usr", "lr_usr", "",
904 "r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "sp_fiq", "lr_fiq", "",
905 "lr_irq", "sp_irq", "lr_svc", "sp_svc", "lr_abt", "sp_abt", "lr_und", "sp_und",
906 "", "", "", "", "lr_mon", "sp_mon", "elr_hyp", "sp_hyp"
908 const char *Name = RegNames[SysM];
909 assert(Name[0] && "invalid banked register operand");
914 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
916 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
917 // Handle the undefined 15 CC value here for printing so we don't abort().
918 if ((unsigned)CC == 15)
920 else if (CC != ARMCC::AL)
921 O << ARMCondCodeToString(CC);
924 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
927 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
928 O << ARMCondCodeToString(CC);
931 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
933 if (MI->getOperand(OpNum).getReg()) {
934 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
935 "Expect ARM CPSR register!");
940 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
942 O << MI->getOperand(OpNum).getImm();
945 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
947 O << "p" << MI->getOperand(OpNum).getImm();
950 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
952 O << "c" << MI->getOperand(OpNum).getImm();
955 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
957 O << "{" << MI->getOperand(OpNum).getImm() << "}";
960 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
962 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
965 template<unsigned scale>
966 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
968 const MCOperand &MO = MI->getOperand(OpNum);
975 int32_t OffImm = (int32_t)MO.getImm() << scale;
977 O << markup("<imm:");
978 if (OffImm == INT32_MIN)
981 O << "#-" << -OffImm;
987 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
990 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
994 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
996 unsigned Imm = MI->getOperand(OpNum).getImm();
998 << "#" << formatImm((Imm == 0 ? 32 : Imm))
1002 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1004 // (3 - the number of trailing zeros) is the number of then / else.
1005 unsigned Mask = MI->getOperand(OpNum).getImm();
1006 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
1007 unsigned CondBit0 = Firstcond & 1;
1008 unsigned NumTZ = countTrailingZeros(Mask);
1009 assert(NumTZ <= 3 && "Invalid IT mask!");
1010 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
1011 bool T = ((Mask >> Pos) & 1) == CondBit0;
1019 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
1021 const MCOperand &MO1 = MI->getOperand(Op);
1022 const MCOperand &MO2 = MI->getOperand(Op + 1);
1024 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1025 printOperand(MI, Op, O);
1029 O << markup("<mem:") << "[";
1030 printRegName(O, MO1.getReg());
1031 if (unsigned RegNum = MO2.getReg()) {
1033 printRegName(O, RegNum);
1035 O << "]" << markup(">");
1038 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1042 const MCOperand &MO1 = MI->getOperand(Op);
1043 const MCOperand &MO2 = MI->getOperand(Op + 1);
1045 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1046 printOperand(MI, Op, O);
1050 O << markup("<mem:") << "[";
1051 printRegName(O, MO1.getReg());
1052 if (unsigned ImmOffs = MO2.getImm()) {
1055 << "#" << formatImm(ImmOffs * Scale)
1058 O << "]" << markup(">");
1061 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1064 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
1067 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1070 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
1073 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1076 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1079 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1081 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1084 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1085 // register with shift forms.
1086 // REG 0 0 - e.g. R5
1087 // REG IMM, SH_OPC - e.g. R5, LSL #3
1088 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1090 const MCOperand &MO1 = MI->getOperand(OpNum);
1091 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1093 unsigned Reg = MO1.getReg();
1094 printRegName(O, Reg);
1096 // Print the shift opc.
1097 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1098 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1099 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1102 template <bool AlwaysPrintImm0>
1103 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1105 const MCOperand &MO1 = MI->getOperand(OpNum);
1106 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1108 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1109 printOperand(MI, OpNum, O);
1113 O << markup("<mem:") << "[";
1114 printRegName(O, MO1.getReg());
1116 int32_t OffImm = (int32_t)MO2.getImm();
1117 bool isSub = OffImm < 0;
1118 // Special value for #-0. All others are normal.
1119 if (OffImm == INT32_MIN)
1124 << "#-" << formatImm(-OffImm)
1127 else if (AlwaysPrintImm0 || OffImm > 0) {
1130 << "#" << formatImm(OffImm)
1133 O << "]" << markup(">");
1136 template<bool AlwaysPrintImm0>
1137 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1140 const MCOperand &MO1 = MI->getOperand(OpNum);
1141 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1143 O << markup("<mem:") << "[";
1144 printRegName(O, MO1.getReg());
1146 int32_t OffImm = (int32_t)MO2.getImm();
1147 bool isSub = OffImm < 0;
1149 if (OffImm == INT32_MIN)
1156 } else if (AlwaysPrintImm0 || OffImm > 0) {
1162 O << "]" << markup(">");
1165 template<bool AlwaysPrintImm0>
1166 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1169 const MCOperand &MO1 = MI->getOperand(OpNum);
1170 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1172 if (!MO1.isReg()) { // For label symbolic references.
1173 printOperand(MI, OpNum, O);
1177 O << markup("<mem:") << "[";
1178 printRegName(O, MO1.getReg());
1180 int32_t OffImm = (int32_t)MO2.getImm();
1181 bool isSub = OffImm < 0;
1183 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1186 if (OffImm == INT32_MIN)
1193 } else if (AlwaysPrintImm0 || OffImm > 0) {
1199 O << "]" << markup(">");
1202 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
1205 const MCOperand &MO1 = MI->getOperand(OpNum);
1206 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1208 O << markup("<mem:") << "[";
1209 printRegName(O, MO1.getReg());
1213 << "#" << formatImm(MO2.getImm() * 4)
1216 O << "]" << markup(">");
1219 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1222 const MCOperand &MO1 = MI->getOperand(OpNum);
1223 int32_t OffImm = (int32_t)MO1.getImm();
1224 O << ", " << markup("<imm:");
1225 if (OffImm == INT32_MIN)
1227 else if (OffImm < 0)
1228 O << "#-" << -OffImm;
1234 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1237 const MCOperand &MO1 = MI->getOperand(OpNum);
1238 int32_t OffImm = (int32_t)MO1.getImm();
1240 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1242 O << ", " << markup("<imm:");
1243 if (OffImm == INT32_MIN)
1245 else if (OffImm < 0)
1246 O << "#-" << -OffImm;
1252 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1255 const MCOperand &MO1 = MI->getOperand(OpNum);
1256 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1257 const MCOperand &MO3 = MI->getOperand(OpNum+2);
1259 O << markup("<mem:") << "[";
1260 printRegName(O, MO1.getReg());
1262 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1264 printRegName(O, MO2.getReg());
1266 unsigned ShAmt = MO3.getImm();
1268 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1274 O << "]" << markup(">");
1277 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1279 const MCOperand &MO = MI->getOperand(OpNum);
1280 O << markup("<imm:")
1281 << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1285 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1287 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1289 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1290 O << markup("<imm:")
1296 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1298 unsigned Imm = MI->getOperand(OpNum).getImm();
1299 O << markup("<imm:")
1300 << "#" << formatImm(Imm + 1)
1304 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1306 unsigned Imm = MI->getOperand(OpNum).getImm();
1313 default: assert (0 && "illegal ror immediate!");
1314 case 1: O << "8"; break;
1315 case 2: O << "16"; break;
1316 case 3: O << "24"; break;
1321 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1323 MCOperand Op = MI->getOperand(OpNum);
1325 // Support for fixups (MCFixup)
1327 return printOperand(MI, OpNum, O);
1329 unsigned Bits = Op.getImm() & 0xFF;
1330 unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1332 bool PrintUnsigned = false;
1333 switch (MI->getOpcode()){
1335 // Movs to PC should be treated unsigned
1336 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1339 // Movs to special registers should be treated unsigned
1340 PrintUnsigned = true;
1344 int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1345 if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1346 // #rot has the least possible value
1347 O << "#" << markup("<imm:");
1349 O << static_cast<uint32_t>(Rotated);
1356 // Explicit #bits, #rot implied
1367 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1369 O << markup("<imm:")
1370 << "#" << 16 - MI->getOperand(OpNum).getImm()
1374 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1376 O << markup("<imm:")
1377 << "#" << 32 - MI->getOperand(OpNum).getImm()
1381 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1383 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1386 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1389 printRegName(O, MI->getOperand(OpNum).getReg());
1393 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1395 unsigned Reg = MI->getOperand(OpNum).getReg();
1396 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1397 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1399 printRegName(O, Reg0);
1401 printRegName(O, Reg1);
1405 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1408 unsigned Reg = MI->getOperand(OpNum).getReg();
1409 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1410 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1412 printRegName(O, Reg0);
1414 printRegName(O, Reg1);
1418 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1420 // Normally, it's not safe to use register enum values directly with
1421 // addition to get the next register, but for VFP registers, the
1422 // sort order is guaranteed because they're all of the form D<n>.
1424 printRegName(O, MI->getOperand(OpNum).getReg());
1426 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1428 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1432 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1434 // Normally, it's not safe to use register enum values directly with
1435 // addition to get the next register, but for VFP registers, the
1436 // sort order is guaranteed because they're all of the form D<n>.
1438 printRegName(O, MI->getOperand(OpNum).getReg());
1440 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1442 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1444 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1448 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1452 printRegName(O, MI->getOperand(OpNum).getReg());
1456 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1459 unsigned Reg = MI->getOperand(OpNum).getReg();
1460 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1461 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1463 printRegName(O, Reg0);
1465 printRegName(O, Reg1);
1469 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1472 // Normally, it's not safe to use register enum values directly with
1473 // addition to get the next register, but for VFP registers, the
1474 // sort order is guaranteed because they're all of the form D<n>.
1476 printRegName(O, MI->getOperand(OpNum).getReg());
1478 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1480 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1484 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1487 // Normally, it's not safe to use register enum values directly with
1488 // addition to get the next register, but for VFP registers, the
1489 // sort order is guaranteed because they're all of the form D<n>.
1491 printRegName(O, MI->getOperand(OpNum).getReg());
1493 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1495 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1497 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1501 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1504 unsigned Reg = MI->getOperand(OpNum).getReg();
1505 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1506 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1508 printRegName(O, Reg0);
1510 printRegName(O, Reg1);
1514 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1517 // Normally, it's not safe to use register enum values directly with
1518 // addition to get the next register, but for VFP registers, the
1519 // sort order is guaranteed because they're all of the form D<n>.
1521 printRegName(O, MI->getOperand(OpNum).getReg());
1523 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1525 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1529 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1532 // Normally, it's not safe to use register enum values directly with
1533 // addition to get the next register, but for VFP registers, the
1534 // sort order is guaranteed because they're all of the form D<n>.
1536 printRegName(O, MI->getOperand(OpNum).getReg());
1538 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1540 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1542 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1546 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1549 // Normally, it's not safe to use register enum values directly with
1550 // addition to get the next register, but for VFP registers, the
1551 // sort order is guaranteed because they're all of the form D<n>.
1553 printRegName(O, MI->getOperand(OpNum).getReg());
1555 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1557 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1561 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1564 // Normally, it's not safe to use register enum values directly with
1565 // addition to get the next register, but for VFP registers, the
1566 // sort order is guaranteed because they're all of the form D<n>.
1568 printRegName(O, MI->getOperand(OpNum).getReg());
1570 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1572 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1574 printRegName(O, MI->getOperand(OpNum).getReg() + 6);