1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/raw_ostream.h"
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31 static unsigned translateShiftImm(unsigned imm) {
32 // lsr #32 and asr #32 exist, but should be encoded as a 0.
33 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
40 /// Prints the shift value with an immediate value.
41 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
42 unsigned ShImm, bool UseMarkup) {
43 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
47 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
48 O << getShiftOpcStr(ShOpc);
50 if (ShOpc != ARM_AM::rrx) {
54 O << "#" << translateShiftImm(ShImm);
60 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
61 const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI,
63 const MCSubtargetInfo &STI) :
64 MCInstPrinter(MAI, MII, MRI) {
65 // Initialize the set of available features.
66 setAvailableFeatures(STI.getFeatureBits());
69 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
71 << getRegisterName(RegNo)
75 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
77 unsigned Opcode = MI->getOpcode();
79 // Check for HINT instructions w/ canonical names.
80 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
81 switch (MI->getOperand(0).getImm()) {
82 case 0: O << "\tnop"; break;
83 case 1: O << "\tyield"; break;
84 case 2: O << "\twfe"; break;
85 case 3: O << "\twfi"; break;
86 case 4: O << "\tsev"; break;
88 // Anything else should just print normally.
89 printInstruction(MI, O);
90 printAnnotation(O, Annot);
93 printPredicateOperand(MI, 1, O);
94 if (Opcode == ARM::t2HINT)
96 printAnnotation(O, Annot);
100 // Check for MOVs and print canonical forms, instead.
101 if (Opcode == ARM::MOVsr) {
102 // FIXME: Thumb variants?
103 const MCOperand &Dst = MI->getOperand(0);
104 const MCOperand &MO1 = MI->getOperand(1);
105 const MCOperand &MO2 = MI->getOperand(2);
106 const MCOperand &MO3 = MI->getOperand(3);
108 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
109 printSBitModifierOperand(MI, 6, O);
110 printPredicateOperand(MI, 4, O);
113 printRegName(O, Dst.getReg());
115 printRegName(O, MO1.getReg());
118 printRegName(O, MO2.getReg());
119 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
120 printAnnotation(O, Annot);
124 if (Opcode == ARM::MOVsi) {
125 // FIXME: Thumb variants?
126 const MCOperand &Dst = MI->getOperand(0);
127 const MCOperand &MO1 = MI->getOperand(1);
128 const MCOperand &MO2 = MI->getOperand(2);
130 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
131 printSBitModifierOperand(MI, 5, O);
132 printPredicateOperand(MI, 3, O);
135 printRegName(O, Dst.getReg());
137 printRegName(O, MO1.getReg());
139 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
140 printAnnotation(O, Annot);
146 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
148 printAnnotation(O, Annot);
154 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
155 MI->getOperand(0).getReg() == ARM::SP &&
156 MI->getNumOperands() > 5) {
157 // Should only print PUSH if there are at least two registers in the list.
159 printPredicateOperand(MI, 2, O);
160 if (Opcode == ARM::t2STMDB_UPD)
163 printRegisterList(MI, 4, O);
164 printAnnotation(O, Annot);
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
168 MI->getOperand(3).getImm() == -4) {
170 printPredicateOperand(MI, 4, O);
172 printRegName(O, MI->getOperand(1).getReg());
174 printAnnotation(O, Annot);
179 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
180 MI->getOperand(0).getReg() == ARM::SP &&
181 MI->getNumOperands() > 5) {
182 // Should only print POP if there are at least two registers in the list.
184 printPredicateOperand(MI, 2, O);
185 if (Opcode == ARM::t2LDMIA_UPD)
188 printRegisterList(MI, 4, O);
189 printAnnotation(O, Annot);
192 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
193 MI->getOperand(4).getImm() == 4) {
195 printPredicateOperand(MI, 5, O);
197 printRegName(O, MI->getOperand(0).getReg());
199 printAnnotation(O, Annot);
205 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
206 MI->getOperand(0).getReg() == ARM::SP) {
207 O << '\t' << "vpush";
208 printPredicateOperand(MI, 2, O);
210 printRegisterList(MI, 4, O);
211 printAnnotation(O, Annot);
216 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
217 MI->getOperand(0).getReg() == ARM::SP) {
219 printPredicateOperand(MI, 2, O);
221 printRegisterList(MI, 4, O);
222 printAnnotation(O, Annot);
226 if (Opcode == ARM::tLDMIA) {
227 bool Writeback = true;
228 unsigned BaseReg = MI->getOperand(0).getReg();
229 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
230 if (MI->getOperand(i).getReg() == BaseReg)
236 printPredicateOperand(MI, 1, O);
238 printRegName(O, BaseReg);
239 if (Writeback) O << "!";
241 printRegisterList(MI, 3, O);
242 printAnnotation(O, Annot);
247 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
248 MI->getOperand(1).getReg() == ARM::R8) {
250 printPredicateOperand(MI, 2, O);
251 printAnnotation(O, Annot);
255 printInstruction(MI, O);
256 printAnnotation(O, Annot);
259 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
261 const MCOperand &Op = MI->getOperand(OpNo);
263 unsigned Reg = Op.getReg();
264 printRegName(O, Reg);
265 } else if (Op.isImm()) {
267 << '#' << Op.getImm()
270 assert(Op.isExpr() && "unknown operand kind in printOperand");
271 // If a symbolic branch target was added as a constant expression then print
272 // that address in hex. And only print 32 unsigned bits for the address.
273 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
275 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
277 O.write_hex((uint32_t)Address);
280 // Otherwise, just print the expression.
286 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
288 const MCOperand &MO1 = MI->getOperand(OpNum);
291 else if (MO1.isImm()) {
292 O << markup("<mem:") << "[pc, "
293 << markup("<imm:") << "#" << MO1.getImm()
294 << markup(">]>", "]");
297 llvm_unreachable("Unknown LDR label operand?");
300 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
301 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
303 // REG REG 0,SH_OPC - e.g. R5, ROR R3
304 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
305 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
307 const MCOperand &MO1 = MI->getOperand(OpNum);
308 const MCOperand &MO2 = MI->getOperand(OpNum+1);
309 const MCOperand &MO3 = MI->getOperand(OpNum+2);
311 printRegName(O, MO1.getReg());
313 // Print the shift opc.
314 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
315 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
316 if (ShOpc == ARM_AM::rrx)
320 printRegName(O, MO2.getReg());
321 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
324 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
326 const MCOperand &MO1 = MI->getOperand(OpNum);
327 const MCOperand &MO2 = MI->getOperand(OpNum+1);
329 printRegName(O, MO1.getReg());
331 // Print the shift opc.
332 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
333 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
337 //===--------------------------------------------------------------------===//
338 // Addressing Mode #2
339 //===--------------------------------------------------------------------===//
341 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
343 const MCOperand &MO1 = MI->getOperand(Op);
344 const MCOperand &MO2 = MI->getOperand(Op+1);
345 const MCOperand &MO3 = MI->getOperand(Op+2);
347 O << markup("<mem:") << "[";
348 printRegName(O, MO1.getReg());
351 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
355 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
356 << ARM_AM::getAM2Offset(MO3.getImm())
359 O << "]" << markup(">");
364 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
365 printRegName(O, MO2.getReg());
367 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
368 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
369 O << "]" << markup(">");
372 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
374 const MCOperand &MO1 = MI->getOperand(Op);
375 const MCOperand &MO2 = MI->getOperand(Op+1);
376 O << markup("<mem:") << "[";
377 printRegName(O, MO1.getReg());
379 printRegName(O, MO2.getReg());
380 O << "]" << markup(">");
383 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
385 const MCOperand &MO1 = MI->getOperand(Op);
386 const MCOperand &MO2 = MI->getOperand(Op+1);
387 O << markup("<mem:") << "[";
388 printRegName(O, MO1.getReg());
390 printRegName(O, MO2.getReg());
391 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
394 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
396 const MCOperand &MO1 = MI->getOperand(Op);
398 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
399 printOperand(MI, Op, O);
404 const MCOperand &MO3 = MI->getOperand(Op+2);
405 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
406 assert(IdxMode != ARMII::IndexModePost &&
407 "Should be pre or offset index op");
410 printAM2PreOrOffsetIndexOp(MI, Op, O);
413 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
416 const MCOperand &MO1 = MI->getOperand(OpNum);
417 const MCOperand &MO2 = MI->getOperand(OpNum+1);
420 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
422 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
428 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
429 printRegName(O, MO1.getReg());
431 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
432 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
435 //===--------------------------------------------------------------------===//
436 // Addressing Mode #3
437 //===--------------------------------------------------------------------===//
439 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
441 const MCOperand &MO1 = MI->getOperand(Op);
442 const MCOperand &MO2 = MI->getOperand(Op+1);
443 const MCOperand &MO3 = MI->getOperand(Op+2);
445 O << markup("<mem:") << "[";
446 printRegName(O, MO1.getReg());
447 O << "], " << markup(">");
450 O << (char)ARM_AM::getAM3Op(MO3.getImm());
451 printRegName(O, MO2.getReg());
455 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
458 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
463 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
465 const MCOperand &MO1 = MI->getOperand(Op);
466 const MCOperand &MO2 = MI->getOperand(Op+1);
467 const MCOperand &MO3 = MI->getOperand(Op+2);
469 O << markup("<mem:") << '[';
470 printRegName(O, MO1.getReg());
473 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
474 printRegName(O, MO2.getReg());
475 O << ']' << markup(">");
479 //If the op is sub we have to print the immediate even if it is 0
480 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
481 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
483 if (ImmOffs || (op == ARM_AM::sub)) {
487 << ARM_AM::getAddrOpcStr(op)
491 O << ']' << markup(">");
494 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
496 const MCOperand &MO1 = MI->getOperand(Op);
497 if (!MO1.isReg()) { // For label symbolic references.
498 printOperand(MI, Op, O);
502 const MCOperand &MO3 = MI->getOperand(Op+2);
503 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
505 if (IdxMode == ARMII::IndexModePost) {
506 printAM3PostIndexOp(MI, Op, O);
509 printAM3PreOrOffsetIndexOp(MI, Op, O);
512 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
515 const MCOperand &MO1 = MI->getOperand(OpNum);
516 const MCOperand &MO2 = MI->getOperand(OpNum+1);
519 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
520 printRegName(O, MO1.getReg());
524 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
526 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
530 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
533 const MCOperand &MO = MI->getOperand(OpNum);
534 unsigned Imm = MO.getImm();
536 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
540 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
542 const MCOperand &MO1 = MI->getOperand(OpNum);
543 const MCOperand &MO2 = MI->getOperand(OpNum+1);
545 O << (MO2.getImm() ? "" : "-");
546 printRegName(O, MO1.getReg());
549 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
552 const MCOperand &MO = MI->getOperand(OpNum);
553 unsigned Imm = MO.getImm();
555 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
560 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
562 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
564 O << ARM_AM::getAMSubModeStr(Mode);
567 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
569 const MCOperand &MO1 = MI->getOperand(OpNum);
570 const MCOperand &MO2 = MI->getOperand(OpNum+1);
572 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
573 printOperand(MI, OpNum, O);
577 O << markup("<mem:") << "[";
578 printRegName(O, MO1.getReg());
580 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
581 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
582 if (ImmOffs || Op == ARM_AM::sub) {
586 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
590 O << "]" << markup(">");
593 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
595 const MCOperand &MO1 = MI->getOperand(OpNum);
596 const MCOperand &MO2 = MI->getOperand(OpNum+1);
598 O << markup("<mem:") << "[";
599 printRegName(O, MO1.getReg());
601 // FIXME: Both darwin as and GNU as violate ARM docs here.
602 O << ", :" << (MO2.getImm() << 3);
604 O << "]" << markup(">");
607 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
609 const MCOperand &MO1 = MI->getOperand(OpNum);
610 O << markup("<mem:") << "[";
611 printRegName(O, MO1.getReg());
612 O << "]" << markup(">");
615 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
618 const MCOperand &MO = MI->getOperand(OpNum);
619 if (MO.getReg() == 0)
623 printRegName(O, MO.getReg());
627 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
630 const MCOperand &MO = MI->getOperand(OpNum);
631 uint32_t v = ~MO.getImm();
632 int32_t lsb = CountTrailingZeros_32(v);
633 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
634 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
635 O << markup("<imm:") << '#' << lsb << markup(">")
637 << markup("<imm:") << '#' << width << markup(">");
640 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
642 unsigned val = MI->getOperand(OpNum).getImm();
643 O << ARM_MB::MemBOptToString(val);
646 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
648 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
649 bool isASR = (ShiftOp & (1 << 5)) != 0;
650 unsigned Amt = ShiftOp & 0x1f;
654 << "#" << (Amt == 0 ? 32 : Amt)
665 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
667 unsigned Imm = MI->getOperand(OpNum).getImm();
670 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
671 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
674 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
676 unsigned Imm = MI->getOperand(OpNum).getImm();
677 // A shift amount of 32 is encoded as 0.
680 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
681 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
684 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
687 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
688 if (i != OpNum) O << ", ";
689 printRegName(O, MI->getOperand(i).getReg());
694 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
696 const MCOperand &Op = MI->getOperand(OpNum);
703 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
705 const MCOperand &Op = MI->getOperand(OpNum);
706 O << ARM_PROC::IModToString(Op.getImm());
709 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
711 const MCOperand &Op = MI->getOperand(OpNum);
712 unsigned IFlags = Op.getImm();
713 for (int i=2; i >= 0; --i)
714 if (IFlags & (1 << i))
715 O << ARM_PROC::IFlagsToString(1 << i);
721 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
723 const MCOperand &Op = MI->getOperand(OpNum);
724 unsigned SpecRegRBit = Op.getImm() >> 4;
725 unsigned Mask = Op.getImm() & 0xf;
727 if (getAvailableFeatures() & ARM::FeatureMClass) {
728 unsigned SYSm = Op.getImm();
729 unsigned Opcode = MI->getOpcode();
730 // For reads of the special registers ignore the "mask encoding" bits
731 // which are only for writes.
732 if (Opcode == ARM::t2MRS_M)
735 default: llvm_unreachable("Unexpected mask value!");
737 case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
738 case 0x400: O << "apsr_g"; return;
739 case 0xc00: O << "apsr_nzcvqg"; return;
741 case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
742 case 0x401: O << "iapsr_g"; return;
743 case 0xc01: O << "iapsr_nzcvqg"; return;
745 case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
746 case 0x402: O << "eapsr_g"; return;
747 case 0xc02: O << "eapsr_nzcvqg"; return;
749 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
750 case 0x403: O << "xpsr_g"; return;
751 case 0xc03: O << "xpsr_nzcvqg"; return;
753 case 0x805: O << "ipsr"; return;
755 case 0x806: O << "epsr"; return;
757 case 0x807: O << "iepsr"; return;
759 case 0x808: O << "msp"; return;
761 case 0x809: O << "psp"; return;
763 case 0x810: O << "primask"; return;
765 case 0x811: O << "basepri"; return;
767 case 0x812: O << "basepri_max"; return;
769 case 0x813: O << "faultmask"; return;
771 case 0x814: O << "control"; return;
775 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
776 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
777 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
780 default: llvm_unreachable("Unexpected mask value!");
781 case 4: O << "g"; return;
782 case 8: O << "nzcvq"; return;
783 case 12: O << "nzcvqg"; return;
794 if (Mask & 8) O << 'f';
795 if (Mask & 4) O << 's';
796 if (Mask & 2) O << 'x';
797 if (Mask & 1) O << 'c';
801 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
803 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
804 // Handle the undefined 15 CC value here for printing so we don't abort().
805 if ((unsigned)CC == 15)
807 else if (CC != ARMCC::AL)
808 O << ARMCondCodeToString(CC);
811 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
814 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
815 O << ARMCondCodeToString(CC);
818 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
820 if (MI->getOperand(OpNum).getReg()) {
821 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
822 "Expect ARM CPSR register!");
827 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
829 O << MI->getOperand(OpNum).getImm();
832 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
834 O << "p" << MI->getOperand(OpNum).getImm();
837 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
839 O << "c" << MI->getOperand(OpNum).getImm();
842 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
844 O << "{" << MI->getOperand(OpNum).getImm() << "}";
847 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
849 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
852 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
854 const MCOperand &MO = MI->getOperand(OpNum);
861 int32_t OffImm = (int32_t)MO.getImm();
863 O << markup("<imm:");
864 if (OffImm == INT32_MIN)
867 O << "#-" << -OffImm;
873 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
876 << "#" << MI->getOperand(OpNum).getImm() * 4
880 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
882 unsigned Imm = MI->getOperand(OpNum).getImm();
884 << "#" << (Imm == 0 ? 32 : Imm)
888 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
890 // (3 - the number of trailing zeros) is the number of then / else.
891 unsigned Mask = MI->getOperand(OpNum).getImm();
892 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
893 unsigned CondBit0 = Firstcond & 1;
894 unsigned NumTZ = CountTrailingZeros_32(Mask);
895 assert(NumTZ <= 3 && "Invalid IT mask!");
896 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
897 bool T = ((Mask >> Pos) & 1) == CondBit0;
905 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
907 const MCOperand &MO1 = MI->getOperand(Op);
908 const MCOperand &MO2 = MI->getOperand(Op + 1);
910 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
911 printOperand(MI, Op, O);
915 O << markup("<mem:") << "[";
916 printRegName(O, MO1.getReg());
917 if (unsigned RegNum = MO2.getReg()) {
919 printRegName(O, RegNum);
921 O << "]" << markup(">");
924 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
928 const MCOperand &MO1 = MI->getOperand(Op);
929 const MCOperand &MO2 = MI->getOperand(Op + 1);
931 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
932 printOperand(MI, Op, O);
936 O << markup("<mem:") << "[";
937 printRegName(O, MO1.getReg());
938 if (unsigned ImmOffs = MO2.getImm()) {
941 << "#" << ImmOffs * Scale
944 O << "]" << markup(">");
947 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
950 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
953 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
956 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
959 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
962 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
965 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
967 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
970 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
971 // register with shift forms.
973 // REG IMM, SH_OPC - e.g. R5, LSL #3
974 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
976 const MCOperand &MO1 = MI->getOperand(OpNum);
977 const MCOperand &MO2 = MI->getOperand(OpNum+1);
979 unsigned Reg = MO1.getReg();
980 printRegName(O, Reg);
982 // Print the shift opc.
983 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
984 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
985 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
988 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
990 const MCOperand &MO1 = MI->getOperand(OpNum);
991 const MCOperand &MO2 = MI->getOperand(OpNum+1);
993 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
994 printOperand(MI, OpNum, O);
998 O << markup("<mem:") << "[";
999 printRegName(O, MO1.getReg());
1001 int32_t OffImm = (int32_t)MO2.getImm();
1002 bool isSub = OffImm < 0;
1003 // Special value for #-0. All others are normal.
1004 if (OffImm == INT32_MIN)
1012 else if (OffImm > 0) {
1018 O << "]" << markup(">");
1021 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1024 const MCOperand &MO1 = MI->getOperand(OpNum);
1025 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1027 O << markup("<mem:") << "[";
1028 printRegName(O, MO1.getReg());
1030 int32_t OffImm = (int32_t)MO2.getImm();
1034 if (OffImm != 0 && UseMarkup)
1036 if (OffImm == INT32_MIN)
1038 else if (OffImm < 0)
1039 O << "#-" << -OffImm;
1040 else if (OffImm > 0)
1042 if (OffImm != 0 && UseMarkup)
1044 O << "]" << markup(">");
1047 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1050 const MCOperand &MO1 = MI->getOperand(OpNum);
1051 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1053 if (!MO1.isReg()) { // For label symbolic references.
1054 printOperand(MI, OpNum, O);
1058 O << markup("<mem:") << "[";
1059 printRegName(O, MO1.getReg());
1061 int32_t OffImm = (int32_t)MO2.getImm();
1063 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1068 if (OffImm != 0 && UseMarkup)
1070 if (OffImm == INT32_MIN)
1072 else if (OffImm < 0)
1073 O << "#-" << -OffImm;
1074 else if (OffImm > 0)
1076 if (OffImm != 0 && UseMarkup)
1078 O << "]" << markup(">");
1081 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
1084 const MCOperand &MO1 = MI->getOperand(OpNum);
1085 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1087 O << markup("<mem:") << "[";
1088 printRegName(O, MO1.getReg());
1092 << "#" << MO2.getImm() * 4
1095 O << "]" << markup(">");
1098 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1101 const MCOperand &MO1 = MI->getOperand(OpNum);
1102 int32_t OffImm = (int32_t)MO1.getImm();
1103 O << ", " << markup("<imm:");
1105 O << "#-" << -OffImm;
1111 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1114 const MCOperand &MO1 = MI->getOperand(OpNum);
1115 int32_t OffImm = (int32_t)MO1.getImm();
1117 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1122 if (OffImm != 0 && UseMarkup)
1124 if (OffImm == INT32_MIN)
1126 else if (OffImm < 0)
1127 O << "#-" << -OffImm;
1128 else if (OffImm > 0)
1130 if (OffImm != 0 && UseMarkup)
1134 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1137 const MCOperand &MO1 = MI->getOperand(OpNum);
1138 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1139 const MCOperand &MO3 = MI->getOperand(OpNum+2);
1141 O << markup("<mem:") << "[";
1142 printRegName(O, MO1.getReg());
1144 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1146 printRegName(O, MO2.getReg());
1148 unsigned ShAmt = MO3.getImm();
1150 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1156 O << "]" << markup(">");
1159 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1161 const MCOperand &MO = MI->getOperand(OpNum);
1162 O << markup("<imm:")
1163 << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1167 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1169 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1171 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1172 O << markup("<imm:")
1178 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1180 unsigned Imm = MI->getOperand(OpNum).getImm();
1181 O << markup("<imm:")
1186 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1188 unsigned Imm = MI->getOperand(OpNum).getImm();
1195 default: assert (0 && "illegal ror immediate!");
1196 case 1: O << "8"; break;
1197 case 2: O << "16"; break;
1198 case 3: O << "24"; break;
1203 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1205 O << markup("<imm:")
1206 << "#" << 16 - MI->getOperand(OpNum).getImm()
1210 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1212 O << markup("<imm:")
1213 << "#" << 32 - MI->getOperand(OpNum).getImm()
1217 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1219 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1222 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1225 printRegName(O, MI->getOperand(OpNum).getReg());
1229 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1231 unsigned Reg = MI->getOperand(OpNum).getReg();
1232 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1233 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1235 printRegName(O, Reg0);
1237 printRegName(O, Reg1);
1241 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1244 unsigned Reg = MI->getOperand(OpNum).getReg();
1245 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1246 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1248 printRegName(O, Reg0);
1250 printRegName(O, Reg1);
1254 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1256 // Normally, it's not safe to use register enum values directly with
1257 // addition to get the next register, but for VFP registers, the
1258 // sort order is guaranteed because they're all of the form D<n>.
1260 printRegName(O, MI->getOperand(OpNum).getReg());
1262 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1264 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1268 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1270 // Normally, it's not safe to use register enum values directly with
1271 // addition to get the next register, but for VFP registers, the
1272 // sort order is guaranteed because they're all of the form D<n>.
1274 printRegName(O, MI->getOperand(OpNum).getReg());
1276 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1278 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1280 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1284 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1288 printRegName(O, MI->getOperand(OpNum).getReg());
1292 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1295 unsigned Reg = MI->getOperand(OpNum).getReg();
1296 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1297 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1299 printRegName(O, Reg0);
1301 printRegName(O, Reg1);
1305 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1308 // Normally, it's not safe to use register enum values directly with
1309 // addition to get the next register, but for VFP registers, the
1310 // sort order is guaranteed because they're all of the form D<n>.
1312 printRegName(O, MI->getOperand(OpNum).getReg());
1314 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1316 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1320 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1323 // Normally, it's not safe to use register enum values directly with
1324 // addition to get the next register, but for VFP registers, the
1325 // sort order is guaranteed because they're all of the form D<n>.
1327 printRegName(O, MI->getOperand(OpNum).getReg());
1329 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1331 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1333 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1337 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1340 unsigned Reg = MI->getOperand(OpNum).getReg();
1341 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1342 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1344 printRegName(O, Reg0);
1346 printRegName(O, Reg1);
1350 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1353 // Normally, it's not safe to use register enum values directly with
1354 // addition to get the next register, but for VFP registers, the
1355 // sort order is guaranteed because they're all of the form D<n>.
1357 printRegName(O, MI->getOperand(OpNum).getReg());
1359 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1361 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1365 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1368 // Normally, it's not safe to use register enum values directly with
1369 // addition to get the next register, but for VFP registers, the
1370 // sort order is guaranteed because they're all of the form D<n>.
1372 printRegName(O, MI->getOperand(OpNum).getReg());
1374 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1376 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1378 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1382 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1385 // Normally, it's not safe to use register enum values directly with
1386 // addition to get the next register, but for VFP registers, the
1387 // sort order is guaranteed because they're all of the form D<n>.
1389 printRegName(O, MI->getOperand(OpNum).getReg());
1391 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1393 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1397 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1400 // Normally, it's not safe to use register enum values directly with
1401 // addition to get the next register, but for VFP registers, the
1402 // sort order is guaranteed because they're all of the form D<n>.
1404 printRegName(O, MI->getOperand(OpNum).getReg());
1406 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1408 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1410 printRegName(O, MI->getOperand(OpNum).getReg() + 6);