1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, but '0' should actually be printed
31 /// 32 as the immediate shouldbe within the range 1-32.
32 static unsigned translateShiftImm(unsigned imm) {
38 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
39 return getInstructionName(Opcode);
42 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
43 OS << getRegisterName(RegNo);
46 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
47 unsigned Opcode = MI->getOpcode();
49 // Check for MOVs and print canonical forms, instead.
50 if (Opcode == ARM::MOVsr) {
51 // FIXME: Thumb variants?
52 const MCOperand &Dst = MI->getOperand(0);
53 const MCOperand &MO1 = MI->getOperand(1);
54 const MCOperand &MO2 = MI->getOperand(2);
55 const MCOperand &MO3 = MI->getOperand(3);
57 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
58 printSBitModifierOperand(MI, 6, O);
59 printPredicateOperand(MI, 4, O);
61 O << '\t' << getRegisterName(Dst.getReg())
62 << ", " << getRegisterName(MO1.getReg());
64 O << ", " << getRegisterName(MO2.getReg());
65 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
69 if (Opcode == ARM::MOVsi) {
70 // FIXME: Thumb variants?
71 const MCOperand &Dst = MI->getOperand(0);
72 const MCOperand &MO1 = MI->getOperand(1);
73 const MCOperand &MO2 = MI->getOperand(2);
75 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
76 printSBitModifierOperand(MI, 5, O);
77 printPredicateOperand(MI, 3, O);
79 O << '\t' << getRegisterName(Dst.getReg())
80 << ", " << getRegisterName(MO1.getReg());
82 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx)
85 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
91 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
92 MI->getOperand(0).getReg() == ARM::SP) {
94 printPredicateOperand(MI, 2, O);
95 if (Opcode == ARM::t2STMDB_UPD)
98 printRegisterList(MI, 4, O);
101 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
102 MI->getOperand(3).getImm() == -4) {
104 printPredicateOperand(MI, 4, O);
105 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
110 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
111 MI->getOperand(0).getReg() == ARM::SP) {
113 printPredicateOperand(MI, 2, O);
114 if (Opcode == ARM::t2LDMIA_UPD)
117 printRegisterList(MI, 4, O);
120 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
121 MI->getOperand(4).getImm() == 4) {
123 printPredicateOperand(MI, 5, O);
124 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
130 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
131 MI->getOperand(0).getReg() == ARM::SP) {
132 O << '\t' << "vpush";
133 printPredicateOperand(MI, 2, O);
135 printRegisterList(MI, 4, O);
140 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
141 MI->getOperand(0).getReg() == ARM::SP) {
143 printPredicateOperand(MI, 2, O);
145 printRegisterList(MI, 4, O);
149 if (Opcode == ARM::tLDMIA) {
150 bool Writeback = true;
151 unsigned BaseReg = MI->getOperand(0).getReg();
152 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
153 if (MI->getOperand(i).getReg() == BaseReg)
159 printPredicateOperand(MI, 1, O);
160 O << '\t' << getRegisterName(BaseReg);
161 if (Writeback) O << "!";
163 printRegisterList(MI, 3, O);
168 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
169 MI->getOperand(1).getReg() == ARM::R8) {
171 printPredicateOperand(MI, 2, O);
175 printInstruction(MI, O);
178 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
180 const MCOperand &Op = MI->getOperand(OpNo);
182 unsigned Reg = Op.getReg();
183 O << getRegisterName(Reg);
184 } else if (Op.isImm()) {
185 O << '#' << Op.getImm();
187 assert(Op.isExpr() && "unknown operand kind in printOperand");
192 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
193 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
195 // REG REG 0,SH_OPC - e.g. R5, ROR R3
196 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
197 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
199 const MCOperand &MO1 = MI->getOperand(OpNum);
200 const MCOperand &MO2 = MI->getOperand(OpNum+1);
201 const MCOperand &MO3 = MI->getOperand(OpNum+2);
203 O << getRegisterName(MO1.getReg());
205 // Print the shift opc.
206 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
207 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
208 if (ShOpc == ARM_AM::rrx)
211 O << ' ' << getRegisterName(MO2.getReg());
212 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
215 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
217 const MCOperand &MO1 = MI->getOperand(OpNum);
218 const MCOperand &MO2 = MI->getOperand(OpNum+1);
220 O << getRegisterName(MO1.getReg());
222 // Print the shift opc.
223 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
224 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
225 if (ShOpc == ARM_AM::rrx)
227 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
231 //===--------------------------------------------------------------------===//
232 // Addressing Mode #2
233 //===--------------------------------------------------------------------===//
235 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
237 const MCOperand &MO1 = MI->getOperand(Op);
238 const MCOperand &MO2 = MI->getOperand(Op+1);
239 const MCOperand &MO3 = MI->getOperand(Op+2);
241 O << "[" << getRegisterName(MO1.getReg());
244 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
246 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
247 << ARM_AM::getAM2Offset(MO3.getImm());
253 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
254 << getRegisterName(MO2.getReg());
256 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
258 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
263 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
265 const MCOperand &MO1 = MI->getOperand(Op);
266 const MCOperand &MO2 = MI->getOperand(Op+1);
267 const MCOperand &MO3 = MI->getOperand(Op+2);
269 O << "[" << getRegisterName(MO1.getReg()) << "], ";
272 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
274 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
279 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
280 << getRegisterName(MO2.getReg());
282 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
284 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
288 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
290 const MCOperand &MO1 = MI->getOperand(Op);
292 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
293 printOperand(MI, Op, O);
297 const MCOperand &MO3 = MI->getOperand(Op+2);
298 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
300 if (IdxMode == ARMII::IndexModePost) {
301 printAM2PostIndexOp(MI, Op, O);
304 printAM2PreOrOffsetIndexOp(MI, Op, O);
307 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
310 const MCOperand &MO1 = MI->getOperand(OpNum);
311 const MCOperand &MO2 = MI->getOperand(OpNum+1);
314 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
316 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
321 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
322 << getRegisterName(MO1.getReg());
324 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
326 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
330 //===--------------------------------------------------------------------===//
331 // Addressing Mode #3
332 //===--------------------------------------------------------------------===//
334 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
336 const MCOperand &MO1 = MI->getOperand(Op);
337 const MCOperand &MO2 = MI->getOperand(Op+1);
338 const MCOperand &MO3 = MI->getOperand(Op+2);
340 O << "[" << getRegisterName(MO1.getReg()) << "], ";
343 O << (char)ARM_AM::getAM3Op(MO3.getImm())
344 << getRegisterName(MO2.getReg());
348 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
350 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
354 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
356 const MCOperand &MO1 = MI->getOperand(Op);
357 const MCOperand &MO2 = MI->getOperand(Op+1);
358 const MCOperand &MO3 = MI->getOperand(Op+2);
360 O << '[' << getRegisterName(MO1.getReg());
363 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
364 << getRegisterName(MO2.getReg()) << ']';
368 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
370 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
375 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
377 const MCOperand &MO3 = MI->getOperand(Op+2);
378 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
380 if (IdxMode == ARMII::IndexModePost) {
381 printAM3PostIndexOp(MI, Op, O);
384 printAM3PreOrOffsetIndexOp(MI, Op, O);
387 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
390 const MCOperand &MO1 = MI->getOperand(OpNum);
391 const MCOperand &MO2 = MI->getOperand(OpNum+1);
394 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
395 << getRegisterName(MO1.getReg());
399 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
401 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
405 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
408 const MCOperand &MO = MI->getOperand(OpNum);
409 unsigned Imm = MO.getImm();
410 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
413 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
415 const MCOperand &MO1 = MI->getOperand(OpNum);
416 const MCOperand &MO2 = MI->getOperand(OpNum+1);
418 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
421 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
424 const MCOperand &MO = MI->getOperand(OpNum);
425 unsigned Imm = MO.getImm();
426 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
430 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
432 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
434 O << ARM_AM::getAMSubModeStr(Mode);
437 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
439 const MCOperand &MO1 = MI->getOperand(OpNum);
440 const MCOperand &MO2 = MI->getOperand(OpNum+1);
442 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
443 printOperand(MI, OpNum, O);
447 O << "[" << getRegisterName(MO1.getReg());
449 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
451 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
457 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
459 const MCOperand &MO1 = MI->getOperand(OpNum);
460 const MCOperand &MO2 = MI->getOperand(OpNum+1);
462 O << "[" << getRegisterName(MO1.getReg());
464 // FIXME: Both darwin as and GNU as violate ARM docs here.
465 O << ", :" << (MO2.getImm() << 3);
470 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
472 const MCOperand &MO1 = MI->getOperand(OpNum);
473 O << "[" << getRegisterName(MO1.getReg()) << "]";
476 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
479 const MCOperand &MO = MI->getOperand(OpNum);
480 if (MO.getReg() == 0)
483 O << ", " << getRegisterName(MO.getReg());
486 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
489 const MCOperand &MO = MI->getOperand(OpNum);
490 uint32_t v = ~MO.getImm();
491 int32_t lsb = CountTrailingZeros_32(v);
492 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
493 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
494 O << '#' << lsb << ", #" << width;
497 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
499 unsigned val = MI->getOperand(OpNum).getImm();
500 O << ARM_MB::MemBOptToString(val);
503 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
505 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
506 bool isASR = (ShiftOp & (1 << 5)) != 0;
507 unsigned Amt = ShiftOp & 0x1f;
509 O << ", asr #" << (Amt == 0 ? 32 : Amt);
511 O << ", lsl #" << Amt;
514 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
516 unsigned Imm = MI->getOperand(OpNum).getImm();
519 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
520 O << ", lsl #" << Imm;
523 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
525 unsigned Imm = MI->getOperand(OpNum).getImm();
526 // A shift amount of 32 is encoded as 0.
529 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
530 O << ", asr #" << Imm;
533 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
536 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
537 if (i != OpNum) O << ", ";
538 O << getRegisterName(MI->getOperand(i).getReg());
543 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
545 const MCOperand &Op = MI->getOperand(OpNum);
552 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
554 const MCOperand &Op = MI->getOperand(OpNum);
555 O << ARM_PROC::IModToString(Op.getImm());
558 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
560 const MCOperand &Op = MI->getOperand(OpNum);
561 unsigned IFlags = Op.getImm();
562 for (int i=2; i >= 0; --i)
563 if (IFlags & (1 << i))
564 O << ARM_PROC::IFlagsToString(1 << i);
567 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
569 const MCOperand &Op = MI->getOperand(OpNum);
570 unsigned SpecRegRBit = Op.getImm() >> 4;
571 unsigned Mask = Op.getImm() & 0xf;
573 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
574 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
575 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
579 case 4: O << "g"; return;
580 case 8: O << "nzcvq"; return;
581 case 12: O << "nzcvqg"; return;
583 llvm_unreachable("Unexpected mask value!");
593 if (Mask & 8) O << 'f';
594 if (Mask & 4) O << 's';
595 if (Mask & 2) O << 'x';
596 if (Mask & 1) O << 'c';
600 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
602 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
604 O << ARMCondCodeToString(CC);
607 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
610 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
611 O << ARMCondCodeToString(CC);
614 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
616 if (MI->getOperand(OpNum).getReg()) {
617 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
618 "Expect ARM CPSR register!");
623 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
625 O << MI->getOperand(OpNum).getImm();
628 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
630 O << "p" << MI->getOperand(OpNum).getImm();
633 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
635 O << "c" << MI->getOperand(OpNum).getImm();
638 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
640 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
643 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
645 O << "#" << MI->getOperand(OpNum).getImm() * 4;
648 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
650 unsigned Imm = MI->getOperand(OpNum).getImm();
651 O << "#" << (Imm == 0 ? 32 : Imm);
654 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
656 // (3 - the number of trailing zeros) is the number of then / else.
657 unsigned Mask = MI->getOperand(OpNum).getImm();
658 unsigned CondBit0 = Mask >> 4 & 1;
659 unsigned NumTZ = CountTrailingZeros_32(Mask);
660 assert(NumTZ <= 3 && "Invalid IT mask!");
661 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
662 bool T = ((Mask >> Pos) & 1) == CondBit0;
670 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
672 const MCOperand &MO1 = MI->getOperand(Op);
673 const MCOperand &MO2 = MI->getOperand(Op + 1);
675 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
676 printOperand(MI, Op, O);
680 O << "[" << getRegisterName(MO1.getReg());
681 if (unsigned RegNum = MO2.getReg())
682 O << ", " << getRegisterName(RegNum);
686 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
690 const MCOperand &MO1 = MI->getOperand(Op);
691 const MCOperand &MO2 = MI->getOperand(Op + 1);
693 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
694 printOperand(MI, Op, O);
698 O << "[" << getRegisterName(MO1.getReg());
699 if (unsigned ImmOffs = MO2.getImm())
700 O << ", #" << ImmOffs * Scale;
704 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
707 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
710 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
713 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
716 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
719 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
722 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
724 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
727 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
728 // register with shift forms.
730 // REG IMM, SH_OPC - e.g. R5, LSL #3
731 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
733 const MCOperand &MO1 = MI->getOperand(OpNum);
734 const MCOperand &MO2 = MI->getOperand(OpNum+1);
736 unsigned Reg = MO1.getReg();
737 O << getRegisterName(Reg);
739 // Print the shift opc.
740 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
741 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
742 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
743 if (ShOpc != ARM_AM::rrx)
744 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
747 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
749 const MCOperand &MO1 = MI->getOperand(OpNum);
750 const MCOperand &MO2 = MI->getOperand(OpNum+1);
752 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
753 printOperand(MI, OpNum, O);
757 O << "[" << getRegisterName(MO1.getReg());
759 int32_t OffImm = (int32_t)MO2.getImm();
760 bool isSub = OffImm < 0;
761 // Special value for #-0. All others are normal.
762 if (OffImm == INT32_MIN)
765 O << ", #-" << -OffImm;
767 O << ", #" << OffImm;
771 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
774 const MCOperand &MO1 = MI->getOperand(OpNum);
775 const MCOperand &MO2 = MI->getOperand(OpNum+1);
777 O << "[" << getRegisterName(MO1.getReg());
779 int32_t OffImm = (int32_t)MO2.getImm();
782 O << ", #-" << -OffImm;
784 O << ", #" << OffImm;
788 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
791 const MCOperand &MO1 = MI->getOperand(OpNum);
792 const MCOperand &MO2 = MI->getOperand(OpNum+1);
794 O << "[" << getRegisterName(MO1.getReg());
796 int32_t OffImm = (int32_t)MO2.getImm() / 4;
799 O << ", #-" << -OffImm * 4;
801 O << ", #" << OffImm * 4;
805 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
808 const MCOperand &MO1 = MI->getOperand(OpNum);
809 int32_t OffImm = (int32_t)MO1.getImm();
812 O << "#-" << -OffImm;
817 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
820 const MCOperand &MO1 = MI->getOperand(OpNum);
821 int32_t OffImm = (int32_t)MO1.getImm() / 4;
824 O << "#-" << -OffImm * 4;
826 O << "#" << OffImm * 4;
829 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
832 const MCOperand &MO1 = MI->getOperand(OpNum);
833 const MCOperand &MO2 = MI->getOperand(OpNum+1);
834 const MCOperand &MO3 = MI->getOperand(OpNum+2);
836 O << "[" << getRegisterName(MO1.getReg());
838 assert(MO2.getReg() && "Invalid so_reg load / store address!");
839 O << ", " << getRegisterName(MO2.getReg());
841 unsigned ShAmt = MO3.getImm();
843 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
844 O << ", lsl #" << ShAmt;
849 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
851 const MCOperand &MO = MI->getOperand(OpNum);
854 O << (float)MO.getFPImm();
861 FPUnion.I = MO.getImm();
866 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
868 const MCOperand &MO = MI->getOperand(OpNum);
873 // We expect the binary encoding of a floating point number here.
879 FPUnion.I = MO.getImm();
884 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
886 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
888 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
889 O << "#0x" << utohexstr(Val);
892 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
894 unsigned Imm = MI->getOperand(OpNum).getImm();
898 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
900 unsigned Imm = MI->getOperand(OpNum).getImm();
905 default: assert (0 && "illegal ror immediate!");
906 case 1: O << "8"; break;
907 case 2: O << "16"; break;
908 case 3: O << "24"; break;