1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31 static unsigned translateShiftImm(unsigned imm) {
38 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
39 const MCRegisterInfo &MRI,
40 const MCSubtargetInfo &STI) :
41 MCInstPrinter(MAI, MRI) {
42 // Initialize the set of available features.
43 setAvailableFeatures(STI.getFeatureBits());
46 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
47 return getInstructionName(Opcode);
50 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51 OS << getRegisterName(RegNo);
54 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
56 unsigned Opcode = MI->getOpcode();
58 // Check for MOVs and print canonical forms, instead.
59 if (Opcode == ARM::MOVsr) {
60 // FIXME: Thumb variants?
61 const MCOperand &Dst = MI->getOperand(0);
62 const MCOperand &MO1 = MI->getOperand(1);
63 const MCOperand &MO2 = MI->getOperand(2);
64 const MCOperand &MO3 = MI->getOperand(3);
66 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
67 printSBitModifierOperand(MI, 6, O);
68 printPredicateOperand(MI, 4, O);
70 O << '\t' << getRegisterName(Dst.getReg())
71 << ", " << getRegisterName(MO1.getReg());
73 O << ", " << getRegisterName(MO2.getReg());
74 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
75 printAnnotation(O, Annot);
79 if (Opcode == ARM::MOVsi) {
80 // FIXME: Thumb variants?
81 const MCOperand &Dst = MI->getOperand(0);
82 const MCOperand &MO1 = MI->getOperand(1);
83 const MCOperand &MO2 = MI->getOperand(2);
85 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
86 printSBitModifierOperand(MI, 5, O);
87 printPredicateOperand(MI, 3, O);
89 O << '\t' << getRegisterName(Dst.getReg())
90 << ", " << getRegisterName(MO1.getReg());
92 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
93 printAnnotation(O, Annot);
97 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
98 printAnnotation(O, Annot);
104 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
105 MI->getOperand(0).getReg() == ARM::SP &&
106 MI->getNumOperands() > 5) {
107 // Should only print PUSH if there are at least two registers in the list.
109 printPredicateOperand(MI, 2, O);
110 if (Opcode == ARM::t2STMDB_UPD)
113 printRegisterList(MI, 4, O);
114 printAnnotation(O, Annot);
117 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
118 MI->getOperand(3).getImm() == -4) {
120 printPredicateOperand(MI, 4, O);
121 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
122 printAnnotation(O, Annot);
127 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
128 MI->getOperand(0).getReg() == ARM::SP &&
129 MI->getNumOperands() > 5) {
130 // Should only print POP if there are at least two registers in the list.
132 printPredicateOperand(MI, 2, O);
133 if (Opcode == ARM::t2LDMIA_UPD)
136 printRegisterList(MI, 4, O);
137 printAnnotation(O, Annot);
140 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
141 MI->getOperand(4).getImm() == 4) {
143 printPredicateOperand(MI, 5, O);
144 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
145 printAnnotation(O, Annot);
151 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
152 MI->getOperand(0).getReg() == ARM::SP) {
153 O << '\t' << "vpush";
154 printPredicateOperand(MI, 2, O);
156 printRegisterList(MI, 4, O);
157 printAnnotation(O, Annot);
162 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
163 MI->getOperand(0).getReg() == ARM::SP) {
165 printPredicateOperand(MI, 2, O);
167 printRegisterList(MI, 4, O);
168 printAnnotation(O, Annot);
172 if (Opcode == ARM::tLDMIA) {
173 bool Writeback = true;
174 unsigned BaseReg = MI->getOperand(0).getReg();
175 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
176 if (MI->getOperand(i).getReg() == BaseReg)
182 printPredicateOperand(MI, 1, O);
183 O << '\t' << getRegisterName(BaseReg);
184 if (Writeback) O << "!";
186 printRegisterList(MI, 3, O);
187 printAnnotation(O, Annot);
192 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
193 MI->getOperand(1).getReg() == ARM::R8) {
195 printPredicateOperand(MI, 2, O);
196 printAnnotation(O, Annot);
200 printInstruction(MI, O);
201 printAnnotation(O, Annot);
204 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
206 const MCOperand &Op = MI->getOperand(OpNo);
208 unsigned Reg = Op.getReg();
209 O << getRegisterName(Reg);
210 } else if (Op.isImm()) {
211 O << '#' << Op.getImm();
213 assert(Op.isExpr() && "unknown operand kind in printOperand");
214 // If a symbolic branch target was added as a constant expression then print
215 // that address in hex.
216 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
218 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
220 O.write_hex(Address);
223 // Otherwise, just print the expression.
229 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
231 const MCOperand &MO1 = MI->getOperand(OpNum);
234 else if (MO1.isImm())
235 O << "[pc, #" << MO1.getImm() << "]";
237 llvm_unreachable("Unknown LDR label operand?");
240 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
241 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
243 // REG REG 0,SH_OPC - e.g. R5, ROR R3
244 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
245 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
247 const MCOperand &MO1 = MI->getOperand(OpNum);
248 const MCOperand &MO2 = MI->getOperand(OpNum+1);
249 const MCOperand &MO3 = MI->getOperand(OpNum+2);
251 O << getRegisterName(MO1.getReg());
253 // Print the shift opc.
254 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
255 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
256 if (ShOpc == ARM_AM::rrx)
259 O << ' ' << getRegisterName(MO2.getReg());
260 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
263 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
265 const MCOperand &MO1 = MI->getOperand(OpNum);
266 const MCOperand &MO2 = MI->getOperand(OpNum+1);
268 O << getRegisterName(MO1.getReg());
270 // Print the shift opc.
271 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
272 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
273 if (ShOpc == ARM_AM::rrx)
275 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
279 //===--------------------------------------------------------------------===//
280 // Addressing Mode #2
281 //===--------------------------------------------------------------------===//
283 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
285 const MCOperand &MO1 = MI->getOperand(Op);
286 const MCOperand &MO2 = MI->getOperand(Op+1);
287 const MCOperand &MO3 = MI->getOperand(Op+2);
289 O << "[" << getRegisterName(MO1.getReg());
292 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
294 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
295 << ARM_AM::getAM2Offset(MO3.getImm());
301 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
302 << getRegisterName(MO2.getReg());
304 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
306 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
311 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
313 const MCOperand &MO1 = MI->getOperand(Op);
314 const MCOperand &MO2 = MI->getOperand(Op+1);
315 const MCOperand &MO3 = MI->getOperand(Op+2);
317 O << "[" << getRegisterName(MO1.getReg()) << "], ";
320 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
322 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
327 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
328 << getRegisterName(MO2.getReg());
330 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
332 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
336 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
338 const MCOperand &MO1 = MI->getOperand(Op);
339 const MCOperand &MO2 = MI->getOperand(Op+1);
340 O << "[" << getRegisterName(MO1.getReg()) << ", "
341 << getRegisterName(MO2.getReg()) << "]";
344 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
346 const MCOperand &MO1 = MI->getOperand(Op);
347 const MCOperand &MO2 = MI->getOperand(Op+1);
348 O << "[" << getRegisterName(MO1.getReg()) << ", "
349 << getRegisterName(MO2.getReg()) << ", lsl #1]";
352 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
354 const MCOperand &MO1 = MI->getOperand(Op);
356 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
357 printOperand(MI, Op, O);
361 const MCOperand &MO3 = MI->getOperand(Op+2);
362 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
364 if (IdxMode == ARMII::IndexModePost) {
365 printAM2PostIndexOp(MI, Op, O);
368 printAM2PreOrOffsetIndexOp(MI, Op, O);
371 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
374 const MCOperand &MO1 = MI->getOperand(OpNum);
375 const MCOperand &MO2 = MI->getOperand(OpNum+1);
378 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
380 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
385 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
386 << getRegisterName(MO1.getReg());
388 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
390 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
394 //===--------------------------------------------------------------------===//
395 // Addressing Mode #3
396 //===--------------------------------------------------------------------===//
398 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
400 const MCOperand &MO1 = MI->getOperand(Op);
401 const MCOperand &MO2 = MI->getOperand(Op+1);
402 const MCOperand &MO3 = MI->getOperand(Op+2);
404 O << "[" << getRegisterName(MO1.getReg()) << "], ";
407 O << (char)ARM_AM::getAM3Op(MO3.getImm())
408 << getRegisterName(MO2.getReg());
412 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
414 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
418 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
420 const MCOperand &MO1 = MI->getOperand(Op);
421 const MCOperand &MO2 = MI->getOperand(Op+1);
422 const MCOperand &MO3 = MI->getOperand(Op+2);
424 O << '[' << getRegisterName(MO1.getReg());
427 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
428 << getRegisterName(MO2.getReg()) << ']';
432 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
434 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
439 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
441 const MCOperand &MO1 = MI->getOperand(Op);
442 if (!MO1.isReg()) { // For label symbolic references.
443 printOperand(MI, Op, O);
447 const MCOperand &MO3 = MI->getOperand(Op+2);
448 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
450 if (IdxMode == ARMII::IndexModePost) {
451 printAM3PostIndexOp(MI, Op, O);
454 printAM3PreOrOffsetIndexOp(MI, Op, O);
457 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
460 const MCOperand &MO1 = MI->getOperand(OpNum);
461 const MCOperand &MO2 = MI->getOperand(OpNum+1);
464 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
465 << getRegisterName(MO1.getReg());
469 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
471 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
475 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
478 const MCOperand &MO = MI->getOperand(OpNum);
479 unsigned Imm = MO.getImm();
480 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
483 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
485 const MCOperand &MO1 = MI->getOperand(OpNum);
486 const MCOperand &MO2 = MI->getOperand(OpNum+1);
488 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
491 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
494 const MCOperand &MO = MI->getOperand(OpNum);
495 unsigned Imm = MO.getImm();
496 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
500 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
502 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
504 O << ARM_AM::getAMSubModeStr(Mode);
507 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
509 const MCOperand &MO1 = MI->getOperand(OpNum);
510 const MCOperand &MO2 = MI->getOperand(OpNum+1);
512 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
513 printOperand(MI, OpNum, O);
517 O << "[" << getRegisterName(MO1.getReg());
519 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
520 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
521 if (ImmOffs || Op == ARM_AM::sub) {
523 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
529 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
531 const MCOperand &MO1 = MI->getOperand(OpNum);
532 const MCOperand &MO2 = MI->getOperand(OpNum+1);
534 O << "[" << getRegisterName(MO1.getReg());
536 // FIXME: Both darwin as and GNU as violate ARM docs here.
537 O << ", :" << (MO2.getImm() << 3);
542 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
544 const MCOperand &MO1 = MI->getOperand(OpNum);
545 O << "[" << getRegisterName(MO1.getReg()) << "]";
548 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
551 const MCOperand &MO = MI->getOperand(OpNum);
552 if (MO.getReg() == 0)
555 O << ", " << getRegisterName(MO.getReg());
558 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
561 const MCOperand &MO = MI->getOperand(OpNum);
562 uint32_t v = ~MO.getImm();
563 int32_t lsb = CountTrailingZeros_32(v);
564 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
565 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
566 O << '#' << lsb << ", #" << width;
569 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
571 unsigned val = MI->getOperand(OpNum).getImm();
572 O << ARM_MB::MemBOptToString(val);
575 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
577 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
578 bool isASR = (ShiftOp & (1 << 5)) != 0;
579 unsigned Amt = ShiftOp & 0x1f;
581 O << ", asr #" << (Amt == 0 ? 32 : Amt);
583 O << ", lsl #" << Amt;
586 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
588 unsigned Imm = MI->getOperand(OpNum).getImm();
591 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
592 O << ", lsl #" << Imm;
595 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
597 unsigned Imm = MI->getOperand(OpNum).getImm();
598 // A shift amount of 32 is encoded as 0.
601 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
602 O << ", asr #" << Imm;
605 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
608 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
609 if (i != OpNum) O << ", ";
610 O << getRegisterName(MI->getOperand(i).getReg());
615 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
617 const MCOperand &Op = MI->getOperand(OpNum);
624 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
626 const MCOperand &Op = MI->getOperand(OpNum);
627 O << ARM_PROC::IModToString(Op.getImm());
630 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
632 const MCOperand &Op = MI->getOperand(OpNum);
633 unsigned IFlags = Op.getImm();
634 for (int i=2; i >= 0; --i)
635 if (IFlags & (1 << i))
636 O << ARM_PROC::IFlagsToString(1 << i);
642 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
644 const MCOperand &Op = MI->getOperand(OpNum);
645 unsigned SpecRegRBit = Op.getImm() >> 4;
646 unsigned Mask = Op.getImm() & 0xf;
648 if (getAvailableFeatures() & ARM::FeatureMClass) {
649 switch (Op.getImm()) {
650 default: llvm_unreachable("Unexpected mask value!");
651 case 0: O << "apsr"; return;
652 case 1: O << "iapsr"; return;
653 case 2: O << "eapsr"; return;
654 case 3: O << "xpsr"; return;
655 case 5: O << "ipsr"; return;
656 case 6: O << "epsr"; return;
657 case 7: O << "iepsr"; return;
658 case 8: O << "msp"; return;
659 case 9: O << "psp"; return;
660 case 16: O << "primask"; return;
661 case 17: O << "basepri"; return;
662 case 18: O << "basepri_max"; return;
663 case 19: O << "faultmask"; return;
664 case 20: O << "control"; return;
668 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
669 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
670 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
673 default: llvm_unreachable("Unexpected mask value!");
674 case 4: O << "g"; return;
675 case 8: O << "nzcvq"; return;
676 case 12: O << "nzcvqg"; return;
687 if (Mask & 8) O << 'f';
688 if (Mask & 4) O << 's';
689 if (Mask & 2) O << 'x';
690 if (Mask & 1) O << 'c';
694 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
696 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
697 // Handle the undefined 15 CC value here for printing so we don't abort().
698 if ((unsigned)CC == 15)
700 else if (CC != ARMCC::AL)
701 O << ARMCondCodeToString(CC);
704 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
707 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
708 O << ARMCondCodeToString(CC);
711 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
713 if (MI->getOperand(OpNum).getReg()) {
714 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
715 "Expect ARM CPSR register!");
720 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
722 O << MI->getOperand(OpNum).getImm();
725 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
727 O << "p" << MI->getOperand(OpNum).getImm();
730 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
732 O << "c" << MI->getOperand(OpNum).getImm();
735 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
737 O << "{" << MI->getOperand(OpNum).getImm() << "}";
740 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
742 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
745 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
747 O << "#" << MI->getOperand(OpNum).getImm() * 4;
750 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
752 unsigned Imm = MI->getOperand(OpNum).getImm();
753 O << "#" << (Imm == 0 ? 32 : Imm);
756 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
758 // (3 - the number of trailing zeros) is the number of then / else.
759 unsigned Mask = MI->getOperand(OpNum).getImm();
760 unsigned CondBit0 = Mask >> 4 & 1;
761 unsigned NumTZ = CountTrailingZeros_32(Mask);
762 assert(NumTZ <= 3 && "Invalid IT mask!");
763 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
764 bool T = ((Mask >> Pos) & 1) == CondBit0;
772 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
774 const MCOperand &MO1 = MI->getOperand(Op);
775 const MCOperand &MO2 = MI->getOperand(Op + 1);
777 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
778 printOperand(MI, Op, O);
782 O << "[" << getRegisterName(MO1.getReg());
783 if (unsigned RegNum = MO2.getReg())
784 O << ", " << getRegisterName(RegNum);
788 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
792 const MCOperand &MO1 = MI->getOperand(Op);
793 const MCOperand &MO2 = MI->getOperand(Op + 1);
795 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
796 printOperand(MI, Op, O);
800 O << "[" << getRegisterName(MO1.getReg());
801 if (unsigned ImmOffs = MO2.getImm())
802 O << ", #" << ImmOffs * Scale;
806 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
809 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
812 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
815 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
818 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
821 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
824 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
826 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
829 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
830 // register with shift forms.
832 // REG IMM, SH_OPC - e.g. R5, LSL #3
833 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
835 const MCOperand &MO1 = MI->getOperand(OpNum);
836 const MCOperand &MO2 = MI->getOperand(OpNum+1);
838 unsigned Reg = MO1.getReg();
839 O << getRegisterName(Reg);
841 // Print the shift opc.
842 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
843 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
844 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
845 if (ShOpc != ARM_AM::rrx)
846 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
849 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
851 const MCOperand &MO1 = MI->getOperand(OpNum);
852 const MCOperand &MO2 = MI->getOperand(OpNum+1);
854 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
855 printOperand(MI, OpNum, O);
859 O << "[" << getRegisterName(MO1.getReg());
861 int32_t OffImm = (int32_t)MO2.getImm();
862 bool isSub = OffImm < 0;
863 // Special value for #-0. All others are normal.
864 if (OffImm == INT32_MIN)
867 O << ", #-" << -OffImm;
869 O << ", #" << OffImm;
873 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
876 const MCOperand &MO1 = MI->getOperand(OpNum);
877 const MCOperand &MO2 = MI->getOperand(OpNum+1);
879 O << "[" << getRegisterName(MO1.getReg());
881 int32_t OffImm = (int32_t)MO2.getImm();
883 if (OffImm == INT32_MIN)
886 O << ", #-" << -OffImm;
888 O << ", #" << OffImm;
892 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
895 const MCOperand &MO1 = MI->getOperand(OpNum);
896 const MCOperand &MO2 = MI->getOperand(OpNum+1);
898 if (!MO1.isReg()) { // For label symbolic references.
899 printOperand(MI, OpNum, O);
903 O << "[" << getRegisterName(MO1.getReg());
905 int32_t OffImm = (int32_t)MO2.getImm() / 4;
908 O << ", #-" << -OffImm * 4;
910 O << ", #" << OffImm * 4;
914 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
917 const MCOperand &MO1 = MI->getOperand(OpNum);
918 const MCOperand &MO2 = MI->getOperand(OpNum+1);
920 O << "[" << getRegisterName(MO1.getReg());
922 O << ", #" << MO2.getImm() * 4;
926 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
929 const MCOperand &MO1 = MI->getOperand(OpNum);
930 int32_t OffImm = (int32_t)MO1.getImm();
933 O << ", #-" << -OffImm;
935 O << ", #" << OffImm;
938 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
941 const MCOperand &MO1 = MI->getOperand(OpNum);
942 int32_t OffImm = (int32_t)MO1.getImm() / 4;
947 O << "#-" << -OffImm * 4;
949 O << "#" << OffImm * 4;
953 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
956 const MCOperand &MO1 = MI->getOperand(OpNum);
957 const MCOperand &MO2 = MI->getOperand(OpNum+1);
958 const MCOperand &MO3 = MI->getOperand(OpNum+2);
960 O << "[" << getRegisterName(MO1.getReg());
962 assert(MO2.getReg() && "Invalid so_reg load / store address!");
963 O << ", " << getRegisterName(MO2.getReg());
965 unsigned ShAmt = MO3.getImm();
967 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
968 O << ", lsl #" << ShAmt;
973 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
975 const MCOperand &MO = MI->getOperand(OpNum);
976 O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
979 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
981 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
983 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
988 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
990 unsigned Imm = MI->getOperand(OpNum).getImm();
994 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
996 unsigned Imm = MI->getOperand(OpNum).getImm();
1001 default: assert (0 && "illegal ror immediate!");
1002 case 1: O << "8"; break;
1003 case 2: O << "16"; break;
1004 case 3: O << "24"; break;
1008 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1010 O << "#" << 16 - MI->getOperand(OpNum).getImm();
1013 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1015 O << "#" << 32 - MI->getOperand(OpNum).getImm();
1018 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1020 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1023 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1025 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "}";
1028 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1030 unsigned Reg = MI->getOperand(OpNum).getReg();
1031 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1032 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1033 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1036 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1039 unsigned Reg = MI->getOperand(OpNum).getReg();
1040 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1041 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1042 O << "{" << getRegisterName(Reg0) << ", " << getRegisterName(Reg1) << "}";
1045 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1047 // Normally, it's not safe to use register enum values directly with
1048 // addition to get the next register, but for VFP registers, the
1049 // sort order is guaranteed because they're all of the form D<n>.
1050 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1051 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1052 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "}";
1055 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1057 // Normally, it's not safe to use register enum values directly with
1058 // addition to get the next register, but for VFP registers, the
1059 // sort order is guaranteed because they're all of the form D<n>.
1060 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1061 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << ", "
1062 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1063 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "}";
1066 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1069 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[]}";
1072 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1075 unsigned Reg = MI->getOperand(OpNum).getReg();
1076 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1077 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1078 O << "{" << getRegisterName(Reg0) << "[], " << getRegisterName(Reg1) << "[]}";
1081 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1084 // Normally, it's not safe to use register enum values directly with
1085 // addition to get the next register, but for VFP registers, the
1086 // sort order is guaranteed because they're all of the form D<n>.
1087 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1088 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1089 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
1092 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1095 // Normally, it's not safe to use register enum values directly with
1096 // addition to get the next register, but for VFP registers, the
1097 // sort order is guaranteed because they're all of the form D<n>.
1098 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1099 << getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
1100 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1101 << getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}";
1104 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1107 // Normally, it's not safe to use register enum values directly with
1108 // addition to get the next register, but for VFP registers, the
1109 // sort order is guaranteed because they're all of the form D<n>.
1110 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1111 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
1114 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1117 // Normally, it's not safe to use register enum values directly with
1118 // addition to get the next register, but for VFP registers, the
1119 // sort order is guaranteed because they're all of the form D<n>.
1120 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1121 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1122 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}";
1125 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1128 // Normally, it's not safe to use register enum values directly with
1129 // addition to get the next register, but for VFP registers, the
1130 // sort order is guaranteed because they're all of the form D<n>.
1131 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
1132 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
1133 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], "
1134 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}";
1137 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1140 // Normally, it's not safe to use register enum values directly with
1141 // addition to get the next register, but for VFP registers, the
1142 // sort order is guaranteed because they're all of the form D<n>.
1143 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1144 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1145 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "}";
1148 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1151 // Normally, it's not safe to use register enum values directly with
1152 // addition to get the next register, but for VFP registers, the
1153 // sort order is guaranteed because they're all of the form D<n>.
1154 O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1155 << getRegisterName(MI->getOperand(OpNum).getReg() + 2) << ", "
1156 << getRegisterName(MI->getOperand(OpNum).getReg() + 4) << ", "
1157 << getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "}";