1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Support/raw_ostream.h"
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, representing '32' as 0.
31 static unsigned translateShiftImm(unsigned imm) {
32 // lsr #32 and asr #32 exist, but should be encoded as a 0.
33 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
40 /// Prints the shift value with an immediate value.
41 static void printRegImmShift(raw_ostream &O, ARM_AM::ShiftOpc ShOpc,
42 unsigned ShImm, bool UseMarkup) {
43 if (ShOpc == ARM_AM::no_shift || (ShOpc == ARM_AM::lsl && !ShImm))
47 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
48 O << getShiftOpcStr(ShOpc);
50 if (ShOpc != ARM_AM::rrx) {
54 O << "#" << translateShiftImm(ShImm);
60 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
61 const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI,
63 const MCSubtargetInfo &STI) :
64 MCInstPrinter(MAI, MII, MRI) {
65 // Initialize the set of available features.
66 setAvailableFeatures(STI.getFeatureBits());
69 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
71 << getRegisterName(RegNo)
75 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
77 unsigned Opcode = MI->getOpcode();
79 // Check for HINT instructions w/ canonical names.
80 if (Opcode == ARM::HINT || Opcode == ARM::t2HINT) {
81 switch (MI->getOperand(0).getImm()) {
82 case 0: O << "\tnop"; break;
83 case 1: O << "\tyield"; break;
84 case 2: O << "\twfe"; break;
85 case 3: O << "\twfi"; break;
86 case 4: O << "\tsev"; break;
88 // Anything else should just print normally.
89 printInstruction(MI, O);
90 printAnnotation(O, Annot);
93 printPredicateOperand(MI, 1, O);
94 if (Opcode == ARM::t2HINT)
96 printAnnotation(O, Annot);
100 // Check for MOVs and print canonical forms, instead.
101 if (Opcode == ARM::MOVsr) {
102 // FIXME: Thumb variants?
103 const MCOperand &Dst = MI->getOperand(0);
104 const MCOperand &MO1 = MI->getOperand(1);
105 const MCOperand &MO2 = MI->getOperand(2);
106 const MCOperand &MO3 = MI->getOperand(3);
108 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
109 printSBitModifierOperand(MI, 6, O);
110 printPredicateOperand(MI, 4, O);
113 printRegName(O, Dst.getReg());
115 printRegName(O, MO1.getReg());
118 printRegName(O, MO2.getReg());
119 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
120 printAnnotation(O, Annot);
124 if (Opcode == ARM::MOVsi) {
125 // FIXME: Thumb variants?
126 const MCOperand &Dst = MI->getOperand(0);
127 const MCOperand &MO1 = MI->getOperand(1);
128 const MCOperand &MO2 = MI->getOperand(2);
130 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
131 printSBitModifierOperand(MI, 5, O);
132 printPredicateOperand(MI, 3, O);
135 printRegName(O, Dst.getReg());
137 printRegName(O, MO1.getReg());
139 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
140 printAnnotation(O, Annot);
146 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
148 printAnnotation(O, Annot);
154 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
155 MI->getOperand(0).getReg() == ARM::SP &&
156 MI->getNumOperands() > 5) {
157 // Should only print PUSH if there are at least two registers in the list.
159 printPredicateOperand(MI, 2, O);
160 if (Opcode == ARM::t2STMDB_UPD)
163 printRegisterList(MI, 4, O);
164 printAnnotation(O, Annot);
167 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
168 MI->getOperand(3).getImm() == -4) {
170 printPredicateOperand(MI, 4, O);
172 printRegName(O, MI->getOperand(1).getReg());
174 printAnnotation(O, Annot);
179 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
180 MI->getOperand(0).getReg() == ARM::SP &&
181 MI->getNumOperands() > 5) {
182 // Should only print POP if there are at least two registers in the list.
184 printPredicateOperand(MI, 2, O);
185 if (Opcode == ARM::t2LDMIA_UPD)
188 printRegisterList(MI, 4, O);
189 printAnnotation(O, Annot);
192 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
193 MI->getOperand(4).getImm() == 4) {
195 printPredicateOperand(MI, 5, O);
197 printRegName(O, MI->getOperand(0).getReg());
199 printAnnotation(O, Annot);
205 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
206 MI->getOperand(0).getReg() == ARM::SP) {
207 O << '\t' << "vpush";
208 printPredicateOperand(MI, 2, O);
210 printRegisterList(MI, 4, O);
211 printAnnotation(O, Annot);
216 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
217 MI->getOperand(0).getReg() == ARM::SP) {
219 printPredicateOperand(MI, 2, O);
221 printRegisterList(MI, 4, O);
222 printAnnotation(O, Annot);
226 if (Opcode == ARM::tLDMIA) {
227 bool Writeback = true;
228 unsigned BaseReg = MI->getOperand(0).getReg();
229 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
230 if (MI->getOperand(i).getReg() == BaseReg)
236 printPredicateOperand(MI, 1, O);
238 printRegName(O, BaseReg);
239 if (Writeback) O << "!";
241 printRegisterList(MI, 3, O);
242 printAnnotation(O, Annot);
246 // Combine 2 GPRs from disassember into a GPRPair to match with instr def.
247 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
248 // a single GPRPair reg operand is used in the .td file to replace the two
249 // GPRs. However, when decoding them, the two GRPs cannot be automatically
250 // expressed as a GPRPair, so we have to manually merge them.
251 // FIXME: We would really like to be able to tablegen'erate this.
252 if (Opcode == ARM::LDREXD || Opcode == ARM::STREXD ||
253 Opcode == ARM::LDAEXD || Opcode == ARM::STLEXD) {
254 const MCRegisterClass& MRC = MRI.getRegClass(ARM::GPRRegClassID);
255 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
256 unsigned Reg = MI->getOperand(isStore ? 1 : 0).getReg();
257 if (MRC.contains(Reg)) {
260 NewMI.setOpcode(Opcode);
263 NewMI.addOperand(MI->getOperand(0));
264 NewReg = MCOperand::CreateReg(MRI.getMatchingSuperReg(Reg, ARM::gsub_0,
265 &MRI.getRegClass(ARM::GPRPairRegClassID)));
266 NewMI.addOperand(NewReg);
268 // Copy the rest operands into NewMI.
269 for(unsigned i= isStore ? 3 : 2; i < MI->getNumOperands(); ++i)
270 NewMI.addOperand(MI->getOperand(i));
271 printInstruction(&NewMI, O);
276 printInstruction(MI, O);
277 printAnnotation(O, Annot);
280 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
282 const MCOperand &Op = MI->getOperand(OpNo);
284 unsigned Reg = Op.getReg();
285 printRegName(O, Reg);
286 } else if (Op.isImm()) {
288 << '#' << formatImm(Op.getImm())
291 assert(Op.isExpr() && "unknown operand kind in printOperand");
292 // If a symbolic branch target was added as a constant expression then print
293 // that address in hex. And only print 32 unsigned bits for the address.
294 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
296 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
298 O.write_hex((uint32_t)Address);
301 // Otherwise, just print the expression.
307 void ARMInstPrinter::printThumbLdrLabelOperand(const MCInst *MI, unsigned OpNum,
309 const MCOperand &MO1 = MI->getOperand(OpNum);
315 O << markup("<mem:") << "[pc, ";
317 int32_t OffImm = (int32_t)MO1.getImm();
318 bool isSub = OffImm < 0;
320 // Special value for #-0. All others are normal.
321 if (OffImm == INT32_MIN)
325 << "#-" << formatImm(-OffImm)
329 << "#" << formatImm(OffImm)
332 O << "]" << markup(">");
335 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
336 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
338 // REG REG 0,SH_OPC - e.g. R5, ROR R3
339 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
340 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
342 const MCOperand &MO1 = MI->getOperand(OpNum);
343 const MCOperand &MO2 = MI->getOperand(OpNum+1);
344 const MCOperand &MO3 = MI->getOperand(OpNum+2);
346 printRegName(O, MO1.getReg());
348 // Print the shift opc.
349 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
350 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
351 if (ShOpc == ARM_AM::rrx)
355 printRegName(O, MO2.getReg());
356 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
359 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
361 const MCOperand &MO1 = MI->getOperand(OpNum);
362 const MCOperand &MO2 = MI->getOperand(OpNum+1);
364 printRegName(O, MO1.getReg());
366 // Print the shift opc.
367 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
368 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
372 //===--------------------------------------------------------------------===//
373 // Addressing Mode #2
374 //===--------------------------------------------------------------------===//
376 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
378 const MCOperand &MO1 = MI->getOperand(Op);
379 const MCOperand &MO2 = MI->getOperand(Op+1);
380 const MCOperand &MO3 = MI->getOperand(Op+2);
382 O << markup("<mem:") << "[";
383 printRegName(O, MO1.getReg());
386 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
390 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
391 << ARM_AM::getAM2Offset(MO3.getImm())
394 O << "]" << markup(">");
399 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
400 printRegName(O, MO2.getReg());
402 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
403 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
404 O << "]" << markup(">");
407 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
409 const MCOperand &MO1 = MI->getOperand(Op);
410 const MCOperand &MO2 = MI->getOperand(Op+1);
411 O << markup("<mem:") << "[";
412 printRegName(O, MO1.getReg());
414 printRegName(O, MO2.getReg());
415 O << "]" << markup(">");
418 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
420 const MCOperand &MO1 = MI->getOperand(Op);
421 const MCOperand &MO2 = MI->getOperand(Op+1);
422 O << markup("<mem:") << "[";
423 printRegName(O, MO1.getReg());
425 printRegName(O, MO2.getReg());
426 O << ", lsl " << markup("<imm:") << "#1" << markup(">") << "]" << markup(">");
429 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
431 const MCOperand &MO1 = MI->getOperand(Op);
433 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
434 printOperand(MI, Op, O);
439 const MCOperand &MO3 = MI->getOperand(Op+2);
440 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
441 assert(IdxMode != ARMII::IndexModePost &&
442 "Should be pre or offset index op");
445 printAM2PreOrOffsetIndexOp(MI, Op, O);
448 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
451 const MCOperand &MO1 = MI->getOperand(OpNum);
452 const MCOperand &MO2 = MI->getOperand(OpNum+1);
455 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
457 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
463 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()));
464 printRegName(O, MO1.getReg());
466 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO2.getImm()),
467 ARM_AM::getAM2Offset(MO2.getImm()), UseMarkup);
470 //===--------------------------------------------------------------------===//
471 // Addressing Mode #3
472 //===--------------------------------------------------------------------===//
474 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
476 const MCOperand &MO1 = MI->getOperand(Op);
477 const MCOperand &MO2 = MI->getOperand(Op+1);
478 const MCOperand &MO3 = MI->getOperand(Op+2);
480 O << markup("<mem:") << "[";
481 printRegName(O, MO1.getReg());
482 O << "], " << markup(">");
485 O << (char)ARM_AM::getAM3Op(MO3.getImm());
486 printRegName(O, MO2.getReg());
490 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
493 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
498 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
500 bool AlwaysPrintImm0) {
501 const MCOperand &MO1 = MI->getOperand(Op);
502 const MCOperand &MO2 = MI->getOperand(Op+1);
503 const MCOperand &MO3 = MI->getOperand(Op+2);
505 O << markup("<mem:") << '[';
506 printRegName(O, MO1.getReg());
509 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
510 printRegName(O, MO2.getReg());
511 O << ']' << markup(">");
515 //If the op is sub we have to print the immediate even if it is 0
516 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
517 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
519 if (AlwaysPrintImm0 || ImmOffs || (op == ARM_AM::sub)) {
523 << ARM_AM::getAddrOpcStr(op)
527 O << ']' << markup(">");
530 template <bool AlwaysPrintImm0>
531 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
533 const MCOperand &MO1 = MI->getOperand(Op);
534 if (!MO1.isReg()) { // For label symbolic references.
535 printOperand(MI, Op, O);
539 const MCOperand &MO3 = MI->getOperand(Op+2);
540 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
542 if (IdxMode == ARMII::IndexModePost) {
543 printAM3PostIndexOp(MI, Op, O);
546 printAM3PreOrOffsetIndexOp(MI, Op, O, AlwaysPrintImm0);
549 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
552 const MCOperand &MO1 = MI->getOperand(OpNum);
553 const MCOperand &MO2 = MI->getOperand(OpNum+1);
556 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()));
557 printRegName(O, MO1.getReg());
561 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
563 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
567 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
570 const MCOperand &MO = MI->getOperand(OpNum);
571 unsigned Imm = MO.getImm();
573 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
577 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
579 const MCOperand &MO1 = MI->getOperand(OpNum);
580 const MCOperand &MO2 = MI->getOperand(OpNum+1);
582 O << (MO2.getImm() ? "" : "-");
583 printRegName(O, MO1.getReg());
586 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
589 const MCOperand &MO = MI->getOperand(OpNum);
590 unsigned Imm = MO.getImm();
592 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
597 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
599 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
601 O << ARM_AM::getAMSubModeStr(Mode);
604 template <bool AlwaysPrintImm0>
605 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
607 const MCOperand &MO1 = MI->getOperand(OpNum);
608 const MCOperand &MO2 = MI->getOperand(OpNum+1);
610 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
611 printOperand(MI, OpNum, O);
615 O << markup("<mem:") << "[";
616 printRegName(O, MO1.getReg());
618 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
619 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
620 if (AlwaysPrintImm0 || ImmOffs || Op == ARM_AM::sub) {
624 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
628 O << "]" << markup(">");
631 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
633 const MCOperand &MO1 = MI->getOperand(OpNum);
634 const MCOperand &MO2 = MI->getOperand(OpNum+1);
636 O << markup("<mem:") << "[";
637 printRegName(O, MO1.getReg());
639 O << ":" << (MO2.getImm() << 3);
641 O << "]" << markup(">");
644 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
646 const MCOperand &MO1 = MI->getOperand(OpNum);
647 O << markup("<mem:") << "[";
648 printRegName(O, MO1.getReg());
649 O << "]" << markup(">");
652 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
655 const MCOperand &MO = MI->getOperand(OpNum);
656 if (MO.getReg() == 0)
660 printRegName(O, MO.getReg());
664 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
667 const MCOperand &MO = MI->getOperand(OpNum);
668 uint32_t v = ~MO.getImm();
669 int32_t lsb = countTrailingZeros(v);
670 int32_t width = (32 - countLeadingZeros (v)) - lsb;
671 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
672 O << markup("<imm:") << '#' << lsb << markup(">")
674 << markup("<imm:") << '#' << width << markup(">");
677 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
679 unsigned val = MI->getOperand(OpNum).getImm();
680 O << ARM_MB::MemBOptToString(val, (getAvailableFeatures() & ARM::HasV8Ops));
683 void ARMInstPrinter::printInstSyncBOption(const MCInst *MI, unsigned OpNum,
685 unsigned val = MI->getOperand(OpNum).getImm();
686 O << ARM_ISB::InstSyncBOptToString(val);
689 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
691 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
692 bool isASR = (ShiftOp & (1 << 5)) != 0;
693 unsigned Amt = ShiftOp & 0x1f;
697 << "#" << (Amt == 0 ? 32 : Amt)
708 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
710 unsigned Imm = MI->getOperand(OpNum).getImm();
713 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
714 O << ", lsl " << markup("<imm:") << "#" << Imm << markup(">");
717 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
719 unsigned Imm = MI->getOperand(OpNum).getImm();
720 // A shift amount of 32 is encoded as 0.
723 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
724 O << ", asr " << markup("<imm:") << "#" << Imm << markup(">");
727 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
730 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
731 if (i != OpNum) O << ", ";
732 printRegName(O, MI->getOperand(i).getReg());
737 void ARMInstPrinter::printGPRPairOperand(const MCInst *MI, unsigned OpNum,
739 unsigned Reg = MI->getOperand(OpNum).getReg();
740 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_0));
742 printRegName(O, MRI.getSubReg(Reg, ARM::gsub_1));
746 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
748 const MCOperand &Op = MI->getOperand(OpNum);
755 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
757 const MCOperand &Op = MI->getOperand(OpNum);
758 O << ARM_PROC::IModToString(Op.getImm());
761 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
763 const MCOperand &Op = MI->getOperand(OpNum);
764 unsigned IFlags = Op.getImm();
765 for (int i=2; i >= 0; --i)
766 if (IFlags & (1 << i))
767 O << ARM_PROC::IFlagsToString(1 << i);
773 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
775 const MCOperand &Op = MI->getOperand(OpNum);
776 unsigned SpecRegRBit = Op.getImm() >> 4;
777 unsigned Mask = Op.getImm() & 0xf;
779 if (getAvailableFeatures() & ARM::FeatureMClass) {
780 unsigned SYSm = Op.getImm();
781 unsigned Opcode = MI->getOpcode();
782 // For reads of the special registers ignore the "mask encoding" bits
783 // which are only for writes.
784 if (Opcode == ARM::t2MRS_M)
787 default: llvm_unreachable("Unexpected mask value!");
789 case 0x800: O << "apsr"; return; // with _nzcvq bits is an alias for aspr
790 case 0x400: O << "apsr_g"; return;
791 case 0xc00: O << "apsr_nzcvqg"; return;
793 case 0x801: O << "iapsr"; return; // with _nzcvq bits is an alias for iapsr
794 case 0x401: O << "iapsr_g"; return;
795 case 0xc01: O << "iapsr_nzcvqg"; return;
797 case 0x802: O << "eapsr"; return; // with _nzcvq bits is an alias for eapsr
798 case 0x402: O << "eapsr_g"; return;
799 case 0xc02: O << "eapsr_nzcvqg"; return;
801 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
802 case 0x403: O << "xpsr_g"; return;
803 case 0xc03: O << "xpsr_nzcvqg"; return;
805 case 0x805: O << "ipsr"; return;
807 case 0x806: O << "epsr"; return;
809 case 0x807: O << "iepsr"; return;
811 case 0x808: O << "msp"; return;
813 case 0x809: O << "psp"; return;
815 case 0x810: O << "primask"; return;
817 case 0x811: O << "basepri"; return;
819 case 0x812: O << "basepri_max"; return;
821 case 0x813: O << "faultmask"; return;
823 case 0x814: O << "control"; return;
827 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
828 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
829 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
832 default: llvm_unreachable("Unexpected mask value!");
833 case 4: O << "g"; return;
834 case 8: O << "nzcvq"; return;
835 case 12: O << "nzcvqg"; return;
846 if (Mask & 8) O << 'f';
847 if (Mask & 4) O << 's';
848 if (Mask & 2) O << 'x';
849 if (Mask & 1) O << 'c';
853 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
855 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
856 // Handle the undefined 15 CC value here for printing so we don't abort().
857 if ((unsigned)CC == 15)
859 else if (CC != ARMCC::AL)
860 O << ARMCondCodeToString(CC);
863 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
866 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
867 O << ARMCondCodeToString(CC);
870 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
872 if (MI->getOperand(OpNum).getReg()) {
873 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
874 "Expect ARM CPSR register!");
879 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
881 O << MI->getOperand(OpNum).getImm();
884 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
886 O << "p" << MI->getOperand(OpNum).getImm();
889 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
891 O << "c" << MI->getOperand(OpNum).getImm();
894 void ARMInstPrinter::printCoprocOptionImm(const MCInst *MI, unsigned OpNum,
896 O << "{" << MI->getOperand(OpNum).getImm() << "}";
899 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
901 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
904 template<unsigned scale>
905 void ARMInstPrinter::printAdrLabelOperand(const MCInst *MI, unsigned OpNum,
907 const MCOperand &MO = MI->getOperand(OpNum);
914 int32_t OffImm = (int32_t)MO.getImm() << scale;
916 O << markup("<imm:");
917 if (OffImm == INT32_MIN)
920 O << "#-" << -OffImm;
926 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
929 << "#" << formatImm(MI->getOperand(OpNum).getImm() * 4)
933 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
935 unsigned Imm = MI->getOperand(OpNum).getImm();
937 << "#" << formatImm((Imm == 0 ? 32 : Imm))
941 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
943 // (3 - the number of trailing zeros) is the number of then / else.
944 unsigned Mask = MI->getOperand(OpNum).getImm();
945 unsigned Firstcond = MI->getOperand(OpNum-1).getImm();
946 unsigned CondBit0 = Firstcond & 1;
947 unsigned NumTZ = countTrailingZeros(Mask);
948 assert(NumTZ <= 3 && "Invalid IT mask!");
949 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
950 bool T = ((Mask >> Pos) & 1) == CondBit0;
958 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
960 const MCOperand &MO1 = MI->getOperand(Op);
961 const MCOperand &MO2 = MI->getOperand(Op + 1);
963 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
964 printOperand(MI, Op, O);
968 O << markup("<mem:") << "[";
969 printRegName(O, MO1.getReg());
970 if (unsigned RegNum = MO2.getReg()) {
972 printRegName(O, RegNum);
974 O << "]" << markup(">");
977 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
981 const MCOperand &MO1 = MI->getOperand(Op);
982 const MCOperand &MO2 = MI->getOperand(Op + 1);
984 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
985 printOperand(MI, Op, O);
989 O << markup("<mem:") << "[";
990 printRegName(O, MO1.getReg());
991 if (unsigned ImmOffs = MO2.getImm()) {
994 << "#" << formatImm(ImmOffs * Scale)
997 O << "]" << markup(">");
1000 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1003 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
1006 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
1009 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
1012 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
1015 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1018 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
1020 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
1023 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1024 // register with shift forms.
1025 // REG 0 0 - e.g. R5
1026 // REG IMM, SH_OPC - e.g. R5, LSL #3
1027 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
1029 const MCOperand &MO1 = MI->getOperand(OpNum);
1030 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1032 unsigned Reg = MO1.getReg();
1033 printRegName(O, Reg);
1035 // Print the shift opc.
1036 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
1037 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm()),
1038 ARM_AM::getSORegOffset(MO2.getImm()), UseMarkup);
1041 template <bool AlwaysPrintImm0>
1042 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
1044 const MCOperand &MO1 = MI->getOperand(OpNum);
1045 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1047 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
1048 printOperand(MI, OpNum, O);
1052 O << markup("<mem:") << "[";
1053 printRegName(O, MO1.getReg());
1055 int32_t OffImm = (int32_t)MO2.getImm();
1056 bool isSub = OffImm < 0;
1057 // Special value for #-0. All others are normal.
1058 if (OffImm == INT32_MIN)
1066 else if (AlwaysPrintImm0 || OffImm > 0) {
1072 O << "]" << markup(">");
1075 template<bool AlwaysPrintImm0>
1076 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
1079 const MCOperand &MO1 = MI->getOperand(OpNum);
1080 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1082 O << markup("<mem:") << "[";
1083 printRegName(O, MO1.getReg());
1085 int32_t OffImm = (int32_t)MO2.getImm();
1086 bool isSub = OffImm < 0;
1088 if (OffImm == INT32_MIN)
1095 } else if (AlwaysPrintImm0 || OffImm > 0) {
1101 O << "]" << markup(">");
1104 template<bool AlwaysPrintImm0>
1105 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
1108 const MCOperand &MO1 = MI->getOperand(OpNum);
1109 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1111 if (!MO1.isReg()) { // For label symbolic references.
1112 printOperand(MI, OpNum, O);
1116 O << markup("<mem:") << "[";
1117 printRegName(O, MO1.getReg());
1119 int32_t OffImm = (int32_t)MO2.getImm();
1120 bool isSub = OffImm < 0;
1122 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1125 if (OffImm == INT32_MIN)
1132 } else if (AlwaysPrintImm0 || OffImm > 0) {
1138 O << "]" << markup(">");
1141 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
1144 const MCOperand &MO1 = MI->getOperand(OpNum);
1145 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1147 O << markup("<mem:") << "[";
1148 printRegName(O, MO1.getReg());
1152 << "#" << formatImm(MO2.getImm() * 4)
1155 O << "]" << markup(">");
1158 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
1161 const MCOperand &MO1 = MI->getOperand(OpNum);
1162 int32_t OffImm = (int32_t)MO1.getImm();
1163 O << ", " << markup("<imm:");
1164 if (OffImm == INT32_MIN)
1166 else if (OffImm < 0)
1167 O << "#-" << -OffImm;
1173 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
1176 const MCOperand &MO1 = MI->getOperand(OpNum);
1177 int32_t OffImm = (int32_t)MO1.getImm();
1179 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1181 O << ", " << markup("<imm:");
1182 if (OffImm == INT32_MIN)
1184 else if (OffImm < 0)
1185 O << "#-" << -OffImm;
1191 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
1194 const MCOperand &MO1 = MI->getOperand(OpNum);
1195 const MCOperand &MO2 = MI->getOperand(OpNum+1);
1196 const MCOperand &MO3 = MI->getOperand(OpNum+2);
1198 O << markup("<mem:") << "[";
1199 printRegName(O, MO1.getReg());
1201 assert(MO2.getReg() && "Invalid so_reg load / store address!");
1203 printRegName(O, MO2.getReg());
1205 unsigned ShAmt = MO3.getImm();
1207 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1213 O << "]" << markup(">");
1216 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1218 const MCOperand &MO = MI->getOperand(OpNum);
1219 O << markup("<imm:")
1220 << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1224 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
1226 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
1228 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1229 O << markup("<imm:")
1235 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
1237 unsigned Imm = MI->getOperand(OpNum).getImm();
1238 O << markup("<imm:")
1239 << "#" << formatImm(Imm + 1)
1243 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
1245 unsigned Imm = MI->getOperand(OpNum).getImm();
1252 default: assert (0 && "illegal ror immediate!");
1253 case 1: O << "8"; break;
1254 case 2: O << "16"; break;
1255 case 3: O << "24"; break;
1260 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
1262 O << markup("<imm:")
1263 << "#" << 16 - MI->getOperand(OpNum).getImm()
1267 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
1269 O << markup("<imm:")
1270 << "#" << 32 - MI->getOperand(OpNum).getImm()
1274 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1276 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1279 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
1282 printRegName(O, MI->getOperand(OpNum).getReg());
1286 void ARMInstPrinter::printVectorListTwo(const MCInst *MI, unsigned OpNum,
1288 unsigned Reg = MI->getOperand(OpNum).getReg();
1289 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1290 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1292 printRegName(O, Reg0);
1294 printRegName(O, Reg1);
1298 void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI,
1301 unsigned Reg = MI->getOperand(OpNum).getReg();
1302 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1303 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1305 printRegName(O, Reg0);
1307 printRegName(O, Reg1);
1311 void ARMInstPrinter::printVectorListThree(const MCInst *MI, unsigned OpNum,
1313 // Normally, it's not safe to use register enum values directly with
1314 // addition to get the next register, but for VFP registers, the
1315 // sort order is guaranteed because they're all of the form D<n>.
1317 printRegName(O, MI->getOperand(OpNum).getReg());
1319 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1321 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1325 void ARMInstPrinter::printVectorListFour(const MCInst *MI, unsigned OpNum,
1327 // Normally, it's not safe to use register enum values directly with
1328 // addition to get the next register, but for VFP registers, the
1329 // sort order is guaranteed because they're all of the form D<n>.
1331 printRegName(O, MI->getOperand(OpNum).getReg());
1333 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1335 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1337 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1341 void ARMInstPrinter::printVectorListOneAllLanes(const MCInst *MI,
1345 printRegName(O, MI->getOperand(OpNum).getReg());
1349 void ARMInstPrinter::printVectorListTwoAllLanes(const MCInst *MI,
1352 unsigned Reg = MI->getOperand(OpNum).getReg();
1353 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1354 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_1);
1356 printRegName(O, Reg0);
1358 printRegName(O, Reg1);
1362 void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
1365 // Normally, it's not safe to use register enum values directly with
1366 // addition to get the next register, but for VFP registers, the
1367 // sort order is guaranteed because they're all of the form D<n>.
1369 printRegName(O, MI->getOperand(OpNum).getReg());
1371 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1373 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1377 void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
1380 // Normally, it's not safe to use register enum values directly with
1381 // addition to get the next register, but for VFP registers, the
1382 // sort order is guaranteed because they're all of the form D<n>.
1384 printRegName(O, MI->getOperand(OpNum).getReg());
1386 printRegName(O, MI->getOperand(OpNum).getReg() + 1);
1388 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1390 printRegName(O, MI->getOperand(OpNum).getReg() + 3);
1394 void ARMInstPrinter::printVectorListTwoSpacedAllLanes(const MCInst *MI,
1397 unsigned Reg = MI->getOperand(OpNum).getReg();
1398 unsigned Reg0 = MRI.getSubReg(Reg, ARM::dsub_0);
1399 unsigned Reg1 = MRI.getSubReg(Reg, ARM::dsub_2);
1401 printRegName(O, Reg0);
1403 printRegName(O, Reg1);
1407 void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
1410 // Normally, it's not safe to use register enum values directly with
1411 // addition to get the next register, but for VFP registers, the
1412 // sort order is guaranteed because they're all of the form D<n>.
1414 printRegName(O, MI->getOperand(OpNum).getReg());
1416 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1418 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1422 void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
1425 // Normally, it's not safe to use register enum values directly with
1426 // addition to get the next register, but for VFP registers, the
1427 // sort order is guaranteed because they're all of the form D<n>.
1429 printRegName(O, MI->getOperand(OpNum).getReg());
1431 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1433 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1435 printRegName(O, MI->getOperand(OpNum).getReg() + 6);
1439 void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
1442 // Normally, it's not safe to use register enum values directly with
1443 // addition to get the next register, but for VFP registers, the
1444 // sort order is guaranteed because they're all of the form D<n>.
1446 printRegName(O, MI->getOperand(OpNum).getReg());
1448 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1450 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1454 void ARMInstPrinter::printVectorListFourSpaced(const MCInst *MI,
1457 // Normally, it's not safe to use register enum values directly with
1458 // addition to get the next register, but for VFP registers, the
1459 // sort order is guaranteed because they're all of the form D<n>.
1461 printRegName(O, MI->getOperand(OpNum).getReg());
1463 printRegName(O, MI->getOperand(OpNum).getReg() + 2);
1465 printRegName(O, MI->getOperand(OpNum).getReg() + 4);
1467 printRegName(O, MI->getOperand(OpNum).getReg() + 6);