1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "MCTargetDesc/ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 #define GET_INSTRUCTION_NAME
26 #include "ARMGenAsmWriter.inc"
28 /// translateShiftImm - Convert shift immediate from 0-31 to 1-32 for printing.
30 /// getSORegOffset returns an integer from 0-31, but '0' should actually be printed
31 /// 32 as the immediate shouldbe within the range 1-32.
32 static unsigned translateShiftImm(unsigned imm) {
39 ARMInstPrinter::ARMInstPrinter(const MCAsmInfo &MAI,
40 const MCSubtargetInfo &STI) :
42 // Initialize the set of available features.
43 setAvailableFeatures(STI.getFeatureBits());
46 StringRef ARMInstPrinter::getOpcodeName(unsigned Opcode) const {
47 return getInstructionName(Opcode);
50 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
51 OS << getRegisterName(RegNo);
54 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
56 unsigned Opcode = MI->getOpcode();
58 // Check for MOVs and print canonical forms, instead.
59 if (Opcode == ARM::MOVsr) {
60 // FIXME: Thumb variants?
61 const MCOperand &Dst = MI->getOperand(0);
62 const MCOperand &MO1 = MI->getOperand(1);
63 const MCOperand &MO2 = MI->getOperand(2);
64 const MCOperand &MO3 = MI->getOperand(3);
66 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
67 printSBitModifierOperand(MI, 6, O);
68 printPredicateOperand(MI, 4, O);
70 O << '\t' << getRegisterName(Dst.getReg())
71 << ", " << getRegisterName(MO1.getReg());
73 O << ", " << getRegisterName(MO2.getReg());
74 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
75 printAnnotation(O, Annot);
79 if (Opcode == ARM::MOVsi) {
80 // FIXME: Thumb variants?
81 const MCOperand &Dst = MI->getOperand(0);
82 const MCOperand &MO1 = MI->getOperand(1);
83 const MCOperand &MO2 = MI->getOperand(2);
85 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
86 printSBitModifierOperand(MI, 5, O);
87 printPredicateOperand(MI, 3, O);
89 O << '\t' << getRegisterName(Dst.getReg())
90 << ", " << getRegisterName(MO1.getReg());
92 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
93 printAnnotation(O, Annot);
97 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
98 printAnnotation(O, Annot);
104 if ((Opcode == ARM::STMDB_UPD || Opcode == ARM::t2STMDB_UPD) &&
105 MI->getOperand(0).getReg() == ARM::SP) {
107 printPredicateOperand(MI, 2, O);
108 if (Opcode == ARM::t2STMDB_UPD)
111 printRegisterList(MI, 4, O);
112 printAnnotation(O, Annot);
115 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP &&
116 MI->getOperand(3).getImm() == -4) {
118 printPredicateOperand(MI, 4, O);
119 O << "\t{" << getRegisterName(MI->getOperand(1).getReg()) << "}";
120 printAnnotation(O, Annot);
125 if ((Opcode == ARM::LDMIA_UPD || Opcode == ARM::t2LDMIA_UPD) &&
126 MI->getOperand(0).getReg() == ARM::SP) {
128 printPredicateOperand(MI, 2, O);
129 if (Opcode == ARM::t2LDMIA_UPD)
132 printRegisterList(MI, 4, O);
133 printAnnotation(O, Annot);
136 if (Opcode == ARM::LDR_POST_IMM && MI->getOperand(2).getReg() == ARM::SP &&
137 MI->getOperand(4).getImm() == 4) {
139 printPredicateOperand(MI, 5, O);
140 O << "\t{" << getRegisterName(MI->getOperand(0).getReg()) << "}";
141 printAnnotation(O, Annot);
147 if ((Opcode == ARM::VSTMSDB_UPD || Opcode == ARM::VSTMDDB_UPD) &&
148 MI->getOperand(0).getReg() == ARM::SP) {
149 O << '\t' << "vpush";
150 printPredicateOperand(MI, 2, O);
152 printRegisterList(MI, 4, O);
153 printAnnotation(O, Annot);
158 if ((Opcode == ARM::VLDMSIA_UPD || Opcode == ARM::VLDMDIA_UPD) &&
159 MI->getOperand(0).getReg() == ARM::SP) {
161 printPredicateOperand(MI, 2, O);
163 printRegisterList(MI, 4, O);
164 printAnnotation(O, Annot);
168 if (Opcode == ARM::tLDMIA) {
169 bool Writeback = true;
170 unsigned BaseReg = MI->getOperand(0).getReg();
171 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
172 if (MI->getOperand(i).getReg() == BaseReg)
178 printPredicateOperand(MI, 1, O);
179 O << '\t' << getRegisterName(BaseReg);
180 if (Writeback) O << "!";
182 printRegisterList(MI, 3, O);
183 printAnnotation(O, Annot);
188 if (Opcode == ARM::tMOVr && MI->getOperand(0).getReg() == ARM::R8 &&
189 MI->getOperand(1).getReg() == ARM::R8) {
191 printPredicateOperand(MI, 2, O);
192 printAnnotation(O, Annot);
196 printInstruction(MI, O);
197 printAnnotation(O, Annot);
200 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
202 const MCOperand &Op = MI->getOperand(OpNo);
204 unsigned Reg = Op.getReg();
205 O << getRegisterName(Reg);
206 } else if (Op.isImm()) {
207 O << '#' << Op.getImm();
209 assert(Op.isExpr() && "unknown operand kind in printOperand");
210 // If a symbolic branch target was added as a constant expression then print
211 // that address in hex.
212 const MCConstantExpr *BranchTarget = dyn_cast<MCConstantExpr>(Op.getExpr());
214 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
216 O.write_hex(Address);
219 // Otherwise, just print the expression.
225 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum,
227 const MCOperand &MO1 = MI->getOperand(OpNum);
230 else if (MO1.isImm())
231 O << "[pc, #" << MO1.getImm() << "]";
233 llvm_unreachable("Unknown LDR label operand?");
236 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
237 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
239 // REG REG 0,SH_OPC - e.g. R5, ROR R3
240 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
241 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum,
243 const MCOperand &MO1 = MI->getOperand(OpNum);
244 const MCOperand &MO2 = MI->getOperand(OpNum+1);
245 const MCOperand &MO3 = MI->getOperand(OpNum+2);
247 O << getRegisterName(MO1.getReg());
249 // Print the shift opc.
250 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
251 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
252 if (ShOpc == ARM_AM::rrx)
255 O << ' ' << getRegisterName(MO2.getReg());
256 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
259 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum,
261 const MCOperand &MO1 = MI->getOperand(OpNum);
262 const MCOperand &MO2 = MI->getOperand(OpNum+1);
264 O << getRegisterName(MO1.getReg());
266 // Print the shift opc.
267 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
268 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
269 if (ShOpc == ARM_AM::rrx)
271 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
275 //===--------------------------------------------------------------------===//
276 // Addressing Mode #2
277 //===--------------------------------------------------------------------===//
279 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
281 const MCOperand &MO1 = MI->getOperand(Op);
282 const MCOperand &MO2 = MI->getOperand(Op+1);
283 const MCOperand &MO3 = MI->getOperand(Op+2);
285 O << "[" << getRegisterName(MO1.getReg());
288 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
290 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
291 << ARM_AM::getAM2Offset(MO3.getImm());
297 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
298 << getRegisterName(MO2.getReg());
300 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
302 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
307 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
309 const MCOperand &MO1 = MI->getOperand(Op);
310 const MCOperand &MO2 = MI->getOperand(Op+1);
311 const MCOperand &MO3 = MI->getOperand(Op+2);
313 O << "[" << getRegisterName(MO1.getReg()) << "], ";
316 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
318 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
323 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
324 << getRegisterName(MO2.getReg());
326 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
328 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
332 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
334 const MCOperand &MO1 = MI->getOperand(Op);
335 const MCOperand &MO2 = MI->getOperand(Op+1);
336 O << "[" << getRegisterName(MO1.getReg()) << ", "
337 << getRegisterName(MO2.getReg()) << "]";
340 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
342 const MCOperand &MO1 = MI->getOperand(Op);
343 const MCOperand &MO2 = MI->getOperand(Op+1);
344 O << "[" << getRegisterName(MO1.getReg()) << ", "
345 << getRegisterName(MO2.getReg()) << ", lsl #1]";
348 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
350 const MCOperand &MO1 = MI->getOperand(Op);
352 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
353 printOperand(MI, Op, O);
357 const MCOperand &MO3 = MI->getOperand(Op+2);
358 unsigned IdxMode = ARM_AM::getAM2IdxMode(MO3.getImm());
360 if (IdxMode == ARMII::IndexModePost) {
361 printAM2PostIndexOp(MI, Op, O);
364 printAM2PreOrOffsetIndexOp(MI, Op, O);
367 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
370 const MCOperand &MO1 = MI->getOperand(OpNum);
371 const MCOperand &MO2 = MI->getOperand(OpNum+1);
374 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
376 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
381 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
382 << getRegisterName(MO1.getReg());
384 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
386 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
390 //===--------------------------------------------------------------------===//
391 // Addressing Mode #3
392 //===--------------------------------------------------------------------===//
394 void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
396 const MCOperand &MO1 = MI->getOperand(Op);
397 const MCOperand &MO2 = MI->getOperand(Op+1);
398 const MCOperand &MO3 = MI->getOperand(Op+2);
400 O << "[" << getRegisterName(MO1.getReg()) << "], ";
403 O << (char)ARM_AM::getAM3Op(MO3.getImm())
404 << getRegisterName(MO2.getReg());
408 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
410 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
414 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
416 const MCOperand &MO1 = MI->getOperand(Op);
417 const MCOperand &MO2 = MI->getOperand(Op+1);
418 const MCOperand &MO3 = MI->getOperand(Op+2);
420 O << '[' << getRegisterName(MO1.getReg());
423 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
424 << getRegisterName(MO2.getReg()) << ']';
428 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
430 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
435 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
437 const MCOperand &MO3 = MI->getOperand(Op+2);
438 unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
440 if (IdxMode == ARMII::IndexModePost) {
441 printAM3PostIndexOp(MI, Op, O);
444 printAM3PreOrOffsetIndexOp(MI, Op, O);
447 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
450 const MCOperand &MO1 = MI->getOperand(OpNum);
451 const MCOperand &MO2 = MI->getOperand(OpNum+1);
454 O << getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
455 << getRegisterName(MO1.getReg());
459 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
461 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
465 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
468 const MCOperand &MO = MI->getOperand(OpNum);
469 unsigned Imm = MO.getImm();
470 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
473 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
475 const MCOperand &MO1 = MI->getOperand(OpNum);
476 const MCOperand &MO2 = MI->getOperand(OpNum+1);
478 O << (MO2.getImm() ? "" : "-") << getRegisterName(MO1.getReg());
481 void ARMInstPrinter::printPostIdxImm8s4Operand(const MCInst *MI,
484 const MCOperand &MO = MI->getOperand(OpNum);
485 unsigned Imm = MO.getImm();
486 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
490 void ARMInstPrinter::printLdStmModeOperand(const MCInst *MI, unsigned OpNum,
492 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MI->getOperand(OpNum)
494 O << ARM_AM::getAMSubModeStr(Mode);
497 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
499 const MCOperand &MO1 = MI->getOperand(OpNum);
500 const MCOperand &MO2 = MI->getOperand(OpNum+1);
502 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
503 printOperand(MI, OpNum, O);
507 O << "[" << getRegisterName(MO1.getReg());
509 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
510 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
511 if (ImmOffs || Op == ARM_AM::sub) {
513 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
519 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
521 const MCOperand &MO1 = MI->getOperand(OpNum);
522 const MCOperand &MO2 = MI->getOperand(OpNum+1);
524 O << "[" << getRegisterName(MO1.getReg());
526 // FIXME: Both darwin as and GNU as violate ARM docs here.
527 O << ", :" << (MO2.getImm() << 3);
532 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
534 const MCOperand &MO1 = MI->getOperand(OpNum);
535 O << "[" << getRegisterName(MO1.getReg()) << "]";
538 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
541 const MCOperand &MO = MI->getOperand(OpNum);
542 if (MO.getReg() == 0)
545 O << ", " << getRegisterName(MO.getReg());
548 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
551 const MCOperand &MO = MI->getOperand(OpNum);
552 uint32_t v = ~MO.getImm();
553 int32_t lsb = CountTrailingZeros_32(v);
554 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
555 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
556 O << '#' << lsb << ", #" << width;
559 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
561 unsigned val = MI->getOperand(OpNum).getImm();
562 O << ARM_MB::MemBOptToString(val);
565 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
567 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
568 bool isASR = (ShiftOp & (1 << 5)) != 0;
569 unsigned Amt = ShiftOp & 0x1f;
571 O << ", asr #" << (Amt == 0 ? 32 : Amt);
573 O << ", lsl #" << Amt;
576 void ARMInstPrinter::printPKHLSLShiftImm(const MCInst *MI, unsigned OpNum,
578 unsigned Imm = MI->getOperand(OpNum).getImm();
581 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
582 O << ", lsl #" << Imm;
585 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
587 unsigned Imm = MI->getOperand(OpNum).getImm();
588 // A shift amount of 32 is encoded as 0.
591 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
592 O << ", asr #" << Imm;
595 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
598 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
599 if (i != OpNum) O << ", ";
600 O << getRegisterName(MI->getOperand(i).getReg());
605 void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum,
607 const MCOperand &Op = MI->getOperand(OpNum);
614 void ARMInstPrinter::printCPSIMod(const MCInst *MI, unsigned OpNum,
616 const MCOperand &Op = MI->getOperand(OpNum);
617 O << ARM_PROC::IModToString(Op.getImm());
620 void ARMInstPrinter::printCPSIFlag(const MCInst *MI, unsigned OpNum,
622 const MCOperand &Op = MI->getOperand(OpNum);
623 unsigned IFlags = Op.getImm();
624 for (int i=2; i >= 0; --i)
625 if (IFlags & (1 << i))
626 O << ARM_PROC::IFlagsToString(1 << i);
632 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
634 const MCOperand &Op = MI->getOperand(OpNum);
635 unsigned SpecRegRBit = Op.getImm() >> 4;
636 unsigned Mask = Op.getImm() & 0xf;
638 if (getAvailableFeatures() & ARM::FeatureMClass) {
639 switch (Op.getImm()) {
640 default: assert(0 && "Unexpected mask value!");
641 case 0: O << "apsr"; return;
642 case 1: O << "iapsr"; return;
643 case 2: O << "eapsr"; return;
644 case 3: O << "xpsr"; return;
645 case 5: O << "ipsr"; return;
646 case 6: O << "epsr"; return;
647 case 7: O << "iepsr"; return;
648 case 8: O << "msp"; return;
649 case 9: O << "psp"; return;
650 case 16: O << "primask"; return;
651 case 17: O << "basepri"; return;
652 case 18: O << "basepri_max"; return;
653 case 19: O << "faultmask"; return;
654 case 20: O << "control"; return;
658 // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as
659 // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively.
660 if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) {
664 case 4: O << "g"; return;
665 case 8: O << "nzcvq"; return;
666 case 12: O << "nzcvqg"; return;
668 llvm_unreachable("Unexpected mask value!");
678 if (Mask & 8) O << 'f';
679 if (Mask & 4) O << 's';
680 if (Mask & 2) O << 'x';
681 if (Mask & 1) O << 'c';
685 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
687 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
689 O << ARMCondCodeToString(CC);
692 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
695 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
696 O << ARMCondCodeToString(CC);
699 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
701 if (MI->getOperand(OpNum).getReg()) {
702 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
703 "Expect ARM CPSR register!");
708 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
710 O << MI->getOperand(OpNum).getImm();
713 void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum,
715 O << "p" << MI->getOperand(OpNum).getImm();
718 void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum,
720 O << "c" << MI->getOperand(OpNum).getImm();
723 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
725 llvm_unreachable("Unhandled PC-relative pseudo-instruction!");
728 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
730 O << "#" << MI->getOperand(OpNum).getImm() * 4;
733 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
735 unsigned Imm = MI->getOperand(OpNum).getImm();
736 O << "#" << (Imm == 0 ? 32 : Imm);
739 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
741 // (3 - the number of trailing zeros) is the number of then / else.
742 unsigned Mask = MI->getOperand(OpNum).getImm();
743 unsigned CondBit0 = Mask >> 4 & 1;
744 unsigned NumTZ = CountTrailingZeros_32(Mask);
745 assert(NumTZ <= 3 && "Invalid IT mask!");
746 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
747 bool T = ((Mask >> Pos) & 1) == CondBit0;
755 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
757 const MCOperand &MO1 = MI->getOperand(Op);
758 const MCOperand &MO2 = MI->getOperand(Op + 1);
760 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
761 printOperand(MI, Op, O);
765 O << "[" << getRegisterName(MO1.getReg());
766 if (unsigned RegNum = MO2.getReg())
767 O << ", " << getRegisterName(RegNum);
771 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
775 const MCOperand &MO1 = MI->getOperand(Op);
776 const MCOperand &MO2 = MI->getOperand(Op + 1);
778 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
779 printOperand(MI, Op, O);
783 O << "[" << getRegisterName(MO1.getReg());
784 if (unsigned ImmOffs = MO2.getImm())
785 O << ", #" << ImmOffs * Scale;
789 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
792 printThumbAddrModeImm5SOperand(MI, Op, O, 1);
795 void ARMInstPrinter::printThumbAddrModeImm5S2Operand(const MCInst *MI,
798 printThumbAddrModeImm5SOperand(MI, Op, O, 2);
801 void ARMInstPrinter::printThumbAddrModeImm5S4Operand(const MCInst *MI,
804 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
807 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
809 printThumbAddrModeImm5SOperand(MI, Op, O, 4);
812 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
813 // register with shift forms.
815 // REG IMM, SH_OPC - e.g. R5, LSL #3
816 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
818 const MCOperand &MO1 = MI->getOperand(OpNum);
819 const MCOperand &MO2 = MI->getOperand(OpNum+1);
821 unsigned Reg = MO1.getReg();
822 O << getRegisterName(Reg);
824 // Print the shift opc.
825 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
826 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
827 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
828 if (ShOpc != ARM_AM::rrx)
829 O << " #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
832 void ARMInstPrinter::printAddrModeImm12Operand(const MCInst *MI, unsigned OpNum,
834 const MCOperand &MO1 = MI->getOperand(OpNum);
835 const MCOperand &MO2 = MI->getOperand(OpNum+1);
837 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
838 printOperand(MI, OpNum, O);
842 O << "[" << getRegisterName(MO1.getReg());
844 int32_t OffImm = (int32_t)MO2.getImm();
845 bool isSub = OffImm < 0;
846 // Special value for #-0. All others are normal.
847 if (OffImm == INT32_MIN)
850 O << ", #-" << -OffImm;
852 O << ", #" << OffImm;
856 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
859 const MCOperand &MO1 = MI->getOperand(OpNum);
860 const MCOperand &MO2 = MI->getOperand(OpNum+1);
862 O << "[" << getRegisterName(MO1.getReg());
864 int32_t OffImm = (int32_t)MO2.getImm();
866 if (OffImm == INT32_MIN)
869 O << ", #-" << -OffImm;
871 O << ", #" << OffImm;
875 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
878 const MCOperand &MO1 = MI->getOperand(OpNum);
879 const MCOperand &MO2 = MI->getOperand(OpNum+1);
881 O << "[" << getRegisterName(MO1.getReg());
883 int32_t OffImm = (int32_t)MO2.getImm() / 4;
886 O << ", #-" << -OffImm * 4;
888 O << ", #" << OffImm * 4;
892 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
895 const MCOperand &MO1 = MI->getOperand(OpNum);
896 const MCOperand &MO2 = MI->getOperand(OpNum+1);
898 O << "[" << getRegisterName(MO1.getReg());
900 O << ", #" << MO2.getImm() * 4;
904 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
907 const MCOperand &MO1 = MI->getOperand(OpNum);
908 int32_t OffImm = (int32_t)MO1.getImm();
911 O << ", #-" << -OffImm;
913 O << ", #" << OffImm;
916 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
919 const MCOperand &MO1 = MI->getOperand(OpNum);
920 int32_t OffImm = (int32_t)MO1.getImm() / 4;
925 O << "#-" << -OffImm * 4;
927 O << "#" << OffImm * 4;
931 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
934 const MCOperand &MO1 = MI->getOperand(OpNum);
935 const MCOperand &MO2 = MI->getOperand(OpNum+1);
936 const MCOperand &MO3 = MI->getOperand(OpNum+2);
938 O << "[" << getRegisterName(MO1.getReg());
940 assert(MO2.getReg() && "Invalid so_reg load / store address!");
941 O << ", " << getRegisterName(MO2.getReg());
943 unsigned ShAmt = MO3.getImm();
945 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
946 O << ", lsl #" << ShAmt;
951 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
953 const MCOperand &MO = MI->getOperand(OpNum);
954 O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
957 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
959 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
961 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
962 O << "#0x" << utohexstr(Val);
965 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
967 unsigned Imm = MI->getOperand(OpNum).getImm();
971 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
973 unsigned Imm = MI->getOperand(OpNum).getImm();
978 default: assert (0 && "illegal ror immediate!");
979 case 1: O << "8"; break;
980 case 2: O << "16"; break;
981 case 3: O << "24"; break;
985 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
987 O << "[" << MI->getOperand(OpNum).getImm() << "]";