1 //===- ThumbDisassemblerCore.h - Thumb disassembler helpers -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code for disassembling a Thumb instr. It is to be included by
12 // ARMDisassemblerCore.cpp because it contains the static DisassembleThumbFrm()
13 // function which acts as the dispatcher to disassemble a Thumb instruction.
15 //===----------------------------------------------------------------------===//
17 ///////////////////////////////
19 // Utility Functions //
21 ///////////////////////////////
23 // Utilities for 16-bit Thumb instructions.
25 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
27 [ tRm ] [ tRn ] [ tRd ]
40 // Extract tRt: Inst{10-8}.
41 static inline unsigned getT1tRt(uint32_t insn) {
42 return slice(insn, 10, 8);
45 // Extract tRm: Inst{8-6}.
46 static inline unsigned getT1tRm(uint32_t insn) {
47 return slice(insn, 8, 6);
50 // Extract tRn: Inst{5-3}.
51 static inline unsigned getT1tRn(uint32_t insn) {
52 return slice(insn, 5, 3);
55 // Extract tRd: Inst{2-0}.
56 static inline unsigned getT1tRd(uint32_t insn) {
57 return slice(insn, 2, 0);
60 // Extract [D:Rd]: Inst{7:2-0}.
61 static inline unsigned getT1Rd(uint32_t insn) {
62 return slice(insn, 7, 7) << 3 | slice(insn, 2, 0);
65 // Extract Rm: Inst{6-3}.
66 static inline unsigned getT1Rm(uint32_t insn) {
67 return slice(insn, 6, 3);
70 // Extract imm3: Inst{8-6}.
71 static inline unsigned getT1Imm3(uint32_t insn) {
72 return slice(insn, 8, 6);
75 // Extract imm5: Inst{10-6}.
76 static inline unsigned getT1Imm5(uint32_t insn) {
77 return slice(insn, 10, 6);
80 // Extract i:imm5: Inst{9:7-3}.
81 static inline unsigned getT1Imm6(uint32_t insn) {
82 return slice(insn, 9, 9) << 5 | slice(insn, 7, 3);
85 // Extract imm7: Inst{6-0}.
86 static inline unsigned getT1Imm7(uint32_t insn) {
87 return slice(insn, 6, 0);
90 // Extract imm8: Inst{7-0}.
91 static inline unsigned getT1Imm8(uint32_t insn) {
92 return slice(insn, 7, 0);
95 // Extract imm11: Inst{10-0}.
96 static inline unsigned getT1Imm11(uint32_t insn) {
97 return slice(insn, 10, 0);
100 // Extract cond: Inst{11-8}.
101 static inline unsigned getT1Cond(uint32_t insn) {
102 return slice(insn, 11, 8);
105 static inline bool IsGPR(unsigned RegClass) {
106 return RegClass == ARM::GPRRegClassID || RegClass == ARM::rGPRRegClassID;
109 // Utilities for 32-bit Thumb instructions.
111 // Extract imm4: Inst{19-16}.
112 static inline unsigned getImm4(uint32_t insn) {
113 return slice(insn, 19, 16);
116 // Extract imm3: Inst{14-12}.
117 static inline unsigned getImm3(uint32_t insn) {
118 return slice(insn, 14, 12);
121 // Extract imm8: Inst{7-0}.
122 static inline unsigned getImm8(uint32_t insn) {
123 return slice(insn, 7, 0);
126 // A8.6.61 LDRB (immediate, Thumb) and friends
129 static inline int decodeImm8(uint32_t insn) {
130 int Offset = getImm8(insn);
131 return slice(insn, 9, 9) ? Offset : -Offset;
134 // Extract imm12: Inst{11-0}.
135 static inline unsigned getImm12(uint32_t insn) {
136 return slice(insn, 11, 0);
139 // A8.6.63 LDRB (literal) and friends
142 static inline int decodeImm12(uint32_t insn) {
143 int Offset = getImm12(insn);
144 return slice(insn, 23, 23) ? Offset : -Offset;
147 // Extract imm2: Inst{7-6}.
148 static inline unsigned getImm2(uint32_t insn) {
149 return slice(insn, 7, 6);
152 // For BFI, BFC, t2SBFX, and t2UBFX.
153 // Extract lsb: Inst{14-12:7-6}.
154 static inline unsigned getLsb(uint32_t insn) {
155 return getImm3(insn) << 2 | getImm2(insn);
159 // Extract msb: Inst{4-0}.
160 static inline unsigned getMsb(uint32_t insn) {
161 return slice(insn, 4, 0);
164 // For t2SBFX and t2UBFX.
165 // Extract widthminus1: Inst{4-0}.
166 static inline unsigned getWidthMinus1(uint32_t insn) {
167 return slice(insn, 4, 0);
170 // For t2ADDri12 and t2SUBri12.
171 // imm12 = i:imm3:imm8;
172 static inline unsigned getIImm3Imm8(uint32_t insn) {
173 return slice(insn, 26, 26) << 11 | getImm3(insn) << 8 | getImm8(insn);
176 // For t2MOVi16 and t2MOVTi16.
177 // imm16 = imm4:i:imm3:imm8;
178 static inline unsigned getImm16(uint32_t insn) {
179 return getImm4(insn) << 12 | slice(insn, 26, 26) << 11 |
180 getImm3(insn) << 8 | getImm8(insn);
183 // Inst{5-4} encodes the shift type.
184 static inline unsigned getShiftTypeBits(uint32_t insn) {
185 return slice(insn, 5, 4);
188 // Inst{14-12}:Inst{7-6} encodes the imm5 shift amount.
189 static inline unsigned getShiftAmtBits(uint32_t insn) {
190 return getImm3(insn) << 2 | getImm2(insn);
194 // Encoding T1 ARMv6T2, ARMv7
195 // LLVM-specific encoding for #<lsb> and #<width>
196 static inline bool getBitfieldInvMask(uint32_t insn, uint32_t &mask) {
197 uint32_t lsb = getImm3(insn) << 2 | getImm2(insn);
198 uint32_t msb = getMsb(insn);
201 DEBUG(errs() << "Encoding error: msb < lsb\n");
204 for (uint32_t i = lsb; i <= msb; ++i)
210 // A8.4 Shifts applied to a register
211 // A8.4.1 Constant shifts
212 // A8.4.3 Pseudocode details of instruction-specified shifts and rotates
214 // decodeImmShift() returns the shift amount and the the shift opcode.
215 // Note that, as of Jan-06-2010, LLVM does not support rrx shifted operands yet.
216 static inline unsigned decodeImmShift(unsigned bits2, unsigned imm5,
217 ARM_AM::ShiftOpc &ShOp) {
219 assert(imm5 < 32 && "Invalid imm5 argument");
221 default: assert(0 && "No such value");
223 ShOp = (imm5 == 0 ? ARM_AM::no_shift : ARM_AM::lsl);
227 return (imm5 == 0 ? 32 : imm5);
230 return (imm5 == 0 ? 32 : imm5);
232 ShOp = (imm5 == 0 ? ARM_AM::rrx : ARM_AM::ror);
233 return (imm5 == 0 ? 1 : imm5);
237 // A6.3.2 Modified immediate constants in Thumb instructions
239 // ThumbExpandImm() returns the modified immediate constant given an imm12 for
240 // Thumb data-processing instructions with modified immediate.
241 // See also A6.3.1 Data-processing (modified immediate).
242 static inline unsigned ThumbExpandImm(unsigned imm12) {
243 assert(imm12 <= 0xFFF && "Invalid imm12 argument");
245 // If the leading two bits is 0b00, the modified immediate constant is
246 // obtained by splatting the low 8 bits into the first byte, every other byte,
247 // or every byte of a 32-bit value.
249 // Otherwise, a rotate right of '1':imm12<6:0> by the amount imm12<11:7> is
252 if (slice(imm12, 11, 10) == 0) {
253 unsigned short control = slice(imm12, 9, 8);
254 unsigned imm8 = slice(imm12, 7, 0);
257 assert(0 && "No such value");
262 return imm8 << 16 | imm8;
264 return imm8 << 24 | imm8 << 8;
266 return imm8 << 24 | imm8 << 16 | imm8 << 8 | imm8;
269 // A rotate is required.
270 unsigned Val = 1 << 7 | slice(imm12, 6, 0);
271 unsigned Amt = slice(imm12, 11, 7);
272 return ARM_AM::rotr32(Val, Amt);
276 static inline int decodeImm32_B_EncodingT3(uint32_t insn) {
277 bool S = slice(insn, 26, 26);
278 bool J1 = slice(insn, 13, 13);
279 bool J2 = slice(insn, 11, 11);
280 unsigned Imm21 = slice(insn, 21, 16) << 12 | slice(insn, 10, 0) << 1;
281 if (S) Imm21 |= 1 << 20;
282 if (J2) Imm21 |= 1 << 19;
283 if (J1) Imm21 |= 1 << 18;
285 return SignExtend32<21>(Imm21);
288 static inline int decodeImm32_B_EncodingT4(uint32_t insn) {
289 unsigned S = slice(insn, 26, 26);
290 bool I1 = slice(insn, 13, 13) == S;
291 bool I2 = slice(insn, 11, 11) == S;
292 unsigned Imm25 = slice(insn, 25, 16) << 12 | slice(insn, 10, 0) << 1;
293 if (S) Imm25 |= 1 << 24;
294 if (I1) Imm25 |= 1 << 23;
295 if (I2) Imm25 |= 1 << 22;
297 return SignExtend32<25>(Imm25);
300 static inline int decodeImm32_BL(uint32_t insn) {
301 unsigned S = slice(insn, 26, 26);
302 bool I1 = slice(insn, 13, 13) == S;
303 bool I2 = slice(insn, 11, 11) == S;
304 unsigned Imm25 = slice(insn, 25, 16) << 12 | slice(insn, 10, 0) << 1;
305 if (S) Imm25 |= 1 << 24;
306 if (I1) Imm25 |= 1 << 23;
307 if (I2) Imm25 |= 1 << 22;
309 return SignExtend32<25>(Imm25);
312 static inline int decodeImm32_BLX(uint32_t insn) {
313 unsigned S = slice(insn, 26, 26);
314 bool I1 = slice(insn, 13, 13) == S;
315 bool I2 = slice(insn, 11, 11) == S;
316 unsigned Imm25 = slice(insn, 25, 16) << 12 | slice(insn, 10, 1) << 2;
317 if (S) Imm25 |= 1 << 24;
318 if (I1) Imm25 |= 1 << 23;
319 if (I2) Imm25 |= 1 << 22;
321 return SignExtend32<25>(Imm25);
324 // See, for example, A8.6.221 SXTAB16.
325 static inline unsigned decodeRotate(uint32_t insn) {
326 unsigned rotate = slice(insn, 5, 4);
330 ///////////////////////////////////////////////
332 // Thumb1 instruction disassembly functions. //
334 ///////////////////////////////////////////////
336 // See "Utilities for 16-bit Thumb instructions" for register naming convention.
338 // A6.2.1 Shift (immediate), add, subtract, move, and compare
340 // shift immediate: tRd CPSR tRn imm5
341 // add/sub register: tRd CPSR tRn tRm
342 // add/sub 3-bit immediate: tRd CPSR tRn imm3
343 // add/sub 8-bit immediate: tRt CPSR tRt(TIED_TO) imm8
344 // mov/cmp immediate: tRt [CPSR] imm8 (CPSR present for mov)
348 static bool DisassembleThumb1General(MCInst &MI, unsigned Opcode, uint32_t insn,
349 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
351 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
352 unsigned &OpIdx = NumOpsAdded;
356 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID
357 && "Invalid arguments");
359 bool Imm3 = (Opcode == ARM::tADDi3 || Opcode == ARM::tSUBi3);
361 // Use Rt implies use imm8.
362 bool UseRt = (Opcode == ARM::tADDi8 || Opcode == ARM::tSUBi8 ||
363 Opcode == ARM::tMOVi8 || Opcode == ARM::tCMPi8);
365 // Add the destination operand.
366 MI.addOperand(MCOperand::CreateReg(
367 getRegisterEnum(B, ARM::tGPRRegClassID,
368 UseRt ? getT1tRt(insn) : getT1tRd(insn))));
371 // Check whether the next operand to be added is a CCR Register.
372 if (OpInfo[OpIdx].RegClass == ARM::CCRRegClassID) {
373 assert(OpInfo[OpIdx].isOptionalDef() && "Optional def operand expected");
374 MI.addOperand(MCOperand::CreateReg(B->InITBlock() ? 0 : ARM::CPSR));
378 // Check whether the next operand to be added is a Thumb1 Register.
379 assert(OpIdx < NumOps && "More operands expected");
380 if (OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID) {
381 // For UseRt, the reg operand is tied to the first reg operand.
382 MI.addOperand(MCOperand::CreateReg(
383 getRegisterEnum(B, ARM::tGPRRegClassID,
384 UseRt ? getT1tRt(insn) : getT1tRn(insn))));
388 // Special case for tMOVSr.
392 // The next available operand is either a reg operand or an imm operand.
393 if (OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID) {
394 // Three register operand instructions.
395 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
398 assert(OpInfo[OpIdx].RegClass < 0 &&
399 !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()
400 && "Pure imm operand expected");
401 MI.addOperand(MCOperand::CreateImm(UseRt ? getT1Imm8(insn)
402 : (Imm3 ? getT1Imm3(insn)
403 : getT1Imm5(insn))));
410 // A6.2.2 Data-processing
412 // tCMPr, tTST, tCMN: tRd tRn
413 // tMVN, tRSB: tRd CPSR tRn
414 // Others: tRd CPSR tRd(TIED_TO) tRn
415 static bool DisassembleThumb1DP(MCInst &MI, unsigned Opcode, uint32_t insn,
416 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
418 const TargetInstrDesc &TID = ARMInsts[Opcode];
419 const TargetOperandInfo *OpInfo = TID.OpInfo;
420 unsigned &OpIdx = NumOpsAdded;
424 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
425 (OpInfo[1].RegClass == ARM::CCRRegClassID
426 || OpInfo[1].RegClass == ARM::tGPRRegClassID)
427 && "Invalid arguments");
429 // Add the destination operand.
430 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
434 // Check whether the next operand to be added is a CCR Register.
435 if (OpInfo[OpIdx].RegClass == ARM::CCRRegClassID) {
436 assert(OpInfo[OpIdx].isOptionalDef() && "Optional def operand expected");
437 MI.addOperand(MCOperand::CreateReg(B->InITBlock() ? 0 : ARM::CPSR));
441 // We have either { tRd(TIED_TO), tRn } or { tRn } remaining.
442 // Process the TIED_TO operand first.
444 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID
445 && "Thumb reg operand expected");
447 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
448 // The reg operand is tied to the first reg operand.
449 MI.addOperand(MI.getOperand(Idx));
453 // Process possible next reg operand.
454 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID) {
456 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
464 // A6.2.3 Special data instructions and branch and exchange
466 // tADDhirr: Rd Rd(TIED_TO) Rm
468 // tMOVr, tMOVgpr2gpr, tMOVgpr2tgpr, tMOVtgpr2gpr: Rd|tRd Rm|tRn
469 // tBX_RET: 0 operand
470 // tBX_RET_vararg: Rm
472 static bool DisassembleThumb1Special(MCInst &MI, unsigned Opcode, uint32_t insn,
473 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
475 // tBX_RET has 0 operand.
479 // BX/BLX has 1 reg operand: Rm.
481 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
487 const TargetInstrDesc &TID = ARMInsts[Opcode];
488 const TargetOperandInfo *OpInfo = TID.OpInfo;
489 unsigned &OpIdx = NumOpsAdded;
493 // Add the destination operand.
494 unsigned RegClass = OpInfo[OpIdx].RegClass;
495 MI.addOperand(MCOperand::CreateReg(
496 getRegisterEnum(B, RegClass,
497 IsGPR(RegClass) ? getT1Rd(insn)
501 // We have either { Rd(TIED_TO), Rm } or { Rm|tRn } remaining.
502 // Process the TIED_TO operand first.
504 assert(OpIdx < NumOps && "More operands expected");
506 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
507 // The reg operand is tied to the first reg operand.
508 MI.addOperand(MI.getOperand(Idx));
512 // The next reg operand is either Rm or tRn.
513 assert(OpIdx < NumOps && "More operands expected");
514 RegClass = OpInfo[OpIdx].RegClass;
515 MI.addOperand(MCOperand::CreateReg(
516 getRegisterEnum(B, RegClass,
517 IsGPR(RegClass) ? getT1Rm(insn)
524 // A8.6.59 LDR (literal)
526 // tLDRpci: tRt imm8*4
527 static bool DisassembleThumb1LdPC(MCInst &MI, unsigned Opcode, uint32_t insn,
528 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
530 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
531 if (!OpInfo) return false;
533 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
534 (OpInfo[1].RegClass < 0 &&
535 !OpInfo[1].isPredicate() &&
536 !OpInfo[1].isOptionalDef())
537 && "Invalid arguments");
539 // Add the destination operand.
540 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
543 // And the (imm8 << 2) operand.
544 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn) << 2));
551 // Thumb specific addressing modes (see ARMInstrThumb.td):
553 // t_addrmode_rr := reg + reg
555 // t_addrmode_s4 := reg + reg
558 // t_addrmode_s2 := reg + reg
561 // t_addrmode_s1 := reg + reg
564 // t_addrmode_sp := sp + imm8 * 4
567 // A8.6.63 LDRB (literal)
568 // A8.6.79 LDRSB (literal)
569 // A8.6.75 LDRH (literal)
570 // A8.6.83 LDRSH (literal)
571 // A8.6.59 LDR (literal)
573 // These instrs calculate an address from the PC value and an immediate offset.
574 // Rd Rn=PC (+/-)imm12 (+ if Inst{23} == 0b1)
575 static bool DisassembleThumb2Ldpci(MCInst &MI, unsigned Opcode,
576 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
578 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
579 if (!OpInfo) return false;
581 assert(NumOps >= 2 &&
582 OpInfo[0].RegClass == ARM::GPRRegClassID &&
583 OpInfo[1].RegClass < 0 &&
584 "Expect >= 2 operands, first as reg, and second as imm operand");
586 // Build the register operand, followed by the (+/-)imm12 immediate.
588 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
591 MI.addOperand(MCOperand::CreateImm(decodeImm12(insn)));
599 // A6.2.4 Load/store single data item
601 // Load/Store Register (reg|imm): tRd tRn imm5 tRm
602 // Load Register Signed Byte|Halfword: tRd tRn tRm
603 static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode,
604 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
606 const TargetInstrDesc &TID = ARMInsts[Opcode];
607 const TargetOperandInfo *OpInfo = TID.OpInfo;
608 unsigned &OpIdx = NumOpsAdded;
610 // Table A6-5 16-bit Thumb Load/store instructions
611 // opA = 0b0101 for STR/LDR (register) and friends.
612 // Otherwise, we have STR/LDR (immediate) and friends.
613 bool Imm5 = (opA != 5);
616 && OpInfo[0].RegClass == ARM::tGPRRegClassID
617 && OpInfo[1].RegClass == ARM::tGPRRegClassID
618 && "Expect >= 2 operands and first two as thumb reg operands");
620 // Add the destination reg and the base reg.
621 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
623 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
627 // We have either { imm5, tRm } or { tRm } remaining.
628 // Process the imm5 first. Note that STR/LDR (register) should skip the imm5
629 // offset operand for t_addrmode_s[1|2|4].
631 assert(OpIdx < NumOps && "More operands expected");
633 if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate() &&
634 !OpInfo[OpIdx].isOptionalDef()) {
636 MI.addOperand(MCOperand::CreateImm(Imm5 ? getT1Imm5(insn) : 0));
640 // The next reg operand is tRm, the offset.
641 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID
642 && "Thumb reg operand expected");
643 MI.addOperand(MCOperand::CreateReg(
645 : getRegisterEnum(B, ARM::tGPRRegClassID,
652 // A6.2.4 Load/store single data item
654 // Load/Store Register SP relative: tRt ARM::SP imm8
655 static bool DisassembleThumb1LdStSP(MCInst &MI, unsigned Opcode, uint32_t insn,
656 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
658 assert((Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)
659 && "Unexpected opcode");
661 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
662 if (!OpInfo) return false;
664 assert(NumOps >= 3 &&
665 OpInfo[0].RegClass == ARM::tGPRRegClassID &&
666 OpInfo[1].RegClass == ARM::GPRRegClassID &&
667 (OpInfo[2].RegClass < 0 &&
668 !OpInfo[2].isPredicate() &&
669 !OpInfo[2].isOptionalDef())
670 && "Invalid arguments");
672 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
674 MI.addOperand(MCOperand::CreateReg(ARM::SP));
675 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn)));
680 // Table A6-1 16-bit Thumb instruction encoding
683 // tADDrPCi: tRt imm8
684 static bool DisassembleThumb1AddPCi(MCInst &MI, unsigned Opcode, uint32_t insn,
685 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
687 assert(Opcode == ARM::tADDrPCi && "Unexpected opcode");
689 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
690 if (!OpInfo) return false;
692 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
693 (OpInfo[1].RegClass < 0 &&
694 !OpInfo[1].isPredicate() &&
695 !OpInfo[1].isOptionalDef())
696 && "Invalid arguments");
698 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
700 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn)));
705 // Table A6-1 16-bit Thumb instruction encoding
706 // A8.6.8 ADD (SP plus immediate)
708 // tADDrSPi: tRt ARM::SP imm8
709 static bool DisassembleThumb1AddSPi(MCInst &MI, unsigned Opcode, uint32_t insn,
710 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
712 assert(Opcode == ARM::tADDrSPi && "Unexpected opcode");
714 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
715 if (!OpInfo) return false;
717 assert(NumOps >= 3 &&
718 OpInfo[0].RegClass == ARM::tGPRRegClassID &&
719 OpInfo[1].RegClass == ARM::GPRRegClassID &&
720 (OpInfo[2].RegClass < 0 &&
721 !OpInfo[2].isPredicate() &&
722 !OpInfo[2].isOptionalDef())
723 && "Invalid arguments");
725 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
727 MI.addOperand(MCOperand::CreateReg(ARM::SP));
728 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn)));
733 // tPUSH, tPOP: Pred-Imm Pred-CCR register_list
735 // where register_list = low registers + [lr] for PUSH or
736 // low registers + [pc] for POP
738 // "low registers" is specified by Inst{7-0}
739 // lr|pc is specified by Inst{8}
740 static bool DisassembleThumb1PushPop(MCInst &MI, unsigned Opcode, uint32_t insn,
741 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
743 assert((Opcode == ARM::tPUSH || Opcode == ARM::tPOP) && "Unexpected opcode");
745 unsigned &OpIdx = NumOpsAdded;
747 // Handling the two predicate operands before the reglist.
748 if (B->DoPredicateOperands(MI, Opcode, insn, NumOps))
751 DEBUG(errs() << "Expected predicate operands not found.\n");
755 unsigned RegListBits = slice(insn, 8, 8) << (Opcode == ARM::tPUSH ? 14 : 15)
758 // Fill the variadic part of reglist.
759 for (unsigned i = 0; i < 16; ++i) {
760 if ((RegListBits >> i) & 1) {
761 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
770 // A6.2.5 Miscellaneous 16-bit instructions
771 // Delegate to DisassembleThumb1PushPop() for tPUSH & tPOP.
773 // tADDspi, tSUBspi: ARM::SP ARM::SP(TIED_TO) imm7
774 // t2IT: firstcond=Inst{7-4} mask=Inst{3-0}
775 // tCBNZ, tCBZ: tRd imm6*2
777 // tNOP, tSEV, tYIELD, tWFE, tWFI:
778 // no operand (except predicate pair)
779 // tSETENDBE, tSETENDLE, :
782 static bool DisassembleThumb1Misc(MCInst &MI, unsigned Opcode, uint32_t insn,
783 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
788 if (Opcode == ARM::tPUSH || Opcode == ARM::tPOP)
789 return DisassembleThumb1PushPop(MI, Opcode, insn, NumOps, NumOpsAdded, B);
791 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
793 // Predicate operands are handled elsewhere.
795 OpInfo[0].isPredicate() && OpInfo[1].isPredicate() &&
796 OpInfo[0].RegClass < 0 && OpInfo[1].RegClass == ARM::CCRRegClassID) {
800 if (Opcode == ARM::tADDspi || Opcode == ARM::tSUBspi) {
801 // Special case handling for tADDspi and tSUBspi.
802 // A8.6.8 ADD (SP plus immediate) & A8.6.215 SUB (SP minus immediate)
803 MI.addOperand(MCOperand::CreateReg(ARM::SP));
804 MI.addOperand(MCOperand::CreateReg(ARM::SP));
805 MI.addOperand(MCOperand::CreateImm(getT1Imm7(insn)));
810 if (Opcode == ARM::t2IT) {
811 // Special case handling for If-Then.
813 // Tag the (firstcond[0] bit << 4) along with mask.
816 MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 4)));
818 // firstcond[0] and mask
819 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
824 if (Opcode == ARM::tBKPT) {
825 MI.addOperand(MCOperand::CreateImm(getT1Imm8(insn))); // breakpoint value
830 // CPS has a singleton $opt operand that contains the following information:
831 // opt{4-0} = don't care
832 // opt{5} = 0 (false)
833 // opt{8-6} = AIF from Inst{2-0}
834 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
835 if (Opcode == ARM::tCPS) {
836 unsigned Option = slice(insn, 2, 0) << 6 | slice(insn, 4, 4) << 9 | 1 << 10;
837 MI.addOperand(MCOperand::CreateImm(Option));
842 assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
843 (OpInfo[1].RegClass < 0 || OpInfo[1].RegClass==ARM::tGPRRegClassID)
844 && "Expect >=2 operands");
846 // Add the destination operand.
847 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
850 if (OpInfo[1].RegClass == ARM::tGPRRegClassID) {
851 // Two register instructions.
852 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
856 assert((Opcode == ARM::tCBNZ || Opcode == ARM::tCBZ) &&"Unexpected opcode");
857 MI.addOperand(MCOperand::CreateImm(getT1Imm6(insn) * 2));
865 // A8.6.53 LDM / LDMIA
866 // A8.6.189 STM / STMIA
868 // tLDMIA_UPD/tSTMIA_UPD: tRt tRt AM4ModeImm Pred-Imm Pred-CCR register_list
869 // tLDMIA: tRt AM4ModeImm Pred-Imm Pred-CCR register_list
870 static bool DisassembleThumb1LdStMul(bool Ld, MCInst &MI, unsigned Opcode,
871 uint32_t insn, unsigned short NumOps,
872 unsigned &NumOpsAdded, BO B) {
873 assert((Opcode == ARM::tLDMIA || Opcode == ARM::tLDMIA_UPD ||
874 Opcode == ARM::tSTMIA_UPD) && "Unexpected opcode");
876 unsigned tRt = getT1tRt(insn);
879 // WB register, if necessary.
880 if (Opcode == ARM::tLDMIA_UPD || Opcode == ARM::tSTMIA_UPD) {
881 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
886 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
890 // Handling the two predicate operands before the reglist.
891 if (B->DoPredicateOperands(MI, Opcode, insn, NumOps)) {
894 DEBUG(errs() << "Expected predicate operands not found.\n");
898 unsigned RegListBits = slice(insn, 7, 0);
900 // Fill the variadic part of reglist.
901 for (unsigned i = 0; i < 8; ++i)
902 if ((RegListBits >> i) & 1) {
903 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::tGPRRegClassID,
911 static bool DisassembleThumb1LdMul(MCInst &MI, unsigned Opcode, uint32_t insn,
912 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
913 return DisassembleThumb1LdStMul(true, MI, Opcode, insn, NumOps, NumOpsAdded,
917 static bool DisassembleThumb1StMul(MCInst &MI, unsigned Opcode, uint32_t insn,
918 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
919 return DisassembleThumb1LdStMul(false, MI, Opcode, insn, NumOps, NumOpsAdded,
923 // A8.6.16 B Encoding T1
924 // cond = Inst{11-8} & imm8 = Inst{7-0}
925 // imm32 = SignExtend(imm8:'0', 32)
927 // tBcc: offset Pred-Imm Pred-CCR
928 // tSVC: imm8 Pred-Imm Pred-CCR
929 // tTRAP: 0 operand (early return)
930 static bool DisassembleThumb1CondBr(MCInst &MI, unsigned Opcode, uint32_t insn,
931 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
933 if (Opcode == ARM::tTRAP)
936 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
937 if (!OpInfo) return false;
939 assert(NumOps == 3 && OpInfo[0].RegClass < 0 &&
940 OpInfo[1].isPredicate() && OpInfo[2].RegClass == ARM::CCRRegClassID
941 && "Exactly 3 operands expected");
943 unsigned Imm8 = getT1Imm8(insn);
944 MI.addOperand(MCOperand::CreateImm(
945 Opcode == ARM::tBcc ? SignExtend32<9>(Imm8 << 1) + 4
948 // Predicate operands by ARMBasicMCBuilder::TryPredicateAndSBitModifier().
954 // A8.6.16 B Encoding T2
955 // imm11 = Inst{10-0}
956 // imm32 = SignExtend(imm11:'0', 32)
959 static bool DisassembleThumb1Br(MCInst &MI, unsigned Opcode, uint32_t insn,
960 unsigned short NumOps, unsigned &NumOpsAdded, BO) {
962 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
963 if (!OpInfo) return false;
965 assert(NumOps == 1 && OpInfo[0].RegClass < 0 && "1 imm operand expected");
967 unsigned Imm11 = getT1Imm11(insn);
969 // When executing a Thumb instruction, PC reads as the address of the current
970 // instruction plus 4. The assembler subtracts 4 from the difference between
971 // the branch instruction and the target address, disassembler has to add 4 to
973 MI.addOperand(MCOperand::CreateImm(SignExtend32<12>(Imm11 << 1) + 4));
981 // See A6.2 16-bit Thumb instruction encoding for instruction classes
982 // corresponding to op.
984 // Table A6-1 16-bit Thumb instruction encoding (abridged)
985 // op Instruction or instruction class
986 // ------ --------------------------------------------------------------------
987 // 00xxxx Shift (immediate), add, subtract, move, and compare on page A6-7
988 // 010000 Data-processing on page A6-8
989 // 010001 Special data instructions and branch and exchange on page A6-9
990 // 01001x Load from Literal Pool, see LDR (literal) on page A8-122
991 // 0101xx Load/store single data item on page A6-10
994 // 10100x Generate PC-relative address, see ADR on page A8-32
995 // 10101x Generate SP-relative address, see ADD (SP plus immediate) on
997 // 1011xx Miscellaneous 16-bit instructions on page A6-11
998 // 11000x Store multiple registers, see STM / STMIA / STMEA on page A8-374
999 // 11001x Load multiple registers, see LDM / LDMIA / LDMFD on page A8-110 a
1000 // 1101xx Conditional branch, and Supervisor Call on page A6-13
1001 // 11100x Unconditional Branch, see B on page A8-44
1003 static bool DisassembleThumb1(uint16_t op, MCInst &MI, unsigned Opcode,
1004 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1006 unsigned op1 = slice(op, 5, 4);
1007 unsigned op2 = slice(op, 3, 2);
1008 unsigned op3 = slice(op, 1, 0);
1009 unsigned opA = slice(op, 5, 2);
1012 // A6.2.1 Shift (immediate), add, subtract, move, and compare
1013 return DisassembleThumb1General(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1019 // A6.2.2 Data-processing
1020 return DisassembleThumb1DP(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1022 // A6.2.3 Special data instructions and branch and exchange
1023 return DisassembleThumb1Special(MI, Opcode, insn, NumOps, NumOpsAdded,
1026 // A8.6.59 LDR (literal)
1027 return DisassembleThumb1LdPC(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1031 // A6.2.4 Load/store single data item
1032 return DisassembleThumb1LdSt(opA, MI, Opcode, insn, NumOps, NumOpsAdded,
1040 // A6.2.4 Load/store single data item
1041 return DisassembleThumb1LdSt(opA, MI, Opcode, insn, NumOps, NumOpsAdded,
1044 // A6.2.4 Load/store single data item
1045 return DisassembleThumb1LdStSP(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1049 return DisassembleThumb1AddPCi(MI, Opcode, insn, NumOps, NumOpsAdded,
1052 // A8.6.8 ADD (SP plus immediate)
1053 return DisassembleThumb1AddSPi(MI, Opcode, insn, NumOps, NumOpsAdded,
1057 // A6.2.5 Miscellaneous 16-bit instructions
1058 return DisassembleThumb1Misc(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1065 // A8.6.189 STM / STMIA / STMEA
1066 return DisassembleThumb1StMul(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1068 // A8.6.53 LDM / LDMIA / LDMFD
1069 return DisassembleThumb1LdMul(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1072 // A6.2.6 Conditional branch, and Supervisor Call
1073 return DisassembleThumb1CondBr(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1075 // Unconditional Branch, see B on page A8-44
1076 return DisassembleThumb1Br(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1078 assert(0 && "Unreachable code");
1083 assert(0 && "Unreachable code");
1090 ///////////////////////////////////////////////
1092 // Thumb2 instruction disassembly functions. //
1094 ///////////////////////////////////////////////
1096 ///////////////////////////////////////////////////////////
1098 // Note: the register naming follows the ARM convention! //
1100 ///////////////////////////////////////////////////////////
1102 static inline bool Thumb2SRSOpcode(unsigned Opcode) {
1106 case ARM::t2SRSDBW: case ARM::t2SRSDB:
1107 case ARM::t2SRSIAW: case ARM::t2SRSIA:
1112 static inline bool Thumb2RFEOpcode(unsigned Opcode) {
1116 case ARM::t2RFEDBW: case ARM::t2RFEDB:
1117 case ARM::t2RFEIAW: case ARM::t2RFEIA:
1122 // t2SRS[IA|DB]W/t2SRS[IA|DB]: mode_imm = Inst{4-0}
1123 static bool DisassembleThumb2SRS(MCInst &MI, unsigned Opcode, uint32_t insn,
1124 unsigned short NumOps, unsigned &NumOpsAdded) {
1125 MI.addOperand(MCOperand::CreateImm(slice(insn, 4, 0)));
1130 // t2RFE[IA|DB]W/t2RFE[IA|DB]: Rn
1131 static bool DisassembleThumb2RFE(MCInst &MI, unsigned Opcode, uint32_t insn,
1132 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1133 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1139 static bool DisassembleThumb2LdStMul(MCInst &MI, unsigned Opcode, uint32_t insn,
1140 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1142 if (Thumb2SRSOpcode(Opcode))
1143 return DisassembleThumb2SRS(MI, Opcode, insn, NumOps, NumOpsAdded);
1145 if (Thumb2RFEOpcode(Opcode))
1146 return DisassembleThumb2RFE(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1148 assert((Opcode == ARM::t2LDMIA || Opcode == ARM::t2LDMIA_UPD ||
1149 Opcode == ARM::t2LDMDB || Opcode == ARM::t2LDMDB_UPD ||
1150 Opcode == ARM::t2STMIA || Opcode == ARM::t2STMIA_UPD ||
1151 Opcode == ARM::t2STMDB || Opcode == ARM::t2STMDB_UPD)
1152 && "Unexpected opcode");
1153 assert(NumOps >= 5 && "Thumb2 LdStMul expects NumOps >= 5");
1157 unsigned Base = getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn));
1159 // Writeback to base.
1160 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD ||
1161 Opcode == ARM::t2STMIA_UPD || Opcode == ARM::t2STMDB_UPD) {
1162 MI.addOperand(MCOperand::CreateReg(Base));
1166 MI.addOperand(MCOperand::CreateReg(Base));
1169 // Handling the two predicate operands before the reglist.
1170 if (B->DoPredicateOperands(MI, Opcode, insn, NumOps)) {
1173 DEBUG(errs() << "Expected predicate operands not found.\n");
1177 unsigned RegListBits = insn & ((1 << 16) - 1);
1179 // Fill the variadic part of reglist.
1180 for (unsigned i = 0; i < 16; ++i)
1181 if ((RegListBits >> i) & 1) {
1182 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1191 // t2LDREXD: Rd Rs Rn
1192 // t2LDREXB, t2LDREXH: Rd Rn
1193 // t2STREX: Rs Rd Rn
1194 // t2STREXD: Rm Rd Rs Rn
1195 // t2STREXB, t2STREXH: Rm Rd Rn
1196 static bool DisassembleThumb2LdStEx(MCInst &MI, unsigned Opcode, uint32_t insn,
1197 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1199 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1200 if (!OpInfo) return false;
1202 unsigned &OpIdx = NumOpsAdded;
1207 && OpInfo[0].RegClass == ARM::GPRRegClassID
1208 && OpInfo[1].RegClass == ARM::GPRRegClassID
1209 && "Expect >=2 operands and first two as reg operands");
1211 bool isStore = (ARM::t2STREX <= Opcode && Opcode <= ARM::t2STREXH);
1212 bool isSW = (Opcode == ARM::t2LDREX || Opcode == ARM::t2STREX);
1213 bool isDW = (Opcode == ARM::t2LDREXD || Opcode == ARM::t2STREXD);
1215 // Add the destination operand for store.
1217 MI.addOperand(MCOperand::CreateReg(
1218 getRegisterEnum(B, ARM::GPRRegClassID,
1219 isSW ? decodeRs(insn) : decodeRm(insn))));
1223 // Source operand for store and destination operand for load.
1224 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1228 // Thumb2 doubleword complication: with an extra source/destination operand.
1230 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1235 // Finally add the pointer operand.
1236 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1243 // LLVM, as of Jan-05-2010, does not output <Rt2>, i.e., Rs, in the asm.
1244 // Whereas the ARM Arch. Manual does not require that t2 = t+1 like in ARM ISA.
1246 // t2LDRDi8: Rd Rs Rn imm8s4 (offset mode)
1247 // t2LDRDpci: Rd Rs imm8s4 (Not decoded, prefer the generic t2LDRDi8 version)
1248 // t2STRDi8: Rd Rs Rn imm8s4 (offset mode)
1250 // Ditto for t2LDRD_PRE, t2LDRD_POST, t2STRD_PRE, t2STRD_POST, which are for
1251 // disassembly only and do not have a tied_to writeback base register operand.
1252 static bool DisassembleThumb2LdStDual(MCInst &MI, unsigned Opcode,
1253 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1255 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1256 if (!OpInfo) return false;
1259 && OpInfo[0].RegClass == ARM::GPRRegClassID
1260 && OpInfo[1].RegClass == ARM::GPRRegClassID
1261 && OpInfo[2].RegClass == ARM::GPRRegClassID
1262 && OpInfo[3].RegClass < 0
1263 && "Expect >= 4 operands and first 3 as reg operands");
1265 // Add the <Rt> <Rt2> operands.
1266 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1268 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1270 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1273 // Finally add (+/-)imm8*4, depending on the U bit.
1274 int Offset = getImm8(insn) * 4;
1275 if (getUBit(insn) == 0)
1277 MI.addOperand(MCOperand::CreateImm(Offset));
1283 // t2TBB, t2TBH: Rn Rm Pred-Imm Pred-CCR
1284 static bool DisassembleThumb2TB(MCInst &MI, unsigned Opcode,
1285 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1287 assert(NumOps >= 2 && "Expect >= 2 operands");
1289 // The generic version of TBB/TBH needs a base register.
1290 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1292 // Add the index register.
1293 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1300 static inline bool Thumb2ShiftOpcode(unsigned Opcode) {
1304 case ARM::t2MOVCClsl: case ARM::t2MOVCClsr:
1305 case ARM::t2MOVCCasr: case ARM::t2MOVCCror:
1306 case ARM::t2LSLri: case ARM::t2LSRri:
1307 case ARM::t2ASRri: case ARM::t2RORri:
1312 // A6.3.11 Data-processing (shifted register)
1314 // Two register operands (Rn=0b1111 no 1st operand reg): Rs Rm
1315 // Two register operands (Rs=0b1111 no dst operand reg): Rn Rm
1316 // Three register operands: Rs Rn Rm
1317 // Three register operands: (Rn=0b1111 Conditional Move) Rs Ro(TIED_TO) Rm
1319 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
1320 // register with shift forms: (Rm, ConstantShiftSpecifier).
1321 // Constant shift specifier: Imm = (ShOp | ShAmt<<3).
1323 // There are special instructions, like t2MOVsra_flag and t2MOVsrl_flag, which
1324 // only require two register operands: Rd, Rm in ARM Reference Manual terms, and
1325 // nothing else, because the shift amount is already specified.
1326 // Similar case holds for t2MOVrx, t2ADDrr, ..., etc.
1327 static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn,
1328 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1330 const TargetInstrDesc &TID = ARMInsts[Opcode];
1331 const TargetOperandInfo *OpInfo = TID.OpInfo;
1332 unsigned &OpIdx = NumOpsAdded;
1334 // Special case handling.
1335 if (Opcode == ARM::t2BR_JT) {
1337 && OpInfo[0].RegClass == ARM::GPRRegClassID
1338 && OpInfo[1].RegClass == ARM::GPRRegClassID
1339 && OpInfo[2].RegClass < 0
1340 && OpInfo[3].RegClass < 0
1341 && "Exactly 4 operands expect and first two as reg operands");
1342 // Only need to populate the src reg operand.
1343 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1345 MI.addOperand(MCOperand::CreateReg(0));
1346 MI.addOperand(MCOperand::CreateImm(0));
1347 MI.addOperand(MCOperand::CreateImm(0));
1355 && (OpInfo[0].RegClass == ARM::GPRRegClassID ||
1356 OpInfo[0].RegClass == ARM::rGPRRegClassID)
1357 && (OpInfo[1].RegClass == ARM::GPRRegClassID ||
1358 OpInfo[1].RegClass == ARM::rGPRRegClassID)
1359 && "Expect >= 2 operands and first two as reg operands");
1361 bool ThreeReg = (NumOps > 2 && (OpInfo[2].RegClass == ARM::GPRRegClassID ||
1362 OpInfo[2].RegClass == ARM::rGPRRegClassID));
1363 bool NoDstReg = (decodeRs(insn) == 0xF);
1365 // Build the register operands, followed by the constant shift specifier.
1367 MI.addOperand(MCOperand::CreateReg(
1368 getRegisterEnum(B, OpInfo[0].RegClass,
1369 NoDstReg ? decodeRn(insn) : decodeRs(insn))));
1374 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
1375 // Process tied_to operand constraint.
1376 MI.addOperand(MI.getOperand(Idx));
1378 } else if (!NoDstReg) {
1379 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[1].RegClass,
1383 DEBUG(errs() << "Thumb2 encoding error: d==15 for three-reg operands.\n");
1388 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
1392 if (NumOps == OpIdx)
1395 if (OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
1396 && !OpInfo[OpIdx].isOptionalDef()) {
1398 if (Thumb2ShiftOpcode(Opcode))
1399 MI.addOperand(MCOperand::CreateImm(getShiftAmtBits(insn)));
1401 // Build the constant shift specifier operand.
1402 unsigned bits2 = getShiftTypeBits(insn);
1403 unsigned imm5 = getShiftAmtBits(insn);
1404 ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift;
1405 unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp);
1406 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt)));
1414 // A6.3.1 Data-processing (modified immediate)
1416 // Two register operands: Rs Rn ModImm
1417 // One register operands (Rs=0b1111 no explicit dest reg): Rn ModImm
1418 // One register operands (Rn=0b1111 no explicit src reg): Rs ModImm -
1421 // ModImm = ThumbExpandImm(i:imm3:imm8)
1422 static bool DisassembleThumb2DPModImm(MCInst &MI, unsigned Opcode,
1423 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1425 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1426 unsigned &OpIdx = NumOpsAdded;
1430 unsigned RdRegClassID = OpInfo[0].RegClass;
1431 assert(NumOps >= 2 && (RdRegClassID == ARM::GPRRegClassID ||
1432 RdRegClassID == ARM::rGPRRegClassID)
1433 && "Expect >= 2 operands and first one as reg operand");
1435 unsigned RnRegClassID = OpInfo[1].RegClass;
1436 bool TwoReg = (RnRegClassID == ARM::GPRRegClassID
1437 || RnRegClassID == ARM::rGPRRegClassID);
1438 bool NoDstReg = (decodeRs(insn) == 0xF);
1440 // Build the register operands, followed by the modified immediate.
1442 MI.addOperand(MCOperand::CreateReg(
1443 getRegisterEnum(B, RdRegClassID,
1444 NoDstReg ? decodeRn(insn) : decodeRs(insn))));
1449 DEBUG(errs()<<"Thumb2 encoding error: d==15 for DPModImm 2-reg instr.\n");
1452 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
1457 // The modified immediate operand should come next.
1458 assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 &&
1459 !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()
1460 && "Pure imm operand expected");
1463 // A6.3.2 Modified immediate constants in Thumb instructions
1464 unsigned imm12 = getIImm3Imm8(insn);
1465 MI.addOperand(MCOperand::CreateImm(ThumbExpandImm(imm12)));
1471 static inline bool Thumb2SaturateOpcode(unsigned Opcode) {
1473 case ARM::t2SSAT: case ARM::t2SSAT16:
1474 case ARM::t2USAT: case ARM::t2USAT16:
1481 /// DisassembleThumb2Sat - Disassemble Thumb2 saturate instructions:
1482 /// o t2SSAT, t2USAT: Rs sat_pos Rn shamt
1483 /// o t2SSAT16, t2USAT16: Rs sat_pos Rn
1484 static bool DisassembleThumb2Sat(MCInst &MI, unsigned Opcode, uint32_t insn,
1485 unsigned &NumOpsAdded, BO B) {
1486 const TargetInstrDesc &TID = ARMInsts[Opcode];
1487 NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands
1489 // Disassemble the register def.
1490 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
1493 unsigned Pos = slice(insn, 4, 0);
1494 if (Opcode == ARM::t2SSAT || Opcode == ARM::t2SSAT16)
1496 MI.addOperand(MCOperand::CreateImm(Pos));
1498 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
1501 if (NumOpsAdded == 4) {
1502 ARM_AM::ShiftOpc Opc = (slice(insn, 21, 21) != 0 ?
1503 ARM_AM::asr : ARM_AM::lsl);
1504 // Inst{14-12:7-6} encodes the imm5 shift amount.
1505 unsigned ShAmt = slice(insn, 14, 12) << 2 | slice(insn, 7, 6);
1507 if (Opc == ARM_AM::asr)
1510 Opc = ARM_AM::no_shift;
1512 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShAmt)));
1517 // A6.3.3 Data-processing (plain binary immediate)
1519 // o t2ADDri12, t2SUBri12: Rs Rn imm12
1520 // o t2LEApcrel (ADR): Rs imm12
1521 // o t2BFC (BFC): Rs Ro(TIED_TO) bf_inv_mask_imm
1522 // o t2BFI (BFI) (Currently not defined in LLVM as of Jan-07-2010)
1523 // o t2MOVi16: Rs imm16
1524 // o t2MOVTi16: Rs imm16
1525 // o t2SBFX (SBFX): Rs Rn lsb width
1526 // o t2UBFX (UBFX): Rs Rn lsb width
1527 // o t2BFI (BFI): Rs Rn lsb width
1528 static bool DisassembleThumb2DPBinImm(MCInst &MI, unsigned Opcode,
1529 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1531 const TargetInstrDesc &TID = ARMInsts[Opcode];
1532 const TargetOperandInfo *OpInfo = TID.OpInfo;
1533 unsigned &OpIdx = NumOpsAdded;
1537 unsigned RdRegClassID = OpInfo[0].RegClass;
1538 assert(NumOps >= 2 && (RdRegClassID == ARM::GPRRegClassID ||
1539 RdRegClassID == ARM::rGPRRegClassID)
1540 && "Expect >= 2 operands and first one as reg operand");
1542 unsigned RnRegClassID = OpInfo[1].RegClass;
1543 bool TwoReg = (RnRegClassID == ARM::GPRRegClassID
1544 || RnRegClassID == ARM::rGPRRegClassID);
1546 // Build the register operand(s), followed by the immediate(s).
1548 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RdRegClassID,
1553 assert(NumOps >= 3 && "Expect >= 3 operands");
1555 if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
1556 // Process tied_to operand constraint.
1557 MI.addOperand(MI.getOperand(Idx));
1559 // Add src reg operand.
1560 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
1566 if (Opcode == ARM::t2BFI) {
1567 // Add val reg operand.
1568 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, RnRegClassID,
1573 assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
1574 && !OpInfo[OpIdx].isOptionalDef()
1575 && "Pure imm operand expected");
1577 // Pre-increment OpIdx.
1580 if (Opcode == ARM::t2ADDri12 || Opcode == ARM::t2SUBri12
1581 || Opcode == ARM::t2LEApcrel)
1582 MI.addOperand(MCOperand::CreateImm(getIImm3Imm8(insn)));
1583 else if (Opcode == ARM::t2MOVi16 || Opcode == ARM::t2MOVTi16)
1584 MI.addOperand(MCOperand::CreateImm(getImm16(insn)));
1585 else if (Opcode == ARM::t2BFC || Opcode == ARM::t2BFI) {
1587 if (getBitfieldInvMask(insn, mask))
1588 MI.addOperand(MCOperand::CreateImm(mask));
1592 // Handle the case of: lsb width
1593 assert((Opcode == ARM::t2SBFX || Opcode == ARM::t2UBFX)
1594 && "Unexpected opcode");
1595 MI.addOperand(MCOperand::CreateImm(getLsb(insn)));
1596 MI.addOperand(MCOperand::CreateImm(getWidthMinus1(insn) + 1));
1604 // A6.3.4 Table A6-15 Miscellaneous control instructions
1608 static inline bool t2MiscCtrlInstr(uint32_t insn) {
1609 if (slice(insn, 31, 20) == 0xf3b && slice(insn, 15, 14) == 2 &&
1610 slice(insn, 12, 12) == 0)
1616 // A6.3.4 Branches and miscellaneous control
1619 // Branches: t2B, t2Bcc -> imm operand
1621 // Branches: t2TPsoft -> no operand
1623 // A8.6.23 BL, BLX (immediate)
1624 // Branches (defined in ARMInstrThumb.td): tBLr9, tBLXi_r9 -> imm operand
1629 // Miscellaneous control: t2DMBsy (and its t2DMB variants),
1630 // t2DSBsy (and its t2DSB varianst), t2ISBsy, t2CLREX
1631 // -> no operand (except pred-imm pred-ccr for CLREX, memory barrier variants)
1633 // Hint: t2NOP, t2YIELD, t2WFE, t2WFI, t2SEV
1634 // -> no operand (except pred-imm pred-ccr)
1636 // t2DBG -> imm4 = Inst{3-0}
1638 // t2MRS/t2MRSsys -> Rs
1639 // t2MSR/t2MSRsys -> Rn mask=Inst{11-8}
1640 // t2SMC -> imm4 = Inst{19-16}
1641 static bool DisassembleThumb2BrMiscCtrl(MCInst &MI, unsigned Opcode,
1642 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1647 if (t2MiscCtrlInstr(insn))
1662 // CPS has a singleton $opt operand that contains the following information:
1663 // opt{4-0} = mode from Inst{4-0}
1664 // opt{5} = changemode from Inst{8}
1665 // opt{8-6} = AIF from Inst{7-5}
1666 // opt{10-9} = imod from Inst{10-9} with 0b10 as enable and 0b11 as disable
1667 if (Opcode == ARM::t2CPS) {
1668 unsigned Option = slice(insn, 4, 0) | slice(insn, 8, 8) << 5 |
1669 slice(insn, 7, 5) << 6 | slice(insn, 10, 9) << 9;
1670 MI.addOperand(MCOperand::CreateImm(Option));
1675 // DBG has its option specified in Inst{3-0}.
1676 if (Opcode == ARM::t2DBG) {
1677 MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 0)));
1682 // MRS and MRSsys take one GPR reg Rs.
1683 if (Opcode == ARM::t2MRS || Opcode == ARM::t2MRSsys) {
1684 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1689 // BXJ takes one GPR reg Rn.
1690 if (Opcode == ARM::t2BXJ) {
1691 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1696 // MSR and MSRsys take one GPR reg Rn, followed by the mask.
1697 if (Opcode == ARM::t2MSR || Opcode == ARM::t2MSRsys || Opcode == ARM::t2BXJ) {
1698 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1700 MI.addOperand(MCOperand::CreateImm(slice(insn, 11, 8)));
1705 if (Opcode == ARM::t2SMC) {
1706 MI.addOperand(MCOperand::CreateImm(slice(insn, 19, 16)));
1711 // Add the imm operand.
1716 assert(0 && "Unexpected opcode");
1719 Offset = decodeImm32_B_EncodingT4(insn);
1722 Offset = decodeImm32_B_EncodingT3(insn);
1725 Offset = decodeImm32_BL(insn);
1728 Offset = decodeImm32_BLX(insn);
1731 // When executing a Thumb instruction, PC reads as the address of the current
1732 // instruction plus 4. The assembler subtracts 4 from the difference between
1733 // the branch instruction and the target address, disassembler has to add 4 to
1735 MI.addOperand(MCOperand::CreateImm(Offset + 4));
1742 static inline bool Thumb2PreloadOpcode(unsigned Opcode) {
1746 case ARM::t2PLDi12: case ARM::t2PLDi8:
1748 case ARM::t2PLDWi12: case ARM::t2PLDWi8:
1750 case ARM::t2PLIi12: case ARM::t2PLIi8:
1756 static bool DisassembleThumb2PreLoad(MCInst &MI, unsigned Opcode, uint32_t insn,
1757 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1759 // Preload Data/Instruction requires either 2 or 3 operands.
1760 // t2PLDi12, t2PLDi8, t2PLDpci: Rn [+/-]imm12/imm8
1762 // t2PLDs: Rn Rm imm2=Inst{5-4}
1763 // Same pattern applies for t2PLDW* and t2PLI*.
1765 const TargetInstrDesc &TID = ARMInsts[Opcode];
1766 const TargetOperandInfo *OpInfo = TID.OpInfo;
1767 unsigned &OpIdx = NumOpsAdded;
1771 assert(NumOps >= 2 &&
1772 OpInfo[0].RegClass == ARM::GPRRegClassID &&
1773 "Expect >= 2 operands and first one as reg operand");
1775 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1779 if (OpInfo[OpIdx].RegClass == ARM::GPRRegClassID) {
1780 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1783 assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
1784 && !OpInfo[OpIdx].isOptionalDef()
1785 && "Pure imm operand expected");
1787 if (slice(insn, 19, 16) == 0xFF) {
1788 bool Negative = slice(insn, 23, 23) == 0;
1789 unsigned Imm12 = getImm12(insn);
1790 Offset = Negative ? -1 - Imm12 : 1 * Imm12;
1791 } else if (Opcode == ARM::t2PLDi8 || Opcode == ARM::t2PLDWi8 ||
1792 Opcode == ARM::t2PLIi8) {
1793 // A8.6.117 Encoding T2: add = FALSE
1794 unsigned Imm8 = getImm8(insn);
1796 } else // The i12 forms. See, for example, A8.6.117 Encoding T1.
1797 Offset = decodeImm12(insn);
1798 MI.addOperand(MCOperand::CreateImm(Offset));
1802 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0 &&
1803 !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1804 // Fills in the shift amount for t2PLDs, t2PLDWs, t2PLIs.
1805 MI.addOperand(MCOperand::CreateImm(slice(insn, 5, 4)));
1812 // A6.3.10 Store single data item
1813 // A6.3.9 Load byte, memory hints
1814 // A6.3.8 Load halfword, memory hints
1819 // t2LDRi12: Rd Rn (+)imm12
1820 // t2LDRi8: Rd Rn (+/-)imm8 (+ if Inst{9} == 0b1)
1821 // t2LDRs: Rd Rn Rm ConstantShiftSpecifier (see also
1822 // DisassembleThumb2DPSoReg)
1823 // t2LDR_POST: Rd Rn Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
1824 // t2LDR_PRE: Rd Rn Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
1826 // t2STRi12: Rd Rn (+)imm12
1827 // t2STRi8: Rd Rn (+/-)imm8 (+ if Inst{9} == 0b1)
1828 // t2STRs: Rd Rn Rm ConstantShiftSpecifier (see also
1829 // DisassembleThumb2DPSoReg)
1830 // t2STR_POST: Rn Rd Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
1831 // t2STR_PRE: Rn Rd Rn(TIED_TO) (+/-)imm8 (+ if Inst{9} == 0b1)
1833 // Note that for indexed modes, the Rn(TIED_TO) operand needs to be populated
1834 // correctly, as LLVM AsmPrinter depends on it. For indexed stores, the first
1835 // operand is Rn; for all the other instructions, Rd is the first operand.
1837 // Delegates to DisassembleThumb2PreLoad() for preload data/instruction.
1838 // Delegates to DisassembleThumb2Ldpci() for load * literal operations.
1839 static bool DisassembleThumb2LdSt(bool Load, MCInst &MI, unsigned Opcode,
1840 uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1842 unsigned Rn = decodeRn(insn);
1844 if (Thumb2PreloadOpcode(Opcode))
1845 return DisassembleThumb2PreLoad(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1847 // See, for example, A6.3.7 Load word: Table A6-18 Load word.
1848 if (Load && Rn == 15)
1849 return DisassembleThumb2Ldpci(MI, Opcode, insn, NumOps, NumOpsAdded, B);
1850 const TargetInstrDesc &TID = ARMInsts[Opcode];
1851 const TargetOperandInfo *OpInfo = TID.OpInfo;
1852 unsigned &OpIdx = NumOpsAdded;
1856 assert(NumOps >= 3 &&
1857 OpInfo[0].RegClass == ARM::GPRRegClassID &&
1858 OpInfo[1].RegClass == ARM::GPRRegClassID &&
1859 "Expect >= 3 operands and first two as reg operands");
1861 bool ThreeReg = (OpInfo[2].RegClass == ARM::GPRRegClassID);
1862 bool TIED_TO = ThreeReg && TID.getOperandConstraint(2, TOI::TIED_TO) != -1;
1863 bool Imm12 = !ThreeReg && slice(insn, 23, 23) == 1; // ARMInstrThumb2.td
1865 // Build the register operands, followed by the immediate.
1866 unsigned R0, R1, R2 = 0;
1867 unsigned Rd = decodeRd(insn);
1870 if (!Load && TIED_TO) {
1880 Imm = decodeImm8(insn);
1882 R2 = decodeRm(insn);
1883 // See, for example, A8.6.64 LDRB (register).
1884 // And ARMAsmPrinter::printT2AddrModeSoRegOperand().
1885 // LSL is the default shift opc, and LLVM does not expect it to be encoded
1886 // as part of the immediate operand.
1887 // Imm = ARM_AM::getSORegOpc(ARM_AM::lsl, slice(insn, 5, 4));
1888 Imm = slice(insn, 5, 4);
1892 Imm = getImm12(insn);
1894 Imm = decodeImm8(insn);
1897 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1900 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1905 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
1910 assert(OpInfo[OpIdx].RegClass < 0 && !OpInfo[OpIdx].isPredicate()
1911 && !OpInfo[OpIdx].isOptionalDef()
1912 && "Pure imm operand expected");
1914 MI.addOperand(MCOperand::CreateImm(Imm));
1920 // A6.3.12 Data-processing (register)
1922 // Two register operands [rotate]: Rs Rm [rotation(= (rotate:'000'))]
1923 // Three register operands only: Rs Rn Rm
1924 // Three register operands [rotate]: Rs Rn Rm [rotation(= (rotate:'000'))]
1926 // Parallel addition and subtraction 32-bit Thumb instructions: Rs Rn Rm
1928 // Miscellaneous operations: Rs [Rn] Rm
1929 static bool DisassembleThumb2DPReg(MCInst &MI, unsigned Opcode, uint32_t insn,
1930 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1932 const TargetInstrDesc &TID = ARMInsts[Opcode];
1933 const TargetOperandInfo *OpInfo = TID.OpInfo;
1934 unsigned &OpIdx = NumOpsAdded;
1938 assert(NumOps >= 2 &&
1939 OpInfo[0].RegClass == ARM::rGPRRegClassID &&
1940 OpInfo[1].RegClass == ARM::rGPRRegClassID &&
1941 "Expect >= 2 operands and first two as reg operands");
1943 // Build the register operands, followed by the optional rotation amount.
1945 bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::rGPRRegClassID;
1947 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
1952 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
1957 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
1961 if (OpIdx < NumOps && OpInfo[OpIdx].RegClass < 0
1962 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
1963 // Add the rotation amount immediate.
1964 MI.addOperand(MCOperand::CreateImm(decodeRotate(insn)));
1971 // A6.3.16 Multiply, multiply accumulate, and absolute difference
1973 // t2MLA, t2MLS, t2SMMLA, t2SMMLS: Rs Rn Rm Ra=Inst{15-12}
1974 // t2MUL, t2SMMUL: Rs Rn Rm
1975 // t2SMLA[BB|BT|TB|TT|WB|WT]: Rs Rn Rm Ra=Inst{15-12}
1976 // t2SMUL[BB|BT|TB|TT|WB|WT]: Rs Rn Rm
1978 // Dual halfword multiply: t2SMUAD[X], t2SMUSD[X], t2SMLAD[X], t2SMLSD[X]:
1979 // Rs Rn Rm Ra=Inst{15-12}
1981 // Unsigned Sum of Absolute Differences [and Accumulate]
1982 // Rs Rn Rm [Ra=Inst{15-12}]
1983 static bool DisassembleThumb2Mul(MCInst &MI, unsigned Opcode, uint32_t insn,
1984 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
1986 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
1988 assert(NumOps >= 3 &&
1989 OpInfo[0].RegClass == ARM::rGPRRegClassID &&
1990 OpInfo[1].RegClass == ARM::rGPRRegClassID &&
1991 OpInfo[2].RegClass == ARM::rGPRRegClassID &&
1992 "Expect >= 3 operands and first three as reg operands");
1994 // Build the register operands.
1996 bool FourReg = NumOps > 3 && OpInfo[3].RegClass == ARM::rGPRRegClassID;
1998 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2001 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2004 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2008 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2011 NumOpsAdded = FourReg ? 4 : 3;
2016 // A6.3.17 Long multiply, long multiply accumulate, and divide
2018 // t2SMULL, t2UMULL, t2SMLAL, t2UMLAL, t2UMAAL: RdLo RdHi Rn Rm
2019 // where RdLo = Inst{15-12} and RdHi = Inst{11-8}
2021 // Halfword multiple accumulate long: t2SMLAL<x><y>: RdLo RdHi Rn Rm
2022 // where RdLo = Inst{15-12} and RdHi = Inst{11-8}
2024 // Dual halfword multiple: t2SMLALD[X], t2SMLSLD[X]: RdLo RdHi Rn Rm
2025 // where RdLo = Inst{15-12} and RdHi = Inst{11-8}
2027 // Signed/Unsigned divide: t2SDIV, t2UDIV: Rs Rn Rm
2028 static bool DisassembleThumb2LongMul(MCInst &MI, unsigned Opcode, uint32_t insn,
2029 unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
2031 const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
2033 assert(NumOps >= 3 &&
2034 OpInfo[0].RegClass == ARM::rGPRRegClassID &&
2035 OpInfo[1].RegClass == ARM::rGPRRegClassID &&
2036 OpInfo[2].RegClass == ARM::rGPRRegClassID &&
2037 "Expect >= 3 operands and first three as reg operands");
2039 bool FourReg = NumOps > 3 && OpInfo[3].RegClass == ARM::rGPRRegClassID;
2041 // Build the register operands.
2044 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2047 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2050 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2053 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID,
2064 // See A6.3 32-bit Thumb instruction encoding for instruction classes
2065 // corresponding to (op1, op2, op).
2067 // Table A6-9 32-bit Thumb instruction encoding
2068 // op1 op2 op Instruction class, see
2069 // --- ------- -- -----------------------------------------------------------
2070 // 01 00xx0xx - Load/store multiple on page A6-23
2071 // 00xx1xx - Load/store dual, load/store exclusive, table branch on
2073 // 01xxxxx - Data-processing (shifted register) on page A6-31
2074 // 1xxxxxx - Coprocessor instructions on page A6-40
2075 // 10 x0xxxxx 0 Data-processing (modified immediate) on page A6-15
2076 // x1xxxxx 0 Data-processing (plain binary immediate) on page A6-19
2077 // - 1 Branches and miscellaneous control on page A6-20
2078 // 11 000xxx0 - Store single data item on page A6-30
2079 // 001xxx0 - Advanced SIMD element or structure load/store instructions
2081 // 00xx001 - Load byte, memory hints on page A6-28
2082 // 00xx011 - Load halfword, memory hints on page A6-26
2083 // 00xx101 - Load word on page A6-25
2084 // 00xx111 - UNDEFINED
2085 // 010xxxx - Data-processing (register) on page A6-33
2086 // 0110xxx - Multiply, multiply accumulate, and absolute difference on
2088 // 0111xxx - Long multiply, long multiply accumulate, and divide on
2090 // 1xxxxxx - Coprocessor instructions on page A6-40
2092 static bool DisassembleThumb2(uint16_t op1, uint16_t op2, uint16_t op,
2093 MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps,
2094 unsigned &NumOpsAdded, BO B) {
2098 if (slice(op2, 6, 5) == 0) {
2099 if (slice(op2, 2, 2) == 0) {
2100 // Load/store multiple.
2101 return DisassembleThumb2LdStMul(MI, Opcode, insn, NumOps, NumOpsAdded,
2105 // Load/store dual, load/store exclusive, table branch, otherwise.
2106 assert(slice(op2, 2, 2) == 1 && "Thumb2 encoding error!");
2107 if ((ARM::t2LDREX <= Opcode && Opcode <= ARM::t2LDREXH) ||
2108 (ARM::t2STREX <= Opcode && Opcode <= ARM::t2STREXH)) {
2109 // Load/store exclusive.
2110 return DisassembleThumb2LdStEx(MI, Opcode, insn, NumOps, NumOpsAdded,
2113 if (Opcode == ARM::t2LDRDi8 ||
2114 Opcode == ARM::t2LDRD_PRE || Opcode == ARM::t2LDRD_POST ||
2115 Opcode == ARM::t2STRDi8 ||
2116 Opcode == ARM::t2STRD_PRE || Opcode == ARM::t2STRD_POST) {
2118 return DisassembleThumb2LdStDual(MI, Opcode, insn, NumOps, NumOpsAdded,
2121 if (Opcode == ARM::t2TBB || Opcode == ARM::t2TBH) {
2123 return DisassembleThumb2TB(MI, Opcode, insn, NumOps, NumOpsAdded, B);
2125 } else if (slice(op2, 6, 5) == 1) {
2126 // Data-processing (shifted register).
2127 return DisassembleThumb2DPSoReg(MI, Opcode, insn, NumOps, NumOpsAdded, B);
2130 // FIXME: A6.3.18 Coprocessor instructions
2131 // But see ThumbDisassembler::getInstruction().
2136 if (slice(op2, 5, 5) == 0)
2137 // Data-processing (modified immediate)
2138 return DisassembleThumb2DPModImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2140 if (Thumb2SaturateOpcode(Opcode))
2141 return DisassembleThumb2Sat(MI, Opcode, insn, NumOpsAdded, B);
2143 // Data-processing (plain binary immediate)
2144 return DisassembleThumb2DPBinImm(MI, Opcode, insn, NumOps, NumOpsAdded,
2147 // Branches and miscellaneous control on page A6-20.
2148 return DisassembleThumb2BrMiscCtrl(MI, Opcode, insn, NumOps, NumOpsAdded,
2151 switch (slice(op2, 6, 5)) {
2153 // Load/store instructions...
2154 if (slice(op2, 0, 0) == 0) {
2155 if (slice(op2, 4, 4) == 0) {
2156 // Store single data item on page A6-30
2157 return DisassembleThumb2LdSt(false, MI,Opcode,insn,NumOps,NumOpsAdded,
2160 // FIXME: Advanced SIMD element or structure load/store instructions.
2161 // But see ThumbDisassembler::getInstruction().
2165 // Table A6-9 32-bit Thumb instruction encoding: Load byte|halfword|word
2166 return DisassembleThumb2LdSt(true, MI, Opcode, insn, NumOps,
2171 if (slice(op2, 4, 4) == 0) {
2172 // A6.3.12 Data-processing (register)
2173 return DisassembleThumb2DPReg(MI, Opcode, insn, NumOps, NumOpsAdded, B);
2174 } else if (slice(op2, 3, 3) == 0) {
2175 // A6.3.16 Multiply, multiply accumulate, and absolute difference
2176 return DisassembleThumb2Mul(MI, Opcode, insn, NumOps, NumOpsAdded, B);
2178 // A6.3.17 Long multiply, long multiply accumulate, and divide
2179 return DisassembleThumb2LongMul(MI, Opcode, insn, NumOps, NumOpsAdded,
2184 // FIXME: A6.3.18 Coprocessor instructions
2185 // But see ThumbDisassembler::getInstruction().
2192 assert(0 && "Thumb2 encoding error!");
2199 static bool DisassembleThumbFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
2200 unsigned short NumOps, unsigned &NumOpsAdded, BO Builder) {
2202 uint16_t HalfWord = slice(insn, 31, 16);
2204 if (HalfWord == 0) {
2205 // A6.2 16-bit Thumb instruction encoding
2207 uint16_t op = slice(insn, 15, 10);
2208 return DisassembleThumb1(op, MI, Opcode, insn, NumOps, NumOpsAdded,
2212 unsigned bits15_11 = slice(HalfWord, 15, 11);
2214 // A6.1 Thumb instruction set encoding
2215 if (!(bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F)) {
2216 assert("Bits[15:11] first halfword of Thumb2 instruction is out of range");
2220 // A6.3 32-bit Thumb instruction encoding
2222 uint16_t op1 = slice(HalfWord, 12, 11);
2223 uint16_t op2 = slice(HalfWord, 10, 4);
2224 uint16_t op = slice(insn, 15, 15);
2226 return DisassembleThumb2(op1, op2, op, MI, Opcode, insn, NumOps, NumOpsAdded,