1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "ARMDisassembler.h"
14 #include "ARMRegisterInfo.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/EDInstInfo.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/Target/TargetRegistry.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
27 // Forward declare these because the autogenerated code will reference them.
28 // Definitions are further down.
29 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
30 uint64_t Address, const void *Decoder);
31 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
32 uint64_t Address, const void *Decoder);
33 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
34 uint64_t Address, const void *Decoder);
35 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
36 uint64_t Address, const void *Decoder);
37 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
38 uint64_t Address, const void *Decoder);
39 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
40 uint64_t Address, const void *Decoder);
41 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
42 uint64_t Address, const void *Decoder);
43 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
44 uint64_t Address, const void *Decoder);
45 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
46 uint64_t Address, const void *Decoder);
47 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
48 uint64_t Address, const void *Decoder);
50 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
51 uint64_t Address, const void *Decoder);
52 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
53 uint64_t Address, const void *Decoder);
54 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
55 uint64_t Address, const void *Decoder);
56 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
57 uint64_t Address, const void *Decoder);
58 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
59 uint64_t Address, const void *Decoder);
60 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
61 uint64_t Address, const void *Decoder);
62 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
63 uint64_t Address, const void *Decoder);
65 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
66 uint64_t Address, const void *Decoder);
67 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
68 uint64_t Address, const void *Decoder);
69 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
70 uint64_t Address, const void *Decoder);
71 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
72 uint64_t Address, const void *Decoder);
73 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
74 uint64_t Address, const void *Decoder);
75 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
76 uint64_t Address, const void *Decoder);
77 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
78 uint64_t Address, const void *Decoder);
80 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
84 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
85 uint64_t Address, const void *Decoder);
86 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
87 uint64_t Address, const void *Decoder);
88 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
89 uint64_t Address, const void *Decoder);
90 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
91 uint64_t Address, const void *Decoder);
92 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
93 uint64_t Address, const void *Decoder);
94 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
95 uint64_t Address, const void *Decoder);
96 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
97 uint64_t Address, const void *Decoder);
98 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
99 uint64_t Address, const void *Decoder);
100 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
101 uint64_t Address, const void *Decoder);
102 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
103 uint64_t Address, const void *Decoder);
104 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
105 uint64_t Address, const void *Decoder);
106 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
107 uint64_t Address, const void *Decoder);
108 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
109 uint64_t Address, const void *Decoder);
110 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
111 uint64_t Address, const void *Decoder);
112 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val,
113 uint64_t Address, const void *Decoder);
114 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
115 uint64_t Address, const void *Decoder);
116 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
117 uint64_t Address, const void *Decoder);
118 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
119 uint64_t Address, const void *Decoder);
120 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
121 uint64_t Address, const void *Decoder);
122 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
123 uint64_t Address, const void *Decoder);
124 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
125 uint64_t Address, const void *Decoder);
126 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
127 uint64_t Address, const void *Decoder);
128 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
129 uint64_t Address, const void *Decoder);
130 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
131 uint64_t Address, const void *Decoder);
132 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Insn,
133 uint64_t Address, const void *Decoder);
134 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
135 uint64_t Address, const void *Decoder);
136 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
137 uint64_t Address, const void *Decoder);
138 static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
139 uint64_t Address, const void *Decoder);
142 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
143 uint64_t Address, const void *Decoder);
144 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
145 uint64_t Address, const void *Decoder);
146 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
147 uint64_t Address, const void *Decoder);
148 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
149 uint64_t Address, const void *Decoder);
150 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
151 uint64_t Address, const void *Decoder);
152 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
153 uint64_t Address, const void *Decoder);
154 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
155 uint64_t Address, const void *Decoder);
156 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
157 uint64_t Address, const void *Decoder);
158 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
159 uint64_t Address, const void *Decoder);
160 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
161 uint64_t Address, const void *Decoder);
162 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
163 uint64_t Address, const void *Decoder);
164 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
165 uint64_t Address, const void *Decoder);
166 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
167 uint64_t Address, const void *Decoder);
168 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
169 uint64_t Address, const void *Decoder);
170 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
171 uint64_t Address, const void *Decoder);
172 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
173 uint64_t Address, const void *Decoder);
174 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
175 uint64_t Address, const void *Decoder);
176 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
177 uint64_t Address, const void *Decoder);
178 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
179 uint64_t Address, const void *Decoder);
180 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
181 uint64_t Address, const void *Decoder);
182 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
183 uint64_t Address, const void *Decoder);
184 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
185 uint64_t Address, const void *Decoder);
186 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
188 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
191 #include "ARMGenDisassemblerTables.inc"
192 #include "ARMGenInstrInfo.inc"
193 #include "ARMGenEDInfo.inc"
195 using namespace llvm;
197 static MCDisassembler *createARMDisassembler(const Target &T) {
198 return new ARMDisassembler;
201 static MCDisassembler *createThumbDisassembler(const Target &T) {
202 return new ThumbDisassembler;
205 EDInstInfo *ARMDisassembler::getEDInfo() const {
209 EDInstInfo *ThumbDisassembler::getEDInfo() const {
214 bool ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
215 const MemoryObject &Region,
216 uint64_t Address,raw_ostream &os) const {
219 // We want to read exactly 4 bytes of data.
220 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
223 // Encoded as a small-endian 32-bit word in the stream.
224 uint32_t insn = (bytes[3] << 24) |
229 // Calling the auto-generated decoder function.
230 bool result = decodeARMInstruction32(MI, insn, Address, this);
236 // Instructions that are shared between ARM and Thumb modes.
237 // FIXME: This shouldn't really exist. It's an artifact of the
238 // fact that we fail to encode a few instructions properly for Thumb.
240 result = decodeCommonInstruction32(MI, insn, Address, this);
246 // VFP and NEON instructions, similarly, are shared between ARM
249 result = decodeVFPInstruction32(MI, insn, Address, this);
256 result = decodeNEONDataInstruction32(MI, insn, Address, this);
259 // Add a fake predicate operand, because we share these instruction
260 // definitions with Thumb2 where these instructions are predicable.
261 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
266 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
269 // Add a fake predicate operand, because we share these instruction
270 // definitions with Thumb2 where these instructions are predicable.
271 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
276 result = decodeNEONDupInstruction32(MI, insn, Address, this);
279 // Add a fake predicate operand, because we share these instruction
280 // definitions with Thumb2 where these instructions are predicable.
281 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return false;
291 extern MCInstrDesc ARMInsts[];
294 // Thumb1 instructions don't have explicit S bits. Rather, they
295 // implicitly set CPSR. Since it's not represented in the encoding, the
296 // auto-generated decoder won't inject the CPSR operand. We need to fix
297 // that as a post-pass.
298 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
299 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
300 MCInst::iterator I = MI.begin();
301 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) {
302 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
303 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
308 if (OpInfo[MI.size()].isOptionalDef() &&
309 OpInfo[MI.size()].RegClass == ARM::CCRRegClassID)
310 MI.insert(MI.end(), MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
313 // Most Thumb instructions don't have explicit predicates in the
314 // encoding, but rather get their predicates from IT context. We need
315 // to fix up the predicate operands using this context information as a
317 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
318 // A few instructions actually have predicates encoded in them. Don't
319 // try to overwrite it if we're seeing one of those.
320 switch (MI.getOpcode()) {
328 // If we're in an IT block, base the predicate on that. Otherwise,
329 // assume a predicate of AL.
331 if (!ITBlock.empty()) {
337 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
338 MCInst::iterator I = MI.begin();
339 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) {
340 if (OpInfo[i].isPredicate()) {
341 I = MI.insert(I, MCOperand::CreateImm(CC));
344 MI.insert(I, MCOperand::CreateReg(0));
346 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
351 MI.insert(MI.end(), MCOperand::CreateImm(CC));
353 MI.insert(MI.end(), MCOperand::CreateReg(0));
355 MI.insert(MI.end(), MCOperand::CreateReg(ARM::CPSR));
358 // Thumb VFP instructions are a special case. Because we share their
359 // encodings between ARM and Thumb modes, and they are predicable in ARM
360 // mode, the auto-generated decoder will give them an (incorrect)
361 // predicate operand. We need to rewrite these operands based on the IT
362 // context as a post-pass.
363 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
365 if (!ITBlock.empty()) {
371 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
372 MCInst::iterator I = MI.begin();
373 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) {
374 if (OpInfo[i].isPredicate() ) {
380 I->setReg(ARM::CPSR);
387 bool ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
388 const MemoryObject &Region,
389 uint64_t Address,raw_ostream &os) const {
392 // We want to read exactly 2 bytes of data.
393 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
396 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
397 bool result = decodeThumbInstruction16(MI, insn16, Address, this);
400 bool InITBlock = !ITBlock.empty();
401 AddThumbPredicate(MI);
402 AddThumb1SBit(MI, InITBlock);
407 result = decodeThumb2Instruction16(MI, insn16, Address, this);
410 AddThumbPredicate(MI);
412 // If we find an IT instruction, we need to parse its condition
413 // code and mask operands so that we can apply them correctly
414 // to the subsequent instructions.
415 if (MI.getOpcode() == ARM::t2IT) {
416 unsigned firstcond = MI.getOperand(0).getImm();
417 uint32_t mask = MI.getOperand(1).getImm();
418 unsigned zeros = CountTrailingZeros_32(mask);
421 for (unsigned i = 0; i < 4 - (zeros+1); ++i) {
422 if (firstcond ^ (mask & 1))
423 ITBlock.push_back(firstcond ^ 1);
425 ITBlock.push_back(firstcond);
428 ITBlock.push_back(firstcond);
434 // We want to read exactly 4 bytes of data.
435 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
438 uint32_t insn32 = (bytes[3] << 8) |
443 result = decodeThumbInstruction32(MI, insn32, Address, this);
446 bool InITBlock = ITBlock.size();
447 AddThumbPredicate(MI);
448 AddThumb1SBit(MI, InITBlock);
453 result = decodeThumb2Instruction32(MI, insn32, Address, this);
456 AddThumbPredicate(MI);
461 result = decodeCommonInstruction32(MI, insn32, Address, this);
464 AddThumbPredicate(MI);
469 result = decodeVFPInstruction32(MI, insn32, Address, this);
472 UpdateThumbVFPPredicate(MI);
477 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
478 uint32_t NEONDataInsn = insn32;
479 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
480 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
481 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
482 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
485 AddThumbPredicate(MI);
491 result = decodeNEONLoadStoreInstruction32(MI, insn32, Address, this);
494 AddThumbPredicate(MI);
499 result = decodeNEONDupInstruction32(MI, insn32, Address, this);
502 AddThumbPredicate(MI);
510 extern "C" void LLVMInitializeARMDisassembler() {
511 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
512 createARMDisassembler);
513 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
514 createThumbDisassembler);
517 static const unsigned GPRDecoderTable[] = {
518 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
519 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
520 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
521 ARM::R12, ARM::SP, ARM::LR, ARM::PC
524 static bool DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
525 uint64_t Address, const void *Decoder) {
529 unsigned Register = GPRDecoderTable[RegNo];
530 Inst.addOperand(MCOperand::CreateReg(Register));
534 static bool DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
535 uint64_t Address, const void *Decoder) {
536 if (RegNo == 15) return false;
537 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
540 static bool DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
541 uint64_t Address, const void *Decoder) {
544 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
547 static bool DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
548 uint64_t Address, const void *Decoder) {
549 unsigned Register = 0;
573 Inst.addOperand(MCOperand::CreateReg(Register));
577 static bool DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
578 uint64_t Address, const void *Decoder) {
579 if (RegNo == 13 || RegNo == 15) return false;
580 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
583 static const unsigned SPRDecoderTable[] = {
584 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
585 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
586 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
587 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
588 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
589 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
590 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
591 ARM::S28, ARM::S29, ARM::S30, ARM::S31
594 static bool DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
595 uint64_t Address, const void *Decoder) {
599 unsigned Register = SPRDecoderTable[RegNo];
600 Inst.addOperand(MCOperand::CreateReg(Register));
604 static const unsigned DPRDecoderTable[] = {
605 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
606 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
607 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
608 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
609 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
610 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
611 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
612 ARM::D28, ARM::D29, ARM::D30, ARM::D31
615 static bool DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
616 uint64_t Address, const void *Decoder) {
620 unsigned Register = DPRDecoderTable[RegNo];
621 Inst.addOperand(MCOperand::CreateReg(Register));
625 static bool DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
626 uint64_t Address, const void *Decoder) {
629 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
632 static bool DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
633 uint64_t Address, const void *Decoder) {
636 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
639 static const unsigned QPRDecoderTable[] = {
640 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
641 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
642 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
643 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
647 static bool DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
648 uint64_t Address, const void *Decoder) {
653 unsigned Register = QPRDecoderTable[RegNo];
654 Inst.addOperand(MCOperand::CreateReg(Register));
658 static bool DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
659 uint64_t Address, const void *Decoder) {
660 if (Val == 0xF) return false;
661 // AL predicate is not allowed on Thumb1 branches.
662 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
664 Inst.addOperand(MCOperand::CreateImm(Val));
665 if (Val == ARMCC::AL) {
666 Inst.addOperand(MCOperand::CreateReg(0));
668 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
672 static bool DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
673 uint64_t Address, const void *Decoder) {
675 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
677 Inst.addOperand(MCOperand::CreateReg(0));
681 static bool DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
682 uint64_t Address, const void *Decoder) {
683 uint32_t imm = Val & 0xFF;
684 uint32_t rot = (Val & 0xF00) >> 7;
685 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
686 Inst.addOperand(MCOperand::CreateImm(rot_imm));
690 static bool DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
691 uint64_t Address, const void *Decoder) {
693 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
697 static bool DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
698 uint64_t Address, const void *Decoder) {
700 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
701 unsigned type = fieldFromInstruction32(Val, 5, 2);
702 unsigned imm = fieldFromInstruction32(Val, 7, 5);
704 // Register-immediate
705 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
707 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
723 if (Shift == ARM_AM::ror && imm == 0)
726 unsigned Op = Shift | (imm << 3);
727 Inst.addOperand(MCOperand::CreateImm(Op));
732 static bool DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
733 uint64_t Address, const void *Decoder) {
735 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
736 unsigned type = fieldFromInstruction32(Val, 5, 2);
737 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
740 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
741 if (!DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)) return false;
743 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
759 Inst.addOperand(MCOperand::CreateImm(Shift));
764 static bool DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
765 uint64_t Address, const void *Decoder) {
766 // Empty register lists are not allowed.
767 if (CountPopulation_32(Val) == 0) return false;
768 for (unsigned i = 0; i < 16; ++i) {
769 if (Val & (1 << i)) {
770 if (!DecodeGPRRegisterClass(Inst, i, Address, Decoder)) return false;
777 static bool DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
778 uint64_t Address, const void *Decoder) {
779 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
780 unsigned regs = Val & 0xFF;
782 if (!DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)) return false;
783 for (unsigned i = 0; i < (regs - 1); ++i) {
784 if (!DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false;
790 static bool DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
791 uint64_t Address, const void *Decoder) {
792 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
793 unsigned regs = (Val & 0xFF) / 2;
795 if (!DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)) return false;
796 for (unsigned i = 0; i < (regs - 1); ++i) {
797 if (!DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)) return false;
803 static bool DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
804 uint64_t Address, const void *Decoder) {
805 // This operand encodes a mask of contiguous zeros between a specified MSB
806 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
807 // the mask of all bits LSB-and-lower, and then xor them to create
808 // the mask of that's all ones on [msb, lsb]. Finally we not it to
809 // create the final mask.
810 unsigned msb = fieldFromInstruction32(Val, 5, 5);
811 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
812 uint32_t msb_mask = (1 << (msb+1)) - 1;
813 uint32_t lsb_mask = (1 << lsb) - 1;
814 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
818 static bool DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
819 uint64_t Address, const void *Decoder) {
820 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
821 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
822 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
823 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
824 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
825 unsigned U = fieldFromInstruction32(Insn, 23, 1);
827 switch (Inst.getOpcode()) {
828 case ARM::LDC_OFFSET:
831 case ARM::LDC_OPTION:
832 case ARM::LDCL_OFFSET:
835 case ARM::LDCL_OPTION:
836 case ARM::STC_OFFSET:
839 case ARM::STC_OPTION:
840 case ARM::STCL_OFFSET:
843 case ARM::STCL_OPTION:
844 if (coproc == 0xA || coproc == 0xB)
851 Inst.addOperand(MCOperand::CreateImm(coproc));
852 Inst.addOperand(MCOperand::CreateImm(CRd));
853 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
854 switch (Inst.getOpcode()) {
855 case ARM::LDC_OPTION:
856 case ARM::LDCL_OPTION:
857 case ARM::LDC2_OPTION:
858 case ARM::LDC2L_OPTION:
859 case ARM::STC_OPTION:
860 case ARM::STCL_OPTION:
861 case ARM::STC2_OPTION:
862 case ARM::STC2L_OPTION:
867 Inst.addOperand(MCOperand::CreateReg(0));
871 unsigned P = fieldFromInstruction32(Insn, 24, 1);
872 unsigned W = fieldFromInstruction32(Insn, 21, 1);
874 bool writeback = (P == 0) || (W == 1);
875 unsigned idx_mode = 0;
877 idx_mode = ARMII::IndexModePre;
878 else if (!P && writeback)
879 idx_mode = ARMII::IndexModePost;
881 switch (Inst.getOpcode()) {
885 case ARM::LDC_OPTION:
886 case ARM::LDCL_OPTION:
887 case ARM::LDC2_OPTION:
888 case ARM::LDC2L_OPTION:
889 case ARM::STC_OPTION:
890 case ARM::STCL_OPTION:
891 case ARM::STC2_OPTION:
892 case ARM::STC2L_OPTION:
893 Inst.addOperand(MCOperand::CreateImm(imm));
897 Inst.addOperand(MCOperand::CreateImm(
898 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
900 Inst.addOperand(MCOperand::CreateImm(
901 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
905 switch (Inst.getOpcode()) {
906 case ARM::LDC_OFFSET:
909 case ARM::LDC_OPTION:
910 case ARM::LDCL_OFFSET:
913 case ARM::LDCL_OPTION:
914 case ARM::STC_OFFSET:
917 case ARM::STC_OPTION:
918 case ARM::STCL_OFFSET:
921 case ARM::STCL_OPTION:
922 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
931 static bool DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
932 uint64_t Address, const void *Decoder) {
933 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
934 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
935 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
936 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
937 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
938 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
939 unsigned P = fieldFromInstruction32(Insn, 24, 1);
940 unsigned W = fieldFromInstruction32(Insn, 21, 1);
942 // On stores, the writeback operand precedes Rt.
943 switch (Inst.getOpcode()) {
944 case ARM::STR_POST_IMM:
945 case ARM::STR_POST_REG:
946 case ARM::STRB_POST_IMM:
947 case ARM::STRB_POST_REG:
950 case ARM::STRBT_POST_REG:
951 case ARM::STRBT_POST_IMM:
952 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
958 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
960 // On loads, the writeback operand comes after Rt.
961 switch (Inst.getOpcode()) {
962 case ARM::LDR_POST_IMM:
963 case ARM::LDR_POST_REG:
964 case ARM::LDRB_POST_IMM:
965 case ARM::LDRB_POST_REG:
967 case ARM::LDRBT_POST_REG:
968 case ARM::LDRBT_POST_IMM:
969 case ARM::LDRT_POST_REG:
970 case ARM::LDRT_POST_IMM:
971 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
978 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
980 ARM_AM::AddrOpc Op = ARM_AM::add;
981 if (!fieldFromInstruction32(Insn, 23, 1))
984 bool writeback = (P == 0) || (W == 1);
985 unsigned idx_mode = 0;
987 idx_mode = ARMII::IndexModePre;
988 else if (!P && writeback)
989 idx_mode = ARMII::IndexModePost;
991 if (writeback && (Rn == 15 || Rn == Rt)) return false; // UNPREDICTABLE
994 if (!DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)) return false;
995 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
996 switch( fieldFromInstruction32(Insn, 5, 2)) {
1012 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1013 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1015 Inst.addOperand(MCOperand::CreateImm(imm));
1017 Inst.addOperand(MCOperand::CreateReg(0));
1018 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1019 Inst.addOperand(MCOperand::CreateImm(tmp));
1022 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
1027 static bool DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1028 uint64_t Address, const void *Decoder) {
1029 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1030 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1031 unsigned type = fieldFromInstruction32(Val, 5, 2);
1032 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1033 unsigned U = fieldFromInstruction32(Val, 12, 1);
1035 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1051 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
1052 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
1055 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1057 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1058 Inst.addOperand(MCOperand::CreateImm(shift));
1063 static bool DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1064 uint64_t Address, const void *Decoder) {
1065 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1066 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1067 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1068 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1069 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1070 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1071 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1072 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1073 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1075 bool writeback = (W == 1) | (P == 0);
1076 if (writeback) { // Writeback
1078 U |= ARMII::IndexModePre << 9;
1080 U |= ARMII::IndexModePost << 9;
1082 // On stores, the writeback operand precedes Rt.
1083 switch (Inst.getOpcode()) {
1086 case ARM::STRD_POST:
1087 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
1095 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))
1097 switch (Inst.getOpcode()) {
1100 case ARM::STRD_POST:
1103 case ARM::LDRD_POST:
1104 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))
1112 // On loads, the writeback operand comes after Rt.
1113 switch (Inst.getOpcode()) {
1116 case ARM::LDRD_POST:
1119 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
1127 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
1131 Inst.addOperand(MCOperand::CreateReg(0));
1132 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1134 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
1136 Inst.addOperand(MCOperand::CreateImm(U));
1139 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
1144 static bool DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1145 uint64_t Address, const void *Decoder) {
1146 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1147 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1164 Inst.addOperand(MCOperand::CreateImm(mode));
1165 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
1170 static bool DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1172 uint64_t Address, const void *Decoder) {
1173 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1174 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1175 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1178 switch (Inst.getOpcode()) {
1180 Inst.setOpcode(ARM::RFEDA);
1182 case ARM::STMDA_UPD:
1183 Inst.setOpcode(ARM::RFEDA_UPD);
1186 Inst.setOpcode(ARM::RFEDB);
1188 case ARM::STMDB_UPD:
1189 Inst.setOpcode(ARM::RFEDB_UPD);
1192 Inst.setOpcode(ARM::RFEIA);
1194 case ARM::STMIA_UPD:
1195 Inst.setOpcode(ARM::RFEIA_UPD);
1198 Inst.setOpcode(ARM::RFEIB);
1200 case ARM::STMIB_UPD:
1201 Inst.setOpcode(ARM::RFEIB_UPD);
1204 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1207 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
1208 !DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) || // Tied
1209 !DecodePredicateOperand(Inst, pred, Address, Decoder) ||
1210 !DecodeRegListOperand(Inst, reglist, Address, Decoder))
1216 static bool DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1217 uint64_t Address, const void *Decoder) {
1218 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1219 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1220 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1221 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1223 // imod == '01' --> UNPREDICTABLE
1224 if (imod == 1) return false;
1226 if (M && mode && imod && iflags) {
1227 Inst.setOpcode(ARM::CPS3p);
1228 Inst.addOperand(MCOperand::CreateImm(imod));
1229 Inst.addOperand(MCOperand::CreateImm(iflags));
1230 Inst.addOperand(MCOperand::CreateImm(mode));
1232 } else if (!mode && !M) {
1233 Inst.setOpcode(ARM::CPS2p);
1234 Inst.addOperand(MCOperand::CreateImm(imod));
1235 Inst.addOperand(MCOperand::CreateImm(iflags));
1237 } else if (!imod && !iflags && M) {
1238 Inst.setOpcode(ARM::CPS1p);
1239 Inst.addOperand(MCOperand::CreateImm(mode));
1246 static bool DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1247 uint64_t Address, const void *Decoder) {
1248 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1249 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1250 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1251 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1252 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1255 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1257 if (!DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder) ||
1258 !DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder) ||
1259 !DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder) ||
1260 !DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))
1266 static bool DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1267 uint64_t Address, const void *Decoder) {
1268 unsigned add = fieldFromInstruction32(Val, 12, 1);
1269 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1270 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1272 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
1275 if (!add) imm *= -1;
1276 if (imm == 0 && !add) imm = INT32_MIN;
1277 Inst.addOperand(MCOperand::CreateImm(imm));
1282 static bool DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1283 uint64_t Address, const void *Decoder) {
1284 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1285 unsigned U = fieldFromInstruction32(Val, 8, 1);
1286 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1288 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))
1292 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1294 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1299 static bool DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1300 uint64_t Address, const void *Decoder) {
1301 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1304 static bool DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1305 uint64_t Address, const void *Decoder) {
1306 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1307 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1310 Inst.setOpcode(ARM::BLXi);
1311 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1312 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1316 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1317 if (!DecodePredicateOperand(Inst, pred, Address, Decoder)) return false;
1323 static bool DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1324 uint64_t Address, const void *Decoder) {
1325 Inst.addOperand(MCOperand::CreateImm(64 - Val));
1329 static bool DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1330 uint64_t Address, const void *Decoder) {
1331 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1332 unsigned align = fieldFromInstruction32(Val, 4, 2);
1334 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
1337 Inst.addOperand(MCOperand::CreateImm(0));
1339 Inst.addOperand(MCOperand::CreateImm(4 << align));
1344 static bool DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1345 uint64_t Address, const void *Decoder) {
1346 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1347 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1348 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1349 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1350 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1351 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1353 // First output register
1354 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
1356 // Second output register
1357 switch (Inst.getOpcode()) {
1362 case ARM::VLD1q8_UPD:
1363 case ARM::VLD1q16_UPD:
1364 case ARM::VLD1q32_UPD:
1365 case ARM::VLD1q64_UPD:
1370 case ARM::VLD1d8T_UPD:
1371 case ARM::VLD1d16T_UPD:
1372 case ARM::VLD1d32T_UPD:
1373 case ARM::VLD1d64T_UPD:
1378 case ARM::VLD1d8Q_UPD:
1379 case ARM::VLD1d16Q_UPD:
1380 case ARM::VLD1d32Q_UPD:
1381 case ARM::VLD1d64Q_UPD:
1385 case ARM::VLD2d8_UPD:
1386 case ARM::VLD2d16_UPD:
1387 case ARM::VLD2d32_UPD:
1391 case ARM::VLD2q8_UPD:
1392 case ARM::VLD2q16_UPD:
1393 case ARM::VLD2q32_UPD:
1397 case ARM::VLD3d8_UPD:
1398 case ARM::VLD3d16_UPD:
1399 case ARM::VLD3d32_UPD:
1403 case ARM::VLD4d8_UPD:
1404 case ARM::VLD4d16_UPD:
1405 case ARM::VLD4d32_UPD:
1406 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false;
1411 case ARM::VLD2b8_UPD:
1412 case ARM::VLD2b16_UPD:
1413 case ARM::VLD2b32_UPD:
1417 case ARM::VLD3q8_UPD:
1418 case ARM::VLD3q16_UPD:
1419 case ARM::VLD3q32_UPD:
1423 case ARM::VLD4q8_UPD:
1424 case ARM::VLD4q16_UPD:
1425 case ARM::VLD4q32_UPD:
1426 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
1431 // Third output register
1432 switch(Inst.getOpcode()) {
1437 case ARM::VLD1d8T_UPD:
1438 case ARM::VLD1d16T_UPD:
1439 case ARM::VLD1d32T_UPD:
1440 case ARM::VLD1d64T_UPD:
1445 case ARM::VLD1d8Q_UPD:
1446 case ARM::VLD1d16Q_UPD:
1447 case ARM::VLD1d32Q_UPD:
1448 case ARM::VLD1d64Q_UPD:
1452 case ARM::VLD2q8_UPD:
1453 case ARM::VLD2q16_UPD:
1454 case ARM::VLD2q32_UPD:
1458 case ARM::VLD3d8_UPD:
1459 case ARM::VLD3d16_UPD:
1460 case ARM::VLD3d32_UPD:
1464 case ARM::VLD4d8_UPD:
1465 case ARM::VLD4d16_UPD:
1466 case ARM::VLD4d32_UPD:
1467 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
1472 case ARM::VLD3q8_UPD:
1473 case ARM::VLD3q16_UPD:
1474 case ARM::VLD3q32_UPD:
1478 case ARM::VLD4q8_UPD:
1479 case ARM::VLD4q16_UPD:
1480 case ARM::VLD4q32_UPD:
1481 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false;
1487 // Fourth output register
1488 switch (Inst.getOpcode()) {
1493 case ARM::VLD1d8Q_UPD:
1494 case ARM::VLD1d16Q_UPD:
1495 case ARM::VLD1d32Q_UPD:
1496 case ARM::VLD1d64Q_UPD:
1500 case ARM::VLD2q8_UPD:
1501 case ARM::VLD2q16_UPD:
1502 case ARM::VLD2q32_UPD:
1506 case ARM::VLD4d8_UPD:
1507 case ARM::VLD4d16_UPD:
1508 case ARM::VLD4d32_UPD:
1509 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false;
1514 case ARM::VLD4q8_UPD:
1515 case ARM::VLD4q16_UPD:
1516 case ARM::VLD4q32_UPD:
1517 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false;
1523 // Writeback operand
1524 switch (Inst.getOpcode()) {
1525 case ARM::VLD1d8_UPD:
1526 case ARM::VLD1d16_UPD:
1527 case ARM::VLD1d32_UPD:
1528 case ARM::VLD1d64_UPD:
1529 case ARM::VLD1q8_UPD:
1530 case ARM::VLD1q16_UPD:
1531 case ARM::VLD1q32_UPD:
1532 case ARM::VLD1q64_UPD:
1533 case ARM::VLD1d8T_UPD:
1534 case ARM::VLD1d16T_UPD:
1535 case ARM::VLD1d32T_UPD:
1536 case ARM::VLD1d64T_UPD:
1537 case ARM::VLD1d8Q_UPD:
1538 case ARM::VLD1d16Q_UPD:
1539 case ARM::VLD1d32Q_UPD:
1540 case ARM::VLD1d64Q_UPD:
1541 case ARM::VLD2d8_UPD:
1542 case ARM::VLD2d16_UPD:
1543 case ARM::VLD2d32_UPD:
1544 case ARM::VLD2q8_UPD:
1545 case ARM::VLD2q16_UPD:
1546 case ARM::VLD2q32_UPD:
1547 case ARM::VLD2b8_UPD:
1548 case ARM::VLD2b16_UPD:
1549 case ARM::VLD2b32_UPD:
1550 case ARM::VLD3d8_UPD:
1551 case ARM::VLD3d16_UPD:
1552 case ARM::VLD3d32_UPD:
1553 case ARM::VLD3q8_UPD:
1554 case ARM::VLD3q16_UPD:
1555 case ARM::VLD3q32_UPD:
1556 case ARM::VLD4d8_UPD:
1557 case ARM::VLD4d16_UPD:
1558 case ARM::VLD4d32_UPD:
1559 case ARM::VLD4q8_UPD:
1560 case ARM::VLD4q16_UPD:
1561 case ARM::VLD4q32_UPD:
1562 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder)) return false;
1568 // AddrMode6 Base (register+alignment)
1569 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false;
1571 // AddrMode6 Offset (register)
1573 Inst.addOperand(MCOperand::CreateReg(0));
1574 else if (Rm != 0xF) {
1575 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))
1582 static bool DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
1583 uint64_t Address, const void *Decoder) {
1584 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1585 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1586 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1587 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1588 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1589 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1591 // Writeback Operand
1592 switch (Inst.getOpcode()) {
1593 case ARM::VST1d8_UPD:
1594 case ARM::VST1d16_UPD:
1595 case ARM::VST1d32_UPD:
1596 case ARM::VST1d64_UPD:
1597 case ARM::VST1q8_UPD:
1598 case ARM::VST1q16_UPD:
1599 case ARM::VST1q32_UPD:
1600 case ARM::VST1q64_UPD:
1601 case ARM::VST1d8T_UPD:
1602 case ARM::VST1d16T_UPD:
1603 case ARM::VST1d32T_UPD:
1604 case ARM::VST1d64T_UPD:
1605 case ARM::VST1d8Q_UPD:
1606 case ARM::VST1d16Q_UPD:
1607 case ARM::VST1d32Q_UPD:
1608 case ARM::VST1d64Q_UPD:
1609 case ARM::VST2d8_UPD:
1610 case ARM::VST2d16_UPD:
1611 case ARM::VST2d32_UPD:
1612 case ARM::VST2q8_UPD:
1613 case ARM::VST2q16_UPD:
1614 case ARM::VST2q32_UPD:
1615 case ARM::VST2b8_UPD:
1616 case ARM::VST2b16_UPD:
1617 case ARM::VST2b32_UPD:
1618 case ARM::VST3d8_UPD:
1619 case ARM::VST3d16_UPD:
1620 case ARM::VST3d32_UPD:
1621 case ARM::VST3q8_UPD:
1622 case ARM::VST3q16_UPD:
1623 case ARM::VST3q32_UPD:
1624 case ARM::VST4d8_UPD:
1625 case ARM::VST4d16_UPD:
1626 case ARM::VST4d32_UPD:
1627 case ARM::VST4q8_UPD:
1628 case ARM::VST4q16_UPD:
1629 case ARM::VST4q32_UPD:
1630 if (!DecodeGPRRegisterClass(Inst, wb, Address, Decoder))
1637 // AddrMode6 Base (register+alignment)
1638 if (!DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)) return false;
1640 // AddrMode6 Offset (register)
1642 Inst.addOperand(MCOperand::CreateReg(0));
1643 else if (Rm != 0xF) {
1644 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
1647 // First input register
1648 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
1650 // Second input register
1651 switch (Inst.getOpcode()) {
1656 case ARM::VST1q8_UPD:
1657 case ARM::VST1q16_UPD:
1658 case ARM::VST1q32_UPD:
1659 case ARM::VST1q64_UPD:
1664 case ARM::VST1d8T_UPD:
1665 case ARM::VST1d16T_UPD:
1666 case ARM::VST1d32T_UPD:
1667 case ARM::VST1d64T_UPD:
1672 case ARM::VST1d8Q_UPD:
1673 case ARM::VST1d16Q_UPD:
1674 case ARM::VST1d32Q_UPD:
1675 case ARM::VST1d64Q_UPD:
1679 case ARM::VST2d8_UPD:
1680 case ARM::VST2d16_UPD:
1681 case ARM::VST2d32_UPD:
1685 case ARM::VST2q8_UPD:
1686 case ARM::VST2q16_UPD:
1687 case ARM::VST2q32_UPD:
1691 case ARM::VST3d8_UPD:
1692 case ARM::VST3d16_UPD:
1693 case ARM::VST3d32_UPD:
1697 case ARM::VST4d8_UPD:
1698 case ARM::VST4d16_UPD:
1699 case ARM::VST4d32_UPD:
1700 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false;
1705 case ARM::VST2b8_UPD:
1706 case ARM::VST2b16_UPD:
1707 case ARM::VST2b32_UPD:
1711 case ARM::VST3q8_UPD:
1712 case ARM::VST3q16_UPD:
1713 case ARM::VST3q32_UPD:
1717 case ARM::VST4q8_UPD:
1718 case ARM::VST4q16_UPD:
1719 case ARM::VST4q32_UPD:
1720 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
1726 // Third input register
1727 switch (Inst.getOpcode()) {
1732 case ARM::VST1d8T_UPD:
1733 case ARM::VST1d16T_UPD:
1734 case ARM::VST1d32T_UPD:
1735 case ARM::VST1d64T_UPD:
1740 case ARM::VST1d8Q_UPD:
1741 case ARM::VST1d16Q_UPD:
1742 case ARM::VST1d32Q_UPD:
1743 case ARM::VST1d64Q_UPD:
1747 case ARM::VST2q8_UPD:
1748 case ARM::VST2q16_UPD:
1749 case ARM::VST2q32_UPD:
1753 case ARM::VST3d8_UPD:
1754 case ARM::VST3d16_UPD:
1755 case ARM::VST3d32_UPD:
1759 case ARM::VST4d8_UPD:
1760 case ARM::VST4d16_UPD:
1761 case ARM::VST4d32_UPD:
1762 if (!DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)) return false;
1767 case ARM::VST3q8_UPD:
1768 case ARM::VST3q16_UPD:
1769 case ARM::VST3q32_UPD:
1773 case ARM::VST4q8_UPD:
1774 case ARM::VST4q16_UPD:
1775 case ARM::VST4q32_UPD:
1776 if (!DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)) return false;
1782 // Fourth input register
1783 switch (Inst.getOpcode()) {
1788 case ARM::VST1d8Q_UPD:
1789 case ARM::VST1d16Q_UPD:
1790 case ARM::VST1d32Q_UPD:
1791 case ARM::VST1d64Q_UPD:
1795 case ARM::VST2q8_UPD:
1796 case ARM::VST2q16_UPD:
1797 case ARM::VST2q32_UPD:
1801 case ARM::VST4d8_UPD:
1802 case ARM::VST4d16_UPD:
1803 case ARM::VST4d32_UPD:
1804 if (!DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)) return false;
1809 case ARM::VST4q8_UPD:
1810 case ARM::VST4q16_UPD:
1811 case ARM::VST4q32_UPD:
1812 if (!DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)) return false;
1821 static bool DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
1822 uint64_t Address, const void *Decoder) {
1823 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1824 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1825 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1826 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1827 unsigned align = fieldFromInstruction32(Insn, 4, 1);
1828 unsigned size = fieldFromInstruction32(Insn, 6, 2);
1829 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
1831 align *= (1 << size);
1833 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
1835 if (!DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)) return false;
1838 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
1841 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
1842 Inst.addOperand(MCOperand::CreateImm(align));
1845 Inst.addOperand(MCOperand::CreateReg(0));
1846 else if (Rm != 0xF) {
1847 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
1853 static bool DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
1854 uint64_t Address, const void *Decoder) {
1855 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1856 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1857 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1858 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1859 unsigned align = fieldFromInstruction32(Insn, 4, 1);
1860 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
1861 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
1864 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
1865 if (!DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)) return false;
1867 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
1870 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
1871 Inst.addOperand(MCOperand::CreateImm(align));
1874 Inst.addOperand(MCOperand::CreateReg(0));
1875 else if (Rm != 0xF) {
1876 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
1882 static bool DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
1883 uint64_t Address, const void *Decoder) {
1884 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1885 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1886 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1887 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1888 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
1890 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) ||
1891 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) ||
1892 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))
1895 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
1898 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
1899 Inst.addOperand(MCOperand::CreateImm(0));
1902 Inst.addOperand(MCOperand::CreateReg(0));
1903 else if (Rm != 0xF) {
1904 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
1910 static bool DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
1911 uint64_t Address, const void *Decoder) {
1912 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1913 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1914 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1915 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1916 unsigned size = fieldFromInstruction32(Insn, 6, 2);
1917 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
1918 unsigned align = fieldFromInstruction32(Insn, 4, 1);
1933 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder) ||
1934 !DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder) ||
1935 !DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder) ||
1936 !DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))
1939 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
1942 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
1943 Inst.addOperand(MCOperand::CreateImm(align));
1946 Inst.addOperand(MCOperand::CreateReg(0));
1947 else if (Rm != 0xF) {
1948 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
1954 static bool DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1955 uint64_t Address, const void *Decoder) {
1956 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1957 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1958 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
1959 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
1960 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
1961 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
1962 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
1963 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
1966 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
1968 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
1971 Inst.addOperand(MCOperand::CreateImm(imm));
1973 switch (Inst.getOpcode()) {
1974 case ARM::VORRiv4i16:
1975 case ARM::VORRiv2i32:
1976 case ARM::VBICiv4i16:
1977 case ARM::VBICiv2i32:
1978 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
1980 case ARM::VORRiv8i16:
1981 case ARM::VORRiv4i32:
1982 case ARM::VBICiv8i16:
1983 case ARM::VBICiv4i32:
1984 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
1993 static bool DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
1994 uint64_t Address, const void *Decoder) {
1995 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1996 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1997 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1998 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
1999 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2001 if (!DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
2002 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
2003 Inst.addOperand(MCOperand::CreateImm(8 << size));
2008 static bool DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2009 uint64_t Address, const void *Decoder) {
2010 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2014 static bool DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2015 uint64_t Address, const void *Decoder) {
2016 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2020 static bool DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2021 uint64_t Address, const void *Decoder) {
2022 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2026 static bool DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2027 uint64_t Address, const void *Decoder) {
2028 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2032 static bool DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2033 uint64_t Address, const void *Decoder) {
2034 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2035 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2036 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2037 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2038 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2039 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2040 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2041 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2043 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
2045 if (!DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)) return false; // Writeback
2048 for (unsigned i = 0; i < length; ++i) {
2049 if (!DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)) return false;
2052 if (!DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
2057 static bool DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
2058 uint64_t Address, const void *Decoder) {
2059 // The immediate needs to be a fully instantiated float. However, the
2060 // auto-generated decoder is only able to fill in some of the bits
2061 // necessary. For instance, the 'b' bit is replicated multiple times,
2062 // and is even present in inverted form in one bit. We do a little
2063 // binary parsing here to fill in those missing bits, and then
2064 // reinterpret it all as a float.
2070 fp_conv.integer = Val;
2071 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2072 fp_conv.integer |= b << 26;
2073 fp_conv.integer |= b << 27;
2074 fp_conv.integer |= b << 28;
2075 fp_conv.integer |= b << 29;
2076 fp_conv.integer |= (~b & 0x1) << 30;
2078 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
2082 static bool DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2083 uint64_t Address, const void *Decoder) {
2084 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2085 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2087 if (!DecodetGPRRegisterClass(Inst, dst, Address, Decoder)) return false;
2089 if (Inst.getOpcode() == ARM::tADR)
2090 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2091 else if (Inst.getOpcode() == ARM::tADDrSPi)
2092 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2096 Inst.addOperand(MCOperand::CreateImm(imm));
2100 static bool DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2101 uint64_t Address, const void *Decoder) {
2102 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2106 static bool DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2107 uint64_t Address, const void *Decoder) {
2108 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2112 static bool DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2113 uint64_t Address, const void *Decoder) {
2114 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2118 static bool DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2119 uint64_t Address, const void *Decoder) {
2120 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2121 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2123 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder) ||
2124 !DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))
2130 static bool DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2131 uint64_t Address, const void *Decoder) {
2132 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2133 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2135 if (!DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
2136 Inst.addOperand(MCOperand::CreateImm(imm));
2141 static bool DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2142 uint64_t Address, const void *Decoder) {
2143 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2148 static bool DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2149 uint64_t Address, const void *Decoder) {
2150 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2151 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2156 static bool DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2157 uint64_t Address, const void *Decoder) {
2158 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2159 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2160 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2162 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
2163 !DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))
2165 Inst.addOperand(MCOperand::CreateImm(imm));
2170 static bool DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2171 uint64_t Address, const void *Decoder) {
2172 if (Inst.getOpcode() != ARM::t2PLDs) {
2173 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2174 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
2177 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2179 switch (Inst.getOpcode()) {
2181 Inst.setOpcode(ARM::t2LDRBpci);
2184 Inst.setOpcode(ARM::t2LDRHpci);
2187 Inst.setOpcode(ARM::t2LDRSHpci);
2190 Inst.setOpcode(ARM::t2LDRSBpci);
2193 Inst.setOpcode(ARM::t2PLDi12);
2194 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2200 int imm = fieldFromInstruction32(Insn, 0, 12);
2201 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2202 Inst.addOperand(MCOperand::CreateImm(imm));
2207 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2208 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2209 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2210 DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder);
2215 static bool DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2216 uint64_t Address, const void *Decoder) {
2217 int imm = Val & 0xFF;
2218 if (!(Val & 0x100)) imm *= -1;
2219 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2224 static bool DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2225 uint64_t Address, const void *Decoder) {
2226 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2227 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2229 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
2230 !DecodeT2Imm8S4(Inst, imm, Address, Decoder))
2236 static bool DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2237 uint64_t Address, const void *Decoder) {
2238 int imm = Val & 0xFF;
2239 if (!(Val & 0x100)) imm *= -1;
2240 Inst.addOperand(MCOperand::CreateImm(imm));
2246 static bool DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2247 uint64_t Address, const void *Decoder) {
2248 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2249 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2251 // Some instructions always use an additive offset.
2252 switch (Inst.getOpcode()) {
2264 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder) ||
2265 !DecodeT2Imm8(Inst, imm, Address, Decoder))
2272 static bool DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2273 uint64_t Address, const void *Decoder) {
2274 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2275 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2277 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;
2278 Inst.addOperand(MCOperand::CreateImm(imm));
2284 static bool DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2285 uint64_t Address, const void *Decoder) {
2286 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2288 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2289 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2290 Inst.addOperand(MCOperand::CreateImm(imm));
2295 static bool DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
2296 uint64_t Address, const void *Decoder) {
2297 if (Inst.getOpcode() == ARM::tADDrSP) {
2298 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2299 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2301 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false;
2302 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2303 if (!DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)) return false;
2304 } else if (Inst.getOpcode() == ARM::tADDspr) {
2305 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2307 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2308 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2309 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
2315 static bool DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
2316 uint64_t Address, const void *Decoder) {
2317 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2318 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2320 Inst.addOperand(MCOperand::CreateImm(imod));
2321 Inst.addOperand(MCOperand::CreateImm(flags));
2326 static bool DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
2327 uint64_t Address, const void *Decoder) {
2328 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2329 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2331 if (!DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) return false;
2332 Inst.addOperand(MCOperand::CreateImm(add));
2337 static bool DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
2338 uint64_t Address, const void *Decoder) {
2339 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2343 static bool DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
2344 uint64_t Address, const void *Decoder) {
2345 if (Val == 0xA || Val == 0xB)
2348 Inst.addOperand(MCOperand::CreateImm(Val));
2352 static bool DecodeThumbSRImm(llvm::MCInst &Inst, unsigned Val,
2353 uint64_t Address, const void *Decoder) {
2355 Inst.addOperand(MCOperand::CreateImm(32));
2357 Inst.addOperand(MCOperand::CreateImm(Val));
2361 static bool DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2362 uint64_t Address, const void *Decoder) {
2363 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2364 if (pred == 0xE || pred == 0xF) {
2365 unsigned opc = fieldFromInstruction32(Insn, 4, 2);
2370 Inst.setOpcode(ARM::t2DSB);
2373 Inst.setOpcode(ARM::t2DMB);
2376 Inst.setOpcode(ARM::t2ISB);
2380 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2381 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
2384 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2385 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2386 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2387 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2388 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2390 if (!DecodeT2BROperand(Inst, brtarget, Address, Decoder) ||
2391 !DecodePredicateOperand(Inst, pred, Address, Decoder))
2397 // Decode a shifted immediate operand. These basically consist
2398 // of an 8-bit value, and a 4-bit directive that specifies either
2399 // a splat operation or a rotation.
2400 static bool DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
2401 uint64_t Address, const void *Decoder) {
2402 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2404 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2405 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2408 Inst.addOperand(MCOperand::CreateImm(imm));
2411 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2414 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2417 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2422 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2423 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2424 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2425 Inst.addOperand(MCOperand::CreateImm(imm));
2431 static bool DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2432 uint64_t Address, const void *Decoder){
2433 Inst.addOperand(MCOperand::CreateImm(Val << 1));
2437 static bool DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
2438 uint64_t Address, const void *Decoder){
2439 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2443 static bool DecodeAddrMode3Offset(llvm::MCInst &Inst, unsigned Val,
2444 uint64_t Address, const void *Decoder) {
2445 bool isImm = fieldFromInstruction32(Val, 9, 1);
2446 bool isAdd = fieldFromInstruction32(Val, 8, 1);
2447 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2450 if (!DecodeGPRRegisterClass(Inst, imm, Address, Decoder)) return false;
2451 Inst.addOperand(MCOperand::CreateImm(!isAdd << 8));
2453 Inst.addOperand(MCOperand::CreateReg(0));
2454 Inst.addOperand(MCOperand::CreateImm(imm | (!isAdd << 8)));
2460 static bool DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
2461 uint64_t Address, const void *Decoder) {
2476 Inst.addOperand(MCOperand::CreateImm(Val));
2480 static bool DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
2481 uint64_t Address, const void *Decoder) {
2482 if (!Val) return false;
2483 Inst.addOperand(MCOperand::CreateImm(Val));
2487 static bool DecodeDoubleRegExclusive(llvm::MCInst &Inst, unsigned Insn,
2488 uint64_t Address, const void *Decoder) {
2489 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2490 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2491 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2493 if (Inst.getOpcode() == ARM::STREXD)
2494 if (!DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)) return false;
2496 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return false;
2497 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return false;
2499 if (!DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)) return false;
2500 if (!DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)) return false;
2501 if (!DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)) return false;