1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the ARM Disassembler.
11 // It contains code to implement the public interfaces of ARMDisassembler and
12 // ThumbDisassembler, both of which are instances of MCDisassembler.
14 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "arm-disassembler"
18 #include "ARMDisassembler.h"
19 #include "ARMDisassemblerCore.h"
21 #include "llvm/MC/EDInstInfo.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/Target/TargetRegistry.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/MemoryObject.h"
26 #include "llvm/Support/ErrorHandling.h"
27 #include "llvm/Support/raw_ostream.h"
29 //#define DEBUG(X) do { X; } while (0)
31 /// ARMGenDecoderTables.inc - ARMDecoderTables.inc is tblgen'ed from
32 /// ARMDecoderEmitter.cpp TableGen backend. It contains:
34 /// o Mappings from opcode to ARM/Thumb instruction format
36 /// o static uint16_t decodeInstruction(uint32_t insn) - the decoding function
37 /// for an ARM instruction.
39 /// o static uint16_t decodeThumbInstruction(field_t insn) - the decoding
40 /// function for a Thumb instruction.
42 #include "ARMGenDecoderTables.inc"
44 #include "ARMGenEDInfo.inc"
48 /// showBitVector - Use the raw_ostream to log a diagnostic message describing
49 /// the inidividual bits of the instruction.
51 static inline void showBitVector(raw_ostream &os, const uint32_t &insn) {
52 // Split the bit position markers into more than one lines to fit 80 columns.
53 os << " 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11"
54 << " 10 9 8 7 6 5 4 3 2 1 0 \n";
55 os << "---------------------------------------------------------------"
56 << "----------------------------------\n";
58 for (unsigned i = 32; i != 0; --i) {
59 if (insn >> (i - 1) & 0x01)
63 os << (i%4 == 1 ? '|' : ':');
66 // Split the bit position markers into more than one lines to fit 80 columns.
67 os << "---------------------------------------------------------------"
68 << "----------------------------------\n";
72 /// decodeARMInstruction is a decorator function which tries special cases of
73 /// instruction matching before calling the auto-generated decoder function.
74 static unsigned decodeARMInstruction(uint32_t &insn) {
75 if (slice(insn, 31, 28) == 15)
76 goto AutoGenedDecoder;
78 // Special case processing, if any, goes here....
80 // LLVM combines the offset mode of A8.6.197 & A8.6.198 into STRB.
81 // The insufficient encoding information of the combined instruction confuses
82 // the decoder wrt BFC/BFI. Therefore, we try to recover here.
83 // For BFC, Inst{27-21} = 0b0111110 & Inst{6-0} = 0b0011111.
84 // For BFI, Inst{27-21} = 0b0111110 & Inst{6-4} = 0b001 & Inst{3-0} =! 0b1111.
85 if (slice(insn, 27, 21) == 0x3e && slice(insn, 6, 4) == 1) {
86 if (slice(insn, 3, 0) == 15)
92 // Ditto for STRBT, which is a super-instruction for A8.6.199 Encodings
94 // As a result, the decoder fails to deocode USAT properly.
95 if (slice(insn, 27, 21) == 0x37 && slice(insn, 5, 4) == 1)
98 // Ditto for ADDSrs, which is a super-instruction for A8.6.7 & A8.6.8.
99 // As a result, the decoder fails to decode UMULL properly.
100 if (slice(insn, 27, 21) == 0x04 && slice(insn, 7, 4) == 9) {
104 // Ditto for STR_PRE, which is a super-instruction for A8.6.194 & A8.6.195.
105 // As a result, the decoder fails to decode SBFX properly.
106 if (slice(insn, 27, 21) == 0x3d && slice(insn, 6, 4) == 5)
109 // And STRB_PRE, which is a super-instruction for A8.6.197 & A8.6.198.
110 // As a result, the decoder fails to decode UBFX properly.
111 if (slice(insn, 27, 21) == 0x3f && slice(insn, 6, 4) == 5)
114 // Ditto for STRT, which is a super-instruction for A8.6.210 Encoding A1 & A2.
115 // As a result, the decoder fails to deocode SSAT properly.
116 if (slice(insn, 27, 21) == 0x35 && slice(insn, 5, 4) == 1)
119 // Ditto for RSCrs, which is a super-instruction for A8.6.146 & A8.6.147.
120 // As a result, the decoder fails to decode STRHT/LDRHT/LDRSHT/LDRSBT.
121 if (slice(insn, 27, 24) == 0) {
122 switch (slice(insn, 21, 20)) {
124 switch (slice(insn, 7, 4)) {
128 break; // fallthrough
132 switch (slice(insn, 7, 4)) {
140 break; // fallthrough
144 break; // fallthrough
148 // Ditto for SBCrs, which is a super-instruction for A8.6.152 & A8.6.153.
149 // As a result, the decoder fails to decode STRH_Post/LDRD_POST/STRD_POST
151 if (slice(insn, 27, 25) == 0 && slice(insn, 20, 20) == 0) {
152 unsigned PW = slice(insn, 24, 24) << 1 | slice(insn, 21, 21);
153 switch (slice(insn, 7, 4)) {
158 case 3: // Pre-indexed
159 return ARM::STRH_PRE;
160 case 0: // Post-indexed
161 return ARM::STRH_POST;
163 break; // fallthrough
170 case 3: // Pre-indexed
171 return ARM::LDRD_PRE;
172 case 0: // Post-indexed
173 return ARM::LDRD_POST;
175 break; // fallthrough
182 case 3: // Pre-indexed
183 return ARM::STRD_PRE;
184 case 0: // Post-indexed
185 return ARM::STRD_POST;
187 break; // fallthrough
191 break; // fallthrough
195 // Ditto for SBCSSrs, which is a super-instruction for A8.6.152 & A8.6.153.
196 // As a result, the decoder fails to decode LDRH_POST/LDRSB_POST/LDRSH_POST
198 if (slice(insn, 27, 25) == 0 && slice(insn, 20, 20) == 1) {
199 unsigned PW = slice(insn, 24, 24) << 1 | slice(insn, 21, 21);
200 switch (slice(insn, 7, 4)) {
205 case 3: // Pre-indexed
206 return ARM::LDRH_PRE;
207 case 0: // Post-indexed
208 return ARM::LDRH_POST;
210 break; // fallthrough
217 case 3: // Pre-indexed
218 return ARM::LDRSB_PRE;
219 case 0: // Post-indexed
220 return ARM::LDRSB_POST;
222 break; // fallthrough
229 case 3: // Pre-indexed
230 return ARM::LDRSH_PRE;
231 case 0: // Post-indexed
232 return ARM::LDRSH_POST;
234 break; // fallthrough
238 break; // fallthrough
243 // Calling the auto-generated decoder function.
244 return decodeInstruction(insn);
247 // Helper function for special case handling of LDR (literal) and friends.
248 // See, for example, A6.3.7 Load word: Table A6-18 Load word.
249 // See A8.6.57 T3, T4 & A8.6.60 T2 and friends for why we morphed the opcode
250 // before returning it.
251 static unsigned T2Morph2LoadLiteral(unsigned Opcode) {
254 return Opcode; // Return unmorphed opcode.
256 case ARM::t2LDR_POST: case ARM::t2LDR_PRE:
257 case ARM::t2LDRi12: case ARM::t2LDRi8:
258 case ARM::t2LDRs: case ARM::t2LDRT:
259 return ARM::t2LDRpci;
261 case ARM::t2LDRB_POST: case ARM::t2LDRB_PRE:
262 case ARM::t2LDRBi12: case ARM::t2LDRBi8:
263 case ARM::t2LDRBs: case ARM::t2LDRBT:
264 return ARM::t2LDRBpci;
266 case ARM::t2LDRH_POST: case ARM::t2LDRH_PRE:
267 case ARM::t2LDRHi12: case ARM::t2LDRHi8:
268 case ARM::t2LDRHs: case ARM::t2LDRHT:
269 return ARM::t2LDRHpci;
271 case ARM::t2LDRSB_POST: case ARM::t2LDRSB_PRE:
272 case ARM::t2LDRSBi12: case ARM::t2LDRSBi8:
273 case ARM::t2LDRSBs: case ARM::t2LDRSBT:
274 return ARM::t2LDRSBpci;
276 case ARM::t2LDRSH_POST: case ARM::t2LDRSH_PRE:
277 case ARM::t2LDRSHi12: case ARM::t2LDRSHi8:
278 case ARM::t2LDRSHs: case ARM::t2LDRSHT:
279 return ARM::t2LDRSHpci;
283 /// decodeThumbSideEffect is a decorator function which can potentially twiddle
284 /// the instruction or morph the returned opcode under Thumb2.
286 /// First it checks whether the insn is a NEON or VFP instr; if true, bit
287 /// twiddling could be performed on insn to turn it into an ARM NEON/VFP
288 /// equivalent instruction and decodeInstruction is called with the transformed
291 /// Next, there is special handling for Load byte/halfword/word instruction by
292 /// checking whether Rn=0b1111 and call T2Morph2LoadLiteral() on the decoded
293 /// Thumb2 instruction. See comments below for further details.
295 /// Finally, one last check is made to see whether the insn is a NEON/VFP and
296 /// decodeInstruction(insn) is invoked on the original insn.
298 /// Otherwise, decodeThumbInstruction is called with the original insn.
299 static unsigned decodeThumbSideEffect(bool IsThumb2, unsigned &insn) {
301 uint16_t op1 = slice(insn, 28, 27);
302 uint16_t op2 = slice(insn, 26, 20);
304 // A6.3 32-bit Thumb instruction encoding
305 // Table A6-9 32-bit Thumb instruction encoding
307 // The coprocessor instructions of interest are transformed to their ARM
310 // --------- Transform Begin Marker ---------
311 if ((op1 == 1 || op1 == 3) && slice(op2, 6, 4) == 7) {
312 // A7.4 Advanced SIMD data-processing instructions
313 // U bit of Thumb corresponds to Inst{24} of ARM.
314 uint16_t U = slice(op1, 1, 1);
316 // Inst{28-24} of ARM = {1,0,0,1,U};
317 uint16_t bits28_24 = 9 << 1 | U;
318 DEBUG(showBitVector(errs(), insn));
319 setSlice(insn, 28, 24, bits28_24);
320 return decodeInstruction(insn);
323 if (op1 == 3 && slice(op2, 6, 4) == 1 && slice(op2, 0, 0) == 0) {
324 // A7.7 Advanced SIMD element or structure load/store instructions
325 // Inst{27-24} of Thumb = 0b1001
326 // Inst{27-24} of ARM = 0b0100
327 DEBUG(showBitVector(errs(), insn));
328 setSlice(insn, 27, 24, 4);
329 return decodeInstruction(insn);
331 // --------- Transform End Marker ---------
333 // See, for example, A6.3.7 Load word: Table A6-18 Load word.
334 // See A8.6.57 T3, T4 & A8.6.60 T2 and friends for why we morphed the opcode
335 // before returning it to our caller.
336 if (op1 == 3 && slice(op2, 6, 5) == 0 && slice(op2, 0, 0) == 1
337 && slice(insn, 19, 16) == 15)
338 return T2Morph2LoadLiteral(decodeThumbInstruction(insn));
340 // One last check for NEON/VFP instructions.
341 if ((op1 == 1 || op1 == 3) && slice(op2, 6, 6) == 1)
342 return decodeInstruction(insn);
347 return decodeThumbInstruction(insn);
351 // Public interface for the disassembler
354 bool ARMDisassembler::getInstruction(MCInst &MI,
356 const MemoryObject &Region,
358 raw_ostream &os) const {
359 // The machine instruction.
363 // We want to read exactly 4 bytes of data.
364 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
367 // Encoded as a small-endian 32-bit word in the stream.
368 insn = (bytes[3] << 24) |
373 unsigned Opcode = decodeARMInstruction(insn);
374 ARMFormat Format = ARMFormats[Opcode];
378 errs() << "Opcode=" << Opcode << " Name=" << ARMUtils::OpcodeName(Opcode)
379 << " Format=" << stringForARMFormat(Format) << '(' << (int)Format
381 showBitVector(errs(), insn);
384 ARMBasicMCBuilder *Builder = CreateMCBuilder(Opcode, Format);
388 if (!Builder->Build(MI, insn))
396 bool ThumbDisassembler::getInstruction(MCInst &MI,
398 const MemoryObject &Region,
400 raw_ostream &os) const {
401 // The Thumb instruction stream is a sequence of halhwords.
403 // This represents the first halfword as well as the machine instruction
404 // passed to decodeThumbInstruction(). For 16-bit Thumb instruction, the top
405 // halfword of insn is 0x00 0x00; otherwise, the first halfword is moved to
406 // the top half followed by the second halfword.
408 // Possible second halfword.
411 // A6.1 Thumb instruction set encoding
413 // If bits [15:11] of the halfword being decoded take any of the following
414 // values, the halfword is the first halfword of a 32-bit instruction:
419 // Otherwise, the halfword is a 16-bit instruction.
421 // Read 2 bytes of data first.
423 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
426 // Encoded as a small-endian 16-bit halfword in the stream.
427 insn = (bytes[1] << 8) | bytes[0];
428 unsigned bits15_11 = slice(insn, 15, 11);
429 bool IsThumb2 = false;
431 // 32-bit instructions if the bits [15:11] of the halfword matches
432 // { 0b11101 /* 0x1D */, 0b11110 /* 0x1E */, ob11111 /* 0x1F */ }.
433 if (bits15_11 == 0x1D || bits15_11 == 0x1E || bits15_11 == 0x1F) {
435 if (Region.readBytes(Address + 2, 2, (uint8_t*)bytes, NULL) == -1)
437 // Encoded as a small-endian 16-bit halfword in the stream.
438 insn1 = (bytes[1] << 8) | bytes[0];
439 insn = (insn << 16 | insn1);
442 // The insn could potentially be bit-twiddled in order to be decoded as an ARM
443 // NEON/VFP opcode. In such case, the modified insn is later disassembled as
444 // an ARM NEON/VFP instruction.
446 // This is a short term solution for lack of encoding bits specified for the
447 // Thumb2 NEON/VFP instructions. The long term solution could be adding some
448 // infrastructure to have each instruction support more than one encodings.
449 // Which encoding is used would be based on which subtarget the compiler/
450 // disassembler is working with at the time. This would allow the sharing of
451 // the NEON patterns between ARM and Thumb2, as well as potential greater
452 // sharing between the regular ARM instructions and the 32-bit wide Thumb2
453 // instructions as well.
454 unsigned Opcode = decodeThumbSideEffect(IsThumb2, insn);
456 ARMFormat Format = ARMFormats[Opcode];
457 Size = IsThumb2 ? 4 : 2;
460 errs() << "Opcode=" << Opcode << " Name=" << ARMUtils::OpcodeName(Opcode)
461 << " Format=" << stringForARMFormat(Format) << '(' << (int)Format
463 showBitVector(errs(), insn);
466 ARMBasicMCBuilder *Builder = CreateMCBuilder(Opcode, Format);
470 Builder->SetSession(const_cast<Session *>(&SO));
472 if (!Builder->Build(MI, insn))
481 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
482 static unsigned short CountITSize(unsigned ITMask) {
483 // First count the trailing zeros of the IT mask.
484 unsigned TZ = CountTrailingZeros_32(ITMask);
486 DEBUG(errs() << "Encoding error: IT Mask '0000'");
492 /// Init ITState. Note that at least one bit is always 1 in mask.
493 bool Session::InitIT(unsigned short bits7_0) {
494 ITCounter = CountITSize(slice(bits7_0, 3, 0));
499 unsigned short FirstCond = slice(bits7_0, 7, 4);
500 if (FirstCond == 0xF) {
501 DEBUG(errs() << "Encoding error: IT FirstCond '1111'");
504 if (FirstCond == 0xE && ITCounter != 1) {
505 DEBUG(errs() << "Encoding error: IT FirstCond '1110' && Mask != '1000'");
514 /// Update ITState if necessary.
515 void Session::UpdateIT() {
521 unsigned short NewITState4_0 = slice(ITState, 4, 0) << 1;
522 setSlice(ITState, 4, 0, NewITState4_0);
526 static MCDisassembler *createARMDisassembler(const Target &T) {
527 return new ARMDisassembler;
530 static MCDisassembler *createThumbDisassembler(const Target &T) {
531 return new ThumbDisassembler;
534 extern "C" void LLVMInitializeARMDisassembler() {
535 // Register the disassembler.
536 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
537 createARMDisassembler);
538 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
539 createThumbDisassembler);
542 EDInstInfo *ARMDisassembler::getEDInfo() const {
546 EDInstInfo *ThumbDisassembler::getEDInfo() const {