1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "llvm/MC/EDInstInfo.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/MC/MCInstrDesc.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCDisassembler.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/TargetRegistry.h"
26 #include "llvm/Support/raw_ostream.h"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 // Handles the condition code status of instructions in IT blocks
38 // Returns the condition code for instruction in IT block
40 unsigned CC = ARMCC::AL;
46 // Advances the IT block state to the next T or E
47 void advanceITState() {
51 // Returns true if the current instruction is in an IT block
52 bool instrInITBlock() {
53 return !ITStates.empty();
56 // Returns true if current instruction is the last instruction in an IT block
57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
61 // Called when decoding an IT instruction. Sets the IT state for the following
62 // instructions that for the IT block. Firstcond and Mask correspond to the
63 // fields in the IT instruction encoding.
64 void setITState(char Firstcond, char Mask) {
65 // (3 - the number of trailing zeros) is the number of then / else.
66 unsigned CondBit0 = Firstcond & 1;
67 unsigned NumTZ = CountTrailingZeros_32(Mask);
68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 && "Invalid IT mask!");
70 // push condition codes onto the stack the correct order for the pops
71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 ITStates.push_back(CCBits);
76 ITStates.push_back(CCBits ^ 1);
78 ITStates.push_back(CCBits);
82 std::vector<unsigned char> ITStates;
87 /// ARMDisassembler - ARM disassembler for all ARM platforms.
88 class ARMDisassembler : public MCDisassembler {
90 /// Constructor - Initializes the disassembler.
92 ARMDisassembler(const MCSubtargetInfo &STI) :
99 /// getInstruction - See MCDisassembler.
100 DecodeStatus getInstruction(MCInst &instr,
102 const MemoryObject ®ion,
104 raw_ostream &vStream,
105 raw_ostream &cStream) const;
107 /// getEDInfo - See MCDisassembler.
108 const EDInstInfo *getEDInfo() const;
112 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
113 class ThumbDisassembler : public MCDisassembler {
115 /// Constructor - Initializes the disassembler.
117 ThumbDisassembler(const MCSubtargetInfo &STI) :
118 MCDisassembler(STI) {
121 ~ThumbDisassembler() {
124 /// getInstruction - See MCDisassembler.
125 DecodeStatus getInstruction(MCInst &instr,
127 const MemoryObject ®ion,
129 raw_ostream &vStream,
130 raw_ostream &cStream) const;
132 /// getEDInfo - See MCDisassembler.
133 const EDInstInfo *getEDInfo() const;
135 mutable ITStatus ITBlock;
136 DecodeStatus AddThumbPredicate(MCInst&) const;
137 void UpdateThumbVFPPredicate(MCInst&) const;
141 static bool Check(DecodeStatus &Out, DecodeStatus In) {
143 case MCDisassembler::Success:
144 // Out stays the same.
146 case MCDisassembler::SoftFail:
149 case MCDisassembler::Fail:
153 llvm_unreachable("Invalid DecodeStatus!");
157 // Forward declare these because the autogenerated code will reference them.
158 // Definitions are further down.
159 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
162 unsigned RegNo, uint64_t Address,
163 const void *Decoder);
164 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
179 const void *Decoder);
180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
185 unsigned RegNo, uint64_t Address,
186 const void *Decoder);
188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
208 const void *Decoder);
209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
221 const void *Decoder);
222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
351 uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
382 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
384 uint64_t Address, const void *Decoder);
385 #include "ARMGenDisassemblerTables.inc"
386 #include "ARMGenInstrInfo.inc"
387 #include "ARMGenEDInfo.inc"
389 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
390 return new ARMDisassembler(STI);
393 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
394 return new ThumbDisassembler(STI);
397 const EDInstInfo *ARMDisassembler::getEDInfo() const {
401 const EDInstInfo *ThumbDisassembler::getEDInfo() const {
405 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
406 const MemoryObject &Region,
409 raw_ostream &cs) const {
414 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
415 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
417 // We want to read exactly 4 bytes of data.
418 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
420 return MCDisassembler::Fail;
423 // Encoded as a small-endian 32-bit word in the stream.
424 uint32_t insn = (bytes[3] << 24) |
429 // Calling the auto-generated decoder function.
430 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
431 if (result != MCDisassembler::Fail) {
436 // VFP and NEON instructions, similarly, are shared between ARM
439 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
440 if (result != MCDisassembler::Fail) {
446 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
447 if (result != MCDisassembler::Fail) {
449 // Add a fake predicate operand, because we share these instruction
450 // definitions with Thumb2 where these instructions are predicable.
451 if (!DecodePredicateOperand(MI, 0xE, Address, this))
452 return MCDisassembler::Fail;
457 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
458 if (result != MCDisassembler::Fail) {
460 // Add a fake predicate operand, because we share these instruction
461 // definitions with Thumb2 where these instructions are predicable.
462 if (!DecodePredicateOperand(MI, 0xE, Address, this))
463 return MCDisassembler::Fail;
468 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
469 if (result != MCDisassembler::Fail) {
471 // Add a fake predicate operand, because we share these instruction
472 // definitions with Thumb2 where these instructions are predicable.
473 if (!DecodePredicateOperand(MI, 0xE, Address, this))
474 return MCDisassembler::Fail;
481 return MCDisassembler::Fail;
485 extern const MCInstrDesc ARMInsts[];
488 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
489 /// immediate Value in the MCInst. The immediate Value has had any PC
490 /// adjustment made by the caller. If the instruction is a branch instruction
491 /// then isBranch is true, else false. If the getOpInfo() function was set as
492 /// part of the setupForSymbolicDisassembly() call then that function is called
493 /// to get any symbolic information at the Address for this instruction. If
494 /// that returns non-zero then the symbolic information it returns is used to
495 /// create an MCExpr and that is added as an operand to the MCInst. If
496 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
497 /// Value is done and if a symbol is found an MCExpr is created with that, else
498 /// an MCExpr with Value is created. This function returns true if it adds an
499 /// operand to the MCInst and false otherwise.
500 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
501 bool isBranch, uint64_t InstSize,
502 MCInst &MI, const void *Decoder) {
503 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
504 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
505 struct LLVMOpInfo1 SymbolicOp;
506 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
507 SymbolicOp.Value = Value;
508 void *DisInfo = Dis->getDisInfoBlock();
511 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
512 // Clear SymbolicOp.Value from above and also all other fields.
513 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
514 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
517 uint64_t ReferenceType;
519 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
521 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
522 const char *ReferenceName;
523 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
526 SymbolicOp.AddSymbol.Name = Name;
527 SymbolicOp.AddSymbol.Present = true;
529 // For branches always create an MCExpr so it gets printed as hex address.
531 SymbolicOp.Value = Value;
533 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
534 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
535 if (!Name && !isBranch)
539 MCContext *Ctx = Dis->getMCContext();
540 const MCExpr *Add = NULL;
541 if (SymbolicOp.AddSymbol.Present) {
542 if (SymbolicOp.AddSymbol.Name) {
543 StringRef Name(SymbolicOp.AddSymbol.Name);
544 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
545 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
547 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
551 const MCExpr *Sub = NULL;
552 if (SymbolicOp.SubtractSymbol.Present) {
553 if (SymbolicOp.SubtractSymbol.Name) {
554 StringRef Name(SymbolicOp.SubtractSymbol.Name);
555 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
556 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
558 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
562 const MCExpr *Off = NULL;
563 if (SymbolicOp.Value != 0)
564 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
570 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
572 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
574 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
579 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
586 Expr = MCConstantExpr::Create(0, *Ctx);
589 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
590 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
591 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
592 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
593 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
594 MI.addOperand(MCOperand::CreateExpr(Expr));
596 llvm_unreachable("bad SymbolicOp.VariantKind");
601 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
602 /// referenced by a load instruction with the base register that is the Pc.
603 /// These can often be values in a literal pool near the Address of the
604 /// instruction. The Address of the instruction and its immediate Value are
605 /// used as a possible literal pool entry. The SymbolLookUp call back will
606 /// return the name of a symbol referenced by the the literal pool's entry if
607 /// the referenced address is that of a symbol. Or it will return a pointer to
608 /// a literal 'C' string if the referenced address of the literal pool's entry
609 /// is an address into a section with 'C' string literals.
610 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
611 const void *Decoder) {
612 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
613 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
615 void *DisInfo = Dis->getDisInfoBlock();
616 uint64_t ReferenceType;
617 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
618 const char *ReferenceName;
619 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
620 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
621 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
622 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
626 // Thumb1 instructions don't have explicit S bits. Rather, they
627 // implicitly set CPSR. Since it's not represented in the encoding, the
628 // auto-generated decoder won't inject the CPSR operand. We need to fix
629 // that as a post-pass.
630 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
631 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
632 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
633 MCInst::iterator I = MI.begin();
634 for (unsigned i = 0; i < NumOps; ++i, ++I) {
635 if (I == MI.end()) break;
636 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
637 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
638 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
643 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
646 // Most Thumb instructions don't have explicit predicates in the
647 // encoding, but rather get their predicates from IT context. We need
648 // to fix up the predicate operands using this context information as a
650 MCDisassembler::DecodeStatus
651 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
652 MCDisassembler::DecodeStatus S = Success;
654 // A few instructions actually have predicates encoded in them. Don't
655 // try to overwrite it if we're seeing one of those.
656 switch (MI.getOpcode()) {
667 // Some instructions (mostly conditional branches) are not
668 // allowed in IT blocks.
669 if (ITBlock.instrInITBlock())
678 // Some instructions (mostly unconditional branches) can
679 // only appears at the end of, or outside of, an IT.
680 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
687 // If we're in an IT block, base the predicate on that. Otherwise,
688 // assume a predicate of AL.
690 CC = ITBlock.getITCC();
693 if (ITBlock.instrInITBlock())
694 ITBlock.advanceITState();
696 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
697 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
698 MCInst::iterator I = MI.begin();
699 for (unsigned i = 0; i < NumOps; ++i, ++I) {
700 if (I == MI.end()) break;
701 if (OpInfo[i].isPredicate()) {
702 I = MI.insert(I, MCOperand::CreateImm(CC));
705 MI.insert(I, MCOperand::CreateReg(0));
707 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
712 I = MI.insert(I, MCOperand::CreateImm(CC));
715 MI.insert(I, MCOperand::CreateReg(0));
717 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
722 // Thumb VFP instructions are a special case. Because we share their
723 // encodings between ARM and Thumb modes, and they are predicable in ARM
724 // mode, the auto-generated decoder will give them an (incorrect)
725 // predicate operand. We need to rewrite these operands based on the IT
726 // context as a post-pass.
727 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
729 CC = ITBlock.getITCC();
730 if (ITBlock.instrInITBlock())
731 ITBlock.advanceITState();
733 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
734 MCInst::iterator I = MI.begin();
735 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
736 for (unsigned i = 0; i < NumOps; ++i, ++I) {
737 if (OpInfo[i].isPredicate() ) {
743 I->setReg(ARM::CPSR);
749 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
750 const MemoryObject &Region,
753 raw_ostream &cs) const {
758 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
759 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
761 // We want to read exactly 2 bytes of data.
762 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
764 return MCDisassembler::Fail;
767 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
768 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
769 if (result != MCDisassembler::Fail) {
771 Check(result, AddThumbPredicate(MI));
776 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
779 bool InITBlock = ITBlock.instrInITBlock();
780 Check(result, AddThumbPredicate(MI));
781 AddThumb1SBit(MI, InITBlock);
786 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
787 if (result != MCDisassembler::Fail) {
790 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
791 // the Thumb predicate.
792 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
793 result = MCDisassembler::SoftFail;
795 Check(result, AddThumbPredicate(MI));
797 // If we find an IT instruction, we need to parse its condition
798 // code and mask operands so that we can apply them correctly
799 // to the subsequent instructions.
800 if (MI.getOpcode() == ARM::t2IT) {
802 unsigned Firstcond = MI.getOperand(0).getImm();
803 unsigned Mask = MI.getOperand(1).getImm();
804 ITBlock.setITState(Firstcond, Mask);
810 // We want to read exactly 4 bytes of data.
811 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
813 return MCDisassembler::Fail;
816 uint32_t insn32 = (bytes[3] << 8) |
821 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
822 if (result != MCDisassembler::Fail) {
824 bool InITBlock = ITBlock.instrInITBlock();
825 Check(result, AddThumbPredicate(MI));
826 AddThumb1SBit(MI, InITBlock);
831 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
832 if (result != MCDisassembler::Fail) {
834 Check(result, AddThumbPredicate(MI));
839 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
840 if (result != MCDisassembler::Fail) {
842 UpdateThumbVFPPredicate(MI);
847 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
848 if (result != MCDisassembler::Fail) {
850 Check(result, AddThumbPredicate(MI));
854 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
856 uint32_t NEONLdStInsn = insn32;
857 NEONLdStInsn &= 0xF0FFFFFF;
858 NEONLdStInsn |= 0x04000000;
859 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
860 if (result != MCDisassembler::Fail) {
862 Check(result, AddThumbPredicate(MI));
867 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
869 uint32_t NEONDataInsn = insn32;
870 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
871 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
872 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
873 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
874 if (result != MCDisassembler::Fail) {
876 Check(result, AddThumbPredicate(MI));
882 return MCDisassembler::Fail;
886 extern "C" void LLVMInitializeARMDisassembler() {
887 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
888 createARMDisassembler);
889 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
890 createThumbDisassembler);
893 static const uint16_t GPRDecoderTable[] = {
894 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
895 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
896 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
897 ARM::R12, ARM::SP, ARM::LR, ARM::PC
900 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
901 uint64_t Address, const void *Decoder) {
903 return MCDisassembler::Fail;
905 unsigned Register = GPRDecoderTable[RegNo];
906 Inst.addOperand(MCOperand::CreateReg(Register));
907 return MCDisassembler::Success;
911 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
912 uint64_t Address, const void *Decoder) {
913 DecodeStatus S = MCDisassembler::Success;
916 S = MCDisassembler::SoftFail;
918 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
923 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
924 uint64_t Address, const void *Decoder) {
926 return MCDisassembler::Fail;
927 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
930 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
931 uint64_t Address, const void *Decoder) {
932 unsigned Register = 0;
953 return MCDisassembler::Fail;
956 Inst.addOperand(MCOperand::CreateReg(Register));
957 return MCDisassembler::Success;
960 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
961 uint64_t Address, const void *Decoder) {
962 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
963 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
966 static const uint16_t SPRDecoderTable[] = {
967 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
968 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
969 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
970 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
971 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
972 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
973 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
974 ARM::S28, ARM::S29, ARM::S30, ARM::S31
977 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
978 uint64_t Address, const void *Decoder) {
980 return MCDisassembler::Fail;
982 unsigned Register = SPRDecoderTable[RegNo];
983 Inst.addOperand(MCOperand::CreateReg(Register));
984 return MCDisassembler::Success;
987 static const uint16_t DPRDecoderTable[] = {
988 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
989 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
990 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
991 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
992 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
993 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
994 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
995 ARM::D28, ARM::D29, ARM::D30, ARM::D31
998 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
999 uint64_t Address, const void *Decoder) {
1001 return MCDisassembler::Fail;
1003 unsigned Register = DPRDecoderTable[RegNo];
1004 Inst.addOperand(MCOperand::CreateReg(Register));
1005 return MCDisassembler::Success;
1008 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1009 uint64_t Address, const void *Decoder) {
1011 return MCDisassembler::Fail;
1012 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1016 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1017 uint64_t Address, const void *Decoder) {
1019 return MCDisassembler::Fail;
1020 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1023 static const uint16_t QPRDecoderTable[] = {
1024 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1025 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1026 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1027 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1031 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1032 uint64_t Address, const void *Decoder) {
1034 return MCDisassembler::Fail;
1037 unsigned Register = QPRDecoderTable[RegNo];
1038 Inst.addOperand(MCOperand::CreateReg(Register));
1039 return MCDisassembler::Success;
1042 static const uint16_t DPairDecoderTable[] = {
1043 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1044 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1045 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1046 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1047 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1051 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1052 uint64_t Address, const void *Decoder) {
1054 return MCDisassembler::Fail;
1056 unsigned Register = DPairDecoderTable[RegNo];
1057 Inst.addOperand(MCOperand::CreateReg(Register));
1058 return MCDisassembler::Success;
1061 static const uint16_t DPairSpacedDecoderTable[] = {
1062 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1063 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1064 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1065 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1066 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1067 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1068 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1069 ARM::D28_D30, ARM::D29_D31
1072 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1075 const void *Decoder) {
1077 return MCDisassembler::Fail;
1079 unsigned Register = DPairSpacedDecoderTable[RegNo];
1080 Inst.addOperand(MCOperand::CreateReg(Register));
1081 return MCDisassembler::Success;
1084 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1085 uint64_t Address, const void *Decoder) {
1086 if (Val == 0xF) return MCDisassembler::Fail;
1087 // AL predicate is not allowed on Thumb1 branches.
1088 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1089 return MCDisassembler::Fail;
1090 Inst.addOperand(MCOperand::CreateImm(Val));
1091 if (Val == ARMCC::AL) {
1092 Inst.addOperand(MCOperand::CreateReg(0));
1094 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1095 return MCDisassembler::Success;
1098 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1099 uint64_t Address, const void *Decoder) {
1101 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1103 Inst.addOperand(MCOperand::CreateReg(0));
1104 return MCDisassembler::Success;
1107 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1108 uint64_t Address, const void *Decoder) {
1109 uint32_t imm = Val & 0xFF;
1110 uint32_t rot = (Val & 0xF00) >> 7;
1111 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1112 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1113 return MCDisassembler::Success;
1116 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1117 uint64_t Address, const void *Decoder) {
1118 DecodeStatus S = MCDisassembler::Success;
1120 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1121 unsigned type = fieldFromInstruction32(Val, 5, 2);
1122 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1124 // Register-immediate
1125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1126 return MCDisassembler::Fail;
1128 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1131 Shift = ARM_AM::lsl;
1134 Shift = ARM_AM::lsr;
1137 Shift = ARM_AM::asr;
1140 Shift = ARM_AM::ror;
1144 if (Shift == ARM_AM::ror && imm == 0)
1145 Shift = ARM_AM::rrx;
1147 unsigned Op = Shift | (imm << 3);
1148 Inst.addOperand(MCOperand::CreateImm(Op));
1153 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1154 uint64_t Address, const void *Decoder) {
1155 DecodeStatus S = MCDisassembler::Success;
1157 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1158 unsigned type = fieldFromInstruction32(Val, 5, 2);
1159 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1161 // Register-register
1162 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1163 return MCDisassembler::Fail;
1164 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1165 return MCDisassembler::Fail;
1167 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1170 Shift = ARM_AM::lsl;
1173 Shift = ARM_AM::lsr;
1176 Shift = ARM_AM::asr;
1179 Shift = ARM_AM::ror;
1183 Inst.addOperand(MCOperand::CreateImm(Shift));
1188 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1189 uint64_t Address, const void *Decoder) {
1190 DecodeStatus S = MCDisassembler::Success;
1192 bool writebackLoad = false;
1193 unsigned writebackReg = 0;
1194 switch (Inst.getOpcode()) {
1197 case ARM::LDMIA_UPD:
1198 case ARM::LDMDB_UPD:
1199 case ARM::LDMIB_UPD:
1200 case ARM::LDMDA_UPD:
1201 case ARM::t2LDMIA_UPD:
1202 case ARM::t2LDMDB_UPD:
1203 writebackLoad = true;
1204 writebackReg = Inst.getOperand(0).getReg();
1208 // Empty register lists are not allowed.
1209 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1210 for (unsigned i = 0; i < 16; ++i) {
1211 if (Val & (1 << i)) {
1212 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1213 return MCDisassembler::Fail;
1214 // Writeback not allowed if Rn is in the target list.
1215 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1216 Check(S, MCDisassembler::SoftFail);
1223 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1224 uint64_t Address, const void *Decoder) {
1225 DecodeStatus S = MCDisassembler::Success;
1227 unsigned Vd = fieldFromInstruction32(Val, 8, 5);
1228 unsigned regs = fieldFromInstruction32(Val, 0, 8);
1230 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1231 return MCDisassembler::Fail;
1232 for (unsigned i = 0; i < (regs - 1); ++i) {
1233 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1234 return MCDisassembler::Fail;
1240 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1241 uint64_t Address, const void *Decoder) {
1242 DecodeStatus S = MCDisassembler::Success;
1244 unsigned Vd = fieldFromInstruction32(Val, 8, 5);
1245 unsigned regs = fieldFromInstruction32(Val, 0, 8);
1249 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1250 return MCDisassembler::Fail;
1251 for (unsigned i = 0; i < (regs - 1); ++i) {
1252 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1253 return MCDisassembler::Fail;
1259 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1260 uint64_t Address, const void *Decoder) {
1261 // This operand encodes a mask of contiguous zeros between a specified MSB
1262 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1263 // the mask of all bits LSB-and-lower, and then xor them to create
1264 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1265 // create the final mask.
1266 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1267 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1269 DecodeStatus S = MCDisassembler::Success;
1270 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1272 uint32_t msb_mask = 0xFFFFFFFF;
1273 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1274 uint32_t lsb_mask = (1U << lsb) - 1;
1276 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1280 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1281 uint64_t Address, const void *Decoder) {
1282 DecodeStatus S = MCDisassembler::Success;
1284 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1285 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1286 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1287 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1288 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1289 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1291 switch (Inst.getOpcode()) {
1292 case ARM::LDC_OFFSET:
1295 case ARM::LDC_OPTION:
1296 case ARM::LDCL_OFFSET:
1298 case ARM::LDCL_POST:
1299 case ARM::LDCL_OPTION:
1300 case ARM::STC_OFFSET:
1303 case ARM::STC_OPTION:
1304 case ARM::STCL_OFFSET:
1306 case ARM::STCL_POST:
1307 case ARM::STCL_OPTION:
1308 case ARM::t2LDC_OFFSET:
1309 case ARM::t2LDC_PRE:
1310 case ARM::t2LDC_POST:
1311 case ARM::t2LDC_OPTION:
1312 case ARM::t2LDCL_OFFSET:
1313 case ARM::t2LDCL_PRE:
1314 case ARM::t2LDCL_POST:
1315 case ARM::t2LDCL_OPTION:
1316 case ARM::t2STC_OFFSET:
1317 case ARM::t2STC_PRE:
1318 case ARM::t2STC_POST:
1319 case ARM::t2STC_OPTION:
1320 case ARM::t2STCL_OFFSET:
1321 case ARM::t2STCL_PRE:
1322 case ARM::t2STCL_POST:
1323 case ARM::t2STCL_OPTION:
1324 if (coproc == 0xA || coproc == 0xB)
1325 return MCDisassembler::Fail;
1331 Inst.addOperand(MCOperand::CreateImm(coproc));
1332 Inst.addOperand(MCOperand::CreateImm(CRd));
1333 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1334 return MCDisassembler::Fail;
1336 switch (Inst.getOpcode()) {
1337 case ARM::t2LDC2_OFFSET:
1338 case ARM::t2LDC2L_OFFSET:
1339 case ARM::t2LDC2_PRE:
1340 case ARM::t2LDC2L_PRE:
1341 case ARM::t2STC2_OFFSET:
1342 case ARM::t2STC2L_OFFSET:
1343 case ARM::t2STC2_PRE:
1344 case ARM::t2STC2L_PRE:
1345 case ARM::LDC2_OFFSET:
1346 case ARM::LDC2L_OFFSET:
1348 case ARM::LDC2L_PRE:
1349 case ARM::STC2_OFFSET:
1350 case ARM::STC2L_OFFSET:
1352 case ARM::STC2L_PRE:
1353 case ARM::t2LDC_OFFSET:
1354 case ARM::t2LDCL_OFFSET:
1355 case ARM::t2LDC_PRE:
1356 case ARM::t2LDCL_PRE:
1357 case ARM::t2STC_OFFSET:
1358 case ARM::t2STCL_OFFSET:
1359 case ARM::t2STC_PRE:
1360 case ARM::t2STCL_PRE:
1361 case ARM::LDC_OFFSET:
1362 case ARM::LDCL_OFFSET:
1365 case ARM::STC_OFFSET:
1366 case ARM::STCL_OFFSET:
1369 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1370 Inst.addOperand(MCOperand::CreateImm(imm));
1372 case ARM::t2LDC2_POST:
1373 case ARM::t2LDC2L_POST:
1374 case ARM::t2STC2_POST:
1375 case ARM::t2STC2L_POST:
1376 case ARM::LDC2_POST:
1377 case ARM::LDC2L_POST:
1378 case ARM::STC2_POST:
1379 case ARM::STC2L_POST:
1380 case ARM::t2LDC_POST:
1381 case ARM::t2LDCL_POST:
1382 case ARM::t2STC_POST:
1383 case ARM::t2STCL_POST:
1385 case ARM::LDCL_POST:
1387 case ARM::STCL_POST:
1391 // The 'option' variant doesn't encode 'U' in the immediate since
1392 // the immediate is unsigned [0,255].
1393 Inst.addOperand(MCOperand::CreateImm(imm));
1397 switch (Inst.getOpcode()) {
1398 case ARM::LDC_OFFSET:
1401 case ARM::LDC_OPTION:
1402 case ARM::LDCL_OFFSET:
1404 case ARM::LDCL_POST:
1405 case ARM::LDCL_OPTION:
1406 case ARM::STC_OFFSET:
1409 case ARM::STC_OPTION:
1410 case ARM::STCL_OFFSET:
1412 case ARM::STCL_POST:
1413 case ARM::STCL_OPTION:
1414 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1415 return MCDisassembler::Fail;
1425 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1426 uint64_t Address, const void *Decoder) {
1427 DecodeStatus S = MCDisassembler::Success;
1429 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1430 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1431 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1432 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1433 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1434 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1435 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1436 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1438 // On stores, the writeback operand precedes Rt.
1439 switch (Inst.getOpcode()) {
1440 case ARM::STR_POST_IMM:
1441 case ARM::STR_POST_REG:
1442 case ARM::STRB_POST_IMM:
1443 case ARM::STRB_POST_REG:
1444 case ARM::STRT_POST_REG:
1445 case ARM::STRT_POST_IMM:
1446 case ARM::STRBT_POST_REG:
1447 case ARM::STRBT_POST_IMM:
1448 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1449 return MCDisassembler::Fail;
1455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1456 return MCDisassembler::Fail;
1458 // On loads, the writeback operand comes after Rt.
1459 switch (Inst.getOpcode()) {
1460 case ARM::LDR_POST_IMM:
1461 case ARM::LDR_POST_REG:
1462 case ARM::LDRB_POST_IMM:
1463 case ARM::LDRB_POST_REG:
1464 case ARM::LDRBT_POST_REG:
1465 case ARM::LDRBT_POST_IMM:
1466 case ARM::LDRT_POST_REG:
1467 case ARM::LDRT_POST_IMM:
1468 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1469 return MCDisassembler::Fail;
1475 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1476 return MCDisassembler::Fail;
1478 ARM_AM::AddrOpc Op = ARM_AM::add;
1479 if (!fieldFromInstruction32(Insn, 23, 1))
1482 bool writeback = (P == 0) || (W == 1);
1483 unsigned idx_mode = 0;
1485 idx_mode = ARMII::IndexModePre;
1486 else if (!P && writeback)
1487 idx_mode = ARMII::IndexModePost;
1489 if (writeback && (Rn == 15 || Rn == Rt))
1490 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1493 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1494 return MCDisassembler::Fail;
1495 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1496 switch( fieldFromInstruction32(Insn, 5, 2)) {
1510 return MCDisassembler::Fail;
1512 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1513 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1515 Inst.addOperand(MCOperand::CreateImm(imm));
1517 Inst.addOperand(MCOperand::CreateReg(0));
1518 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1519 Inst.addOperand(MCOperand::CreateImm(tmp));
1522 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1523 return MCDisassembler::Fail;
1528 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1529 uint64_t Address, const void *Decoder) {
1530 DecodeStatus S = MCDisassembler::Success;
1532 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1533 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1534 unsigned type = fieldFromInstruction32(Val, 5, 2);
1535 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1536 unsigned U = fieldFromInstruction32(Val, 12, 1);
1538 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1555 return MCDisassembler::Fail;
1556 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1557 return MCDisassembler::Fail;
1560 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1562 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1563 Inst.addOperand(MCOperand::CreateImm(shift));
1569 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1570 uint64_t Address, const void *Decoder) {
1571 DecodeStatus S = MCDisassembler::Success;
1573 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1574 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1576 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1577 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1578 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1579 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1580 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1581 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1582 unsigned Rt2 = Rt + 1;
1584 bool writeback = (W == 1) | (P == 0);
1586 // For {LD,ST}RD, Rt must be even, else undefined.
1587 switch (Inst.getOpcode()) {
1590 case ARM::STRD_POST:
1593 case ARM::LDRD_POST:
1594 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1599 switch (Inst.getOpcode()) {
1602 case ARM::STRD_POST:
1603 if (P == 0 && W == 1)
1604 S = MCDisassembler::SoftFail;
1606 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1607 S = MCDisassembler::SoftFail;
1608 if (type && Rm == 15)
1609 S = MCDisassembler::SoftFail;
1611 S = MCDisassembler::SoftFail;
1612 if (!type && fieldFromInstruction32(Insn, 8, 4))
1613 S = MCDisassembler::SoftFail;
1617 case ARM::STRH_POST:
1619 S = MCDisassembler::SoftFail;
1620 if (writeback && (Rn == 15 || Rn == Rt))
1621 S = MCDisassembler::SoftFail;
1622 if (!type && Rm == 15)
1623 S = MCDisassembler::SoftFail;
1627 case ARM::LDRD_POST:
1628 if (type && Rn == 15){
1630 S = MCDisassembler::SoftFail;
1633 if (P == 0 && W == 1)
1634 S = MCDisassembler::SoftFail;
1635 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1636 S = MCDisassembler::SoftFail;
1637 if (!type && writeback && Rn == 15)
1638 S = MCDisassembler::SoftFail;
1639 if (writeback && (Rn == Rt || Rn == Rt2))
1640 S = MCDisassembler::SoftFail;
1644 case ARM::LDRH_POST:
1645 if (type && Rn == 15){
1647 S = MCDisassembler::SoftFail;
1651 S = MCDisassembler::SoftFail;
1652 if (!type && Rm == 15)
1653 S = MCDisassembler::SoftFail;
1654 if (!type && writeback && (Rn == 15 || Rn == Rt))
1655 S = MCDisassembler::SoftFail;
1658 case ARM::LDRSH_PRE:
1659 case ARM::LDRSH_POST:
1661 case ARM::LDRSB_PRE:
1662 case ARM::LDRSB_POST:
1663 if (type && Rn == 15){
1665 S = MCDisassembler::SoftFail;
1668 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1669 S = MCDisassembler::SoftFail;
1670 if (!type && (Rt == 15 || Rm == 15))
1671 S = MCDisassembler::SoftFail;
1672 if (!type && writeback && (Rn == 15 || Rn == Rt))
1673 S = MCDisassembler::SoftFail;
1679 if (writeback) { // Writeback
1681 U |= ARMII::IndexModePre << 9;
1683 U |= ARMII::IndexModePost << 9;
1685 // On stores, the writeback operand precedes Rt.
1686 switch (Inst.getOpcode()) {
1689 case ARM::STRD_POST:
1692 case ARM::STRH_POST:
1693 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1694 return MCDisassembler::Fail;
1701 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1702 return MCDisassembler::Fail;
1703 switch (Inst.getOpcode()) {
1706 case ARM::STRD_POST:
1709 case ARM::LDRD_POST:
1710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1711 return MCDisassembler::Fail;
1718 // On loads, the writeback operand comes after Rt.
1719 switch (Inst.getOpcode()) {
1722 case ARM::LDRD_POST:
1725 case ARM::LDRH_POST:
1727 case ARM::LDRSH_PRE:
1728 case ARM::LDRSH_POST:
1730 case ARM::LDRSB_PRE:
1731 case ARM::LDRSB_POST:
1734 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1735 return MCDisassembler::Fail;
1742 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1743 return MCDisassembler::Fail;
1746 Inst.addOperand(MCOperand::CreateReg(0));
1747 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1750 return MCDisassembler::Fail;
1751 Inst.addOperand(MCOperand::CreateImm(U));
1754 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1755 return MCDisassembler::Fail;
1760 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1761 uint64_t Address, const void *Decoder) {
1762 DecodeStatus S = MCDisassembler::Success;
1764 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1765 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1782 Inst.addOperand(MCOperand::CreateImm(mode));
1783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1784 return MCDisassembler::Fail;
1789 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1791 uint64_t Address, const void *Decoder) {
1792 DecodeStatus S = MCDisassembler::Success;
1794 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1795 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1796 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1799 switch (Inst.getOpcode()) {
1801 Inst.setOpcode(ARM::RFEDA);
1803 case ARM::LDMDA_UPD:
1804 Inst.setOpcode(ARM::RFEDA_UPD);
1807 Inst.setOpcode(ARM::RFEDB);
1809 case ARM::LDMDB_UPD:
1810 Inst.setOpcode(ARM::RFEDB_UPD);
1813 Inst.setOpcode(ARM::RFEIA);
1815 case ARM::LDMIA_UPD:
1816 Inst.setOpcode(ARM::RFEIA_UPD);
1819 Inst.setOpcode(ARM::RFEIB);
1821 case ARM::LDMIB_UPD:
1822 Inst.setOpcode(ARM::RFEIB_UPD);
1825 Inst.setOpcode(ARM::SRSDA);
1827 case ARM::STMDA_UPD:
1828 Inst.setOpcode(ARM::SRSDA_UPD);
1831 Inst.setOpcode(ARM::SRSDB);
1833 case ARM::STMDB_UPD:
1834 Inst.setOpcode(ARM::SRSDB_UPD);
1837 Inst.setOpcode(ARM::SRSIA);
1839 case ARM::STMIA_UPD:
1840 Inst.setOpcode(ARM::SRSIA_UPD);
1843 Inst.setOpcode(ARM::SRSIB);
1845 case ARM::STMIB_UPD:
1846 Inst.setOpcode(ARM::SRSIB_UPD);
1849 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1852 // For stores (which become SRS's, the only operand is the mode.
1853 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1855 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1859 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1863 return MCDisassembler::Fail;
1864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1865 return MCDisassembler::Fail; // Tied
1866 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1867 return MCDisassembler::Fail;
1868 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1869 return MCDisassembler::Fail;
1874 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1875 uint64_t Address, const void *Decoder) {
1876 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1877 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1878 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1879 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1881 DecodeStatus S = MCDisassembler::Success;
1883 // imod == '01' --> UNPREDICTABLE
1884 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1885 // return failure here. The '01' imod value is unprintable, so there's
1886 // nothing useful we could do even if we returned UNPREDICTABLE.
1888 if (imod == 1) return MCDisassembler::Fail;
1891 Inst.setOpcode(ARM::CPS3p);
1892 Inst.addOperand(MCOperand::CreateImm(imod));
1893 Inst.addOperand(MCOperand::CreateImm(iflags));
1894 Inst.addOperand(MCOperand::CreateImm(mode));
1895 } else if (imod && !M) {
1896 Inst.setOpcode(ARM::CPS2p);
1897 Inst.addOperand(MCOperand::CreateImm(imod));
1898 Inst.addOperand(MCOperand::CreateImm(iflags));
1899 if (mode) S = MCDisassembler::SoftFail;
1900 } else if (!imod && M) {
1901 Inst.setOpcode(ARM::CPS1p);
1902 Inst.addOperand(MCOperand::CreateImm(mode));
1903 if (iflags) S = MCDisassembler::SoftFail;
1905 // imod == '00' && M == '0' --> UNPREDICTABLE
1906 Inst.setOpcode(ARM::CPS1p);
1907 Inst.addOperand(MCOperand::CreateImm(mode));
1908 S = MCDisassembler::SoftFail;
1914 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1915 uint64_t Address, const void *Decoder) {
1916 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1917 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1918 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1919 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1921 DecodeStatus S = MCDisassembler::Success;
1923 // imod == '01' --> UNPREDICTABLE
1924 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1925 // return failure here. The '01' imod value is unprintable, so there's
1926 // nothing useful we could do even if we returned UNPREDICTABLE.
1928 if (imod == 1) return MCDisassembler::Fail;
1931 Inst.setOpcode(ARM::t2CPS3p);
1932 Inst.addOperand(MCOperand::CreateImm(imod));
1933 Inst.addOperand(MCOperand::CreateImm(iflags));
1934 Inst.addOperand(MCOperand::CreateImm(mode));
1935 } else if (imod && !M) {
1936 Inst.setOpcode(ARM::t2CPS2p);
1937 Inst.addOperand(MCOperand::CreateImm(imod));
1938 Inst.addOperand(MCOperand::CreateImm(iflags));
1939 if (mode) S = MCDisassembler::SoftFail;
1940 } else if (!imod && M) {
1941 Inst.setOpcode(ARM::t2CPS1p);
1942 Inst.addOperand(MCOperand::CreateImm(mode));
1943 if (iflags) S = MCDisassembler::SoftFail;
1945 // imod == '00' && M == '0' --> UNPREDICTABLE
1946 Inst.setOpcode(ARM::t2CPS1p);
1947 Inst.addOperand(MCOperand::CreateImm(mode));
1948 S = MCDisassembler::SoftFail;
1954 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
1955 uint64_t Address, const void *Decoder) {
1956 DecodeStatus S = MCDisassembler::Success;
1958 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1961 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1962 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1963 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1964 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1966 if (Inst.getOpcode() == ARM::t2MOVTi16)
1967 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1968 return MCDisassembler::Fail;
1969 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1970 return MCDisassembler::Fail;
1972 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1973 Inst.addOperand(MCOperand::CreateImm(imm));
1978 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
1979 uint64_t Address, const void *Decoder) {
1980 DecodeStatus S = MCDisassembler::Success;
1982 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1983 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1986 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1987 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1989 if (Inst.getOpcode() == ARM::MOVTi16)
1990 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1991 return MCDisassembler::Fail;
1992 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1993 return MCDisassembler::Fail;
1995 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1996 Inst.addOperand(MCOperand::CreateImm(imm));
1998 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1999 return MCDisassembler::Fail;
2004 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2005 uint64_t Address, const void *Decoder) {
2006 DecodeStatus S = MCDisassembler::Success;
2008 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
2009 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
2010 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
2011 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
2012 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2015 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2017 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2018 return MCDisassembler::Fail;
2019 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2020 return MCDisassembler::Fail;
2021 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2022 return MCDisassembler::Fail;
2023 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2024 return MCDisassembler::Fail;
2026 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2027 return MCDisassembler::Fail;
2032 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2033 uint64_t Address, const void *Decoder) {
2034 DecodeStatus S = MCDisassembler::Success;
2036 unsigned add = fieldFromInstruction32(Val, 12, 1);
2037 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2038 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2040 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2041 return MCDisassembler::Fail;
2043 if (!add) imm *= -1;
2044 if (imm == 0 && !add) imm = INT32_MIN;
2045 Inst.addOperand(MCOperand::CreateImm(imm));
2047 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2052 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2053 uint64_t Address, const void *Decoder) {
2054 DecodeStatus S = MCDisassembler::Success;
2056 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2057 unsigned U = fieldFromInstruction32(Val, 8, 1);
2058 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2061 return MCDisassembler::Fail;
2064 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2066 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2071 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2072 uint64_t Address, const void *Decoder) {
2073 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2077 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2078 uint64_t Address, const void *Decoder) {
2079 DecodeStatus S = MCDisassembler::Success;
2080 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) |
2081 (fieldFromInstruction32(Insn, 11, 1) << 18) |
2082 (fieldFromInstruction32(Insn, 13, 1) << 17) |
2083 (fieldFromInstruction32(Insn, 16, 6) << 11) |
2084 (fieldFromInstruction32(Insn, 26, 1) << 19);
2085 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
2086 true, 4, Inst, Decoder))
2087 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
2092 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2093 uint64_t Address, const void *Decoder) {
2094 DecodeStatus S = MCDisassembler::Success;
2096 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2097 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
2100 Inst.setOpcode(ARM::BLXi);
2101 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
2102 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2103 true, 4, Inst, Decoder))
2104 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2108 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2109 true, 4, Inst, Decoder))
2110 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2111 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2112 return MCDisassembler::Fail;
2118 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2119 uint64_t Address, const void *Decoder) {
2120 DecodeStatus S = MCDisassembler::Success;
2122 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
2123 unsigned align = fieldFromInstruction32(Val, 4, 2);
2125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2126 return MCDisassembler::Fail;
2128 Inst.addOperand(MCOperand::CreateImm(0));
2130 Inst.addOperand(MCOperand::CreateImm(4 << align));
2135 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2136 uint64_t Address, const void *Decoder) {
2137 DecodeStatus S = MCDisassembler::Success;
2139 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2140 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2141 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2142 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2143 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2144 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2146 // First output register
2147 switch (Inst.getOpcode()) {
2148 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2149 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2150 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2151 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2152 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2153 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2154 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2155 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2156 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2157 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2158 return MCDisassembler::Fail;
2163 case ARM::VLD2b16wb_fixed:
2164 case ARM::VLD2b16wb_register:
2165 case ARM::VLD2b32wb_fixed:
2166 case ARM::VLD2b32wb_register:
2167 case ARM::VLD2b8wb_fixed:
2168 case ARM::VLD2b8wb_register:
2169 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2170 return MCDisassembler::Fail;
2173 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2174 return MCDisassembler::Fail;
2177 // Second output register
2178 switch (Inst.getOpcode()) {
2182 case ARM::VLD3d8_UPD:
2183 case ARM::VLD3d16_UPD:
2184 case ARM::VLD3d32_UPD:
2188 case ARM::VLD4d8_UPD:
2189 case ARM::VLD4d16_UPD:
2190 case ARM::VLD4d32_UPD:
2191 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2192 return MCDisassembler::Fail;
2197 case ARM::VLD3q8_UPD:
2198 case ARM::VLD3q16_UPD:
2199 case ARM::VLD3q32_UPD:
2203 case ARM::VLD4q8_UPD:
2204 case ARM::VLD4q16_UPD:
2205 case ARM::VLD4q32_UPD:
2206 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2207 return MCDisassembler::Fail;
2212 // Third output register
2213 switch(Inst.getOpcode()) {
2217 case ARM::VLD3d8_UPD:
2218 case ARM::VLD3d16_UPD:
2219 case ARM::VLD3d32_UPD:
2223 case ARM::VLD4d8_UPD:
2224 case ARM::VLD4d16_UPD:
2225 case ARM::VLD4d32_UPD:
2226 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2227 return MCDisassembler::Fail;
2232 case ARM::VLD3q8_UPD:
2233 case ARM::VLD3q16_UPD:
2234 case ARM::VLD3q32_UPD:
2238 case ARM::VLD4q8_UPD:
2239 case ARM::VLD4q16_UPD:
2240 case ARM::VLD4q32_UPD:
2241 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2242 return MCDisassembler::Fail;
2248 // Fourth output register
2249 switch (Inst.getOpcode()) {
2253 case ARM::VLD4d8_UPD:
2254 case ARM::VLD4d16_UPD:
2255 case ARM::VLD4d32_UPD:
2256 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2257 return MCDisassembler::Fail;
2262 case ARM::VLD4q8_UPD:
2263 case ARM::VLD4q16_UPD:
2264 case ARM::VLD4q32_UPD:
2265 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2266 return MCDisassembler::Fail;
2272 // Writeback operand
2273 switch (Inst.getOpcode()) {
2274 case ARM::VLD1d8wb_fixed:
2275 case ARM::VLD1d16wb_fixed:
2276 case ARM::VLD1d32wb_fixed:
2277 case ARM::VLD1d64wb_fixed:
2278 case ARM::VLD1d8wb_register:
2279 case ARM::VLD1d16wb_register:
2280 case ARM::VLD1d32wb_register:
2281 case ARM::VLD1d64wb_register:
2282 case ARM::VLD1q8wb_fixed:
2283 case ARM::VLD1q16wb_fixed:
2284 case ARM::VLD1q32wb_fixed:
2285 case ARM::VLD1q64wb_fixed:
2286 case ARM::VLD1q8wb_register:
2287 case ARM::VLD1q16wb_register:
2288 case ARM::VLD1q32wb_register:
2289 case ARM::VLD1q64wb_register:
2290 case ARM::VLD1d8Twb_fixed:
2291 case ARM::VLD1d8Twb_register:
2292 case ARM::VLD1d16Twb_fixed:
2293 case ARM::VLD1d16Twb_register:
2294 case ARM::VLD1d32Twb_fixed:
2295 case ARM::VLD1d32Twb_register:
2296 case ARM::VLD1d64Twb_fixed:
2297 case ARM::VLD1d64Twb_register:
2298 case ARM::VLD1d8Qwb_fixed:
2299 case ARM::VLD1d8Qwb_register:
2300 case ARM::VLD1d16Qwb_fixed:
2301 case ARM::VLD1d16Qwb_register:
2302 case ARM::VLD1d32Qwb_fixed:
2303 case ARM::VLD1d32Qwb_register:
2304 case ARM::VLD1d64Qwb_fixed:
2305 case ARM::VLD1d64Qwb_register:
2306 case ARM::VLD2d8wb_fixed:
2307 case ARM::VLD2d16wb_fixed:
2308 case ARM::VLD2d32wb_fixed:
2309 case ARM::VLD2q8wb_fixed:
2310 case ARM::VLD2q16wb_fixed:
2311 case ARM::VLD2q32wb_fixed:
2312 case ARM::VLD2d8wb_register:
2313 case ARM::VLD2d16wb_register:
2314 case ARM::VLD2d32wb_register:
2315 case ARM::VLD2q8wb_register:
2316 case ARM::VLD2q16wb_register:
2317 case ARM::VLD2q32wb_register:
2318 case ARM::VLD2b8wb_fixed:
2319 case ARM::VLD2b16wb_fixed:
2320 case ARM::VLD2b32wb_fixed:
2321 case ARM::VLD2b8wb_register:
2322 case ARM::VLD2b16wb_register:
2323 case ARM::VLD2b32wb_register:
2324 Inst.addOperand(MCOperand::CreateImm(0));
2326 case ARM::VLD3d8_UPD:
2327 case ARM::VLD3d16_UPD:
2328 case ARM::VLD3d32_UPD:
2329 case ARM::VLD3q8_UPD:
2330 case ARM::VLD3q16_UPD:
2331 case ARM::VLD3q32_UPD:
2332 case ARM::VLD4d8_UPD:
2333 case ARM::VLD4d16_UPD:
2334 case ARM::VLD4d32_UPD:
2335 case ARM::VLD4q8_UPD:
2336 case ARM::VLD4q16_UPD:
2337 case ARM::VLD4q32_UPD:
2338 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2339 return MCDisassembler::Fail;
2345 // AddrMode6 Base (register+alignment)
2346 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2347 return MCDisassembler::Fail;
2349 // AddrMode6 Offset (register)
2350 switch (Inst.getOpcode()) {
2352 // The below have been updated to have explicit am6offset split
2353 // between fixed and register offset. For those instructions not
2354 // yet updated, we need to add an additional reg0 operand for the
2357 // The fixed offset encodes as Rm == 0xd, so we check for that.
2359 Inst.addOperand(MCOperand::CreateReg(0));
2362 // Fall through to handle the register offset variant.
2363 case ARM::VLD1d8wb_fixed:
2364 case ARM::VLD1d16wb_fixed:
2365 case ARM::VLD1d32wb_fixed:
2366 case ARM::VLD1d64wb_fixed:
2367 case ARM::VLD1d8Twb_fixed:
2368 case ARM::VLD1d16Twb_fixed:
2369 case ARM::VLD1d32Twb_fixed:
2370 case ARM::VLD1d64Twb_fixed:
2371 case ARM::VLD1d8Qwb_fixed:
2372 case ARM::VLD1d16Qwb_fixed:
2373 case ARM::VLD1d32Qwb_fixed:
2374 case ARM::VLD1d64Qwb_fixed:
2375 case ARM::VLD1d8wb_register:
2376 case ARM::VLD1d16wb_register:
2377 case ARM::VLD1d32wb_register:
2378 case ARM::VLD1d64wb_register:
2379 case ARM::VLD1q8wb_fixed:
2380 case ARM::VLD1q16wb_fixed:
2381 case ARM::VLD1q32wb_fixed:
2382 case ARM::VLD1q64wb_fixed:
2383 case ARM::VLD1q8wb_register:
2384 case ARM::VLD1q16wb_register:
2385 case ARM::VLD1q32wb_register:
2386 case ARM::VLD1q64wb_register:
2387 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2388 // variant encodes Rm == 0xf. Anything else is a register offset post-
2389 // increment and we need to add the register operand to the instruction.
2390 if (Rm != 0xD && Rm != 0xF &&
2391 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2392 return MCDisassembler::Fail;
2394 case ARM::VLD2d8wb_fixed:
2395 case ARM::VLD2d16wb_fixed:
2396 case ARM::VLD2d32wb_fixed:
2397 case ARM::VLD2b8wb_fixed:
2398 case ARM::VLD2b16wb_fixed:
2399 case ARM::VLD2b32wb_fixed:
2400 case ARM::VLD2q8wb_fixed:
2401 case ARM::VLD2q16wb_fixed:
2402 case ARM::VLD2q32wb_fixed:
2409 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2410 uint64_t Address, const void *Decoder) {
2411 DecodeStatus S = MCDisassembler::Success;
2413 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2414 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2415 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2416 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2417 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2418 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2420 // Writeback Operand
2421 switch (Inst.getOpcode()) {
2422 case ARM::VST1d8wb_fixed:
2423 case ARM::VST1d16wb_fixed:
2424 case ARM::VST1d32wb_fixed:
2425 case ARM::VST1d64wb_fixed:
2426 case ARM::VST1d8wb_register:
2427 case ARM::VST1d16wb_register:
2428 case ARM::VST1d32wb_register:
2429 case ARM::VST1d64wb_register:
2430 case ARM::VST1q8wb_fixed:
2431 case ARM::VST1q16wb_fixed:
2432 case ARM::VST1q32wb_fixed:
2433 case ARM::VST1q64wb_fixed:
2434 case ARM::VST1q8wb_register:
2435 case ARM::VST1q16wb_register:
2436 case ARM::VST1q32wb_register:
2437 case ARM::VST1q64wb_register:
2438 case ARM::VST1d8Twb_fixed:
2439 case ARM::VST1d16Twb_fixed:
2440 case ARM::VST1d32Twb_fixed:
2441 case ARM::VST1d64Twb_fixed:
2442 case ARM::VST1d8Twb_register:
2443 case ARM::VST1d16Twb_register:
2444 case ARM::VST1d32Twb_register:
2445 case ARM::VST1d64Twb_register:
2446 case ARM::VST1d8Qwb_fixed:
2447 case ARM::VST1d16Qwb_fixed:
2448 case ARM::VST1d32Qwb_fixed:
2449 case ARM::VST1d64Qwb_fixed:
2450 case ARM::VST1d8Qwb_register:
2451 case ARM::VST1d16Qwb_register:
2452 case ARM::VST1d32Qwb_register:
2453 case ARM::VST1d64Qwb_register:
2454 case ARM::VST2d8wb_fixed:
2455 case ARM::VST2d16wb_fixed:
2456 case ARM::VST2d32wb_fixed:
2457 case ARM::VST2d8wb_register:
2458 case ARM::VST2d16wb_register:
2459 case ARM::VST2d32wb_register:
2460 case ARM::VST2q8wb_fixed:
2461 case ARM::VST2q16wb_fixed:
2462 case ARM::VST2q32wb_fixed:
2463 case ARM::VST2q8wb_register:
2464 case ARM::VST2q16wb_register:
2465 case ARM::VST2q32wb_register:
2466 case ARM::VST2b8wb_fixed:
2467 case ARM::VST2b16wb_fixed:
2468 case ARM::VST2b32wb_fixed:
2469 case ARM::VST2b8wb_register:
2470 case ARM::VST2b16wb_register:
2471 case ARM::VST2b32wb_register:
2473 return MCDisassembler::Fail;
2474 Inst.addOperand(MCOperand::CreateImm(0));
2476 case ARM::VST3d8_UPD:
2477 case ARM::VST3d16_UPD:
2478 case ARM::VST3d32_UPD:
2479 case ARM::VST3q8_UPD:
2480 case ARM::VST3q16_UPD:
2481 case ARM::VST3q32_UPD:
2482 case ARM::VST4d8_UPD:
2483 case ARM::VST4d16_UPD:
2484 case ARM::VST4d32_UPD:
2485 case ARM::VST4q8_UPD:
2486 case ARM::VST4q16_UPD:
2487 case ARM::VST4q32_UPD:
2488 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2489 return MCDisassembler::Fail;
2495 // AddrMode6 Base (register+alignment)
2496 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2497 return MCDisassembler::Fail;
2499 // AddrMode6 Offset (register)
2500 switch (Inst.getOpcode()) {
2503 Inst.addOperand(MCOperand::CreateReg(0));
2504 else if (Rm != 0xF) {
2505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2506 return MCDisassembler::Fail;
2509 case ARM::VST1d8wb_fixed:
2510 case ARM::VST1d16wb_fixed:
2511 case ARM::VST1d32wb_fixed:
2512 case ARM::VST1d64wb_fixed:
2513 case ARM::VST1q8wb_fixed:
2514 case ARM::VST1q16wb_fixed:
2515 case ARM::VST1q32wb_fixed:
2516 case ARM::VST1q64wb_fixed:
2517 case ARM::VST1d8Twb_fixed:
2518 case ARM::VST1d16Twb_fixed:
2519 case ARM::VST1d32Twb_fixed:
2520 case ARM::VST1d64Twb_fixed:
2521 case ARM::VST1d8Qwb_fixed:
2522 case ARM::VST1d16Qwb_fixed:
2523 case ARM::VST1d32Qwb_fixed:
2524 case ARM::VST1d64Qwb_fixed:
2525 case ARM::VST2d8wb_fixed:
2526 case ARM::VST2d16wb_fixed:
2527 case ARM::VST2d32wb_fixed:
2528 case ARM::VST2q8wb_fixed:
2529 case ARM::VST2q16wb_fixed:
2530 case ARM::VST2q32wb_fixed:
2531 case ARM::VST2b8wb_fixed:
2532 case ARM::VST2b16wb_fixed:
2533 case ARM::VST2b32wb_fixed:
2538 // First input register
2539 switch (Inst.getOpcode()) {
2544 case ARM::VST1q16wb_fixed:
2545 case ARM::VST1q16wb_register:
2546 case ARM::VST1q32wb_fixed:
2547 case ARM::VST1q32wb_register:
2548 case ARM::VST1q64wb_fixed:
2549 case ARM::VST1q64wb_register:
2550 case ARM::VST1q8wb_fixed:
2551 case ARM::VST1q8wb_register:
2555 case ARM::VST2d16wb_fixed:
2556 case ARM::VST2d16wb_register:
2557 case ARM::VST2d32wb_fixed:
2558 case ARM::VST2d32wb_register:
2559 case ARM::VST2d8wb_fixed:
2560 case ARM::VST2d8wb_register:
2561 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2562 return MCDisassembler::Fail;
2567 case ARM::VST2b16wb_fixed:
2568 case ARM::VST2b16wb_register:
2569 case ARM::VST2b32wb_fixed:
2570 case ARM::VST2b32wb_register:
2571 case ARM::VST2b8wb_fixed:
2572 case ARM::VST2b8wb_register:
2573 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2574 return MCDisassembler::Fail;
2577 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2578 return MCDisassembler::Fail;
2581 // Second input register
2582 switch (Inst.getOpcode()) {
2586 case ARM::VST3d8_UPD:
2587 case ARM::VST3d16_UPD:
2588 case ARM::VST3d32_UPD:
2592 case ARM::VST4d8_UPD:
2593 case ARM::VST4d16_UPD:
2594 case ARM::VST4d32_UPD:
2595 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2596 return MCDisassembler::Fail;
2601 case ARM::VST3q8_UPD:
2602 case ARM::VST3q16_UPD:
2603 case ARM::VST3q32_UPD:
2607 case ARM::VST4q8_UPD:
2608 case ARM::VST4q16_UPD:
2609 case ARM::VST4q32_UPD:
2610 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2611 return MCDisassembler::Fail;
2617 // Third input register
2618 switch (Inst.getOpcode()) {
2622 case ARM::VST3d8_UPD:
2623 case ARM::VST3d16_UPD:
2624 case ARM::VST3d32_UPD:
2628 case ARM::VST4d8_UPD:
2629 case ARM::VST4d16_UPD:
2630 case ARM::VST4d32_UPD:
2631 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2632 return MCDisassembler::Fail;
2637 case ARM::VST3q8_UPD:
2638 case ARM::VST3q16_UPD:
2639 case ARM::VST3q32_UPD:
2643 case ARM::VST4q8_UPD:
2644 case ARM::VST4q16_UPD:
2645 case ARM::VST4q32_UPD:
2646 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2647 return MCDisassembler::Fail;
2653 // Fourth input register
2654 switch (Inst.getOpcode()) {
2658 case ARM::VST4d8_UPD:
2659 case ARM::VST4d16_UPD:
2660 case ARM::VST4d32_UPD:
2661 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2662 return MCDisassembler::Fail;
2667 case ARM::VST4q8_UPD:
2668 case ARM::VST4q16_UPD:
2669 case ARM::VST4q32_UPD:
2670 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2671 return MCDisassembler::Fail;
2680 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2681 uint64_t Address, const void *Decoder) {
2682 DecodeStatus S = MCDisassembler::Success;
2684 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2685 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2686 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2687 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2688 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2689 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2691 align *= (1 << size);
2693 switch (Inst.getOpcode()) {
2694 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2695 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2696 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2697 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2698 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2699 return MCDisassembler::Fail;
2702 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2703 return MCDisassembler::Fail;
2707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2708 return MCDisassembler::Fail;
2711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2712 return MCDisassembler::Fail;
2713 Inst.addOperand(MCOperand::CreateImm(align));
2715 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2716 // variant encodes Rm == 0xf. Anything else is a register offset post-
2717 // increment and we need to add the register operand to the instruction.
2718 if (Rm != 0xD && Rm != 0xF &&
2719 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2720 return MCDisassembler::Fail;
2725 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2726 uint64_t Address, const void *Decoder) {
2727 DecodeStatus S = MCDisassembler::Success;
2729 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2730 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2731 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2732 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2733 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2734 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2737 switch (Inst.getOpcode()) {
2738 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2739 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2740 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2741 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2742 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2743 return MCDisassembler::Fail;
2745 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2746 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2747 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2748 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2749 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2750 return MCDisassembler::Fail;
2753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2754 return MCDisassembler::Fail;
2759 Inst.addOperand(MCOperand::CreateImm(0));
2761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2762 return MCDisassembler::Fail;
2763 Inst.addOperand(MCOperand::CreateImm(align));
2765 if (Rm != 0xD && Rm != 0xF) {
2766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2767 return MCDisassembler::Fail;
2773 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2774 uint64_t Address, const void *Decoder) {
2775 DecodeStatus S = MCDisassembler::Success;
2777 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2778 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2779 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2780 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2781 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2783 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2784 return MCDisassembler::Fail;
2785 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2786 return MCDisassembler::Fail;
2787 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2788 return MCDisassembler::Fail;
2790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2791 return MCDisassembler::Fail;
2794 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2795 return MCDisassembler::Fail;
2796 Inst.addOperand(MCOperand::CreateImm(0));
2799 Inst.addOperand(MCOperand::CreateReg(0));
2800 else if (Rm != 0xF) {
2801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2802 return MCDisassembler::Fail;
2808 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2809 uint64_t Address, const void *Decoder) {
2810 DecodeStatus S = MCDisassembler::Success;
2812 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2813 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2814 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2815 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2816 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2817 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2818 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2833 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2834 return MCDisassembler::Fail;
2835 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2836 return MCDisassembler::Fail;
2837 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2838 return MCDisassembler::Fail;
2839 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2840 return MCDisassembler::Fail;
2842 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2843 return MCDisassembler::Fail;
2846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2847 return MCDisassembler::Fail;
2848 Inst.addOperand(MCOperand::CreateImm(align));
2851 Inst.addOperand(MCOperand::CreateReg(0));
2852 else if (Rm != 0xF) {
2853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2854 return MCDisassembler::Fail;
2861 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
2862 uint64_t Address, const void *Decoder) {
2863 DecodeStatus S = MCDisassembler::Success;
2865 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2866 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2867 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2868 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2869 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2870 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2871 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2872 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2875 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2876 return MCDisassembler::Fail;
2878 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2879 return MCDisassembler::Fail;
2882 Inst.addOperand(MCOperand::CreateImm(imm));
2884 switch (Inst.getOpcode()) {
2885 case ARM::VORRiv4i16:
2886 case ARM::VORRiv2i32:
2887 case ARM::VBICiv4i16:
2888 case ARM::VBICiv2i32:
2889 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2890 return MCDisassembler::Fail;
2892 case ARM::VORRiv8i16:
2893 case ARM::VORRiv4i32:
2894 case ARM::VBICiv8i16:
2895 case ARM::VBICiv4i32:
2896 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2897 return MCDisassembler::Fail;
2906 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
2907 uint64_t Address, const void *Decoder) {
2908 DecodeStatus S = MCDisassembler::Success;
2910 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2911 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2912 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2913 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2914 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2916 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2917 return MCDisassembler::Fail;
2918 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2919 return MCDisassembler::Fail;
2920 Inst.addOperand(MCOperand::CreateImm(8 << size));
2925 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
2926 uint64_t Address, const void *Decoder) {
2927 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2928 return MCDisassembler::Success;
2931 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
2932 uint64_t Address, const void *Decoder) {
2933 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2934 return MCDisassembler::Success;
2937 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
2938 uint64_t Address, const void *Decoder) {
2939 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2940 return MCDisassembler::Success;
2943 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
2944 uint64_t Address, const void *Decoder) {
2945 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2946 return MCDisassembler::Success;
2949 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
2950 uint64_t Address, const void *Decoder) {
2951 DecodeStatus S = MCDisassembler::Success;
2953 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2954 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2955 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2956 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2957 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2958 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2959 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2961 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2962 return MCDisassembler::Fail;
2964 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2965 return MCDisassembler::Fail; // Writeback
2968 switch (Inst.getOpcode()) {
2971 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
2972 return MCDisassembler::Fail;
2975 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
2976 return MCDisassembler::Fail;
2979 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2980 return MCDisassembler::Fail;
2985 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
2986 uint64_t Address, const void *Decoder) {
2987 DecodeStatus S = MCDisassembler::Success;
2989 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2990 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2992 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2993 return MCDisassembler::Fail;
2995 switch(Inst.getOpcode()) {
2997 return MCDisassembler::Fail;
2999 break; // tADR does not explicitly represent the PC as an operand.
3001 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3005 Inst.addOperand(MCOperand::CreateImm(imm));
3009 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3010 uint64_t Address, const void *Decoder) {
3011 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3012 true, 2, Inst, Decoder))
3013 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3014 return MCDisassembler::Success;
3017 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3018 uint64_t Address, const void *Decoder) {
3019 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3020 true, 4, Inst, Decoder))
3021 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3022 return MCDisassembler::Success;
3025 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3026 uint64_t Address, const void *Decoder) {
3027 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<7>(Val<<1) + 4,
3028 true, 2, Inst, Decoder))
3029 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
3030 return MCDisassembler::Success;
3033 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3034 uint64_t Address, const void *Decoder) {
3035 DecodeStatus S = MCDisassembler::Success;
3037 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3038 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
3040 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3041 return MCDisassembler::Fail;
3042 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3043 return MCDisassembler::Fail;
3048 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3049 uint64_t Address, const void *Decoder) {
3050 DecodeStatus S = MCDisassembler::Success;
3052 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3053 unsigned imm = fieldFromInstruction32(Val, 3, 5);
3055 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3056 return MCDisassembler::Fail;
3057 Inst.addOperand(MCOperand::CreateImm(imm));
3062 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3063 uint64_t Address, const void *Decoder) {
3064 unsigned imm = Val << 2;
3066 Inst.addOperand(MCOperand::CreateImm(imm));
3067 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3069 return MCDisassembler::Success;
3072 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3073 uint64_t Address, const void *Decoder) {
3074 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3075 Inst.addOperand(MCOperand::CreateImm(Val));
3077 return MCDisassembler::Success;
3080 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3081 uint64_t Address, const void *Decoder) {
3082 DecodeStatus S = MCDisassembler::Success;
3084 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
3085 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
3086 unsigned imm = fieldFromInstruction32(Val, 0, 2);
3088 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3089 return MCDisassembler::Fail;
3090 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3091 return MCDisassembler::Fail;
3092 Inst.addOperand(MCOperand::CreateImm(imm));
3097 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3098 uint64_t Address, const void *Decoder) {
3099 DecodeStatus S = MCDisassembler::Success;
3101 switch (Inst.getOpcode()) {
3107 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3108 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3109 return MCDisassembler::Fail;
3113 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3115 switch (Inst.getOpcode()) {
3117 Inst.setOpcode(ARM::t2LDRBpci);
3120 Inst.setOpcode(ARM::t2LDRHpci);
3123 Inst.setOpcode(ARM::t2LDRSHpci);
3126 Inst.setOpcode(ARM::t2LDRSBpci);
3129 Inst.setOpcode(ARM::t2PLDi12);
3130 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3133 return MCDisassembler::Fail;
3136 int imm = fieldFromInstruction32(Insn, 0, 12);
3137 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
3138 Inst.addOperand(MCOperand::CreateImm(imm));
3143 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
3144 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
3145 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
3146 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3147 return MCDisassembler::Fail;
3152 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3153 uint64_t Address, const void *Decoder) {
3154 int imm = Val & 0xFF;
3155 if (!(Val & 0x100)) imm *= -1;
3156 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3158 return MCDisassembler::Success;
3161 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3162 uint64_t Address, const void *Decoder) {
3163 DecodeStatus S = MCDisassembler::Success;
3165 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3166 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3168 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3169 return MCDisassembler::Fail;
3170 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3171 return MCDisassembler::Fail;
3176 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3177 uint64_t Address, const void *Decoder) {
3178 DecodeStatus S = MCDisassembler::Success;
3180 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3181 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3183 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3184 return MCDisassembler::Fail;
3186 Inst.addOperand(MCOperand::CreateImm(imm));
3191 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3192 uint64_t Address, const void *Decoder) {
3193 int imm = Val & 0xFF;
3196 else if (!(Val & 0x100))
3198 Inst.addOperand(MCOperand::CreateImm(imm));
3200 return MCDisassembler::Success;
3204 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3205 uint64_t Address, const void *Decoder) {
3206 DecodeStatus S = MCDisassembler::Success;
3208 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3209 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3211 // Some instructions always use an additive offset.
3212 switch (Inst.getOpcode()) {
3227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3228 return MCDisassembler::Fail;
3229 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3230 return MCDisassembler::Fail;
3235 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3236 uint64_t Address, const void *Decoder) {
3237 DecodeStatus S = MCDisassembler::Success;
3239 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3240 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3241 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3242 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3244 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3248 return MCDisassembler::Fail;
3251 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3252 return MCDisassembler::Fail;
3255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3256 return MCDisassembler::Fail;
3259 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3260 return MCDisassembler::Fail;
3265 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3266 uint64_t Address, const void *Decoder) {
3267 DecodeStatus S = MCDisassembler::Success;
3269 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3270 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3273 return MCDisassembler::Fail;
3274 Inst.addOperand(MCOperand::CreateImm(imm));
3280 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3281 uint64_t Address, const void *Decoder) {
3282 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3284 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3285 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3286 Inst.addOperand(MCOperand::CreateImm(imm));
3288 return MCDisassembler::Success;
3291 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3292 uint64_t Address, const void *Decoder) {
3293 DecodeStatus S = MCDisassembler::Success;
3295 if (Inst.getOpcode() == ARM::tADDrSP) {
3296 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3297 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3300 return MCDisassembler::Fail;
3301 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3303 return MCDisassembler::Fail;
3304 } else if (Inst.getOpcode() == ARM::tADDspr) {
3305 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3307 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3308 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3310 return MCDisassembler::Fail;
3316 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3317 uint64_t Address, const void *Decoder) {
3318 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3319 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3321 Inst.addOperand(MCOperand::CreateImm(imod));
3322 Inst.addOperand(MCOperand::CreateImm(flags));
3324 return MCDisassembler::Success;
3327 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3328 uint64_t Address, const void *Decoder) {
3329 DecodeStatus S = MCDisassembler::Success;
3330 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3331 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3333 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3334 return MCDisassembler::Fail;
3335 Inst.addOperand(MCOperand::CreateImm(add));
3340 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3341 uint64_t Address, const void *Decoder) {
3342 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3343 // Note only one trailing zero not two. Also the J1 and J2 values are from
3344 // the encoded instruction. So here change to I1 and I2 values via:
3345 // I1 = NOT(J1 EOR S);
3346 // I2 = NOT(J2 EOR S);
3347 // and build the imm32 with two trailing zeros as documented:
3348 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3349 unsigned S = (Val >> 23) & 1;
3350 unsigned J1 = (Val >> 22) & 1;
3351 unsigned J2 = (Val >> 21) & 1;
3352 unsigned I1 = !(J1 ^ S);
3353 unsigned I2 = !(J2 ^ S);
3354 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3355 int imm32 = SignExtend32<25>(tmp << 1);
3357 if (!tryAddingSymbolicOperand(Address,
3358 (Address & ~2u) + imm32 + 4,
3359 true, 4, Inst, Decoder))
3360 Inst.addOperand(MCOperand::CreateImm(imm32));
3361 return MCDisassembler::Success;
3364 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3365 uint64_t Address, const void *Decoder) {
3366 if (Val == 0xA || Val == 0xB)
3367 return MCDisassembler::Fail;
3369 Inst.addOperand(MCOperand::CreateImm(Val));
3370 return MCDisassembler::Success;
3374 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3375 uint64_t Address, const void *Decoder) {
3376 DecodeStatus S = MCDisassembler::Success;
3378 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3379 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3381 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3383 return MCDisassembler::Fail;
3384 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3385 return MCDisassembler::Fail;
3390 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3391 uint64_t Address, const void *Decoder) {
3392 DecodeStatus S = MCDisassembler::Success;
3394 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3395 if (pred == 0xE || pred == 0xF) {
3396 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
3399 return MCDisassembler::Fail;
3401 Inst.setOpcode(ARM::t2DSB);
3404 Inst.setOpcode(ARM::t2DMB);
3407 Inst.setOpcode(ARM::t2ISB);
3411 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
3412 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3415 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3416 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3417 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3418 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3419 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3421 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3422 return MCDisassembler::Fail;
3423 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3424 return MCDisassembler::Fail;
3429 // Decode a shifted immediate operand. These basically consist
3430 // of an 8-bit value, and a 4-bit directive that specifies either
3431 // a splat operation or a rotation.
3432 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3433 uint64_t Address, const void *Decoder) {
3434 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3436 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3437 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3440 Inst.addOperand(MCOperand::CreateImm(imm));
3443 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3446 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3449 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3454 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3455 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3456 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3457 Inst.addOperand(MCOperand::CreateImm(imm));
3460 return MCDisassembler::Success;
3464 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3465 uint64_t Address, const void *Decoder){
3466 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<8>(Val<<1) + 4,
3467 true, 2, Inst, Decoder))
3468 Inst.addOperand(MCOperand::CreateImm(SignExtend32<8>(Val << 1)));
3469 return MCDisassembler::Success;
3472 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3473 uint64_t Address, const void *Decoder){
3474 // Val is passed in as S:J1:J2:imm10:imm11
3475 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3476 // the encoded instruction. So here change to I1 and I2 values via:
3477 // I1 = NOT(J1 EOR S);
3478 // I2 = NOT(J2 EOR S);
3479 // and build the imm32 with one trailing zero as documented:
3480 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3481 unsigned S = (Val >> 23) & 1;
3482 unsigned J1 = (Val >> 22) & 1;
3483 unsigned J2 = (Val >> 21) & 1;
3484 unsigned I1 = !(J1 ^ S);
3485 unsigned I2 = !(J2 ^ S);
3486 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3487 int imm32 = SignExtend32<25>(tmp << 1);
3489 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3490 true, 4, Inst, Decoder))
3491 Inst.addOperand(MCOperand::CreateImm(imm32));
3492 return MCDisassembler::Success;
3495 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3496 uint64_t Address, const void *Decoder) {
3499 return MCDisassembler::Fail;
3511 Inst.addOperand(MCOperand::CreateImm(Val));
3512 return MCDisassembler::Success;
3515 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3516 uint64_t Address, const void *Decoder) {
3517 if (!Val) return MCDisassembler::Fail;
3518 Inst.addOperand(MCOperand::CreateImm(Val));
3519 return MCDisassembler::Success;
3522 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3523 uint64_t Address, const void *Decoder) {
3524 DecodeStatus S = MCDisassembler::Success;
3526 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3527 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3528 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3530 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3532 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3533 return MCDisassembler::Fail;
3534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3535 return MCDisassembler::Fail;
3536 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3537 return MCDisassembler::Fail;
3538 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3539 return MCDisassembler::Fail;
3545 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
3546 uint64_t Address, const void *Decoder){
3547 DecodeStatus S = MCDisassembler::Success;
3549 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3550 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3551 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3552 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3554 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3555 return MCDisassembler::Fail;
3557 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3558 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3561 return MCDisassembler::Fail;
3562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3563 return MCDisassembler::Fail;
3564 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3565 return MCDisassembler::Fail;
3566 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3567 return MCDisassembler::Fail;
3572 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
3573 uint64_t Address, const void *Decoder) {
3574 DecodeStatus S = MCDisassembler::Success;
3576 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3577 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3578 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3579 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3580 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3581 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3583 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3585 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3586 return MCDisassembler::Fail;
3587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3588 return MCDisassembler::Fail;
3589 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3590 return MCDisassembler::Fail;
3591 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3592 return MCDisassembler::Fail;
3597 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
3598 uint64_t Address, const void *Decoder) {
3599 DecodeStatus S = MCDisassembler::Success;
3601 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3602 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3603 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3604 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3605 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3606 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3607 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3609 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3610 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3612 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3613 return MCDisassembler::Fail;
3614 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3615 return MCDisassembler::Fail;
3616 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3617 return MCDisassembler::Fail;
3618 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3619 return MCDisassembler::Fail;
3625 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
3626 uint64_t Address, const void *Decoder) {
3627 DecodeStatus S = MCDisassembler::Success;
3629 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3630 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3631 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3632 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3633 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3634 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3636 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3638 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3639 return MCDisassembler::Fail;
3640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3641 return MCDisassembler::Fail;
3642 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3643 return MCDisassembler::Fail;
3644 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3645 return MCDisassembler::Fail;
3650 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
3651 uint64_t Address, const void *Decoder) {
3652 DecodeStatus S = MCDisassembler::Success;
3654 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3655 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3656 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3657 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3658 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3659 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3661 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3664 return MCDisassembler::Fail;
3665 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3666 return MCDisassembler::Fail;
3667 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3668 return MCDisassembler::Fail;
3669 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3670 return MCDisassembler::Fail;
3675 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
3676 uint64_t Address, const void *Decoder) {
3677 DecodeStatus S = MCDisassembler::Success;
3679 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3680 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3681 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3682 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3683 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3689 return MCDisassembler::Fail;
3691 if (fieldFromInstruction32(Insn, 4, 1))
3692 return MCDisassembler::Fail; // UNDEFINED
3693 index = fieldFromInstruction32(Insn, 5, 3);
3696 if (fieldFromInstruction32(Insn, 5, 1))
3697 return MCDisassembler::Fail; // UNDEFINED
3698 index = fieldFromInstruction32(Insn, 6, 2);
3699 if (fieldFromInstruction32(Insn, 4, 1))
3703 if (fieldFromInstruction32(Insn, 6, 1))
3704 return MCDisassembler::Fail; // UNDEFINED
3705 index = fieldFromInstruction32(Insn, 7, 1);
3706 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3710 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3711 return MCDisassembler::Fail;
3712 if (Rm != 0xF) { // Writeback
3713 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3714 return MCDisassembler::Fail;
3716 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3717 return MCDisassembler::Fail;
3718 Inst.addOperand(MCOperand::CreateImm(align));
3721 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3722 return MCDisassembler::Fail;
3724 Inst.addOperand(MCOperand::CreateReg(0));
3727 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3728 return MCDisassembler::Fail;
3729 Inst.addOperand(MCOperand::CreateImm(index));
3734 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
3735 uint64_t Address, const void *Decoder) {
3736 DecodeStatus S = MCDisassembler::Success;
3738 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3739 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3740 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3741 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3742 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3748 return MCDisassembler::Fail;
3750 if (fieldFromInstruction32(Insn, 4, 1))
3751 return MCDisassembler::Fail; // UNDEFINED
3752 index = fieldFromInstruction32(Insn, 5, 3);
3755 if (fieldFromInstruction32(Insn, 5, 1))
3756 return MCDisassembler::Fail; // UNDEFINED
3757 index = fieldFromInstruction32(Insn, 6, 2);
3758 if (fieldFromInstruction32(Insn, 4, 1))
3762 if (fieldFromInstruction32(Insn, 6, 1))
3763 return MCDisassembler::Fail; // UNDEFINED
3764 index = fieldFromInstruction32(Insn, 7, 1);
3765 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3769 if (Rm != 0xF) { // Writeback
3770 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3771 return MCDisassembler::Fail;
3773 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3774 return MCDisassembler::Fail;
3775 Inst.addOperand(MCOperand::CreateImm(align));
3778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3779 return MCDisassembler::Fail;
3781 Inst.addOperand(MCOperand::CreateReg(0));
3784 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3785 return MCDisassembler::Fail;
3786 Inst.addOperand(MCOperand::CreateImm(index));
3792 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
3793 uint64_t Address, const void *Decoder) {
3794 DecodeStatus S = MCDisassembler::Success;
3796 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3797 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3798 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3799 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3800 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3807 return MCDisassembler::Fail;
3809 index = fieldFromInstruction32(Insn, 5, 3);
3810 if (fieldFromInstruction32(Insn, 4, 1))
3814 index = fieldFromInstruction32(Insn, 6, 2);
3815 if (fieldFromInstruction32(Insn, 4, 1))
3817 if (fieldFromInstruction32(Insn, 5, 1))
3821 if (fieldFromInstruction32(Insn, 5, 1))
3822 return MCDisassembler::Fail; // UNDEFINED
3823 index = fieldFromInstruction32(Insn, 7, 1);
3824 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3826 if (fieldFromInstruction32(Insn, 6, 1))
3831 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3832 return MCDisassembler::Fail;
3833 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3834 return MCDisassembler::Fail;
3835 if (Rm != 0xF) { // Writeback
3836 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3837 return MCDisassembler::Fail;
3839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3840 return MCDisassembler::Fail;
3841 Inst.addOperand(MCOperand::CreateImm(align));
3844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3845 return MCDisassembler::Fail;
3847 Inst.addOperand(MCOperand::CreateReg(0));
3850 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3851 return MCDisassembler::Fail;
3852 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3853 return MCDisassembler::Fail;
3854 Inst.addOperand(MCOperand::CreateImm(index));
3859 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
3860 uint64_t Address, const void *Decoder) {
3861 DecodeStatus S = MCDisassembler::Success;
3863 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3864 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3865 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3866 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3867 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3874 return MCDisassembler::Fail;
3876 index = fieldFromInstruction32(Insn, 5, 3);
3877 if (fieldFromInstruction32(Insn, 4, 1))
3881 index = fieldFromInstruction32(Insn, 6, 2);
3882 if (fieldFromInstruction32(Insn, 4, 1))
3884 if (fieldFromInstruction32(Insn, 5, 1))
3888 if (fieldFromInstruction32(Insn, 5, 1))
3889 return MCDisassembler::Fail; // UNDEFINED
3890 index = fieldFromInstruction32(Insn, 7, 1);
3891 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3893 if (fieldFromInstruction32(Insn, 6, 1))
3898 if (Rm != 0xF) { // Writeback
3899 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3900 return MCDisassembler::Fail;
3902 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3903 return MCDisassembler::Fail;
3904 Inst.addOperand(MCOperand::CreateImm(align));
3907 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3908 return MCDisassembler::Fail;
3910 Inst.addOperand(MCOperand::CreateReg(0));
3913 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3914 return MCDisassembler::Fail;
3915 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3916 return MCDisassembler::Fail;
3917 Inst.addOperand(MCOperand::CreateImm(index));
3923 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
3924 uint64_t Address, const void *Decoder) {
3925 DecodeStatus S = MCDisassembler::Success;
3927 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3928 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3929 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3930 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3931 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3938 return MCDisassembler::Fail;
3940 if (fieldFromInstruction32(Insn, 4, 1))
3941 return MCDisassembler::Fail; // UNDEFINED
3942 index = fieldFromInstruction32(Insn, 5, 3);
3945 if (fieldFromInstruction32(Insn, 4, 1))
3946 return MCDisassembler::Fail; // UNDEFINED
3947 index = fieldFromInstruction32(Insn, 6, 2);
3948 if (fieldFromInstruction32(Insn, 5, 1))
3952 if (fieldFromInstruction32(Insn, 4, 2))
3953 return MCDisassembler::Fail; // UNDEFINED
3954 index = fieldFromInstruction32(Insn, 7, 1);
3955 if (fieldFromInstruction32(Insn, 6, 1))
3960 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3961 return MCDisassembler::Fail;
3962 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3963 return MCDisassembler::Fail;
3964 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3965 return MCDisassembler::Fail;
3967 if (Rm != 0xF) { // Writeback
3968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3969 return MCDisassembler::Fail;
3971 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3972 return MCDisassembler::Fail;
3973 Inst.addOperand(MCOperand::CreateImm(align));
3976 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3977 return MCDisassembler::Fail;
3979 Inst.addOperand(MCOperand::CreateReg(0));
3982 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3983 return MCDisassembler::Fail;
3984 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3985 return MCDisassembler::Fail;
3986 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3987 return MCDisassembler::Fail;
3988 Inst.addOperand(MCOperand::CreateImm(index));
3993 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
3994 uint64_t Address, const void *Decoder) {
3995 DecodeStatus S = MCDisassembler::Success;
3997 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3998 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3999 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4000 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4001 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4008 return MCDisassembler::Fail;
4010 if (fieldFromInstruction32(Insn, 4, 1))
4011 return MCDisassembler::Fail; // UNDEFINED
4012 index = fieldFromInstruction32(Insn, 5, 3);
4015 if (fieldFromInstruction32(Insn, 4, 1))
4016 return MCDisassembler::Fail; // UNDEFINED
4017 index = fieldFromInstruction32(Insn, 6, 2);
4018 if (fieldFromInstruction32(Insn, 5, 1))
4022 if (fieldFromInstruction32(Insn, 4, 2))
4023 return MCDisassembler::Fail; // UNDEFINED
4024 index = fieldFromInstruction32(Insn, 7, 1);
4025 if (fieldFromInstruction32(Insn, 6, 1))
4030 if (Rm != 0xF) { // Writeback
4031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4032 return MCDisassembler::Fail;
4034 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4035 return MCDisassembler::Fail;
4036 Inst.addOperand(MCOperand::CreateImm(align));
4039 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4040 return MCDisassembler::Fail;
4042 Inst.addOperand(MCOperand::CreateReg(0));
4045 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4046 return MCDisassembler::Fail;
4047 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4048 return MCDisassembler::Fail;
4049 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4050 return MCDisassembler::Fail;
4051 Inst.addOperand(MCOperand::CreateImm(index));
4057 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4058 uint64_t Address, const void *Decoder) {
4059 DecodeStatus S = MCDisassembler::Success;
4061 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4062 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4063 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4064 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4065 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4072 return MCDisassembler::Fail;
4074 if (fieldFromInstruction32(Insn, 4, 1))
4076 index = fieldFromInstruction32(Insn, 5, 3);
4079 if (fieldFromInstruction32(Insn, 4, 1))
4081 index = fieldFromInstruction32(Insn, 6, 2);
4082 if (fieldFromInstruction32(Insn, 5, 1))
4086 if (fieldFromInstruction32(Insn, 4, 2))
4087 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4088 index = fieldFromInstruction32(Insn, 7, 1);
4089 if (fieldFromInstruction32(Insn, 6, 1))
4094 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4095 return MCDisassembler::Fail;
4096 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4097 return MCDisassembler::Fail;
4098 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4099 return MCDisassembler::Fail;
4100 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4101 return MCDisassembler::Fail;
4103 if (Rm != 0xF) { // Writeback
4104 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4105 return MCDisassembler::Fail;
4107 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4108 return MCDisassembler::Fail;
4109 Inst.addOperand(MCOperand::CreateImm(align));
4112 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4113 return MCDisassembler::Fail;
4115 Inst.addOperand(MCOperand::CreateReg(0));
4118 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4119 return MCDisassembler::Fail;
4120 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4121 return MCDisassembler::Fail;
4122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4123 return MCDisassembler::Fail;
4124 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4125 return MCDisassembler::Fail;
4126 Inst.addOperand(MCOperand::CreateImm(index));
4131 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4132 uint64_t Address, const void *Decoder) {
4133 DecodeStatus S = MCDisassembler::Success;
4135 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4136 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4137 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4138 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4139 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4146 return MCDisassembler::Fail;
4148 if (fieldFromInstruction32(Insn, 4, 1))
4150 index = fieldFromInstruction32(Insn, 5, 3);
4153 if (fieldFromInstruction32(Insn, 4, 1))
4155 index = fieldFromInstruction32(Insn, 6, 2);
4156 if (fieldFromInstruction32(Insn, 5, 1))
4160 if (fieldFromInstruction32(Insn, 4, 2))
4161 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4162 index = fieldFromInstruction32(Insn, 7, 1);
4163 if (fieldFromInstruction32(Insn, 6, 1))
4168 if (Rm != 0xF) { // Writeback
4169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4170 return MCDisassembler::Fail;
4172 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4173 return MCDisassembler::Fail;
4174 Inst.addOperand(MCOperand::CreateImm(align));
4177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4178 return MCDisassembler::Fail;
4180 Inst.addOperand(MCOperand::CreateReg(0));
4183 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4184 return MCDisassembler::Fail;
4185 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4186 return MCDisassembler::Fail;
4187 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4188 return MCDisassembler::Fail;
4189 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4190 return MCDisassembler::Fail;
4191 Inst.addOperand(MCOperand::CreateImm(index));
4196 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4197 uint64_t Address, const void *Decoder) {
4198 DecodeStatus S = MCDisassembler::Success;
4199 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4200 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4201 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4202 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4203 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4205 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4206 S = MCDisassembler::SoftFail;
4208 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4209 return MCDisassembler::Fail;
4210 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4211 return MCDisassembler::Fail;
4212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4213 return MCDisassembler::Fail;
4214 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4215 return MCDisassembler::Fail;
4216 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4217 return MCDisassembler::Fail;
4222 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4223 uint64_t Address, const void *Decoder) {
4224 DecodeStatus S = MCDisassembler::Success;
4225 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4226 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4227 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4228 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4229 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
4231 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4232 S = MCDisassembler::SoftFail;
4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4235 return MCDisassembler::Fail;
4236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4237 return MCDisassembler::Fail;
4238 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4239 return MCDisassembler::Fail;
4240 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4241 return MCDisassembler::Fail;
4242 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4243 return MCDisassembler::Fail;
4248 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4249 uint64_t Address, const void *Decoder) {
4250 DecodeStatus S = MCDisassembler::Success;
4251 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4252 unsigned mask = fieldFromInstruction16(Insn, 0, 4);
4256 S = MCDisassembler::SoftFail;
4261 S = MCDisassembler::SoftFail;
4264 Inst.addOperand(MCOperand::CreateImm(pred));
4265 Inst.addOperand(MCOperand::CreateImm(mask));
4270 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4271 uint64_t Address, const void *Decoder) {
4272 DecodeStatus S = MCDisassembler::Success;
4274 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4275 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4276 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4277 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4278 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4279 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4280 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4281 bool writeback = (W == 1) | (P == 0);
4283 addr |= (U << 8) | (Rn << 9);
4285 if (writeback && (Rn == Rt || Rn == Rt2))
4286 Check(S, MCDisassembler::SoftFail);
4288 Check(S, MCDisassembler::SoftFail);
4291 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4292 return MCDisassembler::Fail;
4294 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4295 return MCDisassembler::Fail;
4296 // Writeback operand
4297 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4298 return MCDisassembler::Fail;
4300 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4301 return MCDisassembler::Fail;
4307 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4308 uint64_t Address, const void *Decoder) {
4309 DecodeStatus S = MCDisassembler::Success;
4311 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4312 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4313 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4314 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4315 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4316 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4317 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4318 bool writeback = (W == 1) | (P == 0);
4320 addr |= (U << 8) | (Rn << 9);
4322 if (writeback && (Rn == Rt || Rn == Rt2))
4323 Check(S, MCDisassembler::SoftFail);
4325 // Writeback operand
4326 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4327 return MCDisassembler::Fail;
4329 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4330 return MCDisassembler::Fail;
4332 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4333 return MCDisassembler::Fail;
4335 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4336 return MCDisassembler::Fail;
4341 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4342 uint64_t Address, const void *Decoder) {
4343 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4344 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4345 if (sign1 != sign2) return MCDisassembler::Fail;
4347 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4348 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4349 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4351 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4353 return MCDisassembler::Success;
4356 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4358 const void *Decoder) {
4359 DecodeStatus S = MCDisassembler::Success;
4361 // Shift of "asr #32" is not allowed in Thumb2 mode.
4362 if (Val == 0x20) S = MCDisassembler::SoftFail;
4363 Inst.addOperand(MCOperand::CreateImm(Val));
4367 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4368 uint64_t Address, const void *Decoder) {
4369 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4370 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4371 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4372 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4375 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4377 DecodeStatus S = MCDisassembler::Success;
4379 if (Rt == Rn || Rn == Rt2)
4380 S = MCDisassembler::SoftFail;
4382 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4383 return MCDisassembler::Fail;
4384 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4385 return MCDisassembler::Fail;
4386 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4387 return MCDisassembler::Fail;
4388 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4389 return MCDisassembler::Fail;
4394 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4395 uint64_t Address, const void *Decoder) {
4396 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4397 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4398 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4399 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4400 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4401 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4403 DecodeStatus S = MCDisassembler::Success;
4405 // VMOVv2f32 is ambiguous with these decodings.
4406 if (!(imm & 0x38) && cmode == 0xF) {
4407 Inst.setOpcode(ARM::VMOVv2f32);
4408 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4411 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4413 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4414 return MCDisassembler::Fail;
4415 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4416 return MCDisassembler::Fail;
4417 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4422 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4423 uint64_t Address, const void *Decoder) {
4424 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4425 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4426 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4427 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4428 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4429 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4431 DecodeStatus S = MCDisassembler::Success;
4433 // VMOVv4f32 is ambiguous with these decodings.
4434 if (!(imm & 0x38) && cmode == 0xF) {
4435 Inst.setOpcode(ARM::VMOVv4f32);
4436 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4439 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4441 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4442 return MCDisassembler::Fail;
4443 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4444 return MCDisassembler::Fail;
4445 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4450 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4451 uint64_t Address, const void *Decoder) {
4452 DecodeStatus S = MCDisassembler::Success;
4454 unsigned Rn = fieldFromInstruction32(Val, 16, 4);
4455 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4456 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
4457 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
4458 unsigned Cond = fieldFromInstruction32(Val, 28, 4);
4460 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
4461 S = MCDisassembler::SoftFail;
4463 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4464 return MCDisassembler::Fail;
4465 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4466 return MCDisassembler::Fail;
4467 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4468 return MCDisassembler::Fail;
4469 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4470 return MCDisassembler::Fail;
4471 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4472 return MCDisassembler::Fail;
4477 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4478 uint64_t Address, const void *Decoder) {
4480 DecodeStatus S = MCDisassembler::Success;
4482 unsigned CRm = fieldFromInstruction32(Val, 0, 4);
4483 unsigned opc1 = fieldFromInstruction32(Val, 4, 4);
4484 unsigned cop = fieldFromInstruction32(Val, 8, 4);
4485 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4486 unsigned Rt2 = fieldFromInstruction32(Val, 16, 4);
4488 if ((cop & ~0x1) == 0xa)
4489 return MCDisassembler::Fail;
4492 S = MCDisassembler::SoftFail;
4494 Inst.addOperand(MCOperand::CreateImm(cop));
4495 Inst.addOperand(MCOperand::CreateImm(opc1));
4496 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4497 return MCDisassembler::Fail;
4498 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4499 return MCDisassembler::Fail;
4500 Inst.addOperand(MCOperand::CreateImm(CRm));