1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "llvm/MC/MCDisassembler.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/LEB128.h"
25 #include "llvm/Support/MemoryObject.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
35 // Handles the condition code status of instructions in IT blocks
39 // Returns the condition code for instruction in IT block
41 unsigned CC = ARMCC::AL;
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = CountTrailingZeros_32(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 ITStates.push_back(CCBits);
77 ITStates.push_back(CCBits ^ 1);
79 ITStates.push_back(CCBits);
83 std::vector<unsigned char> ITStates;
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
91 /// Constructor - Initializes the disassembler.
93 ARMDisassembler(const MCSubtargetInfo &STI) :
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr,
103 const MemoryObject ®ion,
105 raw_ostream &vStream,
106 raw_ostream &cStream) const;
109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
110 class ThumbDisassembler : public MCDisassembler {
112 /// Constructor - Initializes the disassembler.
114 ThumbDisassembler(const MCSubtargetInfo &STI) :
115 MCDisassembler(STI) {
118 ~ThumbDisassembler() {
121 /// getInstruction - See MCDisassembler.
122 DecodeStatus getInstruction(MCInst &instr,
124 const MemoryObject ®ion,
126 raw_ostream &vStream,
127 raw_ostream &cStream) const;
130 mutable ITStatus ITBlock;
131 DecodeStatus AddThumbPredicate(MCInst&) const;
132 void UpdateThumbVFPPredicate(MCInst&) const;
136 static bool Check(DecodeStatus &Out, DecodeStatus In) {
138 case MCDisassembler::Success:
139 // Out stays the same.
141 case MCDisassembler::SoftFail:
144 case MCDisassembler::Fail:
148 llvm_unreachable("Invalid DecodeStatus!");
152 // Forward declare these because the autogenerated code will reference them.
153 // Definitions are further down.
154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
157 unsigned RegNo, uint64_t Address,
158 const void *Decoder);
159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
160 unsigned RegNo, uint64_t Address,
161 const void *Decoder);
162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
177 const void *Decoder);
178 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
183 unsigned RegNo, uint64_t Address,
184 const void *Decoder);
186 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
206 const void *Decoder);
207 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
219 const void *Decoder);
220 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVST1Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVST2Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVST3Instruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVST4Instruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
323 const void *Decoder);
326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
351 uint64_t Address, const void *Decoder);
352 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
353 uint64_t Address, const void *Decoder);
354 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
387 uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
390 uint64_t Address, const void *Decoder);
391 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
392 uint64_t Address, const void *Decoder);
393 #include "ARMGenDisassemblerTables.inc"
395 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
396 return new ARMDisassembler(STI);
399 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
400 return new ThumbDisassembler(STI);
403 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
404 const MemoryObject &Region,
407 raw_ostream &cs) const {
412 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
413 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
415 // We want to read exactly 4 bytes of data.
416 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
418 return MCDisassembler::Fail;
421 // Encoded as a small-endian 32-bit word in the stream.
422 uint32_t insn = (bytes[3] << 24) |
427 // Calling the auto-generated decoder function.
428 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
430 if (result != MCDisassembler::Fail) {
435 // VFP and NEON instructions, similarly, are shared between ARM
438 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
439 if (result != MCDisassembler::Fail) {
445 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
447 if (result != MCDisassembler::Fail) {
449 // Add a fake predicate operand, because we share these instruction
450 // definitions with Thumb2 where these instructions are predicable.
451 if (!DecodePredicateOperand(MI, 0xE, Address, this))
452 return MCDisassembler::Fail;
457 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
459 if (result != MCDisassembler::Fail) {
461 // Add a fake predicate operand, because we share these instruction
462 // definitions with Thumb2 where these instructions are predicable.
463 if (!DecodePredicateOperand(MI, 0xE, Address, this))
464 return MCDisassembler::Fail;
469 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
471 if (result != MCDisassembler::Fail) {
473 // Add a fake predicate operand, because we share these instruction
474 // definitions with Thumb2 where these instructions are predicable.
475 if (!DecodePredicateOperand(MI, 0xE, Address, this))
476 return MCDisassembler::Fail;
483 return MCDisassembler::Fail;
487 extern const MCInstrDesc ARMInsts[];
490 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
491 /// immediate Value in the MCInst. The immediate Value has had any PC
492 /// adjustment made by the caller. If the instruction is a branch instruction
493 /// then isBranch is true, else false. If the getOpInfo() function was set as
494 /// part of the setupForSymbolicDisassembly() call then that function is called
495 /// to get any symbolic information at the Address for this instruction. If
496 /// that returns non-zero then the symbolic information it returns is used to
497 /// create an MCExpr and that is added as an operand to the MCInst. If
498 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
499 /// Value is done and if a symbol is found an MCExpr is created with that, else
500 /// an MCExpr with Value is created. This function returns true if it adds an
501 /// operand to the MCInst and false otherwise.
502 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
503 bool isBranch, uint64_t InstSize,
504 MCInst &MI, const void *Decoder) {
505 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
506 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
507 struct LLVMOpInfo1 SymbolicOp;
508 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
509 SymbolicOp.Value = Value;
510 void *DisInfo = Dis->getDisInfoBlock();
513 !getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
514 // Clear SymbolicOp.Value from above and also all other fields.
515 memset(&SymbolicOp, '\0', sizeof(struct LLVMOpInfo1));
516 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
519 uint64_t ReferenceType;
521 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
523 ReferenceType = LLVMDisassembler_ReferenceType_InOut_None;
524 const char *ReferenceName;
525 uint64_t SymbolValue = 0x00000000ffffffffULL & Value;
526 const char *Name = SymbolLookUp(DisInfo, SymbolValue, &ReferenceType,
527 Address, &ReferenceName);
529 SymbolicOp.AddSymbol.Name = Name;
530 SymbolicOp.AddSymbol.Present = true;
532 // For branches always create an MCExpr so it gets printed as hex address.
534 SymbolicOp.Value = Value;
536 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
537 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
538 if (!Name && !isBranch)
542 MCContext *Ctx = Dis->getMCContext();
543 const MCExpr *Add = NULL;
544 if (SymbolicOp.AddSymbol.Present) {
545 if (SymbolicOp.AddSymbol.Name) {
546 StringRef Name(SymbolicOp.AddSymbol.Name);
547 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
548 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
550 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
554 const MCExpr *Sub = NULL;
555 if (SymbolicOp.SubtractSymbol.Present) {
556 if (SymbolicOp.SubtractSymbol.Name) {
557 StringRef Name(SymbolicOp.SubtractSymbol.Name);
558 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
559 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
561 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
565 const MCExpr *Off = NULL;
566 if (SymbolicOp.Value != 0)
567 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
573 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
575 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
577 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
582 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
589 Expr = MCConstantExpr::Create(0, *Ctx);
592 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
593 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
594 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
595 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
596 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
597 MI.addOperand(MCOperand::CreateExpr(Expr));
599 llvm_unreachable("bad SymbolicOp.VariantKind");
604 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
605 /// referenced by a load instruction with the base register that is the Pc.
606 /// These can often be values in a literal pool near the Address of the
607 /// instruction. The Address of the instruction and its immediate Value are
608 /// used as a possible literal pool entry. The SymbolLookUp call back will
609 /// return the name of a symbol referenced by the literal pool's entry if
610 /// the referenced address is that of a symbol. Or it will return a pointer to
611 /// a literal 'C' string if the referenced address of the literal pool's entry
612 /// is an address into a section with 'C' string literals.
613 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
614 const void *Decoder) {
615 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
616 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
618 void *DisInfo = Dis->getDisInfoBlock();
619 uint64_t ReferenceType;
620 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
621 const char *ReferenceName;
622 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
623 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
624 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
625 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
629 // Thumb1 instructions don't have explicit S bits. Rather, they
630 // implicitly set CPSR. Since it's not represented in the encoding, the
631 // auto-generated decoder won't inject the CPSR operand. We need to fix
632 // that as a post-pass.
633 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
634 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
635 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
636 MCInst::iterator I = MI.begin();
637 for (unsigned i = 0; i < NumOps; ++i, ++I) {
638 if (I == MI.end()) break;
639 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
640 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
641 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
646 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
649 // Most Thumb instructions don't have explicit predicates in the
650 // encoding, but rather get their predicates from IT context. We need
651 // to fix up the predicate operands using this context information as a
653 MCDisassembler::DecodeStatus
654 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
655 MCDisassembler::DecodeStatus S = Success;
657 // A few instructions actually have predicates encoded in them. Don't
658 // try to overwrite it if we're seeing one of those.
659 switch (MI.getOpcode()) {
670 // Some instructions (mostly conditional branches) are not
671 // allowed in IT blocks.
672 if (ITBlock.instrInITBlock())
681 // Some instructions (mostly unconditional branches) can
682 // only appears at the end of, or outside of, an IT.
683 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
690 // If we're in an IT block, base the predicate on that. Otherwise,
691 // assume a predicate of AL.
693 CC = ITBlock.getITCC();
696 if (ITBlock.instrInITBlock())
697 ITBlock.advanceITState();
699 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
700 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
701 MCInst::iterator I = MI.begin();
702 for (unsigned i = 0; i < NumOps; ++i, ++I) {
703 if (I == MI.end()) break;
704 if (OpInfo[i].isPredicate()) {
705 I = MI.insert(I, MCOperand::CreateImm(CC));
708 MI.insert(I, MCOperand::CreateReg(0));
710 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
715 I = MI.insert(I, MCOperand::CreateImm(CC));
718 MI.insert(I, MCOperand::CreateReg(0));
720 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
725 // Thumb VFP instructions are a special case. Because we share their
726 // encodings between ARM and Thumb modes, and they are predicable in ARM
727 // mode, the auto-generated decoder will give them an (incorrect)
728 // predicate operand. We need to rewrite these operands based on the IT
729 // context as a post-pass.
730 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
732 CC = ITBlock.getITCC();
733 if (ITBlock.instrInITBlock())
734 ITBlock.advanceITState();
736 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
737 MCInst::iterator I = MI.begin();
738 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
739 for (unsigned i = 0; i < NumOps; ++i, ++I) {
740 if (OpInfo[i].isPredicate() ) {
746 I->setReg(ARM::CPSR);
752 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
753 const MemoryObject &Region,
756 raw_ostream &cs) const {
761 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
762 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
764 // We want to read exactly 2 bytes of data.
765 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
767 return MCDisassembler::Fail;
770 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
771 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
773 if (result != MCDisassembler::Fail) {
775 Check(result, AddThumbPredicate(MI));
780 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
784 bool InITBlock = ITBlock.instrInITBlock();
785 Check(result, AddThumbPredicate(MI));
786 AddThumb1SBit(MI, InITBlock);
791 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
793 if (result != MCDisassembler::Fail) {
796 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
797 // the Thumb predicate.
798 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
799 result = MCDisassembler::SoftFail;
801 Check(result, AddThumbPredicate(MI));
803 // If we find an IT instruction, we need to parse its condition
804 // code and mask operands so that we can apply them correctly
805 // to the subsequent instructions.
806 if (MI.getOpcode() == ARM::t2IT) {
808 unsigned Firstcond = MI.getOperand(0).getImm();
809 unsigned Mask = MI.getOperand(1).getImm();
810 ITBlock.setITState(Firstcond, Mask);
816 // We want to read exactly 4 bytes of data.
817 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
819 return MCDisassembler::Fail;
822 uint32_t insn32 = (bytes[3] << 8) |
827 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
829 if (result != MCDisassembler::Fail) {
831 bool InITBlock = ITBlock.instrInITBlock();
832 Check(result, AddThumbPredicate(MI));
833 AddThumb1SBit(MI, InITBlock);
838 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
840 if (result != MCDisassembler::Fail) {
842 Check(result, AddThumbPredicate(MI));
847 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
848 if (result != MCDisassembler::Fail) {
850 UpdateThumbVFPPredicate(MI);
855 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
857 if (result != MCDisassembler::Fail) {
859 Check(result, AddThumbPredicate(MI));
863 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
865 uint32_t NEONLdStInsn = insn32;
866 NEONLdStInsn &= 0xF0FFFFFF;
867 NEONLdStInsn |= 0x04000000;
868 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
870 if (result != MCDisassembler::Fail) {
872 Check(result, AddThumbPredicate(MI));
877 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
879 uint32_t NEONDataInsn = insn32;
880 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
881 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
882 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
883 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
885 if (result != MCDisassembler::Fail) {
887 Check(result, AddThumbPredicate(MI));
893 return MCDisassembler::Fail;
897 extern "C" void LLVMInitializeARMDisassembler() {
898 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
899 createARMDisassembler);
900 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
901 createThumbDisassembler);
904 static const uint16_t GPRDecoderTable[] = {
905 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
906 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
907 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
908 ARM::R12, ARM::SP, ARM::LR, ARM::PC
911 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
912 uint64_t Address, const void *Decoder) {
914 return MCDisassembler::Fail;
916 unsigned Register = GPRDecoderTable[RegNo];
917 Inst.addOperand(MCOperand::CreateReg(Register));
918 return MCDisassembler::Success;
922 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
923 uint64_t Address, const void *Decoder) {
924 DecodeStatus S = MCDisassembler::Success;
927 S = MCDisassembler::SoftFail;
929 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
935 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
936 uint64_t Address, const void *Decoder) {
937 DecodeStatus S = MCDisassembler::Success;
941 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
942 return MCDisassembler::Success;
945 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
949 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
950 uint64_t Address, const void *Decoder) {
952 return MCDisassembler::Fail;
953 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
956 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
957 uint64_t Address, const void *Decoder) {
958 unsigned Register = 0;
979 return MCDisassembler::Fail;
982 Inst.addOperand(MCOperand::CreateReg(Register));
983 return MCDisassembler::Success;
986 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
987 uint64_t Address, const void *Decoder) {
988 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
989 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
992 static const uint16_t SPRDecoderTable[] = {
993 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
994 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
995 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
996 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
997 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
998 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
999 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1000 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1003 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1004 uint64_t Address, const void *Decoder) {
1006 return MCDisassembler::Fail;
1008 unsigned Register = SPRDecoderTable[RegNo];
1009 Inst.addOperand(MCOperand::CreateReg(Register));
1010 return MCDisassembler::Success;
1013 static const uint16_t DPRDecoderTable[] = {
1014 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1015 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1016 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1017 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1018 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1019 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1020 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1021 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1024 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1025 uint64_t Address, const void *Decoder) {
1027 return MCDisassembler::Fail;
1029 unsigned Register = DPRDecoderTable[RegNo];
1030 Inst.addOperand(MCOperand::CreateReg(Register));
1031 return MCDisassembler::Success;
1034 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1035 uint64_t Address, const void *Decoder) {
1037 return MCDisassembler::Fail;
1038 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1042 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1043 uint64_t Address, const void *Decoder) {
1045 return MCDisassembler::Fail;
1046 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1049 static const uint16_t QPRDecoderTable[] = {
1050 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1051 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1052 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1053 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1057 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1058 uint64_t Address, const void *Decoder) {
1059 if (RegNo > 31 || (RegNo & 1) != 0)
1060 return MCDisassembler::Fail;
1063 unsigned Register = QPRDecoderTable[RegNo];
1064 Inst.addOperand(MCOperand::CreateReg(Register));
1065 return MCDisassembler::Success;
1068 static const uint16_t DPairDecoderTable[] = {
1069 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1070 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1071 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1072 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1073 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1077 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1078 uint64_t Address, const void *Decoder) {
1080 return MCDisassembler::Fail;
1082 unsigned Register = DPairDecoderTable[RegNo];
1083 Inst.addOperand(MCOperand::CreateReg(Register));
1084 return MCDisassembler::Success;
1087 static const uint16_t DPairSpacedDecoderTable[] = {
1088 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1089 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1090 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1091 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1092 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1093 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1094 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1095 ARM::D28_D30, ARM::D29_D31
1098 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1101 const void *Decoder) {
1103 return MCDisassembler::Fail;
1105 unsigned Register = DPairSpacedDecoderTable[RegNo];
1106 Inst.addOperand(MCOperand::CreateReg(Register));
1107 return MCDisassembler::Success;
1110 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1111 uint64_t Address, const void *Decoder) {
1112 if (Val == 0xF) return MCDisassembler::Fail;
1113 // AL predicate is not allowed on Thumb1 branches.
1114 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1115 return MCDisassembler::Fail;
1116 Inst.addOperand(MCOperand::CreateImm(Val));
1117 if (Val == ARMCC::AL) {
1118 Inst.addOperand(MCOperand::CreateReg(0));
1120 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1121 return MCDisassembler::Success;
1124 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1125 uint64_t Address, const void *Decoder) {
1127 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1129 Inst.addOperand(MCOperand::CreateReg(0));
1130 return MCDisassembler::Success;
1133 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1134 uint64_t Address, const void *Decoder) {
1135 uint32_t imm = Val & 0xFF;
1136 uint32_t rot = (Val & 0xF00) >> 7;
1137 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1138 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1139 return MCDisassembler::Success;
1142 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1143 uint64_t Address, const void *Decoder) {
1144 DecodeStatus S = MCDisassembler::Success;
1146 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1147 unsigned type = fieldFromInstruction(Val, 5, 2);
1148 unsigned imm = fieldFromInstruction(Val, 7, 5);
1150 // Register-immediate
1151 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1152 return MCDisassembler::Fail;
1154 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1157 Shift = ARM_AM::lsl;
1160 Shift = ARM_AM::lsr;
1163 Shift = ARM_AM::asr;
1166 Shift = ARM_AM::ror;
1170 if (Shift == ARM_AM::ror && imm == 0)
1171 Shift = ARM_AM::rrx;
1173 unsigned Op = Shift | (imm << 3);
1174 Inst.addOperand(MCOperand::CreateImm(Op));
1179 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1180 uint64_t Address, const void *Decoder) {
1181 DecodeStatus S = MCDisassembler::Success;
1183 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1184 unsigned type = fieldFromInstruction(Val, 5, 2);
1185 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1187 // Register-register
1188 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1189 return MCDisassembler::Fail;
1190 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1191 return MCDisassembler::Fail;
1193 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1196 Shift = ARM_AM::lsl;
1199 Shift = ARM_AM::lsr;
1202 Shift = ARM_AM::asr;
1205 Shift = ARM_AM::ror;
1209 Inst.addOperand(MCOperand::CreateImm(Shift));
1214 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1215 uint64_t Address, const void *Decoder) {
1216 DecodeStatus S = MCDisassembler::Success;
1218 bool writebackLoad = false;
1219 unsigned writebackReg = 0;
1220 switch (Inst.getOpcode()) {
1223 case ARM::LDMIA_UPD:
1224 case ARM::LDMDB_UPD:
1225 case ARM::LDMIB_UPD:
1226 case ARM::LDMDA_UPD:
1227 case ARM::t2LDMIA_UPD:
1228 case ARM::t2LDMDB_UPD:
1229 writebackLoad = true;
1230 writebackReg = Inst.getOperand(0).getReg();
1234 // Empty register lists are not allowed.
1235 if (Val == 0) return MCDisassembler::Fail;
1236 for (unsigned i = 0; i < 16; ++i) {
1237 if (Val & (1 << i)) {
1238 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1239 return MCDisassembler::Fail;
1240 // Writeback not allowed if Rn is in the target list.
1241 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1242 Check(S, MCDisassembler::SoftFail);
1249 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1250 uint64_t Address, const void *Decoder) {
1251 DecodeStatus S = MCDisassembler::Success;
1253 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1254 unsigned regs = fieldFromInstruction(Val, 0, 8);
1256 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1257 return MCDisassembler::Fail;
1258 for (unsigned i = 0; i < (regs - 1); ++i) {
1259 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1260 return MCDisassembler::Fail;
1266 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1267 uint64_t Address, const void *Decoder) {
1268 DecodeStatus S = MCDisassembler::Success;
1270 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1271 unsigned regs = fieldFromInstruction(Val, 0, 8);
1275 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1276 return MCDisassembler::Fail;
1277 for (unsigned i = 0; i < (regs - 1); ++i) {
1278 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1279 return MCDisassembler::Fail;
1285 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1286 uint64_t Address, const void *Decoder) {
1287 // This operand encodes a mask of contiguous zeros between a specified MSB
1288 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1289 // the mask of all bits LSB-and-lower, and then xor them to create
1290 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1291 // create the final mask.
1292 unsigned msb = fieldFromInstruction(Val, 5, 5);
1293 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1295 DecodeStatus S = MCDisassembler::Success;
1297 Check(S, MCDisassembler::SoftFail);
1298 // The check above will cause the warning for the "potentially undefined
1299 // instruction encoding" but we can't build a bad MCOperand value here
1300 // with a lsb > msb or else printing the MCInst will cause a crash.
1304 uint32_t msb_mask = 0xFFFFFFFF;
1305 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1306 uint32_t lsb_mask = (1U << lsb) - 1;
1308 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1312 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1313 uint64_t Address, const void *Decoder) {
1314 DecodeStatus S = MCDisassembler::Success;
1316 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1317 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1318 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1319 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1320 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1321 unsigned U = fieldFromInstruction(Insn, 23, 1);
1323 switch (Inst.getOpcode()) {
1324 case ARM::LDC_OFFSET:
1327 case ARM::LDC_OPTION:
1328 case ARM::LDCL_OFFSET:
1330 case ARM::LDCL_POST:
1331 case ARM::LDCL_OPTION:
1332 case ARM::STC_OFFSET:
1335 case ARM::STC_OPTION:
1336 case ARM::STCL_OFFSET:
1338 case ARM::STCL_POST:
1339 case ARM::STCL_OPTION:
1340 case ARM::t2LDC_OFFSET:
1341 case ARM::t2LDC_PRE:
1342 case ARM::t2LDC_POST:
1343 case ARM::t2LDC_OPTION:
1344 case ARM::t2LDCL_OFFSET:
1345 case ARM::t2LDCL_PRE:
1346 case ARM::t2LDCL_POST:
1347 case ARM::t2LDCL_OPTION:
1348 case ARM::t2STC_OFFSET:
1349 case ARM::t2STC_PRE:
1350 case ARM::t2STC_POST:
1351 case ARM::t2STC_OPTION:
1352 case ARM::t2STCL_OFFSET:
1353 case ARM::t2STCL_PRE:
1354 case ARM::t2STCL_POST:
1355 case ARM::t2STCL_OPTION:
1356 if (coproc == 0xA || coproc == 0xB)
1357 return MCDisassembler::Fail;
1363 Inst.addOperand(MCOperand::CreateImm(coproc));
1364 Inst.addOperand(MCOperand::CreateImm(CRd));
1365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1366 return MCDisassembler::Fail;
1368 switch (Inst.getOpcode()) {
1369 case ARM::t2LDC2_OFFSET:
1370 case ARM::t2LDC2L_OFFSET:
1371 case ARM::t2LDC2_PRE:
1372 case ARM::t2LDC2L_PRE:
1373 case ARM::t2STC2_OFFSET:
1374 case ARM::t2STC2L_OFFSET:
1375 case ARM::t2STC2_PRE:
1376 case ARM::t2STC2L_PRE:
1377 case ARM::LDC2_OFFSET:
1378 case ARM::LDC2L_OFFSET:
1380 case ARM::LDC2L_PRE:
1381 case ARM::STC2_OFFSET:
1382 case ARM::STC2L_OFFSET:
1384 case ARM::STC2L_PRE:
1385 case ARM::t2LDC_OFFSET:
1386 case ARM::t2LDCL_OFFSET:
1387 case ARM::t2LDC_PRE:
1388 case ARM::t2LDCL_PRE:
1389 case ARM::t2STC_OFFSET:
1390 case ARM::t2STCL_OFFSET:
1391 case ARM::t2STC_PRE:
1392 case ARM::t2STCL_PRE:
1393 case ARM::LDC_OFFSET:
1394 case ARM::LDCL_OFFSET:
1397 case ARM::STC_OFFSET:
1398 case ARM::STCL_OFFSET:
1401 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1402 Inst.addOperand(MCOperand::CreateImm(imm));
1404 case ARM::t2LDC2_POST:
1405 case ARM::t2LDC2L_POST:
1406 case ARM::t2STC2_POST:
1407 case ARM::t2STC2L_POST:
1408 case ARM::LDC2_POST:
1409 case ARM::LDC2L_POST:
1410 case ARM::STC2_POST:
1411 case ARM::STC2L_POST:
1412 case ARM::t2LDC_POST:
1413 case ARM::t2LDCL_POST:
1414 case ARM::t2STC_POST:
1415 case ARM::t2STCL_POST:
1417 case ARM::LDCL_POST:
1419 case ARM::STCL_POST:
1423 // The 'option' variant doesn't encode 'U' in the immediate since
1424 // the immediate is unsigned [0,255].
1425 Inst.addOperand(MCOperand::CreateImm(imm));
1429 switch (Inst.getOpcode()) {
1430 case ARM::LDC_OFFSET:
1433 case ARM::LDC_OPTION:
1434 case ARM::LDCL_OFFSET:
1436 case ARM::LDCL_POST:
1437 case ARM::LDCL_OPTION:
1438 case ARM::STC_OFFSET:
1441 case ARM::STC_OPTION:
1442 case ARM::STCL_OFFSET:
1444 case ARM::STCL_POST:
1445 case ARM::STCL_OPTION:
1446 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1447 return MCDisassembler::Fail;
1457 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1458 uint64_t Address, const void *Decoder) {
1459 DecodeStatus S = MCDisassembler::Success;
1461 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1462 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1463 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1464 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1465 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1466 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1467 unsigned P = fieldFromInstruction(Insn, 24, 1);
1468 unsigned W = fieldFromInstruction(Insn, 21, 1);
1470 // On stores, the writeback operand precedes Rt.
1471 switch (Inst.getOpcode()) {
1472 case ARM::STR_POST_IMM:
1473 case ARM::STR_POST_REG:
1474 case ARM::STRB_POST_IMM:
1475 case ARM::STRB_POST_REG:
1476 case ARM::STRT_POST_REG:
1477 case ARM::STRT_POST_IMM:
1478 case ARM::STRBT_POST_REG:
1479 case ARM::STRBT_POST_IMM:
1480 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1481 return MCDisassembler::Fail;
1487 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1488 return MCDisassembler::Fail;
1490 // On loads, the writeback operand comes after Rt.
1491 switch (Inst.getOpcode()) {
1492 case ARM::LDR_POST_IMM:
1493 case ARM::LDR_POST_REG:
1494 case ARM::LDRB_POST_IMM:
1495 case ARM::LDRB_POST_REG:
1496 case ARM::LDRBT_POST_REG:
1497 case ARM::LDRBT_POST_IMM:
1498 case ARM::LDRT_POST_REG:
1499 case ARM::LDRT_POST_IMM:
1500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1501 return MCDisassembler::Fail;
1507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1508 return MCDisassembler::Fail;
1510 ARM_AM::AddrOpc Op = ARM_AM::add;
1511 if (!fieldFromInstruction(Insn, 23, 1))
1514 bool writeback = (P == 0) || (W == 1);
1515 unsigned idx_mode = 0;
1517 idx_mode = ARMII::IndexModePre;
1518 else if (!P && writeback)
1519 idx_mode = ARMII::IndexModePost;
1521 if (writeback && (Rn == 15 || Rn == Rt))
1522 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1525 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1526 return MCDisassembler::Fail;
1527 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1528 switch( fieldFromInstruction(Insn, 5, 2)) {
1542 return MCDisassembler::Fail;
1544 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1545 if (Opc == ARM_AM::ror && amt == 0)
1547 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1549 Inst.addOperand(MCOperand::CreateImm(imm));
1551 Inst.addOperand(MCOperand::CreateReg(0));
1552 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1553 Inst.addOperand(MCOperand::CreateImm(tmp));
1556 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1557 return MCDisassembler::Fail;
1562 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1563 uint64_t Address, const void *Decoder) {
1564 DecodeStatus S = MCDisassembler::Success;
1566 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1567 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1568 unsigned type = fieldFromInstruction(Val, 5, 2);
1569 unsigned imm = fieldFromInstruction(Val, 7, 5);
1570 unsigned U = fieldFromInstruction(Val, 12, 1);
1572 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1588 if (ShOp == ARM_AM::ror && imm == 0)
1591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1592 return MCDisassembler::Fail;
1593 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1594 return MCDisassembler::Fail;
1597 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1599 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1600 Inst.addOperand(MCOperand::CreateImm(shift));
1606 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1607 uint64_t Address, const void *Decoder) {
1608 DecodeStatus S = MCDisassembler::Success;
1610 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1611 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1612 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1613 unsigned type = fieldFromInstruction(Insn, 22, 1);
1614 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1615 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1616 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1617 unsigned W = fieldFromInstruction(Insn, 21, 1);
1618 unsigned P = fieldFromInstruction(Insn, 24, 1);
1619 unsigned Rt2 = Rt + 1;
1621 bool writeback = (W == 1) | (P == 0);
1623 // For {LD,ST}RD, Rt must be even, else undefined.
1624 switch (Inst.getOpcode()) {
1627 case ARM::STRD_POST:
1630 case ARM::LDRD_POST:
1631 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1636 switch (Inst.getOpcode()) {
1639 case ARM::STRD_POST:
1640 if (P == 0 && W == 1)
1641 S = MCDisassembler::SoftFail;
1643 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1644 S = MCDisassembler::SoftFail;
1645 if (type && Rm == 15)
1646 S = MCDisassembler::SoftFail;
1648 S = MCDisassembler::SoftFail;
1649 if (!type && fieldFromInstruction(Insn, 8, 4))
1650 S = MCDisassembler::SoftFail;
1654 case ARM::STRH_POST:
1656 S = MCDisassembler::SoftFail;
1657 if (writeback && (Rn == 15 || Rn == Rt))
1658 S = MCDisassembler::SoftFail;
1659 if (!type && Rm == 15)
1660 S = MCDisassembler::SoftFail;
1664 case ARM::LDRD_POST:
1665 if (type && Rn == 15){
1667 S = MCDisassembler::SoftFail;
1670 if (P == 0 && W == 1)
1671 S = MCDisassembler::SoftFail;
1672 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1673 S = MCDisassembler::SoftFail;
1674 if (!type && writeback && Rn == 15)
1675 S = MCDisassembler::SoftFail;
1676 if (writeback && (Rn == Rt || Rn == Rt2))
1677 S = MCDisassembler::SoftFail;
1681 case ARM::LDRH_POST:
1682 if (type && Rn == 15){
1684 S = MCDisassembler::SoftFail;
1688 S = MCDisassembler::SoftFail;
1689 if (!type && Rm == 15)
1690 S = MCDisassembler::SoftFail;
1691 if (!type && writeback && (Rn == 15 || Rn == Rt))
1692 S = MCDisassembler::SoftFail;
1695 case ARM::LDRSH_PRE:
1696 case ARM::LDRSH_POST:
1698 case ARM::LDRSB_PRE:
1699 case ARM::LDRSB_POST:
1700 if (type && Rn == 15){
1702 S = MCDisassembler::SoftFail;
1705 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1706 S = MCDisassembler::SoftFail;
1707 if (!type && (Rt == 15 || Rm == 15))
1708 S = MCDisassembler::SoftFail;
1709 if (!type && writeback && (Rn == 15 || Rn == Rt))
1710 S = MCDisassembler::SoftFail;
1716 if (writeback) { // Writeback
1718 U |= ARMII::IndexModePre << 9;
1720 U |= ARMII::IndexModePost << 9;
1722 // On stores, the writeback operand precedes Rt.
1723 switch (Inst.getOpcode()) {
1726 case ARM::STRD_POST:
1729 case ARM::STRH_POST:
1730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1731 return MCDisassembler::Fail;
1738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1739 return MCDisassembler::Fail;
1740 switch (Inst.getOpcode()) {
1743 case ARM::STRD_POST:
1746 case ARM::LDRD_POST:
1747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1748 return MCDisassembler::Fail;
1755 // On loads, the writeback operand comes after Rt.
1756 switch (Inst.getOpcode()) {
1759 case ARM::LDRD_POST:
1762 case ARM::LDRH_POST:
1764 case ARM::LDRSH_PRE:
1765 case ARM::LDRSH_POST:
1767 case ARM::LDRSB_PRE:
1768 case ARM::LDRSB_POST:
1771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1772 return MCDisassembler::Fail;
1779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1780 return MCDisassembler::Fail;
1783 Inst.addOperand(MCOperand::CreateReg(0));
1784 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1787 return MCDisassembler::Fail;
1788 Inst.addOperand(MCOperand::CreateImm(U));
1791 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1792 return MCDisassembler::Fail;
1797 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1798 uint64_t Address, const void *Decoder) {
1799 DecodeStatus S = MCDisassembler::Success;
1801 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1802 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1819 Inst.addOperand(MCOperand::CreateImm(mode));
1820 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1821 return MCDisassembler::Fail;
1826 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1828 uint64_t Address, const void *Decoder) {
1829 DecodeStatus S = MCDisassembler::Success;
1831 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1832 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1833 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1836 switch (Inst.getOpcode()) {
1838 Inst.setOpcode(ARM::RFEDA);
1840 case ARM::LDMDA_UPD:
1841 Inst.setOpcode(ARM::RFEDA_UPD);
1844 Inst.setOpcode(ARM::RFEDB);
1846 case ARM::LDMDB_UPD:
1847 Inst.setOpcode(ARM::RFEDB_UPD);
1850 Inst.setOpcode(ARM::RFEIA);
1852 case ARM::LDMIA_UPD:
1853 Inst.setOpcode(ARM::RFEIA_UPD);
1856 Inst.setOpcode(ARM::RFEIB);
1858 case ARM::LDMIB_UPD:
1859 Inst.setOpcode(ARM::RFEIB_UPD);
1862 Inst.setOpcode(ARM::SRSDA);
1864 case ARM::STMDA_UPD:
1865 Inst.setOpcode(ARM::SRSDA_UPD);
1868 Inst.setOpcode(ARM::SRSDB);
1870 case ARM::STMDB_UPD:
1871 Inst.setOpcode(ARM::SRSDB_UPD);
1874 Inst.setOpcode(ARM::SRSIA);
1876 case ARM::STMIA_UPD:
1877 Inst.setOpcode(ARM::SRSIA_UPD);
1880 Inst.setOpcode(ARM::SRSIB);
1882 case ARM::STMIB_UPD:
1883 Inst.setOpcode(ARM::SRSIB_UPD);
1886 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1889 // For stores (which become SRS's, the only operand is the mode.
1890 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1892 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1896 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1899 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1900 return MCDisassembler::Fail;
1901 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1902 return MCDisassembler::Fail; // Tied
1903 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1904 return MCDisassembler::Fail;
1905 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1906 return MCDisassembler::Fail;
1911 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1912 uint64_t Address, const void *Decoder) {
1913 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1914 unsigned M = fieldFromInstruction(Insn, 17, 1);
1915 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1916 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1918 DecodeStatus S = MCDisassembler::Success;
1920 // imod == '01' --> UNPREDICTABLE
1921 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1922 // return failure here. The '01' imod value is unprintable, so there's
1923 // nothing useful we could do even if we returned UNPREDICTABLE.
1925 if (imod == 1) return MCDisassembler::Fail;
1928 Inst.setOpcode(ARM::CPS3p);
1929 Inst.addOperand(MCOperand::CreateImm(imod));
1930 Inst.addOperand(MCOperand::CreateImm(iflags));
1931 Inst.addOperand(MCOperand::CreateImm(mode));
1932 } else if (imod && !M) {
1933 Inst.setOpcode(ARM::CPS2p);
1934 Inst.addOperand(MCOperand::CreateImm(imod));
1935 Inst.addOperand(MCOperand::CreateImm(iflags));
1936 if (mode) S = MCDisassembler::SoftFail;
1937 } else if (!imod && M) {
1938 Inst.setOpcode(ARM::CPS1p);
1939 Inst.addOperand(MCOperand::CreateImm(mode));
1940 if (iflags) S = MCDisassembler::SoftFail;
1942 // imod == '00' && M == '0' --> UNPREDICTABLE
1943 Inst.setOpcode(ARM::CPS1p);
1944 Inst.addOperand(MCOperand::CreateImm(mode));
1945 S = MCDisassembler::SoftFail;
1951 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1952 uint64_t Address, const void *Decoder) {
1953 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1954 unsigned M = fieldFromInstruction(Insn, 8, 1);
1955 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1956 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1958 DecodeStatus S = MCDisassembler::Success;
1960 // imod == '01' --> UNPREDICTABLE
1961 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1962 // return failure here. The '01' imod value is unprintable, so there's
1963 // nothing useful we could do even if we returned UNPREDICTABLE.
1965 if (imod == 1) return MCDisassembler::Fail;
1968 Inst.setOpcode(ARM::t2CPS3p);
1969 Inst.addOperand(MCOperand::CreateImm(imod));
1970 Inst.addOperand(MCOperand::CreateImm(iflags));
1971 Inst.addOperand(MCOperand::CreateImm(mode));
1972 } else if (imod && !M) {
1973 Inst.setOpcode(ARM::t2CPS2p);
1974 Inst.addOperand(MCOperand::CreateImm(imod));
1975 Inst.addOperand(MCOperand::CreateImm(iflags));
1976 if (mode) S = MCDisassembler::SoftFail;
1977 } else if (!imod && M) {
1978 Inst.setOpcode(ARM::t2CPS1p);
1979 Inst.addOperand(MCOperand::CreateImm(mode));
1980 if (iflags) S = MCDisassembler::SoftFail;
1982 // imod == '00' && M == '0' --> this is a HINT instruction
1983 int imm = fieldFromInstruction(Insn, 0, 8);
1984 // HINT are defined only for immediate in [0..4]
1985 if(imm > 4) return MCDisassembler::Fail;
1986 Inst.setOpcode(ARM::t2HINT);
1987 Inst.addOperand(MCOperand::CreateImm(imm));
1993 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
1994 uint64_t Address, const void *Decoder) {
1995 DecodeStatus S = MCDisassembler::Success;
1997 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2000 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2001 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2002 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2003 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2005 if (Inst.getOpcode() == ARM::t2MOVTi16)
2006 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2007 return MCDisassembler::Fail;
2008 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2009 return MCDisassembler::Fail;
2011 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2012 Inst.addOperand(MCOperand::CreateImm(imm));
2017 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2018 uint64_t Address, const void *Decoder) {
2019 DecodeStatus S = MCDisassembler::Success;
2021 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2022 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2025 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2026 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2028 if (Inst.getOpcode() == ARM::MOVTi16)
2029 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2030 return MCDisassembler::Fail;
2032 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2033 return MCDisassembler::Fail;
2035 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2036 Inst.addOperand(MCOperand::CreateImm(imm));
2038 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2039 return MCDisassembler::Fail;
2044 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2045 uint64_t Address, const void *Decoder) {
2046 DecodeStatus S = MCDisassembler::Success;
2048 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2049 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2050 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2051 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2052 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2055 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2057 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2058 return MCDisassembler::Fail;
2059 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2060 return MCDisassembler::Fail;
2061 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2062 return MCDisassembler::Fail;
2063 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2064 return MCDisassembler::Fail;
2066 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2067 return MCDisassembler::Fail;
2072 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2073 uint64_t Address, const void *Decoder) {
2074 DecodeStatus S = MCDisassembler::Success;
2076 unsigned add = fieldFromInstruction(Val, 12, 1);
2077 unsigned imm = fieldFromInstruction(Val, 0, 12);
2078 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2081 return MCDisassembler::Fail;
2083 if (!add) imm *= -1;
2084 if (imm == 0 && !add) imm = INT32_MIN;
2085 Inst.addOperand(MCOperand::CreateImm(imm));
2087 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2092 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2093 uint64_t Address, const void *Decoder) {
2094 DecodeStatus S = MCDisassembler::Success;
2096 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2097 unsigned U = fieldFromInstruction(Val, 8, 1);
2098 unsigned imm = fieldFromInstruction(Val, 0, 8);
2100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2101 return MCDisassembler::Fail;
2104 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2106 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2111 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2112 uint64_t Address, const void *Decoder) {
2113 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2117 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2118 uint64_t Address, const void *Decoder) {
2119 DecodeStatus Status = MCDisassembler::Success;
2121 // Note the J1 and J2 values are from the encoded instruction. So here
2122 // change them to I1 and I2 values via as documented:
2123 // I1 = NOT(J1 EOR S);
2124 // I2 = NOT(J2 EOR S);
2125 // and build the imm32 with one trailing zero as documented:
2126 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2127 unsigned S = fieldFromInstruction(Insn, 26, 1);
2128 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2129 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2130 unsigned I1 = !(J1 ^ S);
2131 unsigned I2 = !(J2 ^ S);
2132 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2133 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2134 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2135 int imm32 = SignExtend32<24>(tmp << 1);
2136 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2137 true, 4, Inst, Decoder))
2138 Inst.addOperand(MCOperand::CreateImm(imm32));
2144 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2145 uint64_t Address, const void *Decoder) {
2146 DecodeStatus S = MCDisassembler::Success;
2148 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2149 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2152 Inst.setOpcode(ARM::BLXi);
2153 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2154 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2155 true, 4, Inst, Decoder))
2156 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2160 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2161 true, 4, Inst, Decoder))
2162 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2163 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2164 return MCDisassembler::Fail;
2170 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2171 uint64_t Address, const void *Decoder) {
2172 DecodeStatus S = MCDisassembler::Success;
2174 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2175 unsigned align = fieldFromInstruction(Val, 4, 2);
2177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2178 return MCDisassembler::Fail;
2180 Inst.addOperand(MCOperand::CreateImm(0));
2182 Inst.addOperand(MCOperand::CreateImm(4 << align));
2187 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2188 uint64_t Address, const void *Decoder) {
2189 DecodeStatus S = MCDisassembler::Success;
2191 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2192 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2193 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2194 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2195 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2196 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2198 // First output register
2199 switch (Inst.getOpcode()) {
2200 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2201 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2202 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2203 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2204 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2205 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2206 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2207 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2208 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2209 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2210 return MCDisassembler::Fail;
2215 case ARM::VLD2b16wb_fixed:
2216 case ARM::VLD2b16wb_register:
2217 case ARM::VLD2b32wb_fixed:
2218 case ARM::VLD2b32wb_register:
2219 case ARM::VLD2b8wb_fixed:
2220 case ARM::VLD2b8wb_register:
2221 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2222 return MCDisassembler::Fail;
2225 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2226 return MCDisassembler::Fail;
2229 // Second output register
2230 switch (Inst.getOpcode()) {
2234 case ARM::VLD3d8_UPD:
2235 case ARM::VLD3d16_UPD:
2236 case ARM::VLD3d32_UPD:
2240 case ARM::VLD4d8_UPD:
2241 case ARM::VLD4d16_UPD:
2242 case ARM::VLD4d32_UPD:
2243 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2244 return MCDisassembler::Fail;
2249 case ARM::VLD3q8_UPD:
2250 case ARM::VLD3q16_UPD:
2251 case ARM::VLD3q32_UPD:
2255 case ARM::VLD4q8_UPD:
2256 case ARM::VLD4q16_UPD:
2257 case ARM::VLD4q32_UPD:
2258 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2259 return MCDisassembler::Fail;
2264 // Third output register
2265 switch(Inst.getOpcode()) {
2269 case ARM::VLD3d8_UPD:
2270 case ARM::VLD3d16_UPD:
2271 case ARM::VLD3d32_UPD:
2275 case ARM::VLD4d8_UPD:
2276 case ARM::VLD4d16_UPD:
2277 case ARM::VLD4d32_UPD:
2278 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2279 return MCDisassembler::Fail;
2284 case ARM::VLD3q8_UPD:
2285 case ARM::VLD3q16_UPD:
2286 case ARM::VLD3q32_UPD:
2290 case ARM::VLD4q8_UPD:
2291 case ARM::VLD4q16_UPD:
2292 case ARM::VLD4q32_UPD:
2293 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2294 return MCDisassembler::Fail;
2300 // Fourth output register
2301 switch (Inst.getOpcode()) {
2305 case ARM::VLD4d8_UPD:
2306 case ARM::VLD4d16_UPD:
2307 case ARM::VLD4d32_UPD:
2308 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2309 return MCDisassembler::Fail;
2314 case ARM::VLD4q8_UPD:
2315 case ARM::VLD4q16_UPD:
2316 case ARM::VLD4q32_UPD:
2317 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2318 return MCDisassembler::Fail;
2324 // Writeback operand
2325 switch (Inst.getOpcode()) {
2326 case ARM::VLD1d8wb_fixed:
2327 case ARM::VLD1d16wb_fixed:
2328 case ARM::VLD1d32wb_fixed:
2329 case ARM::VLD1d64wb_fixed:
2330 case ARM::VLD1d8wb_register:
2331 case ARM::VLD1d16wb_register:
2332 case ARM::VLD1d32wb_register:
2333 case ARM::VLD1d64wb_register:
2334 case ARM::VLD1q8wb_fixed:
2335 case ARM::VLD1q16wb_fixed:
2336 case ARM::VLD1q32wb_fixed:
2337 case ARM::VLD1q64wb_fixed:
2338 case ARM::VLD1q8wb_register:
2339 case ARM::VLD1q16wb_register:
2340 case ARM::VLD1q32wb_register:
2341 case ARM::VLD1q64wb_register:
2342 case ARM::VLD1d8Twb_fixed:
2343 case ARM::VLD1d8Twb_register:
2344 case ARM::VLD1d16Twb_fixed:
2345 case ARM::VLD1d16Twb_register:
2346 case ARM::VLD1d32Twb_fixed:
2347 case ARM::VLD1d32Twb_register:
2348 case ARM::VLD1d64Twb_fixed:
2349 case ARM::VLD1d64Twb_register:
2350 case ARM::VLD1d8Qwb_fixed:
2351 case ARM::VLD1d8Qwb_register:
2352 case ARM::VLD1d16Qwb_fixed:
2353 case ARM::VLD1d16Qwb_register:
2354 case ARM::VLD1d32Qwb_fixed:
2355 case ARM::VLD1d32Qwb_register:
2356 case ARM::VLD1d64Qwb_fixed:
2357 case ARM::VLD1d64Qwb_register:
2358 case ARM::VLD2d8wb_fixed:
2359 case ARM::VLD2d16wb_fixed:
2360 case ARM::VLD2d32wb_fixed:
2361 case ARM::VLD2q8wb_fixed:
2362 case ARM::VLD2q16wb_fixed:
2363 case ARM::VLD2q32wb_fixed:
2364 case ARM::VLD2d8wb_register:
2365 case ARM::VLD2d16wb_register:
2366 case ARM::VLD2d32wb_register:
2367 case ARM::VLD2q8wb_register:
2368 case ARM::VLD2q16wb_register:
2369 case ARM::VLD2q32wb_register:
2370 case ARM::VLD2b8wb_fixed:
2371 case ARM::VLD2b16wb_fixed:
2372 case ARM::VLD2b32wb_fixed:
2373 case ARM::VLD2b8wb_register:
2374 case ARM::VLD2b16wb_register:
2375 case ARM::VLD2b32wb_register:
2376 Inst.addOperand(MCOperand::CreateImm(0));
2378 case ARM::VLD3d8_UPD:
2379 case ARM::VLD3d16_UPD:
2380 case ARM::VLD3d32_UPD:
2381 case ARM::VLD3q8_UPD:
2382 case ARM::VLD3q16_UPD:
2383 case ARM::VLD3q32_UPD:
2384 case ARM::VLD4d8_UPD:
2385 case ARM::VLD4d16_UPD:
2386 case ARM::VLD4d32_UPD:
2387 case ARM::VLD4q8_UPD:
2388 case ARM::VLD4q16_UPD:
2389 case ARM::VLD4q32_UPD:
2390 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2391 return MCDisassembler::Fail;
2397 // AddrMode6 Base (register+alignment)
2398 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2399 return MCDisassembler::Fail;
2401 // AddrMode6 Offset (register)
2402 switch (Inst.getOpcode()) {
2404 // The below have been updated to have explicit am6offset split
2405 // between fixed and register offset. For those instructions not
2406 // yet updated, we need to add an additional reg0 operand for the
2409 // The fixed offset encodes as Rm == 0xd, so we check for that.
2411 Inst.addOperand(MCOperand::CreateReg(0));
2414 // Fall through to handle the register offset variant.
2415 case ARM::VLD1d8wb_fixed:
2416 case ARM::VLD1d16wb_fixed:
2417 case ARM::VLD1d32wb_fixed:
2418 case ARM::VLD1d64wb_fixed:
2419 case ARM::VLD1d8Twb_fixed:
2420 case ARM::VLD1d16Twb_fixed:
2421 case ARM::VLD1d32Twb_fixed:
2422 case ARM::VLD1d64Twb_fixed:
2423 case ARM::VLD1d8Qwb_fixed:
2424 case ARM::VLD1d16Qwb_fixed:
2425 case ARM::VLD1d32Qwb_fixed:
2426 case ARM::VLD1d64Qwb_fixed:
2427 case ARM::VLD1d8wb_register:
2428 case ARM::VLD1d16wb_register:
2429 case ARM::VLD1d32wb_register:
2430 case ARM::VLD1d64wb_register:
2431 case ARM::VLD1q8wb_fixed:
2432 case ARM::VLD1q16wb_fixed:
2433 case ARM::VLD1q32wb_fixed:
2434 case ARM::VLD1q64wb_fixed:
2435 case ARM::VLD1q8wb_register:
2436 case ARM::VLD1q16wb_register:
2437 case ARM::VLD1q32wb_register:
2438 case ARM::VLD1q64wb_register:
2439 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2440 // variant encodes Rm == 0xf. Anything else is a register offset post-
2441 // increment and we need to add the register operand to the instruction.
2442 if (Rm != 0xD && Rm != 0xF &&
2443 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2444 return MCDisassembler::Fail;
2446 case ARM::VLD2d8wb_fixed:
2447 case ARM::VLD2d16wb_fixed:
2448 case ARM::VLD2d32wb_fixed:
2449 case ARM::VLD2b8wb_fixed:
2450 case ARM::VLD2b16wb_fixed:
2451 case ARM::VLD2b32wb_fixed:
2452 case ARM::VLD2q8wb_fixed:
2453 case ARM::VLD2q16wb_fixed:
2454 case ARM::VLD2q32wb_fixed:
2461 static DecodeStatus DecodeVST1Instruction(MCInst& Inst, unsigned Insn,
2462 uint64_t Addr, const void* Decoder) {
2463 unsigned type = fieldFromInstruction(Insn, 8, 4);
2464 unsigned align = fieldFromInstruction(Insn, 4, 2);
2465 if(type == 7 && (align & 2)) return MCDisassembler::Fail;
2466 if(type == 10 && align == 3) return MCDisassembler::Fail;
2467 if(type == 6 && (align & 2)) return MCDisassembler::Fail;
2469 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2472 static DecodeStatus DecodeVST2Instruction(MCInst& Inst, unsigned Insn,
2473 uint64_t Addr, const void* Decoder) {
2474 unsigned size = fieldFromInstruction(Insn, 6, 2);
2475 if(size == 3) return MCDisassembler::Fail;
2477 unsigned type = fieldFromInstruction(Insn, 8, 4);
2478 unsigned align = fieldFromInstruction(Insn, 4, 2);
2479 if(type == 8 && align == 3) return MCDisassembler::Fail;
2480 if(type == 9 && align == 3) return MCDisassembler::Fail;
2482 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2485 static DecodeStatus DecodeVST3Instruction(MCInst& Inst, unsigned Insn,
2486 uint64_t Addr, const void* Decoder) {
2487 unsigned size = fieldFromInstruction(Insn, 6, 2);
2488 if(size == 3) return MCDisassembler::Fail;
2490 unsigned align = fieldFromInstruction(Insn, 4, 2);
2491 if(align & 2) return MCDisassembler::Fail;
2493 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2496 static DecodeStatus DecodeVST4Instruction(MCInst& Inst, unsigned Insn,
2497 uint64_t Addr, const void* Decoder) {
2498 unsigned size = fieldFromInstruction(Insn, 6, 2);
2499 if(size == 3) return MCDisassembler::Fail;
2501 return DecodeVSTInstruction(Inst, Insn, Addr, Decoder);
2504 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2505 uint64_t Address, const void *Decoder) {
2506 DecodeStatus S = MCDisassembler::Success;
2508 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2509 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2510 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2511 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2512 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2513 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2515 // Writeback Operand
2516 switch (Inst.getOpcode()) {
2517 case ARM::VST1d8wb_fixed:
2518 case ARM::VST1d16wb_fixed:
2519 case ARM::VST1d32wb_fixed:
2520 case ARM::VST1d64wb_fixed:
2521 case ARM::VST1d8wb_register:
2522 case ARM::VST1d16wb_register:
2523 case ARM::VST1d32wb_register:
2524 case ARM::VST1d64wb_register:
2525 case ARM::VST1q8wb_fixed:
2526 case ARM::VST1q16wb_fixed:
2527 case ARM::VST1q32wb_fixed:
2528 case ARM::VST1q64wb_fixed:
2529 case ARM::VST1q8wb_register:
2530 case ARM::VST1q16wb_register:
2531 case ARM::VST1q32wb_register:
2532 case ARM::VST1q64wb_register:
2533 case ARM::VST1d8Twb_fixed:
2534 case ARM::VST1d16Twb_fixed:
2535 case ARM::VST1d32Twb_fixed:
2536 case ARM::VST1d64Twb_fixed:
2537 case ARM::VST1d8Twb_register:
2538 case ARM::VST1d16Twb_register:
2539 case ARM::VST1d32Twb_register:
2540 case ARM::VST1d64Twb_register:
2541 case ARM::VST1d8Qwb_fixed:
2542 case ARM::VST1d16Qwb_fixed:
2543 case ARM::VST1d32Qwb_fixed:
2544 case ARM::VST1d64Qwb_fixed:
2545 case ARM::VST1d8Qwb_register:
2546 case ARM::VST1d16Qwb_register:
2547 case ARM::VST1d32Qwb_register:
2548 case ARM::VST1d64Qwb_register:
2549 case ARM::VST2d8wb_fixed:
2550 case ARM::VST2d16wb_fixed:
2551 case ARM::VST2d32wb_fixed:
2552 case ARM::VST2d8wb_register:
2553 case ARM::VST2d16wb_register:
2554 case ARM::VST2d32wb_register:
2555 case ARM::VST2q8wb_fixed:
2556 case ARM::VST2q16wb_fixed:
2557 case ARM::VST2q32wb_fixed:
2558 case ARM::VST2q8wb_register:
2559 case ARM::VST2q16wb_register:
2560 case ARM::VST2q32wb_register:
2561 case ARM::VST2b8wb_fixed:
2562 case ARM::VST2b16wb_fixed:
2563 case ARM::VST2b32wb_fixed:
2564 case ARM::VST2b8wb_register:
2565 case ARM::VST2b16wb_register:
2566 case ARM::VST2b32wb_register:
2568 return MCDisassembler::Fail;
2569 Inst.addOperand(MCOperand::CreateImm(0));
2571 case ARM::VST3d8_UPD:
2572 case ARM::VST3d16_UPD:
2573 case ARM::VST3d32_UPD:
2574 case ARM::VST3q8_UPD:
2575 case ARM::VST3q16_UPD:
2576 case ARM::VST3q32_UPD:
2577 case ARM::VST4d8_UPD:
2578 case ARM::VST4d16_UPD:
2579 case ARM::VST4d32_UPD:
2580 case ARM::VST4q8_UPD:
2581 case ARM::VST4q16_UPD:
2582 case ARM::VST4q32_UPD:
2583 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2584 return MCDisassembler::Fail;
2590 // AddrMode6 Base (register+alignment)
2591 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2592 return MCDisassembler::Fail;
2594 // AddrMode6 Offset (register)
2595 switch (Inst.getOpcode()) {
2598 Inst.addOperand(MCOperand::CreateReg(0));
2599 else if (Rm != 0xF) {
2600 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2601 return MCDisassembler::Fail;
2604 case ARM::VST1d8wb_fixed:
2605 case ARM::VST1d16wb_fixed:
2606 case ARM::VST1d32wb_fixed:
2607 case ARM::VST1d64wb_fixed:
2608 case ARM::VST1q8wb_fixed:
2609 case ARM::VST1q16wb_fixed:
2610 case ARM::VST1q32wb_fixed:
2611 case ARM::VST1q64wb_fixed:
2612 case ARM::VST1d8Twb_fixed:
2613 case ARM::VST1d16Twb_fixed:
2614 case ARM::VST1d32Twb_fixed:
2615 case ARM::VST1d64Twb_fixed:
2616 case ARM::VST1d8Qwb_fixed:
2617 case ARM::VST1d16Qwb_fixed:
2618 case ARM::VST1d32Qwb_fixed:
2619 case ARM::VST1d64Qwb_fixed:
2620 case ARM::VST2d8wb_fixed:
2621 case ARM::VST2d16wb_fixed:
2622 case ARM::VST2d32wb_fixed:
2623 case ARM::VST2q8wb_fixed:
2624 case ARM::VST2q16wb_fixed:
2625 case ARM::VST2q32wb_fixed:
2626 case ARM::VST2b8wb_fixed:
2627 case ARM::VST2b16wb_fixed:
2628 case ARM::VST2b32wb_fixed:
2633 // First input register
2634 switch (Inst.getOpcode()) {
2639 case ARM::VST1q16wb_fixed:
2640 case ARM::VST1q16wb_register:
2641 case ARM::VST1q32wb_fixed:
2642 case ARM::VST1q32wb_register:
2643 case ARM::VST1q64wb_fixed:
2644 case ARM::VST1q64wb_register:
2645 case ARM::VST1q8wb_fixed:
2646 case ARM::VST1q8wb_register:
2650 case ARM::VST2d16wb_fixed:
2651 case ARM::VST2d16wb_register:
2652 case ARM::VST2d32wb_fixed:
2653 case ARM::VST2d32wb_register:
2654 case ARM::VST2d8wb_fixed:
2655 case ARM::VST2d8wb_register:
2656 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2657 return MCDisassembler::Fail;
2662 case ARM::VST2b16wb_fixed:
2663 case ARM::VST2b16wb_register:
2664 case ARM::VST2b32wb_fixed:
2665 case ARM::VST2b32wb_register:
2666 case ARM::VST2b8wb_fixed:
2667 case ARM::VST2b8wb_register:
2668 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2669 return MCDisassembler::Fail;
2672 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2673 return MCDisassembler::Fail;
2676 // Second input register
2677 switch (Inst.getOpcode()) {
2681 case ARM::VST3d8_UPD:
2682 case ARM::VST3d16_UPD:
2683 case ARM::VST3d32_UPD:
2687 case ARM::VST4d8_UPD:
2688 case ARM::VST4d16_UPD:
2689 case ARM::VST4d32_UPD:
2690 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2691 return MCDisassembler::Fail;
2696 case ARM::VST3q8_UPD:
2697 case ARM::VST3q16_UPD:
2698 case ARM::VST3q32_UPD:
2702 case ARM::VST4q8_UPD:
2703 case ARM::VST4q16_UPD:
2704 case ARM::VST4q32_UPD:
2705 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2706 return MCDisassembler::Fail;
2712 // Third input register
2713 switch (Inst.getOpcode()) {
2717 case ARM::VST3d8_UPD:
2718 case ARM::VST3d16_UPD:
2719 case ARM::VST3d32_UPD:
2723 case ARM::VST4d8_UPD:
2724 case ARM::VST4d16_UPD:
2725 case ARM::VST4d32_UPD:
2726 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2727 return MCDisassembler::Fail;
2732 case ARM::VST3q8_UPD:
2733 case ARM::VST3q16_UPD:
2734 case ARM::VST3q32_UPD:
2738 case ARM::VST4q8_UPD:
2739 case ARM::VST4q16_UPD:
2740 case ARM::VST4q32_UPD:
2741 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2742 return MCDisassembler::Fail;
2748 // Fourth input register
2749 switch (Inst.getOpcode()) {
2753 case ARM::VST4d8_UPD:
2754 case ARM::VST4d16_UPD:
2755 case ARM::VST4d32_UPD:
2756 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2757 return MCDisassembler::Fail;
2762 case ARM::VST4q8_UPD:
2763 case ARM::VST4q16_UPD:
2764 case ARM::VST4q32_UPD:
2765 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2766 return MCDisassembler::Fail;
2775 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2776 uint64_t Address, const void *Decoder) {
2777 DecodeStatus S = MCDisassembler::Success;
2779 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2780 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2781 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2782 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2783 unsigned align = fieldFromInstruction(Insn, 4, 1);
2784 unsigned size = fieldFromInstruction(Insn, 6, 2);
2786 if (size == 0 && align == 1)
2787 return MCDisassembler::Fail;
2788 align *= (1 << size);
2790 switch (Inst.getOpcode()) {
2791 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2792 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2793 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2794 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2795 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2796 return MCDisassembler::Fail;
2799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2800 return MCDisassembler::Fail;
2804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2805 return MCDisassembler::Fail;
2808 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2809 return MCDisassembler::Fail;
2810 Inst.addOperand(MCOperand::CreateImm(align));
2812 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2813 // variant encodes Rm == 0xf. Anything else is a register offset post-
2814 // increment and we need to add the register operand to the instruction.
2815 if (Rm != 0xD && Rm != 0xF &&
2816 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2817 return MCDisassembler::Fail;
2822 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2823 uint64_t Address, const void *Decoder) {
2824 DecodeStatus S = MCDisassembler::Success;
2826 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2827 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2828 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2829 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2830 unsigned align = fieldFromInstruction(Insn, 4, 1);
2831 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2834 switch (Inst.getOpcode()) {
2835 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2836 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2837 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2838 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2839 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2840 return MCDisassembler::Fail;
2842 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2843 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2844 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2845 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2846 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2847 return MCDisassembler::Fail;
2850 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2851 return MCDisassembler::Fail;
2856 Inst.addOperand(MCOperand::CreateImm(0));
2858 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2859 return MCDisassembler::Fail;
2860 Inst.addOperand(MCOperand::CreateImm(align));
2862 if (Rm != 0xD && Rm != 0xF) {
2863 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2864 return MCDisassembler::Fail;
2870 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2871 uint64_t Address, const void *Decoder) {
2872 DecodeStatus S = MCDisassembler::Success;
2874 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2875 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2876 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2877 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2878 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2880 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2881 return MCDisassembler::Fail;
2882 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2883 return MCDisassembler::Fail;
2884 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2885 return MCDisassembler::Fail;
2887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2888 return MCDisassembler::Fail;
2891 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2892 return MCDisassembler::Fail;
2893 Inst.addOperand(MCOperand::CreateImm(0));
2896 Inst.addOperand(MCOperand::CreateReg(0));
2897 else if (Rm != 0xF) {
2898 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2899 return MCDisassembler::Fail;
2905 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2906 uint64_t Address, const void *Decoder) {
2907 DecodeStatus S = MCDisassembler::Success;
2909 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2910 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2911 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2912 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2913 unsigned size = fieldFromInstruction(Insn, 6, 2);
2914 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2915 unsigned align = fieldFromInstruction(Insn, 4, 1);
2919 return MCDisassembler::Fail;
2932 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2933 return MCDisassembler::Fail;
2934 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2935 return MCDisassembler::Fail;
2936 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2937 return MCDisassembler::Fail;
2938 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2939 return MCDisassembler::Fail;
2941 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2942 return MCDisassembler::Fail;
2945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2946 return MCDisassembler::Fail;
2947 Inst.addOperand(MCOperand::CreateImm(align));
2950 Inst.addOperand(MCOperand::CreateReg(0));
2951 else if (Rm != 0xF) {
2952 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2953 return MCDisassembler::Fail;
2960 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
2961 uint64_t Address, const void *Decoder) {
2962 DecodeStatus S = MCDisassembler::Success;
2964 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2965 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2966 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2967 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2968 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2969 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2970 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2971 unsigned Q = fieldFromInstruction(Insn, 6, 1);
2974 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2975 return MCDisassembler::Fail;
2977 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2978 return MCDisassembler::Fail;
2981 Inst.addOperand(MCOperand::CreateImm(imm));
2983 switch (Inst.getOpcode()) {
2984 case ARM::VORRiv4i16:
2985 case ARM::VORRiv2i32:
2986 case ARM::VBICiv4i16:
2987 case ARM::VBICiv2i32:
2988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2989 return MCDisassembler::Fail;
2991 case ARM::VORRiv8i16:
2992 case ARM::VORRiv4i32:
2993 case ARM::VBICiv8i16:
2994 case ARM::VBICiv4i32:
2995 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2996 return MCDisassembler::Fail;
3005 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3006 uint64_t Address, const void *Decoder) {
3007 DecodeStatus S = MCDisassembler::Success;
3009 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3010 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3011 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3012 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3013 unsigned size = fieldFromInstruction(Insn, 18, 2);
3015 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3016 return MCDisassembler::Fail;
3017 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3018 return MCDisassembler::Fail;
3019 Inst.addOperand(MCOperand::CreateImm(8 << size));
3024 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3025 uint64_t Address, const void *Decoder) {
3026 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3027 return MCDisassembler::Success;
3030 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3031 uint64_t Address, const void *Decoder) {
3032 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3033 return MCDisassembler::Success;
3036 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3037 uint64_t Address, const void *Decoder) {
3038 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3039 return MCDisassembler::Success;
3042 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3043 uint64_t Address, const void *Decoder) {
3044 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3045 return MCDisassembler::Success;
3048 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3049 uint64_t Address, const void *Decoder) {
3050 DecodeStatus S = MCDisassembler::Success;
3052 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3053 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3054 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3055 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3056 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3057 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3058 unsigned op = fieldFromInstruction(Insn, 6, 1);
3060 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3061 return MCDisassembler::Fail;
3063 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3064 return MCDisassembler::Fail; // Writeback
3067 switch (Inst.getOpcode()) {
3070 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3071 return MCDisassembler::Fail;
3074 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3075 return MCDisassembler::Fail;
3078 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3079 return MCDisassembler::Fail;
3084 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3085 uint64_t Address, const void *Decoder) {
3086 DecodeStatus S = MCDisassembler::Success;
3088 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3089 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3091 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3092 return MCDisassembler::Fail;
3094 switch(Inst.getOpcode()) {
3096 return MCDisassembler::Fail;
3098 break; // tADR does not explicitly represent the PC as an operand.
3100 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3104 Inst.addOperand(MCOperand::CreateImm(imm));
3108 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3109 uint64_t Address, const void *Decoder) {
3110 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3111 true, 2, Inst, Decoder))
3112 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3113 return MCDisassembler::Success;
3116 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3117 uint64_t Address, const void *Decoder) {
3118 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3119 true, 4, Inst, Decoder))
3120 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3121 return MCDisassembler::Success;
3124 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3125 uint64_t Address, const void *Decoder) {
3126 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3127 true, 2, Inst, Decoder))
3128 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3129 return MCDisassembler::Success;
3132 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3133 uint64_t Address, const void *Decoder) {
3134 DecodeStatus S = MCDisassembler::Success;
3136 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3137 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3139 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3140 return MCDisassembler::Fail;
3141 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3142 return MCDisassembler::Fail;
3147 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3148 uint64_t Address, const void *Decoder) {
3149 DecodeStatus S = MCDisassembler::Success;
3151 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3152 unsigned imm = fieldFromInstruction(Val, 3, 5);
3154 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3155 return MCDisassembler::Fail;
3156 Inst.addOperand(MCOperand::CreateImm(imm));
3161 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3162 uint64_t Address, const void *Decoder) {
3163 unsigned imm = Val << 2;
3165 Inst.addOperand(MCOperand::CreateImm(imm));
3166 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3168 return MCDisassembler::Success;
3171 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3172 uint64_t Address, const void *Decoder) {
3173 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3174 Inst.addOperand(MCOperand::CreateImm(Val));
3176 return MCDisassembler::Success;
3179 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3180 uint64_t Address, const void *Decoder) {
3181 DecodeStatus S = MCDisassembler::Success;
3183 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3184 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3185 unsigned imm = fieldFromInstruction(Val, 0, 2);
3187 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3188 return MCDisassembler::Fail;
3189 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3190 return MCDisassembler::Fail;
3191 Inst.addOperand(MCOperand::CreateImm(imm));
3196 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3197 uint64_t Address, const void *Decoder) {
3198 DecodeStatus S = MCDisassembler::Success;
3200 switch (Inst.getOpcode()) {
3206 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3207 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3208 return MCDisassembler::Fail;
3212 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3214 switch (Inst.getOpcode()) {
3216 Inst.setOpcode(ARM::t2LDRBpci);
3219 Inst.setOpcode(ARM::t2LDRHpci);
3222 Inst.setOpcode(ARM::t2LDRSHpci);
3225 Inst.setOpcode(ARM::t2LDRSBpci);
3228 Inst.setOpcode(ARM::t2PLDi12);
3229 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
3232 return MCDisassembler::Fail;
3235 int imm = fieldFromInstruction(Insn, 0, 12);
3236 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
3237 Inst.addOperand(MCOperand::CreateImm(imm));
3242 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3243 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3244 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3245 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3246 return MCDisassembler::Fail;
3251 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3252 uint64_t Address, const void *Decoder) {
3254 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3256 int imm = Val & 0xFF;
3258 if (!(Val & 0x100)) imm *= -1;
3259 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3262 return MCDisassembler::Success;
3265 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3266 uint64_t Address, const void *Decoder) {
3267 DecodeStatus S = MCDisassembler::Success;
3269 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3270 unsigned imm = fieldFromInstruction(Val, 0, 9);
3272 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3273 return MCDisassembler::Fail;
3274 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3275 return MCDisassembler::Fail;
3280 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3281 uint64_t Address, const void *Decoder) {
3282 DecodeStatus S = MCDisassembler::Success;
3284 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3285 unsigned imm = fieldFromInstruction(Val, 0, 8);
3287 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3288 return MCDisassembler::Fail;
3290 Inst.addOperand(MCOperand::CreateImm(imm));
3295 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3296 uint64_t Address, const void *Decoder) {
3297 int imm = Val & 0xFF;
3300 else if (!(Val & 0x100))
3302 Inst.addOperand(MCOperand::CreateImm(imm));
3304 return MCDisassembler::Success;
3308 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3309 uint64_t Address, const void *Decoder) {
3310 DecodeStatus S = MCDisassembler::Success;
3312 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3313 unsigned imm = fieldFromInstruction(Val, 0, 9);
3315 // Some instructions always use an additive offset.
3316 switch (Inst.getOpcode()) {
3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3332 return MCDisassembler::Fail;
3333 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3334 return MCDisassembler::Fail;
3339 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3340 uint64_t Address, const void *Decoder) {
3341 DecodeStatus S = MCDisassembler::Success;
3343 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3344 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3345 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3346 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3348 unsigned load = fieldFromInstruction(Insn, 20, 1);
3351 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3352 return MCDisassembler::Fail;
3355 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3356 return MCDisassembler::Fail;
3359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3360 return MCDisassembler::Fail;
3363 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3364 return MCDisassembler::Fail;
3369 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3370 uint64_t Address, const void *Decoder) {
3371 DecodeStatus S = MCDisassembler::Success;
3373 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3374 unsigned imm = fieldFromInstruction(Val, 0, 12);
3376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3377 return MCDisassembler::Fail;
3378 Inst.addOperand(MCOperand::CreateImm(imm));
3384 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3385 uint64_t Address, const void *Decoder) {
3386 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3388 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3389 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3390 Inst.addOperand(MCOperand::CreateImm(imm));
3392 return MCDisassembler::Success;
3395 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3396 uint64_t Address, const void *Decoder) {
3397 DecodeStatus S = MCDisassembler::Success;
3399 if (Inst.getOpcode() == ARM::tADDrSP) {
3400 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3401 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3403 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3404 return MCDisassembler::Fail;
3405 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3406 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3407 return MCDisassembler::Fail;
3408 } else if (Inst.getOpcode() == ARM::tADDspr) {
3409 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3411 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3412 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3414 return MCDisassembler::Fail;
3420 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3421 uint64_t Address, const void *Decoder) {
3422 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3423 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3425 Inst.addOperand(MCOperand::CreateImm(imod));
3426 Inst.addOperand(MCOperand::CreateImm(flags));
3428 return MCDisassembler::Success;
3431 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3432 uint64_t Address, const void *Decoder) {
3433 DecodeStatus S = MCDisassembler::Success;
3434 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3435 unsigned add = fieldFromInstruction(Insn, 4, 1);
3437 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3438 return MCDisassembler::Fail;
3439 Inst.addOperand(MCOperand::CreateImm(add));
3444 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3445 uint64_t Address, const void *Decoder) {
3446 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3447 // Note only one trailing zero not two. Also the J1 and J2 values are from
3448 // the encoded instruction. So here change to I1 and I2 values via:
3449 // I1 = NOT(J1 EOR S);
3450 // I2 = NOT(J2 EOR S);
3451 // and build the imm32 with two trailing zeros as documented:
3452 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3453 unsigned S = (Val >> 23) & 1;
3454 unsigned J1 = (Val >> 22) & 1;
3455 unsigned J2 = (Val >> 21) & 1;
3456 unsigned I1 = !(J1 ^ S);
3457 unsigned I2 = !(J2 ^ S);
3458 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3459 int imm32 = SignExtend32<25>(tmp << 1);
3461 if (!tryAddingSymbolicOperand(Address,
3462 (Address & ~2u) + imm32 + 4,
3463 true, 4, Inst, Decoder))
3464 Inst.addOperand(MCOperand::CreateImm(imm32));
3465 return MCDisassembler::Success;
3468 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3469 uint64_t Address, const void *Decoder) {
3470 if (Val == 0xA || Val == 0xB)
3471 return MCDisassembler::Fail;
3473 Inst.addOperand(MCOperand::CreateImm(Val));
3474 return MCDisassembler::Success;
3478 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3479 uint64_t Address, const void *Decoder) {
3480 DecodeStatus S = MCDisassembler::Success;
3482 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3483 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3485 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3487 return MCDisassembler::Fail;
3488 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3489 return MCDisassembler::Fail;
3494 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3495 uint64_t Address, const void *Decoder) {
3496 DecodeStatus S = MCDisassembler::Success;
3498 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3499 if (pred == 0xE || pred == 0xF) {
3500 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3503 return MCDisassembler::Fail;
3505 Inst.setOpcode(ARM::t2DSB);
3508 Inst.setOpcode(ARM::t2DMB);
3511 Inst.setOpcode(ARM::t2ISB);
3515 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3516 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3519 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3520 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3521 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3522 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3523 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3525 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3526 return MCDisassembler::Fail;
3527 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3528 return MCDisassembler::Fail;
3533 // Decode a shifted immediate operand. These basically consist
3534 // of an 8-bit value, and a 4-bit directive that specifies either
3535 // a splat operation or a rotation.
3536 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3537 uint64_t Address, const void *Decoder) {
3538 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3540 unsigned byte = fieldFromInstruction(Val, 8, 2);
3541 unsigned imm = fieldFromInstruction(Val, 0, 8);
3544 Inst.addOperand(MCOperand::CreateImm(imm));
3547 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3550 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3553 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3558 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3559 unsigned rot = fieldFromInstruction(Val, 7, 5);
3560 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3561 Inst.addOperand(MCOperand::CreateImm(imm));
3564 return MCDisassembler::Success;
3568 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3569 uint64_t Address, const void *Decoder){
3570 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3571 true, 2, Inst, Decoder))
3572 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3573 return MCDisassembler::Success;
3576 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3577 uint64_t Address, const void *Decoder){
3578 // Val is passed in as S:J1:J2:imm10:imm11
3579 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3580 // the encoded instruction. So here change to I1 and I2 values via:
3581 // I1 = NOT(J1 EOR S);
3582 // I2 = NOT(J2 EOR S);
3583 // and build the imm32 with one trailing zero as documented:
3584 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3585 unsigned S = (Val >> 23) & 1;
3586 unsigned J1 = (Val >> 22) & 1;
3587 unsigned J2 = (Val >> 21) & 1;
3588 unsigned I1 = !(J1 ^ S);
3589 unsigned I2 = !(J2 ^ S);
3590 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3591 int imm32 = SignExtend32<25>(tmp << 1);
3593 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3594 true, 4, Inst, Decoder))
3595 Inst.addOperand(MCOperand::CreateImm(imm32));
3596 return MCDisassembler::Success;
3599 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3600 uint64_t Address, const void *Decoder) {
3602 return MCDisassembler::Fail;
3604 Inst.addOperand(MCOperand::CreateImm(Val));
3605 return MCDisassembler::Success;
3608 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3609 uint64_t Address, const void *Decoder) {
3610 if (!Val) return MCDisassembler::Fail;
3611 Inst.addOperand(MCOperand::CreateImm(Val));
3612 return MCDisassembler::Success;
3615 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3616 uint64_t Address, const void *Decoder) {
3617 DecodeStatus S = MCDisassembler::Success;
3619 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3620 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3621 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3623 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3626 return MCDisassembler::Fail;
3627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3628 return MCDisassembler::Fail;
3629 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3630 return MCDisassembler::Fail;
3631 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3632 return MCDisassembler::Fail;
3638 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
3639 uint64_t Address, const void *Decoder){
3640 DecodeStatus S = MCDisassembler::Success;
3642 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3643 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3644 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3645 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3647 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
3648 return MCDisassembler::Fail;
3650 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3651 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3653 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3654 return MCDisassembler::Fail;
3655 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3656 return MCDisassembler::Fail;
3657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3658 return MCDisassembler::Fail;
3659 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3660 return MCDisassembler::Fail;
3665 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
3666 uint64_t Address, const void *Decoder) {
3667 DecodeStatus S = MCDisassembler::Success;
3669 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3670 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3671 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3672 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3673 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3674 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3676 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3678 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3679 return MCDisassembler::Fail;
3680 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3681 return MCDisassembler::Fail;
3682 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3683 return MCDisassembler::Fail;
3684 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3685 return MCDisassembler::Fail;
3690 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
3691 uint64_t Address, const void *Decoder) {
3692 DecodeStatus S = MCDisassembler::Success;
3694 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3695 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3696 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3697 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3698 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3699 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3700 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3702 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3703 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3706 return MCDisassembler::Fail;
3707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3708 return MCDisassembler::Fail;
3709 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3710 return MCDisassembler::Fail;
3711 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3712 return MCDisassembler::Fail;
3718 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
3719 uint64_t Address, const void *Decoder) {
3720 DecodeStatus S = MCDisassembler::Success;
3722 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3723 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3724 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3725 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3726 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3727 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3729 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3732 return MCDisassembler::Fail;
3733 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3734 return MCDisassembler::Fail;
3735 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3736 return MCDisassembler::Fail;
3737 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3738 return MCDisassembler::Fail;
3743 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
3744 uint64_t Address, const void *Decoder) {
3745 DecodeStatus S = MCDisassembler::Success;
3747 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3748 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3749 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3750 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3751 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3752 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3754 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3757 return MCDisassembler::Fail;
3758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3759 return MCDisassembler::Fail;
3760 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3761 return MCDisassembler::Fail;
3762 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3763 return MCDisassembler::Fail;
3768 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
3769 uint64_t Address, const void *Decoder) {
3770 DecodeStatus S = MCDisassembler::Success;
3772 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3773 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3774 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3775 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3776 unsigned size = fieldFromInstruction(Insn, 10, 2);
3782 return MCDisassembler::Fail;
3784 if (fieldFromInstruction(Insn, 4, 1))
3785 return MCDisassembler::Fail; // UNDEFINED
3786 index = fieldFromInstruction(Insn, 5, 3);
3789 if (fieldFromInstruction(Insn, 5, 1))
3790 return MCDisassembler::Fail; // UNDEFINED
3791 index = fieldFromInstruction(Insn, 6, 2);
3792 if (fieldFromInstruction(Insn, 4, 1))
3796 if (fieldFromInstruction(Insn, 6, 1))
3797 return MCDisassembler::Fail; // UNDEFINED
3798 index = fieldFromInstruction(Insn, 7, 1);
3800 switch (fieldFromInstruction(Insn, 4, 2)) {
3806 return MCDisassembler::Fail;
3811 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3812 return MCDisassembler::Fail;
3813 if (Rm != 0xF) { // Writeback
3814 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3815 return MCDisassembler::Fail;
3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3818 return MCDisassembler::Fail;
3819 Inst.addOperand(MCOperand::CreateImm(align));
3822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3823 return MCDisassembler::Fail;
3825 Inst.addOperand(MCOperand::CreateReg(0));
3828 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3829 return MCDisassembler::Fail;
3830 Inst.addOperand(MCOperand::CreateImm(index));
3835 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
3836 uint64_t Address, const void *Decoder) {
3837 DecodeStatus S = MCDisassembler::Success;
3839 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3840 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3841 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3842 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3843 unsigned size = fieldFromInstruction(Insn, 10, 2);
3849 return MCDisassembler::Fail;
3851 if (fieldFromInstruction(Insn, 4, 1))
3852 return MCDisassembler::Fail; // UNDEFINED
3853 index = fieldFromInstruction(Insn, 5, 3);
3856 if (fieldFromInstruction(Insn, 5, 1))
3857 return MCDisassembler::Fail; // UNDEFINED
3858 index = fieldFromInstruction(Insn, 6, 2);
3859 if (fieldFromInstruction(Insn, 4, 1))
3863 if (fieldFromInstruction(Insn, 6, 1))
3864 return MCDisassembler::Fail; // UNDEFINED
3865 index = fieldFromInstruction(Insn, 7, 1);
3867 switch (fieldFromInstruction(Insn, 4, 2)) {
3873 return MCDisassembler::Fail;
3878 if (Rm != 0xF) { // Writeback
3879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3880 return MCDisassembler::Fail;
3882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3883 return MCDisassembler::Fail;
3884 Inst.addOperand(MCOperand::CreateImm(align));
3887 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3888 return MCDisassembler::Fail;
3890 Inst.addOperand(MCOperand::CreateReg(0));
3893 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3894 return MCDisassembler::Fail;
3895 Inst.addOperand(MCOperand::CreateImm(index));
3901 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
3902 uint64_t Address, const void *Decoder) {
3903 DecodeStatus S = MCDisassembler::Success;
3905 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3906 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3907 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3908 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3909 unsigned size = fieldFromInstruction(Insn, 10, 2);
3916 return MCDisassembler::Fail;
3918 index = fieldFromInstruction(Insn, 5, 3);
3919 if (fieldFromInstruction(Insn, 4, 1))
3923 index = fieldFromInstruction(Insn, 6, 2);
3924 if (fieldFromInstruction(Insn, 4, 1))
3926 if (fieldFromInstruction(Insn, 5, 1))
3930 if (fieldFromInstruction(Insn, 5, 1))
3931 return MCDisassembler::Fail; // UNDEFINED
3932 index = fieldFromInstruction(Insn, 7, 1);
3933 if (fieldFromInstruction(Insn, 4, 1) != 0)
3935 if (fieldFromInstruction(Insn, 6, 1))
3940 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3941 return MCDisassembler::Fail;
3942 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3943 return MCDisassembler::Fail;
3944 if (Rm != 0xF) { // Writeback
3945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3946 return MCDisassembler::Fail;
3948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3949 return MCDisassembler::Fail;
3950 Inst.addOperand(MCOperand::CreateImm(align));
3953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3954 return MCDisassembler::Fail;
3956 Inst.addOperand(MCOperand::CreateReg(0));
3959 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3960 return MCDisassembler::Fail;
3961 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3962 return MCDisassembler::Fail;
3963 Inst.addOperand(MCOperand::CreateImm(index));
3968 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
3969 uint64_t Address, const void *Decoder) {
3970 DecodeStatus S = MCDisassembler::Success;
3972 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3973 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3974 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3975 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3976 unsigned size = fieldFromInstruction(Insn, 10, 2);
3983 return MCDisassembler::Fail;
3985 index = fieldFromInstruction(Insn, 5, 3);
3986 if (fieldFromInstruction(Insn, 4, 1))
3990 index = fieldFromInstruction(Insn, 6, 2);
3991 if (fieldFromInstruction(Insn, 4, 1))
3993 if (fieldFromInstruction(Insn, 5, 1))
3997 if (fieldFromInstruction(Insn, 5, 1))
3998 return MCDisassembler::Fail; // UNDEFINED
3999 index = fieldFromInstruction(Insn, 7, 1);
4000 if (fieldFromInstruction(Insn, 4, 1) != 0)
4002 if (fieldFromInstruction(Insn, 6, 1))
4007 if (Rm != 0xF) { // Writeback
4008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4009 return MCDisassembler::Fail;
4011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4012 return MCDisassembler::Fail;
4013 Inst.addOperand(MCOperand::CreateImm(align));
4016 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4017 return MCDisassembler::Fail;
4019 Inst.addOperand(MCOperand::CreateReg(0));
4022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4023 return MCDisassembler::Fail;
4024 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4025 return MCDisassembler::Fail;
4026 Inst.addOperand(MCOperand::CreateImm(index));
4032 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4033 uint64_t Address, const void *Decoder) {
4034 DecodeStatus S = MCDisassembler::Success;
4036 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4037 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4038 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4039 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4040 unsigned size = fieldFromInstruction(Insn, 10, 2);
4047 return MCDisassembler::Fail;
4049 if (fieldFromInstruction(Insn, 4, 1))
4050 return MCDisassembler::Fail; // UNDEFINED
4051 index = fieldFromInstruction(Insn, 5, 3);
4054 if (fieldFromInstruction(Insn, 4, 1))
4055 return MCDisassembler::Fail; // UNDEFINED
4056 index = fieldFromInstruction(Insn, 6, 2);
4057 if (fieldFromInstruction(Insn, 5, 1))
4061 if (fieldFromInstruction(Insn, 4, 2))
4062 return MCDisassembler::Fail; // UNDEFINED
4063 index = fieldFromInstruction(Insn, 7, 1);
4064 if (fieldFromInstruction(Insn, 6, 1))
4069 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4070 return MCDisassembler::Fail;
4071 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4072 return MCDisassembler::Fail;
4073 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4074 return MCDisassembler::Fail;
4076 if (Rm != 0xF) { // Writeback
4077 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4078 return MCDisassembler::Fail;
4080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4081 return MCDisassembler::Fail;
4082 Inst.addOperand(MCOperand::CreateImm(align));
4085 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4086 return MCDisassembler::Fail;
4088 Inst.addOperand(MCOperand::CreateReg(0));
4091 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4092 return MCDisassembler::Fail;
4093 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4094 return MCDisassembler::Fail;
4095 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4096 return MCDisassembler::Fail;
4097 Inst.addOperand(MCOperand::CreateImm(index));
4102 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4103 uint64_t Address, const void *Decoder) {
4104 DecodeStatus S = MCDisassembler::Success;
4106 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4107 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4108 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4109 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4110 unsigned size = fieldFromInstruction(Insn, 10, 2);
4117 return MCDisassembler::Fail;
4119 if (fieldFromInstruction(Insn, 4, 1))
4120 return MCDisassembler::Fail; // UNDEFINED
4121 index = fieldFromInstruction(Insn, 5, 3);
4124 if (fieldFromInstruction(Insn, 4, 1))
4125 return MCDisassembler::Fail; // UNDEFINED
4126 index = fieldFromInstruction(Insn, 6, 2);
4127 if (fieldFromInstruction(Insn, 5, 1))
4131 if (fieldFromInstruction(Insn, 4, 2))
4132 return MCDisassembler::Fail; // UNDEFINED
4133 index = fieldFromInstruction(Insn, 7, 1);
4134 if (fieldFromInstruction(Insn, 6, 1))
4139 if (Rm != 0xF) { // Writeback
4140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4141 return MCDisassembler::Fail;
4143 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4144 return MCDisassembler::Fail;
4145 Inst.addOperand(MCOperand::CreateImm(align));
4148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4149 return MCDisassembler::Fail;
4151 Inst.addOperand(MCOperand::CreateReg(0));
4154 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4155 return MCDisassembler::Fail;
4156 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4157 return MCDisassembler::Fail;
4158 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4159 return MCDisassembler::Fail;
4160 Inst.addOperand(MCOperand::CreateImm(index));
4166 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4167 uint64_t Address, const void *Decoder) {
4168 DecodeStatus S = MCDisassembler::Success;
4170 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4171 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4172 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4173 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4174 unsigned size = fieldFromInstruction(Insn, 10, 2);
4181 return MCDisassembler::Fail;
4183 if (fieldFromInstruction(Insn, 4, 1))
4185 index = fieldFromInstruction(Insn, 5, 3);
4188 if (fieldFromInstruction(Insn, 4, 1))
4190 index = fieldFromInstruction(Insn, 6, 2);
4191 if (fieldFromInstruction(Insn, 5, 1))
4195 switch (fieldFromInstruction(Insn, 4, 2)) {
4199 return MCDisassembler::Fail;
4201 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4204 index = fieldFromInstruction(Insn, 7, 1);
4205 if (fieldFromInstruction(Insn, 6, 1))
4210 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4211 return MCDisassembler::Fail;
4212 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4213 return MCDisassembler::Fail;
4214 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4215 return MCDisassembler::Fail;
4216 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4217 return MCDisassembler::Fail;
4219 if (Rm != 0xF) { // Writeback
4220 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4221 return MCDisassembler::Fail;
4223 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4224 return MCDisassembler::Fail;
4225 Inst.addOperand(MCOperand::CreateImm(align));
4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4229 return MCDisassembler::Fail;
4231 Inst.addOperand(MCOperand::CreateReg(0));
4234 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4235 return MCDisassembler::Fail;
4236 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4237 return MCDisassembler::Fail;
4238 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4239 return MCDisassembler::Fail;
4240 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4241 return MCDisassembler::Fail;
4242 Inst.addOperand(MCOperand::CreateImm(index));
4247 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4248 uint64_t Address, const void *Decoder) {
4249 DecodeStatus S = MCDisassembler::Success;
4251 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4252 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4253 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4254 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4255 unsigned size = fieldFromInstruction(Insn, 10, 2);
4262 return MCDisassembler::Fail;
4264 if (fieldFromInstruction(Insn, 4, 1))
4266 index = fieldFromInstruction(Insn, 5, 3);
4269 if (fieldFromInstruction(Insn, 4, 1))
4271 index = fieldFromInstruction(Insn, 6, 2);
4272 if (fieldFromInstruction(Insn, 5, 1))
4276 switch (fieldFromInstruction(Insn, 4, 2)) {
4280 return MCDisassembler::Fail;
4282 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4285 index = fieldFromInstruction(Insn, 7, 1);
4286 if (fieldFromInstruction(Insn, 6, 1))
4291 if (Rm != 0xF) { // Writeback
4292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4293 return MCDisassembler::Fail;
4295 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4296 return MCDisassembler::Fail;
4297 Inst.addOperand(MCOperand::CreateImm(align));
4300 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4301 return MCDisassembler::Fail;
4303 Inst.addOperand(MCOperand::CreateReg(0));
4306 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4307 return MCDisassembler::Fail;
4308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4309 return MCDisassembler::Fail;
4310 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4311 return MCDisassembler::Fail;
4312 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4313 return MCDisassembler::Fail;
4314 Inst.addOperand(MCOperand::CreateImm(index));
4319 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4320 uint64_t Address, const void *Decoder) {
4321 DecodeStatus S = MCDisassembler::Success;
4322 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4323 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4324 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4325 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4326 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4328 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4329 S = MCDisassembler::SoftFail;
4331 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4332 return MCDisassembler::Fail;
4333 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4334 return MCDisassembler::Fail;
4335 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4336 return MCDisassembler::Fail;
4337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4338 return MCDisassembler::Fail;
4339 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4340 return MCDisassembler::Fail;
4345 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4346 uint64_t Address, const void *Decoder) {
4347 DecodeStatus S = MCDisassembler::Success;
4348 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4349 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4350 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4351 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4352 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4354 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4355 S = MCDisassembler::SoftFail;
4357 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4358 return MCDisassembler::Fail;
4359 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4360 return MCDisassembler::Fail;
4361 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4362 return MCDisassembler::Fail;
4363 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4364 return MCDisassembler::Fail;
4365 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4366 return MCDisassembler::Fail;
4371 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4372 uint64_t Address, const void *Decoder) {
4373 DecodeStatus S = MCDisassembler::Success;
4374 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4375 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4379 S = MCDisassembler::SoftFail;
4384 S = MCDisassembler::SoftFail;
4387 Inst.addOperand(MCOperand::CreateImm(pred));
4388 Inst.addOperand(MCOperand::CreateImm(mask));
4393 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4394 uint64_t Address, const void *Decoder) {
4395 DecodeStatus S = MCDisassembler::Success;
4397 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4398 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4399 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4400 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4401 unsigned W = fieldFromInstruction(Insn, 21, 1);
4402 unsigned U = fieldFromInstruction(Insn, 23, 1);
4403 unsigned P = fieldFromInstruction(Insn, 24, 1);
4404 bool writeback = (W == 1) | (P == 0);
4406 addr |= (U << 8) | (Rn << 9);
4408 if (writeback && (Rn == Rt || Rn == Rt2))
4409 Check(S, MCDisassembler::SoftFail);
4411 Check(S, MCDisassembler::SoftFail);
4414 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4415 return MCDisassembler::Fail;
4417 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4418 return MCDisassembler::Fail;
4419 // Writeback operand
4420 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4421 return MCDisassembler::Fail;
4423 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4424 return MCDisassembler::Fail;
4430 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4431 uint64_t Address, const void *Decoder) {
4432 DecodeStatus S = MCDisassembler::Success;
4434 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4435 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4436 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4437 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4438 unsigned W = fieldFromInstruction(Insn, 21, 1);
4439 unsigned U = fieldFromInstruction(Insn, 23, 1);
4440 unsigned P = fieldFromInstruction(Insn, 24, 1);
4441 bool writeback = (W == 1) | (P == 0);
4443 addr |= (U << 8) | (Rn << 9);
4445 if (writeback && (Rn == Rt || Rn == Rt2))
4446 Check(S, MCDisassembler::SoftFail);
4448 // Writeback operand
4449 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4450 return MCDisassembler::Fail;
4452 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4453 return MCDisassembler::Fail;
4455 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4456 return MCDisassembler::Fail;
4458 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4459 return MCDisassembler::Fail;
4464 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4465 uint64_t Address, const void *Decoder) {
4466 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4467 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4468 if (sign1 != sign2) return MCDisassembler::Fail;
4470 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4471 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4472 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4474 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4476 return MCDisassembler::Success;
4479 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4481 const void *Decoder) {
4482 DecodeStatus S = MCDisassembler::Success;
4484 // Shift of "asr #32" is not allowed in Thumb2 mode.
4485 if (Val == 0x20) S = MCDisassembler::SoftFail;
4486 Inst.addOperand(MCOperand::CreateImm(Val));
4490 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4491 uint64_t Address, const void *Decoder) {
4492 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4493 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4494 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4495 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4498 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4500 DecodeStatus S = MCDisassembler::Success;
4502 if (Rt == Rn || Rn == Rt2)
4503 S = MCDisassembler::SoftFail;
4505 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4506 return MCDisassembler::Fail;
4507 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4508 return MCDisassembler::Fail;
4509 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4510 return MCDisassembler::Fail;
4511 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4512 return MCDisassembler::Fail;
4517 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4518 uint64_t Address, const void *Decoder) {
4519 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4520 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4521 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4522 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4523 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4524 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4526 DecodeStatus S = MCDisassembler::Success;
4528 // VMOVv2f32 is ambiguous with these decodings.
4529 if (!(imm & 0x38) && cmode == 0xF) {
4530 Inst.setOpcode(ARM::VMOVv2f32);
4531 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4534 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4536 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4537 return MCDisassembler::Fail;
4538 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4539 return MCDisassembler::Fail;
4540 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4545 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4546 uint64_t Address, const void *Decoder) {
4547 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4548 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4549 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4550 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4551 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4552 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4554 DecodeStatus S = MCDisassembler::Success;
4556 // VMOVv4f32 is ambiguous with these decodings.
4557 if (!(imm & 0x38) && cmode == 0xF) {
4558 Inst.setOpcode(ARM::VMOVv4f32);
4559 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4562 if (!(imm & 0x20)) Check(S, MCDisassembler::SoftFail);
4564 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4565 return MCDisassembler::Fail;
4566 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4567 return MCDisassembler::Fail;
4568 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4573 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
4574 const void *Decoder)
4576 unsigned Imm = fieldFromInstruction(Insn, 0, 3);
4577 if (Imm > 4) return MCDisassembler::Fail;
4578 Inst.addOperand(MCOperand::CreateImm(Imm));
4579 return MCDisassembler::Success;
4582 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4583 uint64_t Address, const void *Decoder) {
4584 DecodeStatus S = MCDisassembler::Success;
4586 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4587 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4588 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4589 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4590 unsigned Cond = fieldFromInstruction(Val, 28, 4);
4592 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
4593 S = MCDisassembler::SoftFail;
4595 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4596 return MCDisassembler::Fail;
4597 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4598 return MCDisassembler::Fail;
4599 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4600 return MCDisassembler::Fail;
4601 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4602 return MCDisassembler::Fail;
4603 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4604 return MCDisassembler::Fail;
4609 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4610 uint64_t Address, const void *Decoder) {
4612 DecodeStatus S = MCDisassembler::Success;
4614 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4615 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4616 unsigned cop = fieldFromInstruction(Val, 8, 4);
4617 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4618 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
4620 if ((cop & ~0x1) == 0xa)
4621 return MCDisassembler::Fail;
4624 S = MCDisassembler::SoftFail;
4626 Inst.addOperand(MCOperand::CreateImm(cop));
4627 Inst.addOperand(MCOperand::CreateImm(opc1));
4628 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4629 return MCDisassembler::Fail;
4630 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4631 return MCDisassembler::Fail;
4632 Inst.addOperand(MCOperand::CreateImm(CRm));