1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "arm-disassembler"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 // Handles the condition code status of instructions in IT blocks
38 // Returns the condition code for instruction in IT block
40 unsigned CC = ARMCC::AL;
46 // Advances the IT block state to the next T or E
47 void advanceITState() {
51 // Returns true if the current instruction is in an IT block
52 bool instrInITBlock() {
53 return !ITStates.empty();
56 // Returns true if current instruction is the last instruction in an IT block
57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
61 // Called when decoding an IT instruction. Sets the IT state for the following
62 // instructions that for the IT block. Firstcond and Mask correspond to the
63 // fields in the IT instruction encoding.
64 void setITState(char Firstcond, char Mask) {
65 // (3 - the number of trailing zeros) is the number of then / else.
66 unsigned CondBit0 = Firstcond & 1;
67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 && "Invalid IT mask!");
70 // push condition codes onto the stack the correct order for the pops
71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 ITStates.push_back(CCBits);
76 ITStates.push_back(CCBits ^ 1);
78 ITStates.push_back(CCBits);
82 std::vector<unsigned char> ITStates;
87 /// ARM disassembler for all ARM platforms.
88 class ARMDisassembler : public MCDisassembler {
90 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
91 MCDisassembler(STI, Ctx) {
94 ~ARMDisassembler() override {}
96 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
97 ArrayRef<uint8_t> Bytes, uint64_t Address,
99 raw_ostream &CStream) const override;
102 /// Thumb disassembler for all Thumb platforms.
103 class ThumbDisassembler : public MCDisassembler {
105 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
106 MCDisassembler(STI, Ctx) {
109 ~ThumbDisassembler() override {}
111 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
112 ArrayRef<uint8_t> Bytes, uint64_t Address,
113 raw_ostream &VStream,
114 raw_ostream &CStream) const override;
117 mutable ITStatus ITBlock;
118 DecodeStatus AddThumbPredicate(MCInst&) const;
119 void UpdateThumbVFPPredicate(MCInst&) const;
123 static bool Check(DecodeStatus &Out, DecodeStatus In) {
125 case MCDisassembler::Success:
126 // Out stays the same.
128 case MCDisassembler::SoftFail:
131 case MCDisassembler::Fail:
135 llvm_unreachable("Invalid DecodeStatus!");
139 // Forward declare these because the autogenerated code will reference them.
140 // Definitions are further down.
141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
142 uint64_t Address, const void *Decoder);
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
144 unsigned RegNo, uint64_t Address,
145 const void *Decoder);
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
147 unsigned RegNo, uint64_t Address,
148 const void *Decoder);
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address, const void *Decoder);
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
152 uint64_t Address, const void *Decoder);
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address, const void *Decoder);
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
158 uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
166 const void *Decoder);
167 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
168 uint64_t Address, const void *Decoder);
169 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
170 uint64_t Address, const void *Decoder);
171 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
172 unsigned RegNo, uint64_t Address,
173 const void *Decoder);
175 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
176 uint64_t Address, const void *Decoder);
177 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
178 uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
180 uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
182 uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
184 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
193 const void *Decoder);
194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
201 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
206 const void *Decoder);
207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
236 uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
238 uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
240 uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
242 uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
250 uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
252 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
260 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
262 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
312 uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
314 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
316 uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
320 uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
322 uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
324 uint64_t Address, const void *Decoder);
325 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
326 uint64_t Address, const void *Decoder);
327 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
328 uint64_t Address, const void *Decoder);
329 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
330 uint64_t Address, const void *Decoder);
331 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
332 uint64_t Address, const void *Decoder);
333 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
334 uint64_t Address, const void *Decoder);
335 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
336 uint64_t Address, const void *Decoder);
337 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
338 uint64_t Address, const void *Decoder);
339 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
340 uint64_t Address, const void* Decoder);
341 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
342 uint64_t Address, const void* Decoder);
343 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
344 uint64_t Address, const void* Decoder);
345 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
346 uint64_t Address, const void* Decoder);
347 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
348 uint64_t Address, const void *Decoder);
349 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
350 uint64_t Address, const void *Decoder);
351 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
352 uint64_t Address, const void *Decoder);
353 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
354 uint64_t Address, const void *Decoder);
355 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
356 uint64_t Address, const void *Decoder);
357 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
358 uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
360 uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
362 uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
364 uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
366 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
368 uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
370 uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
372 uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
374 uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
376 uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
378 uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
380 uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
382 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
384 uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
386 uint64_t Address, const void *Decoder);
387 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
388 uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
390 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
395 uint64_t Address, const void *Decoder);
396 #include "ARMGenDisassemblerTables.inc"
398 static MCDisassembler *createARMDisassembler(const Target &T,
399 const MCSubtargetInfo &STI,
401 return new ARMDisassembler(STI, Ctx);
404 static MCDisassembler *createThumbDisassembler(const Target &T,
405 const MCSubtargetInfo &STI,
407 return new ThumbDisassembler(STI, Ctx);
410 // Post-decoding checks
411 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
412 uint64_t Address, raw_ostream &OS,
417 switch (MI.getOpcode()) {
419 // HVC is undefined if condition = 0xf otherwise upredictable
420 // if condition != 0xe
421 uint32_t Cond = (Insn >> 28) & 0xF;
423 return MCDisassembler::Fail;
425 return MCDisassembler::SoftFail;
428 default: return Result;
432 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
433 ArrayRef<uint8_t> Bytes,
434 uint64_t Address, raw_ostream &OS,
435 raw_ostream &CS) const {
438 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
439 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
442 // We want to read exactly 4 bytes of data.
443 if (Bytes.size() < 4) {
445 return MCDisassembler::Fail;
448 // Encoded as a small-endian 32-bit word in the stream.
450 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
452 // Calling the auto-generated decoder function.
453 DecodeStatus Result =
454 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
455 if (Result != MCDisassembler::Fail) {
457 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
460 // VFP and NEON instructions, similarly, are shared between ARM
463 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
464 if (Result != MCDisassembler::Fail) {
470 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
471 if (Result != MCDisassembler::Fail) {
478 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
479 if (Result != MCDisassembler::Fail) {
481 // Add a fake predicate operand, because we share these instruction
482 // definitions with Thumb2 where these instructions are predicable.
483 if (!DecodePredicateOperand(MI, 0xE, Address, this))
484 return MCDisassembler::Fail;
489 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
491 if (Result != MCDisassembler::Fail) {
493 // Add a fake predicate operand, because we share these instruction
494 // definitions with Thumb2 where these instructions are predicable.
495 if (!DecodePredicateOperand(MI, 0xE, Address, this))
496 return MCDisassembler::Fail;
502 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
503 if (Result != MCDisassembler::Fail) {
505 // Add a fake predicate operand, because we share these instruction
506 // definitions with Thumb2 where these instructions are predicable.
507 if (!DecodePredicateOperand(MI, 0xE, Address, this))
508 return MCDisassembler::Fail;
514 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
515 if (Result != MCDisassembler::Fail) {
522 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
523 if (Result != MCDisassembler::Fail) {
530 return MCDisassembler::Fail;
534 extern const MCInstrDesc ARMInsts[];
537 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
538 /// immediate Value in the MCInst. The immediate Value has had any PC
539 /// adjustment made by the caller. If the instruction is a branch instruction
540 /// then isBranch is true, else false. If the getOpInfo() function was set as
541 /// part of the setupForSymbolicDisassembly() call then that function is called
542 /// to get any symbolic information at the Address for this instruction. If
543 /// that returns non-zero then the symbolic information it returns is used to
544 /// create an MCExpr and that is added as an operand to the MCInst. If
545 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
546 /// Value is done and if a symbol is found an MCExpr is created with that, else
547 /// an MCExpr with Value is created. This function returns true if it adds an
548 /// operand to the MCInst and false otherwise.
549 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
550 bool isBranch, uint64_t InstSize,
551 MCInst &MI, const void *Decoder) {
552 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
553 // FIXME: Does it make sense for value to be negative?
554 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
555 /* Offset */ 0, InstSize);
558 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
559 /// referenced by a load instruction with the base register that is the Pc.
560 /// These can often be values in a literal pool near the Address of the
561 /// instruction. The Address of the instruction and its immediate Value are
562 /// used as a possible literal pool entry. The SymbolLookUp call back will
563 /// return the name of a symbol referenced by the literal pool's entry if
564 /// the referenced address is that of a symbol. Or it will return a pointer to
565 /// a literal 'C' string if the referenced address of the literal pool's entry
566 /// is an address into a section with 'C' string literals.
567 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
568 const void *Decoder) {
569 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
570 Dis->tryAddingPcLoadReferenceComment(Value, Address);
573 // Thumb1 instructions don't have explicit S bits. Rather, they
574 // implicitly set CPSR. Since it's not represented in the encoding, the
575 // auto-generated decoder won't inject the CPSR operand. We need to fix
576 // that as a post-pass.
577 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
578 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
579 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
580 MCInst::iterator I = MI.begin();
581 for (unsigned i = 0; i < NumOps; ++i, ++I) {
582 if (I == MI.end()) break;
583 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
584 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
585 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
590 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
593 // Most Thumb instructions don't have explicit predicates in the
594 // encoding, but rather get their predicates from IT context. We need
595 // to fix up the predicate operands using this context information as a
597 MCDisassembler::DecodeStatus
598 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
599 MCDisassembler::DecodeStatus S = Success;
601 // A few instructions actually have predicates encoded in them. Don't
602 // try to overwrite it if we're seeing one of those.
603 switch (MI.getOpcode()) {
614 // Some instructions (mostly conditional branches) are not
615 // allowed in IT blocks.
616 if (ITBlock.instrInITBlock())
625 // Some instructions (mostly unconditional branches) can
626 // only appears at the end of, or outside of, an IT.
627 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
634 // If we're in an IT block, base the predicate on that. Otherwise,
635 // assume a predicate of AL.
637 CC = ITBlock.getITCC();
640 if (ITBlock.instrInITBlock())
641 ITBlock.advanceITState();
643 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
644 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
645 MCInst::iterator I = MI.begin();
646 for (unsigned i = 0; i < NumOps; ++i, ++I) {
647 if (I == MI.end()) break;
648 if (OpInfo[i].isPredicate()) {
649 I = MI.insert(I, MCOperand::CreateImm(CC));
652 MI.insert(I, MCOperand::CreateReg(0));
654 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
659 I = MI.insert(I, MCOperand::CreateImm(CC));
662 MI.insert(I, MCOperand::CreateReg(0));
664 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
669 // Thumb VFP instructions are a special case. Because we share their
670 // encodings between ARM and Thumb modes, and they are predicable in ARM
671 // mode, the auto-generated decoder will give them an (incorrect)
672 // predicate operand. We need to rewrite these operands based on the IT
673 // context as a post-pass.
674 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
676 CC = ITBlock.getITCC();
677 if (ITBlock.instrInITBlock())
678 ITBlock.advanceITState();
680 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
681 MCInst::iterator I = MI.begin();
682 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
683 for (unsigned i = 0; i < NumOps; ++i, ++I) {
684 if (OpInfo[i].isPredicate() ) {
690 I->setReg(ARM::CPSR);
696 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
697 ArrayRef<uint8_t> Bytes,
700 raw_ostream &CS) const {
703 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
704 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
706 // We want to read exactly 2 bytes of data.
707 if (Bytes.size() < 2) {
709 return MCDisassembler::Fail;
712 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
713 DecodeStatus Result =
714 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
715 if (Result != MCDisassembler::Fail) {
717 Check(Result, AddThumbPredicate(MI));
722 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
726 bool InITBlock = ITBlock.instrInITBlock();
727 Check(Result, AddThumbPredicate(MI));
728 AddThumb1SBit(MI, InITBlock);
734 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
735 if (Result != MCDisassembler::Fail) {
738 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
739 // the Thumb predicate.
740 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
741 Result = MCDisassembler::SoftFail;
743 Check(Result, AddThumbPredicate(MI));
745 // If we find an IT instruction, we need to parse its condition
746 // code and mask operands so that we can apply them correctly
747 // to the subsequent instructions.
748 if (MI.getOpcode() == ARM::t2IT) {
750 unsigned Firstcond = MI.getOperand(0).getImm();
751 unsigned Mask = MI.getOperand(1).getImm();
752 ITBlock.setITState(Firstcond, Mask);
758 // We want to read exactly 4 bytes of data.
759 if (Bytes.size() < 4) {
761 return MCDisassembler::Fail;
765 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
768 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
769 if (Result != MCDisassembler::Fail) {
771 bool InITBlock = ITBlock.instrInITBlock();
772 Check(Result, AddThumbPredicate(MI));
773 AddThumb1SBit(MI, InITBlock);
779 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
780 if (Result != MCDisassembler::Fail) {
782 Check(Result, AddThumbPredicate(MI));
786 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
789 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
790 if (Result != MCDisassembler::Fail) {
792 UpdateThumbVFPPredicate(MI);
799 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
800 if (Result != MCDisassembler::Fail) {
805 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
807 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
809 if (Result != MCDisassembler::Fail) {
811 Check(Result, AddThumbPredicate(MI));
816 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
818 uint32_t NEONLdStInsn = Insn32;
819 NEONLdStInsn &= 0xF0FFFFFF;
820 NEONLdStInsn |= 0x04000000;
821 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
823 if (Result != MCDisassembler::Fail) {
825 Check(Result, AddThumbPredicate(MI));
830 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
832 uint32_t NEONDataInsn = Insn32;
833 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
834 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
835 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
836 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
838 if (Result != MCDisassembler::Fail) {
840 Check(Result, AddThumbPredicate(MI));
845 uint32_t NEONCryptoInsn = Insn32;
846 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
847 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
848 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
849 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
851 if (Result != MCDisassembler::Fail) {
857 uint32_t NEONv8Insn = Insn32;
858 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
859 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
861 if (Result != MCDisassembler::Fail) {
869 return MCDisassembler::Fail;
873 extern "C" void LLVMInitializeARMDisassembler() {
874 TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
875 createARMDisassembler);
876 TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
877 createARMDisassembler);
878 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
879 createThumbDisassembler);
880 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
881 createThumbDisassembler);
884 static const uint16_t GPRDecoderTable[] = {
885 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
886 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
887 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
888 ARM::R12, ARM::SP, ARM::LR, ARM::PC
891 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
892 uint64_t Address, const void *Decoder) {
894 return MCDisassembler::Fail;
896 unsigned Register = GPRDecoderTable[RegNo];
897 Inst.addOperand(MCOperand::CreateReg(Register));
898 return MCDisassembler::Success;
902 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
903 uint64_t Address, const void *Decoder) {
904 DecodeStatus S = MCDisassembler::Success;
907 S = MCDisassembler::SoftFail;
909 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
915 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
916 uint64_t Address, const void *Decoder) {
917 DecodeStatus S = MCDisassembler::Success;
921 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
922 return MCDisassembler::Success;
925 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
929 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
930 uint64_t Address, const void *Decoder) {
932 return MCDisassembler::Fail;
933 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
936 static const uint16_t GPRPairDecoderTable[] = {
937 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
938 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
941 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
942 uint64_t Address, const void *Decoder) {
943 DecodeStatus S = MCDisassembler::Success;
946 return MCDisassembler::Fail;
948 if ((RegNo & 1) || RegNo == 0xe)
949 S = MCDisassembler::SoftFail;
951 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
952 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
956 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
957 uint64_t Address, const void *Decoder) {
958 unsigned Register = 0;
979 return MCDisassembler::Fail;
982 Inst.addOperand(MCOperand::CreateReg(Register));
983 return MCDisassembler::Success;
986 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
987 uint64_t Address, const void *Decoder) {
988 DecodeStatus S = MCDisassembler::Success;
989 if (RegNo == 13 || RegNo == 15)
990 S = MCDisassembler::SoftFail;
991 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
995 static const uint16_t SPRDecoderTable[] = {
996 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
997 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
998 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
999 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
1000 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
1001 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
1002 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
1003 ARM::S28, ARM::S29, ARM::S30, ARM::S31
1006 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1007 uint64_t Address, const void *Decoder) {
1009 return MCDisassembler::Fail;
1011 unsigned Register = SPRDecoderTable[RegNo];
1012 Inst.addOperand(MCOperand::CreateReg(Register));
1013 return MCDisassembler::Success;
1016 static const uint16_t DPRDecoderTable[] = {
1017 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1018 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1019 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1020 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1021 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1022 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1023 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1024 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1027 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1028 uint64_t Address, const void *Decoder) {
1029 const FeatureBitset &featureBits =
1030 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1032 bool hasD16 = featureBits[ARM::FeatureD16];
1034 if (RegNo > 31 || (hasD16 && RegNo > 15))
1035 return MCDisassembler::Fail;
1037 unsigned Register = DPRDecoderTable[RegNo];
1038 Inst.addOperand(MCOperand::CreateReg(Register));
1039 return MCDisassembler::Success;
1042 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1043 uint64_t Address, const void *Decoder) {
1045 return MCDisassembler::Fail;
1046 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1050 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1051 uint64_t Address, const void *Decoder) {
1053 return MCDisassembler::Fail;
1054 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1057 static const uint16_t QPRDecoderTable[] = {
1058 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1059 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1060 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1061 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1065 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1066 uint64_t Address, const void *Decoder) {
1067 if (RegNo > 31 || (RegNo & 1) != 0)
1068 return MCDisassembler::Fail;
1071 unsigned Register = QPRDecoderTable[RegNo];
1072 Inst.addOperand(MCOperand::CreateReg(Register));
1073 return MCDisassembler::Success;
1076 static const uint16_t DPairDecoderTable[] = {
1077 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1078 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1079 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1080 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1081 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1085 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1086 uint64_t Address, const void *Decoder) {
1088 return MCDisassembler::Fail;
1090 unsigned Register = DPairDecoderTable[RegNo];
1091 Inst.addOperand(MCOperand::CreateReg(Register));
1092 return MCDisassembler::Success;
1095 static const uint16_t DPairSpacedDecoderTable[] = {
1096 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1097 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1098 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1099 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1100 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1101 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1102 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1103 ARM::D28_D30, ARM::D29_D31
1106 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1109 const void *Decoder) {
1111 return MCDisassembler::Fail;
1113 unsigned Register = DPairSpacedDecoderTable[RegNo];
1114 Inst.addOperand(MCOperand::CreateReg(Register));
1115 return MCDisassembler::Success;
1118 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1119 uint64_t Address, const void *Decoder) {
1120 if (Val == 0xF) return MCDisassembler::Fail;
1121 // AL predicate is not allowed on Thumb1 branches.
1122 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1123 return MCDisassembler::Fail;
1124 Inst.addOperand(MCOperand::CreateImm(Val));
1125 if (Val == ARMCC::AL) {
1126 Inst.addOperand(MCOperand::CreateReg(0));
1128 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1129 return MCDisassembler::Success;
1132 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1133 uint64_t Address, const void *Decoder) {
1135 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1137 Inst.addOperand(MCOperand::CreateReg(0));
1138 return MCDisassembler::Success;
1141 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1142 uint64_t Address, const void *Decoder) {
1143 DecodeStatus S = MCDisassembler::Success;
1145 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1146 unsigned type = fieldFromInstruction(Val, 5, 2);
1147 unsigned imm = fieldFromInstruction(Val, 7, 5);
1149 // Register-immediate
1150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1151 return MCDisassembler::Fail;
1153 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1156 Shift = ARM_AM::lsl;
1159 Shift = ARM_AM::lsr;
1162 Shift = ARM_AM::asr;
1165 Shift = ARM_AM::ror;
1169 if (Shift == ARM_AM::ror && imm == 0)
1170 Shift = ARM_AM::rrx;
1172 unsigned Op = Shift | (imm << 3);
1173 Inst.addOperand(MCOperand::CreateImm(Op));
1178 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1179 uint64_t Address, const void *Decoder) {
1180 DecodeStatus S = MCDisassembler::Success;
1182 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1183 unsigned type = fieldFromInstruction(Val, 5, 2);
1184 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1186 // Register-register
1187 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1188 return MCDisassembler::Fail;
1189 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1190 return MCDisassembler::Fail;
1192 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1195 Shift = ARM_AM::lsl;
1198 Shift = ARM_AM::lsr;
1201 Shift = ARM_AM::asr;
1204 Shift = ARM_AM::ror;
1208 Inst.addOperand(MCOperand::CreateImm(Shift));
1213 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1214 uint64_t Address, const void *Decoder) {
1215 DecodeStatus S = MCDisassembler::Success;
1217 bool NeedDisjointWriteback = false;
1218 unsigned WritebackReg = 0;
1219 switch (Inst.getOpcode()) {
1222 case ARM::LDMIA_UPD:
1223 case ARM::LDMDB_UPD:
1224 case ARM::LDMIB_UPD:
1225 case ARM::LDMDA_UPD:
1226 case ARM::t2LDMIA_UPD:
1227 case ARM::t2LDMDB_UPD:
1228 case ARM::t2STMIA_UPD:
1229 case ARM::t2STMDB_UPD:
1230 NeedDisjointWriteback = true;
1231 WritebackReg = Inst.getOperand(0).getReg();
1235 // Empty register lists are not allowed.
1236 if (Val == 0) return MCDisassembler::Fail;
1237 for (unsigned i = 0; i < 16; ++i) {
1238 if (Val & (1 << i)) {
1239 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1240 return MCDisassembler::Fail;
1241 // Writeback not allowed if Rn is in the target list.
1242 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1243 Check(S, MCDisassembler::SoftFail);
1250 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1251 uint64_t Address, const void *Decoder) {
1252 DecodeStatus S = MCDisassembler::Success;
1254 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1255 unsigned regs = fieldFromInstruction(Val, 0, 8);
1257 // In case of unpredictable encoding, tweak the operands.
1258 if (regs == 0 || (Vd + regs) > 32) {
1259 regs = Vd + regs > 32 ? 32 - Vd : regs;
1260 regs = std::max( 1u, regs);
1261 S = MCDisassembler::SoftFail;
1264 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1265 return MCDisassembler::Fail;
1266 for (unsigned i = 0; i < (regs - 1); ++i) {
1267 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1268 return MCDisassembler::Fail;
1274 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1275 uint64_t Address, const void *Decoder) {
1276 DecodeStatus S = MCDisassembler::Success;
1278 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1279 unsigned regs = fieldFromInstruction(Val, 1, 7);
1281 // In case of unpredictable encoding, tweak the operands.
1282 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1283 regs = Vd + regs > 32 ? 32 - Vd : regs;
1284 regs = std::max( 1u, regs);
1285 regs = std::min(16u, regs);
1286 S = MCDisassembler::SoftFail;
1289 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1290 return MCDisassembler::Fail;
1291 for (unsigned i = 0; i < (regs - 1); ++i) {
1292 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1293 return MCDisassembler::Fail;
1299 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1300 uint64_t Address, const void *Decoder) {
1301 // This operand encodes a mask of contiguous zeros between a specified MSB
1302 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1303 // the mask of all bits LSB-and-lower, and then xor them to create
1304 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1305 // create the final mask.
1306 unsigned msb = fieldFromInstruction(Val, 5, 5);
1307 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1309 DecodeStatus S = MCDisassembler::Success;
1311 Check(S, MCDisassembler::SoftFail);
1312 // The check above will cause the warning for the "potentially undefined
1313 // instruction encoding" but we can't build a bad MCOperand value here
1314 // with a lsb > msb or else printing the MCInst will cause a crash.
1318 uint32_t msb_mask = 0xFFFFFFFF;
1319 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1320 uint32_t lsb_mask = (1U << lsb) - 1;
1322 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1326 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1327 uint64_t Address, const void *Decoder) {
1328 DecodeStatus S = MCDisassembler::Success;
1330 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1331 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1332 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1333 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1334 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1335 unsigned U = fieldFromInstruction(Insn, 23, 1);
1337 switch (Inst.getOpcode()) {
1338 case ARM::LDC_OFFSET:
1341 case ARM::LDC_OPTION:
1342 case ARM::LDCL_OFFSET:
1344 case ARM::LDCL_POST:
1345 case ARM::LDCL_OPTION:
1346 case ARM::STC_OFFSET:
1349 case ARM::STC_OPTION:
1350 case ARM::STCL_OFFSET:
1352 case ARM::STCL_POST:
1353 case ARM::STCL_OPTION:
1354 case ARM::t2LDC_OFFSET:
1355 case ARM::t2LDC_PRE:
1356 case ARM::t2LDC_POST:
1357 case ARM::t2LDC_OPTION:
1358 case ARM::t2LDCL_OFFSET:
1359 case ARM::t2LDCL_PRE:
1360 case ARM::t2LDCL_POST:
1361 case ARM::t2LDCL_OPTION:
1362 case ARM::t2STC_OFFSET:
1363 case ARM::t2STC_PRE:
1364 case ARM::t2STC_POST:
1365 case ARM::t2STC_OPTION:
1366 case ARM::t2STCL_OFFSET:
1367 case ARM::t2STCL_PRE:
1368 case ARM::t2STCL_POST:
1369 case ARM::t2STCL_OPTION:
1370 if (coproc == 0xA || coproc == 0xB)
1371 return MCDisassembler::Fail;
1377 const FeatureBitset &featureBits =
1378 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1379 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1380 return MCDisassembler::Fail;
1382 Inst.addOperand(MCOperand::CreateImm(coproc));
1383 Inst.addOperand(MCOperand::CreateImm(CRd));
1384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1385 return MCDisassembler::Fail;
1387 switch (Inst.getOpcode()) {
1388 case ARM::t2LDC2_OFFSET:
1389 case ARM::t2LDC2L_OFFSET:
1390 case ARM::t2LDC2_PRE:
1391 case ARM::t2LDC2L_PRE:
1392 case ARM::t2STC2_OFFSET:
1393 case ARM::t2STC2L_OFFSET:
1394 case ARM::t2STC2_PRE:
1395 case ARM::t2STC2L_PRE:
1396 case ARM::LDC2_OFFSET:
1397 case ARM::LDC2L_OFFSET:
1399 case ARM::LDC2L_PRE:
1400 case ARM::STC2_OFFSET:
1401 case ARM::STC2L_OFFSET:
1403 case ARM::STC2L_PRE:
1404 case ARM::t2LDC_OFFSET:
1405 case ARM::t2LDCL_OFFSET:
1406 case ARM::t2LDC_PRE:
1407 case ARM::t2LDCL_PRE:
1408 case ARM::t2STC_OFFSET:
1409 case ARM::t2STCL_OFFSET:
1410 case ARM::t2STC_PRE:
1411 case ARM::t2STCL_PRE:
1412 case ARM::LDC_OFFSET:
1413 case ARM::LDCL_OFFSET:
1416 case ARM::STC_OFFSET:
1417 case ARM::STCL_OFFSET:
1420 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1421 Inst.addOperand(MCOperand::CreateImm(imm));
1423 case ARM::t2LDC2_POST:
1424 case ARM::t2LDC2L_POST:
1425 case ARM::t2STC2_POST:
1426 case ARM::t2STC2L_POST:
1427 case ARM::LDC2_POST:
1428 case ARM::LDC2L_POST:
1429 case ARM::STC2_POST:
1430 case ARM::STC2L_POST:
1431 case ARM::t2LDC_POST:
1432 case ARM::t2LDCL_POST:
1433 case ARM::t2STC_POST:
1434 case ARM::t2STCL_POST:
1436 case ARM::LDCL_POST:
1438 case ARM::STCL_POST:
1442 // The 'option' variant doesn't encode 'U' in the immediate since
1443 // the immediate is unsigned [0,255].
1444 Inst.addOperand(MCOperand::CreateImm(imm));
1448 switch (Inst.getOpcode()) {
1449 case ARM::LDC_OFFSET:
1452 case ARM::LDC_OPTION:
1453 case ARM::LDCL_OFFSET:
1455 case ARM::LDCL_POST:
1456 case ARM::LDCL_OPTION:
1457 case ARM::STC_OFFSET:
1460 case ARM::STC_OPTION:
1461 case ARM::STCL_OFFSET:
1463 case ARM::STCL_POST:
1464 case ARM::STCL_OPTION:
1465 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1466 return MCDisassembler::Fail;
1476 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1477 uint64_t Address, const void *Decoder) {
1478 DecodeStatus S = MCDisassembler::Success;
1480 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1481 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1482 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1483 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1484 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1485 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1486 unsigned P = fieldFromInstruction(Insn, 24, 1);
1487 unsigned W = fieldFromInstruction(Insn, 21, 1);
1489 // On stores, the writeback operand precedes Rt.
1490 switch (Inst.getOpcode()) {
1491 case ARM::STR_POST_IMM:
1492 case ARM::STR_POST_REG:
1493 case ARM::STRB_POST_IMM:
1494 case ARM::STRB_POST_REG:
1495 case ARM::STRT_POST_REG:
1496 case ARM::STRT_POST_IMM:
1497 case ARM::STRBT_POST_REG:
1498 case ARM::STRBT_POST_IMM:
1499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1500 return MCDisassembler::Fail;
1506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1507 return MCDisassembler::Fail;
1509 // On loads, the writeback operand comes after Rt.
1510 switch (Inst.getOpcode()) {
1511 case ARM::LDR_POST_IMM:
1512 case ARM::LDR_POST_REG:
1513 case ARM::LDRB_POST_IMM:
1514 case ARM::LDRB_POST_REG:
1515 case ARM::LDRBT_POST_REG:
1516 case ARM::LDRBT_POST_IMM:
1517 case ARM::LDRT_POST_REG:
1518 case ARM::LDRT_POST_IMM:
1519 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1520 return MCDisassembler::Fail;
1526 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1527 return MCDisassembler::Fail;
1529 ARM_AM::AddrOpc Op = ARM_AM::add;
1530 if (!fieldFromInstruction(Insn, 23, 1))
1533 bool writeback = (P == 0) || (W == 1);
1534 unsigned idx_mode = 0;
1536 idx_mode = ARMII::IndexModePre;
1537 else if (!P && writeback)
1538 idx_mode = ARMII::IndexModePost;
1540 if (writeback && (Rn == 15 || Rn == Rt))
1541 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1544 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1545 return MCDisassembler::Fail;
1546 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1547 switch( fieldFromInstruction(Insn, 5, 2)) {
1561 return MCDisassembler::Fail;
1563 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1564 if (Opc == ARM_AM::ror && amt == 0)
1566 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1568 Inst.addOperand(MCOperand::CreateImm(imm));
1570 Inst.addOperand(MCOperand::CreateReg(0));
1571 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1572 Inst.addOperand(MCOperand::CreateImm(tmp));
1575 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1576 return MCDisassembler::Fail;
1581 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1582 uint64_t Address, const void *Decoder) {
1583 DecodeStatus S = MCDisassembler::Success;
1585 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1586 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1587 unsigned type = fieldFromInstruction(Val, 5, 2);
1588 unsigned imm = fieldFromInstruction(Val, 7, 5);
1589 unsigned U = fieldFromInstruction(Val, 12, 1);
1591 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1607 if (ShOp == ARM_AM::ror && imm == 0)
1610 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1611 return MCDisassembler::Fail;
1612 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1613 return MCDisassembler::Fail;
1616 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1618 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1619 Inst.addOperand(MCOperand::CreateImm(shift));
1625 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1626 uint64_t Address, const void *Decoder) {
1627 DecodeStatus S = MCDisassembler::Success;
1629 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1630 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1631 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1632 unsigned type = fieldFromInstruction(Insn, 22, 1);
1633 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1634 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1635 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1636 unsigned W = fieldFromInstruction(Insn, 21, 1);
1637 unsigned P = fieldFromInstruction(Insn, 24, 1);
1638 unsigned Rt2 = Rt + 1;
1640 bool writeback = (W == 1) | (P == 0);
1642 // For {LD,ST}RD, Rt must be even, else undefined.
1643 switch (Inst.getOpcode()) {
1646 case ARM::STRD_POST:
1649 case ARM::LDRD_POST:
1650 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1655 switch (Inst.getOpcode()) {
1658 case ARM::STRD_POST:
1659 if (P == 0 && W == 1)
1660 S = MCDisassembler::SoftFail;
1662 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1663 S = MCDisassembler::SoftFail;
1664 if (type && Rm == 15)
1665 S = MCDisassembler::SoftFail;
1667 S = MCDisassembler::SoftFail;
1668 if (!type && fieldFromInstruction(Insn, 8, 4))
1669 S = MCDisassembler::SoftFail;
1673 case ARM::STRH_POST:
1675 S = MCDisassembler::SoftFail;
1676 if (writeback && (Rn == 15 || Rn == Rt))
1677 S = MCDisassembler::SoftFail;
1678 if (!type && Rm == 15)
1679 S = MCDisassembler::SoftFail;
1683 case ARM::LDRD_POST:
1684 if (type && Rn == 15){
1686 S = MCDisassembler::SoftFail;
1689 if (P == 0 && W == 1)
1690 S = MCDisassembler::SoftFail;
1691 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1692 S = MCDisassembler::SoftFail;
1693 if (!type && writeback && Rn == 15)
1694 S = MCDisassembler::SoftFail;
1695 if (writeback && (Rn == Rt || Rn == Rt2))
1696 S = MCDisassembler::SoftFail;
1700 case ARM::LDRH_POST:
1701 if (type && Rn == 15){
1703 S = MCDisassembler::SoftFail;
1707 S = MCDisassembler::SoftFail;
1708 if (!type && Rm == 15)
1709 S = MCDisassembler::SoftFail;
1710 if (!type && writeback && (Rn == 15 || Rn == Rt))
1711 S = MCDisassembler::SoftFail;
1714 case ARM::LDRSH_PRE:
1715 case ARM::LDRSH_POST:
1717 case ARM::LDRSB_PRE:
1718 case ARM::LDRSB_POST:
1719 if (type && Rn == 15){
1721 S = MCDisassembler::SoftFail;
1724 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1725 S = MCDisassembler::SoftFail;
1726 if (!type && (Rt == 15 || Rm == 15))
1727 S = MCDisassembler::SoftFail;
1728 if (!type && writeback && (Rn == 15 || Rn == Rt))
1729 S = MCDisassembler::SoftFail;
1735 if (writeback) { // Writeback
1737 U |= ARMII::IndexModePre << 9;
1739 U |= ARMII::IndexModePost << 9;
1741 // On stores, the writeback operand precedes Rt.
1742 switch (Inst.getOpcode()) {
1745 case ARM::STRD_POST:
1748 case ARM::STRH_POST:
1749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1750 return MCDisassembler::Fail;
1757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1758 return MCDisassembler::Fail;
1759 switch (Inst.getOpcode()) {
1762 case ARM::STRD_POST:
1765 case ARM::LDRD_POST:
1766 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1767 return MCDisassembler::Fail;
1774 // On loads, the writeback operand comes after Rt.
1775 switch (Inst.getOpcode()) {
1778 case ARM::LDRD_POST:
1781 case ARM::LDRH_POST:
1783 case ARM::LDRSH_PRE:
1784 case ARM::LDRSH_POST:
1786 case ARM::LDRSB_PRE:
1787 case ARM::LDRSB_POST:
1790 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1791 return MCDisassembler::Fail;
1798 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1799 return MCDisassembler::Fail;
1802 Inst.addOperand(MCOperand::CreateReg(0));
1803 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1806 return MCDisassembler::Fail;
1807 Inst.addOperand(MCOperand::CreateImm(U));
1810 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1811 return MCDisassembler::Fail;
1816 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1817 uint64_t Address, const void *Decoder) {
1818 DecodeStatus S = MCDisassembler::Success;
1820 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1821 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1838 Inst.addOperand(MCOperand::CreateImm(mode));
1839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1840 return MCDisassembler::Fail;
1845 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1846 uint64_t Address, const void *Decoder) {
1847 DecodeStatus S = MCDisassembler::Success;
1849 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1850 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1851 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1852 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1855 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1857 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1858 return MCDisassembler::Fail;
1859 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1860 return MCDisassembler::Fail;
1861 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1862 return MCDisassembler::Fail;
1863 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1864 return MCDisassembler::Fail;
1868 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1870 uint64_t Address, const void *Decoder) {
1871 DecodeStatus S = MCDisassembler::Success;
1873 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1874 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1875 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1878 // Ambiguous with RFE and SRS
1879 switch (Inst.getOpcode()) {
1881 Inst.setOpcode(ARM::RFEDA);
1883 case ARM::LDMDA_UPD:
1884 Inst.setOpcode(ARM::RFEDA_UPD);
1887 Inst.setOpcode(ARM::RFEDB);
1889 case ARM::LDMDB_UPD:
1890 Inst.setOpcode(ARM::RFEDB_UPD);
1893 Inst.setOpcode(ARM::RFEIA);
1895 case ARM::LDMIA_UPD:
1896 Inst.setOpcode(ARM::RFEIA_UPD);
1899 Inst.setOpcode(ARM::RFEIB);
1901 case ARM::LDMIB_UPD:
1902 Inst.setOpcode(ARM::RFEIB_UPD);
1905 Inst.setOpcode(ARM::SRSDA);
1907 case ARM::STMDA_UPD:
1908 Inst.setOpcode(ARM::SRSDA_UPD);
1911 Inst.setOpcode(ARM::SRSDB);
1913 case ARM::STMDB_UPD:
1914 Inst.setOpcode(ARM::SRSDB_UPD);
1917 Inst.setOpcode(ARM::SRSIA);
1919 case ARM::STMIA_UPD:
1920 Inst.setOpcode(ARM::SRSIA_UPD);
1923 Inst.setOpcode(ARM::SRSIB);
1925 case ARM::STMIB_UPD:
1926 Inst.setOpcode(ARM::SRSIB_UPD);
1929 return MCDisassembler::Fail;
1932 // For stores (which become SRS's, the only operand is the mode.
1933 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1934 // Check SRS encoding constraints
1935 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1936 fieldFromInstruction(Insn, 20, 1) == 0))
1937 return MCDisassembler::Fail;
1940 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1944 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1947 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1948 return MCDisassembler::Fail;
1949 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1950 return MCDisassembler::Fail; // Tied
1951 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1952 return MCDisassembler::Fail;
1953 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1954 return MCDisassembler::Fail;
1959 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1960 uint64_t Address, const void *Decoder) {
1961 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1962 unsigned M = fieldFromInstruction(Insn, 17, 1);
1963 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1964 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1966 DecodeStatus S = MCDisassembler::Success;
1968 // This decoder is called from multiple location that do not check
1969 // the full encoding is valid before they do.
1970 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1971 fieldFromInstruction(Insn, 16, 1) != 0 ||
1972 fieldFromInstruction(Insn, 20, 8) != 0x10)
1973 return MCDisassembler::Fail;
1975 // imod == '01' --> UNPREDICTABLE
1976 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1977 // return failure here. The '01' imod value is unprintable, so there's
1978 // nothing useful we could do even if we returned UNPREDICTABLE.
1980 if (imod == 1) return MCDisassembler::Fail;
1983 Inst.setOpcode(ARM::CPS3p);
1984 Inst.addOperand(MCOperand::CreateImm(imod));
1985 Inst.addOperand(MCOperand::CreateImm(iflags));
1986 Inst.addOperand(MCOperand::CreateImm(mode));
1987 } else if (imod && !M) {
1988 Inst.setOpcode(ARM::CPS2p);
1989 Inst.addOperand(MCOperand::CreateImm(imod));
1990 Inst.addOperand(MCOperand::CreateImm(iflags));
1991 if (mode) S = MCDisassembler::SoftFail;
1992 } else if (!imod && M) {
1993 Inst.setOpcode(ARM::CPS1p);
1994 Inst.addOperand(MCOperand::CreateImm(mode));
1995 if (iflags) S = MCDisassembler::SoftFail;
1997 // imod == '00' && M == '0' --> UNPREDICTABLE
1998 Inst.setOpcode(ARM::CPS1p);
1999 Inst.addOperand(MCOperand::CreateImm(mode));
2000 S = MCDisassembler::SoftFail;
2006 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2007 uint64_t Address, const void *Decoder) {
2008 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2009 unsigned M = fieldFromInstruction(Insn, 8, 1);
2010 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2011 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2013 DecodeStatus S = MCDisassembler::Success;
2015 // imod == '01' --> UNPREDICTABLE
2016 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2017 // return failure here. The '01' imod value is unprintable, so there's
2018 // nothing useful we could do even if we returned UNPREDICTABLE.
2020 if (imod == 1) return MCDisassembler::Fail;
2023 Inst.setOpcode(ARM::t2CPS3p);
2024 Inst.addOperand(MCOperand::CreateImm(imod));
2025 Inst.addOperand(MCOperand::CreateImm(iflags));
2026 Inst.addOperand(MCOperand::CreateImm(mode));
2027 } else if (imod && !M) {
2028 Inst.setOpcode(ARM::t2CPS2p);
2029 Inst.addOperand(MCOperand::CreateImm(imod));
2030 Inst.addOperand(MCOperand::CreateImm(iflags));
2031 if (mode) S = MCDisassembler::SoftFail;
2032 } else if (!imod && M) {
2033 Inst.setOpcode(ARM::t2CPS1p);
2034 Inst.addOperand(MCOperand::CreateImm(mode));
2035 if (iflags) S = MCDisassembler::SoftFail;
2037 // imod == '00' && M == '0' --> this is a HINT instruction
2038 int imm = fieldFromInstruction(Insn, 0, 8);
2039 // HINT are defined only for immediate in [0..4]
2040 if(imm > 4) return MCDisassembler::Fail;
2041 Inst.setOpcode(ARM::t2HINT);
2042 Inst.addOperand(MCOperand::CreateImm(imm));
2048 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2049 uint64_t Address, const void *Decoder) {
2050 DecodeStatus S = MCDisassembler::Success;
2052 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2055 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2056 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2057 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2058 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2060 if (Inst.getOpcode() == ARM::t2MOVTi16)
2061 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2062 return MCDisassembler::Fail;
2063 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2064 return MCDisassembler::Fail;
2066 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2067 Inst.addOperand(MCOperand::CreateImm(imm));
2072 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2073 uint64_t Address, const void *Decoder) {
2074 DecodeStatus S = MCDisassembler::Success;
2076 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2077 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2080 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2081 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2083 if (Inst.getOpcode() == ARM::MOVTi16)
2084 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2085 return MCDisassembler::Fail;
2087 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2088 return MCDisassembler::Fail;
2090 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2091 Inst.addOperand(MCOperand::CreateImm(imm));
2093 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2094 return MCDisassembler::Fail;
2099 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2100 uint64_t Address, const void *Decoder) {
2101 DecodeStatus S = MCDisassembler::Success;
2103 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2104 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2105 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2106 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2107 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2110 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2112 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2113 return MCDisassembler::Fail;
2114 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2115 return MCDisassembler::Fail;
2116 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2117 return MCDisassembler::Fail;
2118 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2119 return MCDisassembler::Fail;
2121 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2122 return MCDisassembler::Fail;
2127 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2128 uint64_t Address, const void *Decoder) {
2129 DecodeStatus S = MCDisassembler::Success;
2131 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2132 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2133 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2136 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2139 return MCDisassembler::Fail;
2140 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2141 return MCDisassembler::Fail;
2142 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2143 return MCDisassembler::Fail;
2148 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2149 uint64_t Address, const void *Decoder) {
2150 DecodeStatus S = MCDisassembler::Success;
2152 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2154 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2155 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2157 if (!FeatureBits[ARM::HasV8_1aOps] ||
2158 !FeatureBits[ARM::HasV8Ops])
2159 return MCDisassembler::Fail;
2161 // Decoder can be called from DecodeTST, which does not check the full
2162 // encoding is valid.
2163 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2164 fieldFromInstruction(Insn, 4,4) != 0)
2165 return MCDisassembler::Fail;
2166 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2167 fieldFromInstruction(Insn, 0,4) != 0)
2168 S = MCDisassembler::SoftFail;
2170 Inst.setOpcode(ARM::SETPAN);
2171 Inst.addOperand(MCOperand::CreateImm(Imm));
2176 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2177 uint64_t Address, const void *Decoder) {
2178 DecodeStatus S = MCDisassembler::Success;
2180 unsigned add = fieldFromInstruction(Val, 12, 1);
2181 unsigned imm = fieldFromInstruction(Val, 0, 12);
2182 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2185 return MCDisassembler::Fail;
2187 if (!add) imm *= -1;
2188 if (imm == 0 && !add) imm = INT32_MIN;
2189 Inst.addOperand(MCOperand::CreateImm(imm));
2191 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2196 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2197 uint64_t Address, const void *Decoder) {
2198 DecodeStatus S = MCDisassembler::Success;
2200 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2201 unsigned U = fieldFromInstruction(Val, 8, 1);
2202 unsigned imm = fieldFromInstruction(Val, 0, 8);
2204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2205 return MCDisassembler::Fail;
2208 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2210 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2215 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2216 uint64_t Address, const void *Decoder) {
2217 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2221 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2222 uint64_t Address, const void *Decoder) {
2223 DecodeStatus Status = MCDisassembler::Success;
2225 // Note the J1 and J2 values are from the encoded instruction. So here
2226 // change them to I1 and I2 values via as documented:
2227 // I1 = NOT(J1 EOR S);
2228 // I2 = NOT(J2 EOR S);
2229 // and build the imm32 with one trailing zero as documented:
2230 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2231 unsigned S = fieldFromInstruction(Insn, 26, 1);
2232 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2233 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2234 unsigned I1 = !(J1 ^ S);
2235 unsigned I2 = !(J2 ^ S);
2236 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2237 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2238 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2239 int imm32 = SignExtend32<25>(tmp << 1);
2240 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2241 true, 4, Inst, Decoder))
2242 Inst.addOperand(MCOperand::CreateImm(imm32));
2248 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2249 uint64_t Address, const void *Decoder) {
2250 DecodeStatus S = MCDisassembler::Success;
2252 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2253 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2256 Inst.setOpcode(ARM::BLXi);
2257 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2258 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2259 true, 4, Inst, Decoder))
2260 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2264 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2265 true, 4, Inst, Decoder))
2266 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2267 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2268 return MCDisassembler::Fail;
2274 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2275 uint64_t Address, const void *Decoder) {
2276 DecodeStatus S = MCDisassembler::Success;
2278 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2279 unsigned align = fieldFromInstruction(Val, 4, 2);
2281 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2282 return MCDisassembler::Fail;
2284 Inst.addOperand(MCOperand::CreateImm(0));
2286 Inst.addOperand(MCOperand::CreateImm(4 << align));
2291 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2292 uint64_t Address, const void *Decoder) {
2293 DecodeStatus S = MCDisassembler::Success;
2295 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2296 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2297 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2298 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2299 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2300 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2302 // First output register
2303 switch (Inst.getOpcode()) {
2304 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2305 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2306 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2307 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2308 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2309 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2310 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2311 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2312 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2313 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2314 return MCDisassembler::Fail;
2319 case ARM::VLD2b16wb_fixed:
2320 case ARM::VLD2b16wb_register:
2321 case ARM::VLD2b32wb_fixed:
2322 case ARM::VLD2b32wb_register:
2323 case ARM::VLD2b8wb_fixed:
2324 case ARM::VLD2b8wb_register:
2325 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2326 return MCDisassembler::Fail;
2329 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2330 return MCDisassembler::Fail;
2333 // Second output register
2334 switch (Inst.getOpcode()) {
2338 case ARM::VLD3d8_UPD:
2339 case ARM::VLD3d16_UPD:
2340 case ARM::VLD3d32_UPD:
2344 case ARM::VLD4d8_UPD:
2345 case ARM::VLD4d16_UPD:
2346 case ARM::VLD4d32_UPD:
2347 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2348 return MCDisassembler::Fail;
2353 case ARM::VLD3q8_UPD:
2354 case ARM::VLD3q16_UPD:
2355 case ARM::VLD3q32_UPD:
2359 case ARM::VLD4q8_UPD:
2360 case ARM::VLD4q16_UPD:
2361 case ARM::VLD4q32_UPD:
2362 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2363 return MCDisassembler::Fail;
2368 // Third output register
2369 switch(Inst.getOpcode()) {
2373 case ARM::VLD3d8_UPD:
2374 case ARM::VLD3d16_UPD:
2375 case ARM::VLD3d32_UPD:
2379 case ARM::VLD4d8_UPD:
2380 case ARM::VLD4d16_UPD:
2381 case ARM::VLD4d32_UPD:
2382 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2383 return MCDisassembler::Fail;
2388 case ARM::VLD3q8_UPD:
2389 case ARM::VLD3q16_UPD:
2390 case ARM::VLD3q32_UPD:
2394 case ARM::VLD4q8_UPD:
2395 case ARM::VLD4q16_UPD:
2396 case ARM::VLD4q32_UPD:
2397 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2398 return MCDisassembler::Fail;
2404 // Fourth output register
2405 switch (Inst.getOpcode()) {
2409 case ARM::VLD4d8_UPD:
2410 case ARM::VLD4d16_UPD:
2411 case ARM::VLD4d32_UPD:
2412 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2413 return MCDisassembler::Fail;
2418 case ARM::VLD4q8_UPD:
2419 case ARM::VLD4q16_UPD:
2420 case ARM::VLD4q32_UPD:
2421 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2422 return MCDisassembler::Fail;
2428 // Writeback operand
2429 switch (Inst.getOpcode()) {
2430 case ARM::VLD1d8wb_fixed:
2431 case ARM::VLD1d16wb_fixed:
2432 case ARM::VLD1d32wb_fixed:
2433 case ARM::VLD1d64wb_fixed:
2434 case ARM::VLD1d8wb_register:
2435 case ARM::VLD1d16wb_register:
2436 case ARM::VLD1d32wb_register:
2437 case ARM::VLD1d64wb_register:
2438 case ARM::VLD1q8wb_fixed:
2439 case ARM::VLD1q16wb_fixed:
2440 case ARM::VLD1q32wb_fixed:
2441 case ARM::VLD1q64wb_fixed:
2442 case ARM::VLD1q8wb_register:
2443 case ARM::VLD1q16wb_register:
2444 case ARM::VLD1q32wb_register:
2445 case ARM::VLD1q64wb_register:
2446 case ARM::VLD1d8Twb_fixed:
2447 case ARM::VLD1d8Twb_register:
2448 case ARM::VLD1d16Twb_fixed:
2449 case ARM::VLD1d16Twb_register:
2450 case ARM::VLD1d32Twb_fixed:
2451 case ARM::VLD1d32Twb_register:
2452 case ARM::VLD1d64Twb_fixed:
2453 case ARM::VLD1d64Twb_register:
2454 case ARM::VLD1d8Qwb_fixed:
2455 case ARM::VLD1d8Qwb_register:
2456 case ARM::VLD1d16Qwb_fixed:
2457 case ARM::VLD1d16Qwb_register:
2458 case ARM::VLD1d32Qwb_fixed:
2459 case ARM::VLD1d32Qwb_register:
2460 case ARM::VLD1d64Qwb_fixed:
2461 case ARM::VLD1d64Qwb_register:
2462 case ARM::VLD2d8wb_fixed:
2463 case ARM::VLD2d16wb_fixed:
2464 case ARM::VLD2d32wb_fixed:
2465 case ARM::VLD2q8wb_fixed:
2466 case ARM::VLD2q16wb_fixed:
2467 case ARM::VLD2q32wb_fixed:
2468 case ARM::VLD2d8wb_register:
2469 case ARM::VLD2d16wb_register:
2470 case ARM::VLD2d32wb_register:
2471 case ARM::VLD2q8wb_register:
2472 case ARM::VLD2q16wb_register:
2473 case ARM::VLD2q32wb_register:
2474 case ARM::VLD2b8wb_fixed:
2475 case ARM::VLD2b16wb_fixed:
2476 case ARM::VLD2b32wb_fixed:
2477 case ARM::VLD2b8wb_register:
2478 case ARM::VLD2b16wb_register:
2479 case ARM::VLD2b32wb_register:
2480 Inst.addOperand(MCOperand::CreateImm(0));
2482 case ARM::VLD3d8_UPD:
2483 case ARM::VLD3d16_UPD:
2484 case ARM::VLD3d32_UPD:
2485 case ARM::VLD3q8_UPD:
2486 case ARM::VLD3q16_UPD:
2487 case ARM::VLD3q32_UPD:
2488 case ARM::VLD4d8_UPD:
2489 case ARM::VLD4d16_UPD:
2490 case ARM::VLD4d32_UPD:
2491 case ARM::VLD4q8_UPD:
2492 case ARM::VLD4q16_UPD:
2493 case ARM::VLD4q32_UPD:
2494 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2495 return MCDisassembler::Fail;
2501 // AddrMode6 Base (register+alignment)
2502 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2503 return MCDisassembler::Fail;
2505 // AddrMode6 Offset (register)
2506 switch (Inst.getOpcode()) {
2508 // The below have been updated to have explicit am6offset split
2509 // between fixed and register offset. For those instructions not
2510 // yet updated, we need to add an additional reg0 operand for the
2513 // The fixed offset encodes as Rm == 0xd, so we check for that.
2515 Inst.addOperand(MCOperand::CreateReg(0));
2518 // Fall through to handle the register offset variant.
2519 case ARM::VLD1d8wb_fixed:
2520 case ARM::VLD1d16wb_fixed:
2521 case ARM::VLD1d32wb_fixed:
2522 case ARM::VLD1d64wb_fixed:
2523 case ARM::VLD1d8Twb_fixed:
2524 case ARM::VLD1d16Twb_fixed:
2525 case ARM::VLD1d32Twb_fixed:
2526 case ARM::VLD1d64Twb_fixed:
2527 case ARM::VLD1d8Qwb_fixed:
2528 case ARM::VLD1d16Qwb_fixed:
2529 case ARM::VLD1d32Qwb_fixed:
2530 case ARM::VLD1d64Qwb_fixed:
2531 case ARM::VLD1d8wb_register:
2532 case ARM::VLD1d16wb_register:
2533 case ARM::VLD1d32wb_register:
2534 case ARM::VLD1d64wb_register:
2535 case ARM::VLD1q8wb_fixed:
2536 case ARM::VLD1q16wb_fixed:
2537 case ARM::VLD1q32wb_fixed:
2538 case ARM::VLD1q64wb_fixed:
2539 case ARM::VLD1q8wb_register:
2540 case ARM::VLD1q16wb_register:
2541 case ARM::VLD1q32wb_register:
2542 case ARM::VLD1q64wb_register:
2543 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2544 // variant encodes Rm == 0xf. Anything else is a register offset post-
2545 // increment and we need to add the register operand to the instruction.
2546 if (Rm != 0xD && Rm != 0xF &&
2547 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2548 return MCDisassembler::Fail;
2550 case ARM::VLD2d8wb_fixed:
2551 case ARM::VLD2d16wb_fixed:
2552 case ARM::VLD2d32wb_fixed:
2553 case ARM::VLD2b8wb_fixed:
2554 case ARM::VLD2b16wb_fixed:
2555 case ARM::VLD2b32wb_fixed:
2556 case ARM::VLD2q8wb_fixed:
2557 case ARM::VLD2q16wb_fixed:
2558 case ARM::VLD2q32wb_fixed:
2565 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2566 uint64_t Address, const void *Decoder) {
2567 unsigned type = fieldFromInstruction(Insn, 8, 4);
2568 unsigned align = fieldFromInstruction(Insn, 4, 2);
2569 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2570 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2571 if (type == 10 && align == 3) return MCDisassembler::Fail;
2573 unsigned load = fieldFromInstruction(Insn, 21, 1);
2574 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2575 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2578 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2579 uint64_t Address, const void *Decoder) {
2580 unsigned size = fieldFromInstruction(Insn, 6, 2);
2581 if (size == 3) return MCDisassembler::Fail;
2583 unsigned type = fieldFromInstruction(Insn, 8, 4);
2584 unsigned align = fieldFromInstruction(Insn, 4, 2);
2585 if (type == 8 && align == 3) return MCDisassembler::Fail;
2586 if (type == 9 && align == 3) return MCDisassembler::Fail;
2588 unsigned load = fieldFromInstruction(Insn, 21, 1);
2589 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2590 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2593 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2594 uint64_t Address, const void *Decoder) {
2595 unsigned size = fieldFromInstruction(Insn, 6, 2);
2596 if (size == 3) return MCDisassembler::Fail;
2598 unsigned align = fieldFromInstruction(Insn, 4, 2);
2599 if (align & 2) return MCDisassembler::Fail;
2601 unsigned load = fieldFromInstruction(Insn, 21, 1);
2602 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2603 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2606 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2607 uint64_t Address, const void *Decoder) {
2608 unsigned size = fieldFromInstruction(Insn, 6, 2);
2609 if (size == 3) return MCDisassembler::Fail;
2611 unsigned load = fieldFromInstruction(Insn, 21, 1);
2612 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2613 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2616 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2617 uint64_t Address, const void *Decoder) {
2618 DecodeStatus S = MCDisassembler::Success;
2620 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2621 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2622 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2623 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2624 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2625 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2627 // Writeback Operand
2628 switch (Inst.getOpcode()) {
2629 case ARM::VST1d8wb_fixed:
2630 case ARM::VST1d16wb_fixed:
2631 case ARM::VST1d32wb_fixed:
2632 case ARM::VST1d64wb_fixed:
2633 case ARM::VST1d8wb_register:
2634 case ARM::VST1d16wb_register:
2635 case ARM::VST1d32wb_register:
2636 case ARM::VST1d64wb_register:
2637 case ARM::VST1q8wb_fixed:
2638 case ARM::VST1q16wb_fixed:
2639 case ARM::VST1q32wb_fixed:
2640 case ARM::VST1q64wb_fixed:
2641 case ARM::VST1q8wb_register:
2642 case ARM::VST1q16wb_register:
2643 case ARM::VST1q32wb_register:
2644 case ARM::VST1q64wb_register:
2645 case ARM::VST1d8Twb_fixed:
2646 case ARM::VST1d16Twb_fixed:
2647 case ARM::VST1d32Twb_fixed:
2648 case ARM::VST1d64Twb_fixed:
2649 case ARM::VST1d8Twb_register:
2650 case ARM::VST1d16Twb_register:
2651 case ARM::VST1d32Twb_register:
2652 case ARM::VST1d64Twb_register:
2653 case ARM::VST1d8Qwb_fixed:
2654 case ARM::VST1d16Qwb_fixed:
2655 case ARM::VST1d32Qwb_fixed:
2656 case ARM::VST1d64Qwb_fixed:
2657 case ARM::VST1d8Qwb_register:
2658 case ARM::VST1d16Qwb_register:
2659 case ARM::VST1d32Qwb_register:
2660 case ARM::VST1d64Qwb_register:
2661 case ARM::VST2d8wb_fixed:
2662 case ARM::VST2d16wb_fixed:
2663 case ARM::VST2d32wb_fixed:
2664 case ARM::VST2d8wb_register:
2665 case ARM::VST2d16wb_register:
2666 case ARM::VST2d32wb_register:
2667 case ARM::VST2q8wb_fixed:
2668 case ARM::VST2q16wb_fixed:
2669 case ARM::VST2q32wb_fixed:
2670 case ARM::VST2q8wb_register:
2671 case ARM::VST2q16wb_register:
2672 case ARM::VST2q32wb_register:
2673 case ARM::VST2b8wb_fixed:
2674 case ARM::VST2b16wb_fixed:
2675 case ARM::VST2b32wb_fixed:
2676 case ARM::VST2b8wb_register:
2677 case ARM::VST2b16wb_register:
2678 case ARM::VST2b32wb_register:
2680 return MCDisassembler::Fail;
2681 Inst.addOperand(MCOperand::CreateImm(0));
2683 case ARM::VST3d8_UPD:
2684 case ARM::VST3d16_UPD:
2685 case ARM::VST3d32_UPD:
2686 case ARM::VST3q8_UPD:
2687 case ARM::VST3q16_UPD:
2688 case ARM::VST3q32_UPD:
2689 case ARM::VST4d8_UPD:
2690 case ARM::VST4d16_UPD:
2691 case ARM::VST4d32_UPD:
2692 case ARM::VST4q8_UPD:
2693 case ARM::VST4q16_UPD:
2694 case ARM::VST4q32_UPD:
2695 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2696 return MCDisassembler::Fail;
2702 // AddrMode6 Base (register+alignment)
2703 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2704 return MCDisassembler::Fail;
2706 // AddrMode6 Offset (register)
2707 switch (Inst.getOpcode()) {
2710 Inst.addOperand(MCOperand::CreateReg(0));
2711 else if (Rm != 0xF) {
2712 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2713 return MCDisassembler::Fail;
2716 case ARM::VST1d8wb_fixed:
2717 case ARM::VST1d16wb_fixed:
2718 case ARM::VST1d32wb_fixed:
2719 case ARM::VST1d64wb_fixed:
2720 case ARM::VST1q8wb_fixed:
2721 case ARM::VST1q16wb_fixed:
2722 case ARM::VST1q32wb_fixed:
2723 case ARM::VST1q64wb_fixed:
2724 case ARM::VST1d8Twb_fixed:
2725 case ARM::VST1d16Twb_fixed:
2726 case ARM::VST1d32Twb_fixed:
2727 case ARM::VST1d64Twb_fixed:
2728 case ARM::VST1d8Qwb_fixed:
2729 case ARM::VST1d16Qwb_fixed:
2730 case ARM::VST1d32Qwb_fixed:
2731 case ARM::VST1d64Qwb_fixed:
2732 case ARM::VST2d8wb_fixed:
2733 case ARM::VST2d16wb_fixed:
2734 case ARM::VST2d32wb_fixed:
2735 case ARM::VST2q8wb_fixed:
2736 case ARM::VST2q16wb_fixed:
2737 case ARM::VST2q32wb_fixed:
2738 case ARM::VST2b8wb_fixed:
2739 case ARM::VST2b16wb_fixed:
2740 case ARM::VST2b32wb_fixed:
2745 // First input register
2746 switch (Inst.getOpcode()) {
2751 case ARM::VST1q16wb_fixed:
2752 case ARM::VST1q16wb_register:
2753 case ARM::VST1q32wb_fixed:
2754 case ARM::VST1q32wb_register:
2755 case ARM::VST1q64wb_fixed:
2756 case ARM::VST1q64wb_register:
2757 case ARM::VST1q8wb_fixed:
2758 case ARM::VST1q8wb_register:
2762 case ARM::VST2d16wb_fixed:
2763 case ARM::VST2d16wb_register:
2764 case ARM::VST2d32wb_fixed:
2765 case ARM::VST2d32wb_register:
2766 case ARM::VST2d8wb_fixed:
2767 case ARM::VST2d8wb_register:
2768 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2769 return MCDisassembler::Fail;
2774 case ARM::VST2b16wb_fixed:
2775 case ARM::VST2b16wb_register:
2776 case ARM::VST2b32wb_fixed:
2777 case ARM::VST2b32wb_register:
2778 case ARM::VST2b8wb_fixed:
2779 case ARM::VST2b8wb_register:
2780 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2781 return MCDisassembler::Fail;
2784 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2785 return MCDisassembler::Fail;
2788 // Second input register
2789 switch (Inst.getOpcode()) {
2793 case ARM::VST3d8_UPD:
2794 case ARM::VST3d16_UPD:
2795 case ARM::VST3d32_UPD:
2799 case ARM::VST4d8_UPD:
2800 case ARM::VST4d16_UPD:
2801 case ARM::VST4d32_UPD:
2802 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2803 return MCDisassembler::Fail;
2808 case ARM::VST3q8_UPD:
2809 case ARM::VST3q16_UPD:
2810 case ARM::VST3q32_UPD:
2814 case ARM::VST4q8_UPD:
2815 case ARM::VST4q16_UPD:
2816 case ARM::VST4q32_UPD:
2817 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2818 return MCDisassembler::Fail;
2824 // Third input register
2825 switch (Inst.getOpcode()) {
2829 case ARM::VST3d8_UPD:
2830 case ARM::VST3d16_UPD:
2831 case ARM::VST3d32_UPD:
2835 case ARM::VST4d8_UPD:
2836 case ARM::VST4d16_UPD:
2837 case ARM::VST4d32_UPD:
2838 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2839 return MCDisassembler::Fail;
2844 case ARM::VST3q8_UPD:
2845 case ARM::VST3q16_UPD:
2846 case ARM::VST3q32_UPD:
2850 case ARM::VST4q8_UPD:
2851 case ARM::VST4q16_UPD:
2852 case ARM::VST4q32_UPD:
2853 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2854 return MCDisassembler::Fail;
2860 // Fourth input register
2861 switch (Inst.getOpcode()) {
2865 case ARM::VST4d8_UPD:
2866 case ARM::VST4d16_UPD:
2867 case ARM::VST4d32_UPD:
2868 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2869 return MCDisassembler::Fail;
2874 case ARM::VST4q8_UPD:
2875 case ARM::VST4q16_UPD:
2876 case ARM::VST4q32_UPD:
2877 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2878 return MCDisassembler::Fail;
2887 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2888 uint64_t Address, const void *Decoder) {
2889 DecodeStatus S = MCDisassembler::Success;
2891 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2892 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2893 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2894 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2895 unsigned align = fieldFromInstruction(Insn, 4, 1);
2896 unsigned size = fieldFromInstruction(Insn, 6, 2);
2898 if (size == 0 && align == 1)
2899 return MCDisassembler::Fail;
2900 align *= (1 << size);
2902 switch (Inst.getOpcode()) {
2903 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2904 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2905 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2906 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2907 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2908 return MCDisassembler::Fail;
2911 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2912 return MCDisassembler::Fail;
2916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2917 return MCDisassembler::Fail;
2920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2921 return MCDisassembler::Fail;
2922 Inst.addOperand(MCOperand::CreateImm(align));
2924 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2925 // variant encodes Rm == 0xf. Anything else is a register offset post-
2926 // increment and we need to add the register operand to the instruction.
2927 if (Rm != 0xD && Rm != 0xF &&
2928 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2929 return MCDisassembler::Fail;
2934 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2935 uint64_t Address, const void *Decoder) {
2936 DecodeStatus S = MCDisassembler::Success;
2938 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2939 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2940 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2941 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2942 unsigned align = fieldFromInstruction(Insn, 4, 1);
2943 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2946 switch (Inst.getOpcode()) {
2947 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2948 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2949 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2950 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2951 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2952 return MCDisassembler::Fail;
2954 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2955 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2956 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2957 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2958 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2959 return MCDisassembler::Fail;
2962 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2963 return MCDisassembler::Fail;
2968 Inst.addOperand(MCOperand::CreateImm(0));
2970 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2971 return MCDisassembler::Fail;
2972 Inst.addOperand(MCOperand::CreateImm(align));
2974 if (Rm != 0xD && Rm != 0xF) {
2975 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2976 return MCDisassembler::Fail;
2982 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2983 uint64_t Address, const void *Decoder) {
2984 DecodeStatus S = MCDisassembler::Success;
2986 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2987 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2988 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2989 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2990 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2992 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2993 return MCDisassembler::Fail;
2994 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2995 return MCDisassembler::Fail;
2996 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2997 return MCDisassembler::Fail;
2999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3000 return MCDisassembler::Fail;
3003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3004 return MCDisassembler::Fail;
3005 Inst.addOperand(MCOperand::CreateImm(0));
3008 Inst.addOperand(MCOperand::CreateReg(0));
3009 else if (Rm != 0xF) {
3010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3011 return MCDisassembler::Fail;
3017 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3018 uint64_t Address, const void *Decoder) {
3019 DecodeStatus S = MCDisassembler::Success;
3021 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3022 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3023 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3024 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3025 unsigned size = fieldFromInstruction(Insn, 6, 2);
3026 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3027 unsigned align = fieldFromInstruction(Insn, 4, 1);
3031 return MCDisassembler::Fail;
3042 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3043 return MCDisassembler::Fail;
3044 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3045 return MCDisassembler::Fail;
3046 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3047 return MCDisassembler::Fail;
3048 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3049 return MCDisassembler::Fail;
3051 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3052 return MCDisassembler::Fail;
3055 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3056 return MCDisassembler::Fail;
3057 Inst.addOperand(MCOperand::CreateImm(align));
3060 Inst.addOperand(MCOperand::CreateReg(0));
3061 else if (Rm != 0xF) {
3062 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3063 return MCDisassembler::Fail;
3070 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3071 uint64_t Address, const void *Decoder) {
3072 DecodeStatus S = MCDisassembler::Success;
3074 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3075 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3076 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3077 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3078 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3079 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3080 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3081 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3084 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3085 return MCDisassembler::Fail;
3087 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3088 return MCDisassembler::Fail;
3091 Inst.addOperand(MCOperand::CreateImm(imm));
3093 switch (Inst.getOpcode()) {
3094 case ARM::VORRiv4i16:
3095 case ARM::VORRiv2i32:
3096 case ARM::VBICiv4i16:
3097 case ARM::VBICiv2i32:
3098 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3099 return MCDisassembler::Fail;
3101 case ARM::VORRiv8i16:
3102 case ARM::VORRiv4i32:
3103 case ARM::VBICiv8i16:
3104 case ARM::VBICiv4i32:
3105 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3106 return MCDisassembler::Fail;
3115 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3116 uint64_t Address, const void *Decoder) {
3117 DecodeStatus S = MCDisassembler::Success;
3119 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3120 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3121 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3122 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3123 unsigned size = fieldFromInstruction(Insn, 18, 2);
3125 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3126 return MCDisassembler::Fail;
3127 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3128 return MCDisassembler::Fail;
3129 Inst.addOperand(MCOperand::CreateImm(8 << size));
3134 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3135 uint64_t Address, const void *Decoder) {
3136 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3137 return MCDisassembler::Success;
3140 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3141 uint64_t Address, const void *Decoder) {
3142 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3143 return MCDisassembler::Success;
3146 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3147 uint64_t Address, const void *Decoder) {
3148 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3149 return MCDisassembler::Success;
3152 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3153 uint64_t Address, const void *Decoder) {
3154 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3155 return MCDisassembler::Success;
3158 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3159 uint64_t Address, const void *Decoder) {
3160 DecodeStatus S = MCDisassembler::Success;
3162 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3163 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3164 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3165 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3166 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3167 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3168 unsigned op = fieldFromInstruction(Insn, 6, 1);
3170 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3171 return MCDisassembler::Fail;
3173 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3174 return MCDisassembler::Fail; // Writeback
3177 switch (Inst.getOpcode()) {
3180 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3181 return MCDisassembler::Fail;
3184 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3185 return MCDisassembler::Fail;
3188 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3189 return MCDisassembler::Fail;
3194 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3195 uint64_t Address, const void *Decoder) {
3196 DecodeStatus S = MCDisassembler::Success;
3198 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3199 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3201 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3202 return MCDisassembler::Fail;
3204 switch(Inst.getOpcode()) {
3206 return MCDisassembler::Fail;
3208 break; // tADR does not explicitly represent the PC as an operand.
3210 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3214 Inst.addOperand(MCOperand::CreateImm(imm));
3218 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3219 uint64_t Address, const void *Decoder) {
3220 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3221 true, 2, Inst, Decoder))
3222 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3223 return MCDisassembler::Success;
3226 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3227 uint64_t Address, const void *Decoder) {
3228 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3229 true, 4, Inst, Decoder))
3230 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3231 return MCDisassembler::Success;
3234 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3235 uint64_t Address, const void *Decoder) {
3236 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3237 true, 2, Inst, Decoder))
3238 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3239 return MCDisassembler::Success;
3242 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3243 uint64_t Address, const void *Decoder) {
3244 DecodeStatus S = MCDisassembler::Success;
3246 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3247 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3249 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3250 return MCDisassembler::Fail;
3251 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3252 return MCDisassembler::Fail;
3257 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3258 uint64_t Address, const void *Decoder) {
3259 DecodeStatus S = MCDisassembler::Success;
3261 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3262 unsigned imm = fieldFromInstruction(Val, 3, 5);
3264 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3265 return MCDisassembler::Fail;
3266 Inst.addOperand(MCOperand::CreateImm(imm));
3271 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3272 uint64_t Address, const void *Decoder) {
3273 unsigned imm = Val << 2;
3275 Inst.addOperand(MCOperand::CreateImm(imm));
3276 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3278 return MCDisassembler::Success;
3281 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3282 uint64_t Address, const void *Decoder) {
3283 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3284 Inst.addOperand(MCOperand::CreateImm(Val));
3286 return MCDisassembler::Success;
3289 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3290 uint64_t Address, const void *Decoder) {
3291 DecodeStatus S = MCDisassembler::Success;
3293 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3294 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3295 unsigned imm = fieldFromInstruction(Val, 0, 2);
3297 // Thumb stores cannot use PC as dest register.
3298 switch (Inst.getOpcode()) {
3303 return MCDisassembler::Fail;
3308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3309 return MCDisassembler::Fail;
3310 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3311 return MCDisassembler::Fail;
3312 Inst.addOperand(MCOperand::CreateImm(imm));
3317 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3318 uint64_t Address, const void *Decoder) {
3319 DecodeStatus S = MCDisassembler::Success;
3321 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3322 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3324 const FeatureBitset &featureBits =
3325 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3327 bool hasMP = featureBits[ARM::FeatureMP];
3328 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3331 switch (Inst.getOpcode()) {
3333 Inst.setOpcode(ARM::t2LDRBpci);
3336 Inst.setOpcode(ARM::t2LDRHpci);
3339 Inst.setOpcode(ARM::t2LDRSHpci);
3342 Inst.setOpcode(ARM::t2LDRSBpci);
3345 Inst.setOpcode(ARM::t2LDRpci);
3348 Inst.setOpcode(ARM::t2PLDpci);
3351 Inst.setOpcode(ARM::t2PLIpci);
3354 return MCDisassembler::Fail;
3357 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3361 switch (Inst.getOpcode()) {
3363 return MCDisassembler::Fail;
3365 Inst.setOpcode(ARM::t2PLDWs);
3368 Inst.setOpcode(ARM::t2PLIs);
3374 switch (Inst.getOpcode()) {
3379 return MCDisassembler::Fail;
3382 if (!hasV7Ops || !hasMP)
3383 return MCDisassembler::Fail;
3386 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3387 return MCDisassembler::Fail;
3390 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3391 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3392 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3393 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3394 return MCDisassembler::Fail;
3399 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3400 uint64_t Address, const void* Decoder) {
3401 DecodeStatus S = MCDisassembler::Success;
3403 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3404 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3405 unsigned U = fieldFromInstruction(Insn, 9, 1);
3406 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3409 unsigned add = fieldFromInstruction(Insn, 9, 1);
3411 const FeatureBitset &featureBits =
3412 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3414 bool hasMP = featureBits[ARM::FeatureMP];
3415 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3418 switch (Inst.getOpcode()) {
3420 Inst.setOpcode(ARM::t2LDRpci);
3423 Inst.setOpcode(ARM::t2LDRBpci);
3425 case ARM::t2LDRSBi8:
3426 Inst.setOpcode(ARM::t2LDRSBpci);
3429 Inst.setOpcode(ARM::t2LDRHpci);
3431 case ARM::t2LDRSHi8:
3432 Inst.setOpcode(ARM::t2LDRSHpci);
3435 Inst.setOpcode(ARM::t2PLDpci);
3438 Inst.setOpcode(ARM::t2PLIpci);
3441 return MCDisassembler::Fail;
3443 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3447 switch (Inst.getOpcode()) {
3448 case ARM::t2LDRSHi8:
3449 return MCDisassembler::Fail;
3452 Inst.setOpcode(ARM::t2PLDWi8);
3454 case ARM::t2LDRSBi8:
3455 Inst.setOpcode(ARM::t2PLIi8);
3462 switch (Inst.getOpcode()) {
3467 return MCDisassembler::Fail;
3470 if (!hasV7Ops || !hasMP)
3471 return MCDisassembler::Fail;
3474 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3475 return MCDisassembler::Fail;
3478 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3479 return MCDisassembler::Fail;
3483 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3484 uint64_t Address, const void* Decoder) {
3485 DecodeStatus S = MCDisassembler::Success;
3487 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3488 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3489 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3492 const FeatureBitset &featureBits =
3493 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3495 bool hasMP = featureBits[ARM::FeatureMP];
3496 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3499 switch (Inst.getOpcode()) {
3501 Inst.setOpcode(ARM::t2LDRpci);
3503 case ARM::t2LDRHi12:
3504 Inst.setOpcode(ARM::t2LDRHpci);
3506 case ARM::t2LDRSHi12:
3507 Inst.setOpcode(ARM::t2LDRSHpci);
3509 case ARM::t2LDRBi12:
3510 Inst.setOpcode(ARM::t2LDRBpci);
3512 case ARM::t2LDRSBi12:
3513 Inst.setOpcode(ARM::t2LDRSBpci);
3516 Inst.setOpcode(ARM::t2PLDpci);
3519 Inst.setOpcode(ARM::t2PLIpci);
3522 return MCDisassembler::Fail;
3524 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3528 switch (Inst.getOpcode()) {
3529 case ARM::t2LDRSHi12:
3530 return MCDisassembler::Fail;
3531 case ARM::t2LDRHi12:
3532 Inst.setOpcode(ARM::t2PLDWi12);
3534 case ARM::t2LDRSBi12:
3535 Inst.setOpcode(ARM::t2PLIi12);
3542 switch (Inst.getOpcode()) {
3547 return MCDisassembler::Fail;
3549 case ARM::t2PLDWi12:
3550 if (!hasV7Ops || !hasMP)
3551 return MCDisassembler::Fail;
3554 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3555 return MCDisassembler::Fail;
3558 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3559 return MCDisassembler::Fail;
3563 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3564 uint64_t Address, const void* Decoder) {
3565 DecodeStatus S = MCDisassembler::Success;
3567 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3568 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3569 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3573 switch (Inst.getOpcode()) {
3575 Inst.setOpcode(ARM::t2LDRpci);
3578 Inst.setOpcode(ARM::t2LDRBpci);
3581 Inst.setOpcode(ARM::t2LDRHpci);
3584 Inst.setOpcode(ARM::t2LDRSBpci);
3587 Inst.setOpcode(ARM::t2LDRSHpci);
3590 return MCDisassembler::Fail;
3592 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3595 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3596 return MCDisassembler::Fail;
3597 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3598 return MCDisassembler::Fail;
3602 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3603 uint64_t Address, const void* Decoder) {
3604 DecodeStatus S = MCDisassembler::Success;
3606 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3607 unsigned U = fieldFromInstruction(Insn, 23, 1);
3608 int imm = fieldFromInstruction(Insn, 0, 12);
3610 const FeatureBitset &featureBits =
3611 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3613 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3616 switch (Inst.getOpcode()) {
3617 case ARM::t2LDRBpci:
3618 case ARM::t2LDRHpci:
3619 Inst.setOpcode(ARM::t2PLDpci);
3621 case ARM::t2LDRSBpci:
3622 Inst.setOpcode(ARM::t2PLIpci);
3624 case ARM::t2LDRSHpci:
3625 return MCDisassembler::Fail;
3631 switch(Inst.getOpcode()) {
3636 return MCDisassembler::Fail;
3639 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3640 return MCDisassembler::Fail;
3644 // Special case for #-0.
3650 Inst.addOperand(MCOperand::CreateImm(imm));
3655 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3656 uint64_t Address, const void *Decoder) {
3658 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3660 int imm = Val & 0xFF;
3662 if (!(Val & 0x100)) imm *= -1;
3663 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3666 return MCDisassembler::Success;
3669 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3670 uint64_t Address, const void *Decoder) {
3671 DecodeStatus S = MCDisassembler::Success;
3673 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3674 unsigned imm = fieldFromInstruction(Val, 0, 9);
3676 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3677 return MCDisassembler::Fail;
3678 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3679 return MCDisassembler::Fail;
3684 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3685 uint64_t Address, const void *Decoder) {
3686 DecodeStatus S = MCDisassembler::Success;
3688 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3689 unsigned imm = fieldFromInstruction(Val, 0, 8);
3691 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3692 return MCDisassembler::Fail;
3694 Inst.addOperand(MCOperand::CreateImm(imm));
3699 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3700 uint64_t Address, const void *Decoder) {
3701 int imm = Val & 0xFF;
3704 else if (!(Val & 0x100))
3706 Inst.addOperand(MCOperand::CreateImm(imm));
3708 return MCDisassembler::Success;
3712 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3713 uint64_t Address, const void *Decoder) {
3714 DecodeStatus S = MCDisassembler::Success;
3716 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3717 unsigned imm = fieldFromInstruction(Val, 0, 9);
3719 // Thumb stores cannot use PC as dest register.
3720 switch (Inst.getOpcode()) {
3728 return MCDisassembler::Fail;
3734 // Some instructions always use an additive offset.
3735 switch (Inst.getOpcode()) {
3750 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3751 return MCDisassembler::Fail;
3752 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3753 return MCDisassembler::Fail;
3758 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3759 uint64_t Address, const void *Decoder) {
3760 DecodeStatus S = MCDisassembler::Success;
3762 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3763 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3764 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3765 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3767 unsigned load = fieldFromInstruction(Insn, 20, 1);
3770 switch (Inst.getOpcode()) {
3771 case ARM::t2LDR_PRE:
3772 case ARM::t2LDR_POST:
3773 Inst.setOpcode(ARM::t2LDRpci);
3775 case ARM::t2LDRB_PRE:
3776 case ARM::t2LDRB_POST:
3777 Inst.setOpcode(ARM::t2LDRBpci);
3779 case ARM::t2LDRH_PRE:
3780 case ARM::t2LDRH_POST:
3781 Inst.setOpcode(ARM::t2LDRHpci);
3783 case ARM::t2LDRSB_PRE:
3784 case ARM::t2LDRSB_POST:
3786 Inst.setOpcode(ARM::t2PLIpci);
3788 Inst.setOpcode(ARM::t2LDRSBpci);
3790 case ARM::t2LDRSH_PRE:
3791 case ARM::t2LDRSH_POST:
3792 Inst.setOpcode(ARM::t2LDRSHpci);
3795 return MCDisassembler::Fail;
3797 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3801 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3802 return MCDisassembler::Fail;
3805 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3806 return MCDisassembler::Fail;
3809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3810 return MCDisassembler::Fail;
3813 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3814 return MCDisassembler::Fail;
3819 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3820 uint64_t Address, const void *Decoder) {
3821 DecodeStatus S = MCDisassembler::Success;
3823 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3824 unsigned imm = fieldFromInstruction(Val, 0, 12);
3826 // Thumb stores cannot use PC as dest register.
3827 switch (Inst.getOpcode()) {
3829 case ARM::t2STRBi12:
3830 case ARM::t2STRHi12:
3832 return MCDisassembler::Fail;
3837 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3838 return MCDisassembler::Fail;
3839 Inst.addOperand(MCOperand::CreateImm(imm));
3845 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3846 uint64_t Address, const void *Decoder) {
3847 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3849 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3850 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3851 Inst.addOperand(MCOperand::CreateImm(imm));
3853 return MCDisassembler::Success;
3856 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3857 uint64_t Address, const void *Decoder) {
3858 DecodeStatus S = MCDisassembler::Success;
3860 if (Inst.getOpcode() == ARM::tADDrSP) {
3861 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3862 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3864 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3865 return MCDisassembler::Fail;
3866 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3867 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3868 return MCDisassembler::Fail;
3869 } else if (Inst.getOpcode() == ARM::tADDspr) {
3870 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3872 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3873 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3875 return MCDisassembler::Fail;
3881 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3882 uint64_t Address, const void *Decoder) {
3883 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3884 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3886 Inst.addOperand(MCOperand::CreateImm(imod));
3887 Inst.addOperand(MCOperand::CreateImm(flags));
3889 return MCDisassembler::Success;
3892 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3893 uint64_t Address, const void *Decoder) {
3894 DecodeStatus S = MCDisassembler::Success;
3895 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3896 unsigned add = fieldFromInstruction(Insn, 4, 1);
3898 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3899 return MCDisassembler::Fail;
3900 Inst.addOperand(MCOperand::CreateImm(add));
3905 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3906 uint64_t Address, const void *Decoder) {
3907 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3908 // Note only one trailing zero not two. Also the J1 and J2 values are from
3909 // the encoded instruction. So here change to I1 and I2 values via:
3910 // I1 = NOT(J1 EOR S);
3911 // I2 = NOT(J2 EOR S);
3912 // and build the imm32 with two trailing zeros as documented:
3913 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3914 unsigned S = (Val >> 23) & 1;
3915 unsigned J1 = (Val >> 22) & 1;
3916 unsigned J2 = (Val >> 21) & 1;
3917 unsigned I1 = !(J1 ^ S);
3918 unsigned I2 = !(J2 ^ S);
3919 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3920 int imm32 = SignExtend32<25>(tmp << 1);
3922 if (!tryAddingSymbolicOperand(Address,
3923 (Address & ~2u) + imm32 + 4,
3924 true, 4, Inst, Decoder))
3925 Inst.addOperand(MCOperand::CreateImm(imm32));
3926 return MCDisassembler::Success;
3929 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3930 uint64_t Address, const void *Decoder) {
3931 if (Val == 0xA || Val == 0xB)
3932 return MCDisassembler::Fail;
3934 const FeatureBitset &featureBits =
3935 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3937 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3938 return MCDisassembler::Fail;
3940 Inst.addOperand(MCOperand::CreateImm(Val));
3941 return MCDisassembler::Success;
3945 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3946 uint64_t Address, const void *Decoder) {
3947 DecodeStatus S = MCDisassembler::Success;
3949 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3950 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3952 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3954 return MCDisassembler::Fail;
3955 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3956 return MCDisassembler::Fail;
3961 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3962 uint64_t Address, const void *Decoder) {
3963 DecodeStatus S = MCDisassembler::Success;
3965 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3966 if (pred == 0xE || pred == 0xF) {
3967 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3970 return MCDisassembler::Fail;
3972 Inst.setOpcode(ARM::t2DSB);
3975 Inst.setOpcode(ARM::t2DMB);
3978 Inst.setOpcode(ARM::t2ISB);
3982 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3983 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3986 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3987 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3988 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3989 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3990 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3992 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3993 return MCDisassembler::Fail;
3994 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3995 return MCDisassembler::Fail;
4000 // Decode a shifted immediate operand. These basically consist
4001 // of an 8-bit value, and a 4-bit directive that specifies either
4002 // a splat operation or a rotation.
4003 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4004 uint64_t Address, const void *Decoder) {
4005 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4007 unsigned byte = fieldFromInstruction(Val, 8, 2);
4008 unsigned imm = fieldFromInstruction(Val, 0, 8);
4011 Inst.addOperand(MCOperand::CreateImm(imm));
4014 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
4017 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
4020 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
4025 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4026 unsigned rot = fieldFromInstruction(Val, 7, 5);
4027 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4028 Inst.addOperand(MCOperand::CreateImm(imm));
4031 return MCDisassembler::Success;
4035 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4036 uint64_t Address, const void *Decoder){
4037 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4038 true, 2, Inst, Decoder))
4039 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
4040 return MCDisassembler::Success;
4043 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4044 uint64_t Address, const void *Decoder){
4045 // Val is passed in as S:J1:J2:imm10:imm11
4046 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4047 // the encoded instruction. So here change to I1 and I2 values via:
4048 // I1 = NOT(J1 EOR S);
4049 // I2 = NOT(J2 EOR S);
4050 // and build the imm32 with one trailing zero as documented:
4051 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4052 unsigned S = (Val >> 23) & 1;
4053 unsigned J1 = (Val >> 22) & 1;
4054 unsigned J2 = (Val >> 21) & 1;
4055 unsigned I1 = !(J1 ^ S);
4056 unsigned I2 = !(J2 ^ S);
4057 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4058 int imm32 = SignExtend32<25>(tmp << 1);
4060 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4061 true, 4, Inst, Decoder))
4062 Inst.addOperand(MCOperand::CreateImm(imm32));
4063 return MCDisassembler::Success;
4066 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4067 uint64_t Address, const void *Decoder) {
4069 return MCDisassembler::Fail;
4071 Inst.addOperand(MCOperand::CreateImm(Val));
4072 return MCDisassembler::Success;
4075 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4076 uint64_t Address, const void *Decoder) {
4078 return MCDisassembler::Fail;
4080 Inst.addOperand(MCOperand::CreateImm(Val));
4081 return MCDisassembler::Success;
4084 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4085 uint64_t Address, const void *Decoder) {
4086 DecodeStatus S = MCDisassembler::Success;
4087 const FeatureBitset &FeatureBits =
4088 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4090 if (FeatureBits[ARM::FeatureMClass]) {
4091 unsigned ValLow = Val & 0xff;
4093 // Validate the SYSm value first.
4108 case 18: // basepri_max
4109 case 19: // faultmask
4110 if (!(FeatureBits[ARM::HasV7Ops]))
4111 // Values basepri, basepri_max and faultmask are only valid for v7m.
4112 return MCDisassembler::Fail;
4115 return MCDisassembler::Fail;
4118 if (Inst.getOpcode() == ARM::t2MSR_M) {
4119 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4120 if (!(FeatureBits[ARM::HasV7Ops])) {
4121 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4124 S = MCDisassembler::SoftFail;
4127 // The ARMv7-M architecture stores an additional 2-bit mask value in
4128 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4129 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4130 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4131 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4132 // only if the processor includes the DSP extension.
4133 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4134 (!(FeatureBits[ARM::FeatureDSPThumb2]) && (Mask & 1)))
4135 S = MCDisassembler::SoftFail;
4141 return MCDisassembler::Fail;
4143 Inst.addOperand(MCOperand::CreateImm(Val));
4147 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4148 uint64_t Address, const void *Decoder) {
4150 unsigned R = fieldFromInstruction(Val, 5, 1);
4151 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4153 // The table of encodings for these banked registers comes from B9.2.3 of the
4154 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4155 // neater. So by fiat, these values are UNPREDICTABLE:
4157 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4158 SysM == 0x1a || SysM == 0x1b)
4159 return MCDisassembler::SoftFail;
4161 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4162 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4163 return MCDisassembler::SoftFail;
4166 Inst.addOperand(MCOperand::CreateImm(Val));
4167 return MCDisassembler::Success;
4170 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4171 uint64_t Address, const void *Decoder) {
4172 DecodeStatus S = MCDisassembler::Success;
4174 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4175 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4176 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4179 S = MCDisassembler::SoftFail;
4181 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4182 return MCDisassembler::Fail;
4183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4184 return MCDisassembler::Fail;
4185 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4186 return MCDisassembler::Fail;
4191 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4192 uint64_t Address, const void *Decoder){
4193 DecodeStatus S = MCDisassembler::Success;
4195 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4196 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4197 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4198 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4200 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4201 return MCDisassembler::Fail;
4203 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4204 S = MCDisassembler::SoftFail;
4206 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4207 return MCDisassembler::Fail;
4208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4209 return MCDisassembler::Fail;
4210 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4211 return MCDisassembler::Fail;
4216 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4217 uint64_t Address, const void *Decoder) {
4218 DecodeStatus S = MCDisassembler::Success;
4220 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4221 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4222 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4223 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4224 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4225 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4227 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4229 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4230 return MCDisassembler::Fail;
4231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4232 return MCDisassembler::Fail;
4233 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4234 return MCDisassembler::Fail;
4235 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4236 return MCDisassembler::Fail;
4241 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4242 uint64_t Address, const void *Decoder) {
4243 DecodeStatus S = MCDisassembler::Success;
4245 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4246 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4247 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4248 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4249 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4250 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4251 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4253 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4254 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4257 return MCDisassembler::Fail;
4258 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4259 return MCDisassembler::Fail;
4260 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4261 return MCDisassembler::Fail;
4262 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4263 return MCDisassembler::Fail;
4269 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4270 uint64_t Address, const void *Decoder) {
4271 DecodeStatus S = MCDisassembler::Success;
4273 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4274 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4275 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4276 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4277 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4278 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4280 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4282 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4283 return MCDisassembler::Fail;
4284 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4285 return MCDisassembler::Fail;
4286 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4287 return MCDisassembler::Fail;
4288 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4289 return MCDisassembler::Fail;
4294 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4295 uint64_t Address, const void *Decoder) {
4296 DecodeStatus S = MCDisassembler::Success;
4298 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4299 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4300 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4301 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4302 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4303 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4305 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4308 return MCDisassembler::Fail;
4309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4310 return MCDisassembler::Fail;
4311 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4312 return MCDisassembler::Fail;
4313 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4314 return MCDisassembler::Fail;
4319 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4320 uint64_t Address, const void *Decoder) {
4321 DecodeStatus S = MCDisassembler::Success;
4323 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4324 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4325 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4326 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4327 unsigned size = fieldFromInstruction(Insn, 10, 2);
4333 return MCDisassembler::Fail;
4335 if (fieldFromInstruction(Insn, 4, 1))
4336 return MCDisassembler::Fail; // UNDEFINED
4337 index = fieldFromInstruction(Insn, 5, 3);
4340 if (fieldFromInstruction(Insn, 5, 1))
4341 return MCDisassembler::Fail; // UNDEFINED
4342 index = fieldFromInstruction(Insn, 6, 2);
4343 if (fieldFromInstruction(Insn, 4, 1))
4347 if (fieldFromInstruction(Insn, 6, 1))
4348 return MCDisassembler::Fail; // UNDEFINED
4349 index = fieldFromInstruction(Insn, 7, 1);
4351 switch (fieldFromInstruction(Insn, 4, 2)) {
4357 return MCDisassembler::Fail;
4362 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4363 return MCDisassembler::Fail;
4364 if (Rm != 0xF) { // Writeback
4365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4366 return MCDisassembler::Fail;
4368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4369 return MCDisassembler::Fail;
4370 Inst.addOperand(MCOperand::CreateImm(align));
4373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4374 return MCDisassembler::Fail;
4376 Inst.addOperand(MCOperand::CreateReg(0));
4379 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4380 return MCDisassembler::Fail;
4381 Inst.addOperand(MCOperand::CreateImm(index));
4386 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4387 uint64_t Address, const void *Decoder) {
4388 DecodeStatus S = MCDisassembler::Success;
4390 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4391 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4392 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4393 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4394 unsigned size = fieldFromInstruction(Insn, 10, 2);
4400 return MCDisassembler::Fail;
4402 if (fieldFromInstruction(Insn, 4, 1))
4403 return MCDisassembler::Fail; // UNDEFINED
4404 index = fieldFromInstruction(Insn, 5, 3);
4407 if (fieldFromInstruction(Insn, 5, 1))
4408 return MCDisassembler::Fail; // UNDEFINED
4409 index = fieldFromInstruction(Insn, 6, 2);
4410 if (fieldFromInstruction(Insn, 4, 1))
4414 if (fieldFromInstruction(Insn, 6, 1))
4415 return MCDisassembler::Fail; // UNDEFINED
4416 index = fieldFromInstruction(Insn, 7, 1);
4418 switch (fieldFromInstruction(Insn, 4, 2)) {
4424 return MCDisassembler::Fail;
4429 if (Rm != 0xF) { // Writeback
4430 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4431 return MCDisassembler::Fail;
4433 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4434 return MCDisassembler::Fail;
4435 Inst.addOperand(MCOperand::CreateImm(align));
4438 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4439 return MCDisassembler::Fail;
4441 Inst.addOperand(MCOperand::CreateReg(0));
4444 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4445 return MCDisassembler::Fail;
4446 Inst.addOperand(MCOperand::CreateImm(index));
4452 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4453 uint64_t Address, const void *Decoder) {
4454 DecodeStatus S = MCDisassembler::Success;
4456 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4457 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4458 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4459 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4460 unsigned size = fieldFromInstruction(Insn, 10, 2);
4467 return MCDisassembler::Fail;
4469 index = fieldFromInstruction(Insn, 5, 3);
4470 if (fieldFromInstruction(Insn, 4, 1))
4474 index = fieldFromInstruction(Insn, 6, 2);
4475 if (fieldFromInstruction(Insn, 4, 1))
4477 if (fieldFromInstruction(Insn, 5, 1))
4481 if (fieldFromInstruction(Insn, 5, 1))
4482 return MCDisassembler::Fail; // UNDEFINED
4483 index = fieldFromInstruction(Insn, 7, 1);
4484 if (fieldFromInstruction(Insn, 4, 1) != 0)
4486 if (fieldFromInstruction(Insn, 6, 1))
4491 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4492 return MCDisassembler::Fail;
4493 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4494 return MCDisassembler::Fail;
4495 if (Rm != 0xF) { // Writeback
4496 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4497 return MCDisassembler::Fail;
4499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4500 return MCDisassembler::Fail;
4501 Inst.addOperand(MCOperand::CreateImm(align));
4504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4505 return MCDisassembler::Fail;
4507 Inst.addOperand(MCOperand::CreateReg(0));
4510 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4511 return MCDisassembler::Fail;
4512 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4513 return MCDisassembler::Fail;
4514 Inst.addOperand(MCOperand::CreateImm(index));
4519 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4520 uint64_t Address, const void *Decoder) {
4521 DecodeStatus S = MCDisassembler::Success;
4523 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4524 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4525 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4526 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4527 unsigned size = fieldFromInstruction(Insn, 10, 2);
4534 return MCDisassembler::Fail;
4536 index = fieldFromInstruction(Insn, 5, 3);
4537 if (fieldFromInstruction(Insn, 4, 1))
4541 index = fieldFromInstruction(Insn, 6, 2);
4542 if (fieldFromInstruction(Insn, 4, 1))
4544 if (fieldFromInstruction(Insn, 5, 1))
4548 if (fieldFromInstruction(Insn, 5, 1))
4549 return MCDisassembler::Fail; // UNDEFINED
4550 index = fieldFromInstruction(Insn, 7, 1);
4551 if (fieldFromInstruction(Insn, 4, 1) != 0)
4553 if (fieldFromInstruction(Insn, 6, 1))
4558 if (Rm != 0xF) { // Writeback
4559 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4560 return MCDisassembler::Fail;
4562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4563 return MCDisassembler::Fail;
4564 Inst.addOperand(MCOperand::CreateImm(align));
4567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4568 return MCDisassembler::Fail;
4570 Inst.addOperand(MCOperand::CreateReg(0));
4573 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4574 return MCDisassembler::Fail;
4575 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4576 return MCDisassembler::Fail;
4577 Inst.addOperand(MCOperand::CreateImm(index));
4583 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4584 uint64_t Address, const void *Decoder) {
4585 DecodeStatus S = MCDisassembler::Success;
4587 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4588 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4589 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4590 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4591 unsigned size = fieldFromInstruction(Insn, 10, 2);
4598 return MCDisassembler::Fail;
4600 if (fieldFromInstruction(Insn, 4, 1))
4601 return MCDisassembler::Fail; // UNDEFINED
4602 index = fieldFromInstruction(Insn, 5, 3);
4605 if (fieldFromInstruction(Insn, 4, 1))
4606 return MCDisassembler::Fail; // UNDEFINED
4607 index = fieldFromInstruction(Insn, 6, 2);
4608 if (fieldFromInstruction(Insn, 5, 1))
4612 if (fieldFromInstruction(Insn, 4, 2))
4613 return MCDisassembler::Fail; // UNDEFINED
4614 index = fieldFromInstruction(Insn, 7, 1);
4615 if (fieldFromInstruction(Insn, 6, 1))
4620 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4621 return MCDisassembler::Fail;
4622 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4623 return MCDisassembler::Fail;
4624 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4625 return MCDisassembler::Fail;
4627 if (Rm != 0xF) { // Writeback
4628 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4629 return MCDisassembler::Fail;
4631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4632 return MCDisassembler::Fail;
4633 Inst.addOperand(MCOperand::CreateImm(align));
4636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4637 return MCDisassembler::Fail;
4639 Inst.addOperand(MCOperand::CreateReg(0));
4642 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4643 return MCDisassembler::Fail;
4644 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4645 return MCDisassembler::Fail;
4646 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4647 return MCDisassembler::Fail;
4648 Inst.addOperand(MCOperand::CreateImm(index));
4653 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4654 uint64_t Address, const void *Decoder) {
4655 DecodeStatus S = MCDisassembler::Success;
4657 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4658 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4659 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4660 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4661 unsigned size = fieldFromInstruction(Insn, 10, 2);
4668 return MCDisassembler::Fail;
4670 if (fieldFromInstruction(Insn, 4, 1))
4671 return MCDisassembler::Fail; // UNDEFINED
4672 index = fieldFromInstruction(Insn, 5, 3);
4675 if (fieldFromInstruction(Insn, 4, 1))
4676 return MCDisassembler::Fail; // UNDEFINED
4677 index = fieldFromInstruction(Insn, 6, 2);
4678 if (fieldFromInstruction(Insn, 5, 1))
4682 if (fieldFromInstruction(Insn, 4, 2))
4683 return MCDisassembler::Fail; // UNDEFINED
4684 index = fieldFromInstruction(Insn, 7, 1);
4685 if (fieldFromInstruction(Insn, 6, 1))
4690 if (Rm != 0xF) { // Writeback
4691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4692 return MCDisassembler::Fail;
4694 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4695 return MCDisassembler::Fail;
4696 Inst.addOperand(MCOperand::CreateImm(align));
4699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4700 return MCDisassembler::Fail;
4702 Inst.addOperand(MCOperand::CreateReg(0));
4705 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4706 return MCDisassembler::Fail;
4707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4708 return MCDisassembler::Fail;
4709 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4710 return MCDisassembler::Fail;
4711 Inst.addOperand(MCOperand::CreateImm(index));
4717 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4718 uint64_t Address, const void *Decoder) {
4719 DecodeStatus S = MCDisassembler::Success;
4721 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4722 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4723 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4724 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4725 unsigned size = fieldFromInstruction(Insn, 10, 2);
4732 return MCDisassembler::Fail;
4734 if (fieldFromInstruction(Insn, 4, 1))
4736 index = fieldFromInstruction(Insn, 5, 3);
4739 if (fieldFromInstruction(Insn, 4, 1))
4741 index = fieldFromInstruction(Insn, 6, 2);
4742 if (fieldFromInstruction(Insn, 5, 1))
4746 switch (fieldFromInstruction(Insn, 4, 2)) {
4750 return MCDisassembler::Fail;
4752 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4755 index = fieldFromInstruction(Insn, 7, 1);
4756 if (fieldFromInstruction(Insn, 6, 1))
4761 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4762 return MCDisassembler::Fail;
4763 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4764 return MCDisassembler::Fail;
4765 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4766 return MCDisassembler::Fail;
4767 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4768 return MCDisassembler::Fail;
4770 if (Rm != 0xF) { // Writeback
4771 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4772 return MCDisassembler::Fail;
4774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4775 return MCDisassembler::Fail;
4776 Inst.addOperand(MCOperand::CreateImm(align));
4779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4780 return MCDisassembler::Fail;
4782 Inst.addOperand(MCOperand::CreateReg(0));
4785 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4786 return MCDisassembler::Fail;
4787 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4788 return MCDisassembler::Fail;
4789 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4790 return MCDisassembler::Fail;
4791 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4792 return MCDisassembler::Fail;
4793 Inst.addOperand(MCOperand::CreateImm(index));
4798 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4799 uint64_t Address, const void *Decoder) {
4800 DecodeStatus S = MCDisassembler::Success;
4802 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4803 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4804 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4805 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4806 unsigned size = fieldFromInstruction(Insn, 10, 2);
4813 return MCDisassembler::Fail;
4815 if (fieldFromInstruction(Insn, 4, 1))
4817 index = fieldFromInstruction(Insn, 5, 3);
4820 if (fieldFromInstruction(Insn, 4, 1))
4822 index = fieldFromInstruction(Insn, 6, 2);
4823 if (fieldFromInstruction(Insn, 5, 1))
4827 switch (fieldFromInstruction(Insn, 4, 2)) {
4831 return MCDisassembler::Fail;
4833 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4836 index = fieldFromInstruction(Insn, 7, 1);
4837 if (fieldFromInstruction(Insn, 6, 1))
4842 if (Rm != 0xF) { // Writeback
4843 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4844 return MCDisassembler::Fail;
4846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4847 return MCDisassembler::Fail;
4848 Inst.addOperand(MCOperand::CreateImm(align));
4851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4852 return MCDisassembler::Fail;
4854 Inst.addOperand(MCOperand::CreateReg(0));
4857 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4858 return MCDisassembler::Fail;
4859 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4860 return MCDisassembler::Fail;
4861 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4862 return MCDisassembler::Fail;
4863 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4864 return MCDisassembler::Fail;
4865 Inst.addOperand(MCOperand::CreateImm(index));
4870 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4871 uint64_t Address, const void *Decoder) {
4872 DecodeStatus S = MCDisassembler::Success;
4873 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4874 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4875 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4876 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4877 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4879 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4880 S = MCDisassembler::SoftFail;
4882 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4883 return MCDisassembler::Fail;
4884 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4885 return MCDisassembler::Fail;
4886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4887 return MCDisassembler::Fail;
4888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4889 return MCDisassembler::Fail;
4890 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4891 return MCDisassembler::Fail;
4896 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4897 uint64_t Address, const void *Decoder) {
4898 DecodeStatus S = MCDisassembler::Success;
4899 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4900 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4901 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4902 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4903 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4905 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4906 S = MCDisassembler::SoftFail;
4908 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4909 return MCDisassembler::Fail;
4910 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4911 return MCDisassembler::Fail;
4912 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4913 return MCDisassembler::Fail;
4914 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4915 return MCDisassembler::Fail;
4916 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4917 return MCDisassembler::Fail;
4922 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4923 uint64_t Address, const void *Decoder) {
4924 DecodeStatus S = MCDisassembler::Success;
4925 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4926 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4930 S = MCDisassembler::SoftFail;
4934 return MCDisassembler::Fail;
4936 Inst.addOperand(MCOperand::CreateImm(pred));
4937 Inst.addOperand(MCOperand::CreateImm(mask));
4942 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4943 uint64_t Address, const void *Decoder) {
4944 DecodeStatus S = MCDisassembler::Success;
4946 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4947 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4948 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4949 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4950 unsigned W = fieldFromInstruction(Insn, 21, 1);
4951 unsigned U = fieldFromInstruction(Insn, 23, 1);
4952 unsigned P = fieldFromInstruction(Insn, 24, 1);
4953 bool writeback = (W == 1) | (P == 0);
4955 addr |= (U << 8) | (Rn << 9);
4957 if (writeback && (Rn == Rt || Rn == Rt2))
4958 Check(S, MCDisassembler::SoftFail);
4960 Check(S, MCDisassembler::SoftFail);
4963 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4964 return MCDisassembler::Fail;
4966 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4967 return MCDisassembler::Fail;
4968 // Writeback operand
4969 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4970 return MCDisassembler::Fail;
4972 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4973 return MCDisassembler::Fail;
4979 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4980 uint64_t Address, const void *Decoder) {
4981 DecodeStatus S = MCDisassembler::Success;
4983 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4984 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4985 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4986 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4987 unsigned W = fieldFromInstruction(Insn, 21, 1);
4988 unsigned U = fieldFromInstruction(Insn, 23, 1);
4989 unsigned P = fieldFromInstruction(Insn, 24, 1);
4990 bool writeback = (W == 1) | (P == 0);
4992 addr |= (U << 8) | (Rn << 9);
4994 if (writeback && (Rn == Rt || Rn == Rt2))
4995 Check(S, MCDisassembler::SoftFail);
4997 // Writeback operand
4998 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4999 return MCDisassembler::Fail;
5001 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5002 return MCDisassembler::Fail;
5004 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5005 return MCDisassembler::Fail;
5007 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5008 return MCDisassembler::Fail;
5013 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5014 uint64_t Address, const void *Decoder) {
5015 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5016 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5017 if (sign1 != sign2) return MCDisassembler::Fail;
5019 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5020 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5021 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5023 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
5025 return MCDisassembler::Success;
5028 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5030 const void *Decoder) {
5031 DecodeStatus S = MCDisassembler::Success;
5033 // Shift of "asr #32" is not allowed in Thumb2 mode.
5034 if (Val == 0x20) S = MCDisassembler::Fail;
5035 Inst.addOperand(MCOperand::CreateImm(Val));
5039 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5040 uint64_t Address, const void *Decoder) {
5041 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5042 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5043 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5044 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5047 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5049 DecodeStatus S = MCDisassembler::Success;
5051 if (Rt == Rn || Rn == Rt2)
5052 S = MCDisassembler::SoftFail;
5054 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5055 return MCDisassembler::Fail;
5056 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5057 return MCDisassembler::Fail;
5058 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5059 return MCDisassembler::Fail;
5060 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5061 return MCDisassembler::Fail;
5066 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5067 uint64_t Address, const void *Decoder) {
5068 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5069 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5070 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5071 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5072 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5073 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5074 unsigned op = fieldFromInstruction(Insn, 5, 1);
5076 DecodeStatus S = MCDisassembler::Success;
5078 // VMOVv2f32 is ambiguous with these decodings.
5079 if (!(imm & 0x38) && cmode == 0xF) {
5080 if (op == 1) return MCDisassembler::Fail;
5081 Inst.setOpcode(ARM::VMOVv2f32);
5082 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5085 if (!(imm & 0x20)) return MCDisassembler::Fail;
5087 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5088 return MCDisassembler::Fail;
5089 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5090 return MCDisassembler::Fail;
5091 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5096 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5097 uint64_t Address, const void *Decoder) {
5098 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5099 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5100 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5101 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5102 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5103 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5104 unsigned op = fieldFromInstruction(Insn, 5, 1);
5106 DecodeStatus S = MCDisassembler::Success;
5108 // VMOVv4f32 is ambiguous with these decodings.
5109 if (!(imm & 0x38) && cmode == 0xF) {
5110 if (op == 1) return MCDisassembler::Fail;
5111 Inst.setOpcode(ARM::VMOVv4f32);
5112 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5115 if (!(imm & 0x20)) return MCDisassembler::Fail;
5117 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5118 return MCDisassembler::Fail;
5119 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5120 return MCDisassembler::Fail;
5121 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5126 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5127 uint64_t Address, const void *Decoder) {
5128 DecodeStatus S = MCDisassembler::Success;
5130 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5131 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5132 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5133 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5134 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5136 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5137 S = MCDisassembler::SoftFail;
5139 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5140 return MCDisassembler::Fail;
5141 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5142 return MCDisassembler::Fail;
5143 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5144 return MCDisassembler::Fail;
5145 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5146 return MCDisassembler::Fail;
5147 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5148 return MCDisassembler::Fail;
5153 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
5154 uint64_t Address, const void *Decoder) {
5156 DecodeStatus S = MCDisassembler::Success;
5158 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5159 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5160 unsigned cop = fieldFromInstruction(Val, 8, 4);
5161 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5162 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5164 if ((cop & ~0x1) == 0xa)
5165 return MCDisassembler::Fail;
5168 S = MCDisassembler::SoftFail;
5170 Inst.addOperand(MCOperand::CreateImm(cop));
5171 Inst.addOperand(MCOperand::CreateImm(opc1));
5172 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5173 return MCDisassembler::Fail;
5174 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5175 return MCDisassembler::Fail;
5176 Inst.addOperand(MCOperand::CreateImm(CRm));