1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "ARMDisassembler.h"
14 #include "ARMRegisterInfo.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/EDInstInfo.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/MemoryObject.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/raw_ostream.h"
27 // Pull DecodeStatus and its enum values into the global namespace.
28 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
29 #define Success llvm::MCDisassembler::Success
30 #define Unpredictable llvm::MCDisassembler::SoftFail
31 #define Fail llvm::MCDisassembler::Fail
33 // Helper macro to perform setwise reduction of the current running status
34 // and another status, and return if the new status is Fail.
35 #define CHECK(S,X) do { \
36 S = (DecodeStatus) ((int)S & (X)); \
37 if (S == Fail) return Fail; \
40 // Forward declare these because the autogenerated code will reference them.
41 // Definitions are further down.
42 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43 uint64_t Address, const void *Decoder);
44 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
45 unsigned RegNo, uint64_t Address,
47 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
48 uint64_t Address, const void *Decoder);
49 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
50 uint64_t Address, const void *Decoder);
51 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52 uint64_t Address, const void *Decoder);
53 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
54 uint64_t Address, const void *Decoder);
55 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
56 uint64_t Address, const void *Decoder);
57 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
58 uint64_t Address, const void *Decoder);
59 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
63 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
64 uint64_t Address, const void *Decoder);
66 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
67 uint64_t Address, const void *Decoder);
68 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
69 uint64_t Address, const void *Decoder);
70 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
71 uint64_t Address, const void *Decoder);
72 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
73 uint64_t Address, const void *Decoder);
74 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
75 uint64_t Address, const void *Decoder);
76 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
77 uint64_t Address, const void *Decoder);
79 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
80 uint64_t Address, const void *Decoder);
81 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
82 uint64_t Address, const void *Decoder);
83 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
87 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
88 uint64_t Address, const void *Decoder);
89 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
90 uint64_t Address, const void *Decoder);
91 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
92 uint64_t Address, const void *Decoder);
93 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
94 uint64_t Address, const void *Decoder);
96 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
100 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
101 uint64_t Address, const void *Decoder);
102 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
103 uint64_t Address, const void *Decoder);
104 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
105 uint64_t Address, const void *Decoder);
106 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
107 uint64_t Address, const void *Decoder);
108 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
109 uint64_t Address, const void *Decoder);
110 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
111 uint64_t Address, const void *Decoder);
112 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
113 uint64_t Address, const void *Decoder);
114 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
115 uint64_t Address, const void *Decoder);
116 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
117 uint64_t Address, const void *Decoder);
118 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
119 uint64_t Address, const void *Decoder);
120 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
121 uint64_t Address, const void *Decoder);
122 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
123 uint64_t Address, const void *Decoder);
124 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
125 uint64_t Address, const void *Decoder);
126 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
127 uint64_t Address, const void *Decoder);
128 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
129 uint64_t Address, const void *Decoder);
130 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
131 uint64_t Address, const void *Decoder);
132 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
133 uint64_t Address, const void *Decoder);
134 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
135 uint64_t Address, const void *Decoder);
136 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
137 uint64_t Address, const void *Decoder);
138 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
139 uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
141 uint64_t Address, const void *Decoder);
142 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
143 uint64_t Address, const void *Decoder);
144 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
145 uint64_t Address, const void *Decoder);
146 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
147 uint64_t Address, const void *Decoder);
148 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
149 uint64_t Address, const void *Decoder);
150 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
153 uint64_t Address, const void *Decoder);
154 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
157 uint64_t Address, const void *Decoder);
158 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
185 uint64_t Address, const void *Decoder);
187 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
188 uint64_t Address, const void *Decoder);
189 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
190 uint64_t Address, const void *Decoder);
191 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
192 uint64_t Address, const void *Decoder);
193 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
194 uint64_t Address, const void *Decoder);
195 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
196 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val,
236 uint64_t Address, const void *Decoder);
238 #include "ARMGenDisassemblerTables.inc"
239 #include "ARMGenInstrInfo.inc"
240 #include "ARMGenEDInfo.inc"
242 using namespace llvm;
244 static MCDisassembler *createARMDisassembler(const Target &T) {
245 return new ARMDisassembler;
248 static MCDisassembler *createThumbDisassembler(const Target &T) {
249 return new ThumbDisassembler;
252 EDInstInfo *ARMDisassembler::getEDInfo() const {
256 EDInstInfo *ThumbDisassembler::getEDInfo() const {
260 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
261 const MemoryObject &Region,
263 raw_ostream &os) const {
266 // We want to read exactly 4 bytes of data.
267 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
272 // Encoded as a small-endian 32-bit word in the stream.
273 uint32_t insn = (bytes[3] << 24) |
278 // Calling the auto-generated decoder function.
279 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
280 if (result != Fail) {
285 // Instructions that are shared between ARM and Thumb modes.
286 // FIXME: This shouldn't really exist. It's an artifact of the
287 // fact that we fail to encode a few instructions properly for Thumb.
289 result = decodeCommonInstruction32(MI, insn, Address, this);
290 if (result != Fail) {
295 // VFP and NEON instructions, similarly, are shared between ARM
298 result = decodeVFPInstruction32(MI, insn, Address, this);
299 if (result != Fail) {
305 result = decodeNEONDataInstruction32(MI, insn, Address, this);
306 if (result != Fail) {
308 // Add a fake predicate operand, because we share these instruction
309 // definitions with Thumb2 where these instructions are predicable.
310 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
315 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
316 if (result != Fail) {
318 // Add a fake predicate operand, because we share these instruction
319 // definitions with Thumb2 where these instructions are predicable.
320 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
325 result = decodeNEONDupInstruction32(MI, insn, Address, this);
326 if (result != Fail) {
328 // Add a fake predicate operand, because we share these instruction
329 // definitions with Thumb2 where these instructions are predicable.
330 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
341 extern MCInstrDesc ARMInsts[];
344 // Thumb1 instructions don't have explicit S bits. Rather, they
345 // implicitly set CPSR. Since it's not represented in the encoding, the
346 // auto-generated decoder won't inject the CPSR operand. We need to fix
347 // that as a post-pass.
348 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
349 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
350 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
351 MCInst::iterator I = MI.begin();
352 for (unsigned i = 0; i < NumOps; ++i, ++I) {
353 if (I == MI.end()) break;
354 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
355 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
356 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
361 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
364 // Most Thumb instructions don't have explicit predicates in the
365 // encoding, but rather get their predicates from IT context. We need
366 // to fix up the predicate operands using this context information as a
368 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
369 // A few instructions actually have predicates encoded in them. Don't
370 // try to overwrite it if we're seeing one of those.
371 switch (MI.getOpcode()) {
379 // If we're in an IT block, base the predicate on that. Otherwise,
380 // assume a predicate of AL.
382 if (!ITBlock.empty()) {
390 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
391 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
392 MCInst::iterator I = MI.begin();
393 for (unsigned i = 0; i < NumOps; ++i, ++I) {
394 if (I == MI.end()) break;
395 if (OpInfo[i].isPredicate()) {
396 I = MI.insert(I, MCOperand::CreateImm(CC));
399 MI.insert(I, MCOperand::CreateReg(0));
401 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
406 I = MI.insert(I, MCOperand::CreateImm(CC));
409 MI.insert(I, MCOperand::CreateReg(0));
411 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
414 // Thumb VFP instructions are a special case. Because we share their
415 // encodings between ARM and Thumb modes, and they are predicable in ARM
416 // mode, the auto-generated decoder will give them an (incorrect)
417 // predicate operand. We need to rewrite these operands based on the IT
418 // context as a post-pass.
419 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
421 if (!ITBlock.empty()) {
427 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
428 MCInst::iterator I = MI.begin();
429 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
430 for (unsigned i = 0; i < NumOps; ++i, ++I) {
431 if (OpInfo[i].isPredicate() ) {
437 I->setReg(ARM::CPSR);
443 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
444 const MemoryObject &Region,
446 raw_ostream &os) const {
449 // We want to read exactly 2 bytes of data.
450 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
455 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
456 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
457 if (result != Fail) {
459 AddThumbPredicate(MI);
464 result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
467 bool InITBlock = !ITBlock.empty();
468 AddThumbPredicate(MI);
469 AddThumb1SBit(MI, InITBlock);
474 result = decodeThumb2Instruction16(MI, insn16, Address, this);
475 if (result != Fail) {
477 AddThumbPredicate(MI);
479 // If we find an IT instruction, we need to parse its condition
480 // code and mask operands so that we can apply them correctly
481 // to the subsequent instructions.
482 if (MI.getOpcode() == ARM::t2IT) {
483 unsigned firstcond = MI.getOperand(0).getImm();
484 uint32_t mask = MI.getOperand(1).getImm();
485 unsigned zeros = CountTrailingZeros_32(mask);
488 for (unsigned i = 0; i < 4 - (zeros+1); ++i) {
489 if (firstcond ^ (mask & 1))
490 ITBlock.push_back(firstcond ^ 1);
492 ITBlock.push_back(firstcond);
495 ITBlock.push_back(firstcond);
501 // We want to read exactly 4 bytes of data.
502 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
507 uint32_t insn32 = (bytes[3] << 8) |
512 result = decodeThumbInstruction32(MI, insn32, Address, this);
513 if (result != Fail) {
515 bool InITBlock = ITBlock.size();
516 AddThumbPredicate(MI);
517 AddThumb1SBit(MI, InITBlock);
522 result = decodeThumb2Instruction32(MI, insn32, Address, this);
523 if (result != Fail) {
525 AddThumbPredicate(MI);
530 result = decodeCommonInstruction32(MI, insn32, Address, this);
531 if (result != Fail) {
533 AddThumbPredicate(MI);
538 result = decodeVFPInstruction32(MI, insn32, Address, this);
539 if (result != Fail) {
541 UpdateThumbVFPPredicate(MI);
546 result = decodeNEONDupInstruction32(MI, insn32, Address, this);
547 if (result != Fail) {
549 AddThumbPredicate(MI);
553 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
555 uint32_t NEONLdStInsn = insn32;
556 NEONLdStInsn &= 0xF0FFFFFF;
557 NEONLdStInsn |= 0x04000000;
558 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
559 if (result != Fail) {
561 AddThumbPredicate(MI);
566 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
568 uint32_t NEONDataInsn = insn32;
569 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
570 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
571 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
572 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
573 if (result != Fail) {
575 AddThumbPredicate(MI);
585 extern "C" void LLVMInitializeARMDisassembler() {
586 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
587 createARMDisassembler);
588 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
589 createThumbDisassembler);
592 static const unsigned GPRDecoderTable[] = {
593 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
594 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
595 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
596 ARM::R12, ARM::SP, ARM::LR, ARM::PC
599 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
600 uint64_t Address, const void *Decoder) {
604 unsigned Register = GPRDecoderTable[RegNo];
605 Inst.addOperand(MCOperand::CreateReg(Register));
610 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
611 uint64_t Address, const void *Decoder) {
612 if (RegNo == 15) return Fail;
613 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
616 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
617 uint64_t Address, const void *Decoder) {
620 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
623 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
624 uint64_t Address, const void *Decoder) {
625 unsigned Register = 0;
649 Inst.addOperand(MCOperand::CreateReg(Register));
653 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
654 uint64_t Address, const void *Decoder) {
655 if (RegNo == 13 || RegNo == 15) return Fail;
656 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
659 static const unsigned SPRDecoderTable[] = {
660 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
661 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
662 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
663 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
664 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
665 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
666 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
667 ARM::S28, ARM::S29, ARM::S30, ARM::S31
670 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
671 uint64_t Address, const void *Decoder) {
675 unsigned Register = SPRDecoderTable[RegNo];
676 Inst.addOperand(MCOperand::CreateReg(Register));
680 static const unsigned DPRDecoderTable[] = {
681 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
682 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
683 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
684 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
685 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
686 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
687 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
688 ARM::D28, ARM::D29, ARM::D30, ARM::D31
691 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
692 uint64_t Address, const void *Decoder) {
696 unsigned Register = DPRDecoderTable[RegNo];
697 Inst.addOperand(MCOperand::CreateReg(Register));
701 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
702 uint64_t Address, const void *Decoder) {
705 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
709 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
710 uint64_t Address, const void *Decoder) {
713 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
716 static const unsigned QPRDecoderTable[] = {
717 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
718 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
719 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
720 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
724 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
725 uint64_t Address, const void *Decoder) {
730 unsigned Register = QPRDecoderTable[RegNo];
731 Inst.addOperand(MCOperand::CreateReg(Register));
735 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
736 uint64_t Address, const void *Decoder) {
737 if (Val == 0xF) return Fail;
738 // AL predicate is not allowed on Thumb1 branches.
739 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
741 Inst.addOperand(MCOperand::CreateImm(Val));
742 if (Val == ARMCC::AL) {
743 Inst.addOperand(MCOperand::CreateReg(0));
745 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
749 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
750 uint64_t Address, const void *Decoder) {
752 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
754 Inst.addOperand(MCOperand::CreateReg(0));
758 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
759 uint64_t Address, const void *Decoder) {
760 uint32_t imm = Val & 0xFF;
761 uint32_t rot = (Val & 0xF00) >> 7;
762 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
763 Inst.addOperand(MCOperand::CreateImm(rot_imm));
767 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
768 uint64_t Address, const void *Decoder) {
769 DecodeStatus S = Success;
771 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
772 unsigned type = fieldFromInstruction32(Val, 5, 2);
773 unsigned imm = fieldFromInstruction32(Val, 7, 5);
775 // Register-immediate
776 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
778 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
794 if (Shift == ARM_AM::ror && imm == 0)
797 unsigned Op = Shift | (imm << 3);
798 Inst.addOperand(MCOperand::CreateImm(Op));
803 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
804 uint64_t Address, const void *Decoder) {
805 DecodeStatus S = Success;
807 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
808 unsigned type = fieldFromInstruction32(Val, 5, 2);
809 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
812 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
813 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));
815 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
831 Inst.addOperand(MCOperand::CreateImm(Shift));
836 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
837 uint64_t Address, const void *Decoder) {
838 DecodeStatus S = Success;
840 // Empty register lists are not allowed.
841 if (CountPopulation_32(Val) == 0) return Fail;
842 for (unsigned i = 0; i < 16; ++i) {
843 if (Val & (1 << i)) {
844 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));
851 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
852 uint64_t Address, const void *Decoder) {
853 DecodeStatus S = Success;
855 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
856 unsigned regs = Val & 0xFF;
858 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));
859 for (unsigned i = 0; i < (regs - 1); ++i) {
860 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));
866 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
867 uint64_t Address, const void *Decoder) {
868 DecodeStatus S = Success;
870 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
871 unsigned regs = (Val & 0xFF) / 2;
873 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));
874 for (unsigned i = 0; i < (regs - 1); ++i) {
875 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));
881 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
882 uint64_t Address, const void *Decoder) {
883 // This operand encodes a mask of contiguous zeros between a specified MSB
884 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
885 // the mask of all bits LSB-and-lower, and then xor them to create
886 // the mask of that's all ones on [msb, lsb]. Finally we not it to
887 // create the final mask.
888 unsigned msb = fieldFromInstruction32(Val, 5, 5);
889 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
890 uint32_t msb_mask = (1 << (msb+1)) - 1;
891 uint32_t lsb_mask = (1 << lsb) - 1;
892 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
896 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
897 uint64_t Address, const void *Decoder) {
898 DecodeStatus S = Success;
900 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
901 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
902 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
903 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
904 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
905 unsigned U = fieldFromInstruction32(Insn, 23, 1);
907 switch (Inst.getOpcode()) {
908 case ARM::LDC_OFFSET:
911 case ARM::LDC_OPTION:
912 case ARM::LDCL_OFFSET:
915 case ARM::LDCL_OPTION:
916 case ARM::STC_OFFSET:
919 case ARM::STC_OPTION:
920 case ARM::STCL_OFFSET:
923 case ARM::STCL_OPTION:
924 if (coproc == 0xA || coproc == 0xB)
931 Inst.addOperand(MCOperand::CreateImm(coproc));
932 Inst.addOperand(MCOperand::CreateImm(CRd));
933 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
934 switch (Inst.getOpcode()) {
935 case ARM::LDC_OPTION:
936 case ARM::LDCL_OPTION:
937 case ARM::LDC2_OPTION:
938 case ARM::LDC2L_OPTION:
939 case ARM::STC_OPTION:
940 case ARM::STCL_OPTION:
941 case ARM::STC2_OPTION:
942 case ARM::STC2L_OPTION:
945 case ARM::LDC2L_POST:
946 case ARM::STC2L_POST:
949 Inst.addOperand(MCOperand::CreateReg(0));
953 unsigned P = fieldFromInstruction32(Insn, 24, 1);
954 unsigned W = fieldFromInstruction32(Insn, 21, 1);
956 bool writeback = (P == 0) || (W == 1);
957 unsigned idx_mode = 0;
959 idx_mode = ARMII::IndexModePre;
960 else if (!P && writeback)
961 idx_mode = ARMII::IndexModePost;
963 switch (Inst.getOpcode()) {
966 case ARM::LDC2L_POST:
967 case ARM::STC2L_POST:
969 case ARM::LDC_OPTION:
970 case ARM::LDCL_OPTION:
971 case ARM::LDC2_OPTION:
972 case ARM::LDC2L_OPTION:
973 case ARM::STC_OPTION:
974 case ARM::STCL_OPTION:
975 case ARM::STC2_OPTION:
976 case ARM::STC2L_OPTION:
977 Inst.addOperand(MCOperand::CreateImm(imm));
981 Inst.addOperand(MCOperand::CreateImm(
982 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
984 Inst.addOperand(MCOperand::CreateImm(
985 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
989 switch (Inst.getOpcode()) {
990 case ARM::LDC_OFFSET:
993 case ARM::LDC_OPTION:
994 case ARM::LDCL_OFFSET:
997 case ARM::LDCL_OPTION:
998 case ARM::STC_OFFSET:
1001 case ARM::STC_OPTION:
1002 case ARM::STCL_OFFSET:
1004 case ARM::STCL_POST:
1005 case ARM::STCL_OPTION:
1006 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1016 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1017 uint64_t Address, const void *Decoder) {
1018 DecodeStatus S = Success;
1020 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1021 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1022 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1023 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1024 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1025 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1026 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1027 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1029 // On stores, the writeback operand precedes Rt.
1030 switch (Inst.getOpcode()) {
1031 case ARM::STR_POST_IMM:
1032 case ARM::STR_POST_REG:
1033 case ARM::STRB_POST_IMM:
1034 case ARM::STRB_POST_REG:
1035 case ARM::STRT_POST_REG:
1036 case ARM::STRT_POST_IMM:
1037 case ARM::STRBT_POST_REG:
1038 case ARM::STRBT_POST_IMM:
1039 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1045 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1047 // On loads, the writeback operand comes after Rt.
1048 switch (Inst.getOpcode()) {
1049 case ARM::LDR_POST_IMM:
1050 case ARM::LDR_POST_REG:
1051 case ARM::LDRB_POST_IMM:
1052 case ARM::LDRB_POST_REG:
1053 case ARM::LDRBT_POST_REG:
1054 case ARM::LDRBT_POST_IMM:
1055 case ARM::LDRT_POST_REG:
1056 case ARM::LDRT_POST_IMM:
1057 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1063 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1065 ARM_AM::AddrOpc Op = ARM_AM::add;
1066 if (!fieldFromInstruction32(Insn, 23, 1))
1069 bool writeback = (P == 0) || (W == 1);
1070 unsigned idx_mode = 0;
1072 idx_mode = ARMII::IndexModePre;
1073 else if (!P && writeback)
1074 idx_mode = ARMII::IndexModePost;
1076 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE
1079 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1080 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1081 switch( fieldFromInstruction32(Insn, 5, 2)) {
1097 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1098 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1100 Inst.addOperand(MCOperand::CreateImm(imm));
1102 Inst.addOperand(MCOperand::CreateReg(0));
1103 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1104 Inst.addOperand(MCOperand::CreateImm(tmp));
1107 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1112 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1113 uint64_t Address, const void *Decoder) {
1114 DecodeStatus S = Success;
1116 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1117 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1118 unsigned type = fieldFromInstruction32(Val, 5, 2);
1119 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1120 unsigned U = fieldFromInstruction32(Val, 12, 1);
1122 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1138 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1139 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1142 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1144 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1145 Inst.addOperand(MCOperand::CreateImm(shift));
1151 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1152 uint64_t Address, const void *Decoder) {
1153 DecodeStatus S = Success;
1155 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1156 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1157 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1158 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1159 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1160 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1161 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1162 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1163 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1165 bool writeback = (W == 1) | (P == 0);
1167 // For {LD,ST}RD, Rt must be even, else undefined.
1168 switch (Inst.getOpcode()) {
1171 case ARM::STRD_POST:
1174 case ARM::LDRD_POST:
1175 if (Rt & 0x1) return Fail;
1181 if (writeback) { // Writeback
1183 U |= ARMII::IndexModePre << 9;
1185 U |= ARMII::IndexModePost << 9;
1187 // On stores, the writeback operand precedes Rt.
1188 switch (Inst.getOpcode()) {
1191 case ARM::STRD_POST:
1194 case ARM::STRH_POST:
1195 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1202 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1203 switch (Inst.getOpcode()) {
1206 case ARM::STRD_POST:
1209 case ARM::LDRD_POST:
1210 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
1217 // On loads, the writeback operand comes after Rt.
1218 switch (Inst.getOpcode()) {
1221 case ARM::LDRD_POST:
1224 case ARM::LDRH_POST:
1226 case ARM::LDRSH_PRE:
1227 case ARM::LDRSH_POST:
1229 case ARM::LDRSB_PRE:
1230 case ARM::LDRSB_POST:
1233 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1240 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1243 Inst.addOperand(MCOperand::CreateReg(0));
1244 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1246 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1247 Inst.addOperand(MCOperand::CreateImm(U));
1250 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1255 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1256 uint64_t Address, const void *Decoder) {
1257 DecodeStatus S = Success;
1259 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1260 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1277 Inst.addOperand(MCOperand::CreateImm(mode));
1278 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1283 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1285 uint64_t Address, const void *Decoder) {
1286 DecodeStatus S = Success;
1288 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1289 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1290 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1293 switch (Inst.getOpcode()) {
1295 Inst.setOpcode(ARM::RFEDA);
1297 case ARM::LDMDA_UPD:
1298 Inst.setOpcode(ARM::RFEDA_UPD);
1301 Inst.setOpcode(ARM::RFEDB);
1303 case ARM::LDMDB_UPD:
1304 Inst.setOpcode(ARM::RFEDB_UPD);
1307 Inst.setOpcode(ARM::RFEIA);
1309 case ARM::LDMIA_UPD:
1310 Inst.setOpcode(ARM::RFEIA_UPD);
1313 Inst.setOpcode(ARM::RFEIB);
1315 case ARM::LDMIB_UPD:
1316 Inst.setOpcode(ARM::RFEIB_UPD);
1319 Inst.setOpcode(ARM::SRSDA);
1321 case ARM::STMDA_UPD:
1322 Inst.setOpcode(ARM::SRSDA_UPD);
1325 Inst.setOpcode(ARM::SRSDB);
1327 case ARM::STMDB_UPD:
1328 Inst.setOpcode(ARM::SRSDB_UPD);
1331 Inst.setOpcode(ARM::SRSIA);
1333 case ARM::STMIA_UPD:
1334 Inst.setOpcode(ARM::SRSIA_UPD);
1337 Inst.setOpcode(ARM::SRSIB);
1339 case ARM::STMIB_UPD:
1340 Inst.setOpcode(ARM::SRSIB_UPD);
1346 // For stores (which become SRS's, the only operand is the mode.
1347 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1349 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1353 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1356 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1357 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied
1358 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1359 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));
1364 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1365 uint64_t Address, const void *Decoder) {
1366 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1367 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1368 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1369 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1371 DecodeStatus S = Success;
1373 // imod == '01' --> UNPREDICTABLE
1374 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1375 // return failure here. The '01' imod value is unprintable, so there's
1376 // nothing useful we could do even if we returned UNPREDICTABLE.
1378 if (imod == 1) CHECK(S, Fail);
1381 Inst.setOpcode(ARM::CPS3p);
1382 Inst.addOperand(MCOperand::CreateImm(imod));
1383 Inst.addOperand(MCOperand::CreateImm(iflags));
1384 Inst.addOperand(MCOperand::CreateImm(mode));
1385 } else if (imod && !M) {
1386 Inst.setOpcode(ARM::CPS2p);
1387 Inst.addOperand(MCOperand::CreateImm(imod));
1388 Inst.addOperand(MCOperand::CreateImm(iflags));
1389 if (mode) CHECK(S, Unpredictable);
1390 } else if (!imod && M) {
1391 Inst.setOpcode(ARM::CPS1p);
1392 Inst.addOperand(MCOperand::CreateImm(mode));
1393 if (iflags) CHECK(S, Unpredictable);
1395 // imod == '00' && M == '0' --> UNPREDICTABLE
1396 Inst.setOpcode(ARM::CPS1p);
1397 Inst.addOperand(MCOperand::CreateImm(mode));
1398 CHECK(S, Unpredictable);
1404 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1405 uint64_t Address, const void *Decoder) {
1406 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1407 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1408 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1409 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1411 DecodeStatus S = Success;
1413 // imod == '01' --> UNPREDICTABLE
1414 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1415 // return failure here. The '01' imod value is unprintable, so there's
1416 // nothing useful we could do even if we returned UNPREDICTABLE.
1418 if (imod == 1) CHECK(S, Fail);
1421 Inst.setOpcode(ARM::t2CPS3p);
1422 Inst.addOperand(MCOperand::CreateImm(imod));
1423 Inst.addOperand(MCOperand::CreateImm(iflags));
1424 Inst.addOperand(MCOperand::CreateImm(mode));
1425 } else if (imod && !M) {
1426 Inst.setOpcode(ARM::t2CPS2p);
1427 Inst.addOperand(MCOperand::CreateImm(imod));
1428 Inst.addOperand(MCOperand::CreateImm(iflags));
1429 if (mode) CHECK(S, Unpredictable);
1430 } else if (!imod && M) {
1431 Inst.setOpcode(ARM::t2CPS1p);
1432 Inst.addOperand(MCOperand::CreateImm(mode));
1433 if (iflags) CHECK(S, Unpredictable);
1435 // imod == '00' && M == '0' --> UNPREDICTABLE
1436 Inst.setOpcode(ARM::t2CPS1p);
1437 Inst.addOperand(MCOperand::CreateImm(mode));
1438 CHECK(S, Unpredictable);
1445 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1446 uint64_t Address, const void *Decoder) {
1447 DecodeStatus S = Success;
1449 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1450 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1451 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1452 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1453 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1456 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1458 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));
1459 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));
1460 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1461 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));
1463 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1468 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1469 uint64_t Address, const void *Decoder) {
1470 DecodeStatus S = Success;
1472 unsigned add = fieldFromInstruction32(Val, 12, 1);
1473 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1474 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1476 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1478 if (!add) imm *= -1;
1479 if (imm == 0 && !add) imm = INT32_MIN;
1480 Inst.addOperand(MCOperand::CreateImm(imm));
1485 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1486 uint64_t Address, const void *Decoder) {
1487 DecodeStatus S = Success;
1489 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1490 unsigned U = fieldFromInstruction32(Val, 8, 1);
1491 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1493 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1496 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1498 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1503 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1504 uint64_t Address, const void *Decoder) {
1505 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1509 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1510 uint64_t Address, const void *Decoder) {
1511 DecodeStatus S = Success;
1513 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1514 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1517 Inst.setOpcode(ARM::BLXi);
1518 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1519 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1523 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1524 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1530 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1531 uint64_t Address, const void *Decoder) {
1532 Inst.addOperand(MCOperand::CreateImm(64 - Val));
1536 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1537 uint64_t Address, const void *Decoder) {
1538 DecodeStatus S = Success;
1540 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1541 unsigned align = fieldFromInstruction32(Val, 4, 2);
1543 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1545 Inst.addOperand(MCOperand::CreateImm(0));
1547 Inst.addOperand(MCOperand::CreateImm(4 << align));
1552 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1553 uint64_t Address, const void *Decoder) {
1554 DecodeStatus S = Success;
1556 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1557 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1558 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1559 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1560 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1561 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1563 // First output register
1564 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1566 // Second output register
1567 switch (Inst.getOpcode()) {
1572 case ARM::VLD1q8_UPD:
1573 case ARM::VLD1q16_UPD:
1574 case ARM::VLD1q32_UPD:
1575 case ARM::VLD1q64_UPD:
1580 case ARM::VLD1d8T_UPD:
1581 case ARM::VLD1d16T_UPD:
1582 case ARM::VLD1d32T_UPD:
1583 case ARM::VLD1d64T_UPD:
1588 case ARM::VLD1d8Q_UPD:
1589 case ARM::VLD1d16Q_UPD:
1590 case ARM::VLD1d32Q_UPD:
1591 case ARM::VLD1d64Q_UPD:
1595 case ARM::VLD2d8_UPD:
1596 case ARM::VLD2d16_UPD:
1597 case ARM::VLD2d32_UPD:
1601 case ARM::VLD2q8_UPD:
1602 case ARM::VLD2q16_UPD:
1603 case ARM::VLD2q32_UPD:
1607 case ARM::VLD3d8_UPD:
1608 case ARM::VLD3d16_UPD:
1609 case ARM::VLD3d32_UPD:
1613 case ARM::VLD4d8_UPD:
1614 case ARM::VLD4d16_UPD:
1615 case ARM::VLD4d32_UPD:
1616 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1621 case ARM::VLD2b8_UPD:
1622 case ARM::VLD2b16_UPD:
1623 case ARM::VLD2b32_UPD:
1627 case ARM::VLD3q8_UPD:
1628 case ARM::VLD3q16_UPD:
1629 case ARM::VLD3q32_UPD:
1633 case ARM::VLD4q8_UPD:
1634 case ARM::VLD4q16_UPD:
1635 case ARM::VLD4q32_UPD:
1636 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1641 // Third output register
1642 switch(Inst.getOpcode()) {
1647 case ARM::VLD1d8T_UPD:
1648 case ARM::VLD1d16T_UPD:
1649 case ARM::VLD1d32T_UPD:
1650 case ARM::VLD1d64T_UPD:
1655 case ARM::VLD1d8Q_UPD:
1656 case ARM::VLD1d16Q_UPD:
1657 case ARM::VLD1d32Q_UPD:
1658 case ARM::VLD1d64Q_UPD:
1662 case ARM::VLD2q8_UPD:
1663 case ARM::VLD2q16_UPD:
1664 case ARM::VLD2q32_UPD:
1668 case ARM::VLD3d8_UPD:
1669 case ARM::VLD3d16_UPD:
1670 case ARM::VLD3d32_UPD:
1674 case ARM::VLD4d8_UPD:
1675 case ARM::VLD4d16_UPD:
1676 case ARM::VLD4d32_UPD:
1677 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1682 case ARM::VLD3q8_UPD:
1683 case ARM::VLD3q16_UPD:
1684 case ARM::VLD3q32_UPD:
1688 case ARM::VLD4q8_UPD:
1689 case ARM::VLD4q16_UPD:
1690 case ARM::VLD4q32_UPD:
1691 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1697 // Fourth output register
1698 switch (Inst.getOpcode()) {
1703 case ARM::VLD1d8Q_UPD:
1704 case ARM::VLD1d16Q_UPD:
1705 case ARM::VLD1d32Q_UPD:
1706 case ARM::VLD1d64Q_UPD:
1710 case ARM::VLD2q8_UPD:
1711 case ARM::VLD2q16_UPD:
1712 case ARM::VLD2q32_UPD:
1716 case ARM::VLD4d8_UPD:
1717 case ARM::VLD4d16_UPD:
1718 case ARM::VLD4d32_UPD:
1719 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
1724 case ARM::VLD4q8_UPD:
1725 case ARM::VLD4q16_UPD:
1726 case ARM::VLD4q32_UPD:
1727 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
1733 // Writeback operand
1734 switch (Inst.getOpcode()) {
1735 case ARM::VLD1d8_UPD:
1736 case ARM::VLD1d16_UPD:
1737 case ARM::VLD1d32_UPD:
1738 case ARM::VLD1d64_UPD:
1739 case ARM::VLD1q8_UPD:
1740 case ARM::VLD1q16_UPD:
1741 case ARM::VLD1q32_UPD:
1742 case ARM::VLD1q64_UPD:
1743 case ARM::VLD1d8T_UPD:
1744 case ARM::VLD1d16T_UPD:
1745 case ARM::VLD1d32T_UPD:
1746 case ARM::VLD1d64T_UPD:
1747 case ARM::VLD1d8Q_UPD:
1748 case ARM::VLD1d16Q_UPD:
1749 case ARM::VLD1d32Q_UPD:
1750 case ARM::VLD1d64Q_UPD:
1751 case ARM::VLD2d8_UPD:
1752 case ARM::VLD2d16_UPD:
1753 case ARM::VLD2d32_UPD:
1754 case ARM::VLD2q8_UPD:
1755 case ARM::VLD2q16_UPD:
1756 case ARM::VLD2q32_UPD:
1757 case ARM::VLD2b8_UPD:
1758 case ARM::VLD2b16_UPD:
1759 case ARM::VLD2b32_UPD:
1760 case ARM::VLD3d8_UPD:
1761 case ARM::VLD3d16_UPD:
1762 case ARM::VLD3d32_UPD:
1763 case ARM::VLD3q8_UPD:
1764 case ARM::VLD3q16_UPD:
1765 case ARM::VLD3q32_UPD:
1766 case ARM::VLD4d8_UPD:
1767 case ARM::VLD4d16_UPD:
1768 case ARM::VLD4d32_UPD:
1769 case ARM::VLD4q8_UPD:
1770 case ARM::VLD4q16_UPD:
1771 case ARM::VLD4q32_UPD:
1772 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1778 // AddrMode6 Base (register+alignment)
1779 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1781 // AddrMode6 Offset (register)
1783 Inst.addOperand(MCOperand::CreateReg(0));
1784 else if (Rm != 0xF) {
1785 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1791 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
1792 uint64_t Address, const void *Decoder) {
1793 DecodeStatus S = Success;
1795 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1796 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1797 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1798 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1799 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1800 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1802 // Writeback Operand
1803 switch (Inst.getOpcode()) {
1804 case ARM::VST1d8_UPD:
1805 case ARM::VST1d16_UPD:
1806 case ARM::VST1d32_UPD:
1807 case ARM::VST1d64_UPD:
1808 case ARM::VST1q8_UPD:
1809 case ARM::VST1q16_UPD:
1810 case ARM::VST1q32_UPD:
1811 case ARM::VST1q64_UPD:
1812 case ARM::VST1d8T_UPD:
1813 case ARM::VST1d16T_UPD:
1814 case ARM::VST1d32T_UPD:
1815 case ARM::VST1d64T_UPD:
1816 case ARM::VST1d8Q_UPD:
1817 case ARM::VST1d16Q_UPD:
1818 case ARM::VST1d32Q_UPD:
1819 case ARM::VST1d64Q_UPD:
1820 case ARM::VST2d8_UPD:
1821 case ARM::VST2d16_UPD:
1822 case ARM::VST2d32_UPD:
1823 case ARM::VST2q8_UPD:
1824 case ARM::VST2q16_UPD:
1825 case ARM::VST2q32_UPD:
1826 case ARM::VST2b8_UPD:
1827 case ARM::VST2b16_UPD:
1828 case ARM::VST2b32_UPD:
1829 case ARM::VST3d8_UPD:
1830 case ARM::VST3d16_UPD:
1831 case ARM::VST3d32_UPD:
1832 case ARM::VST3q8_UPD:
1833 case ARM::VST3q16_UPD:
1834 case ARM::VST3q32_UPD:
1835 case ARM::VST4d8_UPD:
1836 case ARM::VST4d16_UPD:
1837 case ARM::VST4d32_UPD:
1838 case ARM::VST4q8_UPD:
1839 case ARM::VST4q16_UPD:
1840 case ARM::VST4q32_UPD:
1841 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1847 // AddrMode6 Base (register+alignment)
1848 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1850 // AddrMode6 Offset (register)
1852 Inst.addOperand(MCOperand::CreateReg(0));
1853 else if (Rm != 0xF) {
1854 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1857 // First input register
1858 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1860 // Second input register
1861 switch (Inst.getOpcode()) {
1866 case ARM::VST1q8_UPD:
1867 case ARM::VST1q16_UPD:
1868 case ARM::VST1q32_UPD:
1869 case ARM::VST1q64_UPD:
1874 case ARM::VST1d8T_UPD:
1875 case ARM::VST1d16T_UPD:
1876 case ARM::VST1d32T_UPD:
1877 case ARM::VST1d64T_UPD:
1882 case ARM::VST1d8Q_UPD:
1883 case ARM::VST1d16Q_UPD:
1884 case ARM::VST1d32Q_UPD:
1885 case ARM::VST1d64Q_UPD:
1889 case ARM::VST2d8_UPD:
1890 case ARM::VST2d16_UPD:
1891 case ARM::VST2d32_UPD:
1895 case ARM::VST2q8_UPD:
1896 case ARM::VST2q16_UPD:
1897 case ARM::VST2q32_UPD:
1901 case ARM::VST3d8_UPD:
1902 case ARM::VST3d16_UPD:
1903 case ARM::VST3d32_UPD:
1907 case ARM::VST4d8_UPD:
1908 case ARM::VST4d16_UPD:
1909 case ARM::VST4d32_UPD:
1910 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1915 case ARM::VST2b8_UPD:
1916 case ARM::VST2b16_UPD:
1917 case ARM::VST2b32_UPD:
1921 case ARM::VST3q8_UPD:
1922 case ARM::VST3q16_UPD:
1923 case ARM::VST3q32_UPD:
1927 case ARM::VST4q8_UPD:
1928 case ARM::VST4q16_UPD:
1929 case ARM::VST4q32_UPD:
1930 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1936 // Third input register
1937 switch (Inst.getOpcode()) {
1942 case ARM::VST1d8T_UPD:
1943 case ARM::VST1d16T_UPD:
1944 case ARM::VST1d32T_UPD:
1945 case ARM::VST1d64T_UPD:
1950 case ARM::VST1d8Q_UPD:
1951 case ARM::VST1d16Q_UPD:
1952 case ARM::VST1d32Q_UPD:
1953 case ARM::VST1d64Q_UPD:
1957 case ARM::VST2q8_UPD:
1958 case ARM::VST2q16_UPD:
1959 case ARM::VST2q32_UPD:
1963 case ARM::VST3d8_UPD:
1964 case ARM::VST3d16_UPD:
1965 case ARM::VST3d32_UPD:
1969 case ARM::VST4d8_UPD:
1970 case ARM::VST4d16_UPD:
1971 case ARM::VST4d32_UPD:
1972 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1977 case ARM::VST3q8_UPD:
1978 case ARM::VST3q16_UPD:
1979 case ARM::VST3q32_UPD:
1983 case ARM::VST4q8_UPD:
1984 case ARM::VST4q16_UPD:
1985 case ARM::VST4q32_UPD:
1986 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1992 // Fourth input register
1993 switch (Inst.getOpcode()) {
1998 case ARM::VST1d8Q_UPD:
1999 case ARM::VST1d16Q_UPD:
2000 case ARM::VST1d32Q_UPD:
2001 case ARM::VST1d64Q_UPD:
2005 case ARM::VST2q8_UPD:
2006 case ARM::VST2q16_UPD:
2007 case ARM::VST2q32_UPD:
2011 case ARM::VST4d8_UPD:
2012 case ARM::VST4d16_UPD:
2013 case ARM::VST4d32_UPD:
2014 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
2019 case ARM::VST4q8_UPD:
2020 case ARM::VST4q16_UPD:
2021 case ARM::VST4q32_UPD:
2022 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
2031 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2032 uint64_t Address, const void *Decoder) {
2033 DecodeStatus S = Success;
2035 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2036 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2037 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2038 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2039 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2040 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2041 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2043 align *= (1 << size);
2045 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2047 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
2050 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2053 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2054 Inst.addOperand(MCOperand::CreateImm(align));
2057 Inst.addOperand(MCOperand::CreateReg(0));
2058 else if (Rm != 0xF) {
2059 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2065 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2066 uint64_t Address, const void *Decoder) {
2067 DecodeStatus S = Success;
2069 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2070 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2071 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2072 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2073 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2074 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2075 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2078 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2079 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2081 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2084 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2085 Inst.addOperand(MCOperand::CreateImm(align));
2088 Inst.addOperand(MCOperand::CreateReg(0));
2089 else if (Rm != 0xF) {
2090 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2096 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2097 uint64_t Address, const void *Decoder) {
2098 DecodeStatus S = Success;
2100 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2101 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2102 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2103 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2104 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2106 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2107 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2108 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2110 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2113 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2114 Inst.addOperand(MCOperand::CreateImm(0));
2117 Inst.addOperand(MCOperand::CreateReg(0));
2118 else if (Rm != 0xF) {
2119 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2125 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2126 uint64_t Address, const void *Decoder) {
2127 DecodeStatus S = Success;
2129 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2130 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2131 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2132 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2133 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2134 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2135 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2150 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2151 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2152 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2153 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
2155 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2158 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2159 Inst.addOperand(MCOperand::CreateImm(align));
2162 Inst.addOperand(MCOperand::CreateReg(0));
2163 else if (Rm != 0xF) {
2164 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2171 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2172 uint64_t Address, const void *Decoder) {
2173 DecodeStatus S = Success;
2175 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2176 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2177 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2178 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2179 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2180 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2181 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2182 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2185 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2187 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2190 Inst.addOperand(MCOperand::CreateImm(imm));
2192 switch (Inst.getOpcode()) {
2193 case ARM::VORRiv4i16:
2194 case ARM::VORRiv2i32:
2195 case ARM::VBICiv4i16:
2196 case ARM::VBICiv2i32:
2197 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2199 case ARM::VORRiv8i16:
2200 case ARM::VORRiv4i32:
2201 case ARM::VBICiv8i16:
2202 case ARM::VBICiv4i32:
2203 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2212 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2213 uint64_t Address, const void *Decoder) {
2214 DecodeStatus S = Success;
2216 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2217 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2218 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2219 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2220 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2222 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2223 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2224 Inst.addOperand(MCOperand::CreateImm(8 << size));
2229 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2230 uint64_t Address, const void *Decoder) {
2231 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2235 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2236 uint64_t Address, const void *Decoder) {
2237 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2241 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2242 uint64_t Address, const void *Decoder) {
2243 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2247 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2248 uint64_t Address, const void *Decoder) {
2249 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2253 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2254 uint64_t Address, const void *Decoder) {
2255 DecodeStatus S = Success;
2257 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2258 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2259 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2260 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2261 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2262 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2263 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2264 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2266 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2268 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback
2271 for (unsigned i = 0; i < length; ++i) {
2272 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));
2275 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2280 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
2281 uint64_t Address, const void *Decoder) {
2282 // The immediate needs to be a fully instantiated float. However, the
2283 // auto-generated decoder is only able to fill in some of the bits
2284 // necessary. For instance, the 'b' bit is replicated multiple times,
2285 // and is even present in inverted form in one bit. We do a little
2286 // binary parsing here to fill in those missing bits, and then
2287 // reinterpret it all as a float.
2293 fp_conv.integer = Val;
2294 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2295 fp_conv.integer |= b << 26;
2296 fp_conv.integer |= b << 27;
2297 fp_conv.integer |= b << 28;
2298 fp_conv.integer |= b << 29;
2299 fp_conv.integer |= (~b & 0x1) << 30;
2301 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
2305 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2306 uint64_t Address, const void *Decoder) {
2307 DecodeStatus S = Success;
2309 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2310 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2312 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
2314 switch(Inst.getOpcode()) {
2318 break; // tADR does not explicitly represent the PC as an operand.
2320 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2324 Inst.addOperand(MCOperand::CreateImm(imm));
2328 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2329 uint64_t Address, const void *Decoder) {
2330 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2334 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2335 uint64_t Address, const void *Decoder) {
2336 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2340 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2341 uint64_t Address, const void *Decoder) {
2342 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2346 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2347 uint64_t Address, const void *Decoder) {
2348 DecodeStatus S = Success;
2350 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2351 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2353 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2354 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));
2359 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2360 uint64_t Address, const void *Decoder) {
2361 DecodeStatus S = Success;
2363 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2364 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2366 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2367 Inst.addOperand(MCOperand::CreateImm(imm));
2372 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2373 uint64_t Address, const void *Decoder) {
2374 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2379 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2380 uint64_t Address, const void *Decoder) {
2381 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2382 Inst.addOperand(MCOperand::CreateImm(Val));
2387 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2388 uint64_t Address, const void *Decoder) {
2389 DecodeStatus S = Success;
2391 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2392 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2393 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2395 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2396 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));
2397 Inst.addOperand(MCOperand::CreateImm(imm));
2402 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2403 uint64_t Address, const void *Decoder) {
2404 DecodeStatus S = Success;
2406 switch (Inst.getOpcode()) {
2412 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2413 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2417 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2419 switch (Inst.getOpcode()) {
2421 Inst.setOpcode(ARM::t2LDRBpci);
2424 Inst.setOpcode(ARM::t2LDRHpci);
2427 Inst.setOpcode(ARM::t2LDRSHpci);
2430 Inst.setOpcode(ARM::t2LDRSBpci);
2433 Inst.setOpcode(ARM::t2PLDi12);
2434 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2440 int imm = fieldFromInstruction32(Insn, 0, 12);
2441 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2442 Inst.addOperand(MCOperand::CreateImm(imm));
2447 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2448 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2449 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2450 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));
2455 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2456 uint64_t Address, const void *Decoder) {
2457 int imm = Val & 0xFF;
2458 if (!(Val & 0x100)) imm *= -1;
2459 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2464 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2465 uint64_t Address, const void *Decoder) {
2466 DecodeStatus S = Success;
2468 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2469 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2471 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2472 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));
2477 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2478 uint64_t Address, const void *Decoder) {
2479 int imm = Val & 0xFF;
2480 if (!(Val & 0x100)) imm *= -1;
2481 Inst.addOperand(MCOperand::CreateImm(imm));
2487 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2488 uint64_t Address, const void *Decoder) {
2489 DecodeStatus S = Success;
2491 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2492 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2494 // Some instructions always use an additive offset.
2495 switch (Inst.getOpcode()) {
2507 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2508 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));
2514 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2515 uint64_t Address, const void *Decoder) {
2516 DecodeStatus S = Success;
2518 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2519 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2521 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2522 Inst.addOperand(MCOperand::CreateImm(imm));
2528 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2529 uint64_t Address, const void *Decoder) {
2530 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2532 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2533 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2534 Inst.addOperand(MCOperand::CreateImm(imm));
2539 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
2540 uint64_t Address, const void *Decoder) {
2541 DecodeStatus S = Success;
2543 if (Inst.getOpcode() == ARM::tADDrSP) {
2544 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2545 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2547 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2548 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2549 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2550 } else if (Inst.getOpcode() == ARM::tADDspr) {
2551 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2553 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2554 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2555 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2561 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
2562 uint64_t Address, const void *Decoder) {
2563 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2564 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2566 Inst.addOperand(MCOperand::CreateImm(imod));
2567 Inst.addOperand(MCOperand::CreateImm(flags));
2572 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
2573 uint64_t Address, const void *Decoder) {
2574 DecodeStatus S = Success;
2575 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2576 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2578 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;
2579 Inst.addOperand(MCOperand::CreateImm(add));
2584 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
2585 uint64_t Address, const void *Decoder) {
2586 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2590 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
2591 uint64_t Address, const void *Decoder) {
2592 if (Val == 0xA || Val == 0xB)
2595 Inst.addOperand(MCOperand::CreateImm(Val));
2600 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2601 uint64_t Address, const void *Decoder) {
2602 DecodeStatus S = Success;
2604 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2605 if (pred == 0xE || pred == 0xF) {
2606 unsigned opc = fieldFromInstruction32(Insn, 4, 2);
2611 Inst.setOpcode(ARM::t2DSB);
2614 Inst.setOpcode(ARM::t2DMB);
2617 Inst.setOpcode(ARM::t2ISB);
2621 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2622 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
2625 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2626 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2627 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2628 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2629 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2631 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));
2632 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2637 // Decode a shifted immediate operand. These basically consist
2638 // of an 8-bit value, and a 4-bit directive that specifies either
2639 // a splat operation or a rotation.
2640 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
2641 uint64_t Address, const void *Decoder) {
2642 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2644 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2645 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2648 Inst.addOperand(MCOperand::CreateImm(imm));
2651 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2654 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2657 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2662 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2663 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2664 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2665 Inst.addOperand(MCOperand::CreateImm(imm));
2672 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2673 uint64_t Address, const void *Decoder){
2674 Inst.addOperand(MCOperand::CreateImm(Val << 1));
2678 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
2679 uint64_t Address, const void *Decoder){
2680 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2684 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
2685 uint64_t Address, const void *Decoder) {
2700 Inst.addOperand(MCOperand::CreateImm(Val));
2704 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
2705 uint64_t Address, const void *Decoder) {
2706 if (!Val) return Fail;
2707 Inst.addOperand(MCOperand::CreateImm(Val));
2711 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
2712 uint64_t Address, const void *Decoder) {
2713 DecodeStatus S = Success;
2715 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2716 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2717 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2719 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2721 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2722 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2723 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2724 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2730 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
2731 uint64_t Address, const void *Decoder){
2732 DecodeStatus S = Success;
2734 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2735 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2736 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2737 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2739 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));
2741 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2742 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;
2744 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2745 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2746 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2747 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2752 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
2753 uint64_t Address, const void *Decoder) {
2754 DecodeStatus S = Success;
2756 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2757 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2758 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2759 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2760 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2761 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2763 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2765 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2766 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2767 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
2768 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2773 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
2774 uint64_t Address, const void *Decoder) {
2775 DecodeStatus S = Success;
2777 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2778 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2779 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2780 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2781 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2782 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2783 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2785 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2786 if (Rm == 0xF) CHECK(S, Unpredictable);
2788 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2789 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2790 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
2791 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2797 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
2798 uint64_t Address, const void *Decoder) {
2799 DecodeStatus S = Success;
2801 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2802 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2803 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2804 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2805 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2806 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2808 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2810 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2811 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2812 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
2813 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2818 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
2819 uint64_t Address, const void *Decoder) {
2820 DecodeStatus S = Success;
2822 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2823 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2824 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2825 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2826 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2827 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2829 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2831 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2832 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2833 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
2834 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2839 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
2840 uint64_t Address, const void *Decoder) {
2841 DecodeStatus S = Success;
2843 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2844 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2845 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2846 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2847 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2855 if (fieldFromInstruction32(Insn, 4, 1))
2856 return Fail; // UNDEFINED
2857 index = fieldFromInstruction32(Insn, 5, 3);
2860 if (fieldFromInstruction32(Insn, 5, 1))
2861 return Fail; // UNDEFINED
2862 index = fieldFromInstruction32(Insn, 6, 2);
2863 if (fieldFromInstruction32(Insn, 4, 1))
2867 if (fieldFromInstruction32(Insn, 6, 1))
2868 return Fail; // UNDEFINED
2869 index = fieldFromInstruction32(Insn, 7, 1);
2870 if (fieldFromInstruction32(Insn, 4, 2) != 0)
2874 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2875 if (Rm != 0xF) { // Writeback
2876 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2878 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2879 Inst.addOperand(MCOperand::CreateImm(align));
2882 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2884 Inst.addOperand(MCOperand::CreateReg(0));
2887 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2888 Inst.addOperand(MCOperand::CreateImm(index));
2893 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
2894 uint64_t Address, const void *Decoder) {
2895 DecodeStatus S = Success;
2897 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2898 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2899 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2900 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2901 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2909 if (fieldFromInstruction32(Insn, 4, 1))
2910 return Fail; // UNDEFINED
2911 index = fieldFromInstruction32(Insn, 5, 3);
2914 if (fieldFromInstruction32(Insn, 5, 1))
2915 return Fail; // UNDEFINED
2916 index = fieldFromInstruction32(Insn, 6, 2);
2917 if (fieldFromInstruction32(Insn, 4, 1))
2921 if (fieldFromInstruction32(Insn, 6, 1))
2922 return Fail; // UNDEFINED
2923 index = fieldFromInstruction32(Insn, 7, 1);
2924 if (fieldFromInstruction32(Insn, 4, 2) != 0)
2928 if (Rm != 0xF) { // Writeback
2929 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2931 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2932 Inst.addOperand(MCOperand::CreateImm(align));
2935 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2937 Inst.addOperand(MCOperand::CreateReg(0));
2940 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2941 Inst.addOperand(MCOperand::CreateImm(index));
2947 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
2948 uint64_t Address, const void *Decoder) {
2949 DecodeStatus S = Success;
2951 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2952 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2953 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2954 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2955 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2964 index = fieldFromInstruction32(Insn, 5, 3);
2965 if (fieldFromInstruction32(Insn, 4, 1))
2969 index = fieldFromInstruction32(Insn, 6, 2);
2970 if (fieldFromInstruction32(Insn, 4, 1))
2972 if (fieldFromInstruction32(Insn, 5, 1))
2976 if (fieldFromInstruction32(Insn, 5, 1))
2977 return Fail; // UNDEFINED
2978 index = fieldFromInstruction32(Insn, 7, 1);
2979 if (fieldFromInstruction32(Insn, 4, 1) != 0)
2981 if (fieldFromInstruction32(Insn, 6, 1))
2986 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2987 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2988 if (Rm != 0xF) { // Writeback
2989 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2991 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2992 Inst.addOperand(MCOperand::CreateImm(align));
2995 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2997 Inst.addOperand(MCOperand::CreateReg(0));
3000 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3001 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3002 Inst.addOperand(MCOperand::CreateImm(index));
3007 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
3008 uint64_t Address, const void *Decoder) {
3009 DecodeStatus S = Success;
3011 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3012 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3013 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3014 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3015 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3024 index = fieldFromInstruction32(Insn, 5, 3);
3025 if (fieldFromInstruction32(Insn, 4, 1))
3029 index = fieldFromInstruction32(Insn, 6, 2);
3030 if (fieldFromInstruction32(Insn, 4, 1))
3032 if (fieldFromInstruction32(Insn, 5, 1))
3036 if (fieldFromInstruction32(Insn, 5, 1))
3037 return Fail; // UNDEFINED
3038 index = fieldFromInstruction32(Insn, 7, 1);
3039 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3041 if (fieldFromInstruction32(Insn, 6, 1))
3046 if (Rm != 0xF) { // Writeback
3047 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3049 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3050 Inst.addOperand(MCOperand::CreateImm(align));
3053 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3055 Inst.addOperand(MCOperand::CreateReg(0));
3058 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3059 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3060 Inst.addOperand(MCOperand::CreateImm(index));
3066 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3067 uint64_t Address, const void *Decoder) {
3068 DecodeStatus S = Success;
3070 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3071 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3072 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3073 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3074 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3083 if (fieldFromInstruction32(Insn, 4, 1))
3084 return Fail; // UNDEFINED
3085 index = fieldFromInstruction32(Insn, 5, 3);
3088 if (fieldFromInstruction32(Insn, 4, 1))
3089 return Fail; // UNDEFINED
3090 index = fieldFromInstruction32(Insn, 6, 2);
3091 if (fieldFromInstruction32(Insn, 5, 1))
3095 if (fieldFromInstruction32(Insn, 4, 2))
3096 return Fail; // UNDEFINED
3097 index = fieldFromInstruction32(Insn, 7, 1);
3098 if (fieldFromInstruction32(Insn, 6, 1))
3103 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3104 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3105 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3107 if (Rm != 0xF) { // Writeback
3108 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3110 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3111 Inst.addOperand(MCOperand::CreateImm(align));
3114 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3116 Inst.addOperand(MCOperand::CreateReg(0));
3119 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3120 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3121 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3122 Inst.addOperand(MCOperand::CreateImm(index));
3127 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3128 uint64_t Address, const void *Decoder) {
3129 DecodeStatus S = Success;
3131 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3132 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3133 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3134 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3135 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3144 if (fieldFromInstruction32(Insn, 4, 1))
3145 return Fail; // UNDEFINED
3146 index = fieldFromInstruction32(Insn, 5, 3);
3149 if (fieldFromInstruction32(Insn, 4, 1))
3150 return Fail; // UNDEFINED
3151 index = fieldFromInstruction32(Insn, 6, 2);
3152 if (fieldFromInstruction32(Insn, 5, 1))
3156 if (fieldFromInstruction32(Insn, 4, 2))
3157 return Fail; // UNDEFINED
3158 index = fieldFromInstruction32(Insn, 7, 1);
3159 if (fieldFromInstruction32(Insn, 6, 1))
3164 if (Rm != 0xF) { // Writeback
3165 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3167 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3168 Inst.addOperand(MCOperand::CreateImm(align));
3171 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3173 Inst.addOperand(MCOperand::CreateReg(0));
3176 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3177 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3178 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3179 Inst.addOperand(MCOperand::CreateImm(index));
3185 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3186 uint64_t Address, const void *Decoder) {
3187 DecodeStatus S = Success;
3189 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3190 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3191 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3192 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3193 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3202 if (fieldFromInstruction32(Insn, 4, 1))
3204 index = fieldFromInstruction32(Insn, 5, 3);
3207 if (fieldFromInstruction32(Insn, 4, 1))
3209 index = fieldFromInstruction32(Insn, 6, 2);
3210 if (fieldFromInstruction32(Insn, 5, 1))
3214 if (fieldFromInstruction32(Insn, 4, 2))
3215 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3216 index = fieldFromInstruction32(Insn, 7, 1);
3217 if (fieldFromInstruction32(Insn, 6, 1))
3222 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3223 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3224 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3225 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3227 if (Rm != 0xF) { // Writeback
3228 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3230 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3231 Inst.addOperand(MCOperand::CreateImm(align));
3234 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3236 Inst.addOperand(MCOperand::CreateReg(0));
3239 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3240 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3241 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3242 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3243 Inst.addOperand(MCOperand::CreateImm(index));
3248 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3249 uint64_t Address, const void *Decoder) {
3250 DecodeStatus S = Success;
3252 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3253 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3254 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3255 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3256 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3265 if (fieldFromInstruction32(Insn, 4, 1))
3267 index = fieldFromInstruction32(Insn, 5, 3);
3270 if (fieldFromInstruction32(Insn, 4, 1))
3272 index = fieldFromInstruction32(Insn, 6, 2);
3273 if (fieldFromInstruction32(Insn, 5, 1))
3277 if (fieldFromInstruction32(Insn, 4, 2))
3278 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3279 index = fieldFromInstruction32(Insn, 7, 1);
3280 if (fieldFromInstruction32(Insn, 6, 1))
3285 if (Rm != 0xF) { // Writeback
3286 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3288 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3289 Inst.addOperand(MCOperand::CreateImm(align));
3292 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3294 Inst.addOperand(MCOperand::CreateReg(0));
3297 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3298 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3299 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3300 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3301 Inst.addOperand(MCOperand::CreateImm(index));
3306 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3307 uint64_t Address, const void *Decoder) {
3308 DecodeStatus S = Success;
3309 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3310 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3311 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3312 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3313 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3315 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3316 CHECK(S, Unpredictable);
3318 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
3319 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3320 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
3321 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3322 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3327 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
3328 uint64_t Address, const void *Decoder) {
3329 DecodeStatus S = Success;
3330 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3331 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3332 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3333 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3334 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3336 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3337 CHECK(S, Unpredictable);
3339 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
3340 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3341 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
3342 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3343 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3348 static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond,
3349 uint64_t Address, const void *Decoder) {
3350 DecodeStatus S = Success;
3353 CHECK(S, Unpredictable);
3356 Inst.addOperand(MCOperand::CreateImm(Cond));
3360 static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask,
3361 uint64_t Address, const void *Decoder) {
3362 DecodeStatus S = Success;
3365 CHECK(S, Unpredictable);
3367 Inst.addOperand(MCOperand::CreateImm(Mask));