1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
13 #include "ARMRegisterInfo.h"
14 #include "ARMSubtarget.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMMCExpr.h"
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/MC/EDInstInfo.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCDisassembler.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/MemoryObject.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 /// ARMDisassembler - ARM disassembler for all ARM platforms.
35 class ARMDisassembler : public MCDisassembler {
37 /// Constructor - Initializes the disassembler.
39 ARMDisassembler(const MCSubtargetInfo &STI) :
46 /// getInstruction - See MCDisassembler.
47 DecodeStatus getInstruction(MCInst &instr,
49 const MemoryObject ®ion,
52 raw_ostream &cStream) const;
54 /// getEDInfo - See MCDisassembler.
55 EDInstInfo *getEDInfo() const;
59 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
60 class ThumbDisassembler : public MCDisassembler {
62 /// Constructor - Initializes the disassembler.
64 ThumbDisassembler(const MCSubtargetInfo &STI) :
68 ~ThumbDisassembler() {
71 /// getInstruction - See MCDisassembler.
72 DecodeStatus getInstruction(MCInst &instr,
74 const MemoryObject ®ion,
77 raw_ostream &cStream) const;
79 /// getEDInfo - See MCDisassembler.
80 EDInstInfo *getEDInfo() const;
82 mutable std::vector<unsigned> ITBlock;
83 DecodeStatus AddThumbPredicate(MCInst&) const;
84 void UpdateThumbVFPPredicate(MCInst&) const;
88 static bool Check(DecodeStatus &Out, DecodeStatus In) {
90 case MCDisassembler::Success:
91 // Out stays the same.
93 case MCDisassembler::SoftFail:
96 case MCDisassembler::Fail:
104 // Forward declare these because the autogenerated code will reference them.
105 // Definitions are further down.
106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
107 uint64_t Address, const void *Decoder);
108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
109 unsigned RegNo, uint64_t Address,
110 const void *Decoder);
111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
112 uint64_t Address, const void *Decoder);
113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
114 uint64_t Address, const void *Decoder);
115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
116 uint64_t Address, const void *Decoder);
117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
118 uint64_t Address, const void *Decoder);
119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
120 uint64_t Address, const void *Decoder);
121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
122 uint64_t Address, const void *Decoder);
123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
126 const void *Decoder);
127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
128 uint64_t Address, const void *Decoder);
130 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
131 uint64_t Address, const void *Decoder);
132 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
133 uint64_t Address, const void *Decoder);
134 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
135 uint64_t Address, const void *Decoder);
136 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
137 uint64_t Address, const void *Decoder);
138 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
139 uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
141 uint64_t Address, const void *Decoder);
143 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
144 uint64_t Address, const void *Decoder);
145 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
146 uint64_t Address, const void *Decoder);
147 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
150 const void *Decoder);
151 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
152 uint64_t Address, const void *Decoder);
153 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
154 uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
156 uint64_t Address, const void *Decoder);
157 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
158 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
163 const void *Decoder);
164 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
201 uint64_t Address, const void *Decoder);
202 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
203 uint64_t Address, const void *Decoder);
204 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
205 uint64_t Address, const void *Decoder);
206 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
207 uint64_t Address, const void *Decoder);
208 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
209 uint64_t Address, const void *Decoder);
210 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
211 uint64_t Address, const void *Decoder);
212 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
213 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
215 uint64_t Address, const void *Decoder);
216 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
217 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
251 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
260 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
262 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Val,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Val,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeT2LDRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeT2STRDPreInstruction(llvm::MCInst &Inst,unsigned Insn,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, unsigned Val,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Val,
312 uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, unsigned Val,
314 uint64_t Address, const void *Decoder);
318 #include "ARMGenDisassemblerTables.inc"
319 #include "ARMGenInstrInfo.inc"
320 #include "ARMGenEDInfo.inc"
322 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
323 return new ARMDisassembler(STI);
326 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
327 return new ThumbDisassembler(STI);
330 EDInstInfo *ARMDisassembler::getEDInfo() const {
334 EDInstInfo *ThumbDisassembler::getEDInfo() const {
338 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
339 const MemoryObject &Region,
342 raw_ostream &cs) const {
347 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
348 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
350 // We want to read exactly 4 bytes of data.
351 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
353 return MCDisassembler::Fail;
356 // Encoded as a small-endian 32-bit word in the stream.
357 uint32_t insn = (bytes[3] << 24) |
362 // Calling the auto-generated decoder function.
363 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
364 if (result != MCDisassembler::Fail) {
369 // VFP and NEON instructions, similarly, are shared between ARM
372 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
373 if (result != MCDisassembler::Fail) {
379 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
380 if (result != MCDisassembler::Fail) {
382 // Add a fake predicate operand, because we share these instruction
383 // definitions with Thumb2 where these instructions are predicable.
384 if (!DecodePredicateOperand(MI, 0xE, Address, this))
385 return MCDisassembler::Fail;
390 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
391 if (result != MCDisassembler::Fail) {
393 // Add a fake predicate operand, because we share these instruction
394 // definitions with Thumb2 where these instructions are predicable.
395 if (!DecodePredicateOperand(MI, 0xE, Address, this))
396 return MCDisassembler::Fail;
401 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
402 if (result != MCDisassembler::Fail) {
404 // Add a fake predicate operand, because we share these instruction
405 // definitions with Thumb2 where these instructions are predicable.
406 if (!DecodePredicateOperand(MI, 0xE, Address, this))
407 return MCDisassembler::Fail;
414 return MCDisassembler::Fail;
418 extern const MCInstrDesc ARMInsts[];
421 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
422 /// immediate Value in the MCInst. The immediate Value has had any PC
423 /// adjustment made by the caller. If the instruction is a branch instruction
424 /// then isBranch is true, else false. If the getOpInfo() function was set as
425 /// part of the setupForSymbolicDisassembly() call then that function is called
426 /// to get any symbolic information at the Address for this instruction. If
427 /// that returns non-zero then the symbolic information it returns is used to
428 /// create an MCExpr and that is added as an operand to the MCInst. If
429 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
430 /// Value is done and if a symbol is found an MCExpr is created with that, else
431 /// an MCExpr with Value is created. This function returns true if it adds an
432 /// operand to the MCInst and false otherwise.
433 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
434 bool isBranch, uint64_t InstSize,
435 MCInst &MI, const void *Decoder) {
436 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
437 LLVMOpInfoCallback getOpInfo = Dis->getLLVMOpInfoCallback();
441 struct LLVMOpInfo1 SymbolicOp;
442 SymbolicOp.Value = Value;
443 void *DisInfo = Dis->getDisInfoBlock();
444 if (!getOpInfo(DisInfo, Address, 0 /* Offset */, InstSize, 1, &SymbolicOp)) {
446 LLVMSymbolLookupCallback SymbolLookUp =
447 Dis->getLLVMSymbolLookupCallback();
449 uint64_t ReferenceType;
450 ReferenceType = LLVMDisassembler_ReferenceType_In_Branch;
451 const char *ReferenceName;
452 const char *Name = SymbolLookUp(DisInfo, Value, &ReferenceType, Address,
455 SymbolicOp.AddSymbol.Name = Name;
456 SymbolicOp.AddSymbol.Present = true;
457 SymbolicOp.Value = 0;
460 SymbolicOp.Value = Value;
462 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_SymbolStub)
463 (*Dis->CommentStream) << "symbol stub for: " << ReferenceName;
474 MCContext *Ctx = Dis->getMCContext();
475 const MCExpr *Add = NULL;
476 if (SymbolicOp.AddSymbol.Present) {
477 if (SymbolicOp.AddSymbol.Name) {
478 StringRef Name(SymbolicOp.AddSymbol.Name);
479 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
480 Add = MCSymbolRefExpr::Create(Sym, *Ctx);
482 Add = MCConstantExpr::Create(SymbolicOp.AddSymbol.Value, *Ctx);
486 const MCExpr *Sub = NULL;
487 if (SymbolicOp.SubtractSymbol.Present) {
488 if (SymbolicOp.SubtractSymbol.Name) {
489 StringRef Name(SymbolicOp.SubtractSymbol.Name);
490 MCSymbol *Sym = Ctx->GetOrCreateSymbol(Name);
491 Sub = MCSymbolRefExpr::Create(Sym, *Ctx);
493 Sub = MCConstantExpr::Create(SymbolicOp.SubtractSymbol.Value, *Ctx);
497 const MCExpr *Off = NULL;
498 if (SymbolicOp.Value != 0)
499 Off = MCConstantExpr::Create(SymbolicOp.Value, *Ctx);
505 LHS = MCBinaryExpr::CreateSub(Add, Sub, *Ctx);
507 LHS = MCUnaryExpr::CreateMinus(Sub, *Ctx);
509 Expr = MCBinaryExpr::CreateAdd(LHS, Off, *Ctx);
514 Expr = MCBinaryExpr::CreateAdd(Add, Off, *Ctx);
521 Expr = MCConstantExpr::Create(0, *Ctx);
524 if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_HI16)
525 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
526 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_ARM_LO16)
527 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
528 else if (SymbolicOp.VariantKind == LLVMDisassembler_VariantKind_None)
529 MI.addOperand(MCOperand::CreateExpr(Expr));
531 assert(0 && "bad SymbolicOp.VariantKind");
536 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
537 /// referenced by a load instruction with the base register that is the Pc.
538 /// These can often be values in a literal pool near the Address of the
539 /// instruction. The Address of the instruction and its immediate Value are
540 /// used as a possible literal pool entry. The SymbolLookUp call back will
541 /// return the name of a symbol referenced by the the literal pool's entry if
542 /// the referenced address is that of a symbol. Or it will return a pointer to
543 /// a literal 'C' string if the referenced address of the literal pool's entry
544 /// is an address into a section with 'C' string literals.
545 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
546 const void *Decoder) {
547 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
548 LLVMSymbolLookupCallback SymbolLookUp = Dis->getLLVMSymbolLookupCallback();
550 void *DisInfo = Dis->getDisInfoBlock();
551 uint64_t ReferenceType;
552 ReferenceType = LLVMDisassembler_ReferenceType_In_PCrel_Load;
553 const char *ReferenceName;
554 (void)SymbolLookUp(DisInfo, Value, &ReferenceType, Address, &ReferenceName);
555 if(ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_SymAddr ||
556 ReferenceType == LLVMDisassembler_ReferenceType_Out_LitPool_CstrAddr)
557 (*Dis->CommentStream) << "literal pool for: " << ReferenceName;
561 // Thumb1 instructions don't have explicit S bits. Rather, they
562 // implicitly set CPSR. Since it's not represented in the encoding, the
563 // auto-generated decoder won't inject the CPSR operand. We need to fix
564 // that as a post-pass.
565 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
566 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
567 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
568 MCInst::iterator I = MI.begin();
569 for (unsigned i = 0; i < NumOps; ++i, ++I) {
570 if (I == MI.end()) break;
571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
572 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
573 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
578 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
581 // Most Thumb instructions don't have explicit predicates in the
582 // encoding, but rather get their predicates from IT context. We need
583 // to fix up the predicate operands using this context information as a
585 MCDisassembler::DecodeStatus
586 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
587 MCDisassembler::DecodeStatus S = Success;
589 // A few instructions actually have predicates encoded in them. Don't
590 // try to overwrite it if we're seeing one of those.
591 switch (MI.getOpcode()) {
602 // Some instructions (mostly conditional branches) are not
603 // allowed in IT blocks.
604 if (!ITBlock.empty())
613 // Some instructions (mostly unconditional branches) can
614 // only appears at the end of, or outside of, an IT.
615 if (ITBlock.size() > 1)
622 // If we're in an IT block, base the predicate on that. Otherwise,
623 // assume a predicate of AL.
625 if (!ITBlock.empty()) {
633 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
634 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
635 MCInst::iterator I = MI.begin();
636 for (unsigned i = 0; i < NumOps; ++i, ++I) {
637 if (I == MI.end()) break;
638 if (OpInfo[i].isPredicate()) {
639 I = MI.insert(I, MCOperand::CreateImm(CC));
642 MI.insert(I, MCOperand::CreateReg(0));
644 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
649 I = MI.insert(I, MCOperand::CreateImm(CC));
652 MI.insert(I, MCOperand::CreateReg(0));
654 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
659 // Thumb VFP instructions are a special case. Because we share their
660 // encodings between ARM and Thumb modes, and they are predicable in ARM
661 // mode, the auto-generated decoder will give them an (incorrect)
662 // predicate operand. We need to rewrite these operands based on the IT
663 // context as a post-pass.
664 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
666 if (!ITBlock.empty()) {
672 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
673 MCInst::iterator I = MI.begin();
674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
675 for (unsigned i = 0; i < NumOps; ++i, ++I) {
676 if (OpInfo[i].isPredicate() ) {
682 I->setReg(ARM::CPSR);
688 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
689 const MemoryObject &Region,
692 raw_ostream &cs) const {
697 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
698 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
700 // We want to read exactly 2 bytes of data.
701 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1) {
703 return MCDisassembler::Fail;
706 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
707 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
708 if (result != MCDisassembler::Fail) {
710 Check(result, AddThumbPredicate(MI));
715 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
718 bool InITBlock = !ITBlock.empty();
719 Check(result, AddThumbPredicate(MI));
720 AddThumb1SBit(MI, InITBlock);
725 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
726 if (result != MCDisassembler::Fail) {
729 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
730 // the Thumb predicate.
731 if (MI.getOpcode() == ARM::t2IT && !ITBlock.empty())
732 result = MCDisassembler::SoftFail;
734 Check(result, AddThumbPredicate(MI));
736 // If we find an IT instruction, we need to parse its condition
737 // code and mask operands so that we can apply them correctly
738 // to the subsequent instructions.
739 if (MI.getOpcode() == ARM::t2IT) {
741 // (3 - the number of trailing zeros) is the number of then / else.
742 unsigned firstcond = MI.getOperand(0).getImm();
743 unsigned Mask = MI.getOperand(1).getImm();
744 unsigned CondBit0 = Mask >> 4 & 1;
745 unsigned NumTZ = CountTrailingZeros_32(Mask);
746 assert(NumTZ <= 3 && "Invalid IT mask!");
747 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
748 bool T = ((Mask >> Pos) & 1) == CondBit0;
750 ITBlock.insert(ITBlock.begin(), firstcond);
752 ITBlock.insert(ITBlock.begin(), firstcond ^ 1);
755 ITBlock.push_back(firstcond);
761 // We want to read exactly 4 bytes of data.
762 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1) {
764 return MCDisassembler::Fail;
767 uint32_t insn32 = (bytes[3] << 8) |
772 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
773 if (result != MCDisassembler::Fail) {
775 bool InITBlock = ITBlock.size();
776 Check(result, AddThumbPredicate(MI));
777 AddThumb1SBit(MI, InITBlock);
782 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
783 if (result != MCDisassembler::Fail) {
785 Check(result, AddThumbPredicate(MI));
790 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
791 if (result != MCDisassembler::Fail) {
793 UpdateThumbVFPPredicate(MI);
798 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
799 if (result != MCDisassembler::Fail) {
801 Check(result, AddThumbPredicate(MI));
805 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
807 uint32_t NEONLdStInsn = insn32;
808 NEONLdStInsn &= 0xF0FFFFFF;
809 NEONLdStInsn |= 0x04000000;
810 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
811 if (result != MCDisassembler::Fail) {
813 Check(result, AddThumbPredicate(MI));
818 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
820 uint32_t NEONDataInsn = insn32;
821 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
822 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
823 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
824 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
825 if (result != MCDisassembler::Fail) {
827 Check(result, AddThumbPredicate(MI));
833 return MCDisassembler::Fail;
837 extern "C" void LLVMInitializeARMDisassembler() {
838 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
839 createARMDisassembler);
840 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
841 createThumbDisassembler);
844 static const unsigned GPRDecoderTable[] = {
845 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
846 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
847 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
848 ARM::R12, ARM::SP, ARM::LR, ARM::PC
851 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
852 uint64_t Address, const void *Decoder) {
854 return MCDisassembler::Fail;
856 unsigned Register = GPRDecoderTable[RegNo];
857 Inst.addOperand(MCOperand::CreateReg(Register));
858 return MCDisassembler::Success;
862 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
863 uint64_t Address, const void *Decoder) {
864 if (RegNo == 15) return MCDisassembler::Fail;
865 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
868 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
869 uint64_t Address, const void *Decoder) {
871 return MCDisassembler::Fail;
872 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
875 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
876 uint64_t Address, const void *Decoder) {
877 unsigned Register = 0;
898 return MCDisassembler::Fail;
901 Inst.addOperand(MCOperand::CreateReg(Register));
902 return MCDisassembler::Success;
905 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
906 uint64_t Address, const void *Decoder) {
907 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
908 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
911 static const unsigned SPRDecoderTable[] = {
912 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
913 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
914 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
915 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
916 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
917 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
918 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
919 ARM::S28, ARM::S29, ARM::S30, ARM::S31
922 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
923 uint64_t Address, const void *Decoder) {
925 return MCDisassembler::Fail;
927 unsigned Register = SPRDecoderTable[RegNo];
928 Inst.addOperand(MCOperand::CreateReg(Register));
929 return MCDisassembler::Success;
932 static const unsigned DPRDecoderTable[] = {
933 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
934 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
935 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
936 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
937 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
938 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
939 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
940 ARM::D28, ARM::D29, ARM::D30, ARM::D31
943 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
944 uint64_t Address, const void *Decoder) {
946 return MCDisassembler::Fail;
948 unsigned Register = DPRDecoderTable[RegNo];
949 Inst.addOperand(MCOperand::CreateReg(Register));
950 return MCDisassembler::Success;
953 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
954 uint64_t Address, const void *Decoder) {
956 return MCDisassembler::Fail;
957 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
961 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
962 uint64_t Address, const void *Decoder) {
964 return MCDisassembler::Fail;
965 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
968 static const unsigned QPRDecoderTable[] = {
969 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
970 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
971 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
972 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
976 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
977 uint64_t Address, const void *Decoder) {
979 return MCDisassembler::Fail;
982 unsigned Register = QPRDecoderTable[RegNo];
983 Inst.addOperand(MCOperand::CreateReg(Register));
984 return MCDisassembler::Success;
987 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
988 uint64_t Address, const void *Decoder) {
989 if (Val == 0xF) return MCDisassembler::Fail;
990 // AL predicate is not allowed on Thumb1 branches.
991 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
992 return MCDisassembler::Fail;
993 Inst.addOperand(MCOperand::CreateImm(Val));
994 if (Val == ARMCC::AL) {
995 Inst.addOperand(MCOperand::CreateReg(0));
997 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
998 return MCDisassembler::Success;
1001 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
1002 uint64_t Address, const void *Decoder) {
1004 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1006 Inst.addOperand(MCOperand::CreateReg(0));
1007 return MCDisassembler::Success;
1010 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
1011 uint64_t Address, const void *Decoder) {
1012 uint32_t imm = Val & 0xFF;
1013 uint32_t rot = (Val & 0xF00) >> 7;
1014 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1015 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1016 return MCDisassembler::Success;
1019 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
1020 uint64_t Address, const void *Decoder) {
1021 DecodeStatus S = MCDisassembler::Success;
1023 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1024 unsigned type = fieldFromInstruction32(Val, 5, 2);
1025 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1027 // Register-immediate
1028 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1029 return MCDisassembler::Fail;
1031 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1034 Shift = ARM_AM::lsl;
1037 Shift = ARM_AM::lsr;
1040 Shift = ARM_AM::asr;
1043 Shift = ARM_AM::ror;
1047 if (Shift == ARM_AM::ror && imm == 0)
1048 Shift = ARM_AM::rrx;
1050 unsigned Op = Shift | (imm << 3);
1051 Inst.addOperand(MCOperand::CreateImm(Op));
1056 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
1057 uint64_t Address, const void *Decoder) {
1058 DecodeStatus S = MCDisassembler::Success;
1060 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1061 unsigned type = fieldFromInstruction32(Val, 5, 2);
1062 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1064 // Register-register
1065 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1066 return MCDisassembler::Fail;
1067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1068 return MCDisassembler::Fail;
1070 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1073 Shift = ARM_AM::lsl;
1076 Shift = ARM_AM::lsr;
1079 Shift = ARM_AM::asr;
1082 Shift = ARM_AM::ror;
1086 Inst.addOperand(MCOperand::CreateImm(Shift));
1091 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
1092 uint64_t Address, const void *Decoder) {
1093 DecodeStatus S = MCDisassembler::Success;
1095 bool writebackLoad = false;
1096 unsigned writebackReg = 0;
1097 switch (Inst.getOpcode()) {
1100 case ARM::LDMIA_UPD:
1101 case ARM::LDMDB_UPD:
1102 case ARM::LDMIB_UPD:
1103 case ARM::LDMDA_UPD:
1104 case ARM::t2LDMIA_UPD:
1105 case ARM::t2LDMDB_UPD:
1106 writebackLoad = true;
1107 writebackReg = Inst.getOperand(0).getReg();
1111 // Empty register lists are not allowed.
1112 if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
1113 for (unsigned i = 0; i < 16; ++i) {
1114 if (Val & (1 << i)) {
1115 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1116 return MCDisassembler::Fail;
1117 // Writeback not allowed if Rn is in the target list.
1118 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1119 Check(S, MCDisassembler::SoftFail);
1126 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1127 uint64_t Address, const void *Decoder) {
1128 DecodeStatus S = MCDisassembler::Success;
1130 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1131 unsigned regs = Val & 0xFF;
1133 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1134 return MCDisassembler::Fail;
1135 for (unsigned i = 0; i < (regs - 1); ++i) {
1136 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1137 return MCDisassembler::Fail;
1143 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
1144 uint64_t Address, const void *Decoder) {
1145 DecodeStatus S = MCDisassembler::Success;
1147 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
1148 unsigned regs = (Val & 0xFF) / 2;
1150 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1151 return MCDisassembler::Fail;
1152 for (unsigned i = 0; i < (regs - 1); ++i) {
1153 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1154 return MCDisassembler::Fail;
1160 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
1161 uint64_t Address, const void *Decoder) {
1162 // This operand encodes a mask of contiguous zeros between a specified MSB
1163 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1164 // the mask of all bits LSB-and-lower, and then xor them to create
1165 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1166 // create the final mask.
1167 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1168 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1170 DecodeStatus S = MCDisassembler::Success;
1171 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
1173 uint32_t msb_mask = 0xFFFFFFFF;
1174 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1175 uint32_t lsb_mask = (1U << lsb) - 1;
1177 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1181 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
1182 uint64_t Address, const void *Decoder) {
1183 DecodeStatus S = MCDisassembler::Success;
1185 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1186 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1187 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1188 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1189 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1190 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1192 switch (Inst.getOpcode()) {
1193 case ARM::LDC_OFFSET:
1196 case ARM::LDC_OPTION:
1197 case ARM::LDCL_OFFSET:
1199 case ARM::LDCL_POST:
1200 case ARM::LDCL_OPTION:
1201 case ARM::STC_OFFSET:
1204 case ARM::STC_OPTION:
1205 case ARM::STCL_OFFSET:
1207 case ARM::STCL_POST:
1208 case ARM::STCL_OPTION:
1209 case ARM::t2LDC_OFFSET:
1210 case ARM::t2LDC_PRE:
1211 case ARM::t2LDC_POST:
1212 case ARM::t2LDC_OPTION:
1213 case ARM::t2LDCL_OFFSET:
1214 case ARM::t2LDCL_PRE:
1215 case ARM::t2LDCL_POST:
1216 case ARM::t2LDCL_OPTION:
1217 case ARM::t2STC_OFFSET:
1218 case ARM::t2STC_PRE:
1219 case ARM::t2STC_POST:
1220 case ARM::t2STC_OPTION:
1221 case ARM::t2STCL_OFFSET:
1222 case ARM::t2STCL_PRE:
1223 case ARM::t2STCL_POST:
1224 case ARM::t2STCL_OPTION:
1225 if (coproc == 0xA || coproc == 0xB)
1226 return MCDisassembler::Fail;
1232 Inst.addOperand(MCOperand::CreateImm(coproc));
1233 Inst.addOperand(MCOperand::CreateImm(CRd));
1234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1235 return MCDisassembler::Fail;
1237 switch (Inst.getOpcode()) {
1238 case ARM::t2LDC2_OFFSET:
1239 case ARM::t2LDC2L_OFFSET:
1240 case ARM::t2LDC2_PRE:
1241 case ARM::t2LDC2L_PRE:
1242 case ARM::t2STC2_OFFSET:
1243 case ARM::t2STC2L_OFFSET:
1244 case ARM::t2STC2_PRE:
1245 case ARM::t2STC2L_PRE:
1246 case ARM::LDC2_OFFSET:
1247 case ARM::LDC2L_OFFSET:
1249 case ARM::LDC2L_PRE:
1250 case ARM::STC2_OFFSET:
1251 case ARM::STC2L_OFFSET:
1253 case ARM::STC2L_PRE:
1254 case ARM::t2LDC_OFFSET:
1255 case ARM::t2LDCL_OFFSET:
1256 case ARM::t2LDC_PRE:
1257 case ARM::t2LDCL_PRE:
1258 case ARM::t2STC_OFFSET:
1259 case ARM::t2STCL_OFFSET:
1260 case ARM::t2STC_PRE:
1261 case ARM::t2STCL_PRE:
1262 case ARM::LDC_OFFSET:
1263 case ARM::LDCL_OFFSET:
1266 case ARM::STC_OFFSET:
1267 case ARM::STCL_OFFSET:
1270 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1271 Inst.addOperand(MCOperand::CreateImm(imm));
1273 case ARM::t2LDC2_POST:
1274 case ARM::t2LDC2L_POST:
1275 case ARM::t2STC2_POST:
1276 case ARM::t2STC2L_POST:
1277 case ARM::LDC2_POST:
1278 case ARM::LDC2L_POST:
1279 case ARM::STC2_POST:
1280 case ARM::STC2L_POST:
1281 case ARM::t2LDC_POST:
1282 case ARM::t2LDCL_POST:
1283 case ARM::t2STC_POST:
1284 case ARM::t2STCL_POST:
1286 case ARM::LDCL_POST:
1288 case ARM::STCL_POST:
1292 // The 'option' variant doesn't encode 'U' in the immediate since
1293 // the immediate is unsigned [0,255].
1294 Inst.addOperand(MCOperand::CreateImm(imm));
1298 switch (Inst.getOpcode()) {
1299 case ARM::LDC_OFFSET:
1302 case ARM::LDC_OPTION:
1303 case ARM::LDCL_OFFSET:
1305 case ARM::LDCL_POST:
1306 case ARM::LDCL_OPTION:
1307 case ARM::STC_OFFSET:
1310 case ARM::STC_OPTION:
1311 case ARM::STCL_OFFSET:
1313 case ARM::STCL_POST:
1314 case ARM::STCL_OPTION:
1315 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1316 return MCDisassembler::Fail;
1326 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1327 uint64_t Address, const void *Decoder) {
1328 DecodeStatus S = MCDisassembler::Success;
1330 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1331 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1332 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1333 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1334 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1335 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1336 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1337 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1339 // On stores, the writeback operand precedes Rt.
1340 switch (Inst.getOpcode()) {
1341 case ARM::STR_POST_IMM:
1342 case ARM::STR_POST_REG:
1343 case ARM::STRB_POST_IMM:
1344 case ARM::STRB_POST_REG:
1345 case ARM::STRT_POST_REG:
1346 case ARM::STRT_POST_IMM:
1347 case ARM::STRBT_POST_REG:
1348 case ARM::STRBT_POST_IMM:
1349 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1350 return MCDisassembler::Fail;
1356 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1357 return MCDisassembler::Fail;
1359 // On loads, the writeback operand comes after Rt.
1360 switch (Inst.getOpcode()) {
1361 case ARM::LDR_POST_IMM:
1362 case ARM::LDR_POST_REG:
1363 case ARM::LDRB_POST_IMM:
1364 case ARM::LDRB_POST_REG:
1365 case ARM::LDRBT_POST_REG:
1366 case ARM::LDRBT_POST_IMM:
1367 case ARM::LDRT_POST_REG:
1368 case ARM::LDRT_POST_IMM:
1369 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1370 return MCDisassembler::Fail;
1376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1377 return MCDisassembler::Fail;
1379 ARM_AM::AddrOpc Op = ARM_AM::add;
1380 if (!fieldFromInstruction32(Insn, 23, 1))
1383 bool writeback = (P == 0) || (W == 1);
1384 unsigned idx_mode = 0;
1386 idx_mode = ARMII::IndexModePre;
1387 else if (!P && writeback)
1388 idx_mode = ARMII::IndexModePost;
1390 if (writeback && (Rn == 15 || Rn == Rt))
1391 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1394 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1395 return MCDisassembler::Fail;
1396 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1397 switch( fieldFromInstruction32(Insn, 5, 2)) {
1411 return MCDisassembler::Fail;
1413 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1414 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1416 Inst.addOperand(MCOperand::CreateImm(imm));
1418 Inst.addOperand(MCOperand::CreateReg(0));
1419 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1420 Inst.addOperand(MCOperand::CreateImm(tmp));
1423 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1424 return MCDisassembler::Fail;
1429 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1430 uint64_t Address, const void *Decoder) {
1431 DecodeStatus S = MCDisassembler::Success;
1433 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1434 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1435 unsigned type = fieldFromInstruction32(Val, 5, 2);
1436 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1437 unsigned U = fieldFromInstruction32(Val, 12, 1);
1439 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1455 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1456 return MCDisassembler::Fail;
1457 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1458 return MCDisassembler::Fail;
1461 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1463 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1464 Inst.addOperand(MCOperand::CreateImm(shift));
1470 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1471 uint64_t Address, const void *Decoder) {
1472 DecodeStatus S = MCDisassembler::Success;
1474 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1475 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1476 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1477 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1478 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1479 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1480 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1481 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1482 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1484 bool writeback = (W == 1) | (P == 0);
1486 // For {LD,ST}RD, Rt must be even, else undefined.
1487 switch (Inst.getOpcode()) {
1490 case ARM::STRD_POST:
1493 case ARM::LDRD_POST:
1494 if (Rt & 0x1) return MCDisassembler::Fail;
1500 if (writeback) { // Writeback
1502 U |= ARMII::IndexModePre << 9;
1504 U |= ARMII::IndexModePost << 9;
1506 // On stores, the writeback operand precedes Rt.
1507 switch (Inst.getOpcode()) {
1510 case ARM::STRD_POST:
1513 case ARM::STRH_POST:
1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1515 return MCDisassembler::Fail;
1522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1523 return MCDisassembler::Fail;
1524 switch (Inst.getOpcode()) {
1527 case ARM::STRD_POST:
1530 case ARM::LDRD_POST:
1531 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1532 return MCDisassembler::Fail;
1539 // On loads, the writeback operand comes after Rt.
1540 switch (Inst.getOpcode()) {
1543 case ARM::LDRD_POST:
1546 case ARM::LDRH_POST:
1548 case ARM::LDRSH_PRE:
1549 case ARM::LDRSH_POST:
1551 case ARM::LDRSB_PRE:
1552 case ARM::LDRSB_POST:
1555 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1556 return MCDisassembler::Fail;
1563 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1564 return MCDisassembler::Fail;
1567 Inst.addOperand(MCOperand::CreateReg(0));
1568 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1571 return MCDisassembler::Fail;
1572 Inst.addOperand(MCOperand::CreateImm(U));
1575 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1576 return MCDisassembler::Fail;
1581 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1582 uint64_t Address, const void *Decoder) {
1583 DecodeStatus S = MCDisassembler::Success;
1585 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1586 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1603 Inst.addOperand(MCOperand::CreateImm(mode));
1604 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1605 return MCDisassembler::Fail;
1610 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1612 uint64_t Address, const void *Decoder) {
1613 DecodeStatus S = MCDisassembler::Success;
1615 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1616 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1617 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1620 switch (Inst.getOpcode()) {
1622 Inst.setOpcode(ARM::RFEDA);
1624 case ARM::LDMDA_UPD:
1625 Inst.setOpcode(ARM::RFEDA_UPD);
1628 Inst.setOpcode(ARM::RFEDB);
1630 case ARM::LDMDB_UPD:
1631 Inst.setOpcode(ARM::RFEDB_UPD);
1634 Inst.setOpcode(ARM::RFEIA);
1636 case ARM::LDMIA_UPD:
1637 Inst.setOpcode(ARM::RFEIA_UPD);
1640 Inst.setOpcode(ARM::RFEIB);
1642 case ARM::LDMIB_UPD:
1643 Inst.setOpcode(ARM::RFEIB_UPD);
1646 Inst.setOpcode(ARM::SRSDA);
1648 case ARM::STMDA_UPD:
1649 Inst.setOpcode(ARM::SRSDA_UPD);
1652 Inst.setOpcode(ARM::SRSDB);
1654 case ARM::STMDB_UPD:
1655 Inst.setOpcode(ARM::SRSDB_UPD);
1658 Inst.setOpcode(ARM::SRSIA);
1660 case ARM::STMIA_UPD:
1661 Inst.setOpcode(ARM::SRSIA_UPD);
1664 Inst.setOpcode(ARM::SRSIB);
1666 case ARM::STMIB_UPD:
1667 Inst.setOpcode(ARM::SRSIB_UPD);
1670 if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
1673 // For stores (which become SRS's, the only operand is the mode.
1674 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1676 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1680 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1683 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1684 return MCDisassembler::Fail;
1685 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1686 return MCDisassembler::Fail; // Tied
1687 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1688 return MCDisassembler::Fail;
1689 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1690 return MCDisassembler::Fail;
1695 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1696 uint64_t Address, const void *Decoder) {
1697 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1698 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1699 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1700 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1702 DecodeStatus S = MCDisassembler::Success;
1704 // imod == '01' --> UNPREDICTABLE
1705 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1706 // return failure here. The '01' imod value is unprintable, so there's
1707 // nothing useful we could do even if we returned UNPREDICTABLE.
1709 if (imod == 1) return MCDisassembler::Fail;
1712 Inst.setOpcode(ARM::CPS3p);
1713 Inst.addOperand(MCOperand::CreateImm(imod));
1714 Inst.addOperand(MCOperand::CreateImm(iflags));
1715 Inst.addOperand(MCOperand::CreateImm(mode));
1716 } else if (imod && !M) {
1717 Inst.setOpcode(ARM::CPS2p);
1718 Inst.addOperand(MCOperand::CreateImm(imod));
1719 Inst.addOperand(MCOperand::CreateImm(iflags));
1720 if (mode) S = MCDisassembler::SoftFail;
1721 } else if (!imod && M) {
1722 Inst.setOpcode(ARM::CPS1p);
1723 Inst.addOperand(MCOperand::CreateImm(mode));
1724 if (iflags) S = MCDisassembler::SoftFail;
1726 // imod == '00' && M == '0' --> UNPREDICTABLE
1727 Inst.setOpcode(ARM::CPS1p);
1728 Inst.addOperand(MCOperand::CreateImm(mode));
1729 S = MCDisassembler::SoftFail;
1735 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1736 uint64_t Address, const void *Decoder) {
1737 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1738 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1739 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1740 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1742 DecodeStatus S = MCDisassembler::Success;
1744 // imod == '01' --> UNPREDICTABLE
1745 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1746 // return failure here. The '01' imod value is unprintable, so there's
1747 // nothing useful we could do even if we returned UNPREDICTABLE.
1749 if (imod == 1) return MCDisassembler::Fail;
1752 Inst.setOpcode(ARM::t2CPS3p);
1753 Inst.addOperand(MCOperand::CreateImm(imod));
1754 Inst.addOperand(MCOperand::CreateImm(iflags));
1755 Inst.addOperand(MCOperand::CreateImm(mode));
1756 } else if (imod && !M) {
1757 Inst.setOpcode(ARM::t2CPS2p);
1758 Inst.addOperand(MCOperand::CreateImm(imod));
1759 Inst.addOperand(MCOperand::CreateImm(iflags));
1760 if (mode) S = MCDisassembler::SoftFail;
1761 } else if (!imod && M) {
1762 Inst.setOpcode(ARM::t2CPS1p);
1763 Inst.addOperand(MCOperand::CreateImm(mode));
1764 if (iflags) S = MCDisassembler::SoftFail;
1766 // imod == '00' && M == '0' --> UNPREDICTABLE
1767 Inst.setOpcode(ARM::t2CPS1p);
1768 Inst.addOperand(MCOperand::CreateImm(mode));
1769 S = MCDisassembler::SoftFail;
1775 static DecodeStatus DecodeT2MOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1776 uint64_t Address, const void *Decoder) {
1777 DecodeStatus S = MCDisassembler::Success;
1779 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1782 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1783 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1784 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1785 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1787 if (Inst.getOpcode() == ARM::t2MOVTi16)
1788 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1789 return MCDisassembler::Fail;
1790 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1791 return MCDisassembler::Fail;
1793 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1794 Inst.addOperand(MCOperand::CreateImm(imm));
1799 static DecodeStatus DecodeArmMOVTWInstruction(llvm::MCInst &Inst, unsigned Insn,
1800 uint64_t Address, const void *Decoder) {
1801 DecodeStatus S = MCDisassembler::Success;
1803 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1804 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1807 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1808 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1810 if (Inst.getOpcode() == ARM::MOVTi16)
1811 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1812 return MCDisassembler::Fail;
1813 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1814 return MCDisassembler::Fail;
1816 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1817 Inst.addOperand(MCOperand::CreateImm(imm));
1819 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1820 return MCDisassembler::Fail;
1825 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1826 uint64_t Address, const void *Decoder) {
1827 DecodeStatus S = MCDisassembler::Success;
1829 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1830 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1831 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1832 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1833 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1836 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1838 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1839 return MCDisassembler::Fail;
1840 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1841 return MCDisassembler::Fail;
1842 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1843 return MCDisassembler::Fail;
1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
1845 return MCDisassembler::Fail;
1847 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1848 return MCDisassembler::Fail;
1853 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1854 uint64_t Address, const void *Decoder) {
1855 DecodeStatus S = MCDisassembler::Success;
1857 unsigned add = fieldFromInstruction32(Val, 12, 1);
1858 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1859 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1861 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1862 return MCDisassembler::Fail;
1864 if (!add) imm *= -1;
1865 if (imm == 0 && !add) imm = INT32_MIN;
1866 Inst.addOperand(MCOperand::CreateImm(imm));
1868 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
1873 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1874 uint64_t Address, const void *Decoder) {
1875 DecodeStatus S = MCDisassembler::Success;
1877 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1878 unsigned U = fieldFromInstruction32(Val, 8, 1);
1879 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1881 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1882 return MCDisassembler::Fail;
1885 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1887 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1892 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1893 uint64_t Address, const void *Decoder) {
1894 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1898 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1899 uint64_t Address, const void *Decoder) {
1900 DecodeStatus S = MCDisassembler::Success;
1902 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1903 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1906 Inst.setOpcode(ARM::BLXi);
1907 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1908 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1912 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, true,
1914 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1915 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1916 return MCDisassembler::Fail;
1922 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1923 uint64_t Address, const void *Decoder) {
1924 Inst.addOperand(MCOperand::CreateImm(64 - Val));
1925 return MCDisassembler::Success;
1928 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1929 uint64_t Address, const void *Decoder) {
1930 DecodeStatus S = MCDisassembler::Success;
1932 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1933 unsigned align = fieldFromInstruction32(Val, 4, 2);
1935 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1936 return MCDisassembler::Fail;
1938 Inst.addOperand(MCOperand::CreateImm(0));
1940 Inst.addOperand(MCOperand::CreateImm(4 << align));
1945 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1946 uint64_t Address, const void *Decoder) {
1947 DecodeStatus S = MCDisassembler::Success;
1949 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1950 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1951 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1952 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1953 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1954 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1956 // First output register
1957 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
1958 return MCDisassembler::Fail;
1960 // Second output register
1961 switch (Inst.getOpcode()) {
1965 case ARM::VLD3d8_UPD:
1966 case ARM::VLD3d16_UPD:
1967 case ARM::VLD3d32_UPD:
1971 case ARM::VLD4d8_UPD:
1972 case ARM::VLD4d16_UPD:
1973 case ARM::VLD4d32_UPD:
1974 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
1975 return MCDisassembler::Fail;
1980 case ARM::VLD3q8_UPD:
1981 case ARM::VLD3q16_UPD:
1982 case ARM::VLD3q32_UPD:
1986 case ARM::VLD4q8_UPD:
1987 case ARM::VLD4q16_UPD:
1988 case ARM::VLD4q32_UPD:
1989 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
1990 return MCDisassembler::Fail;
1995 // Third output register
1996 switch(Inst.getOpcode()) {
2000 case ARM::VLD3d8_UPD:
2001 case ARM::VLD3d16_UPD:
2002 case ARM::VLD3d32_UPD:
2006 case ARM::VLD4d8_UPD:
2007 case ARM::VLD4d16_UPD:
2008 case ARM::VLD4d32_UPD:
2009 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2010 return MCDisassembler::Fail;
2015 case ARM::VLD3q8_UPD:
2016 case ARM::VLD3q16_UPD:
2017 case ARM::VLD3q32_UPD:
2021 case ARM::VLD4q8_UPD:
2022 case ARM::VLD4q16_UPD:
2023 case ARM::VLD4q32_UPD:
2024 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2025 return MCDisassembler::Fail;
2031 // Fourth output register
2032 switch (Inst.getOpcode()) {
2036 case ARM::VLD4d8_UPD:
2037 case ARM::VLD4d16_UPD:
2038 case ARM::VLD4d32_UPD:
2039 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2040 return MCDisassembler::Fail;
2045 case ARM::VLD4q8_UPD:
2046 case ARM::VLD4q16_UPD:
2047 case ARM::VLD4q32_UPD:
2048 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2049 return MCDisassembler::Fail;
2055 // Writeback operand
2056 switch (Inst.getOpcode()) {
2057 case ARM::VLD1d8_UPD:
2058 case ARM::VLD1d16_UPD:
2059 case ARM::VLD1d32_UPD:
2060 case ARM::VLD1d64_UPD:
2061 case ARM::VLD1q8_UPD:
2062 case ARM::VLD1q16_UPD:
2063 case ARM::VLD1q32_UPD:
2064 case ARM::VLD1q64_UPD:
2065 case ARM::VLD1d8T_UPD:
2066 case ARM::VLD1d16T_UPD:
2067 case ARM::VLD1d32T_UPD:
2068 case ARM::VLD1d64T_UPD:
2069 case ARM::VLD1d8Q_UPD:
2070 case ARM::VLD1d16Q_UPD:
2071 case ARM::VLD1d32Q_UPD:
2072 case ARM::VLD1d64Q_UPD:
2073 case ARM::VLD2d8_UPD:
2074 case ARM::VLD2d16_UPD:
2075 case ARM::VLD2d32_UPD:
2076 case ARM::VLD2q8_UPD:
2077 case ARM::VLD2q16_UPD:
2078 case ARM::VLD2q32_UPD:
2079 case ARM::VLD2b8_UPD:
2080 case ARM::VLD2b16_UPD:
2081 case ARM::VLD2b32_UPD:
2082 case ARM::VLD3d8_UPD:
2083 case ARM::VLD3d16_UPD:
2084 case ARM::VLD3d32_UPD:
2085 case ARM::VLD3q8_UPD:
2086 case ARM::VLD3q16_UPD:
2087 case ARM::VLD3q32_UPD:
2088 case ARM::VLD4d8_UPD:
2089 case ARM::VLD4d16_UPD:
2090 case ARM::VLD4d32_UPD:
2091 case ARM::VLD4q8_UPD:
2092 case ARM::VLD4q16_UPD:
2093 case ARM::VLD4q32_UPD:
2094 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2095 return MCDisassembler::Fail;
2101 // AddrMode6 Base (register+alignment)
2102 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2103 return MCDisassembler::Fail;
2105 // AddrMode6 Offset (register)
2107 Inst.addOperand(MCOperand::CreateReg(0));
2108 else if (Rm != 0xF) {
2109 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2110 return MCDisassembler::Fail;
2116 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
2117 uint64_t Address, const void *Decoder) {
2118 DecodeStatus S = MCDisassembler::Success;
2120 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2121 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2122 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2123 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2124 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2125 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2127 // Writeback Operand
2128 switch (Inst.getOpcode()) {
2129 case ARM::VST1d8_UPD:
2130 case ARM::VST1d16_UPD:
2131 case ARM::VST1d32_UPD:
2132 case ARM::VST1d64_UPD:
2133 case ARM::VST1q8_UPD:
2134 case ARM::VST1q16_UPD:
2135 case ARM::VST1q32_UPD:
2136 case ARM::VST1q64_UPD:
2137 case ARM::VST1d8T_UPD:
2138 case ARM::VST1d16T_UPD:
2139 case ARM::VST1d32T_UPD:
2140 case ARM::VST1d64T_UPD:
2141 case ARM::VST1d8Q_UPD:
2142 case ARM::VST1d16Q_UPD:
2143 case ARM::VST1d32Q_UPD:
2144 case ARM::VST1d64Q_UPD:
2145 case ARM::VST2d8_UPD:
2146 case ARM::VST2d16_UPD:
2147 case ARM::VST2d32_UPD:
2148 case ARM::VST2q8_UPD:
2149 case ARM::VST2q16_UPD:
2150 case ARM::VST2q32_UPD:
2151 case ARM::VST2b8_UPD:
2152 case ARM::VST2b16_UPD:
2153 case ARM::VST2b32_UPD:
2154 case ARM::VST3d8_UPD:
2155 case ARM::VST3d16_UPD:
2156 case ARM::VST3d32_UPD:
2157 case ARM::VST3q8_UPD:
2158 case ARM::VST3q16_UPD:
2159 case ARM::VST3q32_UPD:
2160 case ARM::VST4d8_UPD:
2161 case ARM::VST4d16_UPD:
2162 case ARM::VST4d32_UPD:
2163 case ARM::VST4q8_UPD:
2164 case ARM::VST4q16_UPD:
2165 case ARM::VST4q32_UPD:
2166 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2167 return MCDisassembler::Fail;
2173 // AddrMode6 Base (register+alignment)
2174 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2175 return MCDisassembler::Fail;
2177 // AddrMode6 Offset (register)
2179 Inst.addOperand(MCOperand::CreateReg(0));
2180 else if (Rm != 0xF) {
2181 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2182 return MCDisassembler::Fail;
2185 // First input register
2186 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2187 return MCDisassembler::Fail;
2189 // Second input register
2190 switch (Inst.getOpcode()) {
2195 case ARM::VST1q8_UPD:
2196 case ARM::VST1q16_UPD:
2197 case ARM::VST1q32_UPD:
2198 case ARM::VST1q64_UPD:
2203 case ARM::VST1d8T_UPD:
2204 case ARM::VST1d16T_UPD:
2205 case ARM::VST1d32T_UPD:
2206 case ARM::VST1d64T_UPD:
2211 case ARM::VST1d8Q_UPD:
2212 case ARM::VST1d16Q_UPD:
2213 case ARM::VST1d32Q_UPD:
2214 case ARM::VST1d64Q_UPD:
2218 case ARM::VST2d8_UPD:
2219 case ARM::VST2d16_UPD:
2220 case ARM::VST2d32_UPD:
2224 case ARM::VST2q8_UPD:
2225 case ARM::VST2q16_UPD:
2226 case ARM::VST2q32_UPD:
2230 case ARM::VST3d8_UPD:
2231 case ARM::VST3d16_UPD:
2232 case ARM::VST3d32_UPD:
2236 case ARM::VST4d8_UPD:
2237 case ARM::VST4d16_UPD:
2238 case ARM::VST4d32_UPD:
2239 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2240 return MCDisassembler::Fail;
2245 case ARM::VST2b8_UPD:
2246 case ARM::VST2b16_UPD:
2247 case ARM::VST2b32_UPD:
2251 case ARM::VST3q8_UPD:
2252 case ARM::VST3q16_UPD:
2253 case ARM::VST3q32_UPD:
2257 case ARM::VST4q8_UPD:
2258 case ARM::VST4q16_UPD:
2259 case ARM::VST4q32_UPD:
2260 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2261 return MCDisassembler::Fail;
2267 // Third input register
2268 switch (Inst.getOpcode()) {
2273 case ARM::VST1d8T_UPD:
2274 case ARM::VST1d16T_UPD:
2275 case ARM::VST1d32T_UPD:
2276 case ARM::VST1d64T_UPD:
2281 case ARM::VST1d8Q_UPD:
2282 case ARM::VST1d16Q_UPD:
2283 case ARM::VST1d32Q_UPD:
2284 case ARM::VST1d64Q_UPD:
2288 case ARM::VST2q8_UPD:
2289 case ARM::VST2q16_UPD:
2290 case ARM::VST2q32_UPD:
2294 case ARM::VST3d8_UPD:
2295 case ARM::VST3d16_UPD:
2296 case ARM::VST3d32_UPD:
2300 case ARM::VST4d8_UPD:
2301 case ARM::VST4d16_UPD:
2302 case ARM::VST4d32_UPD:
2303 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2304 return MCDisassembler::Fail;
2309 case ARM::VST3q8_UPD:
2310 case ARM::VST3q16_UPD:
2311 case ARM::VST3q32_UPD:
2315 case ARM::VST4q8_UPD:
2316 case ARM::VST4q16_UPD:
2317 case ARM::VST4q32_UPD:
2318 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2319 return MCDisassembler::Fail;
2325 // Fourth input register
2326 switch (Inst.getOpcode()) {
2331 case ARM::VST1d8Q_UPD:
2332 case ARM::VST1d16Q_UPD:
2333 case ARM::VST1d32Q_UPD:
2334 case ARM::VST1d64Q_UPD:
2338 case ARM::VST2q8_UPD:
2339 case ARM::VST2q16_UPD:
2340 case ARM::VST2q32_UPD:
2344 case ARM::VST4d8_UPD:
2345 case ARM::VST4d16_UPD:
2346 case ARM::VST4d32_UPD:
2347 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2348 return MCDisassembler::Fail;
2353 case ARM::VST4q8_UPD:
2354 case ARM::VST4q16_UPD:
2355 case ARM::VST4q32_UPD:
2356 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2357 return MCDisassembler::Fail;
2366 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2367 uint64_t Address, const void *Decoder) {
2368 DecodeStatus S = MCDisassembler::Success;
2370 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2371 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2372 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2373 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2374 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2375 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2376 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2378 align *= (1 << size);
2380 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2381 return MCDisassembler::Fail;
2383 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2384 return MCDisassembler::Fail;
2387 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2388 return MCDisassembler::Fail;
2391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2392 return MCDisassembler::Fail;
2393 Inst.addOperand(MCOperand::CreateImm(align));
2396 Inst.addOperand(MCOperand::CreateReg(0));
2397 else if (Rm != 0xF) {
2398 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2399 return MCDisassembler::Fail;
2405 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2406 uint64_t Address, const void *Decoder) {
2407 DecodeStatus S = MCDisassembler::Success;
2409 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2410 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2411 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2412 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2413 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2414 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2415 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2418 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2419 return MCDisassembler::Fail;
2420 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2421 return MCDisassembler::Fail;
2423 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2424 return MCDisassembler::Fail;
2427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2428 return MCDisassembler::Fail;
2429 Inst.addOperand(MCOperand::CreateImm(align));
2432 Inst.addOperand(MCOperand::CreateReg(0));
2433 else if (Rm != 0xF) {
2434 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2435 return MCDisassembler::Fail;
2441 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2442 uint64_t Address, const void *Decoder) {
2443 DecodeStatus S = MCDisassembler::Success;
2445 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2446 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2447 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2448 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2449 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2451 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2452 return MCDisassembler::Fail;
2453 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2454 return MCDisassembler::Fail;
2455 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2456 return MCDisassembler::Fail;
2458 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2459 return MCDisassembler::Fail;
2462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2463 return MCDisassembler::Fail;
2464 Inst.addOperand(MCOperand::CreateImm(0));
2467 Inst.addOperand(MCOperand::CreateReg(0));
2468 else if (Rm != 0xF) {
2469 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2470 return MCDisassembler::Fail;
2476 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2477 uint64_t Address, const void *Decoder) {
2478 DecodeStatus S = MCDisassembler::Success;
2480 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2481 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2482 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2483 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2484 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2485 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2486 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2502 return MCDisassembler::Fail;
2503 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2504 return MCDisassembler::Fail;
2505 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2506 return MCDisassembler::Fail;
2507 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2508 return MCDisassembler::Fail;
2510 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2511 return MCDisassembler::Fail;
2514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2515 return MCDisassembler::Fail;
2516 Inst.addOperand(MCOperand::CreateImm(align));
2519 Inst.addOperand(MCOperand::CreateReg(0));
2520 else if (Rm != 0xF) {
2521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2522 return MCDisassembler::Fail;
2529 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2530 uint64_t Address, const void *Decoder) {
2531 DecodeStatus S = MCDisassembler::Success;
2533 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2534 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2535 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2536 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2537 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2538 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2539 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2540 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2543 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2544 return MCDisassembler::Fail;
2546 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2547 return MCDisassembler::Fail;
2550 Inst.addOperand(MCOperand::CreateImm(imm));
2552 switch (Inst.getOpcode()) {
2553 case ARM::VORRiv4i16:
2554 case ARM::VORRiv2i32:
2555 case ARM::VBICiv4i16:
2556 case ARM::VBICiv2i32:
2557 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2558 return MCDisassembler::Fail;
2560 case ARM::VORRiv8i16:
2561 case ARM::VORRiv4i32:
2562 case ARM::VBICiv8i16:
2563 case ARM::VBICiv4i32:
2564 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2565 return MCDisassembler::Fail;
2574 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2575 uint64_t Address, const void *Decoder) {
2576 DecodeStatus S = MCDisassembler::Success;
2578 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2579 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2580 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2581 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2582 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2584 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2585 return MCDisassembler::Fail;
2586 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2587 return MCDisassembler::Fail;
2588 Inst.addOperand(MCOperand::CreateImm(8 << size));
2593 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2594 uint64_t Address, const void *Decoder) {
2595 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2596 return MCDisassembler::Success;
2599 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2600 uint64_t Address, const void *Decoder) {
2601 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2602 return MCDisassembler::Success;
2605 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2606 uint64_t Address, const void *Decoder) {
2607 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2608 return MCDisassembler::Success;
2611 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2612 uint64_t Address, const void *Decoder) {
2613 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2614 return MCDisassembler::Success;
2617 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2618 uint64_t Address, const void *Decoder) {
2619 DecodeStatus S = MCDisassembler::Success;
2621 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2622 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2623 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2624 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2625 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2626 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2627 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2628 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2631 return MCDisassembler::Fail;
2633 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2634 return MCDisassembler::Fail; // Writeback
2637 for (unsigned i = 0; i < length; ++i) {
2638 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder)))
2639 return MCDisassembler::Fail;
2642 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
2643 return MCDisassembler::Fail;
2648 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2649 uint64_t Address, const void *Decoder) {
2650 DecodeStatus S = MCDisassembler::Success;
2652 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2653 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2655 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
2656 return MCDisassembler::Fail;
2658 switch(Inst.getOpcode()) {
2660 return MCDisassembler::Fail;
2662 break; // tADR does not explicitly represent the PC as an operand.
2664 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2668 Inst.addOperand(MCOperand::CreateImm(imm));
2672 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2673 uint64_t Address, const void *Decoder) {
2674 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2675 return MCDisassembler::Success;
2678 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2679 uint64_t Address, const void *Decoder) {
2680 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2681 return MCDisassembler::Success;
2684 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2685 uint64_t Address, const void *Decoder) {
2686 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2687 return MCDisassembler::Success;
2690 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2691 uint64_t Address, const void *Decoder) {
2692 DecodeStatus S = MCDisassembler::Success;
2694 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2695 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2697 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2698 return MCDisassembler::Fail;
2699 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
2700 return MCDisassembler::Fail;
2705 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2706 uint64_t Address, const void *Decoder) {
2707 DecodeStatus S = MCDisassembler::Success;
2709 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2710 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2712 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
2713 return MCDisassembler::Fail;
2714 Inst.addOperand(MCOperand::CreateImm(imm));
2719 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2720 uint64_t Address, const void *Decoder) {
2721 unsigned imm = Val << 2;
2723 Inst.addOperand(MCOperand::CreateImm(imm));
2724 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
2726 return MCDisassembler::Success;
2729 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2730 uint64_t Address, const void *Decoder) {
2731 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2732 Inst.addOperand(MCOperand::CreateImm(Val));
2734 return MCDisassembler::Success;
2737 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2738 uint64_t Address, const void *Decoder) {
2739 DecodeStatus S = MCDisassembler::Success;
2741 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2742 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2743 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2745 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2746 return MCDisassembler::Fail;
2747 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
2748 return MCDisassembler::Fail;
2749 Inst.addOperand(MCOperand::CreateImm(imm));
2754 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2755 uint64_t Address, const void *Decoder) {
2756 DecodeStatus S = MCDisassembler::Success;
2758 switch (Inst.getOpcode()) {
2764 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2765 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
2766 return MCDisassembler::Fail;
2770 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2772 switch (Inst.getOpcode()) {
2774 Inst.setOpcode(ARM::t2LDRBpci);
2777 Inst.setOpcode(ARM::t2LDRHpci);
2780 Inst.setOpcode(ARM::t2LDRSHpci);
2783 Inst.setOpcode(ARM::t2LDRSBpci);
2786 Inst.setOpcode(ARM::t2PLDi12);
2787 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2790 return MCDisassembler::Fail;
2793 int imm = fieldFromInstruction32(Insn, 0, 12);
2794 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2795 Inst.addOperand(MCOperand::CreateImm(imm));
2800 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2801 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2802 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2803 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
2804 return MCDisassembler::Fail;
2809 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2810 uint64_t Address, const void *Decoder) {
2811 int imm = Val & 0xFF;
2812 if (!(Val & 0x100)) imm *= -1;
2813 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2815 return MCDisassembler::Success;
2818 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2819 uint64_t Address, const void *Decoder) {
2820 DecodeStatus S = MCDisassembler::Success;
2822 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2823 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2825 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2826 return MCDisassembler::Fail;
2827 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
2828 return MCDisassembler::Fail;
2833 static DecodeStatus DecodeT2AddrModeImm0_1020s4(llvm::MCInst &Inst,unsigned Val,
2834 uint64_t Address, const void *Decoder) {
2835 DecodeStatus S = MCDisassembler::Success;
2837 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
2838 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2840 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2841 return MCDisassembler::Fail;
2843 Inst.addOperand(MCOperand::CreateImm(imm));
2848 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2849 uint64_t Address, const void *Decoder) {
2850 int imm = Val & 0xFF;
2853 else if (!(Val & 0x100))
2855 Inst.addOperand(MCOperand::CreateImm(imm));
2857 return MCDisassembler::Success;
2861 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2862 uint64_t Address, const void *Decoder) {
2863 DecodeStatus S = MCDisassembler::Success;
2865 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2866 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2868 // Some instructions always use an additive offset.
2869 switch (Inst.getOpcode()) {
2884 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2885 return MCDisassembler::Fail;
2886 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
2887 return MCDisassembler::Fail;
2892 static DecodeStatus DecodeT2LdStPre(llvm::MCInst &Inst, unsigned Insn,
2893 uint64_t Address, const void *Decoder) {
2894 DecodeStatus S = MCDisassembler::Success;
2896 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2897 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2898 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
2899 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
2901 unsigned load = fieldFromInstruction32(Insn, 20, 1);
2904 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2905 return MCDisassembler::Fail;
2908 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
2909 return MCDisassembler::Fail;
2912 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2913 return MCDisassembler::Fail;
2916 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
2917 return MCDisassembler::Fail;
2922 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2923 uint64_t Address, const void *Decoder) {
2924 DecodeStatus S = MCDisassembler::Success;
2926 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2927 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2930 return MCDisassembler::Fail;
2931 Inst.addOperand(MCOperand::CreateImm(imm));
2937 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2938 uint64_t Address, const void *Decoder) {
2939 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2941 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2942 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2943 Inst.addOperand(MCOperand::CreateImm(imm));
2945 return MCDisassembler::Success;
2948 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
2949 uint64_t Address, const void *Decoder) {
2950 DecodeStatus S = MCDisassembler::Success;
2952 if (Inst.getOpcode() == ARM::tADDrSP) {
2953 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2954 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2957 return MCDisassembler::Fail;
2958 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
2959 return MCDisassembler::Fail;
2960 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2961 } else if (Inst.getOpcode() == ARM::tADDspr) {
2962 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2964 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2965 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2967 return MCDisassembler::Fail;
2973 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
2974 uint64_t Address, const void *Decoder) {
2975 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2976 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2978 Inst.addOperand(MCOperand::CreateImm(imod));
2979 Inst.addOperand(MCOperand::CreateImm(flags));
2981 return MCDisassembler::Success;
2984 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
2985 uint64_t Address, const void *Decoder) {
2986 DecodeStatus S = MCDisassembler::Success;
2987 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2988 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2991 return MCDisassembler::Fail;
2992 Inst.addOperand(MCOperand::CreateImm(add));
2997 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
2998 uint64_t Address, const void *Decoder) {
2999 if (!tryAddingSymbolicOperand(Address,
3000 (Address & ~2u) + SignExtend32<22>(Val << 1) + 4,
3001 true, 4, Inst, Decoder))
3002 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3003 return MCDisassembler::Success;
3006 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
3007 uint64_t Address, const void *Decoder) {
3008 if (Val == 0xA || Val == 0xB)
3009 return MCDisassembler::Fail;
3011 Inst.addOperand(MCOperand::CreateImm(Val));
3012 return MCDisassembler::Success;
3016 DecodeThumbTableBranch(llvm::MCInst &Inst, unsigned Insn,
3017 uint64_t Address, const void *Decoder) {
3018 DecodeStatus S = MCDisassembler::Success;
3020 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3021 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3023 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3024 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3025 return MCDisassembler::Fail;
3026 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3027 return MCDisassembler::Fail;
3032 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
3033 uint64_t Address, const void *Decoder) {
3034 DecodeStatus S = MCDisassembler::Success;
3036 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3037 if (pred == 0xE || pred == 0xF) {
3038 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
3041 return MCDisassembler::Fail;
3043 Inst.setOpcode(ARM::t2DSB);
3046 Inst.setOpcode(ARM::t2DMB);
3049 Inst.setOpcode(ARM::t2ISB);
3053 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
3054 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3057 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3058 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3059 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3060 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3061 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3063 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3064 return MCDisassembler::Fail;
3065 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3066 return MCDisassembler::Fail;
3071 // Decode a shifted immediate operand. These basically consist
3072 // of an 8-bit value, and a 4-bit directive that specifies either
3073 // a splat operation or a rotation.
3074 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
3075 uint64_t Address, const void *Decoder) {
3076 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3078 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3079 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3082 Inst.addOperand(MCOperand::CreateImm(imm));
3085 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3088 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3091 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3096 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3097 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3098 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3099 Inst.addOperand(MCOperand::CreateImm(imm));
3102 return MCDisassembler::Success;
3106 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
3107 uint64_t Address, const void *Decoder){
3108 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3109 return MCDisassembler::Success;
3112 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
3113 uint64_t Address, const void *Decoder){
3114 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
3115 return MCDisassembler::Success;
3118 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
3119 uint64_t Address, const void *Decoder) {
3122 return MCDisassembler::Fail;
3134 Inst.addOperand(MCOperand::CreateImm(Val));
3135 return MCDisassembler::Success;
3138 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
3139 uint64_t Address, const void *Decoder) {
3140 if (!Val) return MCDisassembler::Fail;
3141 Inst.addOperand(MCOperand::CreateImm(Val));
3142 return MCDisassembler::Success;
3145 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
3146 uint64_t Address, const void *Decoder) {
3147 DecodeStatus S = MCDisassembler::Success;
3149 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3150 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3151 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3153 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3155 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3156 return MCDisassembler::Fail;
3157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3158 return MCDisassembler::Fail;
3159 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3160 return MCDisassembler::Fail;
3161 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3162 return MCDisassembler::Fail;
3168 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
3169 uint64_t Address, const void *Decoder){
3170 DecodeStatus S = MCDisassembler::Success;
3172 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3173 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3174 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3175 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3177 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
3178 return MCDisassembler::Fail;
3180 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
3181 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return MCDisassembler::Fail;
3183 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3184 return MCDisassembler::Fail;
3185 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
3186 return MCDisassembler::Fail;
3187 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3188 return MCDisassembler::Fail;
3189 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3190 return MCDisassembler::Fail;
3195 static DecodeStatus DecodeLDRPreImm(llvm::MCInst &Inst, unsigned Insn,
3196 uint64_t Address, const void *Decoder) {
3197 DecodeStatus S = MCDisassembler::Success;
3199 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3200 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3201 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3202 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3203 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3204 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3206 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3208 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3209 return MCDisassembler::Fail;
3210 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3211 return MCDisassembler::Fail;
3212 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3213 return MCDisassembler::Fail;
3214 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3215 return MCDisassembler::Fail;
3220 static DecodeStatus DecodeLDRPreReg(llvm::MCInst &Inst, unsigned Insn,
3221 uint64_t Address, const void *Decoder) {
3222 DecodeStatus S = MCDisassembler::Success;
3224 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3225 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3226 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3227 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3228 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3229 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3230 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3232 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3233 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3235 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3236 return MCDisassembler::Fail;
3237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3238 return MCDisassembler::Fail;
3239 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3240 return MCDisassembler::Fail;
3241 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3242 return MCDisassembler::Fail;
3248 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
3249 uint64_t Address, const void *Decoder) {
3250 DecodeStatus S = MCDisassembler::Success;
3252 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3253 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3254 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3255 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3256 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3257 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3259 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3262 return MCDisassembler::Fail;
3263 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3264 return MCDisassembler::Fail;
3265 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3266 return MCDisassembler::Fail;
3267 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3268 return MCDisassembler::Fail;
3273 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
3274 uint64_t Address, const void *Decoder) {
3275 DecodeStatus S = MCDisassembler::Success;
3277 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3278 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3279 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3280 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3281 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3282 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3284 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3286 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3287 return MCDisassembler::Fail;
3288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3289 return MCDisassembler::Fail;
3290 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3291 return MCDisassembler::Fail;
3292 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3293 return MCDisassembler::Fail;
3298 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
3299 uint64_t Address, const void *Decoder) {
3300 DecodeStatus S = MCDisassembler::Success;
3302 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3303 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3304 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3305 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3306 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3312 return MCDisassembler::Fail;
3314 if (fieldFromInstruction32(Insn, 4, 1))
3315 return MCDisassembler::Fail; // UNDEFINED
3316 index = fieldFromInstruction32(Insn, 5, 3);
3319 if (fieldFromInstruction32(Insn, 5, 1))
3320 return MCDisassembler::Fail; // UNDEFINED
3321 index = fieldFromInstruction32(Insn, 6, 2);
3322 if (fieldFromInstruction32(Insn, 4, 1))
3326 if (fieldFromInstruction32(Insn, 6, 1))
3327 return MCDisassembler::Fail; // UNDEFINED
3328 index = fieldFromInstruction32(Insn, 7, 1);
3329 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3333 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3334 return MCDisassembler::Fail;
3335 if (Rm != 0xF) { // Writeback
3336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3337 return MCDisassembler::Fail;
3339 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3340 return MCDisassembler::Fail;
3341 Inst.addOperand(MCOperand::CreateImm(align));
3344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3345 return MCDisassembler::Fail;
3347 Inst.addOperand(MCOperand::CreateReg(0));
3350 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3351 return MCDisassembler::Fail;
3352 Inst.addOperand(MCOperand::CreateImm(index));
3357 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
3358 uint64_t Address, const void *Decoder) {
3359 DecodeStatus S = MCDisassembler::Success;
3361 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3362 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3363 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3364 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3365 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3371 return MCDisassembler::Fail;
3373 if (fieldFromInstruction32(Insn, 4, 1))
3374 return MCDisassembler::Fail; // UNDEFINED
3375 index = fieldFromInstruction32(Insn, 5, 3);
3378 if (fieldFromInstruction32(Insn, 5, 1))
3379 return MCDisassembler::Fail; // UNDEFINED
3380 index = fieldFromInstruction32(Insn, 6, 2);
3381 if (fieldFromInstruction32(Insn, 4, 1))
3385 if (fieldFromInstruction32(Insn, 6, 1))
3386 return MCDisassembler::Fail; // UNDEFINED
3387 index = fieldFromInstruction32(Insn, 7, 1);
3388 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3392 if (Rm != 0xF) { // Writeback
3393 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3394 return MCDisassembler::Fail;
3396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3397 return MCDisassembler::Fail;
3398 Inst.addOperand(MCOperand::CreateImm(align));
3401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3402 return MCDisassembler::Fail;
3404 Inst.addOperand(MCOperand::CreateReg(0));
3407 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3408 return MCDisassembler::Fail;
3409 Inst.addOperand(MCOperand::CreateImm(index));
3415 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
3416 uint64_t Address, const void *Decoder) {
3417 DecodeStatus S = MCDisassembler::Success;
3419 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3420 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3421 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3422 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3423 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3430 return MCDisassembler::Fail;
3432 index = fieldFromInstruction32(Insn, 5, 3);
3433 if (fieldFromInstruction32(Insn, 4, 1))
3437 index = fieldFromInstruction32(Insn, 6, 2);
3438 if (fieldFromInstruction32(Insn, 4, 1))
3440 if (fieldFromInstruction32(Insn, 5, 1))
3444 if (fieldFromInstruction32(Insn, 5, 1))
3445 return MCDisassembler::Fail; // UNDEFINED
3446 index = fieldFromInstruction32(Insn, 7, 1);
3447 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3449 if (fieldFromInstruction32(Insn, 6, 1))
3454 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3455 return MCDisassembler::Fail;
3456 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3457 return MCDisassembler::Fail;
3458 if (Rm != 0xF) { // Writeback
3459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3460 return MCDisassembler::Fail;
3462 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3463 return MCDisassembler::Fail;
3464 Inst.addOperand(MCOperand::CreateImm(align));
3467 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3468 return MCDisassembler::Fail;
3470 Inst.addOperand(MCOperand::CreateReg(0));
3473 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3474 return MCDisassembler::Fail;
3475 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3476 return MCDisassembler::Fail;
3477 Inst.addOperand(MCOperand::CreateImm(index));
3482 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
3483 uint64_t Address, const void *Decoder) {
3484 DecodeStatus S = MCDisassembler::Success;
3486 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3487 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3488 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3489 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3490 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3497 return MCDisassembler::Fail;
3499 index = fieldFromInstruction32(Insn, 5, 3);
3500 if (fieldFromInstruction32(Insn, 4, 1))
3504 index = fieldFromInstruction32(Insn, 6, 2);
3505 if (fieldFromInstruction32(Insn, 4, 1))
3507 if (fieldFromInstruction32(Insn, 5, 1))
3511 if (fieldFromInstruction32(Insn, 5, 1))
3512 return MCDisassembler::Fail; // UNDEFINED
3513 index = fieldFromInstruction32(Insn, 7, 1);
3514 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3516 if (fieldFromInstruction32(Insn, 6, 1))
3521 if (Rm != 0xF) { // Writeback
3522 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3523 return MCDisassembler::Fail;
3525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3526 return MCDisassembler::Fail;
3527 Inst.addOperand(MCOperand::CreateImm(align));
3530 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3531 return MCDisassembler::Fail;
3533 Inst.addOperand(MCOperand::CreateReg(0));
3536 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3537 return MCDisassembler::Fail;
3538 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3539 return MCDisassembler::Fail;
3540 Inst.addOperand(MCOperand::CreateImm(index));
3546 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3547 uint64_t Address, const void *Decoder) {
3548 DecodeStatus S = MCDisassembler::Success;
3550 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3551 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3552 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3553 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3554 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3561 return MCDisassembler::Fail;
3563 if (fieldFromInstruction32(Insn, 4, 1))
3564 return MCDisassembler::Fail; // UNDEFINED
3565 index = fieldFromInstruction32(Insn, 5, 3);
3568 if (fieldFromInstruction32(Insn, 4, 1))
3569 return MCDisassembler::Fail; // UNDEFINED
3570 index = fieldFromInstruction32(Insn, 6, 2);
3571 if (fieldFromInstruction32(Insn, 5, 1))
3575 if (fieldFromInstruction32(Insn, 4, 2))
3576 return MCDisassembler::Fail; // UNDEFINED
3577 index = fieldFromInstruction32(Insn, 7, 1);
3578 if (fieldFromInstruction32(Insn, 6, 1))
3583 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3584 return MCDisassembler::Fail;
3585 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3586 return MCDisassembler::Fail;
3587 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3588 return MCDisassembler::Fail;
3590 if (Rm != 0xF) { // Writeback
3591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3592 return MCDisassembler::Fail;
3594 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3595 return MCDisassembler::Fail;
3596 Inst.addOperand(MCOperand::CreateImm(align));
3599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3600 return MCDisassembler::Fail;
3602 Inst.addOperand(MCOperand::CreateReg(0));
3605 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3606 return MCDisassembler::Fail;
3607 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3608 return MCDisassembler::Fail;
3609 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3610 return MCDisassembler::Fail;
3611 Inst.addOperand(MCOperand::CreateImm(index));
3616 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3617 uint64_t Address, const void *Decoder) {
3618 DecodeStatus S = MCDisassembler::Success;
3620 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3621 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3622 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3623 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3624 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3631 return MCDisassembler::Fail;
3633 if (fieldFromInstruction32(Insn, 4, 1))
3634 return MCDisassembler::Fail; // UNDEFINED
3635 index = fieldFromInstruction32(Insn, 5, 3);
3638 if (fieldFromInstruction32(Insn, 4, 1))
3639 return MCDisassembler::Fail; // UNDEFINED
3640 index = fieldFromInstruction32(Insn, 6, 2);
3641 if (fieldFromInstruction32(Insn, 5, 1))
3645 if (fieldFromInstruction32(Insn, 4, 2))
3646 return MCDisassembler::Fail; // UNDEFINED
3647 index = fieldFromInstruction32(Insn, 7, 1);
3648 if (fieldFromInstruction32(Insn, 6, 1))
3653 if (Rm != 0xF) { // Writeback
3654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3655 return MCDisassembler::Fail;
3657 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3658 return MCDisassembler::Fail;
3659 Inst.addOperand(MCOperand::CreateImm(align));
3662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3663 return MCDisassembler::Fail;
3665 Inst.addOperand(MCOperand::CreateReg(0));
3668 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3669 return MCDisassembler::Fail;
3670 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3671 return MCDisassembler::Fail;
3672 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3673 return MCDisassembler::Fail;
3674 Inst.addOperand(MCOperand::CreateImm(index));
3680 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3681 uint64_t Address, const void *Decoder) {
3682 DecodeStatus S = MCDisassembler::Success;
3684 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3685 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3686 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3687 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3688 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3695 return MCDisassembler::Fail;
3697 if (fieldFromInstruction32(Insn, 4, 1))
3699 index = fieldFromInstruction32(Insn, 5, 3);
3702 if (fieldFromInstruction32(Insn, 4, 1))
3704 index = fieldFromInstruction32(Insn, 6, 2);
3705 if (fieldFromInstruction32(Insn, 5, 1))
3709 if (fieldFromInstruction32(Insn, 4, 2))
3710 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3711 index = fieldFromInstruction32(Insn, 7, 1);
3712 if (fieldFromInstruction32(Insn, 6, 1))
3717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3718 return MCDisassembler::Fail;
3719 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3720 return MCDisassembler::Fail;
3721 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3722 return MCDisassembler::Fail;
3723 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3724 return MCDisassembler::Fail;
3726 if (Rm != 0xF) { // Writeback
3727 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3728 return MCDisassembler::Fail;
3730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3731 return MCDisassembler::Fail;
3732 Inst.addOperand(MCOperand::CreateImm(align));
3735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3736 return MCDisassembler::Fail;
3738 Inst.addOperand(MCOperand::CreateReg(0));
3741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3742 return MCDisassembler::Fail;
3743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3744 return MCDisassembler::Fail;
3745 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3746 return MCDisassembler::Fail;
3747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3748 return MCDisassembler::Fail;
3749 Inst.addOperand(MCOperand::CreateImm(index));
3754 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3755 uint64_t Address, const void *Decoder) {
3756 DecodeStatus S = MCDisassembler::Success;
3758 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3759 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3760 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3761 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3762 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3769 return MCDisassembler::Fail;
3771 if (fieldFromInstruction32(Insn, 4, 1))
3773 index = fieldFromInstruction32(Insn, 5, 3);
3776 if (fieldFromInstruction32(Insn, 4, 1))
3778 index = fieldFromInstruction32(Insn, 6, 2);
3779 if (fieldFromInstruction32(Insn, 5, 1))
3783 if (fieldFromInstruction32(Insn, 4, 2))
3784 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3785 index = fieldFromInstruction32(Insn, 7, 1);
3786 if (fieldFromInstruction32(Insn, 6, 1))
3791 if (Rm != 0xF) { // Writeback
3792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3793 return MCDisassembler::Fail;
3795 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3796 return MCDisassembler::Fail;
3797 Inst.addOperand(MCOperand::CreateImm(align));
3800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3801 return MCDisassembler::Fail;
3803 Inst.addOperand(MCOperand::CreateReg(0));
3806 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3807 return MCDisassembler::Fail;
3808 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
3809 return MCDisassembler::Fail;
3810 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
3811 return MCDisassembler::Fail;
3812 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
3813 return MCDisassembler::Fail;
3814 Inst.addOperand(MCOperand::CreateImm(index));
3819 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3820 uint64_t Address, const void *Decoder) {
3821 DecodeStatus S = MCDisassembler::Success;
3822 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3823 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3824 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3825 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3826 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3828 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3829 S = MCDisassembler::SoftFail;
3831 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3832 return MCDisassembler::Fail;
3833 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3834 return MCDisassembler::Fail;
3835 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3836 return MCDisassembler::Fail;
3837 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3838 return MCDisassembler::Fail;
3839 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3840 return MCDisassembler::Fail;
3845 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
3846 uint64_t Address, const void *Decoder) {
3847 DecodeStatus S = MCDisassembler::Success;
3848 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3849 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3850 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3851 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3852 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3854 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3855 S = MCDisassembler::SoftFail;
3857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
3858 return MCDisassembler::Fail;
3859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
3860 return MCDisassembler::Fail;
3861 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
3862 return MCDisassembler::Fail;
3863 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
3864 return MCDisassembler::Fail;
3865 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3866 return MCDisassembler::Fail;
3871 static DecodeStatus DecodeIT(llvm::MCInst &Inst, unsigned Insn,
3872 uint64_t Address, const void *Decoder) {
3873 DecodeStatus S = MCDisassembler::Success;
3874 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
3875 // The InstPrinter needs to have the low bit of the predicate in
3876 // the mask operand to be able to print it properly.
3877 unsigned mask = fieldFromInstruction16(Insn, 0, 5);
3881 S = MCDisassembler::SoftFail;
3884 if ((mask & 0xF) == 0) {
3885 // Preserve the high bit of the mask, which is the low bit of
3889 S = MCDisassembler::SoftFail;
3892 Inst.addOperand(MCOperand::CreateImm(pred));
3893 Inst.addOperand(MCOperand::CreateImm(mask));
3898 DecodeT2LDRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3899 uint64_t Address, const void *Decoder) {
3900 DecodeStatus S = MCDisassembler::Success;
3902 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3903 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3904 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3905 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3906 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3907 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3908 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3909 bool writeback = (W == 1) | (P == 0);
3911 addr |= (U << 8) | (Rn << 9);
3913 if (writeback && (Rn == Rt || Rn == Rt2))
3914 Check(S, MCDisassembler::SoftFail);
3916 Check(S, MCDisassembler::SoftFail);
3919 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3920 return MCDisassembler::Fail;
3922 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3923 return MCDisassembler::Fail;
3924 // Writeback operand
3925 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3926 return MCDisassembler::Fail;
3928 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3929 return MCDisassembler::Fail;
3935 DecodeT2STRDPreInstruction(llvm::MCInst &Inst, unsigned Insn,
3936 uint64_t Address, const void *Decoder) {
3937 DecodeStatus S = MCDisassembler::Success;
3939 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3940 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
3941 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3942 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3943 unsigned W = fieldFromInstruction32(Insn, 21, 1);
3944 unsigned U = fieldFromInstruction32(Insn, 23, 1);
3945 unsigned P = fieldFromInstruction32(Insn, 24, 1);
3946 bool writeback = (W == 1) | (P == 0);
3948 addr |= (U << 8) | (Rn << 9);
3950 if (writeback && (Rn == Rt || Rn == Rt2))
3951 Check(S, MCDisassembler::SoftFail);
3953 // Writeback operand
3954 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
3955 return MCDisassembler::Fail;
3957 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3958 return MCDisassembler::Fail;
3960 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
3961 return MCDisassembler::Fail;
3963 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
3964 return MCDisassembler::Fail;
3969 static DecodeStatus DecodeT2Adr(llvm::MCInst &Inst, uint32_t Insn,
3970 uint64_t Address, const void *Decoder) {
3971 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
3972 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
3973 if (sign1 != sign2) return MCDisassembler::Fail;
3975 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
3976 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
3977 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
3979 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
3981 return MCDisassembler::Success;
3984 static DecodeStatus DecodeT2ShifterImmOperand(llvm::MCInst &Inst, uint32_t Val,
3986 const void *Decoder) {
3987 DecodeStatus S = MCDisassembler::Success;
3989 // Shift of "asr #32" is not allowed in Thumb2 mode.
3990 if (Val == 0x20) S = MCDisassembler::SoftFail;
3991 Inst.addOperand(MCOperand::CreateImm(Val));