1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "arm-disassembler"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 // Handles the condition code status of instructions in IT blocks
38 // Returns the condition code for instruction in IT block
40 unsigned CC = ARMCC::AL;
46 // Advances the IT block state to the next T or E
47 void advanceITState() {
51 // Returns true if the current instruction is in an IT block
52 bool instrInITBlock() {
53 return !ITStates.empty();
56 // Returns true if current instruction is the last instruction in an IT block
57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
61 // Called when decoding an IT instruction. Sets the IT state for the following
62 // instructions that for the IT block. Firstcond and Mask correspond to the
63 // fields in the IT instruction encoding.
64 void setITState(char Firstcond, char Mask) {
65 // (3 - the number of trailing zeros) is the number of then / else.
66 unsigned CondBit0 = Firstcond & 1;
67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 && "Invalid IT mask!");
70 // push condition codes onto the stack the correct order for the pops
71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 ITStates.push_back(CCBits);
76 ITStates.push_back(CCBits ^ 1);
78 ITStates.push_back(CCBits);
82 std::vector<unsigned char> ITStates;
87 /// ARM disassembler for all ARM platforms.
88 class ARMDisassembler : public MCDisassembler {
90 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
91 MCDisassembler(STI, Ctx) {
94 ~ARMDisassembler() override {}
96 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
97 ArrayRef<uint8_t> Bytes, uint64_t Address,
99 raw_ostream &CStream) const override;
102 /// Thumb disassembler for all Thumb platforms.
103 class ThumbDisassembler : public MCDisassembler {
105 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
106 MCDisassembler(STI, Ctx) {
109 ~ThumbDisassembler() override {}
111 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
112 ArrayRef<uint8_t> Bytes, uint64_t Address,
113 raw_ostream &VStream,
114 raw_ostream &CStream) const override;
117 mutable ITStatus ITBlock;
118 DecodeStatus AddThumbPredicate(MCInst&) const;
119 void UpdateThumbVFPPredicate(MCInst&) const;
123 static bool Check(DecodeStatus &Out, DecodeStatus In) {
125 case MCDisassembler::Success:
126 // Out stays the same.
128 case MCDisassembler::SoftFail:
131 case MCDisassembler::Fail:
135 llvm_unreachable("Invalid DecodeStatus!");
139 // Forward declare these because the autogenerated code will reference them.
140 // Definitions are further down.
141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
142 uint64_t Address, const void *Decoder);
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
144 unsigned RegNo, uint64_t Address,
145 const void *Decoder);
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
147 unsigned RegNo, uint64_t Address,
148 const void *Decoder);
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address, const void *Decoder);
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
152 uint64_t Address, const void *Decoder);
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address, const void *Decoder);
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
158 uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
166 const void *Decoder);
167 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
168 uint64_t Address, const void *Decoder);
169 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
170 uint64_t Address, const void *Decoder);
171 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
172 unsigned RegNo, uint64_t Address,
173 const void *Decoder);
175 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
176 uint64_t Address, const void *Decoder);
177 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
178 uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
180 uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
182 uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
184 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
193 const void *Decoder);
194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
201 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
206 const void *Decoder);
207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
236 uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
238 uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
240 uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
242 uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
250 uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
252 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
260 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
262 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
312 uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
314 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
316 uint64_t Address, const void *Decoder);
317 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
318 uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
322 uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
324 uint64_t Address, const void *Decoder);
325 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
326 uint64_t Address, const void *Decoder);
327 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
328 uint64_t Address, const void *Decoder);
329 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
330 uint64_t Address, const void *Decoder);
331 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
332 uint64_t Address, const void *Decoder);
333 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
334 uint64_t Address, const void *Decoder);
335 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
336 uint64_t Address, const void *Decoder);
337 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
338 uint64_t Address, const void *Decoder);
339 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
340 uint64_t Address, const void *Decoder);
341 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
342 uint64_t Address, const void* Decoder);
343 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
344 uint64_t Address, const void* Decoder);
345 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
346 uint64_t Address, const void* Decoder);
347 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
348 uint64_t Address, const void* Decoder);
349 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
350 uint64_t Address, const void *Decoder);
351 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
352 uint64_t Address, const void *Decoder);
353 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
354 uint64_t Address, const void *Decoder);
355 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
356 uint64_t Address, const void *Decoder);
357 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
358 uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
360 uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
362 uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
364 uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
366 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
368 uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
370 uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
372 uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
374 uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
376 uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
378 uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
380 uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
382 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
384 uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
386 uint64_t Address, const void *Decoder);
387 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
388 uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
390 uint64_t Address, const void *Decoder);
391 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
392 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
395 uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
397 uint64_t Address, const void *Decoder);
398 #include "ARMGenDisassemblerTables.inc"
400 static MCDisassembler *createARMDisassembler(const Target &T,
401 const MCSubtargetInfo &STI,
403 return new ARMDisassembler(STI, Ctx);
406 static MCDisassembler *createThumbDisassembler(const Target &T,
407 const MCSubtargetInfo &STI,
409 return new ThumbDisassembler(STI, Ctx);
412 // Post-decoding checks
413 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
414 uint64_t Address, raw_ostream &OS,
419 switch (MI.getOpcode()) {
421 // HVC is undefined if condition = 0xf otherwise upredictable
422 // if condition != 0xe
423 uint32_t Cond = (Insn >> 28) & 0xF;
425 return MCDisassembler::Fail;
427 return MCDisassembler::SoftFail;
430 default: return Result;
434 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
435 ArrayRef<uint8_t> Bytes,
436 uint64_t Address, raw_ostream &OS,
437 raw_ostream &CS) const {
440 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
441 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
444 // We want to read exactly 4 bytes of data.
445 if (Bytes.size() < 4) {
447 return MCDisassembler::Fail;
450 // Encoded as a small-endian 32-bit word in the stream.
452 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
454 // Calling the auto-generated decoder function.
455 DecodeStatus Result =
456 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
457 if (Result != MCDisassembler::Fail) {
459 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
462 // VFP and NEON instructions, similarly, are shared between ARM
464 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
465 if (Result != MCDisassembler::Fail) {
470 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
471 if (Result != MCDisassembler::Fail) {
477 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
478 if (Result != MCDisassembler::Fail) {
480 // Add a fake predicate operand, because we share these instruction
481 // definitions with Thumb2 where these instructions are predicable.
482 if (!DecodePredicateOperand(MI, 0xE, Address, this))
483 return MCDisassembler::Fail;
487 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
489 if (Result != MCDisassembler::Fail) {
491 // Add a fake predicate operand, because we share these instruction
492 // definitions with Thumb2 where these instructions are predicable.
493 if (!DecodePredicateOperand(MI, 0xE, Address, this))
494 return MCDisassembler::Fail;
499 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
500 if (Result != MCDisassembler::Fail) {
502 // Add a fake predicate operand, because we share these instruction
503 // definitions with Thumb2 where these instructions are predicable.
504 if (!DecodePredicateOperand(MI, 0xE, Address, this))
505 return MCDisassembler::Fail;
510 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
511 if (Result != MCDisassembler::Fail) {
517 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
518 if (Result != MCDisassembler::Fail) {
524 return MCDisassembler::Fail;
528 extern const MCInstrDesc ARMInsts[];
531 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
532 /// immediate Value in the MCInst. The immediate Value has had any PC
533 /// adjustment made by the caller. If the instruction is a branch instruction
534 /// then isBranch is true, else false. If the getOpInfo() function was set as
535 /// part of the setupForSymbolicDisassembly() call then that function is called
536 /// to get any symbolic information at the Address for this instruction. If
537 /// that returns non-zero then the symbolic information it returns is used to
538 /// create an MCExpr and that is added as an operand to the MCInst. If
539 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
540 /// Value is done and if a symbol is found an MCExpr is created with that, else
541 /// an MCExpr with Value is created. This function returns true if it adds an
542 /// operand to the MCInst and false otherwise.
543 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
544 bool isBranch, uint64_t InstSize,
545 MCInst &MI, const void *Decoder) {
546 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
547 // FIXME: Does it make sense for value to be negative?
548 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
549 /* Offset */ 0, InstSize);
552 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
553 /// referenced by a load instruction with the base register that is the Pc.
554 /// These can often be values in a literal pool near the Address of the
555 /// instruction. The Address of the instruction and its immediate Value are
556 /// used as a possible literal pool entry. The SymbolLookUp call back will
557 /// return the name of a symbol referenced by the literal pool's entry if
558 /// the referenced address is that of a symbol. Or it will return a pointer to
559 /// a literal 'C' string if the referenced address of the literal pool's entry
560 /// is an address into a section with 'C' string literals.
561 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
562 const void *Decoder) {
563 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
564 Dis->tryAddingPcLoadReferenceComment(Value, Address);
567 // Thumb1 instructions don't have explicit S bits. Rather, they
568 // implicitly set CPSR. Since it's not represented in the encoding, the
569 // auto-generated decoder won't inject the CPSR operand. We need to fix
570 // that as a post-pass.
571 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
572 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
573 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
574 MCInst::iterator I = MI.begin();
575 for (unsigned i = 0; i < NumOps; ++i, ++I) {
576 if (I == MI.end()) break;
577 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
578 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
579 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
584 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
587 // Most Thumb instructions don't have explicit predicates in the
588 // encoding, but rather get their predicates from IT context. We need
589 // to fix up the predicate operands using this context information as a
591 MCDisassembler::DecodeStatus
592 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
593 MCDisassembler::DecodeStatus S = Success;
595 // A few instructions actually have predicates encoded in them. Don't
596 // try to overwrite it if we're seeing one of those.
597 switch (MI.getOpcode()) {
608 // Some instructions (mostly conditional branches) are not
609 // allowed in IT blocks.
610 if (ITBlock.instrInITBlock())
619 // Some instructions (mostly unconditional branches) can
620 // only appears at the end of, or outside of, an IT.
621 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
628 // If we're in an IT block, base the predicate on that. Otherwise,
629 // assume a predicate of AL.
631 CC = ITBlock.getITCC();
634 if (ITBlock.instrInITBlock())
635 ITBlock.advanceITState();
637 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
638 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
639 MCInst::iterator I = MI.begin();
640 for (unsigned i = 0; i < NumOps; ++i, ++I) {
641 if (I == MI.end()) break;
642 if (OpInfo[i].isPredicate()) {
643 I = MI.insert(I, MCOperand::createImm(CC));
646 MI.insert(I, MCOperand::createReg(0));
648 MI.insert(I, MCOperand::createReg(ARM::CPSR));
653 I = MI.insert(I, MCOperand::createImm(CC));
656 MI.insert(I, MCOperand::createReg(0));
658 MI.insert(I, MCOperand::createReg(ARM::CPSR));
663 // Thumb VFP instructions are a special case. Because we share their
664 // encodings between ARM and Thumb modes, and they are predicable in ARM
665 // mode, the auto-generated decoder will give them an (incorrect)
666 // predicate operand. We need to rewrite these operands based on the IT
667 // context as a post-pass.
668 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
670 CC = ITBlock.getITCC();
671 if (ITBlock.instrInITBlock())
672 ITBlock.advanceITState();
674 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
675 MCInst::iterator I = MI.begin();
676 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
677 for (unsigned i = 0; i < NumOps; ++i, ++I) {
678 if (OpInfo[i].isPredicate() ) {
684 I->setReg(ARM::CPSR);
690 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
691 ArrayRef<uint8_t> Bytes,
694 raw_ostream &CS) const {
697 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
698 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
700 // We want to read exactly 2 bytes of data.
701 if (Bytes.size() < 2) {
703 return MCDisassembler::Fail;
706 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
707 DecodeStatus Result =
708 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
709 if (Result != MCDisassembler::Fail) {
711 Check(Result, AddThumbPredicate(MI));
715 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
719 bool InITBlock = ITBlock.instrInITBlock();
720 Check(Result, AddThumbPredicate(MI));
721 AddThumb1SBit(MI, InITBlock);
726 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
727 if (Result != MCDisassembler::Fail) {
730 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
731 // the Thumb predicate.
732 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
733 Result = MCDisassembler::SoftFail;
735 Check(Result, AddThumbPredicate(MI));
737 // If we find an IT instruction, we need to parse its condition
738 // code and mask operands so that we can apply them correctly
739 // to the subsequent instructions.
740 if (MI.getOpcode() == ARM::t2IT) {
742 unsigned Firstcond = MI.getOperand(0).getImm();
743 unsigned Mask = MI.getOperand(1).getImm();
744 ITBlock.setITState(Firstcond, Mask);
750 // We want to read exactly 4 bytes of data.
751 if (Bytes.size() < 4) {
753 return MCDisassembler::Fail;
757 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
759 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
760 if (Result != MCDisassembler::Fail) {
762 bool InITBlock = ITBlock.instrInITBlock();
763 Check(Result, AddThumbPredicate(MI));
764 AddThumb1SBit(MI, InITBlock);
769 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
770 if (Result != MCDisassembler::Fail) {
772 Check(Result, AddThumbPredicate(MI));
776 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
778 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
779 if (Result != MCDisassembler::Fail) {
781 UpdateThumbVFPPredicate(MI);
787 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
788 if (Result != MCDisassembler::Fail) {
793 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
794 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
796 if (Result != MCDisassembler::Fail) {
798 Check(Result, AddThumbPredicate(MI));
803 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
804 uint32_t NEONLdStInsn = Insn32;
805 NEONLdStInsn &= 0xF0FFFFFF;
806 NEONLdStInsn |= 0x04000000;
807 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
809 if (Result != MCDisassembler::Fail) {
811 Check(Result, AddThumbPredicate(MI));
816 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
817 uint32_t NEONDataInsn = Insn32;
818 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
819 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
820 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
821 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
823 if (Result != MCDisassembler::Fail) {
825 Check(Result, AddThumbPredicate(MI));
829 uint32_t NEONCryptoInsn = Insn32;
830 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
831 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
832 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
833 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
835 if (Result != MCDisassembler::Fail) {
840 uint32_t NEONv8Insn = Insn32;
841 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
842 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
844 if (Result != MCDisassembler::Fail) {
851 return MCDisassembler::Fail;
855 extern "C" void LLVMInitializeARMDisassembler() {
856 TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
857 createARMDisassembler);
858 TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
859 createARMDisassembler);
860 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
861 createThumbDisassembler);
862 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
863 createThumbDisassembler);
866 static const uint16_t GPRDecoderTable[] = {
867 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
868 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
869 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
870 ARM::R12, ARM::SP, ARM::LR, ARM::PC
873 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
874 uint64_t Address, const void *Decoder) {
876 return MCDisassembler::Fail;
878 unsigned Register = GPRDecoderTable[RegNo];
879 Inst.addOperand(MCOperand::createReg(Register));
880 return MCDisassembler::Success;
884 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
885 uint64_t Address, const void *Decoder) {
886 DecodeStatus S = MCDisassembler::Success;
889 S = MCDisassembler::SoftFail;
891 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
897 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
898 uint64_t Address, const void *Decoder) {
899 DecodeStatus S = MCDisassembler::Success;
903 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
904 return MCDisassembler::Success;
907 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
911 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
912 uint64_t Address, const void *Decoder) {
914 return MCDisassembler::Fail;
915 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
918 static const uint16_t GPRPairDecoderTable[] = {
919 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
920 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
923 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
924 uint64_t Address, const void *Decoder) {
925 DecodeStatus S = MCDisassembler::Success;
928 return MCDisassembler::Fail;
930 if ((RegNo & 1) || RegNo == 0xe)
931 S = MCDisassembler::SoftFail;
933 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
934 Inst.addOperand(MCOperand::createReg(RegisterPair));
938 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
939 uint64_t Address, const void *Decoder) {
940 unsigned Register = 0;
961 return MCDisassembler::Fail;
964 Inst.addOperand(MCOperand::createReg(Register));
965 return MCDisassembler::Success;
968 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
969 uint64_t Address, const void *Decoder) {
970 DecodeStatus S = MCDisassembler::Success;
972 const FeatureBitset &featureBits =
973 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
975 if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
976 S = MCDisassembler::SoftFail;
978 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
982 static const uint16_t SPRDecoderTable[] = {
983 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
984 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
985 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
986 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
987 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
988 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
989 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
990 ARM::S28, ARM::S29, ARM::S30, ARM::S31
993 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
994 uint64_t Address, const void *Decoder) {
996 return MCDisassembler::Fail;
998 unsigned Register = SPRDecoderTable[RegNo];
999 Inst.addOperand(MCOperand::createReg(Register));
1000 return MCDisassembler::Success;
1003 static const uint16_t DPRDecoderTable[] = {
1004 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1005 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1006 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1007 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1008 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1009 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1010 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1011 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1014 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1015 uint64_t Address, const void *Decoder) {
1016 const FeatureBitset &featureBits =
1017 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1019 bool hasD16 = featureBits[ARM::FeatureD16];
1021 if (RegNo > 31 || (hasD16 && RegNo > 15))
1022 return MCDisassembler::Fail;
1024 unsigned Register = DPRDecoderTable[RegNo];
1025 Inst.addOperand(MCOperand::createReg(Register));
1026 return MCDisassembler::Success;
1029 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1030 uint64_t Address, const void *Decoder) {
1032 return MCDisassembler::Fail;
1033 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1037 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1038 uint64_t Address, const void *Decoder) {
1040 return MCDisassembler::Fail;
1041 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1044 static const uint16_t QPRDecoderTable[] = {
1045 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1046 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1047 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1048 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1052 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1053 uint64_t Address, const void *Decoder) {
1054 if (RegNo > 31 || (RegNo & 1) != 0)
1055 return MCDisassembler::Fail;
1058 unsigned Register = QPRDecoderTable[RegNo];
1059 Inst.addOperand(MCOperand::createReg(Register));
1060 return MCDisassembler::Success;
1063 static const uint16_t DPairDecoderTable[] = {
1064 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1065 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1066 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1067 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1068 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1072 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1073 uint64_t Address, const void *Decoder) {
1075 return MCDisassembler::Fail;
1077 unsigned Register = DPairDecoderTable[RegNo];
1078 Inst.addOperand(MCOperand::createReg(Register));
1079 return MCDisassembler::Success;
1082 static const uint16_t DPairSpacedDecoderTable[] = {
1083 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1084 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1085 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1086 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1087 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1088 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1089 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1090 ARM::D28_D30, ARM::D29_D31
1093 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1096 const void *Decoder) {
1098 return MCDisassembler::Fail;
1100 unsigned Register = DPairSpacedDecoderTable[RegNo];
1101 Inst.addOperand(MCOperand::createReg(Register));
1102 return MCDisassembler::Success;
1105 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1106 uint64_t Address, const void *Decoder) {
1107 if (Val == 0xF) return MCDisassembler::Fail;
1108 // AL predicate is not allowed on Thumb1 branches.
1109 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1110 return MCDisassembler::Fail;
1111 Inst.addOperand(MCOperand::createImm(Val));
1112 if (Val == ARMCC::AL) {
1113 Inst.addOperand(MCOperand::createReg(0));
1115 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1116 return MCDisassembler::Success;
1119 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1120 uint64_t Address, const void *Decoder) {
1122 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1124 Inst.addOperand(MCOperand::createReg(0));
1125 return MCDisassembler::Success;
1128 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1129 uint64_t Address, const void *Decoder) {
1130 DecodeStatus S = MCDisassembler::Success;
1132 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1133 unsigned type = fieldFromInstruction(Val, 5, 2);
1134 unsigned imm = fieldFromInstruction(Val, 7, 5);
1136 // Register-immediate
1137 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1138 return MCDisassembler::Fail;
1140 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1143 Shift = ARM_AM::lsl;
1146 Shift = ARM_AM::lsr;
1149 Shift = ARM_AM::asr;
1152 Shift = ARM_AM::ror;
1156 if (Shift == ARM_AM::ror && imm == 0)
1157 Shift = ARM_AM::rrx;
1159 unsigned Op = Shift | (imm << 3);
1160 Inst.addOperand(MCOperand::createImm(Op));
1165 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1166 uint64_t Address, const void *Decoder) {
1167 DecodeStatus S = MCDisassembler::Success;
1169 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1170 unsigned type = fieldFromInstruction(Val, 5, 2);
1171 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1173 // Register-register
1174 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1175 return MCDisassembler::Fail;
1176 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1177 return MCDisassembler::Fail;
1179 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1182 Shift = ARM_AM::lsl;
1185 Shift = ARM_AM::lsr;
1188 Shift = ARM_AM::asr;
1191 Shift = ARM_AM::ror;
1195 Inst.addOperand(MCOperand::createImm(Shift));
1200 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1201 uint64_t Address, const void *Decoder) {
1202 DecodeStatus S = MCDisassembler::Success;
1204 bool NeedDisjointWriteback = false;
1205 unsigned WritebackReg = 0;
1206 switch (Inst.getOpcode()) {
1209 case ARM::LDMIA_UPD:
1210 case ARM::LDMDB_UPD:
1211 case ARM::LDMIB_UPD:
1212 case ARM::LDMDA_UPD:
1213 case ARM::t2LDMIA_UPD:
1214 case ARM::t2LDMDB_UPD:
1215 case ARM::t2STMIA_UPD:
1216 case ARM::t2STMDB_UPD:
1217 NeedDisjointWriteback = true;
1218 WritebackReg = Inst.getOperand(0).getReg();
1222 // Empty register lists are not allowed.
1223 if (Val == 0) return MCDisassembler::Fail;
1224 for (unsigned i = 0; i < 16; ++i) {
1225 if (Val & (1 << i)) {
1226 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1227 return MCDisassembler::Fail;
1228 // Writeback not allowed if Rn is in the target list.
1229 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1230 Check(S, MCDisassembler::SoftFail);
1237 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1238 uint64_t Address, const void *Decoder) {
1239 DecodeStatus S = MCDisassembler::Success;
1241 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1242 unsigned regs = fieldFromInstruction(Val, 0, 8);
1244 // In case of unpredictable encoding, tweak the operands.
1245 if (regs == 0 || (Vd + regs) > 32) {
1246 regs = Vd + regs > 32 ? 32 - Vd : regs;
1247 regs = std::max( 1u, regs);
1248 S = MCDisassembler::SoftFail;
1251 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1252 return MCDisassembler::Fail;
1253 for (unsigned i = 0; i < (regs - 1); ++i) {
1254 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1255 return MCDisassembler::Fail;
1261 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1262 uint64_t Address, const void *Decoder) {
1263 DecodeStatus S = MCDisassembler::Success;
1265 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1266 unsigned regs = fieldFromInstruction(Val, 1, 7);
1268 // In case of unpredictable encoding, tweak the operands.
1269 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1270 regs = Vd + regs > 32 ? 32 - Vd : regs;
1271 regs = std::max( 1u, regs);
1272 regs = std::min(16u, regs);
1273 S = MCDisassembler::SoftFail;
1276 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1277 return MCDisassembler::Fail;
1278 for (unsigned i = 0; i < (regs - 1); ++i) {
1279 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1280 return MCDisassembler::Fail;
1286 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1287 uint64_t Address, const void *Decoder) {
1288 // This operand encodes a mask of contiguous zeros between a specified MSB
1289 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1290 // the mask of all bits LSB-and-lower, and then xor them to create
1291 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1292 // create the final mask.
1293 unsigned msb = fieldFromInstruction(Val, 5, 5);
1294 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1296 DecodeStatus S = MCDisassembler::Success;
1298 Check(S, MCDisassembler::SoftFail);
1299 // The check above will cause the warning for the "potentially undefined
1300 // instruction encoding" but we can't build a bad MCOperand value here
1301 // with a lsb > msb or else printing the MCInst will cause a crash.
1305 uint32_t msb_mask = 0xFFFFFFFF;
1306 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1307 uint32_t lsb_mask = (1U << lsb) - 1;
1309 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1313 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1314 uint64_t Address, const void *Decoder) {
1315 DecodeStatus S = MCDisassembler::Success;
1317 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1318 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1319 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1320 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1321 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1322 unsigned U = fieldFromInstruction(Insn, 23, 1);
1324 switch (Inst.getOpcode()) {
1325 case ARM::LDC_OFFSET:
1328 case ARM::LDC_OPTION:
1329 case ARM::LDCL_OFFSET:
1331 case ARM::LDCL_POST:
1332 case ARM::LDCL_OPTION:
1333 case ARM::STC_OFFSET:
1336 case ARM::STC_OPTION:
1337 case ARM::STCL_OFFSET:
1339 case ARM::STCL_POST:
1340 case ARM::STCL_OPTION:
1341 case ARM::t2LDC_OFFSET:
1342 case ARM::t2LDC_PRE:
1343 case ARM::t2LDC_POST:
1344 case ARM::t2LDC_OPTION:
1345 case ARM::t2LDCL_OFFSET:
1346 case ARM::t2LDCL_PRE:
1347 case ARM::t2LDCL_POST:
1348 case ARM::t2LDCL_OPTION:
1349 case ARM::t2STC_OFFSET:
1350 case ARM::t2STC_PRE:
1351 case ARM::t2STC_POST:
1352 case ARM::t2STC_OPTION:
1353 case ARM::t2STCL_OFFSET:
1354 case ARM::t2STCL_PRE:
1355 case ARM::t2STCL_POST:
1356 case ARM::t2STCL_OPTION:
1357 if (coproc == 0xA || coproc == 0xB)
1358 return MCDisassembler::Fail;
1364 const FeatureBitset &featureBits =
1365 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1366 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1367 return MCDisassembler::Fail;
1369 Inst.addOperand(MCOperand::createImm(coproc));
1370 Inst.addOperand(MCOperand::createImm(CRd));
1371 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1372 return MCDisassembler::Fail;
1374 switch (Inst.getOpcode()) {
1375 case ARM::t2LDC2_OFFSET:
1376 case ARM::t2LDC2L_OFFSET:
1377 case ARM::t2LDC2_PRE:
1378 case ARM::t2LDC2L_PRE:
1379 case ARM::t2STC2_OFFSET:
1380 case ARM::t2STC2L_OFFSET:
1381 case ARM::t2STC2_PRE:
1382 case ARM::t2STC2L_PRE:
1383 case ARM::LDC2_OFFSET:
1384 case ARM::LDC2L_OFFSET:
1386 case ARM::LDC2L_PRE:
1387 case ARM::STC2_OFFSET:
1388 case ARM::STC2L_OFFSET:
1390 case ARM::STC2L_PRE:
1391 case ARM::t2LDC_OFFSET:
1392 case ARM::t2LDCL_OFFSET:
1393 case ARM::t2LDC_PRE:
1394 case ARM::t2LDCL_PRE:
1395 case ARM::t2STC_OFFSET:
1396 case ARM::t2STCL_OFFSET:
1397 case ARM::t2STC_PRE:
1398 case ARM::t2STCL_PRE:
1399 case ARM::LDC_OFFSET:
1400 case ARM::LDCL_OFFSET:
1403 case ARM::STC_OFFSET:
1404 case ARM::STCL_OFFSET:
1407 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1408 Inst.addOperand(MCOperand::createImm(imm));
1410 case ARM::t2LDC2_POST:
1411 case ARM::t2LDC2L_POST:
1412 case ARM::t2STC2_POST:
1413 case ARM::t2STC2L_POST:
1414 case ARM::LDC2_POST:
1415 case ARM::LDC2L_POST:
1416 case ARM::STC2_POST:
1417 case ARM::STC2L_POST:
1418 case ARM::t2LDC_POST:
1419 case ARM::t2LDCL_POST:
1420 case ARM::t2STC_POST:
1421 case ARM::t2STCL_POST:
1423 case ARM::LDCL_POST:
1425 case ARM::STCL_POST:
1429 // The 'option' variant doesn't encode 'U' in the immediate since
1430 // the immediate is unsigned [0,255].
1431 Inst.addOperand(MCOperand::createImm(imm));
1435 switch (Inst.getOpcode()) {
1436 case ARM::LDC_OFFSET:
1439 case ARM::LDC_OPTION:
1440 case ARM::LDCL_OFFSET:
1442 case ARM::LDCL_POST:
1443 case ARM::LDCL_OPTION:
1444 case ARM::STC_OFFSET:
1447 case ARM::STC_OPTION:
1448 case ARM::STCL_OFFSET:
1450 case ARM::STCL_POST:
1451 case ARM::STCL_OPTION:
1452 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1453 return MCDisassembler::Fail;
1463 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1464 uint64_t Address, const void *Decoder) {
1465 DecodeStatus S = MCDisassembler::Success;
1467 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1468 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1469 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1470 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1471 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1472 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1473 unsigned P = fieldFromInstruction(Insn, 24, 1);
1474 unsigned W = fieldFromInstruction(Insn, 21, 1);
1476 // On stores, the writeback operand precedes Rt.
1477 switch (Inst.getOpcode()) {
1478 case ARM::STR_POST_IMM:
1479 case ARM::STR_POST_REG:
1480 case ARM::STRB_POST_IMM:
1481 case ARM::STRB_POST_REG:
1482 case ARM::STRT_POST_REG:
1483 case ARM::STRT_POST_IMM:
1484 case ARM::STRBT_POST_REG:
1485 case ARM::STRBT_POST_IMM:
1486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1487 return MCDisassembler::Fail;
1493 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1494 return MCDisassembler::Fail;
1496 // On loads, the writeback operand comes after Rt.
1497 switch (Inst.getOpcode()) {
1498 case ARM::LDR_POST_IMM:
1499 case ARM::LDR_POST_REG:
1500 case ARM::LDRB_POST_IMM:
1501 case ARM::LDRB_POST_REG:
1502 case ARM::LDRBT_POST_REG:
1503 case ARM::LDRBT_POST_IMM:
1504 case ARM::LDRT_POST_REG:
1505 case ARM::LDRT_POST_IMM:
1506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1507 return MCDisassembler::Fail;
1513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1514 return MCDisassembler::Fail;
1516 ARM_AM::AddrOpc Op = ARM_AM::add;
1517 if (!fieldFromInstruction(Insn, 23, 1))
1520 bool writeback = (P == 0) || (W == 1);
1521 unsigned idx_mode = 0;
1523 idx_mode = ARMII::IndexModePre;
1524 else if (!P && writeback)
1525 idx_mode = ARMII::IndexModePost;
1527 if (writeback && (Rn == 15 || Rn == Rt))
1528 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1531 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1532 return MCDisassembler::Fail;
1533 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1534 switch( fieldFromInstruction(Insn, 5, 2)) {
1548 return MCDisassembler::Fail;
1550 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1551 if (Opc == ARM_AM::ror && amt == 0)
1553 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1555 Inst.addOperand(MCOperand::createImm(imm));
1557 Inst.addOperand(MCOperand::createReg(0));
1558 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1559 Inst.addOperand(MCOperand::createImm(tmp));
1562 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1563 return MCDisassembler::Fail;
1568 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1569 uint64_t Address, const void *Decoder) {
1570 DecodeStatus S = MCDisassembler::Success;
1572 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1573 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1574 unsigned type = fieldFromInstruction(Val, 5, 2);
1575 unsigned imm = fieldFromInstruction(Val, 7, 5);
1576 unsigned U = fieldFromInstruction(Val, 12, 1);
1578 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1594 if (ShOp == ARM_AM::ror && imm == 0)
1597 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1598 return MCDisassembler::Fail;
1599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1600 return MCDisassembler::Fail;
1603 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1605 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1606 Inst.addOperand(MCOperand::createImm(shift));
1612 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1613 uint64_t Address, const void *Decoder) {
1614 DecodeStatus S = MCDisassembler::Success;
1616 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1617 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1618 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1619 unsigned type = fieldFromInstruction(Insn, 22, 1);
1620 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1621 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1622 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1623 unsigned W = fieldFromInstruction(Insn, 21, 1);
1624 unsigned P = fieldFromInstruction(Insn, 24, 1);
1625 unsigned Rt2 = Rt + 1;
1627 bool writeback = (W == 1) | (P == 0);
1629 // For {LD,ST}RD, Rt must be even, else undefined.
1630 switch (Inst.getOpcode()) {
1633 case ARM::STRD_POST:
1636 case ARM::LDRD_POST:
1637 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1642 switch (Inst.getOpcode()) {
1645 case ARM::STRD_POST:
1646 if (P == 0 && W == 1)
1647 S = MCDisassembler::SoftFail;
1649 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1650 S = MCDisassembler::SoftFail;
1651 if (type && Rm == 15)
1652 S = MCDisassembler::SoftFail;
1654 S = MCDisassembler::SoftFail;
1655 if (!type && fieldFromInstruction(Insn, 8, 4))
1656 S = MCDisassembler::SoftFail;
1660 case ARM::STRH_POST:
1662 S = MCDisassembler::SoftFail;
1663 if (writeback && (Rn == 15 || Rn == Rt))
1664 S = MCDisassembler::SoftFail;
1665 if (!type && Rm == 15)
1666 S = MCDisassembler::SoftFail;
1670 case ARM::LDRD_POST:
1671 if (type && Rn == 15){
1673 S = MCDisassembler::SoftFail;
1676 if (P == 0 && W == 1)
1677 S = MCDisassembler::SoftFail;
1678 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1679 S = MCDisassembler::SoftFail;
1680 if (!type && writeback && Rn == 15)
1681 S = MCDisassembler::SoftFail;
1682 if (writeback && (Rn == Rt || Rn == Rt2))
1683 S = MCDisassembler::SoftFail;
1687 case ARM::LDRH_POST:
1688 if (type && Rn == 15){
1690 S = MCDisassembler::SoftFail;
1694 S = MCDisassembler::SoftFail;
1695 if (!type && Rm == 15)
1696 S = MCDisassembler::SoftFail;
1697 if (!type && writeback && (Rn == 15 || Rn == Rt))
1698 S = MCDisassembler::SoftFail;
1701 case ARM::LDRSH_PRE:
1702 case ARM::LDRSH_POST:
1704 case ARM::LDRSB_PRE:
1705 case ARM::LDRSB_POST:
1706 if (type && Rn == 15){
1708 S = MCDisassembler::SoftFail;
1711 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1712 S = MCDisassembler::SoftFail;
1713 if (!type && (Rt == 15 || Rm == 15))
1714 S = MCDisassembler::SoftFail;
1715 if (!type && writeback && (Rn == 15 || Rn == Rt))
1716 S = MCDisassembler::SoftFail;
1722 if (writeback) { // Writeback
1724 U |= ARMII::IndexModePre << 9;
1726 U |= ARMII::IndexModePost << 9;
1728 // On stores, the writeback operand precedes Rt.
1729 switch (Inst.getOpcode()) {
1732 case ARM::STRD_POST:
1735 case ARM::STRH_POST:
1736 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1737 return MCDisassembler::Fail;
1744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1745 return MCDisassembler::Fail;
1746 switch (Inst.getOpcode()) {
1749 case ARM::STRD_POST:
1752 case ARM::LDRD_POST:
1753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1754 return MCDisassembler::Fail;
1761 // On loads, the writeback operand comes after Rt.
1762 switch (Inst.getOpcode()) {
1765 case ARM::LDRD_POST:
1768 case ARM::LDRH_POST:
1770 case ARM::LDRSH_PRE:
1771 case ARM::LDRSH_POST:
1773 case ARM::LDRSB_PRE:
1774 case ARM::LDRSB_POST:
1777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1778 return MCDisassembler::Fail;
1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1786 return MCDisassembler::Fail;
1789 Inst.addOperand(MCOperand::createReg(0));
1790 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1793 return MCDisassembler::Fail;
1794 Inst.addOperand(MCOperand::createImm(U));
1797 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1798 return MCDisassembler::Fail;
1803 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1804 uint64_t Address, const void *Decoder) {
1805 DecodeStatus S = MCDisassembler::Success;
1807 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1808 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1825 Inst.addOperand(MCOperand::createImm(mode));
1826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1827 return MCDisassembler::Fail;
1832 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1833 uint64_t Address, const void *Decoder) {
1834 DecodeStatus S = MCDisassembler::Success;
1836 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1837 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1838 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1839 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1842 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1844 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1845 return MCDisassembler::Fail;
1846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1847 return MCDisassembler::Fail;
1848 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1849 return MCDisassembler::Fail;
1850 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1851 return MCDisassembler::Fail;
1855 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1857 uint64_t Address, const void *Decoder) {
1858 DecodeStatus S = MCDisassembler::Success;
1860 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1861 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1862 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1865 // Ambiguous with RFE and SRS
1866 switch (Inst.getOpcode()) {
1868 Inst.setOpcode(ARM::RFEDA);
1870 case ARM::LDMDA_UPD:
1871 Inst.setOpcode(ARM::RFEDA_UPD);
1874 Inst.setOpcode(ARM::RFEDB);
1876 case ARM::LDMDB_UPD:
1877 Inst.setOpcode(ARM::RFEDB_UPD);
1880 Inst.setOpcode(ARM::RFEIA);
1882 case ARM::LDMIA_UPD:
1883 Inst.setOpcode(ARM::RFEIA_UPD);
1886 Inst.setOpcode(ARM::RFEIB);
1888 case ARM::LDMIB_UPD:
1889 Inst.setOpcode(ARM::RFEIB_UPD);
1892 Inst.setOpcode(ARM::SRSDA);
1894 case ARM::STMDA_UPD:
1895 Inst.setOpcode(ARM::SRSDA_UPD);
1898 Inst.setOpcode(ARM::SRSDB);
1900 case ARM::STMDB_UPD:
1901 Inst.setOpcode(ARM::SRSDB_UPD);
1904 Inst.setOpcode(ARM::SRSIA);
1906 case ARM::STMIA_UPD:
1907 Inst.setOpcode(ARM::SRSIA_UPD);
1910 Inst.setOpcode(ARM::SRSIB);
1912 case ARM::STMIB_UPD:
1913 Inst.setOpcode(ARM::SRSIB_UPD);
1916 return MCDisassembler::Fail;
1919 // For stores (which become SRS's, the only operand is the mode.
1920 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1921 // Check SRS encoding constraints
1922 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1923 fieldFromInstruction(Insn, 20, 1) == 0))
1924 return MCDisassembler::Fail;
1927 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
1931 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1934 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1935 return MCDisassembler::Fail;
1936 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1937 return MCDisassembler::Fail; // Tied
1938 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1939 return MCDisassembler::Fail;
1940 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1941 return MCDisassembler::Fail;
1946 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1947 uint64_t Address, const void *Decoder) {
1948 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1949 unsigned M = fieldFromInstruction(Insn, 17, 1);
1950 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1951 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1953 DecodeStatus S = MCDisassembler::Success;
1955 // This decoder is called from multiple location that do not check
1956 // the full encoding is valid before they do.
1957 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1958 fieldFromInstruction(Insn, 16, 1) != 0 ||
1959 fieldFromInstruction(Insn, 20, 8) != 0x10)
1960 return MCDisassembler::Fail;
1962 // imod == '01' --> UNPREDICTABLE
1963 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1964 // return failure here. The '01' imod value is unprintable, so there's
1965 // nothing useful we could do even if we returned UNPREDICTABLE.
1967 if (imod == 1) return MCDisassembler::Fail;
1970 Inst.setOpcode(ARM::CPS3p);
1971 Inst.addOperand(MCOperand::createImm(imod));
1972 Inst.addOperand(MCOperand::createImm(iflags));
1973 Inst.addOperand(MCOperand::createImm(mode));
1974 } else if (imod && !M) {
1975 Inst.setOpcode(ARM::CPS2p);
1976 Inst.addOperand(MCOperand::createImm(imod));
1977 Inst.addOperand(MCOperand::createImm(iflags));
1978 if (mode) S = MCDisassembler::SoftFail;
1979 } else if (!imod && M) {
1980 Inst.setOpcode(ARM::CPS1p);
1981 Inst.addOperand(MCOperand::createImm(mode));
1982 if (iflags) S = MCDisassembler::SoftFail;
1984 // imod == '00' && M == '0' --> UNPREDICTABLE
1985 Inst.setOpcode(ARM::CPS1p);
1986 Inst.addOperand(MCOperand::createImm(mode));
1987 S = MCDisassembler::SoftFail;
1993 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1994 uint64_t Address, const void *Decoder) {
1995 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1996 unsigned M = fieldFromInstruction(Insn, 8, 1);
1997 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1998 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2000 DecodeStatus S = MCDisassembler::Success;
2002 // imod == '01' --> UNPREDICTABLE
2003 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2004 // return failure here. The '01' imod value is unprintable, so there's
2005 // nothing useful we could do even if we returned UNPREDICTABLE.
2007 if (imod == 1) return MCDisassembler::Fail;
2010 Inst.setOpcode(ARM::t2CPS3p);
2011 Inst.addOperand(MCOperand::createImm(imod));
2012 Inst.addOperand(MCOperand::createImm(iflags));
2013 Inst.addOperand(MCOperand::createImm(mode));
2014 } else if (imod && !M) {
2015 Inst.setOpcode(ARM::t2CPS2p);
2016 Inst.addOperand(MCOperand::createImm(imod));
2017 Inst.addOperand(MCOperand::createImm(iflags));
2018 if (mode) S = MCDisassembler::SoftFail;
2019 } else if (!imod && M) {
2020 Inst.setOpcode(ARM::t2CPS1p);
2021 Inst.addOperand(MCOperand::createImm(mode));
2022 if (iflags) S = MCDisassembler::SoftFail;
2024 // imod == '00' && M == '0' --> this is a HINT instruction
2025 int imm = fieldFromInstruction(Insn, 0, 8);
2026 // HINT are defined only for immediate in [0..4]
2027 if(imm > 4) return MCDisassembler::Fail;
2028 Inst.setOpcode(ARM::t2HINT);
2029 Inst.addOperand(MCOperand::createImm(imm));
2035 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2036 uint64_t Address, const void *Decoder) {
2037 DecodeStatus S = MCDisassembler::Success;
2039 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2042 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2043 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2044 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2045 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2047 if (Inst.getOpcode() == ARM::t2MOVTi16)
2048 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2049 return MCDisassembler::Fail;
2050 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2051 return MCDisassembler::Fail;
2053 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2054 Inst.addOperand(MCOperand::createImm(imm));
2059 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2060 uint64_t Address, const void *Decoder) {
2061 DecodeStatus S = MCDisassembler::Success;
2063 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2064 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2067 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2068 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2070 if (Inst.getOpcode() == ARM::MOVTi16)
2071 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2072 return MCDisassembler::Fail;
2074 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2075 return MCDisassembler::Fail;
2077 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2078 Inst.addOperand(MCOperand::createImm(imm));
2080 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2081 return MCDisassembler::Fail;
2086 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2087 uint64_t Address, const void *Decoder) {
2088 DecodeStatus S = MCDisassembler::Success;
2090 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2091 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2092 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2093 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2094 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2097 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2099 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2100 return MCDisassembler::Fail;
2101 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2102 return MCDisassembler::Fail;
2103 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2104 return MCDisassembler::Fail;
2105 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2106 return MCDisassembler::Fail;
2108 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2109 return MCDisassembler::Fail;
2114 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2115 uint64_t Address, const void *Decoder) {
2116 DecodeStatus S = MCDisassembler::Success;
2118 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2119 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2120 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2123 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2125 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2126 return MCDisassembler::Fail;
2127 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2128 return MCDisassembler::Fail;
2129 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2130 return MCDisassembler::Fail;
2135 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2136 uint64_t Address, const void *Decoder) {
2137 DecodeStatus S = MCDisassembler::Success;
2139 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2141 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2142 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2144 if (!FeatureBits[ARM::HasV8_1aOps] ||
2145 !FeatureBits[ARM::HasV8Ops])
2146 return MCDisassembler::Fail;
2148 // Decoder can be called from DecodeTST, which does not check the full
2149 // encoding is valid.
2150 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2151 fieldFromInstruction(Insn, 4,4) != 0)
2152 return MCDisassembler::Fail;
2153 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2154 fieldFromInstruction(Insn, 0,4) != 0)
2155 S = MCDisassembler::SoftFail;
2157 Inst.setOpcode(ARM::SETPAN);
2158 Inst.addOperand(MCOperand::createImm(Imm));
2163 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2164 uint64_t Address, const void *Decoder) {
2165 DecodeStatus S = MCDisassembler::Success;
2167 unsigned add = fieldFromInstruction(Val, 12, 1);
2168 unsigned imm = fieldFromInstruction(Val, 0, 12);
2169 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2171 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2172 return MCDisassembler::Fail;
2174 if (!add) imm *= -1;
2175 if (imm == 0 && !add) imm = INT32_MIN;
2176 Inst.addOperand(MCOperand::createImm(imm));
2178 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2183 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2184 uint64_t Address, const void *Decoder) {
2185 DecodeStatus S = MCDisassembler::Success;
2187 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2188 // U == 1 to add imm, 0 to subtract it.
2189 unsigned U = fieldFromInstruction(Val, 8, 1);
2190 unsigned imm = fieldFromInstruction(Val, 0, 8);
2192 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2193 return MCDisassembler::Fail;
2196 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2198 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2203 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2204 uint64_t Address, const void *Decoder) {
2205 DecodeStatus S = MCDisassembler::Success;
2207 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2208 // U == 1 to add imm, 0 to subtract it.
2209 unsigned U = fieldFromInstruction(Val, 8, 1);
2210 unsigned imm = fieldFromInstruction(Val, 0, 8);
2212 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2213 return MCDisassembler::Fail;
2216 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2218 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2223 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2224 uint64_t Address, const void *Decoder) {
2225 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2229 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2230 uint64_t Address, const void *Decoder) {
2231 DecodeStatus Status = MCDisassembler::Success;
2233 // Note the J1 and J2 values are from the encoded instruction. So here
2234 // change them to I1 and I2 values via as documented:
2235 // I1 = NOT(J1 EOR S);
2236 // I2 = NOT(J2 EOR S);
2237 // and build the imm32 with one trailing zero as documented:
2238 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2239 unsigned S = fieldFromInstruction(Insn, 26, 1);
2240 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2241 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2242 unsigned I1 = !(J1 ^ S);
2243 unsigned I2 = !(J2 ^ S);
2244 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2245 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2246 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2247 int imm32 = SignExtend32<25>(tmp << 1);
2248 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2249 true, 4, Inst, Decoder))
2250 Inst.addOperand(MCOperand::createImm(imm32));
2256 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2257 uint64_t Address, const void *Decoder) {
2258 DecodeStatus S = MCDisassembler::Success;
2260 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2261 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2264 Inst.setOpcode(ARM::BLXi);
2265 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2266 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2267 true, 4, Inst, Decoder))
2268 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2272 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2273 true, 4, Inst, Decoder))
2274 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2275 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2276 return MCDisassembler::Fail;
2282 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2283 uint64_t Address, const void *Decoder) {
2284 DecodeStatus S = MCDisassembler::Success;
2286 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2287 unsigned align = fieldFromInstruction(Val, 4, 2);
2289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2290 return MCDisassembler::Fail;
2292 Inst.addOperand(MCOperand::createImm(0));
2294 Inst.addOperand(MCOperand::createImm(4 << align));
2299 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2300 uint64_t Address, const void *Decoder) {
2301 DecodeStatus S = MCDisassembler::Success;
2303 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2304 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2305 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2306 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2307 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2308 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2310 // First output register
2311 switch (Inst.getOpcode()) {
2312 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2313 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2314 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2315 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2316 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2317 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2318 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2319 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2320 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2321 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2322 return MCDisassembler::Fail;
2327 case ARM::VLD2b16wb_fixed:
2328 case ARM::VLD2b16wb_register:
2329 case ARM::VLD2b32wb_fixed:
2330 case ARM::VLD2b32wb_register:
2331 case ARM::VLD2b8wb_fixed:
2332 case ARM::VLD2b8wb_register:
2333 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2334 return MCDisassembler::Fail;
2337 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2338 return MCDisassembler::Fail;
2341 // Second output register
2342 switch (Inst.getOpcode()) {
2346 case ARM::VLD3d8_UPD:
2347 case ARM::VLD3d16_UPD:
2348 case ARM::VLD3d32_UPD:
2352 case ARM::VLD4d8_UPD:
2353 case ARM::VLD4d16_UPD:
2354 case ARM::VLD4d32_UPD:
2355 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2356 return MCDisassembler::Fail;
2361 case ARM::VLD3q8_UPD:
2362 case ARM::VLD3q16_UPD:
2363 case ARM::VLD3q32_UPD:
2367 case ARM::VLD4q8_UPD:
2368 case ARM::VLD4q16_UPD:
2369 case ARM::VLD4q32_UPD:
2370 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2371 return MCDisassembler::Fail;
2376 // Third output register
2377 switch(Inst.getOpcode()) {
2381 case ARM::VLD3d8_UPD:
2382 case ARM::VLD3d16_UPD:
2383 case ARM::VLD3d32_UPD:
2387 case ARM::VLD4d8_UPD:
2388 case ARM::VLD4d16_UPD:
2389 case ARM::VLD4d32_UPD:
2390 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2391 return MCDisassembler::Fail;
2396 case ARM::VLD3q8_UPD:
2397 case ARM::VLD3q16_UPD:
2398 case ARM::VLD3q32_UPD:
2402 case ARM::VLD4q8_UPD:
2403 case ARM::VLD4q16_UPD:
2404 case ARM::VLD4q32_UPD:
2405 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2406 return MCDisassembler::Fail;
2412 // Fourth output register
2413 switch (Inst.getOpcode()) {
2417 case ARM::VLD4d8_UPD:
2418 case ARM::VLD4d16_UPD:
2419 case ARM::VLD4d32_UPD:
2420 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2421 return MCDisassembler::Fail;
2426 case ARM::VLD4q8_UPD:
2427 case ARM::VLD4q16_UPD:
2428 case ARM::VLD4q32_UPD:
2429 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2430 return MCDisassembler::Fail;
2436 // Writeback operand
2437 switch (Inst.getOpcode()) {
2438 case ARM::VLD1d8wb_fixed:
2439 case ARM::VLD1d16wb_fixed:
2440 case ARM::VLD1d32wb_fixed:
2441 case ARM::VLD1d64wb_fixed:
2442 case ARM::VLD1d8wb_register:
2443 case ARM::VLD1d16wb_register:
2444 case ARM::VLD1d32wb_register:
2445 case ARM::VLD1d64wb_register:
2446 case ARM::VLD1q8wb_fixed:
2447 case ARM::VLD1q16wb_fixed:
2448 case ARM::VLD1q32wb_fixed:
2449 case ARM::VLD1q64wb_fixed:
2450 case ARM::VLD1q8wb_register:
2451 case ARM::VLD1q16wb_register:
2452 case ARM::VLD1q32wb_register:
2453 case ARM::VLD1q64wb_register:
2454 case ARM::VLD1d8Twb_fixed:
2455 case ARM::VLD1d8Twb_register:
2456 case ARM::VLD1d16Twb_fixed:
2457 case ARM::VLD1d16Twb_register:
2458 case ARM::VLD1d32Twb_fixed:
2459 case ARM::VLD1d32Twb_register:
2460 case ARM::VLD1d64Twb_fixed:
2461 case ARM::VLD1d64Twb_register:
2462 case ARM::VLD1d8Qwb_fixed:
2463 case ARM::VLD1d8Qwb_register:
2464 case ARM::VLD1d16Qwb_fixed:
2465 case ARM::VLD1d16Qwb_register:
2466 case ARM::VLD1d32Qwb_fixed:
2467 case ARM::VLD1d32Qwb_register:
2468 case ARM::VLD1d64Qwb_fixed:
2469 case ARM::VLD1d64Qwb_register:
2470 case ARM::VLD2d8wb_fixed:
2471 case ARM::VLD2d16wb_fixed:
2472 case ARM::VLD2d32wb_fixed:
2473 case ARM::VLD2q8wb_fixed:
2474 case ARM::VLD2q16wb_fixed:
2475 case ARM::VLD2q32wb_fixed:
2476 case ARM::VLD2d8wb_register:
2477 case ARM::VLD2d16wb_register:
2478 case ARM::VLD2d32wb_register:
2479 case ARM::VLD2q8wb_register:
2480 case ARM::VLD2q16wb_register:
2481 case ARM::VLD2q32wb_register:
2482 case ARM::VLD2b8wb_fixed:
2483 case ARM::VLD2b16wb_fixed:
2484 case ARM::VLD2b32wb_fixed:
2485 case ARM::VLD2b8wb_register:
2486 case ARM::VLD2b16wb_register:
2487 case ARM::VLD2b32wb_register:
2488 Inst.addOperand(MCOperand::createImm(0));
2490 case ARM::VLD3d8_UPD:
2491 case ARM::VLD3d16_UPD:
2492 case ARM::VLD3d32_UPD:
2493 case ARM::VLD3q8_UPD:
2494 case ARM::VLD3q16_UPD:
2495 case ARM::VLD3q32_UPD:
2496 case ARM::VLD4d8_UPD:
2497 case ARM::VLD4d16_UPD:
2498 case ARM::VLD4d32_UPD:
2499 case ARM::VLD4q8_UPD:
2500 case ARM::VLD4q16_UPD:
2501 case ARM::VLD4q32_UPD:
2502 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2503 return MCDisassembler::Fail;
2509 // AddrMode6 Base (register+alignment)
2510 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2511 return MCDisassembler::Fail;
2513 // AddrMode6 Offset (register)
2514 switch (Inst.getOpcode()) {
2516 // The below have been updated to have explicit am6offset split
2517 // between fixed and register offset. For those instructions not
2518 // yet updated, we need to add an additional reg0 operand for the
2521 // The fixed offset encodes as Rm == 0xd, so we check for that.
2523 Inst.addOperand(MCOperand::createReg(0));
2526 // Fall through to handle the register offset variant.
2527 case ARM::VLD1d8wb_fixed:
2528 case ARM::VLD1d16wb_fixed:
2529 case ARM::VLD1d32wb_fixed:
2530 case ARM::VLD1d64wb_fixed:
2531 case ARM::VLD1d8Twb_fixed:
2532 case ARM::VLD1d16Twb_fixed:
2533 case ARM::VLD1d32Twb_fixed:
2534 case ARM::VLD1d64Twb_fixed:
2535 case ARM::VLD1d8Qwb_fixed:
2536 case ARM::VLD1d16Qwb_fixed:
2537 case ARM::VLD1d32Qwb_fixed:
2538 case ARM::VLD1d64Qwb_fixed:
2539 case ARM::VLD1d8wb_register:
2540 case ARM::VLD1d16wb_register:
2541 case ARM::VLD1d32wb_register:
2542 case ARM::VLD1d64wb_register:
2543 case ARM::VLD1q8wb_fixed:
2544 case ARM::VLD1q16wb_fixed:
2545 case ARM::VLD1q32wb_fixed:
2546 case ARM::VLD1q64wb_fixed:
2547 case ARM::VLD1q8wb_register:
2548 case ARM::VLD1q16wb_register:
2549 case ARM::VLD1q32wb_register:
2550 case ARM::VLD1q64wb_register:
2551 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2552 // variant encodes Rm == 0xf. Anything else is a register offset post-
2553 // increment and we need to add the register operand to the instruction.
2554 if (Rm != 0xD && Rm != 0xF &&
2555 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2556 return MCDisassembler::Fail;
2558 case ARM::VLD2d8wb_fixed:
2559 case ARM::VLD2d16wb_fixed:
2560 case ARM::VLD2d32wb_fixed:
2561 case ARM::VLD2b8wb_fixed:
2562 case ARM::VLD2b16wb_fixed:
2563 case ARM::VLD2b32wb_fixed:
2564 case ARM::VLD2q8wb_fixed:
2565 case ARM::VLD2q16wb_fixed:
2566 case ARM::VLD2q32wb_fixed:
2573 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2574 uint64_t Address, const void *Decoder) {
2575 unsigned type = fieldFromInstruction(Insn, 8, 4);
2576 unsigned align = fieldFromInstruction(Insn, 4, 2);
2577 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2578 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2579 if (type == 10 && align == 3) return MCDisassembler::Fail;
2581 unsigned load = fieldFromInstruction(Insn, 21, 1);
2582 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2583 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2586 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2587 uint64_t Address, const void *Decoder) {
2588 unsigned size = fieldFromInstruction(Insn, 6, 2);
2589 if (size == 3) return MCDisassembler::Fail;
2591 unsigned type = fieldFromInstruction(Insn, 8, 4);
2592 unsigned align = fieldFromInstruction(Insn, 4, 2);
2593 if (type == 8 && align == 3) return MCDisassembler::Fail;
2594 if (type == 9 && align == 3) return MCDisassembler::Fail;
2596 unsigned load = fieldFromInstruction(Insn, 21, 1);
2597 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2598 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2601 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2602 uint64_t Address, const void *Decoder) {
2603 unsigned size = fieldFromInstruction(Insn, 6, 2);
2604 if (size == 3) return MCDisassembler::Fail;
2606 unsigned align = fieldFromInstruction(Insn, 4, 2);
2607 if (align & 2) return MCDisassembler::Fail;
2609 unsigned load = fieldFromInstruction(Insn, 21, 1);
2610 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2611 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2614 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2615 uint64_t Address, const void *Decoder) {
2616 unsigned size = fieldFromInstruction(Insn, 6, 2);
2617 if (size == 3) return MCDisassembler::Fail;
2619 unsigned load = fieldFromInstruction(Insn, 21, 1);
2620 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2621 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2624 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2625 uint64_t Address, const void *Decoder) {
2626 DecodeStatus S = MCDisassembler::Success;
2628 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2629 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2630 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2631 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2632 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2633 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2635 // Writeback Operand
2636 switch (Inst.getOpcode()) {
2637 case ARM::VST1d8wb_fixed:
2638 case ARM::VST1d16wb_fixed:
2639 case ARM::VST1d32wb_fixed:
2640 case ARM::VST1d64wb_fixed:
2641 case ARM::VST1d8wb_register:
2642 case ARM::VST1d16wb_register:
2643 case ARM::VST1d32wb_register:
2644 case ARM::VST1d64wb_register:
2645 case ARM::VST1q8wb_fixed:
2646 case ARM::VST1q16wb_fixed:
2647 case ARM::VST1q32wb_fixed:
2648 case ARM::VST1q64wb_fixed:
2649 case ARM::VST1q8wb_register:
2650 case ARM::VST1q16wb_register:
2651 case ARM::VST1q32wb_register:
2652 case ARM::VST1q64wb_register:
2653 case ARM::VST1d8Twb_fixed:
2654 case ARM::VST1d16Twb_fixed:
2655 case ARM::VST1d32Twb_fixed:
2656 case ARM::VST1d64Twb_fixed:
2657 case ARM::VST1d8Twb_register:
2658 case ARM::VST1d16Twb_register:
2659 case ARM::VST1d32Twb_register:
2660 case ARM::VST1d64Twb_register:
2661 case ARM::VST1d8Qwb_fixed:
2662 case ARM::VST1d16Qwb_fixed:
2663 case ARM::VST1d32Qwb_fixed:
2664 case ARM::VST1d64Qwb_fixed:
2665 case ARM::VST1d8Qwb_register:
2666 case ARM::VST1d16Qwb_register:
2667 case ARM::VST1d32Qwb_register:
2668 case ARM::VST1d64Qwb_register:
2669 case ARM::VST2d8wb_fixed:
2670 case ARM::VST2d16wb_fixed:
2671 case ARM::VST2d32wb_fixed:
2672 case ARM::VST2d8wb_register:
2673 case ARM::VST2d16wb_register:
2674 case ARM::VST2d32wb_register:
2675 case ARM::VST2q8wb_fixed:
2676 case ARM::VST2q16wb_fixed:
2677 case ARM::VST2q32wb_fixed:
2678 case ARM::VST2q8wb_register:
2679 case ARM::VST2q16wb_register:
2680 case ARM::VST2q32wb_register:
2681 case ARM::VST2b8wb_fixed:
2682 case ARM::VST2b16wb_fixed:
2683 case ARM::VST2b32wb_fixed:
2684 case ARM::VST2b8wb_register:
2685 case ARM::VST2b16wb_register:
2686 case ARM::VST2b32wb_register:
2688 return MCDisassembler::Fail;
2689 Inst.addOperand(MCOperand::createImm(0));
2691 case ARM::VST3d8_UPD:
2692 case ARM::VST3d16_UPD:
2693 case ARM::VST3d32_UPD:
2694 case ARM::VST3q8_UPD:
2695 case ARM::VST3q16_UPD:
2696 case ARM::VST3q32_UPD:
2697 case ARM::VST4d8_UPD:
2698 case ARM::VST4d16_UPD:
2699 case ARM::VST4d32_UPD:
2700 case ARM::VST4q8_UPD:
2701 case ARM::VST4q16_UPD:
2702 case ARM::VST4q32_UPD:
2703 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2704 return MCDisassembler::Fail;
2710 // AddrMode6 Base (register+alignment)
2711 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2712 return MCDisassembler::Fail;
2714 // AddrMode6 Offset (register)
2715 switch (Inst.getOpcode()) {
2718 Inst.addOperand(MCOperand::createReg(0));
2719 else if (Rm != 0xF) {
2720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2721 return MCDisassembler::Fail;
2724 case ARM::VST1d8wb_fixed:
2725 case ARM::VST1d16wb_fixed:
2726 case ARM::VST1d32wb_fixed:
2727 case ARM::VST1d64wb_fixed:
2728 case ARM::VST1q8wb_fixed:
2729 case ARM::VST1q16wb_fixed:
2730 case ARM::VST1q32wb_fixed:
2731 case ARM::VST1q64wb_fixed:
2732 case ARM::VST1d8Twb_fixed:
2733 case ARM::VST1d16Twb_fixed:
2734 case ARM::VST1d32Twb_fixed:
2735 case ARM::VST1d64Twb_fixed:
2736 case ARM::VST1d8Qwb_fixed:
2737 case ARM::VST1d16Qwb_fixed:
2738 case ARM::VST1d32Qwb_fixed:
2739 case ARM::VST1d64Qwb_fixed:
2740 case ARM::VST2d8wb_fixed:
2741 case ARM::VST2d16wb_fixed:
2742 case ARM::VST2d32wb_fixed:
2743 case ARM::VST2q8wb_fixed:
2744 case ARM::VST2q16wb_fixed:
2745 case ARM::VST2q32wb_fixed:
2746 case ARM::VST2b8wb_fixed:
2747 case ARM::VST2b16wb_fixed:
2748 case ARM::VST2b32wb_fixed:
2753 // First input register
2754 switch (Inst.getOpcode()) {
2759 case ARM::VST1q16wb_fixed:
2760 case ARM::VST1q16wb_register:
2761 case ARM::VST1q32wb_fixed:
2762 case ARM::VST1q32wb_register:
2763 case ARM::VST1q64wb_fixed:
2764 case ARM::VST1q64wb_register:
2765 case ARM::VST1q8wb_fixed:
2766 case ARM::VST1q8wb_register:
2770 case ARM::VST2d16wb_fixed:
2771 case ARM::VST2d16wb_register:
2772 case ARM::VST2d32wb_fixed:
2773 case ARM::VST2d32wb_register:
2774 case ARM::VST2d8wb_fixed:
2775 case ARM::VST2d8wb_register:
2776 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2777 return MCDisassembler::Fail;
2782 case ARM::VST2b16wb_fixed:
2783 case ARM::VST2b16wb_register:
2784 case ARM::VST2b32wb_fixed:
2785 case ARM::VST2b32wb_register:
2786 case ARM::VST2b8wb_fixed:
2787 case ARM::VST2b8wb_register:
2788 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2789 return MCDisassembler::Fail;
2792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2793 return MCDisassembler::Fail;
2796 // Second input register
2797 switch (Inst.getOpcode()) {
2801 case ARM::VST3d8_UPD:
2802 case ARM::VST3d16_UPD:
2803 case ARM::VST3d32_UPD:
2807 case ARM::VST4d8_UPD:
2808 case ARM::VST4d16_UPD:
2809 case ARM::VST4d32_UPD:
2810 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2811 return MCDisassembler::Fail;
2816 case ARM::VST3q8_UPD:
2817 case ARM::VST3q16_UPD:
2818 case ARM::VST3q32_UPD:
2822 case ARM::VST4q8_UPD:
2823 case ARM::VST4q16_UPD:
2824 case ARM::VST4q32_UPD:
2825 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2826 return MCDisassembler::Fail;
2832 // Third input register
2833 switch (Inst.getOpcode()) {
2837 case ARM::VST3d8_UPD:
2838 case ARM::VST3d16_UPD:
2839 case ARM::VST3d32_UPD:
2843 case ARM::VST4d8_UPD:
2844 case ARM::VST4d16_UPD:
2845 case ARM::VST4d32_UPD:
2846 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2847 return MCDisassembler::Fail;
2852 case ARM::VST3q8_UPD:
2853 case ARM::VST3q16_UPD:
2854 case ARM::VST3q32_UPD:
2858 case ARM::VST4q8_UPD:
2859 case ARM::VST4q16_UPD:
2860 case ARM::VST4q32_UPD:
2861 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2862 return MCDisassembler::Fail;
2868 // Fourth input register
2869 switch (Inst.getOpcode()) {
2873 case ARM::VST4d8_UPD:
2874 case ARM::VST4d16_UPD:
2875 case ARM::VST4d32_UPD:
2876 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2877 return MCDisassembler::Fail;
2882 case ARM::VST4q8_UPD:
2883 case ARM::VST4q16_UPD:
2884 case ARM::VST4q32_UPD:
2885 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2886 return MCDisassembler::Fail;
2895 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2896 uint64_t Address, const void *Decoder) {
2897 DecodeStatus S = MCDisassembler::Success;
2899 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2900 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2901 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2902 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2903 unsigned align = fieldFromInstruction(Insn, 4, 1);
2904 unsigned size = fieldFromInstruction(Insn, 6, 2);
2906 if (size == 0 && align == 1)
2907 return MCDisassembler::Fail;
2908 align *= (1 << size);
2910 switch (Inst.getOpcode()) {
2911 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2912 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2913 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2914 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2915 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2916 return MCDisassembler::Fail;
2919 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2920 return MCDisassembler::Fail;
2924 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2925 return MCDisassembler::Fail;
2928 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2929 return MCDisassembler::Fail;
2930 Inst.addOperand(MCOperand::createImm(align));
2932 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2933 // variant encodes Rm == 0xf. Anything else is a register offset post-
2934 // increment and we need to add the register operand to the instruction.
2935 if (Rm != 0xD && Rm != 0xF &&
2936 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2937 return MCDisassembler::Fail;
2942 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2943 uint64_t Address, const void *Decoder) {
2944 DecodeStatus S = MCDisassembler::Success;
2946 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2947 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2948 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2949 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2950 unsigned align = fieldFromInstruction(Insn, 4, 1);
2951 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2954 switch (Inst.getOpcode()) {
2955 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2956 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2957 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2958 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2959 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2960 return MCDisassembler::Fail;
2962 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2963 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2964 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2965 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2966 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2967 return MCDisassembler::Fail;
2970 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2971 return MCDisassembler::Fail;
2976 Inst.addOperand(MCOperand::createImm(0));
2978 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2979 return MCDisassembler::Fail;
2980 Inst.addOperand(MCOperand::createImm(align));
2982 if (Rm != 0xD && Rm != 0xF) {
2983 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2984 return MCDisassembler::Fail;
2990 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2991 uint64_t Address, const void *Decoder) {
2992 DecodeStatus S = MCDisassembler::Success;
2994 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2995 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2996 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2997 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2998 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3000 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3001 return MCDisassembler::Fail;
3002 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3003 return MCDisassembler::Fail;
3004 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3005 return MCDisassembler::Fail;
3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3008 return MCDisassembler::Fail;
3011 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3012 return MCDisassembler::Fail;
3013 Inst.addOperand(MCOperand::createImm(0));
3016 Inst.addOperand(MCOperand::createReg(0));
3017 else if (Rm != 0xF) {
3018 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3019 return MCDisassembler::Fail;
3025 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3026 uint64_t Address, const void *Decoder) {
3027 DecodeStatus S = MCDisassembler::Success;
3029 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3030 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3031 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3032 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3033 unsigned size = fieldFromInstruction(Insn, 6, 2);
3034 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3035 unsigned align = fieldFromInstruction(Insn, 4, 1);
3039 return MCDisassembler::Fail;
3050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3051 return MCDisassembler::Fail;
3052 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3053 return MCDisassembler::Fail;
3054 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3055 return MCDisassembler::Fail;
3056 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3057 return MCDisassembler::Fail;
3059 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3060 return MCDisassembler::Fail;
3063 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3064 return MCDisassembler::Fail;
3065 Inst.addOperand(MCOperand::createImm(align));
3068 Inst.addOperand(MCOperand::createReg(0));
3069 else if (Rm != 0xF) {
3070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3071 return MCDisassembler::Fail;
3078 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3079 uint64_t Address, const void *Decoder) {
3080 DecodeStatus S = MCDisassembler::Success;
3082 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3083 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3084 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3085 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3086 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3087 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3088 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3089 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3092 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3093 return MCDisassembler::Fail;
3095 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3096 return MCDisassembler::Fail;
3099 Inst.addOperand(MCOperand::createImm(imm));
3101 switch (Inst.getOpcode()) {
3102 case ARM::VORRiv4i16:
3103 case ARM::VORRiv2i32:
3104 case ARM::VBICiv4i16:
3105 case ARM::VBICiv2i32:
3106 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3107 return MCDisassembler::Fail;
3109 case ARM::VORRiv8i16:
3110 case ARM::VORRiv4i32:
3111 case ARM::VBICiv8i16:
3112 case ARM::VBICiv4i32:
3113 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3114 return MCDisassembler::Fail;
3123 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3124 uint64_t Address, const void *Decoder) {
3125 DecodeStatus S = MCDisassembler::Success;
3127 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3128 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3129 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3130 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3131 unsigned size = fieldFromInstruction(Insn, 18, 2);
3133 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3134 return MCDisassembler::Fail;
3135 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3136 return MCDisassembler::Fail;
3137 Inst.addOperand(MCOperand::createImm(8 << size));
3142 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3143 uint64_t Address, const void *Decoder) {
3144 Inst.addOperand(MCOperand::createImm(8 - Val));
3145 return MCDisassembler::Success;
3148 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3149 uint64_t Address, const void *Decoder) {
3150 Inst.addOperand(MCOperand::createImm(16 - Val));
3151 return MCDisassembler::Success;
3154 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3155 uint64_t Address, const void *Decoder) {
3156 Inst.addOperand(MCOperand::createImm(32 - Val));
3157 return MCDisassembler::Success;
3160 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3161 uint64_t Address, const void *Decoder) {
3162 Inst.addOperand(MCOperand::createImm(64 - Val));
3163 return MCDisassembler::Success;
3166 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3167 uint64_t Address, const void *Decoder) {
3168 DecodeStatus S = MCDisassembler::Success;
3170 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3171 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3172 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3173 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3174 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3175 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3176 unsigned op = fieldFromInstruction(Insn, 6, 1);
3178 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3179 return MCDisassembler::Fail;
3181 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3182 return MCDisassembler::Fail; // Writeback
3185 switch (Inst.getOpcode()) {
3188 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3189 return MCDisassembler::Fail;
3192 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3193 return MCDisassembler::Fail;
3196 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3197 return MCDisassembler::Fail;
3202 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3203 uint64_t Address, const void *Decoder) {
3204 DecodeStatus S = MCDisassembler::Success;
3206 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3207 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3209 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3210 return MCDisassembler::Fail;
3212 switch(Inst.getOpcode()) {
3214 return MCDisassembler::Fail;
3216 break; // tADR does not explicitly represent the PC as an operand.
3218 Inst.addOperand(MCOperand::createReg(ARM::SP));
3222 Inst.addOperand(MCOperand::createImm(imm));
3226 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3227 uint64_t Address, const void *Decoder) {
3228 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3229 true, 2, Inst, Decoder))
3230 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3231 return MCDisassembler::Success;
3234 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3235 uint64_t Address, const void *Decoder) {
3236 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3237 true, 4, Inst, Decoder))
3238 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3239 return MCDisassembler::Success;
3242 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3243 uint64_t Address, const void *Decoder) {
3244 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3245 true, 2, Inst, Decoder))
3246 Inst.addOperand(MCOperand::createImm(Val << 1));
3247 return MCDisassembler::Success;
3250 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3251 uint64_t Address, const void *Decoder) {
3252 DecodeStatus S = MCDisassembler::Success;
3254 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3255 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3257 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3258 return MCDisassembler::Fail;
3259 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3260 return MCDisassembler::Fail;
3265 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3266 uint64_t Address, const void *Decoder) {
3267 DecodeStatus S = MCDisassembler::Success;
3269 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3270 unsigned imm = fieldFromInstruction(Val, 3, 5);
3272 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3273 return MCDisassembler::Fail;
3274 Inst.addOperand(MCOperand::createImm(imm));
3279 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3280 uint64_t Address, const void *Decoder) {
3281 unsigned imm = Val << 2;
3283 Inst.addOperand(MCOperand::createImm(imm));
3284 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3286 return MCDisassembler::Success;
3289 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3290 uint64_t Address, const void *Decoder) {
3291 Inst.addOperand(MCOperand::createReg(ARM::SP));
3292 Inst.addOperand(MCOperand::createImm(Val));
3294 return MCDisassembler::Success;
3297 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3298 uint64_t Address, const void *Decoder) {
3299 DecodeStatus S = MCDisassembler::Success;
3301 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3302 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3303 unsigned imm = fieldFromInstruction(Val, 0, 2);
3305 // Thumb stores cannot use PC as dest register.
3306 switch (Inst.getOpcode()) {
3311 return MCDisassembler::Fail;
3316 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3317 return MCDisassembler::Fail;
3318 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3319 return MCDisassembler::Fail;
3320 Inst.addOperand(MCOperand::createImm(imm));
3325 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3326 uint64_t Address, const void *Decoder) {
3327 DecodeStatus S = MCDisassembler::Success;
3329 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3330 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3332 const FeatureBitset &featureBits =
3333 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3335 bool hasMP = featureBits[ARM::FeatureMP];
3336 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3339 switch (Inst.getOpcode()) {
3341 Inst.setOpcode(ARM::t2LDRBpci);
3344 Inst.setOpcode(ARM::t2LDRHpci);
3347 Inst.setOpcode(ARM::t2LDRSHpci);
3350 Inst.setOpcode(ARM::t2LDRSBpci);
3353 Inst.setOpcode(ARM::t2LDRpci);
3356 Inst.setOpcode(ARM::t2PLDpci);
3359 Inst.setOpcode(ARM::t2PLIpci);
3362 return MCDisassembler::Fail;
3365 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3369 switch (Inst.getOpcode()) {
3371 return MCDisassembler::Fail;
3373 Inst.setOpcode(ARM::t2PLDWs);
3376 Inst.setOpcode(ARM::t2PLIs);
3382 switch (Inst.getOpcode()) {
3387 return MCDisassembler::Fail;
3390 if (!hasV7Ops || !hasMP)
3391 return MCDisassembler::Fail;
3394 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3395 return MCDisassembler::Fail;
3398 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3399 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3400 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3401 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3402 return MCDisassembler::Fail;
3407 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3408 uint64_t Address, const void* Decoder) {
3409 DecodeStatus S = MCDisassembler::Success;
3411 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3412 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3413 unsigned U = fieldFromInstruction(Insn, 9, 1);
3414 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3417 unsigned add = fieldFromInstruction(Insn, 9, 1);
3419 const FeatureBitset &featureBits =
3420 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3422 bool hasMP = featureBits[ARM::FeatureMP];
3423 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3426 switch (Inst.getOpcode()) {
3428 Inst.setOpcode(ARM::t2LDRpci);
3431 Inst.setOpcode(ARM::t2LDRBpci);
3433 case ARM::t2LDRSBi8:
3434 Inst.setOpcode(ARM::t2LDRSBpci);
3437 Inst.setOpcode(ARM::t2LDRHpci);
3439 case ARM::t2LDRSHi8:
3440 Inst.setOpcode(ARM::t2LDRSHpci);
3443 Inst.setOpcode(ARM::t2PLDpci);
3446 Inst.setOpcode(ARM::t2PLIpci);
3449 return MCDisassembler::Fail;
3451 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3455 switch (Inst.getOpcode()) {
3456 case ARM::t2LDRSHi8:
3457 return MCDisassembler::Fail;
3460 Inst.setOpcode(ARM::t2PLDWi8);
3462 case ARM::t2LDRSBi8:
3463 Inst.setOpcode(ARM::t2PLIi8);
3470 switch (Inst.getOpcode()) {
3475 return MCDisassembler::Fail;
3478 if (!hasV7Ops || !hasMP)
3479 return MCDisassembler::Fail;
3482 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3483 return MCDisassembler::Fail;
3486 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3487 return MCDisassembler::Fail;
3491 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3492 uint64_t Address, const void* Decoder) {
3493 DecodeStatus S = MCDisassembler::Success;
3495 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3496 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3497 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3500 const FeatureBitset &featureBits =
3501 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3503 bool hasMP = featureBits[ARM::FeatureMP];
3504 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3507 switch (Inst.getOpcode()) {
3509 Inst.setOpcode(ARM::t2LDRpci);
3511 case ARM::t2LDRHi12:
3512 Inst.setOpcode(ARM::t2LDRHpci);
3514 case ARM::t2LDRSHi12:
3515 Inst.setOpcode(ARM::t2LDRSHpci);
3517 case ARM::t2LDRBi12:
3518 Inst.setOpcode(ARM::t2LDRBpci);
3520 case ARM::t2LDRSBi12:
3521 Inst.setOpcode(ARM::t2LDRSBpci);
3524 Inst.setOpcode(ARM::t2PLDpci);
3527 Inst.setOpcode(ARM::t2PLIpci);
3530 return MCDisassembler::Fail;
3532 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3536 switch (Inst.getOpcode()) {
3537 case ARM::t2LDRSHi12:
3538 return MCDisassembler::Fail;
3539 case ARM::t2LDRHi12:
3540 Inst.setOpcode(ARM::t2PLDWi12);
3542 case ARM::t2LDRSBi12:
3543 Inst.setOpcode(ARM::t2PLIi12);
3550 switch (Inst.getOpcode()) {
3555 return MCDisassembler::Fail;
3557 case ARM::t2PLDWi12:
3558 if (!hasV7Ops || !hasMP)
3559 return MCDisassembler::Fail;
3562 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3563 return MCDisassembler::Fail;
3566 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3567 return MCDisassembler::Fail;
3571 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3572 uint64_t Address, const void* Decoder) {
3573 DecodeStatus S = MCDisassembler::Success;
3575 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3576 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3577 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3581 switch (Inst.getOpcode()) {
3583 Inst.setOpcode(ARM::t2LDRpci);
3586 Inst.setOpcode(ARM::t2LDRBpci);
3589 Inst.setOpcode(ARM::t2LDRHpci);
3592 Inst.setOpcode(ARM::t2LDRSBpci);
3595 Inst.setOpcode(ARM::t2LDRSHpci);
3598 return MCDisassembler::Fail;
3600 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3603 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3604 return MCDisassembler::Fail;
3605 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3606 return MCDisassembler::Fail;
3610 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3611 uint64_t Address, const void* Decoder) {
3612 DecodeStatus S = MCDisassembler::Success;
3614 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3615 unsigned U = fieldFromInstruction(Insn, 23, 1);
3616 int imm = fieldFromInstruction(Insn, 0, 12);
3618 const FeatureBitset &featureBits =
3619 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3621 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3624 switch (Inst.getOpcode()) {
3625 case ARM::t2LDRBpci:
3626 case ARM::t2LDRHpci:
3627 Inst.setOpcode(ARM::t2PLDpci);
3629 case ARM::t2LDRSBpci:
3630 Inst.setOpcode(ARM::t2PLIpci);
3632 case ARM::t2LDRSHpci:
3633 return MCDisassembler::Fail;
3639 switch(Inst.getOpcode()) {
3644 return MCDisassembler::Fail;
3647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3648 return MCDisassembler::Fail;
3652 // Special case for #-0.
3658 Inst.addOperand(MCOperand::createImm(imm));
3663 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3664 uint64_t Address, const void *Decoder) {
3666 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3668 int imm = Val & 0xFF;
3670 if (!(Val & 0x100)) imm *= -1;
3671 Inst.addOperand(MCOperand::createImm(imm * 4));
3674 return MCDisassembler::Success;
3677 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3678 uint64_t Address, const void *Decoder) {
3679 DecodeStatus S = MCDisassembler::Success;
3681 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3682 unsigned imm = fieldFromInstruction(Val, 0, 9);
3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3685 return MCDisassembler::Fail;
3686 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3687 return MCDisassembler::Fail;
3692 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3693 uint64_t Address, const void *Decoder) {
3694 DecodeStatus S = MCDisassembler::Success;
3696 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3697 unsigned imm = fieldFromInstruction(Val, 0, 8);
3699 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3700 return MCDisassembler::Fail;
3702 Inst.addOperand(MCOperand::createImm(imm));
3707 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3708 uint64_t Address, const void *Decoder) {
3709 int imm = Val & 0xFF;
3712 else if (!(Val & 0x100))
3714 Inst.addOperand(MCOperand::createImm(imm));
3716 return MCDisassembler::Success;
3720 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3721 uint64_t Address, const void *Decoder) {
3722 DecodeStatus S = MCDisassembler::Success;
3724 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3725 unsigned imm = fieldFromInstruction(Val, 0, 9);
3727 // Thumb stores cannot use PC as dest register.
3728 switch (Inst.getOpcode()) {
3736 return MCDisassembler::Fail;
3742 // Some instructions always use an additive offset.
3743 switch (Inst.getOpcode()) {
3758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3759 return MCDisassembler::Fail;
3760 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3761 return MCDisassembler::Fail;
3766 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3767 uint64_t Address, const void *Decoder) {
3768 DecodeStatus S = MCDisassembler::Success;
3770 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3771 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3772 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3773 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3775 unsigned load = fieldFromInstruction(Insn, 20, 1);
3778 switch (Inst.getOpcode()) {
3779 case ARM::t2LDR_PRE:
3780 case ARM::t2LDR_POST:
3781 Inst.setOpcode(ARM::t2LDRpci);
3783 case ARM::t2LDRB_PRE:
3784 case ARM::t2LDRB_POST:
3785 Inst.setOpcode(ARM::t2LDRBpci);
3787 case ARM::t2LDRH_PRE:
3788 case ARM::t2LDRH_POST:
3789 Inst.setOpcode(ARM::t2LDRHpci);
3791 case ARM::t2LDRSB_PRE:
3792 case ARM::t2LDRSB_POST:
3794 Inst.setOpcode(ARM::t2PLIpci);
3796 Inst.setOpcode(ARM::t2LDRSBpci);
3798 case ARM::t2LDRSH_PRE:
3799 case ARM::t2LDRSH_POST:
3800 Inst.setOpcode(ARM::t2LDRSHpci);
3803 return MCDisassembler::Fail;
3805 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3810 return MCDisassembler::Fail;
3813 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3814 return MCDisassembler::Fail;
3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3818 return MCDisassembler::Fail;
3821 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3822 return MCDisassembler::Fail;
3827 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3828 uint64_t Address, const void *Decoder) {
3829 DecodeStatus S = MCDisassembler::Success;
3831 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3832 unsigned imm = fieldFromInstruction(Val, 0, 12);
3834 // Thumb stores cannot use PC as dest register.
3835 switch (Inst.getOpcode()) {
3837 case ARM::t2STRBi12:
3838 case ARM::t2STRHi12:
3840 return MCDisassembler::Fail;
3845 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3846 return MCDisassembler::Fail;
3847 Inst.addOperand(MCOperand::createImm(imm));
3853 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3854 uint64_t Address, const void *Decoder) {
3855 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3857 Inst.addOperand(MCOperand::createReg(ARM::SP));
3858 Inst.addOperand(MCOperand::createReg(ARM::SP));
3859 Inst.addOperand(MCOperand::createImm(imm));
3861 return MCDisassembler::Success;
3864 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3865 uint64_t Address, const void *Decoder) {
3866 DecodeStatus S = MCDisassembler::Success;
3868 if (Inst.getOpcode() == ARM::tADDrSP) {
3869 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3870 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3873 return MCDisassembler::Fail;
3874 Inst.addOperand(MCOperand::createReg(ARM::SP));
3875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3876 return MCDisassembler::Fail;
3877 } else if (Inst.getOpcode() == ARM::tADDspr) {
3878 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3880 Inst.addOperand(MCOperand::createReg(ARM::SP));
3881 Inst.addOperand(MCOperand::createReg(ARM::SP));
3882 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3883 return MCDisassembler::Fail;
3889 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3890 uint64_t Address, const void *Decoder) {
3891 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3892 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3894 Inst.addOperand(MCOperand::createImm(imod));
3895 Inst.addOperand(MCOperand::createImm(flags));
3897 return MCDisassembler::Success;
3900 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3901 uint64_t Address, const void *Decoder) {
3902 DecodeStatus S = MCDisassembler::Success;
3903 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3904 unsigned add = fieldFromInstruction(Insn, 4, 1);
3906 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3907 return MCDisassembler::Fail;
3908 Inst.addOperand(MCOperand::createImm(add));
3913 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3914 uint64_t Address, const void *Decoder) {
3915 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3916 // Note only one trailing zero not two. Also the J1 and J2 values are from
3917 // the encoded instruction. So here change to I1 and I2 values via:
3918 // I1 = NOT(J1 EOR S);
3919 // I2 = NOT(J2 EOR S);
3920 // and build the imm32 with two trailing zeros as documented:
3921 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3922 unsigned S = (Val >> 23) & 1;
3923 unsigned J1 = (Val >> 22) & 1;
3924 unsigned J2 = (Val >> 21) & 1;
3925 unsigned I1 = !(J1 ^ S);
3926 unsigned I2 = !(J2 ^ S);
3927 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3928 int imm32 = SignExtend32<25>(tmp << 1);
3930 if (!tryAddingSymbolicOperand(Address,
3931 (Address & ~2u) + imm32 + 4,
3932 true, 4, Inst, Decoder))
3933 Inst.addOperand(MCOperand::createImm(imm32));
3934 return MCDisassembler::Success;
3937 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3938 uint64_t Address, const void *Decoder) {
3939 if (Val == 0xA || Val == 0xB)
3940 return MCDisassembler::Fail;
3942 const FeatureBitset &featureBits =
3943 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3945 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3946 return MCDisassembler::Fail;
3948 Inst.addOperand(MCOperand::createImm(Val));
3949 return MCDisassembler::Success;
3953 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3954 uint64_t Address, const void *Decoder) {
3955 DecodeStatus S = MCDisassembler::Success;
3957 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3958 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3960 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3961 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3962 return MCDisassembler::Fail;
3963 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3964 return MCDisassembler::Fail;
3969 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3970 uint64_t Address, const void *Decoder) {
3971 DecodeStatus S = MCDisassembler::Success;
3973 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3974 if (pred == 0xE || pred == 0xF) {
3975 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3978 return MCDisassembler::Fail;
3980 Inst.setOpcode(ARM::t2DSB);
3983 Inst.setOpcode(ARM::t2DMB);
3986 Inst.setOpcode(ARM::t2ISB);
3990 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3991 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3994 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3995 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3996 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3997 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3998 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
4000 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4001 return MCDisassembler::Fail;
4002 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4003 return MCDisassembler::Fail;
4008 // Decode a shifted immediate operand. These basically consist
4009 // of an 8-bit value, and a 4-bit directive that specifies either
4010 // a splat operation or a rotation.
4011 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
4012 uint64_t Address, const void *Decoder) {
4013 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
4015 unsigned byte = fieldFromInstruction(Val, 8, 2);
4016 unsigned imm = fieldFromInstruction(Val, 0, 8);
4019 Inst.addOperand(MCOperand::createImm(imm));
4022 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4025 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4028 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4033 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4034 unsigned rot = fieldFromInstruction(Val, 7, 5);
4035 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4036 Inst.addOperand(MCOperand::createImm(imm));
4039 return MCDisassembler::Success;
4043 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4044 uint64_t Address, const void *Decoder){
4045 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4046 true, 2, Inst, Decoder))
4047 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4048 return MCDisassembler::Success;
4051 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4052 uint64_t Address, const void *Decoder){
4053 // Val is passed in as S:J1:J2:imm10:imm11
4054 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4055 // the encoded instruction. So here change to I1 and I2 values via:
4056 // I1 = NOT(J1 EOR S);
4057 // I2 = NOT(J2 EOR S);
4058 // and build the imm32 with one trailing zero as documented:
4059 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4060 unsigned S = (Val >> 23) & 1;
4061 unsigned J1 = (Val >> 22) & 1;
4062 unsigned J2 = (Val >> 21) & 1;
4063 unsigned I1 = !(J1 ^ S);
4064 unsigned I2 = !(J2 ^ S);
4065 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4066 int imm32 = SignExtend32<25>(tmp << 1);
4068 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4069 true, 4, Inst, Decoder))
4070 Inst.addOperand(MCOperand::createImm(imm32));
4071 return MCDisassembler::Success;
4074 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4075 uint64_t Address, const void *Decoder) {
4077 return MCDisassembler::Fail;
4079 Inst.addOperand(MCOperand::createImm(Val));
4080 return MCDisassembler::Success;
4083 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4084 uint64_t Address, const void *Decoder) {
4086 return MCDisassembler::Fail;
4088 Inst.addOperand(MCOperand::createImm(Val));
4089 return MCDisassembler::Success;
4092 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4093 uint64_t Address, const void *Decoder) {
4094 DecodeStatus S = MCDisassembler::Success;
4095 const FeatureBitset &FeatureBits =
4096 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4098 if (FeatureBits[ARM::FeatureMClass]) {
4099 unsigned ValLow = Val & 0xff;
4101 // Validate the SYSm value first.
4116 case 18: // basepri_max
4117 case 19: // faultmask
4118 if (!(FeatureBits[ARM::HasV7Ops]))
4119 // Values basepri, basepri_max and faultmask are only valid for v7m.
4120 return MCDisassembler::Fail;
4123 return MCDisassembler::Fail;
4126 if (Inst.getOpcode() == ARM::t2MSR_M) {
4127 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4128 if (!(FeatureBits[ARM::HasV7Ops])) {
4129 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4132 S = MCDisassembler::SoftFail;
4135 // The ARMv7-M architecture stores an additional 2-bit mask value in
4136 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4137 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4138 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4139 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4140 // only if the processor includes the DSP extension.
4141 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4142 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4143 S = MCDisassembler::SoftFail;
4149 return MCDisassembler::Fail;
4151 Inst.addOperand(MCOperand::createImm(Val));
4155 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4156 uint64_t Address, const void *Decoder) {
4158 unsigned R = fieldFromInstruction(Val, 5, 1);
4159 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4161 // The table of encodings for these banked registers comes from B9.2.3 of the
4162 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4163 // neater. So by fiat, these values are UNPREDICTABLE:
4165 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4166 SysM == 0x1a || SysM == 0x1b)
4167 return MCDisassembler::SoftFail;
4169 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4170 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4171 return MCDisassembler::SoftFail;
4174 Inst.addOperand(MCOperand::createImm(Val));
4175 return MCDisassembler::Success;
4178 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4179 uint64_t Address, const void *Decoder) {
4180 DecodeStatus S = MCDisassembler::Success;
4182 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4183 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4184 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4187 S = MCDisassembler::SoftFail;
4189 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4190 return MCDisassembler::Fail;
4191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4192 return MCDisassembler::Fail;
4193 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4194 return MCDisassembler::Fail;
4199 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4200 uint64_t Address, const void *Decoder){
4201 DecodeStatus S = MCDisassembler::Success;
4203 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4204 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4205 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4206 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4208 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4209 return MCDisassembler::Fail;
4211 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4212 S = MCDisassembler::SoftFail;
4214 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4215 return MCDisassembler::Fail;
4216 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4217 return MCDisassembler::Fail;
4218 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4219 return MCDisassembler::Fail;
4224 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4225 uint64_t Address, const void *Decoder) {
4226 DecodeStatus S = MCDisassembler::Success;
4228 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4229 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4230 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4231 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4232 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4233 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4235 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4237 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4238 return MCDisassembler::Fail;
4239 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4240 return MCDisassembler::Fail;
4241 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4242 return MCDisassembler::Fail;
4243 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4244 return MCDisassembler::Fail;
4249 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4250 uint64_t Address, const void *Decoder) {
4251 DecodeStatus S = MCDisassembler::Success;
4253 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4254 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4255 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4256 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4257 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4258 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4259 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4261 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4262 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4264 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4265 return MCDisassembler::Fail;
4266 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4267 return MCDisassembler::Fail;
4268 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4269 return MCDisassembler::Fail;
4270 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4271 return MCDisassembler::Fail;
4277 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4278 uint64_t Address, const void *Decoder) {
4279 DecodeStatus S = MCDisassembler::Success;
4281 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4282 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4283 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4284 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4285 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4286 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4288 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4291 return MCDisassembler::Fail;
4292 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4293 return MCDisassembler::Fail;
4294 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4295 return MCDisassembler::Fail;
4296 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4297 return MCDisassembler::Fail;
4302 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4303 uint64_t Address, const void *Decoder) {
4304 DecodeStatus S = MCDisassembler::Success;
4306 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4307 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4308 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4309 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4310 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4311 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4313 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4316 return MCDisassembler::Fail;
4317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4318 return MCDisassembler::Fail;
4319 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4320 return MCDisassembler::Fail;
4321 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4322 return MCDisassembler::Fail;
4327 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4328 uint64_t Address, const void *Decoder) {
4329 DecodeStatus S = MCDisassembler::Success;
4331 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4332 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4333 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4334 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4335 unsigned size = fieldFromInstruction(Insn, 10, 2);
4341 return MCDisassembler::Fail;
4343 if (fieldFromInstruction(Insn, 4, 1))
4344 return MCDisassembler::Fail; // UNDEFINED
4345 index = fieldFromInstruction(Insn, 5, 3);
4348 if (fieldFromInstruction(Insn, 5, 1))
4349 return MCDisassembler::Fail; // UNDEFINED
4350 index = fieldFromInstruction(Insn, 6, 2);
4351 if (fieldFromInstruction(Insn, 4, 1))
4355 if (fieldFromInstruction(Insn, 6, 1))
4356 return MCDisassembler::Fail; // UNDEFINED
4357 index = fieldFromInstruction(Insn, 7, 1);
4359 switch (fieldFromInstruction(Insn, 4, 2)) {
4365 return MCDisassembler::Fail;
4370 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4371 return MCDisassembler::Fail;
4372 if (Rm != 0xF) { // Writeback
4373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4374 return MCDisassembler::Fail;
4376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4377 return MCDisassembler::Fail;
4378 Inst.addOperand(MCOperand::createImm(align));
4381 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4382 return MCDisassembler::Fail;
4384 Inst.addOperand(MCOperand::createReg(0));
4387 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4388 return MCDisassembler::Fail;
4389 Inst.addOperand(MCOperand::createImm(index));
4394 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4395 uint64_t Address, const void *Decoder) {
4396 DecodeStatus S = MCDisassembler::Success;
4398 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4399 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4400 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4401 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4402 unsigned size = fieldFromInstruction(Insn, 10, 2);
4408 return MCDisassembler::Fail;
4410 if (fieldFromInstruction(Insn, 4, 1))
4411 return MCDisassembler::Fail; // UNDEFINED
4412 index = fieldFromInstruction(Insn, 5, 3);
4415 if (fieldFromInstruction(Insn, 5, 1))
4416 return MCDisassembler::Fail; // UNDEFINED
4417 index = fieldFromInstruction(Insn, 6, 2);
4418 if (fieldFromInstruction(Insn, 4, 1))
4422 if (fieldFromInstruction(Insn, 6, 1))
4423 return MCDisassembler::Fail; // UNDEFINED
4424 index = fieldFromInstruction(Insn, 7, 1);
4426 switch (fieldFromInstruction(Insn, 4, 2)) {
4432 return MCDisassembler::Fail;
4437 if (Rm != 0xF) { // Writeback
4438 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4439 return MCDisassembler::Fail;
4441 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4442 return MCDisassembler::Fail;
4443 Inst.addOperand(MCOperand::createImm(align));
4446 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4447 return MCDisassembler::Fail;
4449 Inst.addOperand(MCOperand::createReg(0));
4452 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4453 return MCDisassembler::Fail;
4454 Inst.addOperand(MCOperand::createImm(index));
4460 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4461 uint64_t Address, const void *Decoder) {
4462 DecodeStatus S = MCDisassembler::Success;
4464 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4465 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4466 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4467 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4468 unsigned size = fieldFromInstruction(Insn, 10, 2);
4475 return MCDisassembler::Fail;
4477 index = fieldFromInstruction(Insn, 5, 3);
4478 if (fieldFromInstruction(Insn, 4, 1))
4482 index = fieldFromInstruction(Insn, 6, 2);
4483 if (fieldFromInstruction(Insn, 4, 1))
4485 if (fieldFromInstruction(Insn, 5, 1))
4489 if (fieldFromInstruction(Insn, 5, 1))
4490 return MCDisassembler::Fail; // UNDEFINED
4491 index = fieldFromInstruction(Insn, 7, 1);
4492 if (fieldFromInstruction(Insn, 4, 1) != 0)
4494 if (fieldFromInstruction(Insn, 6, 1))
4499 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4500 return MCDisassembler::Fail;
4501 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4502 return MCDisassembler::Fail;
4503 if (Rm != 0xF) { // Writeback
4504 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4505 return MCDisassembler::Fail;
4507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4508 return MCDisassembler::Fail;
4509 Inst.addOperand(MCOperand::createImm(align));
4512 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4513 return MCDisassembler::Fail;
4515 Inst.addOperand(MCOperand::createReg(0));
4518 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4519 return MCDisassembler::Fail;
4520 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4521 return MCDisassembler::Fail;
4522 Inst.addOperand(MCOperand::createImm(index));
4527 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4528 uint64_t Address, const void *Decoder) {
4529 DecodeStatus S = MCDisassembler::Success;
4531 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4532 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4533 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4534 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4535 unsigned size = fieldFromInstruction(Insn, 10, 2);
4542 return MCDisassembler::Fail;
4544 index = fieldFromInstruction(Insn, 5, 3);
4545 if (fieldFromInstruction(Insn, 4, 1))
4549 index = fieldFromInstruction(Insn, 6, 2);
4550 if (fieldFromInstruction(Insn, 4, 1))
4552 if (fieldFromInstruction(Insn, 5, 1))
4556 if (fieldFromInstruction(Insn, 5, 1))
4557 return MCDisassembler::Fail; // UNDEFINED
4558 index = fieldFromInstruction(Insn, 7, 1);
4559 if (fieldFromInstruction(Insn, 4, 1) != 0)
4561 if (fieldFromInstruction(Insn, 6, 1))
4566 if (Rm != 0xF) { // Writeback
4567 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4568 return MCDisassembler::Fail;
4570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4571 return MCDisassembler::Fail;
4572 Inst.addOperand(MCOperand::createImm(align));
4575 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4576 return MCDisassembler::Fail;
4578 Inst.addOperand(MCOperand::createReg(0));
4581 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4582 return MCDisassembler::Fail;
4583 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4584 return MCDisassembler::Fail;
4585 Inst.addOperand(MCOperand::createImm(index));
4591 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4592 uint64_t Address, const void *Decoder) {
4593 DecodeStatus S = MCDisassembler::Success;
4595 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4596 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4597 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4598 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4599 unsigned size = fieldFromInstruction(Insn, 10, 2);
4606 return MCDisassembler::Fail;
4608 if (fieldFromInstruction(Insn, 4, 1))
4609 return MCDisassembler::Fail; // UNDEFINED
4610 index = fieldFromInstruction(Insn, 5, 3);
4613 if (fieldFromInstruction(Insn, 4, 1))
4614 return MCDisassembler::Fail; // UNDEFINED
4615 index = fieldFromInstruction(Insn, 6, 2);
4616 if (fieldFromInstruction(Insn, 5, 1))
4620 if (fieldFromInstruction(Insn, 4, 2))
4621 return MCDisassembler::Fail; // UNDEFINED
4622 index = fieldFromInstruction(Insn, 7, 1);
4623 if (fieldFromInstruction(Insn, 6, 1))
4628 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4629 return MCDisassembler::Fail;
4630 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4631 return MCDisassembler::Fail;
4632 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4633 return MCDisassembler::Fail;
4635 if (Rm != 0xF) { // Writeback
4636 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4637 return MCDisassembler::Fail;
4639 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4640 return MCDisassembler::Fail;
4641 Inst.addOperand(MCOperand::createImm(align));
4644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4645 return MCDisassembler::Fail;
4647 Inst.addOperand(MCOperand::createReg(0));
4650 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4651 return MCDisassembler::Fail;
4652 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4653 return MCDisassembler::Fail;
4654 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4655 return MCDisassembler::Fail;
4656 Inst.addOperand(MCOperand::createImm(index));
4661 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4662 uint64_t Address, const void *Decoder) {
4663 DecodeStatus S = MCDisassembler::Success;
4665 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4666 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4667 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4668 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4669 unsigned size = fieldFromInstruction(Insn, 10, 2);
4676 return MCDisassembler::Fail;
4678 if (fieldFromInstruction(Insn, 4, 1))
4679 return MCDisassembler::Fail; // UNDEFINED
4680 index = fieldFromInstruction(Insn, 5, 3);
4683 if (fieldFromInstruction(Insn, 4, 1))
4684 return MCDisassembler::Fail; // UNDEFINED
4685 index = fieldFromInstruction(Insn, 6, 2);
4686 if (fieldFromInstruction(Insn, 5, 1))
4690 if (fieldFromInstruction(Insn, 4, 2))
4691 return MCDisassembler::Fail; // UNDEFINED
4692 index = fieldFromInstruction(Insn, 7, 1);
4693 if (fieldFromInstruction(Insn, 6, 1))
4698 if (Rm != 0xF) { // Writeback
4699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4700 return MCDisassembler::Fail;
4702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4703 return MCDisassembler::Fail;
4704 Inst.addOperand(MCOperand::createImm(align));
4707 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4708 return MCDisassembler::Fail;
4710 Inst.addOperand(MCOperand::createReg(0));
4713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4714 return MCDisassembler::Fail;
4715 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4716 return MCDisassembler::Fail;
4717 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4718 return MCDisassembler::Fail;
4719 Inst.addOperand(MCOperand::createImm(index));
4725 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4726 uint64_t Address, const void *Decoder) {
4727 DecodeStatus S = MCDisassembler::Success;
4729 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4730 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4731 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4732 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4733 unsigned size = fieldFromInstruction(Insn, 10, 2);
4740 return MCDisassembler::Fail;
4742 if (fieldFromInstruction(Insn, 4, 1))
4744 index = fieldFromInstruction(Insn, 5, 3);
4747 if (fieldFromInstruction(Insn, 4, 1))
4749 index = fieldFromInstruction(Insn, 6, 2);
4750 if (fieldFromInstruction(Insn, 5, 1))
4754 switch (fieldFromInstruction(Insn, 4, 2)) {
4758 return MCDisassembler::Fail;
4760 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4763 index = fieldFromInstruction(Insn, 7, 1);
4764 if (fieldFromInstruction(Insn, 6, 1))
4769 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4770 return MCDisassembler::Fail;
4771 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4772 return MCDisassembler::Fail;
4773 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4774 return MCDisassembler::Fail;
4775 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4776 return MCDisassembler::Fail;
4778 if (Rm != 0xF) { // Writeback
4779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4780 return MCDisassembler::Fail;
4782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4783 return MCDisassembler::Fail;
4784 Inst.addOperand(MCOperand::createImm(align));
4787 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4788 return MCDisassembler::Fail;
4790 Inst.addOperand(MCOperand::createReg(0));
4793 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4794 return MCDisassembler::Fail;
4795 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4796 return MCDisassembler::Fail;
4797 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4798 return MCDisassembler::Fail;
4799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4800 return MCDisassembler::Fail;
4801 Inst.addOperand(MCOperand::createImm(index));
4806 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4807 uint64_t Address, const void *Decoder) {
4808 DecodeStatus S = MCDisassembler::Success;
4810 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4811 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4812 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4813 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4814 unsigned size = fieldFromInstruction(Insn, 10, 2);
4821 return MCDisassembler::Fail;
4823 if (fieldFromInstruction(Insn, 4, 1))
4825 index = fieldFromInstruction(Insn, 5, 3);
4828 if (fieldFromInstruction(Insn, 4, 1))
4830 index = fieldFromInstruction(Insn, 6, 2);
4831 if (fieldFromInstruction(Insn, 5, 1))
4835 switch (fieldFromInstruction(Insn, 4, 2)) {
4839 return MCDisassembler::Fail;
4841 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4844 index = fieldFromInstruction(Insn, 7, 1);
4845 if (fieldFromInstruction(Insn, 6, 1))
4850 if (Rm != 0xF) { // Writeback
4851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4852 return MCDisassembler::Fail;
4854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4855 return MCDisassembler::Fail;
4856 Inst.addOperand(MCOperand::createImm(align));
4859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4860 return MCDisassembler::Fail;
4862 Inst.addOperand(MCOperand::createReg(0));
4865 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4866 return MCDisassembler::Fail;
4867 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4868 return MCDisassembler::Fail;
4869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4870 return MCDisassembler::Fail;
4871 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4872 return MCDisassembler::Fail;
4873 Inst.addOperand(MCOperand::createImm(index));
4878 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4879 uint64_t Address, const void *Decoder) {
4880 DecodeStatus S = MCDisassembler::Success;
4881 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4882 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4883 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4884 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4885 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4887 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4888 S = MCDisassembler::SoftFail;
4890 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4891 return MCDisassembler::Fail;
4892 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4893 return MCDisassembler::Fail;
4894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4895 return MCDisassembler::Fail;
4896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4897 return MCDisassembler::Fail;
4898 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4899 return MCDisassembler::Fail;
4904 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4905 uint64_t Address, const void *Decoder) {
4906 DecodeStatus S = MCDisassembler::Success;
4907 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4908 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4909 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4910 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4911 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4913 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4914 S = MCDisassembler::SoftFail;
4916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4917 return MCDisassembler::Fail;
4918 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4919 return MCDisassembler::Fail;
4920 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4921 return MCDisassembler::Fail;
4922 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4923 return MCDisassembler::Fail;
4924 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4925 return MCDisassembler::Fail;
4930 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4931 uint64_t Address, const void *Decoder) {
4932 DecodeStatus S = MCDisassembler::Success;
4933 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4934 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4938 S = MCDisassembler::SoftFail;
4942 return MCDisassembler::Fail;
4944 Inst.addOperand(MCOperand::createImm(pred));
4945 Inst.addOperand(MCOperand::createImm(mask));
4950 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4951 uint64_t Address, const void *Decoder) {
4952 DecodeStatus S = MCDisassembler::Success;
4954 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4955 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4956 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4957 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4958 unsigned W = fieldFromInstruction(Insn, 21, 1);
4959 unsigned U = fieldFromInstruction(Insn, 23, 1);
4960 unsigned P = fieldFromInstruction(Insn, 24, 1);
4961 bool writeback = (W == 1) | (P == 0);
4963 addr |= (U << 8) | (Rn << 9);
4965 if (writeback && (Rn == Rt || Rn == Rt2))
4966 Check(S, MCDisassembler::SoftFail);
4968 Check(S, MCDisassembler::SoftFail);
4971 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4972 return MCDisassembler::Fail;
4974 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4975 return MCDisassembler::Fail;
4976 // Writeback operand
4977 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4978 return MCDisassembler::Fail;
4980 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4981 return MCDisassembler::Fail;
4987 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4988 uint64_t Address, const void *Decoder) {
4989 DecodeStatus S = MCDisassembler::Success;
4991 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4992 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4993 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4994 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4995 unsigned W = fieldFromInstruction(Insn, 21, 1);
4996 unsigned U = fieldFromInstruction(Insn, 23, 1);
4997 unsigned P = fieldFromInstruction(Insn, 24, 1);
4998 bool writeback = (W == 1) | (P == 0);
5000 addr |= (U << 8) | (Rn << 9);
5002 if (writeback && (Rn == Rt || Rn == Rt2))
5003 Check(S, MCDisassembler::SoftFail);
5005 // Writeback operand
5006 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5007 return MCDisassembler::Fail;
5009 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5010 return MCDisassembler::Fail;
5012 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5013 return MCDisassembler::Fail;
5015 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5016 return MCDisassembler::Fail;
5021 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
5022 uint64_t Address, const void *Decoder) {
5023 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
5024 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
5025 if (sign1 != sign2) return MCDisassembler::Fail;
5027 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5028 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5029 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5031 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5033 return MCDisassembler::Success;
5036 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5038 const void *Decoder) {
5039 DecodeStatus S = MCDisassembler::Success;
5041 // Shift of "asr #32" is not allowed in Thumb2 mode.
5042 if (Val == 0x20) S = MCDisassembler::Fail;
5043 Inst.addOperand(MCOperand::createImm(Val));
5047 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5048 uint64_t Address, const void *Decoder) {
5049 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5050 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5051 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5052 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5055 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5057 DecodeStatus S = MCDisassembler::Success;
5059 if (Rt == Rn || Rn == Rt2)
5060 S = MCDisassembler::SoftFail;
5062 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5063 return MCDisassembler::Fail;
5064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5065 return MCDisassembler::Fail;
5066 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5067 return MCDisassembler::Fail;
5068 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5069 return MCDisassembler::Fail;
5074 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5075 uint64_t Address, const void *Decoder) {
5076 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5077 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5078 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5079 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5080 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5081 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5082 unsigned op = fieldFromInstruction(Insn, 5, 1);
5084 DecodeStatus S = MCDisassembler::Success;
5086 // VMOVv2f32 is ambiguous with these decodings.
5087 if (!(imm & 0x38) && cmode == 0xF) {
5088 if (op == 1) return MCDisassembler::Fail;
5089 Inst.setOpcode(ARM::VMOVv2f32);
5090 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5093 if (!(imm & 0x20)) return MCDisassembler::Fail;
5095 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5096 return MCDisassembler::Fail;
5097 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5098 return MCDisassembler::Fail;
5099 Inst.addOperand(MCOperand::createImm(64 - imm));
5104 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5105 uint64_t Address, const void *Decoder) {
5106 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5107 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5108 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5109 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5110 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5111 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5112 unsigned op = fieldFromInstruction(Insn, 5, 1);
5114 DecodeStatus S = MCDisassembler::Success;
5116 // VMOVv4f32 is ambiguous with these decodings.
5117 if (!(imm & 0x38) && cmode == 0xF) {
5118 if (op == 1) return MCDisassembler::Fail;
5119 Inst.setOpcode(ARM::VMOVv4f32);
5120 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5123 if (!(imm & 0x20)) return MCDisassembler::Fail;
5125 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5126 return MCDisassembler::Fail;
5127 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5128 return MCDisassembler::Fail;
5129 Inst.addOperand(MCOperand::createImm(64 - imm));
5134 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5135 uint64_t Address, const void *Decoder) {
5136 DecodeStatus S = MCDisassembler::Success;
5138 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5139 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5140 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5141 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5142 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5144 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5145 S = MCDisassembler::SoftFail;
5147 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5148 return MCDisassembler::Fail;
5149 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5150 return MCDisassembler::Fail;
5151 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5152 return MCDisassembler::Fail;
5153 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5154 return MCDisassembler::Fail;
5155 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5156 return MCDisassembler::Fail;
5161 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
5162 uint64_t Address, const void *Decoder) {
5164 DecodeStatus S = MCDisassembler::Success;
5166 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5167 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5168 unsigned cop = fieldFromInstruction(Val, 8, 4);
5169 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5170 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5172 if ((cop & ~0x1) == 0xa)
5173 return MCDisassembler::Fail;
5176 S = MCDisassembler::SoftFail;
5178 Inst.addOperand(MCOperand::createImm(cop));
5179 Inst.addOperand(MCOperand::createImm(opc1));
5180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5181 return MCDisassembler::Fail;
5182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5183 return MCDisassembler::Fail;
5184 Inst.addOperand(MCOperand::createImm(CRm));