1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "ARMDisassembler.h"
14 #include "ARMRegisterInfo.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/EDInstInfo.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/MemoryObject.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/raw_ostream.h"
27 // Pull DecodeStatus and its enum values into the global namespace.
28 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
29 #define Success llvm::MCDisassembler::Success
30 #define Unpredictable llvm::MCDisassembler::SoftFail
31 #define Fail llvm::MCDisassembler::Fail
33 // Helper macro to perform setwise reduction of the current running status
34 // and another status, and return if the new status is Fail.
35 #define CHECK(S,X) do { \
36 S = (DecodeStatus) ((int)S & (X)); \
37 if (S == Fail) return Fail; \
40 // Forward declare these because the autogenerated code will reference them.
41 // Definitions are further down.
42 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43 uint64_t Address, const void *Decoder);
44 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
45 unsigned RegNo, uint64_t Address,
47 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
48 uint64_t Address, const void *Decoder);
49 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
50 uint64_t Address, const void *Decoder);
51 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52 uint64_t Address, const void *Decoder);
53 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
54 uint64_t Address, const void *Decoder);
55 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
56 uint64_t Address, const void *Decoder);
57 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
58 uint64_t Address, const void *Decoder);
59 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
63 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
64 uint64_t Address, const void *Decoder);
66 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
67 uint64_t Address, const void *Decoder);
68 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
69 uint64_t Address, const void *Decoder);
70 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
71 uint64_t Address, const void *Decoder);
72 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
73 uint64_t Address, const void *Decoder);
74 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
75 uint64_t Address, const void *Decoder);
76 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
77 uint64_t Address, const void *Decoder);
78 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
79 uint64_t Address, const void *Decoder);
81 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
82 uint64_t Address, const void *Decoder);
83 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
84 uint64_t Address, const void *Decoder);
85 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
89 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
90 uint64_t Address, const void *Decoder);
91 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
92 uint64_t Address, const void *Decoder);
93 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
94 uint64_t Address, const void *Decoder);
95 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
96 uint64_t Address, const void *Decoder);
98 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
101 const void *Decoder);
102 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
103 uint64_t Address, const void *Decoder);
104 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
105 uint64_t Address, const void *Decoder);
106 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
107 uint64_t Address, const void *Decoder);
108 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
109 uint64_t Address, const void *Decoder);
110 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
111 uint64_t Address, const void *Decoder);
112 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
113 uint64_t Address, const void *Decoder);
114 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
115 uint64_t Address, const void *Decoder);
116 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
117 uint64_t Address, const void *Decoder);
118 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
119 uint64_t Address, const void *Decoder);
120 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
121 uint64_t Address, const void *Decoder);
122 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
123 uint64_t Address, const void *Decoder);
124 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
125 uint64_t Address, const void *Decoder);
126 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
127 uint64_t Address, const void *Decoder);
128 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
129 uint64_t Address, const void *Decoder);
130 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
131 uint64_t Address, const void *Decoder);
132 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
133 uint64_t Address, const void *Decoder);
134 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
135 uint64_t Address, const void *Decoder);
136 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
137 uint64_t Address, const void *Decoder);
138 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
139 uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
141 uint64_t Address, const void *Decoder);
142 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
143 uint64_t Address, const void *Decoder);
144 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
145 uint64_t Address, const void *Decoder);
146 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
147 uint64_t Address, const void *Decoder);
148 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
149 uint64_t Address, const void *Decoder);
150 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
153 uint64_t Address, const void *Decoder);
154 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
157 uint64_t Address, const void *Decoder);
158 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
183 uint64_t Address, const void *Decoder);
185 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
186 uint64_t Address, const void *Decoder);
187 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
188 uint64_t Address, const void *Decoder);
189 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
190 uint64_t Address, const void *Decoder);
191 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
192 uint64_t Address, const void *Decoder);
193 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
194 uint64_t Address, const void *Decoder);
195 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
196 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Val,
234 uint64_t Address, const void *Decoder);
236 #include "ARMGenDisassemblerTables.inc"
237 #include "ARMGenInstrInfo.inc"
238 #include "ARMGenEDInfo.inc"
240 using namespace llvm;
242 static MCDisassembler *createARMDisassembler(const Target &T) {
243 return new ARMDisassembler;
246 static MCDisassembler *createThumbDisassembler(const Target &T) {
247 return new ThumbDisassembler;
250 EDInstInfo *ARMDisassembler::getEDInfo() const {
254 EDInstInfo *ThumbDisassembler::getEDInfo() const {
258 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
259 const MemoryObject &Region,
261 raw_ostream &os) const {
264 // We want to read exactly 4 bytes of data.
265 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
268 // Encoded as a small-endian 32-bit word in the stream.
269 uint32_t insn = (bytes[3] << 24) |
274 // Calling the auto-generated decoder function.
275 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
276 if (result != Fail) {
281 // Instructions that are shared between ARM and Thumb modes.
282 // FIXME: This shouldn't really exist. It's an artifact of the
283 // fact that we fail to encode a few instructions properly for Thumb.
285 result = decodeCommonInstruction32(MI, insn, Address, this);
286 if (result != Fail) {
291 // VFP and NEON instructions, similarly, are shared between ARM
294 result = decodeVFPInstruction32(MI, insn, Address, this);
295 if (result != Fail) {
301 result = decodeNEONDataInstruction32(MI, insn, Address, this);
302 if (result != Fail) {
304 // Add a fake predicate operand, because we share these instruction
305 // definitions with Thumb2 where these instructions are predicable.
306 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
311 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
312 if (result != Fail) {
314 // Add a fake predicate operand, because we share these instruction
315 // definitions with Thumb2 where these instructions are predicable.
316 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
321 result = decodeNEONDupInstruction32(MI, insn, Address, this);
322 if (result != Fail) {
324 // Add a fake predicate operand, because we share these instruction
325 // definitions with Thumb2 where these instructions are predicable.
326 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
336 extern MCInstrDesc ARMInsts[];
339 // Thumb1 instructions don't have explicit S bits. Rather, they
340 // implicitly set CPSR. Since it's not represented in the encoding, the
341 // auto-generated decoder won't inject the CPSR operand. We need to fix
342 // that as a post-pass.
343 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
344 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
345 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
346 MCInst::iterator I = MI.begin();
347 for (unsigned i = 0; i < NumOps; ++i, ++I) {
348 if (I == MI.end()) break;
349 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
350 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
351 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
356 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
359 // Most Thumb instructions don't have explicit predicates in the
360 // encoding, but rather get their predicates from IT context. We need
361 // to fix up the predicate operands using this context information as a
363 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
364 // A few instructions actually have predicates encoded in them. Don't
365 // try to overwrite it if we're seeing one of those.
366 switch (MI.getOpcode()) {
374 // If we're in an IT block, base the predicate on that. Otherwise,
375 // assume a predicate of AL.
377 if (!ITBlock.empty()) {
383 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
384 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
385 MCInst::iterator I = MI.begin();
386 for (unsigned i = 0; i < NumOps; ++i, ++I) {
387 if (I == MI.end()) break;
388 if (OpInfo[i].isPredicate()) {
389 I = MI.insert(I, MCOperand::CreateImm(CC));
392 MI.insert(I, MCOperand::CreateReg(0));
394 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
399 I = MI.insert(I, MCOperand::CreateImm(CC));
402 MI.insert(I, MCOperand::CreateReg(0));
404 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
407 // Thumb VFP instructions are a special case. Because we share their
408 // encodings between ARM and Thumb modes, and they are predicable in ARM
409 // mode, the auto-generated decoder will give them an (incorrect)
410 // predicate operand. We need to rewrite these operands based on the IT
411 // context as a post-pass.
412 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
414 if (!ITBlock.empty()) {
420 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
421 MCInst::iterator I = MI.begin();
422 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
423 for (unsigned i = 0; i < NumOps; ++i, ++I) {
424 if (OpInfo[i].isPredicate() ) {
430 I->setReg(ARM::CPSR);
436 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
437 const MemoryObject &Region,
439 raw_ostream &os) const {
442 // We want to read exactly 2 bytes of data.
443 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
446 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
447 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
448 if (result != Fail) {
450 AddThumbPredicate(MI);
455 result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
458 bool InITBlock = !ITBlock.empty();
459 AddThumbPredicate(MI);
460 AddThumb1SBit(MI, InITBlock);
465 result = decodeThumb2Instruction16(MI, insn16, Address, this);
466 if (result != Fail) {
468 AddThumbPredicate(MI);
470 // If we find an IT instruction, we need to parse its condition
471 // code and mask operands so that we can apply them correctly
472 // to the subsequent instructions.
473 if (MI.getOpcode() == ARM::t2IT) {
474 unsigned firstcond = MI.getOperand(0).getImm();
475 uint32_t mask = MI.getOperand(1).getImm();
476 unsigned zeros = CountTrailingZeros_32(mask);
479 for (unsigned i = 0; i < 4 - (zeros+1); ++i) {
480 if (firstcond ^ (mask & 1))
481 ITBlock.push_back(firstcond ^ 1);
483 ITBlock.push_back(firstcond);
486 ITBlock.push_back(firstcond);
492 // We want to read exactly 4 bytes of data.
493 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
496 uint32_t insn32 = (bytes[3] << 8) |
501 result = decodeThumbInstruction32(MI, insn32, Address, this);
502 if (result != Fail) {
504 bool InITBlock = ITBlock.size();
505 AddThumbPredicate(MI);
506 AddThumb1SBit(MI, InITBlock);
511 result = decodeThumb2Instruction32(MI, insn32, Address, this);
512 if (result != Fail) {
514 AddThumbPredicate(MI);
519 result = decodeCommonInstruction32(MI, insn32, Address, this);
520 if (result != Fail) {
522 AddThumbPredicate(MI);
527 result = decodeVFPInstruction32(MI, insn32, Address, this);
528 if (result != Fail) {
530 UpdateThumbVFPPredicate(MI);
535 result = decodeNEONDupInstruction32(MI, insn32, Address, this);
536 if (result != Fail) {
538 AddThumbPredicate(MI);
542 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
544 uint32_t NEONLdStInsn = insn32;
545 NEONLdStInsn &= 0xF0FFFFFF;
546 NEONLdStInsn |= 0x04000000;
547 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
548 if (result != Fail) {
550 AddThumbPredicate(MI);
555 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
557 uint32_t NEONDataInsn = insn32;
558 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
559 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
560 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
561 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
562 if (result != Fail) {
564 AddThumbPredicate(MI);
573 extern "C" void LLVMInitializeARMDisassembler() {
574 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
575 createARMDisassembler);
576 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
577 createThumbDisassembler);
580 static const unsigned GPRDecoderTable[] = {
581 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
582 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
583 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
584 ARM::R12, ARM::SP, ARM::LR, ARM::PC
587 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
588 uint64_t Address, const void *Decoder) {
592 unsigned Register = GPRDecoderTable[RegNo];
593 Inst.addOperand(MCOperand::CreateReg(Register));
598 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
599 uint64_t Address, const void *Decoder) {
600 if (RegNo == 15) return Fail;
601 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
604 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
605 uint64_t Address, const void *Decoder) {
608 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
611 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
612 uint64_t Address, const void *Decoder) {
613 unsigned Register = 0;
637 Inst.addOperand(MCOperand::CreateReg(Register));
641 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
642 uint64_t Address, const void *Decoder) {
643 if (RegNo == 13 || RegNo == 15) return Fail;
644 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
647 static const unsigned SPRDecoderTable[] = {
648 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
649 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
650 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
651 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
652 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
653 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
654 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
655 ARM::S28, ARM::S29, ARM::S30, ARM::S31
658 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
659 uint64_t Address, const void *Decoder) {
663 unsigned Register = SPRDecoderTable[RegNo];
664 Inst.addOperand(MCOperand::CreateReg(Register));
668 static const unsigned DPRDecoderTable[] = {
669 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
670 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
671 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
672 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
673 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
674 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
675 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
676 ARM::D28, ARM::D29, ARM::D30, ARM::D31
679 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
680 uint64_t Address, const void *Decoder) {
684 unsigned Register = DPRDecoderTable[RegNo];
685 Inst.addOperand(MCOperand::CreateReg(Register));
689 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
690 uint64_t Address, const void *Decoder) {
693 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
697 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
698 uint64_t Address, const void *Decoder) {
701 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
704 static const unsigned QPRDecoderTable[] = {
705 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
706 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
707 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
708 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
712 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
713 uint64_t Address, const void *Decoder) {
718 unsigned Register = QPRDecoderTable[RegNo];
719 Inst.addOperand(MCOperand::CreateReg(Register));
723 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
724 uint64_t Address, const void *Decoder) {
725 if (Val == 0xF) return Fail;
726 // AL predicate is not allowed on Thumb1 branches.
727 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
729 Inst.addOperand(MCOperand::CreateImm(Val));
730 if (Val == ARMCC::AL) {
731 Inst.addOperand(MCOperand::CreateReg(0));
733 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
737 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
738 uint64_t Address, const void *Decoder) {
740 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
742 Inst.addOperand(MCOperand::CreateReg(0));
746 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
747 uint64_t Address, const void *Decoder) {
748 uint32_t imm = Val & 0xFF;
749 uint32_t rot = (Val & 0xF00) >> 7;
750 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
751 Inst.addOperand(MCOperand::CreateImm(rot_imm));
755 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
756 uint64_t Address, const void *Decoder) {
758 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
762 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
763 uint64_t Address, const void *Decoder) {
764 DecodeStatus S = Success;
766 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
767 unsigned type = fieldFromInstruction32(Val, 5, 2);
768 unsigned imm = fieldFromInstruction32(Val, 7, 5);
770 // Register-immediate
771 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
773 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
789 if (Shift == ARM_AM::ror && imm == 0)
792 unsigned Op = Shift | (imm << 3);
793 Inst.addOperand(MCOperand::CreateImm(Op));
798 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
799 uint64_t Address, const void *Decoder) {
800 DecodeStatus S = Success;
802 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
803 unsigned type = fieldFromInstruction32(Val, 5, 2);
804 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
807 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
808 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));
810 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
826 Inst.addOperand(MCOperand::CreateImm(Shift));
831 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
832 uint64_t Address, const void *Decoder) {
833 DecodeStatus S = Success;
835 // Empty register lists are not allowed.
836 if (CountPopulation_32(Val) == 0) return Fail;
837 for (unsigned i = 0; i < 16; ++i) {
838 if (Val & (1 << i)) {
839 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));
846 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
847 uint64_t Address, const void *Decoder) {
848 DecodeStatus S = Success;
850 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
851 unsigned regs = Val & 0xFF;
853 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));
854 for (unsigned i = 0; i < (regs - 1); ++i) {
855 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));
861 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
862 uint64_t Address, const void *Decoder) {
863 DecodeStatus S = Success;
865 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
866 unsigned regs = (Val & 0xFF) / 2;
868 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));
869 for (unsigned i = 0; i < (regs - 1); ++i) {
870 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));
876 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
877 uint64_t Address, const void *Decoder) {
878 // This operand encodes a mask of contiguous zeros between a specified MSB
879 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
880 // the mask of all bits LSB-and-lower, and then xor them to create
881 // the mask of that's all ones on [msb, lsb]. Finally we not it to
882 // create the final mask.
883 unsigned msb = fieldFromInstruction32(Val, 5, 5);
884 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
885 uint32_t msb_mask = (1 << (msb+1)) - 1;
886 uint32_t lsb_mask = (1 << lsb) - 1;
887 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
891 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
892 uint64_t Address, const void *Decoder) {
893 DecodeStatus S = Success;
895 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
896 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
897 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
898 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
899 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
900 unsigned U = fieldFromInstruction32(Insn, 23, 1);
902 switch (Inst.getOpcode()) {
903 case ARM::LDC_OFFSET:
906 case ARM::LDC_OPTION:
907 case ARM::LDCL_OFFSET:
910 case ARM::LDCL_OPTION:
911 case ARM::STC_OFFSET:
914 case ARM::STC_OPTION:
915 case ARM::STCL_OFFSET:
918 case ARM::STCL_OPTION:
919 if (coproc == 0xA || coproc == 0xB)
926 Inst.addOperand(MCOperand::CreateImm(coproc));
927 Inst.addOperand(MCOperand::CreateImm(CRd));
928 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
929 switch (Inst.getOpcode()) {
930 case ARM::LDC_OPTION:
931 case ARM::LDCL_OPTION:
932 case ARM::LDC2_OPTION:
933 case ARM::LDC2L_OPTION:
934 case ARM::STC_OPTION:
935 case ARM::STCL_OPTION:
936 case ARM::STC2_OPTION:
937 case ARM::STC2L_OPTION:
940 case ARM::LDC2L_POST:
941 case ARM::STC2L_POST:
944 Inst.addOperand(MCOperand::CreateReg(0));
948 unsigned P = fieldFromInstruction32(Insn, 24, 1);
949 unsigned W = fieldFromInstruction32(Insn, 21, 1);
951 bool writeback = (P == 0) || (W == 1);
952 unsigned idx_mode = 0;
954 idx_mode = ARMII::IndexModePre;
955 else if (!P && writeback)
956 idx_mode = ARMII::IndexModePost;
958 switch (Inst.getOpcode()) {
961 case ARM::LDC2L_POST:
962 case ARM::STC2L_POST:
964 case ARM::LDC_OPTION:
965 case ARM::LDCL_OPTION:
966 case ARM::LDC2_OPTION:
967 case ARM::LDC2L_OPTION:
968 case ARM::STC_OPTION:
969 case ARM::STCL_OPTION:
970 case ARM::STC2_OPTION:
971 case ARM::STC2L_OPTION:
972 Inst.addOperand(MCOperand::CreateImm(imm));
976 Inst.addOperand(MCOperand::CreateImm(
977 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
979 Inst.addOperand(MCOperand::CreateImm(
980 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
984 switch (Inst.getOpcode()) {
985 case ARM::LDC_OFFSET:
988 case ARM::LDC_OPTION:
989 case ARM::LDCL_OFFSET:
992 case ARM::LDCL_OPTION:
993 case ARM::STC_OFFSET:
996 case ARM::STC_OPTION:
997 case ARM::STCL_OFFSET:
1000 case ARM::STCL_OPTION:
1001 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1011 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1012 uint64_t Address, const void *Decoder) {
1013 DecodeStatus S = Success;
1015 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1016 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1017 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1018 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1019 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1020 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1021 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1022 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1024 // On stores, the writeback operand precedes Rt.
1025 switch (Inst.getOpcode()) {
1026 case ARM::STR_POST_IMM:
1027 case ARM::STR_POST_REG:
1028 case ARM::STRB_POST_IMM:
1029 case ARM::STRB_POST_REG:
1030 case ARM::STRT_POST_REG:
1031 case ARM::STRT_POST_IMM:
1032 case ARM::STRBT_POST_REG:
1033 case ARM::STRBT_POST_IMM:
1034 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1040 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1042 // On loads, the writeback operand comes after Rt.
1043 switch (Inst.getOpcode()) {
1044 case ARM::LDR_POST_IMM:
1045 case ARM::LDR_POST_REG:
1046 case ARM::LDRB_POST_IMM:
1047 case ARM::LDRB_POST_REG:
1050 case ARM::LDRBT_POST_REG:
1051 case ARM::LDRBT_POST_IMM:
1052 case ARM::LDRT_POST_REG:
1053 case ARM::LDRT_POST_IMM:
1054 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1060 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1062 ARM_AM::AddrOpc Op = ARM_AM::add;
1063 if (!fieldFromInstruction32(Insn, 23, 1))
1066 bool writeback = (P == 0) || (W == 1);
1067 unsigned idx_mode = 0;
1069 idx_mode = ARMII::IndexModePre;
1070 else if (!P && writeback)
1071 idx_mode = ARMII::IndexModePost;
1073 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE
1076 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1077 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1078 switch( fieldFromInstruction32(Insn, 5, 2)) {
1094 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1095 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1097 Inst.addOperand(MCOperand::CreateImm(imm));
1099 Inst.addOperand(MCOperand::CreateReg(0));
1100 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1101 Inst.addOperand(MCOperand::CreateImm(tmp));
1104 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1109 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1110 uint64_t Address, const void *Decoder) {
1111 DecodeStatus S = Success;
1113 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1114 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1115 unsigned type = fieldFromInstruction32(Val, 5, 2);
1116 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1117 unsigned U = fieldFromInstruction32(Val, 12, 1);
1119 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1135 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1136 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1139 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1141 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1142 Inst.addOperand(MCOperand::CreateImm(shift));
1148 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1149 uint64_t Address, const void *Decoder) {
1150 DecodeStatus S = Success;
1152 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1153 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1154 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1155 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1156 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1157 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1158 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1159 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1160 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1162 bool writeback = (W == 1) | (P == 0);
1164 // For {LD,ST}RD, Rt must be even, else undefined.
1165 switch (Inst.getOpcode()) {
1168 case ARM::STRD_POST:
1171 case ARM::LDRD_POST:
1172 if (Rt & 0x1) return Fail;
1178 if (writeback) { // Writeback
1180 U |= ARMII::IndexModePre << 9;
1182 U |= ARMII::IndexModePost << 9;
1184 // On stores, the writeback operand precedes Rt.
1185 switch (Inst.getOpcode()) {
1188 case ARM::STRD_POST:
1191 case ARM::STRH_POST:
1192 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1199 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1200 switch (Inst.getOpcode()) {
1203 case ARM::STRD_POST:
1206 case ARM::LDRD_POST:
1207 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
1214 // On loads, the writeback operand comes after Rt.
1215 switch (Inst.getOpcode()) {
1218 case ARM::LDRD_POST:
1221 case ARM::LDRH_POST:
1223 case ARM::LDRSH_PRE:
1224 case ARM::LDRSH_POST:
1226 case ARM::LDRSB_PRE:
1227 case ARM::LDRSB_POST:
1230 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1237 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1240 Inst.addOperand(MCOperand::CreateReg(0));
1241 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1243 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1244 Inst.addOperand(MCOperand::CreateImm(U));
1247 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1252 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1253 uint64_t Address, const void *Decoder) {
1254 DecodeStatus S = Success;
1256 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1257 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1274 Inst.addOperand(MCOperand::CreateImm(mode));
1275 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1280 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1282 uint64_t Address, const void *Decoder) {
1283 DecodeStatus S = Success;
1285 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1286 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1287 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1290 switch (Inst.getOpcode()) {
1292 Inst.setOpcode(ARM::RFEDA);
1294 case ARM::LDMDA_UPD:
1295 Inst.setOpcode(ARM::RFEDA_UPD);
1298 Inst.setOpcode(ARM::RFEDB);
1300 case ARM::LDMDB_UPD:
1301 Inst.setOpcode(ARM::RFEDB_UPD);
1304 Inst.setOpcode(ARM::RFEIA);
1306 case ARM::LDMIA_UPD:
1307 Inst.setOpcode(ARM::RFEIA_UPD);
1310 Inst.setOpcode(ARM::RFEIB);
1312 case ARM::LDMIB_UPD:
1313 Inst.setOpcode(ARM::RFEIB_UPD);
1316 Inst.setOpcode(ARM::SRSDA);
1318 case ARM::STMDA_UPD:
1319 Inst.setOpcode(ARM::SRSDA_UPD);
1322 Inst.setOpcode(ARM::SRSDB);
1324 case ARM::STMDB_UPD:
1325 Inst.setOpcode(ARM::SRSDB_UPD);
1328 Inst.setOpcode(ARM::SRSIA);
1330 case ARM::STMIA_UPD:
1331 Inst.setOpcode(ARM::SRSIA_UPD);
1334 Inst.setOpcode(ARM::SRSIB);
1336 case ARM::STMIB_UPD:
1337 Inst.setOpcode(ARM::SRSIB_UPD);
1343 // For stores (which become SRS's, the only operand is the mode.
1344 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1346 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1350 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1353 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1354 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied
1355 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1356 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));
1361 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1362 uint64_t Address, const void *Decoder) {
1363 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1364 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1365 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1366 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1368 DecodeStatus S = Success;
1370 // imod == '01' --> UNPREDICTABLE
1371 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1372 // return failure here. The '01' imod value is unprintable, so there's
1373 // nothing useful we could do even if we returned UNPREDICTABLE.
1375 if (imod == 1) CHECK(S, Fail);
1378 Inst.setOpcode(ARM::CPS3p);
1379 Inst.addOperand(MCOperand::CreateImm(imod));
1380 Inst.addOperand(MCOperand::CreateImm(iflags));
1381 Inst.addOperand(MCOperand::CreateImm(mode));
1382 } else if (imod && !M) {
1383 Inst.setOpcode(ARM::CPS2p);
1384 Inst.addOperand(MCOperand::CreateImm(imod));
1385 Inst.addOperand(MCOperand::CreateImm(iflags));
1386 if (mode) CHECK(S, Unpredictable);
1387 } else if (!imod && M) {
1388 Inst.setOpcode(ARM::CPS1p);
1389 Inst.addOperand(MCOperand::CreateImm(mode));
1390 if (iflags) CHECK(S, Unpredictable);
1392 // imod == '00' && M == '0' --> UNPREDICTABLE
1393 Inst.setOpcode(ARM::CPS1p);
1394 Inst.addOperand(MCOperand::CreateImm(mode));
1395 CHECK(S, Unpredictable);
1401 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1402 uint64_t Address, const void *Decoder) {
1403 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1404 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1405 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1406 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1408 DecodeStatus S = Success;
1410 // imod == '01' --> UNPREDICTABLE
1411 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1412 // return failure here. The '01' imod value is unprintable, so there's
1413 // nothing useful we could do even if we returned UNPREDICTABLE.
1415 if (imod == 1) CHECK(S, Fail);
1418 Inst.setOpcode(ARM::t2CPS3p);
1419 Inst.addOperand(MCOperand::CreateImm(imod));
1420 Inst.addOperand(MCOperand::CreateImm(iflags));
1421 Inst.addOperand(MCOperand::CreateImm(mode));
1422 } else if (imod && !M) {
1423 Inst.setOpcode(ARM::t2CPS2p);
1424 Inst.addOperand(MCOperand::CreateImm(imod));
1425 Inst.addOperand(MCOperand::CreateImm(iflags));
1426 if (mode) CHECK(S, Unpredictable);
1427 } else if (!imod && M) {
1428 Inst.setOpcode(ARM::t2CPS1p);
1429 Inst.addOperand(MCOperand::CreateImm(mode));
1430 if (iflags) CHECK(S, Unpredictable);
1432 // imod == '00' && M == '0' --> UNPREDICTABLE
1433 Inst.setOpcode(ARM::t2CPS1p);
1434 Inst.addOperand(MCOperand::CreateImm(mode));
1435 CHECK(S, Unpredictable);
1442 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1443 uint64_t Address, const void *Decoder) {
1444 DecodeStatus S = Success;
1446 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1447 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1448 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1449 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1450 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1453 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1455 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));
1456 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));
1457 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1458 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));
1460 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1465 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1466 uint64_t Address, const void *Decoder) {
1467 DecodeStatus S = Success;
1469 unsigned add = fieldFromInstruction32(Val, 12, 1);
1470 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1471 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1473 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1475 if (!add) imm *= -1;
1476 if (imm == 0 && !add) imm = INT32_MIN;
1477 Inst.addOperand(MCOperand::CreateImm(imm));
1482 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1483 uint64_t Address, const void *Decoder) {
1484 DecodeStatus S = Success;
1486 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1487 unsigned U = fieldFromInstruction32(Val, 8, 1);
1488 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1490 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1493 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1495 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1500 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1501 uint64_t Address, const void *Decoder) {
1502 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1506 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1507 uint64_t Address, const void *Decoder) {
1508 DecodeStatus S = Success;
1510 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1511 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1514 Inst.setOpcode(ARM::BLXi);
1515 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1516 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1520 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1521 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1527 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1528 uint64_t Address, const void *Decoder) {
1529 Inst.addOperand(MCOperand::CreateImm(64 - Val));
1533 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1534 uint64_t Address, const void *Decoder) {
1535 DecodeStatus S = Success;
1537 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1538 unsigned align = fieldFromInstruction32(Val, 4, 2);
1540 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1542 Inst.addOperand(MCOperand::CreateImm(0));
1544 Inst.addOperand(MCOperand::CreateImm(4 << align));
1549 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1550 uint64_t Address, const void *Decoder) {
1551 DecodeStatus S = Success;
1553 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1554 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1555 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1556 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1557 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1558 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1560 // First output register
1561 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1563 // Second output register
1564 switch (Inst.getOpcode()) {
1569 case ARM::VLD1q8_UPD:
1570 case ARM::VLD1q16_UPD:
1571 case ARM::VLD1q32_UPD:
1572 case ARM::VLD1q64_UPD:
1577 case ARM::VLD1d8T_UPD:
1578 case ARM::VLD1d16T_UPD:
1579 case ARM::VLD1d32T_UPD:
1580 case ARM::VLD1d64T_UPD:
1585 case ARM::VLD1d8Q_UPD:
1586 case ARM::VLD1d16Q_UPD:
1587 case ARM::VLD1d32Q_UPD:
1588 case ARM::VLD1d64Q_UPD:
1592 case ARM::VLD2d8_UPD:
1593 case ARM::VLD2d16_UPD:
1594 case ARM::VLD2d32_UPD:
1598 case ARM::VLD2q8_UPD:
1599 case ARM::VLD2q16_UPD:
1600 case ARM::VLD2q32_UPD:
1604 case ARM::VLD3d8_UPD:
1605 case ARM::VLD3d16_UPD:
1606 case ARM::VLD3d32_UPD:
1610 case ARM::VLD4d8_UPD:
1611 case ARM::VLD4d16_UPD:
1612 case ARM::VLD4d32_UPD:
1613 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1618 case ARM::VLD2b8_UPD:
1619 case ARM::VLD2b16_UPD:
1620 case ARM::VLD2b32_UPD:
1624 case ARM::VLD3q8_UPD:
1625 case ARM::VLD3q16_UPD:
1626 case ARM::VLD3q32_UPD:
1630 case ARM::VLD4q8_UPD:
1631 case ARM::VLD4q16_UPD:
1632 case ARM::VLD4q32_UPD:
1633 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1638 // Third output register
1639 switch(Inst.getOpcode()) {
1644 case ARM::VLD1d8T_UPD:
1645 case ARM::VLD1d16T_UPD:
1646 case ARM::VLD1d32T_UPD:
1647 case ARM::VLD1d64T_UPD:
1652 case ARM::VLD1d8Q_UPD:
1653 case ARM::VLD1d16Q_UPD:
1654 case ARM::VLD1d32Q_UPD:
1655 case ARM::VLD1d64Q_UPD:
1659 case ARM::VLD2q8_UPD:
1660 case ARM::VLD2q16_UPD:
1661 case ARM::VLD2q32_UPD:
1665 case ARM::VLD3d8_UPD:
1666 case ARM::VLD3d16_UPD:
1667 case ARM::VLD3d32_UPD:
1671 case ARM::VLD4d8_UPD:
1672 case ARM::VLD4d16_UPD:
1673 case ARM::VLD4d32_UPD:
1674 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1679 case ARM::VLD3q8_UPD:
1680 case ARM::VLD3q16_UPD:
1681 case ARM::VLD3q32_UPD:
1685 case ARM::VLD4q8_UPD:
1686 case ARM::VLD4q16_UPD:
1687 case ARM::VLD4q32_UPD:
1688 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1694 // Fourth output register
1695 switch (Inst.getOpcode()) {
1700 case ARM::VLD1d8Q_UPD:
1701 case ARM::VLD1d16Q_UPD:
1702 case ARM::VLD1d32Q_UPD:
1703 case ARM::VLD1d64Q_UPD:
1707 case ARM::VLD2q8_UPD:
1708 case ARM::VLD2q16_UPD:
1709 case ARM::VLD2q32_UPD:
1713 case ARM::VLD4d8_UPD:
1714 case ARM::VLD4d16_UPD:
1715 case ARM::VLD4d32_UPD:
1716 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
1721 case ARM::VLD4q8_UPD:
1722 case ARM::VLD4q16_UPD:
1723 case ARM::VLD4q32_UPD:
1724 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
1730 // Writeback operand
1731 switch (Inst.getOpcode()) {
1732 case ARM::VLD1d8_UPD:
1733 case ARM::VLD1d16_UPD:
1734 case ARM::VLD1d32_UPD:
1735 case ARM::VLD1d64_UPD:
1736 case ARM::VLD1q8_UPD:
1737 case ARM::VLD1q16_UPD:
1738 case ARM::VLD1q32_UPD:
1739 case ARM::VLD1q64_UPD:
1740 case ARM::VLD1d8T_UPD:
1741 case ARM::VLD1d16T_UPD:
1742 case ARM::VLD1d32T_UPD:
1743 case ARM::VLD1d64T_UPD:
1744 case ARM::VLD1d8Q_UPD:
1745 case ARM::VLD1d16Q_UPD:
1746 case ARM::VLD1d32Q_UPD:
1747 case ARM::VLD1d64Q_UPD:
1748 case ARM::VLD2d8_UPD:
1749 case ARM::VLD2d16_UPD:
1750 case ARM::VLD2d32_UPD:
1751 case ARM::VLD2q8_UPD:
1752 case ARM::VLD2q16_UPD:
1753 case ARM::VLD2q32_UPD:
1754 case ARM::VLD2b8_UPD:
1755 case ARM::VLD2b16_UPD:
1756 case ARM::VLD2b32_UPD:
1757 case ARM::VLD3d8_UPD:
1758 case ARM::VLD3d16_UPD:
1759 case ARM::VLD3d32_UPD:
1760 case ARM::VLD3q8_UPD:
1761 case ARM::VLD3q16_UPD:
1762 case ARM::VLD3q32_UPD:
1763 case ARM::VLD4d8_UPD:
1764 case ARM::VLD4d16_UPD:
1765 case ARM::VLD4d32_UPD:
1766 case ARM::VLD4q8_UPD:
1767 case ARM::VLD4q16_UPD:
1768 case ARM::VLD4q32_UPD:
1769 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1775 // AddrMode6 Base (register+alignment)
1776 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1778 // AddrMode6 Offset (register)
1780 Inst.addOperand(MCOperand::CreateReg(0));
1781 else if (Rm != 0xF) {
1782 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1788 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
1789 uint64_t Address, const void *Decoder) {
1790 DecodeStatus S = Success;
1792 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1793 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1794 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1795 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1796 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1797 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1799 // Writeback Operand
1800 switch (Inst.getOpcode()) {
1801 case ARM::VST1d8_UPD:
1802 case ARM::VST1d16_UPD:
1803 case ARM::VST1d32_UPD:
1804 case ARM::VST1d64_UPD:
1805 case ARM::VST1q8_UPD:
1806 case ARM::VST1q16_UPD:
1807 case ARM::VST1q32_UPD:
1808 case ARM::VST1q64_UPD:
1809 case ARM::VST1d8T_UPD:
1810 case ARM::VST1d16T_UPD:
1811 case ARM::VST1d32T_UPD:
1812 case ARM::VST1d64T_UPD:
1813 case ARM::VST1d8Q_UPD:
1814 case ARM::VST1d16Q_UPD:
1815 case ARM::VST1d32Q_UPD:
1816 case ARM::VST1d64Q_UPD:
1817 case ARM::VST2d8_UPD:
1818 case ARM::VST2d16_UPD:
1819 case ARM::VST2d32_UPD:
1820 case ARM::VST2q8_UPD:
1821 case ARM::VST2q16_UPD:
1822 case ARM::VST2q32_UPD:
1823 case ARM::VST2b8_UPD:
1824 case ARM::VST2b16_UPD:
1825 case ARM::VST2b32_UPD:
1826 case ARM::VST3d8_UPD:
1827 case ARM::VST3d16_UPD:
1828 case ARM::VST3d32_UPD:
1829 case ARM::VST3q8_UPD:
1830 case ARM::VST3q16_UPD:
1831 case ARM::VST3q32_UPD:
1832 case ARM::VST4d8_UPD:
1833 case ARM::VST4d16_UPD:
1834 case ARM::VST4d32_UPD:
1835 case ARM::VST4q8_UPD:
1836 case ARM::VST4q16_UPD:
1837 case ARM::VST4q32_UPD:
1838 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1844 // AddrMode6 Base (register+alignment)
1845 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1847 // AddrMode6 Offset (register)
1849 Inst.addOperand(MCOperand::CreateReg(0));
1850 else if (Rm != 0xF) {
1851 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1854 // First input register
1855 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1857 // Second input register
1858 switch (Inst.getOpcode()) {
1863 case ARM::VST1q8_UPD:
1864 case ARM::VST1q16_UPD:
1865 case ARM::VST1q32_UPD:
1866 case ARM::VST1q64_UPD:
1871 case ARM::VST1d8T_UPD:
1872 case ARM::VST1d16T_UPD:
1873 case ARM::VST1d32T_UPD:
1874 case ARM::VST1d64T_UPD:
1879 case ARM::VST1d8Q_UPD:
1880 case ARM::VST1d16Q_UPD:
1881 case ARM::VST1d32Q_UPD:
1882 case ARM::VST1d64Q_UPD:
1886 case ARM::VST2d8_UPD:
1887 case ARM::VST2d16_UPD:
1888 case ARM::VST2d32_UPD:
1892 case ARM::VST2q8_UPD:
1893 case ARM::VST2q16_UPD:
1894 case ARM::VST2q32_UPD:
1898 case ARM::VST3d8_UPD:
1899 case ARM::VST3d16_UPD:
1900 case ARM::VST3d32_UPD:
1904 case ARM::VST4d8_UPD:
1905 case ARM::VST4d16_UPD:
1906 case ARM::VST4d32_UPD:
1907 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1912 case ARM::VST2b8_UPD:
1913 case ARM::VST2b16_UPD:
1914 case ARM::VST2b32_UPD:
1918 case ARM::VST3q8_UPD:
1919 case ARM::VST3q16_UPD:
1920 case ARM::VST3q32_UPD:
1924 case ARM::VST4q8_UPD:
1925 case ARM::VST4q16_UPD:
1926 case ARM::VST4q32_UPD:
1927 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1933 // Third input register
1934 switch (Inst.getOpcode()) {
1939 case ARM::VST1d8T_UPD:
1940 case ARM::VST1d16T_UPD:
1941 case ARM::VST1d32T_UPD:
1942 case ARM::VST1d64T_UPD:
1947 case ARM::VST1d8Q_UPD:
1948 case ARM::VST1d16Q_UPD:
1949 case ARM::VST1d32Q_UPD:
1950 case ARM::VST1d64Q_UPD:
1954 case ARM::VST2q8_UPD:
1955 case ARM::VST2q16_UPD:
1956 case ARM::VST2q32_UPD:
1960 case ARM::VST3d8_UPD:
1961 case ARM::VST3d16_UPD:
1962 case ARM::VST3d32_UPD:
1966 case ARM::VST4d8_UPD:
1967 case ARM::VST4d16_UPD:
1968 case ARM::VST4d32_UPD:
1969 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1974 case ARM::VST3q8_UPD:
1975 case ARM::VST3q16_UPD:
1976 case ARM::VST3q32_UPD:
1980 case ARM::VST4q8_UPD:
1981 case ARM::VST4q16_UPD:
1982 case ARM::VST4q32_UPD:
1983 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1989 // Fourth input register
1990 switch (Inst.getOpcode()) {
1995 case ARM::VST1d8Q_UPD:
1996 case ARM::VST1d16Q_UPD:
1997 case ARM::VST1d32Q_UPD:
1998 case ARM::VST1d64Q_UPD:
2002 case ARM::VST2q8_UPD:
2003 case ARM::VST2q16_UPD:
2004 case ARM::VST2q32_UPD:
2008 case ARM::VST4d8_UPD:
2009 case ARM::VST4d16_UPD:
2010 case ARM::VST4d32_UPD:
2011 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
2016 case ARM::VST4q8_UPD:
2017 case ARM::VST4q16_UPD:
2018 case ARM::VST4q32_UPD:
2019 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
2028 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2029 uint64_t Address, const void *Decoder) {
2030 DecodeStatus S = Success;
2032 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2033 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2034 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2035 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2036 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2037 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2038 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2040 align *= (1 << size);
2042 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2044 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
2047 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2050 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2051 Inst.addOperand(MCOperand::CreateImm(align));
2054 Inst.addOperand(MCOperand::CreateReg(0));
2055 else if (Rm != 0xF) {
2056 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2062 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2063 uint64_t Address, const void *Decoder) {
2064 DecodeStatus S = Success;
2066 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2067 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2068 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2069 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2070 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2071 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2072 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2075 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2076 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2078 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2081 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2082 Inst.addOperand(MCOperand::CreateImm(align));
2085 Inst.addOperand(MCOperand::CreateReg(0));
2086 else if (Rm != 0xF) {
2087 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2093 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2094 uint64_t Address, const void *Decoder) {
2095 DecodeStatus S = Success;
2097 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2098 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2099 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2100 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2101 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2103 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2104 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2105 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2107 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2110 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2111 Inst.addOperand(MCOperand::CreateImm(0));
2114 Inst.addOperand(MCOperand::CreateReg(0));
2115 else if (Rm != 0xF) {
2116 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2122 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2123 uint64_t Address, const void *Decoder) {
2124 DecodeStatus S = Success;
2126 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2127 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2128 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2129 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2130 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2131 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2132 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2147 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2148 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2149 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2150 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
2152 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2155 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2156 Inst.addOperand(MCOperand::CreateImm(align));
2159 Inst.addOperand(MCOperand::CreateReg(0));
2160 else if (Rm != 0xF) {
2161 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2168 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2169 uint64_t Address, const void *Decoder) {
2170 DecodeStatus S = Success;
2172 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2173 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2174 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2175 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2176 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2177 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2178 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2179 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2182 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2184 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2187 Inst.addOperand(MCOperand::CreateImm(imm));
2189 switch (Inst.getOpcode()) {
2190 case ARM::VORRiv4i16:
2191 case ARM::VORRiv2i32:
2192 case ARM::VBICiv4i16:
2193 case ARM::VBICiv2i32:
2194 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2196 case ARM::VORRiv8i16:
2197 case ARM::VORRiv4i32:
2198 case ARM::VBICiv8i16:
2199 case ARM::VBICiv4i32:
2200 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2209 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2210 uint64_t Address, const void *Decoder) {
2211 DecodeStatus S = Success;
2213 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2214 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2215 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2216 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2217 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2219 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2220 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2221 Inst.addOperand(MCOperand::CreateImm(8 << size));
2226 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2227 uint64_t Address, const void *Decoder) {
2228 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2232 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2233 uint64_t Address, const void *Decoder) {
2234 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2238 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2239 uint64_t Address, const void *Decoder) {
2240 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2244 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2245 uint64_t Address, const void *Decoder) {
2246 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2250 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2251 uint64_t Address, const void *Decoder) {
2252 DecodeStatus S = Success;
2254 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2255 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2256 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2257 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2258 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2259 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2260 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2261 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2263 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2265 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback
2268 for (unsigned i = 0; i < length; ++i) {
2269 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));
2272 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2277 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
2278 uint64_t Address, const void *Decoder) {
2279 // The immediate needs to be a fully instantiated float. However, the
2280 // auto-generated decoder is only able to fill in some of the bits
2281 // necessary. For instance, the 'b' bit is replicated multiple times,
2282 // and is even present in inverted form in one bit. We do a little
2283 // binary parsing here to fill in those missing bits, and then
2284 // reinterpret it all as a float.
2290 fp_conv.integer = Val;
2291 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2292 fp_conv.integer |= b << 26;
2293 fp_conv.integer |= b << 27;
2294 fp_conv.integer |= b << 28;
2295 fp_conv.integer |= b << 29;
2296 fp_conv.integer |= (~b & 0x1) << 30;
2298 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
2302 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2303 uint64_t Address, const void *Decoder) {
2304 DecodeStatus S = Success;
2306 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2307 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2309 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
2311 if (Inst.getOpcode() == ARM::tADR)
2312 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2313 else if (Inst.getOpcode() == ARM::tADDrSPi)
2314 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2318 Inst.addOperand(MCOperand::CreateImm(imm));
2322 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2323 uint64_t Address, const void *Decoder) {
2324 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2328 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2329 uint64_t Address, const void *Decoder) {
2330 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2334 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2335 uint64_t Address, const void *Decoder) {
2336 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2340 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2341 uint64_t Address, const void *Decoder) {
2342 DecodeStatus S = Success;
2344 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2345 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2347 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2348 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));
2353 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2354 uint64_t Address, const void *Decoder) {
2355 DecodeStatus S = Success;
2357 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2358 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2360 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2361 Inst.addOperand(MCOperand::CreateImm(imm));
2366 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2367 uint64_t Address, const void *Decoder) {
2368 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2373 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2374 uint64_t Address, const void *Decoder) {
2375 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2376 Inst.addOperand(MCOperand::CreateImm(Val));
2381 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2382 uint64_t Address, const void *Decoder) {
2383 DecodeStatus S = Success;
2385 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2386 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2387 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2389 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2390 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));
2391 Inst.addOperand(MCOperand::CreateImm(imm));
2396 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2397 uint64_t Address, const void *Decoder) {
2398 DecodeStatus S = Success;
2400 switch (Inst.getOpcode()) {
2406 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2407 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2411 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2413 switch (Inst.getOpcode()) {
2415 Inst.setOpcode(ARM::t2LDRBpci);
2418 Inst.setOpcode(ARM::t2LDRHpci);
2421 Inst.setOpcode(ARM::t2LDRSHpci);
2424 Inst.setOpcode(ARM::t2LDRSBpci);
2427 Inst.setOpcode(ARM::t2PLDi12);
2428 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2434 int imm = fieldFromInstruction32(Insn, 0, 12);
2435 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2436 Inst.addOperand(MCOperand::CreateImm(imm));
2441 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2442 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2443 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2444 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));
2449 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2450 uint64_t Address, const void *Decoder) {
2451 int imm = Val & 0xFF;
2452 if (!(Val & 0x100)) imm *= -1;
2453 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2458 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2459 uint64_t Address, const void *Decoder) {
2460 DecodeStatus S = Success;
2462 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2463 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2465 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2466 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));
2471 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2472 uint64_t Address, const void *Decoder) {
2473 int imm = Val & 0xFF;
2474 if (!(Val & 0x100)) imm *= -1;
2475 Inst.addOperand(MCOperand::CreateImm(imm));
2481 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2482 uint64_t Address, const void *Decoder) {
2483 DecodeStatus S = Success;
2485 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2486 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2488 // Some instructions always use an additive offset.
2489 switch (Inst.getOpcode()) {
2501 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2502 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));
2508 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2509 uint64_t Address, const void *Decoder) {
2510 DecodeStatus S = Success;
2512 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2513 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2515 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2516 Inst.addOperand(MCOperand::CreateImm(imm));
2522 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2523 uint64_t Address, const void *Decoder) {
2524 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2526 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2527 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2528 Inst.addOperand(MCOperand::CreateImm(imm));
2533 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
2534 uint64_t Address, const void *Decoder) {
2535 DecodeStatus S = Success;
2537 if (Inst.getOpcode() == ARM::tADDrSP) {
2538 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2539 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2541 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2542 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2543 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2544 } else if (Inst.getOpcode() == ARM::tADDspr) {
2545 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2547 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2548 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2549 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2555 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
2556 uint64_t Address, const void *Decoder) {
2557 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2558 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2560 Inst.addOperand(MCOperand::CreateImm(imod));
2561 Inst.addOperand(MCOperand::CreateImm(flags));
2566 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
2567 uint64_t Address, const void *Decoder) {
2568 DecodeStatus S = Success;
2569 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2570 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2572 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;
2573 Inst.addOperand(MCOperand::CreateImm(add));
2578 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
2579 uint64_t Address, const void *Decoder) {
2580 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2584 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
2585 uint64_t Address, const void *Decoder) {
2586 if (Val == 0xA || Val == 0xB)
2589 Inst.addOperand(MCOperand::CreateImm(Val));
2594 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2595 uint64_t Address, const void *Decoder) {
2596 DecodeStatus S = Success;
2598 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2599 if (pred == 0xE || pred == 0xF) {
2600 unsigned opc = fieldFromInstruction32(Insn, 4, 2);
2605 Inst.setOpcode(ARM::t2DSB);
2608 Inst.setOpcode(ARM::t2DMB);
2611 Inst.setOpcode(ARM::t2ISB);
2615 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2616 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
2619 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2620 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2621 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2622 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2623 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2625 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));
2626 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2631 // Decode a shifted immediate operand. These basically consist
2632 // of an 8-bit value, and a 4-bit directive that specifies either
2633 // a splat operation or a rotation.
2634 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
2635 uint64_t Address, const void *Decoder) {
2636 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2638 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2639 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2642 Inst.addOperand(MCOperand::CreateImm(imm));
2645 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2648 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2651 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2656 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2657 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2658 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2659 Inst.addOperand(MCOperand::CreateImm(imm));
2666 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2667 uint64_t Address, const void *Decoder){
2668 Inst.addOperand(MCOperand::CreateImm(Val << 1));
2672 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
2673 uint64_t Address, const void *Decoder){
2674 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2678 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
2679 uint64_t Address, const void *Decoder) {
2694 Inst.addOperand(MCOperand::CreateImm(Val));
2698 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
2699 uint64_t Address, const void *Decoder) {
2700 if (!Val) return Fail;
2701 Inst.addOperand(MCOperand::CreateImm(Val));
2705 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
2706 uint64_t Address, const void *Decoder) {
2707 DecodeStatus S = Success;
2709 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2710 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2711 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2713 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2715 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2716 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2717 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2718 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2724 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
2725 uint64_t Address, const void *Decoder){
2726 DecodeStatus S = Success;
2728 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2729 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2730 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2731 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2733 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));
2735 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2736 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;
2738 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2739 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2740 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2741 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2746 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
2747 uint64_t Address, const void *Decoder) {
2748 DecodeStatus S = Success;
2750 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2751 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2752 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2753 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2754 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2755 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2757 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2759 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2760 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2761 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
2762 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2767 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
2768 uint64_t Address, const void *Decoder) {
2769 DecodeStatus S = Success;
2771 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2772 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2773 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2774 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2775 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2776 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2778 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2780 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2781 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2782 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
2783 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2788 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
2789 uint64_t Address, const void *Decoder) {
2790 DecodeStatus S = Success;
2792 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2793 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2794 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2795 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2796 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2804 if (fieldFromInstruction32(Insn, 4, 1))
2805 return Fail; // UNDEFINED
2806 index = fieldFromInstruction32(Insn, 5, 3);
2809 if (fieldFromInstruction32(Insn, 5, 1))
2810 return Fail; // UNDEFINED
2811 index = fieldFromInstruction32(Insn, 6, 2);
2812 if (fieldFromInstruction32(Insn, 4, 1))
2816 if (fieldFromInstruction32(Insn, 6, 1))
2817 return Fail; // UNDEFINED
2818 index = fieldFromInstruction32(Insn, 7, 1);
2819 if (fieldFromInstruction32(Insn, 4, 2) != 0)
2823 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2824 if (Rm != 0xF) { // Writeback
2825 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2827 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2828 Inst.addOperand(MCOperand::CreateImm(align));
2831 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2833 Inst.addOperand(MCOperand::CreateReg(0));
2836 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2837 Inst.addOperand(MCOperand::CreateImm(index));
2842 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
2843 uint64_t Address, const void *Decoder) {
2844 DecodeStatus S = Success;
2846 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2847 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2848 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2849 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2850 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2858 if (fieldFromInstruction32(Insn, 4, 1))
2859 return Fail; // UNDEFINED
2860 index = fieldFromInstruction32(Insn, 5, 3);
2863 if (fieldFromInstruction32(Insn, 5, 1))
2864 return Fail; // UNDEFINED
2865 index = fieldFromInstruction32(Insn, 6, 2);
2866 if (fieldFromInstruction32(Insn, 4, 1))
2870 if (fieldFromInstruction32(Insn, 6, 1))
2871 return Fail; // UNDEFINED
2872 index = fieldFromInstruction32(Insn, 7, 1);
2873 if (fieldFromInstruction32(Insn, 4, 2) != 0)
2877 if (Rm != 0xF) { // Writeback
2878 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2880 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2881 Inst.addOperand(MCOperand::CreateImm(align));
2884 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2886 Inst.addOperand(MCOperand::CreateReg(0));
2889 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2890 Inst.addOperand(MCOperand::CreateImm(index));
2896 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
2897 uint64_t Address, const void *Decoder) {
2898 DecodeStatus S = Success;
2900 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2901 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2902 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2903 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2904 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2913 index = fieldFromInstruction32(Insn, 5, 3);
2914 if (fieldFromInstruction32(Insn, 4, 1))
2918 index = fieldFromInstruction32(Insn, 6, 2);
2919 if (fieldFromInstruction32(Insn, 4, 1))
2921 if (fieldFromInstruction32(Insn, 5, 1))
2925 if (fieldFromInstruction32(Insn, 5, 1))
2926 return Fail; // UNDEFINED
2927 index = fieldFromInstruction32(Insn, 7, 1);
2928 if (fieldFromInstruction32(Insn, 4, 1) != 0)
2930 if (fieldFromInstruction32(Insn, 6, 1))
2935 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2936 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2937 if (Rm != 0xF) { // Writeback
2938 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2940 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2941 Inst.addOperand(MCOperand::CreateImm(align));
2944 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2946 Inst.addOperand(MCOperand::CreateReg(0));
2949 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2950 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2951 Inst.addOperand(MCOperand::CreateImm(index));
2956 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
2957 uint64_t Address, const void *Decoder) {
2958 DecodeStatus S = Success;
2960 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2961 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2962 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2963 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2964 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2973 index = fieldFromInstruction32(Insn, 5, 3);
2974 if (fieldFromInstruction32(Insn, 4, 1))
2978 index = fieldFromInstruction32(Insn, 6, 2);
2979 if (fieldFromInstruction32(Insn, 4, 1))
2981 if (fieldFromInstruction32(Insn, 5, 1))
2985 if (fieldFromInstruction32(Insn, 5, 1))
2986 return Fail; // UNDEFINED
2987 index = fieldFromInstruction32(Insn, 7, 1);
2988 if (fieldFromInstruction32(Insn, 4, 1) != 0)
2990 if (fieldFromInstruction32(Insn, 6, 1))
2995 if (Rm != 0xF) { // Writeback
2996 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2998 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2999 Inst.addOperand(MCOperand::CreateImm(align));
3002 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3004 Inst.addOperand(MCOperand::CreateReg(0));
3007 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3008 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3009 Inst.addOperand(MCOperand::CreateImm(index));
3015 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3016 uint64_t Address, const void *Decoder) {
3017 DecodeStatus S = Success;
3019 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3020 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3021 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3022 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3023 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3032 if (fieldFromInstruction32(Insn, 4, 1))
3033 return Fail; // UNDEFINED
3034 index = fieldFromInstruction32(Insn, 5, 3);
3037 if (fieldFromInstruction32(Insn, 4, 1))
3038 return Fail; // UNDEFINED
3039 index = fieldFromInstruction32(Insn, 6, 2);
3040 if (fieldFromInstruction32(Insn, 5, 1))
3044 if (fieldFromInstruction32(Insn, 4, 2))
3045 return Fail; // UNDEFINED
3046 index = fieldFromInstruction32(Insn, 7, 1);
3047 if (fieldFromInstruction32(Insn, 6, 1))
3052 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3053 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3054 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3056 if (Rm != 0xF) { // Writeback
3057 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3059 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3060 Inst.addOperand(MCOperand::CreateImm(align));
3063 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3065 Inst.addOperand(MCOperand::CreateReg(0));
3068 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3069 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3070 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3071 Inst.addOperand(MCOperand::CreateImm(index));
3076 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3077 uint64_t Address, const void *Decoder) {
3078 DecodeStatus S = Success;
3080 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3081 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3082 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3083 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3084 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3093 if (fieldFromInstruction32(Insn, 4, 1))
3094 return Fail; // UNDEFINED
3095 index = fieldFromInstruction32(Insn, 5, 3);
3098 if (fieldFromInstruction32(Insn, 4, 1))
3099 return Fail; // UNDEFINED
3100 index = fieldFromInstruction32(Insn, 6, 2);
3101 if (fieldFromInstruction32(Insn, 5, 1))
3105 if (fieldFromInstruction32(Insn, 4, 2))
3106 return Fail; // UNDEFINED
3107 index = fieldFromInstruction32(Insn, 7, 1);
3108 if (fieldFromInstruction32(Insn, 6, 1))
3113 if (Rm != 0xF) { // Writeback
3114 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3116 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3117 Inst.addOperand(MCOperand::CreateImm(align));
3120 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3122 Inst.addOperand(MCOperand::CreateReg(0));
3125 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3126 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3127 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3128 Inst.addOperand(MCOperand::CreateImm(index));
3134 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3135 uint64_t Address, const void *Decoder) {
3136 DecodeStatus S = Success;
3138 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3139 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3140 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3141 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3142 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3151 if (fieldFromInstruction32(Insn, 4, 1))
3153 index = fieldFromInstruction32(Insn, 5, 3);
3156 if (fieldFromInstruction32(Insn, 4, 1))
3158 index = fieldFromInstruction32(Insn, 6, 2);
3159 if (fieldFromInstruction32(Insn, 5, 1))
3163 if (fieldFromInstruction32(Insn, 4, 2))
3164 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3165 index = fieldFromInstruction32(Insn, 7, 1);
3166 if (fieldFromInstruction32(Insn, 6, 1))
3171 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3172 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3173 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3174 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3176 if (Rm != 0xF) { // Writeback
3177 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3179 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3180 Inst.addOperand(MCOperand::CreateImm(align));
3183 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3185 Inst.addOperand(MCOperand::CreateReg(0));
3188 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3189 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3190 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3191 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3192 Inst.addOperand(MCOperand::CreateImm(index));
3197 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3198 uint64_t Address, const void *Decoder) {
3199 DecodeStatus S = Success;
3201 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3202 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3203 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3204 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3205 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3214 if (fieldFromInstruction32(Insn, 4, 1))
3216 index = fieldFromInstruction32(Insn, 5, 3);
3219 if (fieldFromInstruction32(Insn, 4, 1))
3221 index = fieldFromInstruction32(Insn, 6, 2);
3222 if (fieldFromInstruction32(Insn, 5, 1))
3226 if (fieldFromInstruction32(Insn, 4, 2))
3227 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3228 index = fieldFromInstruction32(Insn, 7, 1);
3229 if (fieldFromInstruction32(Insn, 6, 1))
3234 if (Rm != 0xF) { // Writeback
3235 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3237 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3238 Inst.addOperand(MCOperand::CreateImm(align));
3241 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3243 Inst.addOperand(MCOperand::CreateReg(0));
3246 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3247 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3248 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3249 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3250 Inst.addOperand(MCOperand::CreateImm(index));
3255 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3256 uint64_t Address, const void *Decoder) {
3257 DecodeStatus S = Success;
3258 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3259 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3260 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3261 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3262 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3264 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3265 CHECK(S, Unpredictable);
3267 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
3268 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3269 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
3270 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3271 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3276 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
3277 uint64_t Address, const void *Decoder) {
3278 DecodeStatus S = Success;
3279 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3280 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3281 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3282 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3283 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3285 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3286 CHECK(S, Unpredictable);
3288 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
3289 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3290 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
3291 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3292 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3297 static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond,
3298 uint64_t Address, const void *Decoder) {
3299 DecodeStatus S = Success;
3302 CHECK(S, Unpredictable);
3305 Inst.addOperand(MCOperand::CreateImm(Cond));
3309 static DecodeStatus DecodeITMask(llvm::MCInst &Inst, unsigned Mask,
3310 uint64_t Address, const void *Decoder) {
3311 DecodeStatus S = Success;
3314 CHECK(S, Unpredictable);
3316 Inst.addOperand(MCOperand::CreateImm(Mask));