1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "ARMDisassembler.h"
14 #include "ARMRegisterInfo.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/EDInstInfo.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/Target/TargetRegistry.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
27 // Pull DecodeStatus and its enum values into the global namespace.
28 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
29 #define Success llvm::MCDisassembler::Success
30 #define Unpredictable llvm::MCDisassembler::SoftFail
31 #define Fail llvm::MCDisassembler::Fail
33 // Helper macro to perform setwise reduction of the current running status
34 // and another status, and return if the new status is Fail.
35 #define CHECK(S,X) do { \
36 S = (DecodeStatus) ((int)S & (X)); \
37 if (S == Fail) return Fail; \
40 // Forward declare these because the autogenerated code will reference them.
41 // Definitions are further down.
42 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43 uint64_t Address, const void *Decoder);
44 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
45 unsigned RegNo, uint64_t Address,
47 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
48 uint64_t Address, const void *Decoder);
49 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
50 uint64_t Address, const void *Decoder);
51 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52 uint64_t Address, const void *Decoder);
53 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
54 uint64_t Address, const void *Decoder);
55 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
56 uint64_t Address, const void *Decoder);
57 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
58 uint64_t Address, const void *Decoder);
59 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
63 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
64 uint64_t Address, const void *Decoder);
66 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
67 uint64_t Address, const void *Decoder);
68 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
69 uint64_t Address, const void *Decoder);
70 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
71 uint64_t Address, const void *Decoder);
72 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
73 uint64_t Address, const void *Decoder);
74 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
75 uint64_t Address, const void *Decoder);
76 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
77 uint64_t Address, const void *Decoder);
78 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
79 uint64_t Address, const void *Decoder);
81 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
82 uint64_t Address, const void *Decoder);
83 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
84 uint64_t Address, const void *Decoder);
85 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
89 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
90 uint64_t Address, const void *Decoder);
91 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
92 uint64_t Address, const void *Decoder);
93 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
94 uint64_t Address, const void *Decoder);
95 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
96 uint64_t Address, const void *Decoder);
98 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
101 const void *Decoder);
102 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
103 uint64_t Address, const void *Decoder);
104 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
105 uint64_t Address, const void *Decoder);
106 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
107 uint64_t Address, const void *Decoder);
108 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
109 uint64_t Address, const void *Decoder);
110 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
111 uint64_t Address, const void *Decoder);
112 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
113 uint64_t Address, const void *Decoder);
114 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
115 uint64_t Address, const void *Decoder);
116 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
117 uint64_t Address, const void *Decoder);
118 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
119 uint64_t Address, const void *Decoder);
120 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
121 uint64_t Address, const void *Decoder);
122 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
123 uint64_t Address, const void *Decoder);
124 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
125 uint64_t Address, const void *Decoder);
126 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
127 uint64_t Address, const void *Decoder);
128 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
129 uint64_t Address, const void *Decoder);
130 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
131 uint64_t Address, const void *Decoder);
132 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
133 uint64_t Address, const void *Decoder);
134 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
135 uint64_t Address, const void *Decoder);
136 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
137 uint64_t Address, const void *Decoder);
138 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
139 uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
141 uint64_t Address, const void *Decoder);
142 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
143 uint64_t Address, const void *Decoder);
144 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
145 uint64_t Address, const void *Decoder);
146 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
147 uint64_t Address, const void *Decoder);
148 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
149 uint64_t Address, const void *Decoder);
150 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
153 uint64_t Address, const void *Decoder);
154 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
157 uint64_t Address, const void *Decoder);
158 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
183 uint64_t Address, const void *Decoder);
185 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
186 uint64_t Address, const void *Decoder);
187 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
188 uint64_t Address, const void *Decoder);
189 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
190 uint64_t Address, const void *Decoder);
191 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
192 uint64_t Address, const void *Decoder);
193 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
194 uint64_t Address, const void *Decoder);
195 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
196 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
230 uint64_t Address, const void *Decoder);
232 #include "ARMGenDisassemblerTables.inc"
233 #include "ARMGenInstrInfo.inc"
234 #include "ARMGenEDInfo.inc"
236 using namespace llvm;
238 static MCDisassembler *createARMDisassembler(const Target &T) {
239 return new ARMDisassembler;
242 static MCDisassembler *createThumbDisassembler(const Target &T) {
243 return new ThumbDisassembler;
246 EDInstInfo *ARMDisassembler::getEDInfo() const {
250 EDInstInfo *ThumbDisassembler::getEDInfo() const {
254 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
255 const MemoryObject &Region,
257 raw_ostream &os) const {
260 // We want to read exactly 4 bytes of data.
261 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
264 // Encoded as a small-endian 32-bit word in the stream.
265 uint32_t insn = (bytes[3] << 24) |
270 // Calling the auto-generated decoder function.
271 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
272 if (result != Fail) {
277 // Instructions that are shared between ARM and Thumb modes.
278 // FIXME: This shouldn't really exist. It's an artifact of the
279 // fact that we fail to encode a few instructions properly for Thumb.
281 result = decodeCommonInstruction32(MI, insn, Address, this);
282 if (result != Fail) {
287 // VFP and NEON instructions, similarly, are shared between ARM
290 result = decodeVFPInstruction32(MI, insn, Address, this);
291 if (result != Fail) {
297 result = decodeNEONDataInstruction32(MI, insn, Address, this);
298 if (result != Fail) {
300 // Add a fake predicate operand, because we share these instruction
301 // definitions with Thumb2 where these instructions are predicable.
302 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
307 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
308 if (result != Fail) {
310 // Add a fake predicate operand, because we share these instruction
311 // definitions with Thumb2 where these instructions are predicable.
312 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
317 result = decodeNEONDupInstruction32(MI, insn, Address, this);
318 if (result != Fail) {
320 // Add a fake predicate operand, because we share these instruction
321 // definitions with Thumb2 where these instructions are predicable.
322 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
332 extern MCInstrDesc ARMInsts[];
335 // Thumb1 instructions don't have explicit S bits. Rather, they
336 // implicitly set CPSR. Since it's not represented in the encoding, the
337 // auto-generated decoder won't inject the CPSR operand. We need to fix
338 // that as a post-pass.
339 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
340 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
341 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
342 MCInst::iterator I = MI.begin();
343 for (unsigned i = 0; i < NumOps; ++i, ++I) {
344 if (I == MI.end()) break;
345 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
346 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
347 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
352 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
355 // Most Thumb instructions don't have explicit predicates in the
356 // encoding, but rather get their predicates from IT context. We need
357 // to fix up the predicate operands using this context information as a
359 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
360 // A few instructions actually have predicates encoded in them. Don't
361 // try to overwrite it if we're seeing one of those.
362 switch (MI.getOpcode()) {
370 // If we're in an IT block, base the predicate on that. Otherwise,
371 // assume a predicate of AL.
373 if (!ITBlock.empty()) {
379 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
380 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
381 MCInst::iterator I = MI.begin();
382 for (unsigned i = 0; i < NumOps; ++i, ++I) {
383 if (I == MI.end()) break;
384 if (OpInfo[i].isPredicate()) {
385 I = MI.insert(I, MCOperand::CreateImm(CC));
388 MI.insert(I, MCOperand::CreateReg(0));
390 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
395 I = MI.insert(I, MCOperand::CreateImm(CC));
398 MI.insert(I, MCOperand::CreateReg(0));
400 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
403 // Thumb VFP instructions are a special case. Because we share their
404 // encodings between ARM and Thumb modes, and they are predicable in ARM
405 // mode, the auto-generated decoder will give them an (incorrect)
406 // predicate operand. We need to rewrite these operands based on the IT
407 // context as a post-pass.
408 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
410 if (!ITBlock.empty()) {
416 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
417 MCInst::iterator I = MI.begin();
418 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) {
419 if (OpInfo[i].isPredicate() ) {
425 I->setReg(ARM::CPSR);
431 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
432 const MemoryObject &Region,
434 raw_ostream &os) const {
437 // We want to read exactly 2 bytes of data.
438 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
441 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
442 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
443 if (result != Fail) {
445 AddThumbPredicate(MI);
450 result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
453 bool InITBlock = !ITBlock.empty();
454 AddThumbPredicate(MI);
455 AddThumb1SBit(MI, InITBlock);
460 result = decodeThumb2Instruction16(MI, insn16, Address, this);
461 if (result != Fail) {
463 AddThumbPredicate(MI);
465 // If we find an IT instruction, we need to parse its condition
466 // code and mask operands so that we can apply them correctly
467 // to the subsequent instructions.
468 if (MI.getOpcode() == ARM::t2IT) {
469 unsigned firstcond = MI.getOperand(0).getImm();
470 uint32_t mask = MI.getOperand(1).getImm();
471 unsigned zeros = CountTrailingZeros_32(mask);
474 for (unsigned i = 0; i < 4 - (zeros+1); ++i) {
475 if (firstcond ^ (mask & 1))
476 ITBlock.push_back(firstcond ^ 1);
478 ITBlock.push_back(firstcond);
481 ITBlock.push_back(firstcond);
487 // We want to read exactly 4 bytes of data.
488 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
491 uint32_t insn32 = (bytes[3] << 8) |
496 result = decodeThumbInstruction32(MI, insn32, Address, this);
497 if (result != Fail) {
499 bool InITBlock = ITBlock.size();
500 AddThumbPredicate(MI);
501 AddThumb1SBit(MI, InITBlock);
506 result = decodeThumb2Instruction32(MI, insn32, Address, this);
507 if (result != Fail) {
509 AddThumbPredicate(MI);
514 result = decodeCommonInstruction32(MI, insn32, Address, this);
515 if (result != Fail) {
517 AddThumbPredicate(MI);
522 result = decodeVFPInstruction32(MI, insn32, Address, this);
523 if (result != Fail) {
525 UpdateThumbVFPPredicate(MI);
530 result = decodeNEONDupInstruction32(MI, insn32, Address, this);
531 if (result != Fail) {
533 AddThumbPredicate(MI);
537 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
539 uint32_t NEONLdStInsn = insn32;
540 NEONLdStInsn &= 0xF0FFFFFF;
541 NEONLdStInsn |= 0x04000000;
542 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
543 if (result != Fail) {
545 AddThumbPredicate(MI);
550 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
552 uint32_t NEONDataInsn = insn32;
553 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
554 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
555 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
556 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
557 if (result != Fail) {
559 AddThumbPredicate(MI);
568 extern "C" void LLVMInitializeARMDisassembler() {
569 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
570 createARMDisassembler);
571 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
572 createThumbDisassembler);
575 static const unsigned GPRDecoderTable[] = {
576 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
577 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
578 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
579 ARM::R12, ARM::SP, ARM::LR, ARM::PC
582 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
583 uint64_t Address, const void *Decoder) {
587 unsigned Register = GPRDecoderTable[RegNo];
588 Inst.addOperand(MCOperand::CreateReg(Register));
593 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
594 uint64_t Address, const void *Decoder) {
595 if (RegNo == 15) return Fail;
596 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
599 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
600 uint64_t Address, const void *Decoder) {
603 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
606 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
607 uint64_t Address, const void *Decoder) {
608 unsigned Register = 0;
632 Inst.addOperand(MCOperand::CreateReg(Register));
636 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
637 uint64_t Address, const void *Decoder) {
638 if (RegNo == 13 || RegNo == 15) return Fail;
639 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
642 static const unsigned SPRDecoderTable[] = {
643 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
644 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
645 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
646 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
647 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
648 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
649 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
650 ARM::S28, ARM::S29, ARM::S30, ARM::S31
653 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
654 uint64_t Address, const void *Decoder) {
658 unsigned Register = SPRDecoderTable[RegNo];
659 Inst.addOperand(MCOperand::CreateReg(Register));
663 static const unsigned DPRDecoderTable[] = {
664 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
665 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
666 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
667 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
668 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
669 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
670 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
671 ARM::D28, ARM::D29, ARM::D30, ARM::D31
674 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
675 uint64_t Address, const void *Decoder) {
679 unsigned Register = DPRDecoderTable[RegNo];
680 Inst.addOperand(MCOperand::CreateReg(Register));
684 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
685 uint64_t Address, const void *Decoder) {
688 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
692 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
693 uint64_t Address, const void *Decoder) {
696 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
699 static const unsigned QPRDecoderTable[] = {
700 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
701 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
702 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
703 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
707 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
708 uint64_t Address, const void *Decoder) {
713 unsigned Register = QPRDecoderTable[RegNo];
714 Inst.addOperand(MCOperand::CreateReg(Register));
718 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
719 uint64_t Address, const void *Decoder) {
720 if (Val == 0xF) return Fail;
721 // AL predicate is not allowed on Thumb1 branches.
722 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
724 Inst.addOperand(MCOperand::CreateImm(Val));
725 if (Val == ARMCC::AL) {
726 Inst.addOperand(MCOperand::CreateReg(0));
728 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
732 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
733 uint64_t Address, const void *Decoder) {
735 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
737 Inst.addOperand(MCOperand::CreateReg(0));
741 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
742 uint64_t Address, const void *Decoder) {
743 uint32_t imm = Val & 0xFF;
744 uint32_t rot = (Val & 0xF00) >> 7;
745 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
746 Inst.addOperand(MCOperand::CreateImm(rot_imm));
750 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
751 uint64_t Address, const void *Decoder) {
753 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
757 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
758 uint64_t Address, const void *Decoder) {
759 DecodeStatus S = Success;
761 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
762 unsigned type = fieldFromInstruction32(Val, 5, 2);
763 unsigned imm = fieldFromInstruction32(Val, 7, 5);
765 // Register-immediate
766 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
768 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
784 if (Shift == ARM_AM::ror && imm == 0)
787 unsigned Op = Shift | (imm << 3);
788 Inst.addOperand(MCOperand::CreateImm(Op));
793 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
794 uint64_t Address, const void *Decoder) {
795 DecodeStatus S = Success;
797 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
798 unsigned type = fieldFromInstruction32(Val, 5, 2);
799 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
802 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
803 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));
805 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
821 Inst.addOperand(MCOperand::CreateImm(Shift));
826 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
827 uint64_t Address, const void *Decoder) {
828 DecodeStatus S = Success;
830 // Empty register lists are not allowed.
831 if (CountPopulation_32(Val) == 0) return Fail;
832 for (unsigned i = 0; i < 16; ++i) {
833 if (Val & (1 << i)) {
834 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));
841 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
842 uint64_t Address, const void *Decoder) {
843 DecodeStatus S = Success;
845 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
846 unsigned regs = Val & 0xFF;
848 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));
849 for (unsigned i = 0; i < (regs - 1); ++i) {
850 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));
856 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
857 uint64_t Address, const void *Decoder) {
858 DecodeStatus S = Success;
860 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
861 unsigned regs = (Val & 0xFF) / 2;
863 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));
864 for (unsigned i = 0; i < (regs - 1); ++i) {
865 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));
871 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
872 uint64_t Address, const void *Decoder) {
873 // This operand encodes a mask of contiguous zeros between a specified MSB
874 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
875 // the mask of all bits LSB-and-lower, and then xor them to create
876 // the mask of that's all ones on [msb, lsb]. Finally we not it to
877 // create the final mask.
878 unsigned msb = fieldFromInstruction32(Val, 5, 5);
879 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
880 uint32_t msb_mask = (1 << (msb+1)) - 1;
881 uint32_t lsb_mask = (1 << lsb) - 1;
882 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
886 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
887 uint64_t Address, const void *Decoder) {
888 DecodeStatus S = Success;
890 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
891 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
892 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
893 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
894 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
895 unsigned U = fieldFromInstruction32(Insn, 23, 1);
897 switch (Inst.getOpcode()) {
898 case ARM::LDC_OFFSET:
901 case ARM::LDC_OPTION:
902 case ARM::LDCL_OFFSET:
905 case ARM::LDCL_OPTION:
906 case ARM::STC_OFFSET:
909 case ARM::STC_OPTION:
910 case ARM::STCL_OFFSET:
913 case ARM::STCL_OPTION:
914 if (coproc == 0xA || coproc == 0xB)
921 Inst.addOperand(MCOperand::CreateImm(coproc));
922 Inst.addOperand(MCOperand::CreateImm(CRd));
923 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
924 switch (Inst.getOpcode()) {
925 case ARM::LDC_OPTION:
926 case ARM::LDCL_OPTION:
927 case ARM::LDC2_OPTION:
928 case ARM::LDC2L_OPTION:
929 case ARM::STC_OPTION:
930 case ARM::STCL_OPTION:
931 case ARM::STC2_OPTION:
932 case ARM::STC2L_OPTION:
935 case ARM::LDC2L_POST:
936 case ARM::STC2L_POST:
939 Inst.addOperand(MCOperand::CreateReg(0));
943 unsigned P = fieldFromInstruction32(Insn, 24, 1);
944 unsigned W = fieldFromInstruction32(Insn, 21, 1);
946 bool writeback = (P == 0) || (W == 1);
947 unsigned idx_mode = 0;
949 idx_mode = ARMII::IndexModePre;
950 else if (!P && writeback)
951 idx_mode = ARMII::IndexModePost;
953 switch (Inst.getOpcode()) {
956 case ARM::LDC2L_POST:
957 case ARM::STC2L_POST:
959 case ARM::LDC_OPTION:
960 case ARM::LDCL_OPTION:
961 case ARM::LDC2_OPTION:
962 case ARM::LDC2L_OPTION:
963 case ARM::STC_OPTION:
964 case ARM::STCL_OPTION:
965 case ARM::STC2_OPTION:
966 case ARM::STC2L_OPTION:
967 Inst.addOperand(MCOperand::CreateImm(imm));
971 Inst.addOperand(MCOperand::CreateImm(
972 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
974 Inst.addOperand(MCOperand::CreateImm(
975 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
979 switch (Inst.getOpcode()) {
980 case ARM::LDC_OFFSET:
983 case ARM::LDC_OPTION:
984 case ARM::LDCL_OFFSET:
987 case ARM::LDCL_OPTION:
988 case ARM::STC_OFFSET:
991 case ARM::STC_OPTION:
992 case ARM::STCL_OFFSET:
995 case ARM::STCL_OPTION:
996 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1006 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1007 uint64_t Address, const void *Decoder) {
1008 DecodeStatus S = Success;
1010 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1011 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1012 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1013 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1014 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1015 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1016 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1017 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1019 // On stores, the writeback operand precedes Rt.
1020 switch (Inst.getOpcode()) {
1021 case ARM::STR_POST_IMM:
1022 case ARM::STR_POST_REG:
1023 case ARM::STRB_POST_IMM:
1024 case ARM::STRB_POST_REG:
1025 case ARM::STRT_POST_REG:
1026 case ARM::STRT_POST_IMM:
1027 case ARM::STRBT_POST_REG:
1028 case ARM::STRBT_POST_IMM:
1029 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1035 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1037 // On loads, the writeback operand comes after Rt.
1038 switch (Inst.getOpcode()) {
1039 case ARM::LDR_POST_IMM:
1040 case ARM::LDR_POST_REG:
1041 case ARM::LDRB_POST_IMM:
1042 case ARM::LDRB_POST_REG:
1045 case ARM::LDRBT_POST_REG:
1046 case ARM::LDRBT_POST_IMM:
1047 case ARM::LDRT_POST_REG:
1048 case ARM::LDRT_POST_IMM:
1049 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1055 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1057 ARM_AM::AddrOpc Op = ARM_AM::add;
1058 if (!fieldFromInstruction32(Insn, 23, 1))
1061 bool writeback = (P == 0) || (W == 1);
1062 unsigned idx_mode = 0;
1064 idx_mode = ARMII::IndexModePre;
1065 else if (!P && writeback)
1066 idx_mode = ARMII::IndexModePost;
1068 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE
1071 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1072 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1073 switch( fieldFromInstruction32(Insn, 5, 2)) {
1089 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1090 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1092 Inst.addOperand(MCOperand::CreateImm(imm));
1094 Inst.addOperand(MCOperand::CreateReg(0));
1095 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1096 Inst.addOperand(MCOperand::CreateImm(tmp));
1099 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1104 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1105 uint64_t Address, const void *Decoder) {
1106 DecodeStatus S = Success;
1108 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1109 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1110 unsigned type = fieldFromInstruction32(Val, 5, 2);
1111 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1112 unsigned U = fieldFromInstruction32(Val, 12, 1);
1114 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1130 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1131 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1134 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1136 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1137 Inst.addOperand(MCOperand::CreateImm(shift));
1143 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1144 uint64_t Address, const void *Decoder) {
1145 DecodeStatus S = Success;
1147 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1148 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1149 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1150 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1151 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1152 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1153 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1154 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1155 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1157 bool writeback = (W == 1) | (P == 0);
1159 // For {LD,ST}RD, Rt must be even, else undefined.
1160 switch (Inst.getOpcode()) {
1163 case ARM::STRD_POST:
1166 case ARM::LDRD_POST:
1167 if (Rt & 0x1) return Fail;
1173 if (writeback) { // Writeback
1175 U |= ARMII::IndexModePre << 9;
1177 U |= ARMII::IndexModePost << 9;
1179 // On stores, the writeback operand precedes Rt.
1180 switch (Inst.getOpcode()) {
1183 case ARM::STRD_POST:
1186 case ARM::STRH_POST:
1187 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1194 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1195 switch (Inst.getOpcode()) {
1198 case ARM::STRD_POST:
1201 case ARM::LDRD_POST:
1202 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
1209 // On loads, the writeback operand comes after Rt.
1210 switch (Inst.getOpcode()) {
1213 case ARM::LDRD_POST:
1216 case ARM::LDRH_POST:
1218 case ARM::LDRSH_PRE:
1219 case ARM::LDRSH_POST:
1221 case ARM::LDRSB_PRE:
1222 case ARM::LDRSB_POST:
1225 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1232 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1235 Inst.addOperand(MCOperand::CreateReg(0));
1236 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1238 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1239 Inst.addOperand(MCOperand::CreateImm(U));
1242 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1247 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1248 uint64_t Address, const void *Decoder) {
1249 DecodeStatus S = Success;
1251 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1252 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1269 Inst.addOperand(MCOperand::CreateImm(mode));
1270 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1275 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1277 uint64_t Address, const void *Decoder) {
1278 DecodeStatus S = Success;
1280 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1281 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1282 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1285 switch (Inst.getOpcode()) {
1287 Inst.setOpcode(ARM::RFEDA);
1289 case ARM::LDMDA_UPD:
1290 Inst.setOpcode(ARM::RFEDA_UPD);
1293 Inst.setOpcode(ARM::RFEDB);
1295 case ARM::LDMDB_UPD:
1296 Inst.setOpcode(ARM::RFEDB_UPD);
1299 Inst.setOpcode(ARM::RFEIA);
1301 case ARM::LDMIA_UPD:
1302 Inst.setOpcode(ARM::RFEIA_UPD);
1305 Inst.setOpcode(ARM::RFEIB);
1307 case ARM::LDMIB_UPD:
1308 Inst.setOpcode(ARM::RFEIB_UPD);
1311 Inst.setOpcode(ARM::SRSDA);
1313 case ARM::STMDA_UPD:
1314 Inst.setOpcode(ARM::SRSDA_UPD);
1317 Inst.setOpcode(ARM::SRSDB);
1319 case ARM::STMDB_UPD:
1320 Inst.setOpcode(ARM::SRSDB_UPD);
1323 Inst.setOpcode(ARM::SRSIA);
1325 case ARM::STMIA_UPD:
1326 Inst.setOpcode(ARM::SRSIA_UPD);
1329 Inst.setOpcode(ARM::SRSIB);
1331 case ARM::STMIB_UPD:
1332 Inst.setOpcode(ARM::SRSIB_UPD);
1338 // For stores (which become SRS's, the only operand is the mode.
1339 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1341 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1345 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1348 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1349 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied
1350 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1351 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));
1356 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1357 uint64_t Address, const void *Decoder) {
1358 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1359 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1360 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1361 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1363 DecodeStatus S = Success;
1365 // imod == '01' --> UNPREDICTABLE
1366 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1367 // return failure here. The '01' imod value is unprintable, so there's
1368 // nothing useful we could do even if we returned UNPREDICTABLE.
1370 if (imod == 1) CHECK(S, Fail);
1373 Inst.setOpcode(ARM::CPS3p);
1374 Inst.addOperand(MCOperand::CreateImm(imod));
1375 Inst.addOperand(MCOperand::CreateImm(iflags));
1376 Inst.addOperand(MCOperand::CreateImm(mode));
1377 } else if (imod && !M) {
1378 Inst.setOpcode(ARM::CPS2p);
1379 Inst.addOperand(MCOperand::CreateImm(imod));
1380 Inst.addOperand(MCOperand::CreateImm(iflags));
1381 if (mode) CHECK(S, Unpredictable);
1382 } else if (!imod && M) {
1383 Inst.setOpcode(ARM::CPS1p);
1384 Inst.addOperand(MCOperand::CreateImm(mode));
1385 if (iflags) CHECK(S, Unpredictable);
1387 // imod == '00' && M == '0' --> UNPREDICTABLE
1388 Inst.setOpcode(ARM::CPS1p);
1389 Inst.addOperand(MCOperand::CreateImm(mode));
1390 CHECK(S, Unpredictable);
1396 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1397 uint64_t Address, const void *Decoder) {
1398 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1399 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1400 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1401 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1403 DecodeStatus S = Success;
1405 // imod == '01' --> UNPREDICTABLE
1406 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1407 // return failure here. The '01' imod value is unprintable, so there's
1408 // nothing useful we could do even if we returned UNPREDICTABLE.
1410 if (imod == 1) CHECK(S, Fail);
1413 Inst.setOpcode(ARM::t2CPS3p);
1414 Inst.addOperand(MCOperand::CreateImm(imod));
1415 Inst.addOperand(MCOperand::CreateImm(iflags));
1416 Inst.addOperand(MCOperand::CreateImm(mode));
1417 } else if (imod && !M) {
1418 Inst.setOpcode(ARM::t2CPS2p);
1419 Inst.addOperand(MCOperand::CreateImm(imod));
1420 Inst.addOperand(MCOperand::CreateImm(iflags));
1421 if (mode) CHECK(S, Unpredictable);
1422 } else if (!imod && M) {
1423 Inst.setOpcode(ARM::t2CPS1p);
1424 Inst.addOperand(MCOperand::CreateImm(mode));
1425 if (iflags) CHECK(S, Unpredictable);
1427 // imod == '00' && M == '0' --> UNPREDICTABLE
1428 Inst.setOpcode(ARM::t2CPS1p);
1429 Inst.addOperand(MCOperand::CreateImm(mode));
1430 CHECK(S, Unpredictable);
1437 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1438 uint64_t Address, const void *Decoder) {
1439 DecodeStatus S = Success;
1441 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1442 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1443 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1444 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1445 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1448 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1450 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));
1451 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));
1452 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1453 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));
1455 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1460 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1461 uint64_t Address, const void *Decoder) {
1462 DecodeStatus S = Success;
1464 unsigned add = fieldFromInstruction32(Val, 12, 1);
1465 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1466 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1468 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1470 if (!add) imm *= -1;
1471 if (imm == 0 && !add) imm = INT32_MIN;
1472 Inst.addOperand(MCOperand::CreateImm(imm));
1477 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1478 uint64_t Address, const void *Decoder) {
1479 DecodeStatus S = Success;
1481 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1482 unsigned U = fieldFromInstruction32(Val, 8, 1);
1483 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1485 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1488 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1490 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1495 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1496 uint64_t Address, const void *Decoder) {
1497 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1501 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1502 uint64_t Address, const void *Decoder) {
1503 DecodeStatus S = Success;
1505 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1506 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1509 Inst.setOpcode(ARM::BLXi);
1510 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1511 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1515 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1516 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1522 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1523 uint64_t Address, const void *Decoder) {
1524 Inst.addOperand(MCOperand::CreateImm(64 - Val));
1528 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1529 uint64_t Address, const void *Decoder) {
1530 DecodeStatus S = Success;
1532 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1533 unsigned align = fieldFromInstruction32(Val, 4, 2);
1535 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1537 Inst.addOperand(MCOperand::CreateImm(0));
1539 Inst.addOperand(MCOperand::CreateImm(4 << align));
1544 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1545 uint64_t Address, const void *Decoder) {
1546 DecodeStatus S = Success;
1548 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1549 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1550 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1551 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1552 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1553 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1555 // First output register
1556 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1558 // Second output register
1559 switch (Inst.getOpcode()) {
1564 case ARM::VLD1q8_UPD:
1565 case ARM::VLD1q16_UPD:
1566 case ARM::VLD1q32_UPD:
1567 case ARM::VLD1q64_UPD:
1572 case ARM::VLD1d8T_UPD:
1573 case ARM::VLD1d16T_UPD:
1574 case ARM::VLD1d32T_UPD:
1575 case ARM::VLD1d64T_UPD:
1580 case ARM::VLD1d8Q_UPD:
1581 case ARM::VLD1d16Q_UPD:
1582 case ARM::VLD1d32Q_UPD:
1583 case ARM::VLD1d64Q_UPD:
1587 case ARM::VLD2d8_UPD:
1588 case ARM::VLD2d16_UPD:
1589 case ARM::VLD2d32_UPD:
1593 case ARM::VLD2q8_UPD:
1594 case ARM::VLD2q16_UPD:
1595 case ARM::VLD2q32_UPD:
1599 case ARM::VLD3d8_UPD:
1600 case ARM::VLD3d16_UPD:
1601 case ARM::VLD3d32_UPD:
1605 case ARM::VLD4d8_UPD:
1606 case ARM::VLD4d16_UPD:
1607 case ARM::VLD4d32_UPD:
1608 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1613 case ARM::VLD2b8_UPD:
1614 case ARM::VLD2b16_UPD:
1615 case ARM::VLD2b32_UPD:
1619 case ARM::VLD3q8_UPD:
1620 case ARM::VLD3q16_UPD:
1621 case ARM::VLD3q32_UPD:
1625 case ARM::VLD4q8_UPD:
1626 case ARM::VLD4q16_UPD:
1627 case ARM::VLD4q32_UPD:
1628 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1633 // Third output register
1634 switch(Inst.getOpcode()) {
1639 case ARM::VLD1d8T_UPD:
1640 case ARM::VLD1d16T_UPD:
1641 case ARM::VLD1d32T_UPD:
1642 case ARM::VLD1d64T_UPD:
1647 case ARM::VLD1d8Q_UPD:
1648 case ARM::VLD1d16Q_UPD:
1649 case ARM::VLD1d32Q_UPD:
1650 case ARM::VLD1d64Q_UPD:
1654 case ARM::VLD2q8_UPD:
1655 case ARM::VLD2q16_UPD:
1656 case ARM::VLD2q32_UPD:
1660 case ARM::VLD3d8_UPD:
1661 case ARM::VLD3d16_UPD:
1662 case ARM::VLD3d32_UPD:
1666 case ARM::VLD4d8_UPD:
1667 case ARM::VLD4d16_UPD:
1668 case ARM::VLD4d32_UPD:
1669 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1674 case ARM::VLD3q8_UPD:
1675 case ARM::VLD3q16_UPD:
1676 case ARM::VLD3q32_UPD:
1680 case ARM::VLD4q8_UPD:
1681 case ARM::VLD4q16_UPD:
1682 case ARM::VLD4q32_UPD:
1683 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1689 // Fourth output register
1690 switch (Inst.getOpcode()) {
1695 case ARM::VLD1d8Q_UPD:
1696 case ARM::VLD1d16Q_UPD:
1697 case ARM::VLD1d32Q_UPD:
1698 case ARM::VLD1d64Q_UPD:
1702 case ARM::VLD2q8_UPD:
1703 case ARM::VLD2q16_UPD:
1704 case ARM::VLD2q32_UPD:
1708 case ARM::VLD4d8_UPD:
1709 case ARM::VLD4d16_UPD:
1710 case ARM::VLD4d32_UPD:
1711 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
1716 case ARM::VLD4q8_UPD:
1717 case ARM::VLD4q16_UPD:
1718 case ARM::VLD4q32_UPD:
1719 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
1725 // Writeback operand
1726 switch (Inst.getOpcode()) {
1727 case ARM::VLD1d8_UPD:
1728 case ARM::VLD1d16_UPD:
1729 case ARM::VLD1d32_UPD:
1730 case ARM::VLD1d64_UPD:
1731 case ARM::VLD1q8_UPD:
1732 case ARM::VLD1q16_UPD:
1733 case ARM::VLD1q32_UPD:
1734 case ARM::VLD1q64_UPD:
1735 case ARM::VLD1d8T_UPD:
1736 case ARM::VLD1d16T_UPD:
1737 case ARM::VLD1d32T_UPD:
1738 case ARM::VLD1d64T_UPD:
1739 case ARM::VLD1d8Q_UPD:
1740 case ARM::VLD1d16Q_UPD:
1741 case ARM::VLD1d32Q_UPD:
1742 case ARM::VLD1d64Q_UPD:
1743 case ARM::VLD2d8_UPD:
1744 case ARM::VLD2d16_UPD:
1745 case ARM::VLD2d32_UPD:
1746 case ARM::VLD2q8_UPD:
1747 case ARM::VLD2q16_UPD:
1748 case ARM::VLD2q32_UPD:
1749 case ARM::VLD2b8_UPD:
1750 case ARM::VLD2b16_UPD:
1751 case ARM::VLD2b32_UPD:
1752 case ARM::VLD3d8_UPD:
1753 case ARM::VLD3d16_UPD:
1754 case ARM::VLD3d32_UPD:
1755 case ARM::VLD3q8_UPD:
1756 case ARM::VLD3q16_UPD:
1757 case ARM::VLD3q32_UPD:
1758 case ARM::VLD4d8_UPD:
1759 case ARM::VLD4d16_UPD:
1760 case ARM::VLD4d32_UPD:
1761 case ARM::VLD4q8_UPD:
1762 case ARM::VLD4q16_UPD:
1763 case ARM::VLD4q32_UPD:
1764 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1770 // AddrMode6 Base (register+alignment)
1771 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1773 // AddrMode6 Offset (register)
1775 Inst.addOperand(MCOperand::CreateReg(0));
1776 else if (Rm != 0xF) {
1777 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1783 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
1784 uint64_t Address, const void *Decoder) {
1785 DecodeStatus S = Success;
1787 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1788 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1789 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1790 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1791 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1792 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1794 // Writeback Operand
1795 switch (Inst.getOpcode()) {
1796 case ARM::VST1d8_UPD:
1797 case ARM::VST1d16_UPD:
1798 case ARM::VST1d32_UPD:
1799 case ARM::VST1d64_UPD:
1800 case ARM::VST1q8_UPD:
1801 case ARM::VST1q16_UPD:
1802 case ARM::VST1q32_UPD:
1803 case ARM::VST1q64_UPD:
1804 case ARM::VST1d8T_UPD:
1805 case ARM::VST1d16T_UPD:
1806 case ARM::VST1d32T_UPD:
1807 case ARM::VST1d64T_UPD:
1808 case ARM::VST1d8Q_UPD:
1809 case ARM::VST1d16Q_UPD:
1810 case ARM::VST1d32Q_UPD:
1811 case ARM::VST1d64Q_UPD:
1812 case ARM::VST2d8_UPD:
1813 case ARM::VST2d16_UPD:
1814 case ARM::VST2d32_UPD:
1815 case ARM::VST2q8_UPD:
1816 case ARM::VST2q16_UPD:
1817 case ARM::VST2q32_UPD:
1818 case ARM::VST2b8_UPD:
1819 case ARM::VST2b16_UPD:
1820 case ARM::VST2b32_UPD:
1821 case ARM::VST3d8_UPD:
1822 case ARM::VST3d16_UPD:
1823 case ARM::VST3d32_UPD:
1824 case ARM::VST3q8_UPD:
1825 case ARM::VST3q16_UPD:
1826 case ARM::VST3q32_UPD:
1827 case ARM::VST4d8_UPD:
1828 case ARM::VST4d16_UPD:
1829 case ARM::VST4d32_UPD:
1830 case ARM::VST4q8_UPD:
1831 case ARM::VST4q16_UPD:
1832 case ARM::VST4q32_UPD:
1833 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1839 // AddrMode6 Base (register+alignment)
1840 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1842 // AddrMode6 Offset (register)
1844 Inst.addOperand(MCOperand::CreateReg(0));
1845 else if (Rm != 0xF) {
1846 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1849 // First input register
1850 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1852 // Second input register
1853 switch (Inst.getOpcode()) {
1858 case ARM::VST1q8_UPD:
1859 case ARM::VST1q16_UPD:
1860 case ARM::VST1q32_UPD:
1861 case ARM::VST1q64_UPD:
1866 case ARM::VST1d8T_UPD:
1867 case ARM::VST1d16T_UPD:
1868 case ARM::VST1d32T_UPD:
1869 case ARM::VST1d64T_UPD:
1874 case ARM::VST1d8Q_UPD:
1875 case ARM::VST1d16Q_UPD:
1876 case ARM::VST1d32Q_UPD:
1877 case ARM::VST1d64Q_UPD:
1881 case ARM::VST2d8_UPD:
1882 case ARM::VST2d16_UPD:
1883 case ARM::VST2d32_UPD:
1887 case ARM::VST2q8_UPD:
1888 case ARM::VST2q16_UPD:
1889 case ARM::VST2q32_UPD:
1893 case ARM::VST3d8_UPD:
1894 case ARM::VST3d16_UPD:
1895 case ARM::VST3d32_UPD:
1899 case ARM::VST4d8_UPD:
1900 case ARM::VST4d16_UPD:
1901 case ARM::VST4d32_UPD:
1902 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1907 case ARM::VST2b8_UPD:
1908 case ARM::VST2b16_UPD:
1909 case ARM::VST2b32_UPD:
1913 case ARM::VST3q8_UPD:
1914 case ARM::VST3q16_UPD:
1915 case ARM::VST3q32_UPD:
1919 case ARM::VST4q8_UPD:
1920 case ARM::VST4q16_UPD:
1921 case ARM::VST4q32_UPD:
1922 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1928 // Third input register
1929 switch (Inst.getOpcode()) {
1934 case ARM::VST1d8T_UPD:
1935 case ARM::VST1d16T_UPD:
1936 case ARM::VST1d32T_UPD:
1937 case ARM::VST1d64T_UPD:
1942 case ARM::VST1d8Q_UPD:
1943 case ARM::VST1d16Q_UPD:
1944 case ARM::VST1d32Q_UPD:
1945 case ARM::VST1d64Q_UPD:
1949 case ARM::VST2q8_UPD:
1950 case ARM::VST2q16_UPD:
1951 case ARM::VST2q32_UPD:
1955 case ARM::VST3d8_UPD:
1956 case ARM::VST3d16_UPD:
1957 case ARM::VST3d32_UPD:
1961 case ARM::VST4d8_UPD:
1962 case ARM::VST4d16_UPD:
1963 case ARM::VST4d32_UPD:
1964 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1969 case ARM::VST3q8_UPD:
1970 case ARM::VST3q16_UPD:
1971 case ARM::VST3q32_UPD:
1975 case ARM::VST4q8_UPD:
1976 case ARM::VST4q16_UPD:
1977 case ARM::VST4q32_UPD:
1978 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1984 // Fourth input register
1985 switch (Inst.getOpcode()) {
1990 case ARM::VST1d8Q_UPD:
1991 case ARM::VST1d16Q_UPD:
1992 case ARM::VST1d32Q_UPD:
1993 case ARM::VST1d64Q_UPD:
1997 case ARM::VST2q8_UPD:
1998 case ARM::VST2q16_UPD:
1999 case ARM::VST2q32_UPD:
2003 case ARM::VST4d8_UPD:
2004 case ARM::VST4d16_UPD:
2005 case ARM::VST4d32_UPD:
2006 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
2011 case ARM::VST4q8_UPD:
2012 case ARM::VST4q16_UPD:
2013 case ARM::VST4q32_UPD:
2014 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
2023 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2024 uint64_t Address, const void *Decoder) {
2025 DecodeStatus S = Success;
2027 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2028 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2029 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2030 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2031 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2032 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2033 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2035 align *= (1 << size);
2037 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2039 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
2042 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2045 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2046 Inst.addOperand(MCOperand::CreateImm(align));
2049 Inst.addOperand(MCOperand::CreateReg(0));
2050 else if (Rm != 0xF) {
2051 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2057 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2058 uint64_t Address, const void *Decoder) {
2059 DecodeStatus S = Success;
2061 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2062 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2063 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2064 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2065 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2066 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2067 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2070 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2071 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2073 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2076 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2077 Inst.addOperand(MCOperand::CreateImm(align));
2080 Inst.addOperand(MCOperand::CreateReg(0));
2081 else if (Rm != 0xF) {
2082 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2088 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2089 uint64_t Address, const void *Decoder) {
2090 DecodeStatus S = Success;
2092 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2093 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2094 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2095 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2096 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2098 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2099 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2100 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2102 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2105 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2106 Inst.addOperand(MCOperand::CreateImm(0));
2109 Inst.addOperand(MCOperand::CreateReg(0));
2110 else if (Rm != 0xF) {
2111 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2117 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2118 uint64_t Address, const void *Decoder) {
2119 DecodeStatus S = Success;
2121 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2122 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2123 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2124 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2125 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2126 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2127 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2142 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2143 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2144 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2145 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
2147 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2150 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2151 Inst.addOperand(MCOperand::CreateImm(align));
2154 Inst.addOperand(MCOperand::CreateReg(0));
2155 else if (Rm != 0xF) {
2156 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2163 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2164 uint64_t Address, const void *Decoder) {
2165 DecodeStatus S = Success;
2167 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2168 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2169 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2170 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2171 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2172 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2173 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2174 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2177 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2179 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2182 Inst.addOperand(MCOperand::CreateImm(imm));
2184 switch (Inst.getOpcode()) {
2185 case ARM::VORRiv4i16:
2186 case ARM::VORRiv2i32:
2187 case ARM::VBICiv4i16:
2188 case ARM::VBICiv2i32:
2189 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2191 case ARM::VORRiv8i16:
2192 case ARM::VORRiv4i32:
2193 case ARM::VBICiv8i16:
2194 case ARM::VBICiv4i32:
2195 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2204 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2205 uint64_t Address, const void *Decoder) {
2206 DecodeStatus S = Success;
2208 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2209 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2210 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2211 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2212 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2214 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2215 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2216 Inst.addOperand(MCOperand::CreateImm(8 << size));
2221 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2222 uint64_t Address, const void *Decoder) {
2223 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2227 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2228 uint64_t Address, const void *Decoder) {
2229 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2233 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2234 uint64_t Address, const void *Decoder) {
2235 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2239 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2240 uint64_t Address, const void *Decoder) {
2241 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2245 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2246 uint64_t Address, const void *Decoder) {
2247 DecodeStatus S = Success;
2249 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2250 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2251 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2252 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2253 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2254 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2255 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2256 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2258 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2260 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback
2263 for (unsigned i = 0; i < length; ++i) {
2264 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));
2267 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2272 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
2273 uint64_t Address, const void *Decoder) {
2274 // The immediate needs to be a fully instantiated float. However, the
2275 // auto-generated decoder is only able to fill in some of the bits
2276 // necessary. For instance, the 'b' bit is replicated multiple times,
2277 // and is even present in inverted form in one bit. We do a little
2278 // binary parsing here to fill in those missing bits, and then
2279 // reinterpret it all as a float.
2285 fp_conv.integer = Val;
2286 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2287 fp_conv.integer |= b << 26;
2288 fp_conv.integer |= b << 27;
2289 fp_conv.integer |= b << 28;
2290 fp_conv.integer |= b << 29;
2291 fp_conv.integer |= (~b & 0x1) << 30;
2293 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
2297 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2298 uint64_t Address, const void *Decoder) {
2299 DecodeStatus S = Success;
2301 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2302 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2304 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
2306 if (Inst.getOpcode() == ARM::tADR)
2307 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2308 else if (Inst.getOpcode() == ARM::tADDrSPi)
2309 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2313 Inst.addOperand(MCOperand::CreateImm(imm));
2317 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2318 uint64_t Address, const void *Decoder) {
2319 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2323 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2324 uint64_t Address, const void *Decoder) {
2325 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2329 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2330 uint64_t Address, const void *Decoder) {
2331 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2335 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2336 uint64_t Address, const void *Decoder) {
2337 DecodeStatus S = Success;
2339 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2340 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2342 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2343 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));
2348 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2349 uint64_t Address, const void *Decoder) {
2350 DecodeStatus S = Success;
2352 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2353 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2355 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2356 Inst.addOperand(MCOperand::CreateImm(imm));
2361 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2362 uint64_t Address, const void *Decoder) {
2363 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2368 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2369 uint64_t Address, const void *Decoder) {
2370 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2371 Inst.addOperand(MCOperand::CreateImm(Val));
2376 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2377 uint64_t Address, const void *Decoder) {
2378 DecodeStatus S = Success;
2380 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2381 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2382 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2384 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2385 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));
2386 Inst.addOperand(MCOperand::CreateImm(imm));
2391 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2392 uint64_t Address, const void *Decoder) {
2393 DecodeStatus S = Success;
2395 if (Inst.getOpcode() != ARM::t2PLDs) {
2396 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2397 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2400 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2402 switch (Inst.getOpcode()) {
2404 Inst.setOpcode(ARM::t2LDRBpci);
2407 Inst.setOpcode(ARM::t2LDRHpci);
2410 Inst.setOpcode(ARM::t2LDRSHpci);
2413 Inst.setOpcode(ARM::t2LDRSBpci);
2416 Inst.setOpcode(ARM::t2PLDi12);
2417 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2423 int imm = fieldFromInstruction32(Insn, 0, 12);
2424 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2425 Inst.addOperand(MCOperand::CreateImm(imm));
2430 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2431 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2432 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2433 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));
2438 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2439 uint64_t Address, const void *Decoder) {
2440 int imm = Val & 0xFF;
2441 if (!(Val & 0x100)) imm *= -1;
2442 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2447 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2448 uint64_t Address, const void *Decoder) {
2449 DecodeStatus S = Success;
2451 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2452 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2454 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2455 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));
2460 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2461 uint64_t Address, const void *Decoder) {
2462 int imm = Val & 0xFF;
2463 if (!(Val & 0x100)) imm *= -1;
2464 Inst.addOperand(MCOperand::CreateImm(imm));
2470 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2471 uint64_t Address, const void *Decoder) {
2472 DecodeStatus S = Success;
2474 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2475 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2477 // Some instructions always use an additive offset.
2478 switch (Inst.getOpcode()) {
2490 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2491 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));
2497 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2498 uint64_t Address, const void *Decoder) {
2499 DecodeStatus S = Success;
2501 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2502 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2504 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2505 Inst.addOperand(MCOperand::CreateImm(imm));
2511 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2512 uint64_t Address, const void *Decoder) {
2513 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2515 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2516 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2517 Inst.addOperand(MCOperand::CreateImm(imm));
2522 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
2523 uint64_t Address, const void *Decoder) {
2524 DecodeStatus S = Success;
2526 if (Inst.getOpcode() == ARM::tADDrSP) {
2527 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2528 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2530 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2531 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2532 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2533 } else if (Inst.getOpcode() == ARM::tADDspr) {
2534 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2536 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2537 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2538 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2544 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
2545 uint64_t Address, const void *Decoder) {
2546 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2547 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2549 Inst.addOperand(MCOperand::CreateImm(imod));
2550 Inst.addOperand(MCOperand::CreateImm(flags));
2555 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
2556 uint64_t Address, const void *Decoder) {
2557 DecodeStatus S = Success;
2558 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2559 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2561 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;
2562 Inst.addOperand(MCOperand::CreateImm(add));
2567 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
2568 uint64_t Address, const void *Decoder) {
2569 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2573 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
2574 uint64_t Address, const void *Decoder) {
2575 if (Val == 0xA || Val == 0xB)
2578 Inst.addOperand(MCOperand::CreateImm(Val));
2583 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2584 uint64_t Address, const void *Decoder) {
2585 DecodeStatus S = Success;
2587 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2588 if (pred == 0xE || pred == 0xF) {
2589 unsigned opc = fieldFromInstruction32(Insn, 4, 2);
2594 Inst.setOpcode(ARM::t2DSB);
2597 Inst.setOpcode(ARM::t2DMB);
2600 Inst.setOpcode(ARM::t2ISB);
2604 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2605 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
2608 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2609 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2610 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2611 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2612 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2614 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));
2615 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2620 // Decode a shifted immediate operand. These basically consist
2621 // of an 8-bit value, and a 4-bit directive that specifies either
2622 // a splat operation or a rotation.
2623 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
2624 uint64_t Address, const void *Decoder) {
2625 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2627 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2628 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2631 Inst.addOperand(MCOperand::CreateImm(imm));
2634 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2637 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2640 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2645 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2646 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2647 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2648 Inst.addOperand(MCOperand::CreateImm(imm));
2655 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2656 uint64_t Address, const void *Decoder){
2657 Inst.addOperand(MCOperand::CreateImm(Val << 1));
2661 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
2662 uint64_t Address, const void *Decoder){
2663 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2667 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
2668 uint64_t Address, const void *Decoder) {
2683 Inst.addOperand(MCOperand::CreateImm(Val));
2687 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
2688 uint64_t Address, const void *Decoder) {
2689 if (!Val) return Fail;
2690 Inst.addOperand(MCOperand::CreateImm(Val));
2694 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
2695 uint64_t Address, const void *Decoder) {
2696 DecodeStatus S = Success;
2698 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2699 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2700 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2702 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2704 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2705 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2706 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2707 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2713 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
2714 uint64_t Address, const void *Decoder){
2715 DecodeStatus S = Success;
2717 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2718 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2719 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2720 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2722 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));
2724 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2725 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;
2727 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2728 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2729 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2730 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2735 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
2736 uint64_t Address, const void *Decoder) {
2737 DecodeStatus S = Success;
2739 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2740 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2741 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2742 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2743 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2744 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2746 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2748 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2749 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2750 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
2751 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2756 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
2757 uint64_t Address, const void *Decoder) {
2758 DecodeStatus S = Success;
2760 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2761 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2762 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2763 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2764 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2765 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2767 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2769 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2770 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2771 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
2772 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2777 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
2778 uint64_t Address, const void *Decoder) {
2779 DecodeStatus S = Success;
2781 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2782 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2783 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2784 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2785 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2793 if (fieldFromInstruction32(Insn, 4, 1))
2794 return Fail; // UNDEFINED
2795 index = fieldFromInstruction32(Insn, 5, 3);
2798 if (fieldFromInstruction32(Insn, 5, 1))
2799 return Fail; // UNDEFINED
2800 index = fieldFromInstruction32(Insn, 6, 2);
2801 if (fieldFromInstruction32(Insn, 4, 1))
2805 if (fieldFromInstruction32(Insn, 6, 1))
2806 return Fail; // UNDEFINED
2807 index = fieldFromInstruction32(Insn, 7, 1);
2808 if (fieldFromInstruction32(Insn, 4, 2) != 0)
2812 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2813 if (Rm != 0xF) { // Writeback
2814 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2816 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2817 Inst.addOperand(MCOperand::CreateImm(align));
2820 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2822 Inst.addOperand(MCOperand::CreateReg(0));
2825 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2826 Inst.addOperand(MCOperand::CreateImm(index));
2831 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
2832 uint64_t Address, const void *Decoder) {
2833 DecodeStatus S = Success;
2835 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2836 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2837 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2838 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2839 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2847 if (fieldFromInstruction32(Insn, 4, 1))
2848 return Fail; // UNDEFINED
2849 index = fieldFromInstruction32(Insn, 5, 3);
2852 if (fieldFromInstruction32(Insn, 5, 1))
2853 return Fail; // UNDEFINED
2854 index = fieldFromInstruction32(Insn, 6, 2);
2855 if (fieldFromInstruction32(Insn, 4, 1))
2859 if (fieldFromInstruction32(Insn, 6, 1))
2860 return Fail; // UNDEFINED
2861 index = fieldFromInstruction32(Insn, 7, 1);
2862 if (fieldFromInstruction32(Insn, 4, 2) != 0)
2866 if (Rm != 0xF) { // Writeback
2867 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2869 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2870 Inst.addOperand(MCOperand::CreateImm(align));
2873 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2875 Inst.addOperand(MCOperand::CreateReg(0));
2878 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2879 Inst.addOperand(MCOperand::CreateImm(index));
2885 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
2886 uint64_t Address, const void *Decoder) {
2887 DecodeStatus S = Success;
2889 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2890 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2891 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2892 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2893 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2902 index = fieldFromInstruction32(Insn, 5, 3);
2903 if (fieldFromInstruction32(Insn, 4, 1))
2907 index = fieldFromInstruction32(Insn, 6, 2);
2908 if (fieldFromInstruction32(Insn, 4, 1))
2910 if (fieldFromInstruction32(Insn, 5, 1))
2914 if (fieldFromInstruction32(Insn, 5, 1))
2915 return Fail; // UNDEFINED
2916 index = fieldFromInstruction32(Insn, 7, 1);
2917 if (fieldFromInstruction32(Insn, 4, 1) != 0)
2919 if (fieldFromInstruction32(Insn, 6, 1))
2924 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2925 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2926 if (Rm != 0xF) { // Writeback
2927 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2929 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2930 Inst.addOperand(MCOperand::CreateImm(align));
2933 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2935 Inst.addOperand(MCOperand::CreateReg(0));
2938 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2939 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2940 Inst.addOperand(MCOperand::CreateImm(index));
2945 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
2946 uint64_t Address, const void *Decoder) {
2947 DecodeStatus S = Success;
2949 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2950 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2951 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2952 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2953 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2962 index = fieldFromInstruction32(Insn, 5, 3);
2963 if (fieldFromInstruction32(Insn, 4, 1))
2967 index = fieldFromInstruction32(Insn, 6, 2);
2968 if (fieldFromInstruction32(Insn, 4, 1))
2970 if (fieldFromInstruction32(Insn, 5, 1))
2974 if (fieldFromInstruction32(Insn, 5, 1))
2975 return Fail; // UNDEFINED
2976 index = fieldFromInstruction32(Insn, 7, 1);
2977 if (fieldFromInstruction32(Insn, 4, 1) != 0)
2979 if (fieldFromInstruction32(Insn, 6, 1))
2984 if (Rm != 0xF) { // Writeback
2985 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2987 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2988 Inst.addOperand(MCOperand::CreateImm(align));
2991 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2993 Inst.addOperand(MCOperand::CreateReg(0));
2996 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2997 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2998 Inst.addOperand(MCOperand::CreateImm(index));
3004 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3005 uint64_t Address, const void *Decoder) {
3006 DecodeStatus S = Success;
3008 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3009 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3010 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3011 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3012 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3021 if (fieldFromInstruction32(Insn, 4, 1))
3022 return Fail; // UNDEFINED
3023 index = fieldFromInstruction32(Insn, 5, 3);
3026 if (fieldFromInstruction32(Insn, 4, 1))
3027 return Fail; // UNDEFINED
3028 index = fieldFromInstruction32(Insn, 6, 2);
3029 if (fieldFromInstruction32(Insn, 5, 1))
3033 if (fieldFromInstruction32(Insn, 4, 2))
3034 return Fail; // UNDEFINED
3035 index = fieldFromInstruction32(Insn, 7, 1);
3036 if (fieldFromInstruction32(Insn, 6, 1))
3041 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3042 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3043 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3045 if (Rm != 0xF) { // Writeback
3046 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3048 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3049 Inst.addOperand(MCOperand::CreateImm(align));
3052 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3054 Inst.addOperand(MCOperand::CreateReg(0));
3057 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3058 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3059 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3060 Inst.addOperand(MCOperand::CreateImm(index));
3065 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3066 uint64_t Address, const void *Decoder) {
3067 DecodeStatus S = Success;
3069 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3070 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3071 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3072 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3073 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3082 if (fieldFromInstruction32(Insn, 4, 1))
3083 return Fail; // UNDEFINED
3084 index = fieldFromInstruction32(Insn, 5, 3);
3087 if (fieldFromInstruction32(Insn, 4, 1))
3088 return Fail; // UNDEFINED
3089 index = fieldFromInstruction32(Insn, 6, 2);
3090 if (fieldFromInstruction32(Insn, 5, 1))
3094 if (fieldFromInstruction32(Insn, 4, 2))
3095 return Fail; // UNDEFINED
3096 index = fieldFromInstruction32(Insn, 7, 1);
3097 if (fieldFromInstruction32(Insn, 6, 1))
3102 if (Rm != 0xF) { // Writeback
3103 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3105 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3106 Inst.addOperand(MCOperand::CreateImm(align));
3109 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3111 Inst.addOperand(MCOperand::CreateReg(0));
3114 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3115 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3116 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3117 Inst.addOperand(MCOperand::CreateImm(index));
3123 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3124 uint64_t Address, const void *Decoder) {
3125 DecodeStatus S = Success;
3127 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3128 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3129 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3130 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3131 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3140 if (fieldFromInstruction32(Insn, 4, 1))
3142 index = fieldFromInstruction32(Insn, 5, 3);
3145 if (fieldFromInstruction32(Insn, 4, 1))
3147 index = fieldFromInstruction32(Insn, 6, 2);
3148 if (fieldFromInstruction32(Insn, 5, 1))
3152 if (fieldFromInstruction32(Insn, 4, 2))
3153 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3154 index = fieldFromInstruction32(Insn, 7, 1);
3155 if (fieldFromInstruction32(Insn, 6, 1))
3160 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3161 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3162 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3163 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3165 if (Rm != 0xF) { // Writeback
3166 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3168 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3169 Inst.addOperand(MCOperand::CreateImm(align));
3172 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3174 Inst.addOperand(MCOperand::CreateReg(0));
3177 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3178 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3179 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3180 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3181 Inst.addOperand(MCOperand::CreateImm(index));
3186 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3187 uint64_t Address, const void *Decoder) {
3188 DecodeStatus S = Success;
3190 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3191 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3192 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3193 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3194 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3203 if (fieldFromInstruction32(Insn, 4, 1))
3205 index = fieldFromInstruction32(Insn, 5, 3);
3208 if (fieldFromInstruction32(Insn, 4, 1))
3210 index = fieldFromInstruction32(Insn, 6, 2);
3211 if (fieldFromInstruction32(Insn, 5, 1))
3215 if (fieldFromInstruction32(Insn, 4, 2))
3216 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3217 index = fieldFromInstruction32(Insn, 7, 1);
3218 if (fieldFromInstruction32(Insn, 6, 1))
3223 if (Rm != 0xF) { // Writeback
3224 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3226 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3227 Inst.addOperand(MCOperand::CreateImm(align));
3230 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3232 Inst.addOperand(MCOperand::CreateReg(0));
3235 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3236 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3237 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3238 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3239 Inst.addOperand(MCOperand::CreateImm(index));
3244 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3245 uint64_t Address, const void *Decoder) {
3246 DecodeStatus S = Success;
3247 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3248 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3249 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3250 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3251 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3253 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3254 CHECK(S, Unpredictable);
3256 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
3257 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3258 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
3259 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3260 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3265 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
3266 uint64_t Address, const void *Decoder) {
3267 DecodeStatus S = Success;
3268 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3269 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3270 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3271 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3272 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3274 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3275 CHECK(S, Unpredictable);
3277 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
3278 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3279 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
3280 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3281 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));