1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
29 #define DEBUG_TYPE "arm-disassembler"
31 typedef MCDisassembler::DecodeStatus DecodeStatus;
34 // Handles the condition code status of instructions in IT blocks
38 // Returns the condition code for instruction in IT block
40 unsigned CC = ARMCC::AL;
46 // Advances the IT block state to the next T or E
47 void advanceITState() {
51 // Returns true if the current instruction is in an IT block
52 bool instrInITBlock() {
53 return !ITStates.empty();
56 // Returns true if current instruction is the last instruction in an IT block
57 bool instrLastInITBlock() {
58 return ITStates.size() == 1;
61 // Called when decoding an IT instruction. Sets the IT state for the following
62 // instructions that for the IT block. Firstcond and Mask correspond to the
63 // fields in the IT instruction encoding.
64 void setITState(char Firstcond, char Mask) {
65 // (3 - the number of trailing zeros) is the number of then / else.
66 unsigned CondBit0 = Firstcond & 1;
67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
69 assert(NumTZ <= 3 && "Invalid IT mask!");
70 // push condition codes onto the stack the correct order for the pops
71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
72 bool T = ((Mask >> Pos) & 1) == CondBit0;
74 ITStates.push_back(CCBits);
76 ITStates.push_back(CCBits ^ 1);
78 ITStates.push_back(CCBits);
82 std::vector<unsigned char> ITStates;
87 /// ARM disassembler for all ARM platforms.
88 class ARMDisassembler : public MCDisassembler {
90 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
91 MCDisassembler(STI, Ctx) {
94 ~ARMDisassembler() override {}
96 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
97 ArrayRef<uint8_t> Bytes, uint64_t Address,
99 raw_ostream &CStream) const override;
102 /// Thumb disassembler for all Thumb platforms.
103 class ThumbDisassembler : public MCDisassembler {
105 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
106 MCDisassembler(STI, Ctx) {
109 ~ThumbDisassembler() override {}
111 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
112 ArrayRef<uint8_t> Bytes, uint64_t Address,
113 raw_ostream &VStream,
114 raw_ostream &CStream) const override;
117 mutable ITStatus ITBlock;
118 DecodeStatus AddThumbPredicate(MCInst&) const;
119 void UpdateThumbVFPPredicate(MCInst&) const;
123 static bool Check(DecodeStatus &Out, DecodeStatus In) {
125 case MCDisassembler::Success:
126 // Out stays the same.
128 case MCDisassembler::SoftFail:
131 case MCDisassembler::Fail:
135 llvm_unreachable("Invalid DecodeStatus!");
139 // Forward declare these because the autogenerated code will reference them.
140 // Definitions are further down.
141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
142 uint64_t Address, const void *Decoder);
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
144 unsigned RegNo, uint64_t Address,
145 const void *Decoder);
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
147 unsigned RegNo, uint64_t Address,
148 const void *Decoder);
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
150 uint64_t Address, const void *Decoder);
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
152 uint64_t Address, const void *Decoder);
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
154 uint64_t Address, const void *Decoder);
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
156 uint64_t Address, const void *Decoder);
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
158 uint64_t Address, const void *Decoder);
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
160 uint64_t Address, const void *Decoder);
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
162 uint64_t Address, const void *Decoder);
163 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
166 const void *Decoder);
167 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
168 uint64_t Address, const void *Decoder);
169 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
170 uint64_t Address, const void *Decoder);
171 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
172 unsigned RegNo, uint64_t Address,
173 const void *Decoder);
175 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
176 uint64_t Address, const void *Decoder);
177 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
178 uint64_t Address, const void *Decoder);
179 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
180 uint64_t Address, const void *Decoder);
181 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
182 uint64_t Address, const void *Decoder);
183 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
184 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
193 const void *Decoder);
194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
199 uint64_t Address, const void *Decoder);
200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
201 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
206 const void *Decoder);
207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
232 uint64_t Address, const void *Decoder);
233 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
234 uint64_t Address, const void *Decoder);
235 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
236 uint64_t Address, const void *Decoder);
237 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
238 uint64_t Address, const void *Decoder);
239 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
240 uint64_t Address, const void *Decoder);
241 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
242 uint64_t Address, const void *Decoder);
243 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
244 uint64_t Address, const void *Decoder);
245 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
246 uint64_t Address, const void *Decoder);
247 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
248 uint64_t Address, const void *Decoder);
249 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
250 uint64_t Address, const void *Decoder);
251 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
252 uint64_t Address, const void *Decoder);
253 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
254 uint64_t Address, const void *Decoder);
255 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
256 uint64_t Address, const void *Decoder);
257 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
258 uint64_t Address, const void *Decoder);
259 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
260 uint64_t Address, const void *Decoder);
261 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
262 uint64_t Address, const void *Decoder);
263 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
264 uint64_t Address, const void *Decoder);
265 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
266 uint64_t Address, const void *Decoder);
267 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
268 uint64_t Address, const void *Decoder);
269 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
270 uint64_t Address, const void *Decoder);
271 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
272 uint64_t Address, const void *Decoder);
273 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
274 uint64_t Address, const void *Decoder);
275 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
276 uint64_t Address, const void *Decoder);
277 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
278 uint64_t Address, const void *Decoder);
279 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
280 uint64_t Address, const void *Decoder);
281 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
282 uint64_t Address, const void *Decoder);
283 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
284 uint64_t Address, const void *Decoder);
285 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
286 uint64_t Address, const void *Decoder);
287 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
288 uint64_t Address, const void *Decoder);
289 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
290 uint64_t Address, const void *Decoder);
291 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
292 uint64_t Address, const void *Decoder);
293 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
294 uint64_t Address, const void *Decoder);
295 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
296 uint64_t Address, const void *Decoder);
297 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
298 uint64_t Address, const void *Decoder);
299 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
300 uint64_t Address, const void *Decoder);
301 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
302 uint64_t Address, const void *Decoder);
303 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
304 uint64_t Address, const void *Decoder);
305 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
306 uint64_t Address, const void *Decoder);
307 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
308 uint64_t Address, const void *Decoder);
309 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
310 uint64_t Address, const void *Decoder);
311 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
312 uint64_t Address, const void *Decoder);
313 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
314 uint64_t Address, const void *Decoder);
315 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
316 uint64_t Address, const void *Decoder);
319 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
320 uint64_t Address, const void *Decoder);
321 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
322 uint64_t Address, const void *Decoder);
323 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
324 uint64_t Address, const void *Decoder);
325 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
326 uint64_t Address, const void *Decoder);
327 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
328 uint64_t Address, const void *Decoder);
329 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
330 uint64_t Address, const void *Decoder);
331 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
332 uint64_t Address, const void *Decoder);
333 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
334 uint64_t Address, const void *Decoder);
335 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
336 uint64_t Address, const void *Decoder);
337 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
338 uint64_t Address, const void *Decoder);
339 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
340 uint64_t Address, const void* Decoder);
341 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
342 uint64_t Address, const void* Decoder);
343 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
344 uint64_t Address, const void* Decoder);
345 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
346 uint64_t Address, const void* Decoder);
347 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
348 uint64_t Address, const void *Decoder);
349 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
350 uint64_t Address, const void *Decoder);
351 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
352 uint64_t Address, const void *Decoder);
353 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
354 uint64_t Address, const void *Decoder);
355 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
356 uint64_t Address, const void *Decoder);
357 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
358 uint64_t Address, const void *Decoder);
359 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
360 uint64_t Address, const void *Decoder);
361 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
362 uint64_t Address, const void *Decoder);
363 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
364 uint64_t Address, const void *Decoder);
365 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
366 uint64_t Address, const void *Decoder);
367 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
368 uint64_t Address, const void *Decoder);
369 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
370 uint64_t Address, const void *Decoder);
371 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
372 uint64_t Address, const void *Decoder);
373 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
374 uint64_t Address, const void *Decoder);
375 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
376 uint64_t Address, const void *Decoder);
377 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
378 uint64_t Address, const void *Decoder);
379 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
380 uint64_t Address, const void *Decoder);
381 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
382 uint64_t Address, const void *Decoder);
383 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
384 uint64_t Address, const void *Decoder);
385 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
386 uint64_t Address, const void *Decoder);
387 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
388 uint64_t Address, const void *Decoder);
389 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
390 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
395 uint64_t Address, const void *Decoder);
396 #include "ARMGenDisassemblerTables.inc"
398 static MCDisassembler *createARMDisassembler(const Target &T,
399 const MCSubtargetInfo &STI,
401 return new ARMDisassembler(STI, Ctx);
404 static MCDisassembler *createThumbDisassembler(const Target &T,
405 const MCSubtargetInfo &STI,
407 return new ThumbDisassembler(STI, Ctx);
410 // Post-decoding checks
411 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
412 uint64_t Address, raw_ostream &OS,
417 switch (MI.getOpcode()) {
419 // HVC is undefined if condition = 0xf otherwise upredictable
420 // if condition != 0xe
421 uint32_t Cond = (Insn >> 28) & 0xF;
423 return MCDisassembler::Fail;
425 return MCDisassembler::SoftFail;
428 default: return Result;
432 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
433 ArrayRef<uint8_t> Bytes,
434 uint64_t Address, raw_ostream &OS,
435 raw_ostream &CS) const {
438 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
439 "Asked to disassemble an ARM instruction but Subtarget is in Thumb "
442 // We want to read exactly 4 bytes of data.
443 if (Bytes.size() < 4) {
445 return MCDisassembler::Fail;
448 // Encoded as a small-endian 32-bit word in the stream.
450 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);
452 // Calling the auto-generated decoder function.
453 DecodeStatus Result =
454 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
455 if (Result != MCDisassembler::Fail) {
457 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result);
460 // VFP and NEON instructions, similarly, are shared between ARM
462 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI);
463 if (Result != MCDisassembler::Fail) {
468 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI);
469 if (Result != MCDisassembler::Fail) {
475 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI);
476 if (Result != MCDisassembler::Fail) {
478 // Add a fake predicate operand, because we share these instruction
479 // definitions with Thumb2 where these instructions are predicable.
480 if (!DecodePredicateOperand(MI, 0xE, Address, this))
481 return MCDisassembler::Fail;
485 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address,
487 if (Result != MCDisassembler::Fail) {
489 // Add a fake predicate operand, because we share these instruction
490 // definitions with Thumb2 where these instructions are predicable.
491 if (!DecodePredicateOperand(MI, 0xE, Address, this))
492 return MCDisassembler::Fail;
497 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI);
498 if (Result != MCDisassembler::Fail) {
500 // Add a fake predicate operand, because we share these instruction
501 // definitions with Thumb2 where these instructions are predicable.
502 if (!DecodePredicateOperand(MI, 0xE, Address, this))
503 return MCDisassembler::Fail;
508 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI);
509 if (Result != MCDisassembler::Fail) {
515 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI);
516 if (Result != MCDisassembler::Fail) {
522 return MCDisassembler::Fail;
526 extern const MCInstrDesc ARMInsts[];
529 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
530 /// immediate Value in the MCInst. The immediate Value has had any PC
531 /// adjustment made by the caller. If the instruction is a branch instruction
532 /// then isBranch is true, else false. If the getOpInfo() function was set as
533 /// part of the setupForSymbolicDisassembly() call then that function is called
534 /// to get any symbolic information at the Address for this instruction. If
535 /// that returns non-zero then the symbolic information it returns is used to
536 /// create an MCExpr and that is added as an operand to the MCInst. If
537 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
538 /// Value is done and if a symbol is found an MCExpr is created with that, else
539 /// an MCExpr with Value is created. This function returns true if it adds an
540 /// operand to the MCInst and false otherwise.
541 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
542 bool isBranch, uint64_t InstSize,
543 MCInst &MI, const void *Decoder) {
544 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
545 // FIXME: Does it make sense for value to be negative?
546 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
547 /* Offset */ 0, InstSize);
550 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
551 /// referenced by a load instruction with the base register that is the Pc.
552 /// These can often be values in a literal pool near the Address of the
553 /// instruction. The Address of the instruction and its immediate Value are
554 /// used as a possible literal pool entry. The SymbolLookUp call back will
555 /// return the name of a symbol referenced by the literal pool's entry if
556 /// the referenced address is that of a symbol. Or it will return a pointer to
557 /// a literal 'C' string if the referenced address of the literal pool's entry
558 /// is an address into a section with 'C' string literals.
559 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
560 const void *Decoder) {
561 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
562 Dis->tryAddingPcLoadReferenceComment(Value, Address);
565 // Thumb1 instructions don't have explicit S bits. Rather, they
566 // implicitly set CPSR. Since it's not represented in the encoding, the
567 // auto-generated decoder won't inject the CPSR operand. We need to fix
568 // that as a post-pass.
569 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
570 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
571 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
572 MCInst::iterator I = MI.begin();
573 for (unsigned i = 0; i < NumOps; ++i, ++I) {
574 if (I == MI.end()) break;
575 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
576 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
577 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
582 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
585 // Most Thumb instructions don't have explicit predicates in the
586 // encoding, but rather get their predicates from IT context. We need
587 // to fix up the predicate operands using this context information as a
589 MCDisassembler::DecodeStatus
590 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
591 MCDisassembler::DecodeStatus S = Success;
593 // A few instructions actually have predicates encoded in them. Don't
594 // try to overwrite it if we're seeing one of those.
595 switch (MI.getOpcode()) {
606 // Some instructions (mostly conditional branches) are not
607 // allowed in IT blocks.
608 if (ITBlock.instrInITBlock())
617 // Some instructions (mostly unconditional branches) can
618 // only appears at the end of, or outside of, an IT.
619 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
626 // If we're in an IT block, base the predicate on that. Otherwise,
627 // assume a predicate of AL.
629 CC = ITBlock.getITCC();
632 if (ITBlock.instrInITBlock())
633 ITBlock.advanceITState();
635 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
636 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
637 MCInst::iterator I = MI.begin();
638 for (unsigned i = 0; i < NumOps; ++i, ++I) {
639 if (I == MI.end()) break;
640 if (OpInfo[i].isPredicate()) {
641 I = MI.insert(I, MCOperand::createImm(CC));
644 MI.insert(I, MCOperand::createReg(0));
646 MI.insert(I, MCOperand::createReg(ARM::CPSR));
651 I = MI.insert(I, MCOperand::createImm(CC));
654 MI.insert(I, MCOperand::createReg(0));
656 MI.insert(I, MCOperand::createReg(ARM::CPSR));
661 // Thumb VFP instructions are a special case. Because we share their
662 // encodings between ARM and Thumb modes, and they are predicable in ARM
663 // mode, the auto-generated decoder will give them an (incorrect)
664 // predicate operand. We need to rewrite these operands based on the IT
665 // context as a post-pass.
666 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
668 CC = ITBlock.getITCC();
669 if (ITBlock.instrInITBlock())
670 ITBlock.advanceITState();
672 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
673 MCInst::iterator I = MI.begin();
674 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
675 for (unsigned i = 0; i < NumOps; ++i, ++I) {
676 if (OpInfo[i].isPredicate() ) {
682 I->setReg(ARM::CPSR);
688 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
689 ArrayRef<uint8_t> Bytes,
692 raw_ostream &CS) const {
695 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
696 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
698 // We want to read exactly 2 bytes of data.
699 if (Bytes.size() < 2) {
701 return MCDisassembler::Fail;
704 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0];
705 DecodeStatus Result =
706 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
707 if (Result != MCDisassembler::Fail) {
709 Check(Result, AddThumbPredicate(MI));
713 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this,
717 bool InITBlock = ITBlock.instrInITBlock();
718 Check(Result, AddThumbPredicate(MI));
719 AddThumb1SBit(MI, InITBlock);
724 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
725 if (Result != MCDisassembler::Fail) {
728 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
729 // the Thumb predicate.
730 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
731 Result = MCDisassembler::SoftFail;
733 Check(Result, AddThumbPredicate(MI));
735 // If we find an IT instruction, we need to parse its condition
736 // code and mask operands so that we can apply them correctly
737 // to the subsequent instructions.
738 if (MI.getOpcode() == ARM::t2IT) {
740 unsigned Firstcond = MI.getOperand(0).getImm();
741 unsigned Mask = MI.getOperand(1).getImm();
742 ITBlock.setITState(Firstcond, Mask);
748 // We want to read exactly 4 bytes of data.
749 if (Bytes.size() < 4) {
751 return MCDisassembler::Fail;
755 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16);
757 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
758 if (Result != MCDisassembler::Fail) {
760 bool InITBlock = ITBlock.instrInITBlock();
761 Check(Result, AddThumbPredicate(MI));
762 AddThumb1SBit(MI, InITBlock);
767 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
768 if (Result != MCDisassembler::Fail) {
770 Check(Result, AddThumbPredicate(MI));
774 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
776 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
777 if (Result != MCDisassembler::Fail) {
779 UpdateThumbVFPPredicate(MI);
785 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
786 if (Result != MCDisassembler::Fail) {
791 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) {
792 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this,
794 if (Result != MCDisassembler::Fail) {
796 Check(Result, AddThumbPredicate(MI));
801 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) {
802 uint32_t NEONLdStInsn = Insn32;
803 NEONLdStInsn &= 0xF0FFFFFF;
804 NEONLdStInsn |= 0x04000000;
805 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
807 if (Result != MCDisassembler::Fail) {
809 Check(Result, AddThumbPredicate(MI));
814 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) {
815 uint32_t NEONDataInsn = Insn32;
816 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
817 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
818 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
819 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
821 if (Result != MCDisassembler::Fail) {
823 Check(Result, AddThumbPredicate(MI));
827 uint32_t NEONCryptoInsn = Insn32;
828 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
829 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
830 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
831 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
833 if (Result != MCDisassembler::Fail) {
838 uint32_t NEONv8Insn = Insn32;
839 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
840 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
842 if (Result != MCDisassembler::Fail) {
849 return MCDisassembler::Fail;
853 extern "C" void LLVMInitializeARMDisassembler() {
854 TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
855 createARMDisassembler);
856 TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
857 createARMDisassembler);
858 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
859 createThumbDisassembler);
860 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
861 createThumbDisassembler);
864 static const uint16_t GPRDecoderTable[] = {
865 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
866 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
867 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
868 ARM::R12, ARM::SP, ARM::LR, ARM::PC
871 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
872 uint64_t Address, const void *Decoder) {
874 return MCDisassembler::Fail;
876 unsigned Register = GPRDecoderTable[RegNo];
877 Inst.addOperand(MCOperand::createReg(Register));
878 return MCDisassembler::Success;
882 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
883 uint64_t Address, const void *Decoder) {
884 DecodeStatus S = MCDisassembler::Success;
887 S = MCDisassembler::SoftFail;
889 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
895 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
896 uint64_t Address, const void *Decoder) {
897 DecodeStatus S = MCDisassembler::Success;
901 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
902 return MCDisassembler::Success;
905 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
909 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
910 uint64_t Address, const void *Decoder) {
912 return MCDisassembler::Fail;
913 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
916 static const uint16_t GPRPairDecoderTable[] = {
917 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
918 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
921 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
922 uint64_t Address, const void *Decoder) {
923 DecodeStatus S = MCDisassembler::Success;
926 return MCDisassembler::Fail;
928 if ((RegNo & 1) || RegNo == 0xe)
929 S = MCDisassembler::SoftFail;
931 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
932 Inst.addOperand(MCOperand::createReg(RegisterPair));
936 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
937 uint64_t Address, const void *Decoder) {
938 unsigned Register = 0;
959 return MCDisassembler::Fail;
962 Inst.addOperand(MCOperand::createReg(Register));
963 return MCDisassembler::Success;
966 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
967 uint64_t Address, const void *Decoder) {
968 DecodeStatus S = MCDisassembler::Success;
969 if (RegNo == 13 || RegNo == 15)
970 S = MCDisassembler::SoftFail;
971 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
975 static const uint16_t SPRDecoderTable[] = {
976 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
977 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
978 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
979 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
980 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
981 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
982 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
983 ARM::S28, ARM::S29, ARM::S30, ARM::S31
986 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
987 uint64_t Address, const void *Decoder) {
989 return MCDisassembler::Fail;
991 unsigned Register = SPRDecoderTable[RegNo];
992 Inst.addOperand(MCOperand::createReg(Register));
993 return MCDisassembler::Success;
996 static const uint16_t DPRDecoderTable[] = {
997 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
998 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
999 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1000 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1001 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1002 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1003 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1004 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1007 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1008 uint64_t Address, const void *Decoder) {
1009 const FeatureBitset &featureBits =
1010 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1012 bool hasD16 = featureBits[ARM::FeatureD16];
1014 if (RegNo > 31 || (hasD16 && RegNo > 15))
1015 return MCDisassembler::Fail;
1017 unsigned Register = DPRDecoderTable[RegNo];
1018 Inst.addOperand(MCOperand::createReg(Register));
1019 return MCDisassembler::Success;
1022 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1023 uint64_t Address, const void *Decoder) {
1025 return MCDisassembler::Fail;
1026 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1030 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1031 uint64_t Address, const void *Decoder) {
1033 return MCDisassembler::Fail;
1034 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1037 static const uint16_t QPRDecoderTable[] = {
1038 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1039 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1040 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1041 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1045 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1046 uint64_t Address, const void *Decoder) {
1047 if (RegNo > 31 || (RegNo & 1) != 0)
1048 return MCDisassembler::Fail;
1051 unsigned Register = QPRDecoderTable[RegNo];
1052 Inst.addOperand(MCOperand::createReg(Register));
1053 return MCDisassembler::Success;
1056 static const uint16_t DPairDecoderTable[] = {
1057 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1058 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1059 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1060 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1061 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1065 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1066 uint64_t Address, const void *Decoder) {
1068 return MCDisassembler::Fail;
1070 unsigned Register = DPairDecoderTable[RegNo];
1071 Inst.addOperand(MCOperand::createReg(Register));
1072 return MCDisassembler::Success;
1075 static const uint16_t DPairSpacedDecoderTable[] = {
1076 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1077 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1078 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1079 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1080 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1081 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1082 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1083 ARM::D28_D30, ARM::D29_D31
1086 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1089 const void *Decoder) {
1091 return MCDisassembler::Fail;
1093 unsigned Register = DPairSpacedDecoderTable[RegNo];
1094 Inst.addOperand(MCOperand::createReg(Register));
1095 return MCDisassembler::Success;
1098 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1099 uint64_t Address, const void *Decoder) {
1100 if (Val == 0xF) return MCDisassembler::Fail;
1101 // AL predicate is not allowed on Thumb1 branches.
1102 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1103 return MCDisassembler::Fail;
1104 Inst.addOperand(MCOperand::createImm(Val));
1105 if (Val == ARMCC::AL) {
1106 Inst.addOperand(MCOperand::createReg(0));
1108 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1109 return MCDisassembler::Success;
1112 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1113 uint64_t Address, const void *Decoder) {
1115 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1117 Inst.addOperand(MCOperand::createReg(0));
1118 return MCDisassembler::Success;
1121 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1122 uint64_t Address, const void *Decoder) {
1123 DecodeStatus S = MCDisassembler::Success;
1125 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1126 unsigned type = fieldFromInstruction(Val, 5, 2);
1127 unsigned imm = fieldFromInstruction(Val, 7, 5);
1129 // Register-immediate
1130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1131 return MCDisassembler::Fail;
1133 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1136 Shift = ARM_AM::lsl;
1139 Shift = ARM_AM::lsr;
1142 Shift = ARM_AM::asr;
1145 Shift = ARM_AM::ror;
1149 if (Shift == ARM_AM::ror && imm == 0)
1150 Shift = ARM_AM::rrx;
1152 unsigned Op = Shift | (imm << 3);
1153 Inst.addOperand(MCOperand::createImm(Op));
1158 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1159 uint64_t Address, const void *Decoder) {
1160 DecodeStatus S = MCDisassembler::Success;
1162 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1163 unsigned type = fieldFromInstruction(Val, 5, 2);
1164 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1166 // Register-register
1167 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1168 return MCDisassembler::Fail;
1169 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1170 return MCDisassembler::Fail;
1172 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1175 Shift = ARM_AM::lsl;
1178 Shift = ARM_AM::lsr;
1181 Shift = ARM_AM::asr;
1184 Shift = ARM_AM::ror;
1188 Inst.addOperand(MCOperand::createImm(Shift));
1193 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1194 uint64_t Address, const void *Decoder) {
1195 DecodeStatus S = MCDisassembler::Success;
1197 bool NeedDisjointWriteback = false;
1198 unsigned WritebackReg = 0;
1199 switch (Inst.getOpcode()) {
1202 case ARM::LDMIA_UPD:
1203 case ARM::LDMDB_UPD:
1204 case ARM::LDMIB_UPD:
1205 case ARM::LDMDA_UPD:
1206 case ARM::t2LDMIA_UPD:
1207 case ARM::t2LDMDB_UPD:
1208 case ARM::t2STMIA_UPD:
1209 case ARM::t2STMDB_UPD:
1210 NeedDisjointWriteback = true;
1211 WritebackReg = Inst.getOperand(0).getReg();
1215 // Empty register lists are not allowed.
1216 if (Val == 0) return MCDisassembler::Fail;
1217 for (unsigned i = 0; i < 16; ++i) {
1218 if (Val & (1 << i)) {
1219 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1220 return MCDisassembler::Fail;
1221 // Writeback not allowed if Rn is in the target list.
1222 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1223 Check(S, MCDisassembler::SoftFail);
1230 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1231 uint64_t Address, const void *Decoder) {
1232 DecodeStatus S = MCDisassembler::Success;
1234 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1235 unsigned regs = fieldFromInstruction(Val, 0, 8);
1237 // In case of unpredictable encoding, tweak the operands.
1238 if (regs == 0 || (Vd + regs) > 32) {
1239 regs = Vd + regs > 32 ? 32 - Vd : regs;
1240 regs = std::max( 1u, regs);
1241 S = MCDisassembler::SoftFail;
1244 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1245 return MCDisassembler::Fail;
1246 for (unsigned i = 0; i < (regs - 1); ++i) {
1247 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1248 return MCDisassembler::Fail;
1254 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1255 uint64_t Address, const void *Decoder) {
1256 DecodeStatus S = MCDisassembler::Success;
1258 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1259 unsigned regs = fieldFromInstruction(Val, 1, 7);
1261 // In case of unpredictable encoding, tweak the operands.
1262 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1263 regs = Vd + regs > 32 ? 32 - Vd : regs;
1264 regs = std::max( 1u, regs);
1265 regs = std::min(16u, regs);
1266 S = MCDisassembler::SoftFail;
1269 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1270 return MCDisassembler::Fail;
1271 for (unsigned i = 0; i < (regs - 1); ++i) {
1272 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1273 return MCDisassembler::Fail;
1279 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1280 uint64_t Address, const void *Decoder) {
1281 // This operand encodes a mask of contiguous zeros between a specified MSB
1282 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1283 // the mask of all bits LSB-and-lower, and then xor them to create
1284 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1285 // create the final mask.
1286 unsigned msb = fieldFromInstruction(Val, 5, 5);
1287 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1289 DecodeStatus S = MCDisassembler::Success;
1291 Check(S, MCDisassembler::SoftFail);
1292 // The check above will cause the warning for the "potentially undefined
1293 // instruction encoding" but we can't build a bad MCOperand value here
1294 // with a lsb > msb or else printing the MCInst will cause a crash.
1298 uint32_t msb_mask = 0xFFFFFFFF;
1299 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1300 uint32_t lsb_mask = (1U << lsb) - 1;
1302 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1306 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1307 uint64_t Address, const void *Decoder) {
1308 DecodeStatus S = MCDisassembler::Success;
1310 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1311 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1312 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1313 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1314 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1315 unsigned U = fieldFromInstruction(Insn, 23, 1);
1317 switch (Inst.getOpcode()) {
1318 case ARM::LDC_OFFSET:
1321 case ARM::LDC_OPTION:
1322 case ARM::LDCL_OFFSET:
1324 case ARM::LDCL_POST:
1325 case ARM::LDCL_OPTION:
1326 case ARM::STC_OFFSET:
1329 case ARM::STC_OPTION:
1330 case ARM::STCL_OFFSET:
1332 case ARM::STCL_POST:
1333 case ARM::STCL_OPTION:
1334 case ARM::t2LDC_OFFSET:
1335 case ARM::t2LDC_PRE:
1336 case ARM::t2LDC_POST:
1337 case ARM::t2LDC_OPTION:
1338 case ARM::t2LDCL_OFFSET:
1339 case ARM::t2LDCL_PRE:
1340 case ARM::t2LDCL_POST:
1341 case ARM::t2LDCL_OPTION:
1342 case ARM::t2STC_OFFSET:
1343 case ARM::t2STC_PRE:
1344 case ARM::t2STC_POST:
1345 case ARM::t2STC_OPTION:
1346 case ARM::t2STCL_OFFSET:
1347 case ARM::t2STCL_PRE:
1348 case ARM::t2STCL_POST:
1349 case ARM::t2STCL_OPTION:
1350 if (coproc == 0xA || coproc == 0xB)
1351 return MCDisassembler::Fail;
1357 const FeatureBitset &featureBits =
1358 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
1359 if (featureBits[ARM::HasV8Ops] && (coproc != 14))
1360 return MCDisassembler::Fail;
1362 Inst.addOperand(MCOperand::createImm(coproc));
1363 Inst.addOperand(MCOperand::createImm(CRd));
1364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1365 return MCDisassembler::Fail;
1367 switch (Inst.getOpcode()) {
1368 case ARM::t2LDC2_OFFSET:
1369 case ARM::t2LDC2L_OFFSET:
1370 case ARM::t2LDC2_PRE:
1371 case ARM::t2LDC2L_PRE:
1372 case ARM::t2STC2_OFFSET:
1373 case ARM::t2STC2L_OFFSET:
1374 case ARM::t2STC2_PRE:
1375 case ARM::t2STC2L_PRE:
1376 case ARM::LDC2_OFFSET:
1377 case ARM::LDC2L_OFFSET:
1379 case ARM::LDC2L_PRE:
1380 case ARM::STC2_OFFSET:
1381 case ARM::STC2L_OFFSET:
1383 case ARM::STC2L_PRE:
1384 case ARM::t2LDC_OFFSET:
1385 case ARM::t2LDCL_OFFSET:
1386 case ARM::t2LDC_PRE:
1387 case ARM::t2LDCL_PRE:
1388 case ARM::t2STC_OFFSET:
1389 case ARM::t2STCL_OFFSET:
1390 case ARM::t2STC_PRE:
1391 case ARM::t2STCL_PRE:
1392 case ARM::LDC_OFFSET:
1393 case ARM::LDCL_OFFSET:
1396 case ARM::STC_OFFSET:
1397 case ARM::STCL_OFFSET:
1400 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1401 Inst.addOperand(MCOperand::createImm(imm));
1403 case ARM::t2LDC2_POST:
1404 case ARM::t2LDC2L_POST:
1405 case ARM::t2STC2_POST:
1406 case ARM::t2STC2L_POST:
1407 case ARM::LDC2_POST:
1408 case ARM::LDC2L_POST:
1409 case ARM::STC2_POST:
1410 case ARM::STC2L_POST:
1411 case ARM::t2LDC_POST:
1412 case ARM::t2LDCL_POST:
1413 case ARM::t2STC_POST:
1414 case ARM::t2STCL_POST:
1416 case ARM::LDCL_POST:
1418 case ARM::STCL_POST:
1422 // The 'option' variant doesn't encode 'U' in the immediate since
1423 // the immediate is unsigned [0,255].
1424 Inst.addOperand(MCOperand::createImm(imm));
1428 switch (Inst.getOpcode()) {
1429 case ARM::LDC_OFFSET:
1432 case ARM::LDC_OPTION:
1433 case ARM::LDCL_OFFSET:
1435 case ARM::LDCL_POST:
1436 case ARM::LDCL_OPTION:
1437 case ARM::STC_OFFSET:
1440 case ARM::STC_OPTION:
1441 case ARM::STCL_OFFSET:
1443 case ARM::STCL_POST:
1444 case ARM::STCL_OPTION:
1445 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1446 return MCDisassembler::Fail;
1456 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1457 uint64_t Address, const void *Decoder) {
1458 DecodeStatus S = MCDisassembler::Success;
1460 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1461 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1462 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1463 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1464 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1465 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1466 unsigned P = fieldFromInstruction(Insn, 24, 1);
1467 unsigned W = fieldFromInstruction(Insn, 21, 1);
1469 // On stores, the writeback operand precedes Rt.
1470 switch (Inst.getOpcode()) {
1471 case ARM::STR_POST_IMM:
1472 case ARM::STR_POST_REG:
1473 case ARM::STRB_POST_IMM:
1474 case ARM::STRB_POST_REG:
1475 case ARM::STRT_POST_REG:
1476 case ARM::STRT_POST_IMM:
1477 case ARM::STRBT_POST_REG:
1478 case ARM::STRBT_POST_IMM:
1479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1480 return MCDisassembler::Fail;
1486 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1487 return MCDisassembler::Fail;
1489 // On loads, the writeback operand comes after Rt.
1490 switch (Inst.getOpcode()) {
1491 case ARM::LDR_POST_IMM:
1492 case ARM::LDR_POST_REG:
1493 case ARM::LDRB_POST_IMM:
1494 case ARM::LDRB_POST_REG:
1495 case ARM::LDRBT_POST_REG:
1496 case ARM::LDRBT_POST_IMM:
1497 case ARM::LDRT_POST_REG:
1498 case ARM::LDRT_POST_IMM:
1499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1500 return MCDisassembler::Fail;
1506 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1507 return MCDisassembler::Fail;
1509 ARM_AM::AddrOpc Op = ARM_AM::add;
1510 if (!fieldFromInstruction(Insn, 23, 1))
1513 bool writeback = (P == 0) || (W == 1);
1514 unsigned idx_mode = 0;
1516 idx_mode = ARMII::IndexModePre;
1517 else if (!P && writeback)
1518 idx_mode = ARMII::IndexModePost;
1520 if (writeback && (Rn == 15 || Rn == Rt))
1521 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1524 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1525 return MCDisassembler::Fail;
1526 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1527 switch( fieldFromInstruction(Insn, 5, 2)) {
1541 return MCDisassembler::Fail;
1543 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1544 if (Opc == ARM_AM::ror && amt == 0)
1546 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1548 Inst.addOperand(MCOperand::createImm(imm));
1550 Inst.addOperand(MCOperand::createReg(0));
1551 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1552 Inst.addOperand(MCOperand::createImm(tmp));
1555 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1556 return MCDisassembler::Fail;
1561 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1562 uint64_t Address, const void *Decoder) {
1563 DecodeStatus S = MCDisassembler::Success;
1565 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1566 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1567 unsigned type = fieldFromInstruction(Val, 5, 2);
1568 unsigned imm = fieldFromInstruction(Val, 7, 5);
1569 unsigned U = fieldFromInstruction(Val, 12, 1);
1571 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1587 if (ShOp == ARM_AM::ror && imm == 0)
1590 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1591 return MCDisassembler::Fail;
1592 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1593 return MCDisassembler::Fail;
1596 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1598 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1599 Inst.addOperand(MCOperand::createImm(shift));
1605 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1606 uint64_t Address, const void *Decoder) {
1607 DecodeStatus S = MCDisassembler::Success;
1609 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1610 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1611 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1612 unsigned type = fieldFromInstruction(Insn, 22, 1);
1613 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1614 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1615 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1616 unsigned W = fieldFromInstruction(Insn, 21, 1);
1617 unsigned P = fieldFromInstruction(Insn, 24, 1);
1618 unsigned Rt2 = Rt + 1;
1620 bool writeback = (W == 1) | (P == 0);
1622 // For {LD,ST}RD, Rt must be even, else undefined.
1623 switch (Inst.getOpcode()) {
1626 case ARM::STRD_POST:
1629 case ARM::LDRD_POST:
1630 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1635 switch (Inst.getOpcode()) {
1638 case ARM::STRD_POST:
1639 if (P == 0 && W == 1)
1640 S = MCDisassembler::SoftFail;
1642 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1643 S = MCDisassembler::SoftFail;
1644 if (type && Rm == 15)
1645 S = MCDisassembler::SoftFail;
1647 S = MCDisassembler::SoftFail;
1648 if (!type && fieldFromInstruction(Insn, 8, 4))
1649 S = MCDisassembler::SoftFail;
1653 case ARM::STRH_POST:
1655 S = MCDisassembler::SoftFail;
1656 if (writeback && (Rn == 15 || Rn == Rt))
1657 S = MCDisassembler::SoftFail;
1658 if (!type && Rm == 15)
1659 S = MCDisassembler::SoftFail;
1663 case ARM::LDRD_POST:
1664 if (type && Rn == 15){
1666 S = MCDisassembler::SoftFail;
1669 if (P == 0 && W == 1)
1670 S = MCDisassembler::SoftFail;
1671 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1672 S = MCDisassembler::SoftFail;
1673 if (!type && writeback && Rn == 15)
1674 S = MCDisassembler::SoftFail;
1675 if (writeback && (Rn == Rt || Rn == Rt2))
1676 S = MCDisassembler::SoftFail;
1680 case ARM::LDRH_POST:
1681 if (type && Rn == 15){
1683 S = MCDisassembler::SoftFail;
1687 S = MCDisassembler::SoftFail;
1688 if (!type && Rm == 15)
1689 S = MCDisassembler::SoftFail;
1690 if (!type && writeback && (Rn == 15 || Rn == Rt))
1691 S = MCDisassembler::SoftFail;
1694 case ARM::LDRSH_PRE:
1695 case ARM::LDRSH_POST:
1697 case ARM::LDRSB_PRE:
1698 case ARM::LDRSB_POST:
1699 if (type && Rn == 15){
1701 S = MCDisassembler::SoftFail;
1704 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1705 S = MCDisassembler::SoftFail;
1706 if (!type && (Rt == 15 || Rm == 15))
1707 S = MCDisassembler::SoftFail;
1708 if (!type && writeback && (Rn == 15 || Rn == Rt))
1709 S = MCDisassembler::SoftFail;
1715 if (writeback) { // Writeback
1717 U |= ARMII::IndexModePre << 9;
1719 U |= ARMII::IndexModePost << 9;
1721 // On stores, the writeback operand precedes Rt.
1722 switch (Inst.getOpcode()) {
1725 case ARM::STRD_POST:
1728 case ARM::STRH_POST:
1729 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1730 return MCDisassembler::Fail;
1737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1738 return MCDisassembler::Fail;
1739 switch (Inst.getOpcode()) {
1742 case ARM::STRD_POST:
1745 case ARM::LDRD_POST:
1746 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1747 return MCDisassembler::Fail;
1754 // On loads, the writeback operand comes after Rt.
1755 switch (Inst.getOpcode()) {
1758 case ARM::LDRD_POST:
1761 case ARM::LDRH_POST:
1763 case ARM::LDRSH_PRE:
1764 case ARM::LDRSH_POST:
1766 case ARM::LDRSB_PRE:
1767 case ARM::LDRSB_POST:
1770 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1771 return MCDisassembler::Fail;
1778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1779 return MCDisassembler::Fail;
1782 Inst.addOperand(MCOperand::createReg(0));
1783 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1786 return MCDisassembler::Fail;
1787 Inst.addOperand(MCOperand::createImm(U));
1790 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1791 return MCDisassembler::Fail;
1796 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1797 uint64_t Address, const void *Decoder) {
1798 DecodeStatus S = MCDisassembler::Success;
1800 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1801 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1818 Inst.addOperand(MCOperand::createImm(mode));
1819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1820 return MCDisassembler::Fail;
1825 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1826 uint64_t Address, const void *Decoder) {
1827 DecodeStatus S = MCDisassembler::Success;
1829 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1830 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1831 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1832 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1835 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1837 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1838 return MCDisassembler::Fail;
1839 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1840 return MCDisassembler::Fail;
1841 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1842 return MCDisassembler::Fail;
1843 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1844 return MCDisassembler::Fail;
1848 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1850 uint64_t Address, const void *Decoder) {
1851 DecodeStatus S = MCDisassembler::Success;
1853 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1854 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1855 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1858 // Ambiguous with RFE and SRS
1859 switch (Inst.getOpcode()) {
1861 Inst.setOpcode(ARM::RFEDA);
1863 case ARM::LDMDA_UPD:
1864 Inst.setOpcode(ARM::RFEDA_UPD);
1867 Inst.setOpcode(ARM::RFEDB);
1869 case ARM::LDMDB_UPD:
1870 Inst.setOpcode(ARM::RFEDB_UPD);
1873 Inst.setOpcode(ARM::RFEIA);
1875 case ARM::LDMIA_UPD:
1876 Inst.setOpcode(ARM::RFEIA_UPD);
1879 Inst.setOpcode(ARM::RFEIB);
1881 case ARM::LDMIB_UPD:
1882 Inst.setOpcode(ARM::RFEIB_UPD);
1885 Inst.setOpcode(ARM::SRSDA);
1887 case ARM::STMDA_UPD:
1888 Inst.setOpcode(ARM::SRSDA_UPD);
1891 Inst.setOpcode(ARM::SRSDB);
1893 case ARM::STMDB_UPD:
1894 Inst.setOpcode(ARM::SRSDB_UPD);
1897 Inst.setOpcode(ARM::SRSIA);
1899 case ARM::STMIA_UPD:
1900 Inst.setOpcode(ARM::SRSIA_UPD);
1903 Inst.setOpcode(ARM::SRSIB);
1905 case ARM::STMIB_UPD:
1906 Inst.setOpcode(ARM::SRSIB_UPD);
1909 return MCDisassembler::Fail;
1912 // For stores (which become SRS's, the only operand is the mode.
1913 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1914 // Check SRS encoding constraints
1915 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1916 fieldFromInstruction(Insn, 20, 1) == 0))
1917 return MCDisassembler::Fail;
1920 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
1924 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1927 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1928 return MCDisassembler::Fail;
1929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1930 return MCDisassembler::Fail; // Tied
1931 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1932 return MCDisassembler::Fail;
1933 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1934 return MCDisassembler::Fail;
1939 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1940 uint64_t Address, const void *Decoder) {
1941 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1942 unsigned M = fieldFromInstruction(Insn, 17, 1);
1943 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1944 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1946 DecodeStatus S = MCDisassembler::Success;
1948 // This decoder is called from multiple location that do not check
1949 // the full encoding is valid before they do.
1950 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1951 fieldFromInstruction(Insn, 16, 1) != 0 ||
1952 fieldFromInstruction(Insn, 20, 8) != 0x10)
1953 return MCDisassembler::Fail;
1955 // imod == '01' --> UNPREDICTABLE
1956 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1957 // return failure here. The '01' imod value is unprintable, so there's
1958 // nothing useful we could do even if we returned UNPREDICTABLE.
1960 if (imod == 1) return MCDisassembler::Fail;
1963 Inst.setOpcode(ARM::CPS3p);
1964 Inst.addOperand(MCOperand::createImm(imod));
1965 Inst.addOperand(MCOperand::createImm(iflags));
1966 Inst.addOperand(MCOperand::createImm(mode));
1967 } else if (imod && !M) {
1968 Inst.setOpcode(ARM::CPS2p);
1969 Inst.addOperand(MCOperand::createImm(imod));
1970 Inst.addOperand(MCOperand::createImm(iflags));
1971 if (mode) S = MCDisassembler::SoftFail;
1972 } else if (!imod && M) {
1973 Inst.setOpcode(ARM::CPS1p);
1974 Inst.addOperand(MCOperand::createImm(mode));
1975 if (iflags) S = MCDisassembler::SoftFail;
1977 // imod == '00' && M == '0' --> UNPREDICTABLE
1978 Inst.setOpcode(ARM::CPS1p);
1979 Inst.addOperand(MCOperand::createImm(mode));
1980 S = MCDisassembler::SoftFail;
1986 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1987 uint64_t Address, const void *Decoder) {
1988 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1989 unsigned M = fieldFromInstruction(Insn, 8, 1);
1990 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1991 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1993 DecodeStatus S = MCDisassembler::Success;
1995 // imod == '01' --> UNPREDICTABLE
1996 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1997 // return failure here. The '01' imod value is unprintable, so there's
1998 // nothing useful we could do even if we returned UNPREDICTABLE.
2000 if (imod == 1) return MCDisassembler::Fail;
2003 Inst.setOpcode(ARM::t2CPS3p);
2004 Inst.addOperand(MCOperand::createImm(imod));
2005 Inst.addOperand(MCOperand::createImm(iflags));
2006 Inst.addOperand(MCOperand::createImm(mode));
2007 } else if (imod && !M) {
2008 Inst.setOpcode(ARM::t2CPS2p);
2009 Inst.addOperand(MCOperand::createImm(imod));
2010 Inst.addOperand(MCOperand::createImm(iflags));
2011 if (mode) S = MCDisassembler::SoftFail;
2012 } else if (!imod && M) {
2013 Inst.setOpcode(ARM::t2CPS1p);
2014 Inst.addOperand(MCOperand::createImm(mode));
2015 if (iflags) S = MCDisassembler::SoftFail;
2017 // imod == '00' && M == '0' --> this is a HINT instruction
2018 int imm = fieldFromInstruction(Insn, 0, 8);
2019 // HINT are defined only for immediate in [0..4]
2020 if(imm > 4) return MCDisassembler::Fail;
2021 Inst.setOpcode(ARM::t2HINT);
2022 Inst.addOperand(MCOperand::createImm(imm));
2028 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2029 uint64_t Address, const void *Decoder) {
2030 DecodeStatus S = MCDisassembler::Success;
2032 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2035 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2036 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2037 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2038 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2040 if (Inst.getOpcode() == ARM::t2MOVTi16)
2041 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2042 return MCDisassembler::Fail;
2043 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2044 return MCDisassembler::Fail;
2046 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2047 Inst.addOperand(MCOperand::createImm(imm));
2052 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2053 uint64_t Address, const void *Decoder) {
2054 DecodeStatus S = MCDisassembler::Success;
2056 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2057 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2060 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2061 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2063 if (Inst.getOpcode() == ARM::MOVTi16)
2064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2065 return MCDisassembler::Fail;
2067 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2068 return MCDisassembler::Fail;
2070 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2071 Inst.addOperand(MCOperand::createImm(imm));
2073 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2074 return MCDisassembler::Fail;
2079 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2080 uint64_t Address, const void *Decoder) {
2081 DecodeStatus S = MCDisassembler::Success;
2083 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2084 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2085 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2086 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2087 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2090 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2092 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2093 return MCDisassembler::Fail;
2094 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2095 return MCDisassembler::Fail;
2096 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2097 return MCDisassembler::Fail;
2098 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2099 return MCDisassembler::Fail;
2101 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2102 return MCDisassembler::Fail;
2107 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2108 uint64_t Address, const void *Decoder) {
2109 DecodeStatus S = MCDisassembler::Success;
2111 unsigned Pred = fieldFromInstruction(Insn, 28, 4);
2112 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2113 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2116 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2118 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2119 return MCDisassembler::Fail;
2120 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2121 return MCDisassembler::Fail;
2122 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2123 return MCDisassembler::Fail;
2128 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2129 uint64_t Address, const void *Decoder) {
2130 DecodeStatus S = MCDisassembler::Success;
2132 unsigned Imm = fieldFromInstruction(Insn, 9, 1);
2134 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
2135 const FeatureBitset &FeatureBits = Dis->getSubtargetInfo().getFeatureBits();
2137 if (!FeatureBits[ARM::HasV8_1aOps] ||
2138 !FeatureBits[ARM::HasV8Ops])
2139 return MCDisassembler::Fail;
2141 // Decoder can be called from DecodeTST, which does not check the full
2142 // encoding is valid.
2143 if (fieldFromInstruction(Insn, 20,12) != 0xf11 ||
2144 fieldFromInstruction(Insn, 4,4) != 0)
2145 return MCDisassembler::Fail;
2146 if (fieldFromInstruction(Insn, 10,10) != 0 ||
2147 fieldFromInstruction(Insn, 0,4) != 0)
2148 S = MCDisassembler::SoftFail;
2150 Inst.setOpcode(ARM::SETPAN);
2151 Inst.addOperand(MCOperand::createImm(Imm));
2156 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2157 uint64_t Address, const void *Decoder) {
2158 DecodeStatus S = MCDisassembler::Success;
2160 unsigned add = fieldFromInstruction(Val, 12, 1);
2161 unsigned imm = fieldFromInstruction(Val, 0, 12);
2162 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2164 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2165 return MCDisassembler::Fail;
2167 if (!add) imm *= -1;
2168 if (imm == 0 && !add) imm = INT32_MIN;
2169 Inst.addOperand(MCOperand::createImm(imm));
2171 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2176 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2177 uint64_t Address, const void *Decoder) {
2178 DecodeStatus S = MCDisassembler::Success;
2180 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2181 unsigned U = fieldFromInstruction(Val, 8, 1);
2182 unsigned imm = fieldFromInstruction(Val, 0, 8);
2184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2185 return MCDisassembler::Fail;
2188 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2190 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2195 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2196 uint64_t Address, const void *Decoder) {
2197 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2201 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2202 uint64_t Address, const void *Decoder) {
2203 DecodeStatus Status = MCDisassembler::Success;
2205 // Note the J1 and J2 values are from the encoded instruction. So here
2206 // change them to I1 and I2 values via as documented:
2207 // I1 = NOT(J1 EOR S);
2208 // I2 = NOT(J2 EOR S);
2209 // and build the imm32 with one trailing zero as documented:
2210 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2211 unsigned S = fieldFromInstruction(Insn, 26, 1);
2212 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2213 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2214 unsigned I1 = !(J1 ^ S);
2215 unsigned I2 = !(J2 ^ S);
2216 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2217 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2218 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2219 int imm32 = SignExtend32<25>(tmp << 1);
2220 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2221 true, 4, Inst, Decoder))
2222 Inst.addOperand(MCOperand::createImm(imm32));
2228 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2229 uint64_t Address, const void *Decoder) {
2230 DecodeStatus S = MCDisassembler::Success;
2232 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2233 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2236 Inst.setOpcode(ARM::BLXi);
2237 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2238 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2239 true, 4, Inst, Decoder))
2240 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2244 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2245 true, 4, Inst, Decoder))
2246 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2247 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2248 return MCDisassembler::Fail;
2254 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2255 uint64_t Address, const void *Decoder) {
2256 DecodeStatus S = MCDisassembler::Success;
2258 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2259 unsigned align = fieldFromInstruction(Val, 4, 2);
2261 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2262 return MCDisassembler::Fail;
2264 Inst.addOperand(MCOperand::createImm(0));
2266 Inst.addOperand(MCOperand::createImm(4 << align));
2271 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2272 uint64_t Address, const void *Decoder) {
2273 DecodeStatus S = MCDisassembler::Success;
2275 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2276 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2277 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2278 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2279 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2280 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2282 // First output register
2283 switch (Inst.getOpcode()) {
2284 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2285 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2286 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2287 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2288 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2289 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2290 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2291 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2292 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2293 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2294 return MCDisassembler::Fail;
2299 case ARM::VLD2b16wb_fixed:
2300 case ARM::VLD2b16wb_register:
2301 case ARM::VLD2b32wb_fixed:
2302 case ARM::VLD2b32wb_register:
2303 case ARM::VLD2b8wb_fixed:
2304 case ARM::VLD2b8wb_register:
2305 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2306 return MCDisassembler::Fail;
2309 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2310 return MCDisassembler::Fail;
2313 // Second output register
2314 switch (Inst.getOpcode()) {
2318 case ARM::VLD3d8_UPD:
2319 case ARM::VLD3d16_UPD:
2320 case ARM::VLD3d32_UPD:
2324 case ARM::VLD4d8_UPD:
2325 case ARM::VLD4d16_UPD:
2326 case ARM::VLD4d32_UPD:
2327 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2328 return MCDisassembler::Fail;
2333 case ARM::VLD3q8_UPD:
2334 case ARM::VLD3q16_UPD:
2335 case ARM::VLD3q32_UPD:
2339 case ARM::VLD4q8_UPD:
2340 case ARM::VLD4q16_UPD:
2341 case ARM::VLD4q32_UPD:
2342 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2343 return MCDisassembler::Fail;
2348 // Third output register
2349 switch(Inst.getOpcode()) {
2353 case ARM::VLD3d8_UPD:
2354 case ARM::VLD3d16_UPD:
2355 case ARM::VLD3d32_UPD:
2359 case ARM::VLD4d8_UPD:
2360 case ARM::VLD4d16_UPD:
2361 case ARM::VLD4d32_UPD:
2362 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2363 return MCDisassembler::Fail;
2368 case ARM::VLD3q8_UPD:
2369 case ARM::VLD3q16_UPD:
2370 case ARM::VLD3q32_UPD:
2374 case ARM::VLD4q8_UPD:
2375 case ARM::VLD4q16_UPD:
2376 case ARM::VLD4q32_UPD:
2377 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2378 return MCDisassembler::Fail;
2384 // Fourth output register
2385 switch (Inst.getOpcode()) {
2389 case ARM::VLD4d8_UPD:
2390 case ARM::VLD4d16_UPD:
2391 case ARM::VLD4d32_UPD:
2392 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2393 return MCDisassembler::Fail;
2398 case ARM::VLD4q8_UPD:
2399 case ARM::VLD4q16_UPD:
2400 case ARM::VLD4q32_UPD:
2401 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2402 return MCDisassembler::Fail;
2408 // Writeback operand
2409 switch (Inst.getOpcode()) {
2410 case ARM::VLD1d8wb_fixed:
2411 case ARM::VLD1d16wb_fixed:
2412 case ARM::VLD1d32wb_fixed:
2413 case ARM::VLD1d64wb_fixed:
2414 case ARM::VLD1d8wb_register:
2415 case ARM::VLD1d16wb_register:
2416 case ARM::VLD1d32wb_register:
2417 case ARM::VLD1d64wb_register:
2418 case ARM::VLD1q8wb_fixed:
2419 case ARM::VLD1q16wb_fixed:
2420 case ARM::VLD1q32wb_fixed:
2421 case ARM::VLD1q64wb_fixed:
2422 case ARM::VLD1q8wb_register:
2423 case ARM::VLD1q16wb_register:
2424 case ARM::VLD1q32wb_register:
2425 case ARM::VLD1q64wb_register:
2426 case ARM::VLD1d8Twb_fixed:
2427 case ARM::VLD1d8Twb_register:
2428 case ARM::VLD1d16Twb_fixed:
2429 case ARM::VLD1d16Twb_register:
2430 case ARM::VLD1d32Twb_fixed:
2431 case ARM::VLD1d32Twb_register:
2432 case ARM::VLD1d64Twb_fixed:
2433 case ARM::VLD1d64Twb_register:
2434 case ARM::VLD1d8Qwb_fixed:
2435 case ARM::VLD1d8Qwb_register:
2436 case ARM::VLD1d16Qwb_fixed:
2437 case ARM::VLD1d16Qwb_register:
2438 case ARM::VLD1d32Qwb_fixed:
2439 case ARM::VLD1d32Qwb_register:
2440 case ARM::VLD1d64Qwb_fixed:
2441 case ARM::VLD1d64Qwb_register:
2442 case ARM::VLD2d8wb_fixed:
2443 case ARM::VLD2d16wb_fixed:
2444 case ARM::VLD2d32wb_fixed:
2445 case ARM::VLD2q8wb_fixed:
2446 case ARM::VLD2q16wb_fixed:
2447 case ARM::VLD2q32wb_fixed:
2448 case ARM::VLD2d8wb_register:
2449 case ARM::VLD2d16wb_register:
2450 case ARM::VLD2d32wb_register:
2451 case ARM::VLD2q8wb_register:
2452 case ARM::VLD2q16wb_register:
2453 case ARM::VLD2q32wb_register:
2454 case ARM::VLD2b8wb_fixed:
2455 case ARM::VLD2b16wb_fixed:
2456 case ARM::VLD2b32wb_fixed:
2457 case ARM::VLD2b8wb_register:
2458 case ARM::VLD2b16wb_register:
2459 case ARM::VLD2b32wb_register:
2460 Inst.addOperand(MCOperand::createImm(0));
2462 case ARM::VLD3d8_UPD:
2463 case ARM::VLD3d16_UPD:
2464 case ARM::VLD3d32_UPD:
2465 case ARM::VLD3q8_UPD:
2466 case ARM::VLD3q16_UPD:
2467 case ARM::VLD3q32_UPD:
2468 case ARM::VLD4d8_UPD:
2469 case ARM::VLD4d16_UPD:
2470 case ARM::VLD4d32_UPD:
2471 case ARM::VLD4q8_UPD:
2472 case ARM::VLD4q16_UPD:
2473 case ARM::VLD4q32_UPD:
2474 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2475 return MCDisassembler::Fail;
2481 // AddrMode6 Base (register+alignment)
2482 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2483 return MCDisassembler::Fail;
2485 // AddrMode6 Offset (register)
2486 switch (Inst.getOpcode()) {
2488 // The below have been updated to have explicit am6offset split
2489 // between fixed and register offset. For those instructions not
2490 // yet updated, we need to add an additional reg0 operand for the
2493 // The fixed offset encodes as Rm == 0xd, so we check for that.
2495 Inst.addOperand(MCOperand::createReg(0));
2498 // Fall through to handle the register offset variant.
2499 case ARM::VLD1d8wb_fixed:
2500 case ARM::VLD1d16wb_fixed:
2501 case ARM::VLD1d32wb_fixed:
2502 case ARM::VLD1d64wb_fixed:
2503 case ARM::VLD1d8Twb_fixed:
2504 case ARM::VLD1d16Twb_fixed:
2505 case ARM::VLD1d32Twb_fixed:
2506 case ARM::VLD1d64Twb_fixed:
2507 case ARM::VLD1d8Qwb_fixed:
2508 case ARM::VLD1d16Qwb_fixed:
2509 case ARM::VLD1d32Qwb_fixed:
2510 case ARM::VLD1d64Qwb_fixed:
2511 case ARM::VLD1d8wb_register:
2512 case ARM::VLD1d16wb_register:
2513 case ARM::VLD1d32wb_register:
2514 case ARM::VLD1d64wb_register:
2515 case ARM::VLD1q8wb_fixed:
2516 case ARM::VLD1q16wb_fixed:
2517 case ARM::VLD1q32wb_fixed:
2518 case ARM::VLD1q64wb_fixed:
2519 case ARM::VLD1q8wb_register:
2520 case ARM::VLD1q16wb_register:
2521 case ARM::VLD1q32wb_register:
2522 case ARM::VLD1q64wb_register:
2523 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2524 // variant encodes Rm == 0xf. Anything else is a register offset post-
2525 // increment and we need to add the register operand to the instruction.
2526 if (Rm != 0xD && Rm != 0xF &&
2527 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2528 return MCDisassembler::Fail;
2530 case ARM::VLD2d8wb_fixed:
2531 case ARM::VLD2d16wb_fixed:
2532 case ARM::VLD2d32wb_fixed:
2533 case ARM::VLD2b8wb_fixed:
2534 case ARM::VLD2b16wb_fixed:
2535 case ARM::VLD2b32wb_fixed:
2536 case ARM::VLD2q8wb_fixed:
2537 case ARM::VLD2q16wb_fixed:
2538 case ARM::VLD2q32wb_fixed:
2545 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2546 uint64_t Address, const void *Decoder) {
2547 unsigned type = fieldFromInstruction(Insn, 8, 4);
2548 unsigned align = fieldFromInstruction(Insn, 4, 2);
2549 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2550 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2551 if (type == 10 && align == 3) return MCDisassembler::Fail;
2553 unsigned load = fieldFromInstruction(Insn, 21, 1);
2554 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2555 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2558 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2559 uint64_t Address, const void *Decoder) {
2560 unsigned size = fieldFromInstruction(Insn, 6, 2);
2561 if (size == 3) return MCDisassembler::Fail;
2563 unsigned type = fieldFromInstruction(Insn, 8, 4);
2564 unsigned align = fieldFromInstruction(Insn, 4, 2);
2565 if (type == 8 && align == 3) return MCDisassembler::Fail;
2566 if (type == 9 && align == 3) return MCDisassembler::Fail;
2568 unsigned load = fieldFromInstruction(Insn, 21, 1);
2569 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2570 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2573 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2574 uint64_t Address, const void *Decoder) {
2575 unsigned size = fieldFromInstruction(Insn, 6, 2);
2576 if (size == 3) return MCDisassembler::Fail;
2578 unsigned align = fieldFromInstruction(Insn, 4, 2);
2579 if (align & 2) return MCDisassembler::Fail;
2581 unsigned load = fieldFromInstruction(Insn, 21, 1);
2582 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2583 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2586 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2587 uint64_t Address, const void *Decoder) {
2588 unsigned size = fieldFromInstruction(Insn, 6, 2);
2589 if (size == 3) return MCDisassembler::Fail;
2591 unsigned load = fieldFromInstruction(Insn, 21, 1);
2592 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2593 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2596 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2597 uint64_t Address, const void *Decoder) {
2598 DecodeStatus S = MCDisassembler::Success;
2600 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2601 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2602 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2603 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2604 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2605 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2607 // Writeback Operand
2608 switch (Inst.getOpcode()) {
2609 case ARM::VST1d8wb_fixed:
2610 case ARM::VST1d16wb_fixed:
2611 case ARM::VST1d32wb_fixed:
2612 case ARM::VST1d64wb_fixed:
2613 case ARM::VST1d8wb_register:
2614 case ARM::VST1d16wb_register:
2615 case ARM::VST1d32wb_register:
2616 case ARM::VST1d64wb_register:
2617 case ARM::VST1q8wb_fixed:
2618 case ARM::VST1q16wb_fixed:
2619 case ARM::VST1q32wb_fixed:
2620 case ARM::VST1q64wb_fixed:
2621 case ARM::VST1q8wb_register:
2622 case ARM::VST1q16wb_register:
2623 case ARM::VST1q32wb_register:
2624 case ARM::VST1q64wb_register:
2625 case ARM::VST1d8Twb_fixed:
2626 case ARM::VST1d16Twb_fixed:
2627 case ARM::VST1d32Twb_fixed:
2628 case ARM::VST1d64Twb_fixed:
2629 case ARM::VST1d8Twb_register:
2630 case ARM::VST1d16Twb_register:
2631 case ARM::VST1d32Twb_register:
2632 case ARM::VST1d64Twb_register:
2633 case ARM::VST1d8Qwb_fixed:
2634 case ARM::VST1d16Qwb_fixed:
2635 case ARM::VST1d32Qwb_fixed:
2636 case ARM::VST1d64Qwb_fixed:
2637 case ARM::VST1d8Qwb_register:
2638 case ARM::VST1d16Qwb_register:
2639 case ARM::VST1d32Qwb_register:
2640 case ARM::VST1d64Qwb_register:
2641 case ARM::VST2d8wb_fixed:
2642 case ARM::VST2d16wb_fixed:
2643 case ARM::VST2d32wb_fixed:
2644 case ARM::VST2d8wb_register:
2645 case ARM::VST2d16wb_register:
2646 case ARM::VST2d32wb_register:
2647 case ARM::VST2q8wb_fixed:
2648 case ARM::VST2q16wb_fixed:
2649 case ARM::VST2q32wb_fixed:
2650 case ARM::VST2q8wb_register:
2651 case ARM::VST2q16wb_register:
2652 case ARM::VST2q32wb_register:
2653 case ARM::VST2b8wb_fixed:
2654 case ARM::VST2b16wb_fixed:
2655 case ARM::VST2b32wb_fixed:
2656 case ARM::VST2b8wb_register:
2657 case ARM::VST2b16wb_register:
2658 case ARM::VST2b32wb_register:
2660 return MCDisassembler::Fail;
2661 Inst.addOperand(MCOperand::createImm(0));
2663 case ARM::VST3d8_UPD:
2664 case ARM::VST3d16_UPD:
2665 case ARM::VST3d32_UPD:
2666 case ARM::VST3q8_UPD:
2667 case ARM::VST3q16_UPD:
2668 case ARM::VST3q32_UPD:
2669 case ARM::VST4d8_UPD:
2670 case ARM::VST4d16_UPD:
2671 case ARM::VST4d32_UPD:
2672 case ARM::VST4q8_UPD:
2673 case ARM::VST4q16_UPD:
2674 case ARM::VST4q32_UPD:
2675 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2676 return MCDisassembler::Fail;
2682 // AddrMode6 Base (register+alignment)
2683 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2684 return MCDisassembler::Fail;
2686 // AddrMode6 Offset (register)
2687 switch (Inst.getOpcode()) {
2690 Inst.addOperand(MCOperand::createReg(0));
2691 else if (Rm != 0xF) {
2692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2693 return MCDisassembler::Fail;
2696 case ARM::VST1d8wb_fixed:
2697 case ARM::VST1d16wb_fixed:
2698 case ARM::VST1d32wb_fixed:
2699 case ARM::VST1d64wb_fixed:
2700 case ARM::VST1q8wb_fixed:
2701 case ARM::VST1q16wb_fixed:
2702 case ARM::VST1q32wb_fixed:
2703 case ARM::VST1q64wb_fixed:
2704 case ARM::VST1d8Twb_fixed:
2705 case ARM::VST1d16Twb_fixed:
2706 case ARM::VST1d32Twb_fixed:
2707 case ARM::VST1d64Twb_fixed:
2708 case ARM::VST1d8Qwb_fixed:
2709 case ARM::VST1d16Qwb_fixed:
2710 case ARM::VST1d32Qwb_fixed:
2711 case ARM::VST1d64Qwb_fixed:
2712 case ARM::VST2d8wb_fixed:
2713 case ARM::VST2d16wb_fixed:
2714 case ARM::VST2d32wb_fixed:
2715 case ARM::VST2q8wb_fixed:
2716 case ARM::VST2q16wb_fixed:
2717 case ARM::VST2q32wb_fixed:
2718 case ARM::VST2b8wb_fixed:
2719 case ARM::VST2b16wb_fixed:
2720 case ARM::VST2b32wb_fixed:
2725 // First input register
2726 switch (Inst.getOpcode()) {
2731 case ARM::VST1q16wb_fixed:
2732 case ARM::VST1q16wb_register:
2733 case ARM::VST1q32wb_fixed:
2734 case ARM::VST1q32wb_register:
2735 case ARM::VST1q64wb_fixed:
2736 case ARM::VST1q64wb_register:
2737 case ARM::VST1q8wb_fixed:
2738 case ARM::VST1q8wb_register:
2742 case ARM::VST2d16wb_fixed:
2743 case ARM::VST2d16wb_register:
2744 case ARM::VST2d32wb_fixed:
2745 case ARM::VST2d32wb_register:
2746 case ARM::VST2d8wb_fixed:
2747 case ARM::VST2d8wb_register:
2748 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2749 return MCDisassembler::Fail;
2754 case ARM::VST2b16wb_fixed:
2755 case ARM::VST2b16wb_register:
2756 case ARM::VST2b32wb_fixed:
2757 case ARM::VST2b32wb_register:
2758 case ARM::VST2b8wb_fixed:
2759 case ARM::VST2b8wb_register:
2760 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2761 return MCDisassembler::Fail;
2764 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2765 return MCDisassembler::Fail;
2768 // Second input register
2769 switch (Inst.getOpcode()) {
2773 case ARM::VST3d8_UPD:
2774 case ARM::VST3d16_UPD:
2775 case ARM::VST3d32_UPD:
2779 case ARM::VST4d8_UPD:
2780 case ARM::VST4d16_UPD:
2781 case ARM::VST4d32_UPD:
2782 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2783 return MCDisassembler::Fail;
2788 case ARM::VST3q8_UPD:
2789 case ARM::VST3q16_UPD:
2790 case ARM::VST3q32_UPD:
2794 case ARM::VST4q8_UPD:
2795 case ARM::VST4q16_UPD:
2796 case ARM::VST4q32_UPD:
2797 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2798 return MCDisassembler::Fail;
2804 // Third input register
2805 switch (Inst.getOpcode()) {
2809 case ARM::VST3d8_UPD:
2810 case ARM::VST3d16_UPD:
2811 case ARM::VST3d32_UPD:
2815 case ARM::VST4d8_UPD:
2816 case ARM::VST4d16_UPD:
2817 case ARM::VST4d32_UPD:
2818 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2819 return MCDisassembler::Fail;
2824 case ARM::VST3q8_UPD:
2825 case ARM::VST3q16_UPD:
2826 case ARM::VST3q32_UPD:
2830 case ARM::VST4q8_UPD:
2831 case ARM::VST4q16_UPD:
2832 case ARM::VST4q32_UPD:
2833 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2834 return MCDisassembler::Fail;
2840 // Fourth input register
2841 switch (Inst.getOpcode()) {
2845 case ARM::VST4d8_UPD:
2846 case ARM::VST4d16_UPD:
2847 case ARM::VST4d32_UPD:
2848 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2849 return MCDisassembler::Fail;
2854 case ARM::VST4q8_UPD:
2855 case ARM::VST4q16_UPD:
2856 case ARM::VST4q32_UPD:
2857 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2858 return MCDisassembler::Fail;
2867 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2868 uint64_t Address, const void *Decoder) {
2869 DecodeStatus S = MCDisassembler::Success;
2871 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2872 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2873 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2874 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2875 unsigned align = fieldFromInstruction(Insn, 4, 1);
2876 unsigned size = fieldFromInstruction(Insn, 6, 2);
2878 if (size == 0 && align == 1)
2879 return MCDisassembler::Fail;
2880 align *= (1 << size);
2882 switch (Inst.getOpcode()) {
2883 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2884 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2885 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2886 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2887 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2888 return MCDisassembler::Fail;
2891 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2892 return MCDisassembler::Fail;
2896 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2897 return MCDisassembler::Fail;
2900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2901 return MCDisassembler::Fail;
2902 Inst.addOperand(MCOperand::createImm(align));
2904 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2905 // variant encodes Rm == 0xf. Anything else is a register offset post-
2906 // increment and we need to add the register operand to the instruction.
2907 if (Rm != 0xD && Rm != 0xF &&
2908 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2909 return MCDisassembler::Fail;
2914 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2915 uint64_t Address, const void *Decoder) {
2916 DecodeStatus S = MCDisassembler::Success;
2918 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2919 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2920 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2921 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2922 unsigned align = fieldFromInstruction(Insn, 4, 1);
2923 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2926 switch (Inst.getOpcode()) {
2927 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2928 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2929 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2930 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2931 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2932 return MCDisassembler::Fail;
2934 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2935 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2936 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2937 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2938 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2939 return MCDisassembler::Fail;
2942 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2943 return MCDisassembler::Fail;
2948 Inst.addOperand(MCOperand::createImm(0));
2950 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2951 return MCDisassembler::Fail;
2952 Inst.addOperand(MCOperand::createImm(align));
2954 if (Rm != 0xD && Rm != 0xF) {
2955 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2956 return MCDisassembler::Fail;
2962 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2963 uint64_t Address, const void *Decoder) {
2964 DecodeStatus S = MCDisassembler::Success;
2966 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2967 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2968 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2969 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2970 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2972 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2973 return MCDisassembler::Fail;
2974 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2975 return MCDisassembler::Fail;
2976 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2977 return MCDisassembler::Fail;
2979 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2980 return MCDisassembler::Fail;
2983 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2984 return MCDisassembler::Fail;
2985 Inst.addOperand(MCOperand::createImm(0));
2988 Inst.addOperand(MCOperand::createReg(0));
2989 else if (Rm != 0xF) {
2990 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2991 return MCDisassembler::Fail;
2997 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2998 uint64_t Address, const void *Decoder) {
2999 DecodeStatus S = MCDisassembler::Success;
3001 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3002 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3003 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3004 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3005 unsigned size = fieldFromInstruction(Insn, 6, 2);
3006 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
3007 unsigned align = fieldFromInstruction(Insn, 4, 1);
3011 return MCDisassembler::Fail;
3022 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3023 return MCDisassembler::Fail;
3024 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3025 return MCDisassembler::Fail;
3026 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3027 return MCDisassembler::Fail;
3028 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3029 return MCDisassembler::Fail;
3031 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3032 return MCDisassembler::Fail;
3035 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3036 return MCDisassembler::Fail;
3037 Inst.addOperand(MCOperand::createImm(align));
3040 Inst.addOperand(MCOperand::createReg(0));
3041 else if (Rm != 0xF) {
3042 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3043 return MCDisassembler::Fail;
3050 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3051 uint64_t Address, const void *Decoder) {
3052 DecodeStatus S = MCDisassembler::Success;
3054 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3055 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3056 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3057 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3058 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3059 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3060 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3061 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3064 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3065 return MCDisassembler::Fail;
3067 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3068 return MCDisassembler::Fail;
3071 Inst.addOperand(MCOperand::createImm(imm));
3073 switch (Inst.getOpcode()) {
3074 case ARM::VORRiv4i16:
3075 case ARM::VORRiv2i32:
3076 case ARM::VBICiv4i16:
3077 case ARM::VBICiv2i32:
3078 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3079 return MCDisassembler::Fail;
3081 case ARM::VORRiv8i16:
3082 case ARM::VORRiv4i32:
3083 case ARM::VBICiv8i16:
3084 case ARM::VBICiv4i32:
3085 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3086 return MCDisassembler::Fail;
3095 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3096 uint64_t Address, const void *Decoder) {
3097 DecodeStatus S = MCDisassembler::Success;
3099 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3100 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3101 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3102 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3103 unsigned size = fieldFromInstruction(Insn, 18, 2);
3105 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3106 return MCDisassembler::Fail;
3107 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3108 return MCDisassembler::Fail;
3109 Inst.addOperand(MCOperand::createImm(8 << size));
3114 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3115 uint64_t Address, const void *Decoder) {
3116 Inst.addOperand(MCOperand::createImm(8 - Val));
3117 return MCDisassembler::Success;
3120 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3121 uint64_t Address, const void *Decoder) {
3122 Inst.addOperand(MCOperand::createImm(16 - Val));
3123 return MCDisassembler::Success;
3126 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3127 uint64_t Address, const void *Decoder) {
3128 Inst.addOperand(MCOperand::createImm(32 - Val));
3129 return MCDisassembler::Success;
3132 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3133 uint64_t Address, const void *Decoder) {
3134 Inst.addOperand(MCOperand::createImm(64 - Val));
3135 return MCDisassembler::Success;
3138 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3139 uint64_t Address, const void *Decoder) {
3140 DecodeStatus S = MCDisassembler::Success;
3142 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3143 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3144 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3145 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3146 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3147 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3148 unsigned op = fieldFromInstruction(Insn, 6, 1);
3150 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3151 return MCDisassembler::Fail;
3153 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3154 return MCDisassembler::Fail; // Writeback
3157 switch (Inst.getOpcode()) {
3160 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3161 return MCDisassembler::Fail;
3164 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3165 return MCDisassembler::Fail;
3168 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3169 return MCDisassembler::Fail;
3174 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3175 uint64_t Address, const void *Decoder) {
3176 DecodeStatus S = MCDisassembler::Success;
3178 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3179 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3181 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3182 return MCDisassembler::Fail;
3184 switch(Inst.getOpcode()) {
3186 return MCDisassembler::Fail;
3188 break; // tADR does not explicitly represent the PC as an operand.
3190 Inst.addOperand(MCOperand::createReg(ARM::SP));
3194 Inst.addOperand(MCOperand::createImm(imm));
3198 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3199 uint64_t Address, const void *Decoder) {
3200 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3201 true, 2, Inst, Decoder))
3202 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3203 return MCDisassembler::Success;
3206 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3207 uint64_t Address, const void *Decoder) {
3208 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3209 true, 4, Inst, Decoder))
3210 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3211 return MCDisassembler::Success;
3214 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3215 uint64_t Address, const void *Decoder) {
3216 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3217 true, 2, Inst, Decoder))
3218 Inst.addOperand(MCOperand::createImm(Val << 1));
3219 return MCDisassembler::Success;
3222 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3223 uint64_t Address, const void *Decoder) {
3224 DecodeStatus S = MCDisassembler::Success;
3226 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3227 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3229 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3230 return MCDisassembler::Fail;
3231 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3232 return MCDisassembler::Fail;
3237 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3238 uint64_t Address, const void *Decoder) {
3239 DecodeStatus S = MCDisassembler::Success;
3241 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3242 unsigned imm = fieldFromInstruction(Val, 3, 5);
3244 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3245 return MCDisassembler::Fail;
3246 Inst.addOperand(MCOperand::createImm(imm));
3251 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3252 uint64_t Address, const void *Decoder) {
3253 unsigned imm = Val << 2;
3255 Inst.addOperand(MCOperand::createImm(imm));
3256 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3258 return MCDisassembler::Success;
3261 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3262 uint64_t Address, const void *Decoder) {
3263 Inst.addOperand(MCOperand::createReg(ARM::SP));
3264 Inst.addOperand(MCOperand::createImm(Val));
3266 return MCDisassembler::Success;
3269 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3270 uint64_t Address, const void *Decoder) {
3271 DecodeStatus S = MCDisassembler::Success;
3273 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3274 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3275 unsigned imm = fieldFromInstruction(Val, 0, 2);
3277 // Thumb stores cannot use PC as dest register.
3278 switch (Inst.getOpcode()) {
3283 return MCDisassembler::Fail;
3288 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3289 return MCDisassembler::Fail;
3290 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3291 return MCDisassembler::Fail;
3292 Inst.addOperand(MCOperand::createImm(imm));
3297 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3298 uint64_t Address, const void *Decoder) {
3299 DecodeStatus S = MCDisassembler::Success;
3301 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3302 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3304 const FeatureBitset &featureBits =
3305 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3307 bool hasMP = featureBits[ARM::FeatureMP];
3308 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3311 switch (Inst.getOpcode()) {
3313 Inst.setOpcode(ARM::t2LDRBpci);
3316 Inst.setOpcode(ARM::t2LDRHpci);
3319 Inst.setOpcode(ARM::t2LDRSHpci);
3322 Inst.setOpcode(ARM::t2LDRSBpci);
3325 Inst.setOpcode(ARM::t2LDRpci);
3328 Inst.setOpcode(ARM::t2PLDpci);
3331 Inst.setOpcode(ARM::t2PLIpci);
3334 return MCDisassembler::Fail;
3337 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3341 switch (Inst.getOpcode()) {
3343 return MCDisassembler::Fail;
3345 Inst.setOpcode(ARM::t2PLDWs);
3348 Inst.setOpcode(ARM::t2PLIs);
3354 switch (Inst.getOpcode()) {
3359 return MCDisassembler::Fail;
3362 if (!hasV7Ops || !hasMP)
3363 return MCDisassembler::Fail;
3366 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3367 return MCDisassembler::Fail;
3370 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3371 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3372 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3373 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3374 return MCDisassembler::Fail;
3379 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3380 uint64_t Address, const void* Decoder) {
3381 DecodeStatus S = MCDisassembler::Success;
3383 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3384 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3385 unsigned U = fieldFromInstruction(Insn, 9, 1);
3386 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3389 unsigned add = fieldFromInstruction(Insn, 9, 1);
3391 const FeatureBitset &featureBits =
3392 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3394 bool hasMP = featureBits[ARM::FeatureMP];
3395 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3398 switch (Inst.getOpcode()) {
3400 Inst.setOpcode(ARM::t2LDRpci);
3403 Inst.setOpcode(ARM::t2LDRBpci);
3405 case ARM::t2LDRSBi8:
3406 Inst.setOpcode(ARM::t2LDRSBpci);
3409 Inst.setOpcode(ARM::t2LDRHpci);
3411 case ARM::t2LDRSHi8:
3412 Inst.setOpcode(ARM::t2LDRSHpci);
3415 Inst.setOpcode(ARM::t2PLDpci);
3418 Inst.setOpcode(ARM::t2PLIpci);
3421 return MCDisassembler::Fail;
3423 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3427 switch (Inst.getOpcode()) {
3428 case ARM::t2LDRSHi8:
3429 return MCDisassembler::Fail;
3432 Inst.setOpcode(ARM::t2PLDWi8);
3434 case ARM::t2LDRSBi8:
3435 Inst.setOpcode(ARM::t2PLIi8);
3442 switch (Inst.getOpcode()) {
3447 return MCDisassembler::Fail;
3450 if (!hasV7Ops || !hasMP)
3451 return MCDisassembler::Fail;
3454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3455 return MCDisassembler::Fail;
3458 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3459 return MCDisassembler::Fail;
3463 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3464 uint64_t Address, const void* Decoder) {
3465 DecodeStatus S = MCDisassembler::Success;
3467 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3468 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3469 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3472 const FeatureBitset &featureBits =
3473 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3475 bool hasMP = featureBits[ARM::FeatureMP];
3476 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3479 switch (Inst.getOpcode()) {
3481 Inst.setOpcode(ARM::t2LDRpci);
3483 case ARM::t2LDRHi12:
3484 Inst.setOpcode(ARM::t2LDRHpci);
3486 case ARM::t2LDRSHi12:
3487 Inst.setOpcode(ARM::t2LDRSHpci);
3489 case ARM::t2LDRBi12:
3490 Inst.setOpcode(ARM::t2LDRBpci);
3492 case ARM::t2LDRSBi12:
3493 Inst.setOpcode(ARM::t2LDRSBpci);
3496 Inst.setOpcode(ARM::t2PLDpci);
3499 Inst.setOpcode(ARM::t2PLIpci);
3502 return MCDisassembler::Fail;
3504 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3508 switch (Inst.getOpcode()) {
3509 case ARM::t2LDRSHi12:
3510 return MCDisassembler::Fail;
3511 case ARM::t2LDRHi12:
3512 Inst.setOpcode(ARM::t2PLDWi12);
3514 case ARM::t2LDRSBi12:
3515 Inst.setOpcode(ARM::t2PLIi12);
3522 switch (Inst.getOpcode()) {
3527 return MCDisassembler::Fail;
3529 case ARM::t2PLDWi12:
3530 if (!hasV7Ops || !hasMP)
3531 return MCDisassembler::Fail;
3534 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3535 return MCDisassembler::Fail;
3538 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3539 return MCDisassembler::Fail;
3543 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3544 uint64_t Address, const void* Decoder) {
3545 DecodeStatus S = MCDisassembler::Success;
3547 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3548 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3549 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3553 switch (Inst.getOpcode()) {
3555 Inst.setOpcode(ARM::t2LDRpci);
3558 Inst.setOpcode(ARM::t2LDRBpci);
3561 Inst.setOpcode(ARM::t2LDRHpci);
3564 Inst.setOpcode(ARM::t2LDRSBpci);
3567 Inst.setOpcode(ARM::t2LDRSHpci);
3570 return MCDisassembler::Fail;
3572 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3575 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3576 return MCDisassembler::Fail;
3577 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3578 return MCDisassembler::Fail;
3582 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3583 uint64_t Address, const void* Decoder) {
3584 DecodeStatus S = MCDisassembler::Success;
3586 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3587 unsigned U = fieldFromInstruction(Insn, 23, 1);
3588 int imm = fieldFromInstruction(Insn, 0, 12);
3590 const FeatureBitset &featureBits =
3591 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3593 bool hasV7Ops = featureBits[ARM::HasV7Ops];
3596 switch (Inst.getOpcode()) {
3597 case ARM::t2LDRBpci:
3598 case ARM::t2LDRHpci:
3599 Inst.setOpcode(ARM::t2PLDpci);
3601 case ARM::t2LDRSBpci:
3602 Inst.setOpcode(ARM::t2PLIpci);
3604 case ARM::t2LDRSHpci:
3605 return MCDisassembler::Fail;
3611 switch(Inst.getOpcode()) {
3616 return MCDisassembler::Fail;
3619 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3620 return MCDisassembler::Fail;
3624 // Special case for #-0.
3630 Inst.addOperand(MCOperand::createImm(imm));
3635 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3636 uint64_t Address, const void *Decoder) {
3638 Inst.addOperand(MCOperand::createImm(INT32_MIN));
3640 int imm = Val & 0xFF;
3642 if (!(Val & 0x100)) imm *= -1;
3643 Inst.addOperand(MCOperand::createImm(imm * 4));
3646 return MCDisassembler::Success;
3649 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3650 uint64_t Address, const void *Decoder) {
3651 DecodeStatus S = MCDisassembler::Success;
3653 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3654 unsigned imm = fieldFromInstruction(Val, 0, 9);
3656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3657 return MCDisassembler::Fail;
3658 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3659 return MCDisassembler::Fail;
3664 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3665 uint64_t Address, const void *Decoder) {
3666 DecodeStatus S = MCDisassembler::Success;
3668 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3669 unsigned imm = fieldFromInstruction(Val, 0, 8);
3671 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3672 return MCDisassembler::Fail;
3674 Inst.addOperand(MCOperand::createImm(imm));
3679 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3680 uint64_t Address, const void *Decoder) {
3681 int imm = Val & 0xFF;
3684 else if (!(Val & 0x100))
3686 Inst.addOperand(MCOperand::createImm(imm));
3688 return MCDisassembler::Success;
3692 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3693 uint64_t Address, const void *Decoder) {
3694 DecodeStatus S = MCDisassembler::Success;
3696 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3697 unsigned imm = fieldFromInstruction(Val, 0, 9);
3699 // Thumb stores cannot use PC as dest register.
3700 switch (Inst.getOpcode()) {
3708 return MCDisassembler::Fail;
3714 // Some instructions always use an additive offset.
3715 switch (Inst.getOpcode()) {
3730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3731 return MCDisassembler::Fail;
3732 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3733 return MCDisassembler::Fail;
3738 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3739 uint64_t Address, const void *Decoder) {
3740 DecodeStatus S = MCDisassembler::Success;
3742 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3743 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3744 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3745 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3747 unsigned load = fieldFromInstruction(Insn, 20, 1);
3750 switch (Inst.getOpcode()) {
3751 case ARM::t2LDR_PRE:
3752 case ARM::t2LDR_POST:
3753 Inst.setOpcode(ARM::t2LDRpci);
3755 case ARM::t2LDRB_PRE:
3756 case ARM::t2LDRB_POST:
3757 Inst.setOpcode(ARM::t2LDRBpci);
3759 case ARM::t2LDRH_PRE:
3760 case ARM::t2LDRH_POST:
3761 Inst.setOpcode(ARM::t2LDRHpci);
3763 case ARM::t2LDRSB_PRE:
3764 case ARM::t2LDRSB_POST:
3766 Inst.setOpcode(ARM::t2PLIpci);
3768 Inst.setOpcode(ARM::t2LDRSBpci);
3770 case ARM::t2LDRSH_PRE:
3771 case ARM::t2LDRSH_POST:
3772 Inst.setOpcode(ARM::t2LDRSHpci);
3775 return MCDisassembler::Fail;
3777 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3781 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3782 return MCDisassembler::Fail;
3785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3786 return MCDisassembler::Fail;
3789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3790 return MCDisassembler::Fail;
3793 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3794 return MCDisassembler::Fail;
3799 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3800 uint64_t Address, const void *Decoder) {
3801 DecodeStatus S = MCDisassembler::Success;
3803 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3804 unsigned imm = fieldFromInstruction(Val, 0, 12);
3806 // Thumb stores cannot use PC as dest register.
3807 switch (Inst.getOpcode()) {
3809 case ARM::t2STRBi12:
3810 case ARM::t2STRHi12:
3812 return MCDisassembler::Fail;
3817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3818 return MCDisassembler::Fail;
3819 Inst.addOperand(MCOperand::createImm(imm));
3825 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3826 uint64_t Address, const void *Decoder) {
3827 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3829 Inst.addOperand(MCOperand::createReg(ARM::SP));
3830 Inst.addOperand(MCOperand::createReg(ARM::SP));
3831 Inst.addOperand(MCOperand::createImm(imm));
3833 return MCDisassembler::Success;
3836 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3837 uint64_t Address, const void *Decoder) {
3838 DecodeStatus S = MCDisassembler::Success;
3840 if (Inst.getOpcode() == ARM::tADDrSP) {
3841 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3842 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3844 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3845 return MCDisassembler::Fail;
3846 Inst.addOperand(MCOperand::createReg(ARM::SP));
3847 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3848 return MCDisassembler::Fail;
3849 } else if (Inst.getOpcode() == ARM::tADDspr) {
3850 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3852 Inst.addOperand(MCOperand::createReg(ARM::SP));
3853 Inst.addOperand(MCOperand::createReg(ARM::SP));
3854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3855 return MCDisassembler::Fail;
3861 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3862 uint64_t Address, const void *Decoder) {
3863 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3864 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3866 Inst.addOperand(MCOperand::createImm(imod));
3867 Inst.addOperand(MCOperand::createImm(flags));
3869 return MCDisassembler::Success;
3872 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3873 uint64_t Address, const void *Decoder) {
3874 DecodeStatus S = MCDisassembler::Success;
3875 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3876 unsigned add = fieldFromInstruction(Insn, 4, 1);
3878 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3879 return MCDisassembler::Fail;
3880 Inst.addOperand(MCOperand::createImm(add));
3885 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3886 uint64_t Address, const void *Decoder) {
3887 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3888 // Note only one trailing zero not two. Also the J1 and J2 values are from
3889 // the encoded instruction. So here change to I1 and I2 values via:
3890 // I1 = NOT(J1 EOR S);
3891 // I2 = NOT(J2 EOR S);
3892 // and build the imm32 with two trailing zeros as documented:
3893 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3894 unsigned S = (Val >> 23) & 1;
3895 unsigned J1 = (Val >> 22) & 1;
3896 unsigned J2 = (Val >> 21) & 1;
3897 unsigned I1 = !(J1 ^ S);
3898 unsigned I2 = !(J2 ^ S);
3899 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3900 int imm32 = SignExtend32<25>(tmp << 1);
3902 if (!tryAddingSymbolicOperand(Address,
3903 (Address & ~2u) + imm32 + 4,
3904 true, 4, Inst, Decoder))
3905 Inst.addOperand(MCOperand::createImm(imm32));
3906 return MCDisassembler::Success;
3909 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3910 uint64_t Address, const void *Decoder) {
3911 if (Val == 0xA || Val == 0xB)
3912 return MCDisassembler::Fail;
3914 const FeatureBitset &featureBits =
3915 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
3917 if (featureBits[ARM::HasV8Ops] && !(Val == 14 || Val == 15))
3918 return MCDisassembler::Fail;
3920 Inst.addOperand(MCOperand::createImm(Val));
3921 return MCDisassembler::Success;
3925 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3926 uint64_t Address, const void *Decoder) {
3927 DecodeStatus S = MCDisassembler::Success;
3929 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3930 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3932 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3933 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3934 return MCDisassembler::Fail;
3935 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3936 return MCDisassembler::Fail;
3941 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3942 uint64_t Address, const void *Decoder) {
3943 DecodeStatus S = MCDisassembler::Success;
3945 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3946 if (pred == 0xE || pred == 0xF) {
3947 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3950 return MCDisassembler::Fail;
3952 Inst.setOpcode(ARM::t2DSB);
3955 Inst.setOpcode(ARM::t2DMB);
3958 Inst.setOpcode(ARM::t2ISB);
3962 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3963 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3966 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3967 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3968 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3969 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3970 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3972 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3973 return MCDisassembler::Fail;
3974 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3975 return MCDisassembler::Fail;
3980 // Decode a shifted immediate operand. These basically consist
3981 // of an 8-bit value, and a 4-bit directive that specifies either
3982 // a splat operation or a rotation.
3983 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3984 uint64_t Address, const void *Decoder) {
3985 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3987 unsigned byte = fieldFromInstruction(Val, 8, 2);
3988 unsigned imm = fieldFromInstruction(Val, 0, 8);
3991 Inst.addOperand(MCOperand::createImm(imm));
3994 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
3997 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4000 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4005 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
4006 unsigned rot = fieldFromInstruction(Val, 7, 5);
4007 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
4008 Inst.addOperand(MCOperand::createImm(imm));
4011 return MCDisassembler::Success;
4015 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4016 uint64_t Address, const void *Decoder){
4017 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
4018 true, 2, Inst, Decoder))
4019 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4020 return MCDisassembler::Success;
4023 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4024 uint64_t Address, const void *Decoder){
4025 // Val is passed in as S:J1:J2:imm10:imm11
4026 // Note no trailing zero after imm11. Also the J1 and J2 values are from
4027 // the encoded instruction. So here change to I1 and I2 values via:
4028 // I1 = NOT(J1 EOR S);
4029 // I2 = NOT(J2 EOR S);
4030 // and build the imm32 with one trailing zero as documented:
4031 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
4032 unsigned S = (Val >> 23) & 1;
4033 unsigned J1 = (Val >> 22) & 1;
4034 unsigned J2 = (Val >> 21) & 1;
4035 unsigned I1 = !(J1 ^ S);
4036 unsigned I2 = !(J2 ^ S);
4037 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4038 int imm32 = SignExtend32<25>(tmp << 1);
4040 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4041 true, 4, Inst, Decoder))
4042 Inst.addOperand(MCOperand::createImm(imm32));
4043 return MCDisassembler::Success;
4046 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4047 uint64_t Address, const void *Decoder) {
4049 return MCDisassembler::Fail;
4051 Inst.addOperand(MCOperand::createImm(Val));
4052 return MCDisassembler::Success;
4055 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4056 uint64_t Address, const void *Decoder) {
4058 return MCDisassembler::Fail;
4060 Inst.addOperand(MCOperand::createImm(Val));
4061 return MCDisassembler::Success;
4064 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4065 uint64_t Address, const void *Decoder) {
4066 DecodeStatus S = MCDisassembler::Success;
4067 const FeatureBitset &FeatureBits =
4068 ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
4070 if (FeatureBits[ARM::FeatureMClass]) {
4071 unsigned ValLow = Val & 0xff;
4073 // Validate the SYSm value first.
4088 case 18: // basepri_max
4089 case 19: // faultmask
4090 if (!(FeatureBits[ARM::HasV7Ops]))
4091 // Values basepri, basepri_max and faultmask are only valid for v7m.
4092 return MCDisassembler::Fail;
4095 return MCDisassembler::Fail;
4098 if (Inst.getOpcode() == ARM::t2MSR_M) {
4099 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4100 if (!(FeatureBits[ARM::HasV7Ops])) {
4101 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4104 S = MCDisassembler::SoftFail;
4107 // The ARMv7-M architecture stores an additional 2-bit mask value in
4108 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4109 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4110 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4111 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4112 // only if the processor includes the DSP extension.
4113 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4114 (!(FeatureBits[ARM::FeatureDSP]) && (Mask & 1)))
4115 S = MCDisassembler::SoftFail;
4121 return MCDisassembler::Fail;
4123 Inst.addOperand(MCOperand::createImm(Val));
4127 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4128 uint64_t Address, const void *Decoder) {
4130 unsigned R = fieldFromInstruction(Val, 5, 1);
4131 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4133 // The table of encodings for these banked registers comes from B9.2.3 of the
4134 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4135 // neater. So by fiat, these values are UNPREDICTABLE:
4137 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4138 SysM == 0x1a || SysM == 0x1b)
4139 return MCDisassembler::SoftFail;
4141 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4142 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4143 return MCDisassembler::SoftFail;
4146 Inst.addOperand(MCOperand::createImm(Val));
4147 return MCDisassembler::Success;
4150 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4151 uint64_t Address, const void *Decoder) {
4152 DecodeStatus S = MCDisassembler::Success;
4154 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4155 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4156 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4159 S = MCDisassembler::SoftFail;
4161 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4162 return MCDisassembler::Fail;
4163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4164 return MCDisassembler::Fail;
4165 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4166 return MCDisassembler::Fail;
4171 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4172 uint64_t Address, const void *Decoder){
4173 DecodeStatus S = MCDisassembler::Success;
4175 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4176 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4177 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4178 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4180 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4181 return MCDisassembler::Fail;
4183 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4184 S = MCDisassembler::SoftFail;
4186 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4187 return MCDisassembler::Fail;
4188 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4189 return MCDisassembler::Fail;
4190 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4191 return MCDisassembler::Fail;
4196 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4197 uint64_t Address, const void *Decoder) {
4198 DecodeStatus S = MCDisassembler::Success;
4200 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4201 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4202 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4203 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4204 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4205 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4207 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4209 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4210 return MCDisassembler::Fail;
4211 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4212 return MCDisassembler::Fail;
4213 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4214 return MCDisassembler::Fail;
4215 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4216 return MCDisassembler::Fail;
4221 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4222 uint64_t Address, const void *Decoder) {
4223 DecodeStatus S = MCDisassembler::Success;
4225 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4226 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4227 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4228 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4229 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4230 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4231 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4233 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4234 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4237 return MCDisassembler::Fail;
4238 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4239 return MCDisassembler::Fail;
4240 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4241 return MCDisassembler::Fail;
4242 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4243 return MCDisassembler::Fail;
4249 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4250 uint64_t Address, const void *Decoder) {
4251 DecodeStatus S = MCDisassembler::Success;
4253 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4254 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4255 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4256 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4257 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4258 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4260 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4262 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4263 return MCDisassembler::Fail;
4264 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4265 return MCDisassembler::Fail;
4266 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4267 return MCDisassembler::Fail;
4268 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4269 return MCDisassembler::Fail;
4274 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4275 uint64_t Address, const void *Decoder) {
4276 DecodeStatus S = MCDisassembler::Success;
4278 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4279 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4280 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4281 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4282 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4283 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4285 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4287 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4288 return MCDisassembler::Fail;
4289 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4290 return MCDisassembler::Fail;
4291 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4292 return MCDisassembler::Fail;
4293 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4294 return MCDisassembler::Fail;
4299 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4300 uint64_t Address, const void *Decoder) {
4301 DecodeStatus S = MCDisassembler::Success;
4303 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4304 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4305 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4306 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4307 unsigned size = fieldFromInstruction(Insn, 10, 2);
4313 return MCDisassembler::Fail;
4315 if (fieldFromInstruction(Insn, 4, 1))
4316 return MCDisassembler::Fail; // UNDEFINED
4317 index = fieldFromInstruction(Insn, 5, 3);
4320 if (fieldFromInstruction(Insn, 5, 1))
4321 return MCDisassembler::Fail; // UNDEFINED
4322 index = fieldFromInstruction(Insn, 6, 2);
4323 if (fieldFromInstruction(Insn, 4, 1))
4327 if (fieldFromInstruction(Insn, 6, 1))
4328 return MCDisassembler::Fail; // UNDEFINED
4329 index = fieldFromInstruction(Insn, 7, 1);
4331 switch (fieldFromInstruction(Insn, 4, 2)) {
4337 return MCDisassembler::Fail;
4342 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4343 return MCDisassembler::Fail;
4344 if (Rm != 0xF) { // Writeback
4345 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4346 return MCDisassembler::Fail;
4348 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4349 return MCDisassembler::Fail;
4350 Inst.addOperand(MCOperand::createImm(align));
4353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4354 return MCDisassembler::Fail;
4356 Inst.addOperand(MCOperand::createReg(0));
4359 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4360 return MCDisassembler::Fail;
4361 Inst.addOperand(MCOperand::createImm(index));
4366 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4367 uint64_t Address, const void *Decoder) {
4368 DecodeStatus S = MCDisassembler::Success;
4370 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4371 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4372 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4373 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4374 unsigned size = fieldFromInstruction(Insn, 10, 2);
4380 return MCDisassembler::Fail;
4382 if (fieldFromInstruction(Insn, 4, 1))
4383 return MCDisassembler::Fail; // UNDEFINED
4384 index = fieldFromInstruction(Insn, 5, 3);
4387 if (fieldFromInstruction(Insn, 5, 1))
4388 return MCDisassembler::Fail; // UNDEFINED
4389 index = fieldFromInstruction(Insn, 6, 2);
4390 if (fieldFromInstruction(Insn, 4, 1))
4394 if (fieldFromInstruction(Insn, 6, 1))
4395 return MCDisassembler::Fail; // UNDEFINED
4396 index = fieldFromInstruction(Insn, 7, 1);
4398 switch (fieldFromInstruction(Insn, 4, 2)) {
4404 return MCDisassembler::Fail;
4409 if (Rm != 0xF) { // Writeback
4410 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4411 return MCDisassembler::Fail;
4413 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4414 return MCDisassembler::Fail;
4415 Inst.addOperand(MCOperand::createImm(align));
4418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4419 return MCDisassembler::Fail;
4421 Inst.addOperand(MCOperand::createReg(0));
4424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4425 return MCDisassembler::Fail;
4426 Inst.addOperand(MCOperand::createImm(index));
4432 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4433 uint64_t Address, const void *Decoder) {
4434 DecodeStatus S = MCDisassembler::Success;
4436 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4437 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4438 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4439 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4440 unsigned size = fieldFromInstruction(Insn, 10, 2);
4447 return MCDisassembler::Fail;
4449 index = fieldFromInstruction(Insn, 5, 3);
4450 if (fieldFromInstruction(Insn, 4, 1))
4454 index = fieldFromInstruction(Insn, 6, 2);
4455 if (fieldFromInstruction(Insn, 4, 1))
4457 if (fieldFromInstruction(Insn, 5, 1))
4461 if (fieldFromInstruction(Insn, 5, 1))
4462 return MCDisassembler::Fail; // UNDEFINED
4463 index = fieldFromInstruction(Insn, 7, 1);
4464 if (fieldFromInstruction(Insn, 4, 1) != 0)
4466 if (fieldFromInstruction(Insn, 6, 1))
4471 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4472 return MCDisassembler::Fail;
4473 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4474 return MCDisassembler::Fail;
4475 if (Rm != 0xF) { // Writeback
4476 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4477 return MCDisassembler::Fail;
4479 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4480 return MCDisassembler::Fail;
4481 Inst.addOperand(MCOperand::createImm(align));
4484 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4485 return MCDisassembler::Fail;
4487 Inst.addOperand(MCOperand::createReg(0));
4490 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4491 return MCDisassembler::Fail;
4492 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4493 return MCDisassembler::Fail;
4494 Inst.addOperand(MCOperand::createImm(index));
4499 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4500 uint64_t Address, const void *Decoder) {
4501 DecodeStatus S = MCDisassembler::Success;
4503 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4504 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4505 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4506 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4507 unsigned size = fieldFromInstruction(Insn, 10, 2);
4514 return MCDisassembler::Fail;
4516 index = fieldFromInstruction(Insn, 5, 3);
4517 if (fieldFromInstruction(Insn, 4, 1))
4521 index = fieldFromInstruction(Insn, 6, 2);
4522 if (fieldFromInstruction(Insn, 4, 1))
4524 if (fieldFromInstruction(Insn, 5, 1))
4528 if (fieldFromInstruction(Insn, 5, 1))
4529 return MCDisassembler::Fail; // UNDEFINED
4530 index = fieldFromInstruction(Insn, 7, 1);
4531 if (fieldFromInstruction(Insn, 4, 1) != 0)
4533 if (fieldFromInstruction(Insn, 6, 1))
4538 if (Rm != 0xF) { // Writeback
4539 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4540 return MCDisassembler::Fail;
4542 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4543 return MCDisassembler::Fail;
4544 Inst.addOperand(MCOperand::createImm(align));
4547 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4548 return MCDisassembler::Fail;
4550 Inst.addOperand(MCOperand::createReg(0));
4553 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4554 return MCDisassembler::Fail;
4555 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4556 return MCDisassembler::Fail;
4557 Inst.addOperand(MCOperand::createImm(index));
4563 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4564 uint64_t Address, const void *Decoder) {
4565 DecodeStatus S = MCDisassembler::Success;
4567 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4568 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4569 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4570 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4571 unsigned size = fieldFromInstruction(Insn, 10, 2);
4578 return MCDisassembler::Fail;
4580 if (fieldFromInstruction(Insn, 4, 1))
4581 return MCDisassembler::Fail; // UNDEFINED
4582 index = fieldFromInstruction(Insn, 5, 3);
4585 if (fieldFromInstruction(Insn, 4, 1))
4586 return MCDisassembler::Fail; // UNDEFINED
4587 index = fieldFromInstruction(Insn, 6, 2);
4588 if (fieldFromInstruction(Insn, 5, 1))
4592 if (fieldFromInstruction(Insn, 4, 2))
4593 return MCDisassembler::Fail; // UNDEFINED
4594 index = fieldFromInstruction(Insn, 7, 1);
4595 if (fieldFromInstruction(Insn, 6, 1))
4600 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4601 return MCDisassembler::Fail;
4602 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4603 return MCDisassembler::Fail;
4604 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4605 return MCDisassembler::Fail;
4607 if (Rm != 0xF) { // Writeback
4608 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4609 return MCDisassembler::Fail;
4611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4612 return MCDisassembler::Fail;
4613 Inst.addOperand(MCOperand::createImm(align));
4616 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4617 return MCDisassembler::Fail;
4619 Inst.addOperand(MCOperand::createReg(0));
4622 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4623 return MCDisassembler::Fail;
4624 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4625 return MCDisassembler::Fail;
4626 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4627 return MCDisassembler::Fail;
4628 Inst.addOperand(MCOperand::createImm(index));
4633 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4634 uint64_t Address, const void *Decoder) {
4635 DecodeStatus S = MCDisassembler::Success;
4637 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4638 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4639 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4640 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4641 unsigned size = fieldFromInstruction(Insn, 10, 2);
4648 return MCDisassembler::Fail;
4650 if (fieldFromInstruction(Insn, 4, 1))
4651 return MCDisassembler::Fail; // UNDEFINED
4652 index = fieldFromInstruction(Insn, 5, 3);
4655 if (fieldFromInstruction(Insn, 4, 1))
4656 return MCDisassembler::Fail; // UNDEFINED
4657 index = fieldFromInstruction(Insn, 6, 2);
4658 if (fieldFromInstruction(Insn, 5, 1))
4662 if (fieldFromInstruction(Insn, 4, 2))
4663 return MCDisassembler::Fail; // UNDEFINED
4664 index = fieldFromInstruction(Insn, 7, 1);
4665 if (fieldFromInstruction(Insn, 6, 1))
4670 if (Rm != 0xF) { // Writeback
4671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4672 return MCDisassembler::Fail;
4674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4675 return MCDisassembler::Fail;
4676 Inst.addOperand(MCOperand::createImm(align));
4679 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4680 return MCDisassembler::Fail;
4682 Inst.addOperand(MCOperand::createReg(0));
4685 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4686 return MCDisassembler::Fail;
4687 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4688 return MCDisassembler::Fail;
4689 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4690 return MCDisassembler::Fail;
4691 Inst.addOperand(MCOperand::createImm(index));
4697 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4698 uint64_t Address, const void *Decoder) {
4699 DecodeStatus S = MCDisassembler::Success;
4701 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4702 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4703 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4704 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4705 unsigned size = fieldFromInstruction(Insn, 10, 2);
4712 return MCDisassembler::Fail;
4714 if (fieldFromInstruction(Insn, 4, 1))
4716 index = fieldFromInstruction(Insn, 5, 3);
4719 if (fieldFromInstruction(Insn, 4, 1))
4721 index = fieldFromInstruction(Insn, 6, 2);
4722 if (fieldFromInstruction(Insn, 5, 1))
4726 switch (fieldFromInstruction(Insn, 4, 2)) {
4730 return MCDisassembler::Fail;
4732 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4735 index = fieldFromInstruction(Insn, 7, 1);
4736 if (fieldFromInstruction(Insn, 6, 1))
4741 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4742 return MCDisassembler::Fail;
4743 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4744 return MCDisassembler::Fail;
4745 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4746 return MCDisassembler::Fail;
4747 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4748 return MCDisassembler::Fail;
4750 if (Rm != 0xF) { // Writeback
4751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4752 return MCDisassembler::Fail;
4754 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4755 return MCDisassembler::Fail;
4756 Inst.addOperand(MCOperand::createImm(align));
4759 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4760 return MCDisassembler::Fail;
4762 Inst.addOperand(MCOperand::createReg(0));
4765 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4766 return MCDisassembler::Fail;
4767 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4768 return MCDisassembler::Fail;
4769 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4770 return MCDisassembler::Fail;
4771 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4772 return MCDisassembler::Fail;
4773 Inst.addOperand(MCOperand::createImm(index));
4778 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4779 uint64_t Address, const void *Decoder) {
4780 DecodeStatus S = MCDisassembler::Success;
4782 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4783 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4784 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4785 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4786 unsigned size = fieldFromInstruction(Insn, 10, 2);
4793 return MCDisassembler::Fail;
4795 if (fieldFromInstruction(Insn, 4, 1))
4797 index = fieldFromInstruction(Insn, 5, 3);
4800 if (fieldFromInstruction(Insn, 4, 1))
4802 index = fieldFromInstruction(Insn, 6, 2);
4803 if (fieldFromInstruction(Insn, 5, 1))
4807 switch (fieldFromInstruction(Insn, 4, 2)) {
4811 return MCDisassembler::Fail;
4813 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4816 index = fieldFromInstruction(Insn, 7, 1);
4817 if (fieldFromInstruction(Insn, 6, 1))
4822 if (Rm != 0xF) { // Writeback
4823 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4824 return MCDisassembler::Fail;
4826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4827 return MCDisassembler::Fail;
4828 Inst.addOperand(MCOperand::createImm(align));
4831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4832 return MCDisassembler::Fail;
4834 Inst.addOperand(MCOperand::createReg(0));
4837 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4838 return MCDisassembler::Fail;
4839 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4840 return MCDisassembler::Fail;
4841 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4842 return MCDisassembler::Fail;
4843 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4844 return MCDisassembler::Fail;
4845 Inst.addOperand(MCOperand::createImm(index));
4850 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4851 uint64_t Address, const void *Decoder) {
4852 DecodeStatus S = MCDisassembler::Success;
4853 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4854 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4855 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4856 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4857 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4859 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4860 S = MCDisassembler::SoftFail;
4862 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4863 return MCDisassembler::Fail;
4864 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4865 return MCDisassembler::Fail;
4866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4867 return MCDisassembler::Fail;
4868 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4869 return MCDisassembler::Fail;
4870 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4871 return MCDisassembler::Fail;
4876 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4877 uint64_t Address, const void *Decoder) {
4878 DecodeStatus S = MCDisassembler::Success;
4879 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4880 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4881 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4882 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4883 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4885 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4886 S = MCDisassembler::SoftFail;
4888 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4889 return MCDisassembler::Fail;
4890 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4891 return MCDisassembler::Fail;
4892 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4893 return MCDisassembler::Fail;
4894 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4895 return MCDisassembler::Fail;
4896 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4897 return MCDisassembler::Fail;
4902 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4903 uint64_t Address, const void *Decoder) {
4904 DecodeStatus S = MCDisassembler::Success;
4905 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4906 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4910 S = MCDisassembler::SoftFail;
4914 return MCDisassembler::Fail;
4916 Inst.addOperand(MCOperand::createImm(pred));
4917 Inst.addOperand(MCOperand::createImm(mask));
4922 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4923 uint64_t Address, const void *Decoder) {
4924 DecodeStatus S = MCDisassembler::Success;
4926 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4927 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4928 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4929 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4930 unsigned W = fieldFromInstruction(Insn, 21, 1);
4931 unsigned U = fieldFromInstruction(Insn, 23, 1);
4932 unsigned P = fieldFromInstruction(Insn, 24, 1);
4933 bool writeback = (W == 1) | (P == 0);
4935 addr |= (U << 8) | (Rn << 9);
4937 if (writeback && (Rn == Rt || Rn == Rt2))
4938 Check(S, MCDisassembler::SoftFail);
4940 Check(S, MCDisassembler::SoftFail);
4943 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4944 return MCDisassembler::Fail;
4946 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4947 return MCDisassembler::Fail;
4948 // Writeback operand
4949 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4950 return MCDisassembler::Fail;
4952 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4953 return MCDisassembler::Fail;
4959 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4960 uint64_t Address, const void *Decoder) {
4961 DecodeStatus S = MCDisassembler::Success;
4963 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4964 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4965 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4966 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4967 unsigned W = fieldFromInstruction(Insn, 21, 1);
4968 unsigned U = fieldFromInstruction(Insn, 23, 1);
4969 unsigned P = fieldFromInstruction(Insn, 24, 1);
4970 bool writeback = (W == 1) | (P == 0);
4972 addr |= (U << 8) | (Rn << 9);
4974 if (writeback && (Rn == Rt || Rn == Rt2))
4975 Check(S, MCDisassembler::SoftFail);
4977 // Writeback operand
4978 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4979 return MCDisassembler::Fail;
4981 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4982 return MCDisassembler::Fail;
4984 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4985 return MCDisassembler::Fail;
4987 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4988 return MCDisassembler::Fail;
4993 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4994 uint64_t Address, const void *Decoder) {
4995 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4996 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4997 if (sign1 != sign2) return MCDisassembler::Fail;
4999 unsigned Val = fieldFromInstruction(Insn, 0, 8);
5000 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
5001 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
5003 Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
5005 return MCDisassembler::Success;
5008 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5010 const void *Decoder) {
5011 DecodeStatus S = MCDisassembler::Success;
5013 // Shift of "asr #32" is not allowed in Thumb2 mode.
5014 if (Val == 0x20) S = MCDisassembler::Fail;
5015 Inst.addOperand(MCOperand::createImm(Val));
5019 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
5020 uint64_t Address, const void *Decoder) {
5021 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
5022 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
5023 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
5024 unsigned pred = fieldFromInstruction(Insn, 28, 4);
5027 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
5029 DecodeStatus S = MCDisassembler::Success;
5031 if (Rt == Rn || Rn == Rt2)
5032 S = MCDisassembler::SoftFail;
5034 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5035 return MCDisassembler::Fail;
5036 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5037 return MCDisassembler::Fail;
5038 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5039 return MCDisassembler::Fail;
5040 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5041 return MCDisassembler::Fail;
5046 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5047 uint64_t Address, const void *Decoder) {
5048 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5049 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5050 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5051 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5052 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5053 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5054 unsigned op = fieldFromInstruction(Insn, 5, 1);
5056 DecodeStatus S = MCDisassembler::Success;
5058 // VMOVv2f32 is ambiguous with these decodings.
5059 if (!(imm & 0x38) && cmode == 0xF) {
5060 if (op == 1) return MCDisassembler::Fail;
5061 Inst.setOpcode(ARM::VMOVv2f32);
5062 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5065 if (!(imm & 0x20)) return MCDisassembler::Fail;
5067 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5068 return MCDisassembler::Fail;
5069 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5070 return MCDisassembler::Fail;
5071 Inst.addOperand(MCOperand::createImm(64 - imm));
5076 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5077 uint64_t Address, const void *Decoder) {
5078 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5079 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5080 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5081 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5082 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5083 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5084 unsigned op = fieldFromInstruction(Insn, 5, 1);
5086 DecodeStatus S = MCDisassembler::Success;
5088 // VMOVv4f32 is ambiguous with these decodings.
5089 if (!(imm & 0x38) && cmode == 0xF) {
5090 if (op == 1) return MCDisassembler::Fail;
5091 Inst.setOpcode(ARM::VMOVv4f32);
5092 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5095 if (!(imm & 0x20)) return MCDisassembler::Fail;
5097 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5098 return MCDisassembler::Fail;
5099 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5100 return MCDisassembler::Fail;
5101 Inst.addOperand(MCOperand::createImm(64 - imm));
5106 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5107 uint64_t Address, const void *Decoder) {
5108 DecodeStatus S = MCDisassembler::Success;
5110 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5111 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5112 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5113 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5114 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5116 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5117 S = MCDisassembler::SoftFail;
5119 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5120 return MCDisassembler::Fail;
5121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5122 return MCDisassembler::Fail;
5123 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5124 return MCDisassembler::Fail;
5125 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5126 return MCDisassembler::Fail;
5127 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5128 return MCDisassembler::Fail;
5133 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
5134 uint64_t Address, const void *Decoder) {
5136 DecodeStatus S = MCDisassembler::Success;
5138 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5139 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5140 unsigned cop = fieldFromInstruction(Val, 8, 4);
5141 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5142 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5144 if ((cop & ~0x1) == 0xa)
5145 return MCDisassembler::Fail;
5148 S = MCDisassembler::SoftFail;
5150 Inst.addOperand(MCOperand::createImm(cop));
5151 Inst.addOperand(MCOperand::createImm(opc1));
5152 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5153 return MCDisassembler::Fail;
5154 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5155 return MCDisassembler::Fail;
5156 Inst.addOperand(MCOperand::createImm(CRm));