1 //===- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "ARMDisassembler.h"
14 #include "ARMRegisterInfo.h"
15 #include "MCTargetDesc/ARMAddressingModes.h"
16 #include "MCTargetDesc/ARMBaseInfo.h"
17 #include "llvm/MC/EDInstInfo.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCContext.h"
21 #include "llvm/Target/TargetRegistry.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
27 // Pull DecodeStatus and its enum values into the global namespace.
28 typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
29 #define Success llvm::MCDisassembler::Success
30 #define Unpredictable llvm::MCDisassembler::SoftFail
31 #define Fail llvm::MCDisassembler::Fail
33 // Helper macro to perform setwise reduction of the current running status
34 // and another status, and return if the new status is Fail.
35 #define CHECK(S,X) do { \
36 S = (DecodeStatus) ((int)S & (X)); \
37 if (S == Fail) return Fail; \
40 // Forward declare these because the autogenerated code will reference them.
41 // Definitions are further down.
42 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
43 uint64_t Address, const void *Decoder);
44 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
45 unsigned RegNo, uint64_t Address,
47 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
48 uint64_t Address, const void *Decoder);
49 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
50 uint64_t Address, const void *Decoder);
51 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
52 uint64_t Address, const void *Decoder);
53 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
54 uint64_t Address, const void *Decoder);
55 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
56 uint64_t Address, const void *Decoder);
57 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
58 uint64_t Address, const void *Decoder);
59 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
63 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
64 uint64_t Address, const void *Decoder);
66 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
67 uint64_t Address, const void *Decoder);
68 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
69 uint64_t Address, const void *Decoder);
70 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
71 uint64_t Address, const void *Decoder);
72 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
73 uint64_t Address, const void *Decoder);
74 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
75 uint64_t Address, const void *Decoder);
76 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
77 uint64_t Address, const void *Decoder);
78 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
79 uint64_t Address, const void *Decoder);
81 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
82 uint64_t Address, const void *Decoder);
83 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
84 uint64_t Address, const void *Decoder);
85 static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
89 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
90 uint64_t Address, const void *Decoder);
91 static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
92 uint64_t Address, const void *Decoder);
93 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
94 uint64_t Address, const void *Decoder);
95 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Insn,
96 uint64_t Address, const void *Decoder);
98 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst & Inst,
101 const void *Decoder);
102 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
103 uint64_t Address, const void *Decoder);
104 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
105 uint64_t Address, const void *Decoder);
106 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
107 uint64_t Address, const void *Decoder);
108 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
109 uint64_t Address, const void *Decoder);
110 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
111 uint64_t Address, const void *Decoder);
112 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
113 uint64_t Address, const void *Decoder);
114 static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
115 uint64_t Address, const void *Decoder);
116 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
117 uint64_t Address, const void *Decoder);
118 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
119 uint64_t Address, const void *Decoder);
120 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Val,
121 uint64_t Address, const void *Decoder);
122 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Val,
123 uint64_t Address, const void *Decoder);
124 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Val,
125 uint64_t Address, const void *Decoder);
126 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Val,
127 uint64_t Address, const void *Decoder);
128 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
129 uint64_t Address, const void *Decoder);
130 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
131 uint64_t Address, const void *Decoder);
132 static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
133 uint64_t Address, const void *Decoder);
134 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
135 uint64_t Address, const void *Decoder);
136 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
137 uint64_t Address, const void *Decoder);
138 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
139 uint64_t Address, const void *Decoder);
140 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
141 uint64_t Address, const void *Decoder);
142 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
143 uint64_t Address, const void *Decoder);
144 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
145 uint64_t Address, const void *Decoder);
146 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
147 uint64_t Address, const void *Decoder);
148 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
149 uint64_t Address, const void *Decoder);
150 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Insn,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Insn,
153 uint64_t Address, const void *Decoder);
154 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Insn,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
157 uint64_t Address, const void *Decoder);
158 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
183 uint64_t Address, const void *Decoder);
185 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
186 uint64_t Address, const void *Decoder);
187 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
188 uint64_t Address, const void *Decoder);
189 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
190 uint64_t Address, const void *Decoder);
191 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
192 uint64_t Address, const void *Decoder);
193 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
194 uint64_t Address, const void *Decoder);
195 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
196 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Val,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Val,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
216 uint64_t Address, const void *Decoder);
217 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
218 uint64_t Address, const void *Decoder);
219 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Insn,
220 uint64_t Address, const void *Decoder);
221 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
222 uint64_t Address, const void *Decoder);
223 static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
224 uint64_t Address, const void *Decoder);
225 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
226 uint64_t Address, const void *Decoder);
227 static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
228 uint64_t Address, const void *Decoder);
229 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
230 uint64_t Address, const void *Decoder);
231 static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Val,
232 uint64_t Address, const void *Decoder);
234 #include "ARMGenDisassemblerTables.inc"
235 #include "ARMGenInstrInfo.inc"
236 #include "ARMGenEDInfo.inc"
238 using namespace llvm;
240 static MCDisassembler *createARMDisassembler(const Target &T) {
241 return new ARMDisassembler;
244 static MCDisassembler *createThumbDisassembler(const Target &T) {
245 return new ThumbDisassembler;
248 EDInstInfo *ARMDisassembler::getEDInfo() const {
252 EDInstInfo *ThumbDisassembler::getEDInfo() const {
256 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
257 const MemoryObject &Region,
259 raw_ostream &os) const {
262 // We want to read exactly 4 bytes of data.
263 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
266 // Encoded as a small-endian 32-bit word in the stream.
267 uint32_t insn = (bytes[3] << 24) |
272 // Calling the auto-generated decoder function.
273 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this);
274 if (result != Fail) {
279 // Instructions that are shared between ARM and Thumb modes.
280 // FIXME: This shouldn't really exist. It's an artifact of the
281 // fact that we fail to encode a few instructions properly for Thumb.
283 result = decodeCommonInstruction32(MI, insn, Address, this);
284 if (result != Fail) {
289 // VFP and NEON instructions, similarly, are shared between ARM
292 result = decodeVFPInstruction32(MI, insn, Address, this);
293 if (result != Fail) {
299 result = decodeNEONDataInstruction32(MI, insn, Address, this);
300 if (result != Fail) {
302 // Add a fake predicate operand, because we share these instruction
303 // definitions with Thumb2 where these instructions are predicable.
304 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
309 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this);
310 if (result != Fail) {
312 // Add a fake predicate operand, because we share these instruction
313 // definitions with Thumb2 where these instructions are predicable.
314 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
319 result = decodeNEONDupInstruction32(MI, insn, Address, this);
320 if (result != Fail) {
322 // Add a fake predicate operand, because we share these instruction
323 // definitions with Thumb2 where these instructions are predicable.
324 if (!DecodePredicateOperand(MI, 0xE, Address, this)) return Fail;
334 extern MCInstrDesc ARMInsts[];
337 // Thumb1 instructions don't have explicit S bits. Rather, they
338 // implicitly set CPSR. Since it's not represented in the encoding, the
339 // auto-generated decoder won't inject the CPSR operand. We need to fix
340 // that as a post-pass.
341 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
342 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
343 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
344 MCInst::iterator I = MI.begin();
345 for (unsigned i = 0; i < NumOps; ++i, ++I) {
346 if (I == MI.end()) break;
347 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
348 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
349 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
354 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
357 // Most Thumb instructions don't have explicit predicates in the
358 // encoding, but rather get their predicates from IT context. We need
359 // to fix up the predicate operands using this context information as a
361 void ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
362 // A few instructions actually have predicates encoded in them. Don't
363 // try to overwrite it if we're seeing one of those.
364 switch (MI.getOpcode()) {
372 // If we're in an IT block, base the predicate on that. Otherwise,
373 // assume a predicate of AL.
375 if (!ITBlock.empty()) {
381 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
382 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
383 MCInst::iterator I = MI.begin();
384 for (unsigned i = 0; i < NumOps; ++i, ++I) {
385 if (I == MI.end()) break;
386 if (OpInfo[i].isPredicate()) {
387 I = MI.insert(I, MCOperand::CreateImm(CC));
390 MI.insert(I, MCOperand::CreateReg(0));
392 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
397 I = MI.insert(I, MCOperand::CreateImm(CC));
400 MI.insert(I, MCOperand::CreateReg(0));
402 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
405 // Thumb VFP instructions are a special case. Because we share their
406 // encodings between ARM and Thumb modes, and they are predicable in ARM
407 // mode, the auto-generated decoder will give them an (incorrect)
408 // predicate operand. We need to rewrite these operands based on the IT
409 // context as a post-pass.
410 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
412 if (!ITBlock.empty()) {
418 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
419 MCInst::iterator I = MI.begin();
420 for (unsigned i = 0, e = MI.size(); i < e; ++i, ++I) {
421 if (OpInfo[i].isPredicate() ) {
427 I->setReg(ARM::CPSR);
433 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
434 const MemoryObject &Region,
436 raw_ostream &os) const {
439 // We want to read exactly 2 bytes of data.
440 if (Region.readBytes(Address, 2, (uint8_t*)bytes, NULL) == -1)
443 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
444 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this);
445 if (result != Fail) {
447 AddThumbPredicate(MI);
452 result = decodeThumbSBitInstruction16(MI, insn16, Address, this);
455 bool InITBlock = !ITBlock.empty();
456 AddThumbPredicate(MI);
457 AddThumb1SBit(MI, InITBlock);
462 result = decodeThumb2Instruction16(MI, insn16, Address, this);
463 if (result != Fail) {
465 AddThumbPredicate(MI);
467 // If we find an IT instruction, we need to parse its condition
468 // code and mask operands so that we can apply them correctly
469 // to the subsequent instructions.
470 if (MI.getOpcode() == ARM::t2IT) {
471 unsigned firstcond = MI.getOperand(0).getImm();
472 uint32_t mask = MI.getOperand(1).getImm();
473 unsigned zeros = CountTrailingZeros_32(mask);
476 for (unsigned i = 0; i < 4 - (zeros+1); ++i) {
477 if (firstcond ^ (mask & 1))
478 ITBlock.push_back(firstcond ^ 1);
480 ITBlock.push_back(firstcond);
483 ITBlock.push_back(firstcond);
489 // We want to read exactly 4 bytes of data.
490 if (Region.readBytes(Address, 4, (uint8_t*)bytes, NULL) == -1)
493 uint32_t insn32 = (bytes[3] << 8) |
498 result = decodeThumbInstruction32(MI, insn32, Address, this);
499 if (result != Fail) {
501 bool InITBlock = ITBlock.size();
502 AddThumbPredicate(MI);
503 AddThumb1SBit(MI, InITBlock);
508 result = decodeThumb2Instruction32(MI, insn32, Address, this);
509 if (result != Fail) {
511 AddThumbPredicate(MI);
516 result = decodeCommonInstruction32(MI, insn32, Address, this);
517 if (result != Fail) {
519 AddThumbPredicate(MI);
524 result = decodeVFPInstruction32(MI, insn32, Address, this);
525 if (result != Fail) {
527 UpdateThumbVFPPredicate(MI);
532 result = decodeNEONDupInstruction32(MI, insn32, Address, this);
533 if (result != Fail) {
535 AddThumbPredicate(MI);
539 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
541 uint32_t NEONLdStInsn = insn32;
542 NEONLdStInsn &= 0xF0FFFFFF;
543 NEONLdStInsn |= 0x04000000;
544 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this);
545 if (result != Fail) {
547 AddThumbPredicate(MI);
552 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
554 uint32_t NEONDataInsn = insn32;
555 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
556 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
557 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
558 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this);
559 if (result != Fail) {
561 AddThumbPredicate(MI);
570 extern "C" void LLVMInitializeARMDisassembler() {
571 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
572 createARMDisassembler);
573 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
574 createThumbDisassembler);
577 static const unsigned GPRDecoderTable[] = {
578 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
579 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
580 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
581 ARM::R12, ARM::SP, ARM::LR, ARM::PC
584 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
585 uint64_t Address, const void *Decoder) {
589 unsigned Register = GPRDecoderTable[RegNo];
590 Inst.addOperand(MCOperand::CreateReg(Register));
595 DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
596 uint64_t Address, const void *Decoder) {
597 if (RegNo == 15) return Fail;
598 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
601 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
602 uint64_t Address, const void *Decoder) {
605 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
608 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
609 uint64_t Address, const void *Decoder) {
610 unsigned Register = 0;
634 Inst.addOperand(MCOperand::CreateReg(Register));
638 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
639 uint64_t Address, const void *Decoder) {
640 if (RegNo == 13 || RegNo == 15) return Fail;
641 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
644 static const unsigned SPRDecoderTable[] = {
645 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
646 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
647 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
648 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
649 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
650 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
651 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
652 ARM::S28, ARM::S29, ARM::S30, ARM::S31
655 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
656 uint64_t Address, const void *Decoder) {
660 unsigned Register = SPRDecoderTable[RegNo];
661 Inst.addOperand(MCOperand::CreateReg(Register));
665 static const unsigned DPRDecoderTable[] = {
666 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
667 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
668 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
669 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
670 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
671 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
672 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
673 ARM::D28, ARM::D29, ARM::D30, ARM::D31
676 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
677 uint64_t Address, const void *Decoder) {
681 unsigned Register = DPRDecoderTable[RegNo];
682 Inst.addOperand(MCOperand::CreateReg(Register));
686 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
687 uint64_t Address, const void *Decoder) {
690 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
694 DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
695 uint64_t Address, const void *Decoder) {
698 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
701 static const unsigned QPRDecoderTable[] = {
702 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
703 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
704 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
705 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
709 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
710 uint64_t Address, const void *Decoder) {
715 unsigned Register = QPRDecoderTable[RegNo];
716 Inst.addOperand(MCOperand::CreateReg(Register));
720 static DecodeStatus DecodePredicateOperand(llvm::MCInst &Inst, unsigned Val,
721 uint64_t Address, const void *Decoder) {
722 if (Val == 0xF) return Fail;
723 // AL predicate is not allowed on Thumb1 branches.
724 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
726 Inst.addOperand(MCOperand::CreateImm(Val));
727 if (Val == ARMCC::AL) {
728 Inst.addOperand(MCOperand::CreateReg(0));
730 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
734 static DecodeStatus DecodeCCOutOperand(llvm::MCInst &Inst, unsigned Val,
735 uint64_t Address, const void *Decoder) {
737 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
739 Inst.addOperand(MCOperand::CreateReg(0));
743 static DecodeStatus DecodeSOImmOperand(llvm::MCInst &Inst, unsigned Val,
744 uint64_t Address, const void *Decoder) {
745 uint32_t imm = Val & 0xFF;
746 uint32_t rot = (Val & 0xF00) >> 7;
747 uint32_t rot_imm = (imm >> rot) | (imm << (32-rot));
748 Inst.addOperand(MCOperand::CreateImm(rot_imm));
752 static DecodeStatus DecodeBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
753 uint64_t Address, const void *Decoder) {
755 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(Val)));
759 static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Val,
760 uint64_t Address, const void *Decoder) {
761 DecodeStatus S = Success;
763 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
764 unsigned type = fieldFromInstruction32(Val, 5, 2);
765 unsigned imm = fieldFromInstruction32(Val, 7, 5);
767 // Register-immediate
768 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
770 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
786 if (Shift == ARM_AM::ror && imm == 0)
789 unsigned Op = Shift | (imm << 3);
790 Inst.addOperand(MCOperand::CreateImm(Op));
795 static DecodeStatus DecodeSORegRegOperand(llvm::MCInst &Inst, unsigned Val,
796 uint64_t Address, const void *Decoder) {
797 DecodeStatus S = Success;
799 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
800 unsigned type = fieldFromInstruction32(Val, 5, 2);
801 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
804 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
805 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder));
807 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
823 Inst.addOperand(MCOperand::CreateImm(Shift));
828 static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
829 uint64_t Address, const void *Decoder) {
830 DecodeStatus S = Success;
832 // Empty register lists are not allowed.
833 if (CountPopulation_32(Val) == 0) return Fail;
834 for (unsigned i = 0; i < 16; ++i) {
835 if (Val & (1 << i)) {
836 CHECK(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder));
843 static DecodeStatus DecodeSPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
844 uint64_t Address, const void *Decoder) {
845 DecodeStatus S = Success;
847 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
848 unsigned regs = Val & 0xFF;
850 CHECK(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder));
851 for (unsigned i = 0; i < (regs - 1); ++i) {
852 CHECK(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder));
858 static DecodeStatus DecodeDPRRegListOperand(llvm::MCInst &Inst, unsigned Val,
859 uint64_t Address, const void *Decoder) {
860 DecodeStatus S = Success;
862 unsigned Vd = fieldFromInstruction32(Val, 8, 4);
863 unsigned regs = (Val & 0xFF) / 2;
865 CHECK(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder));
866 for (unsigned i = 0; i < (regs - 1); ++i) {
867 CHECK(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder));
873 static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
874 uint64_t Address, const void *Decoder) {
875 // This operand encodes a mask of contiguous zeros between a specified MSB
876 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
877 // the mask of all bits LSB-and-lower, and then xor them to create
878 // the mask of that's all ones on [msb, lsb]. Finally we not it to
879 // create the final mask.
880 unsigned msb = fieldFromInstruction32(Val, 5, 5);
881 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
882 uint32_t msb_mask = (1 << (msb+1)) - 1;
883 uint32_t lsb_mask = (1 << lsb) - 1;
884 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
888 static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
889 uint64_t Address, const void *Decoder) {
890 DecodeStatus S = Success;
892 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
893 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
894 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
895 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
896 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
897 unsigned U = fieldFromInstruction32(Insn, 23, 1);
899 switch (Inst.getOpcode()) {
900 case ARM::LDC_OFFSET:
903 case ARM::LDC_OPTION:
904 case ARM::LDCL_OFFSET:
907 case ARM::LDCL_OPTION:
908 case ARM::STC_OFFSET:
911 case ARM::STC_OPTION:
912 case ARM::STCL_OFFSET:
915 case ARM::STCL_OPTION:
916 if (coproc == 0xA || coproc == 0xB)
923 Inst.addOperand(MCOperand::CreateImm(coproc));
924 Inst.addOperand(MCOperand::CreateImm(CRd));
925 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
926 switch (Inst.getOpcode()) {
927 case ARM::LDC_OPTION:
928 case ARM::LDCL_OPTION:
929 case ARM::LDC2_OPTION:
930 case ARM::LDC2L_OPTION:
931 case ARM::STC_OPTION:
932 case ARM::STCL_OPTION:
933 case ARM::STC2_OPTION:
934 case ARM::STC2L_OPTION:
937 case ARM::LDC2L_POST:
938 case ARM::STC2L_POST:
941 Inst.addOperand(MCOperand::CreateReg(0));
945 unsigned P = fieldFromInstruction32(Insn, 24, 1);
946 unsigned W = fieldFromInstruction32(Insn, 21, 1);
948 bool writeback = (P == 0) || (W == 1);
949 unsigned idx_mode = 0;
951 idx_mode = ARMII::IndexModePre;
952 else if (!P && writeback)
953 idx_mode = ARMII::IndexModePost;
955 switch (Inst.getOpcode()) {
958 case ARM::LDC2L_POST:
959 case ARM::STC2L_POST:
961 case ARM::LDC_OPTION:
962 case ARM::LDCL_OPTION:
963 case ARM::LDC2_OPTION:
964 case ARM::LDC2L_OPTION:
965 case ARM::STC_OPTION:
966 case ARM::STCL_OPTION:
967 case ARM::STC2_OPTION:
968 case ARM::STC2L_OPTION:
969 Inst.addOperand(MCOperand::CreateImm(imm));
973 Inst.addOperand(MCOperand::CreateImm(
974 ARM_AM::getAM2Opc(ARM_AM::add, imm, ARM_AM::lsl, idx_mode)));
976 Inst.addOperand(MCOperand::CreateImm(
977 ARM_AM::getAM2Opc(ARM_AM::sub, imm, ARM_AM::lsl, idx_mode)));
981 switch (Inst.getOpcode()) {
982 case ARM::LDC_OFFSET:
985 case ARM::LDC_OPTION:
986 case ARM::LDCL_OFFSET:
989 case ARM::LDCL_OPTION:
990 case ARM::STC_OFFSET:
993 case ARM::STC_OPTION:
994 case ARM::STCL_OFFSET:
997 case ARM::STCL_OPTION:
998 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1008 DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
1009 uint64_t Address, const void *Decoder) {
1010 DecodeStatus S = Success;
1012 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1013 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1014 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1015 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1016 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1017 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1018 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1019 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1021 // On stores, the writeback operand precedes Rt.
1022 switch (Inst.getOpcode()) {
1023 case ARM::STR_POST_IMM:
1024 case ARM::STR_POST_REG:
1025 case ARM::STRB_POST_IMM:
1026 case ARM::STRB_POST_REG:
1027 case ARM::STRT_POST_REG:
1028 case ARM::STRT_POST_IMM:
1029 case ARM::STRBT_POST_REG:
1030 case ARM::STRBT_POST_IMM:
1031 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1037 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1039 // On loads, the writeback operand comes after Rt.
1040 switch (Inst.getOpcode()) {
1041 case ARM::LDR_POST_IMM:
1042 case ARM::LDR_POST_REG:
1043 case ARM::LDRB_POST_IMM:
1044 case ARM::LDRB_POST_REG:
1047 case ARM::LDRBT_POST_REG:
1048 case ARM::LDRBT_POST_IMM:
1049 case ARM::LDRT_POST_REG:
1050 case ARM::LDRT_POST_IMM:
1051 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1057 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1059 ARM_AM::AddrOpc Op = ARM_AM::add;
1060 if (!fieldFromInstruction32(Insn, 23, 1))
1063 bool writeback = (P == 0) || (W == 1);
1064 unsigned idx_mode = 0;
1066 idx_mode = ARMII::IndexModePre;
1067 else if (!P && writeback)
1068 idx_mode = ARMII::IndexModePost;
1070 if (writeback && (Rn == 15 || Rn == Rt)) S = Unpredictable; // UNPREDICTABLE
1073 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1074 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1075 switch( fieldFromInstruction32(Insn, 5, 2)) {
1091 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1092 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1094 Inst.addOperand(MCOperand::CreateImm(imm));
1096 Inst.addOperand(MCOperand::CreateReg(0));
1097 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1098 Inst.addOperand(MCOperand::CreateImm(tmp));
1101 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1106 static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
1107 uint64_t Address, const void *Decoder) {
1108 DecodeStatus S = Success;
1110 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1111 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1112 unsigned type = fieldFromInstruction32(Val, 5, 2);
1113 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1114 unsigned U = fieldFromInstruction32(Val, 12, 1);
1116 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1132 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1133 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1136 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1138 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1139 Inst.addOperand(MCOperand::CreateImm(shift));
1145 DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
1146 uint64_t Address, const void *Decoder) {
1147 DecodeStatus S = Success;
1149 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1150 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1151 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1152 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1153 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1154 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1155 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1156 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1157 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1159 bool writeback = (W == 1) | (P == 0);
1161 // For {LD,ST}RD, Rt must be even, else undefined.
1162 switch (Inst.getOpcode()) {
1165 case ARM::STRD_POST:
1168 case ARM::LDRD_POST:
1169 if (Rt & 0x1) return Fail;
1175 if (writeback) { // Writeback
1177 U |= ARMII::IndexModePre << 9;
1179 U |= ARMII::IndexModePost << 9;
1181 // On stores, the writeback operand precedes Rt.
1182 switch (Inst.getOpcode()) {
1185 case ARM::STRD_POST:
1188 case ARM::STRH_POST:
1189 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1196 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
1197 switch (Inst.getOpcode()) {
1200 case ARM::STRD_POST:
1203 case ARM::LDRD_POST:
1204 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
1211 // On loads, the writeback operand comes after Rt.
1212 switch (Inst.getOpcode()) {
1215 case ARM::LDRD_POST:
1218 case ARM::LDRH_POST:
1220 case ARM::LDRSH_PRE:
1221 case ARM::LDRSH_POST:
1223 case ARM::LDRSB_PRE:
1224 case ARM::LDRSB_POST:
1227 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1234 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1237 Inst.addOperand(MCOperand::CreateReg(0));
1238 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1240 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1241 Inst.addOperand(MCOperand::CreateImm(U));
1244 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1249 static DecodeStatus DecodeRFEInstruction(llvm::MCInst &Inst, unsigned Insn,
1250 uint64_t Address, const void *Decoder) {
1251 DecodeStatus S = Success;
1253 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1254 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1271 Inst.addOperand(MCOperand::CreateImm(mode));
1272 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1277 static DecodeStatus DecodeMemMultipleWritebackInstruction(llvm::MCInst &Inst,
1279 uint64_t Address, const void *Decoder) {
1280 DecodeStatus S = Success;
1282 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1283 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1284 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1287 switch (Inst.getOpcode()) {
1289 Inst.setOpcode(ARM::RFEDA);
1291 case ARM::LDMDA_UPD:
1292 Inst.setOpcode(ARM::RFEDA_UPD);
1295 Inst.setOpcode(ARM::RFEDB);
1297 case ARM::LDMDB_UPD:
1298 Inst.setOpcode(ARM::RFEDB_UPD);
1301 Inst.setOpcode(ARM::RFEIA);
1303 case ARM::LDMIA_UPD:
1304 Inst.setOpcode(ARM::RFEIA_UPD);
1307 Inst.setOpcode(ARM::RFEIB);
1309 case ARM::LDMIB_UPD:
1310 Inst.setOpcode(ARM::RFEIB_UPD);
1313 Inst.setOpcode(ARM::SRSDA);
1315 case ARM::STMDA_UPD:
1316 Inst.setOpcode(ARM::SRSDA_UPD);
1319 Inst.setOpcode(ARM::SRSDB);
1321 case ARM::STMDB_UPD:
1322 Inst.setOpcode(ARM::SRSDB_UPD);
1325 Inst.setOpcode(ARM::SRSIA);
1327 case ARM::STMIA_UPD:
1328 Inst.setOpcode(ARM::SRSIA_UPD);
1331 Inst.setOpcode(ARM::SRSIB);
1333 case ARM::STMIB_UPD:
1334 Inst.setOpcode(ARM::SRSIB_UPD);
1340 // For stores (which become SRS's, the only operand is the mode.
1341 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1343 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1347 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1350 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1351 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)); // Tied
1352 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1353 CHECK(S, DecodeRegListOperand(Inst, reglist, Address, Decoder));
1358 static DecodeStatus DecodeCPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1359 uint64_t Address, const void *Decoder) {
1360 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1361 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1362 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1363 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1365 DecodeStatus S = Success;
1367 // imod == '01' --> UNPREDICTABLE
1368 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1369 // return failure here. The '01' imod value is unprintable, so there's
1370 // nothing useful we could do even if we returned UNPREDICTABLE.
1372 if (imod == 1) CHECK(S, Fail);
1375 Inst.setOpcode(ARM::CPS3p);
1376 Inst.addOperand(MCOperand::CreateImm(imod));
1377 Inst.addOperand(MCOperand::CreateImm(iflags));
1378 Inst.addOperand(MCOperand::CreateImm(mode));
1379 } else if (imod && !M) {
1380 Inst.setOpcode(ARM::CPS2p);
1381 Inst.addOperand(MCOperand::CreateImm(imod));
1382 Inst.addOperand(MCOperand::CreateImm(iflags));
1383 if (mode) CHECK(S, Unpredictable);
1384 } else if (!imod && M) {
1385 Inst.setOpcode(ARM::CPS1p);
1386 Inst.addOperand(MCOperand::CreateImm(mode));
1387 if (iflags) CHECK(S, Unpredictable);
1389 // imod == '00' && M == '0' --> UNPREDICTABLE
1390 Inst.setOpcode(ARM::CPS1p);
1391 Inst.addOperand(MCOperand::CreateImm(mode));
1392 CHECK(S, Unpredictable);
1398 static DecodeStatus DecodeT2CPSInstruction(llvm::MCInst &Inst, unsigned Insn,
1399 uint64_t Address, const void *Decoder) {
1400 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1401 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1402 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1403 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1405 DecodeStatus S = Success;
1407 // imod == '01' --> UNPREDICTABLE
1408 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1409 // return failure here. The '01' imod value is unprintable, so there's
1410 // nothing useful we could do even if we returned UNPREDICTABLE.
1412 if (imod == 1) CHECK(S, Fail);
1415 Inst.setOpcode(ARM::t2CPS3p);
1416 Inst.addOperand(MCOperand::CreateImm(imod));
1417 Inst.addOperand(MCOperand::CreateImm(iflags));
1418 Inst.addOperand(MCOperand::CreateImm(mode));
1419 } else if (imod && !M) {
1420 Inst.setOpcode(ARM::t2CPS2p);
1421 Inst.addOperand(MCOperand::CreateImm(imod));
1422 Inst.addOperand(MCOperand::CreateImm(iflags));
1423 if (mode) CHECK(S, Unpredictable);
1424 } else if (!imod && M) {
1425 Inst.setOpcode(ARM::t2CPS1p);
1426 Inst.addOperand(MCOperand::CreateImm(mode));
1427 if (iflags) CHECK(S, Unpredictable);
1429 // imod == '00' && M == '0' --> UNPREDICTABLE
1430 Inst.setOpcode(ARM::t2CPS1p);
1431 Inst.addOperand(MCOperand::CreateImm(mode));
1432 CHECK(S, Unpredictable);
1439 static DecodeStatus DecodeSMLAInstruction(llvm::MCInst &Inst, unsigned Insn,
1440 uint64_t Address, const void *Decoder) {
1441 DecodeStatus S = Success;
1443 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
1444 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
1445 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
1446 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
1447 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1450 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1452 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder));
1453 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder));
1454 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder));
1455 CHECK(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder));
1457 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1462 static DecodeStatus DecodeAddrModeImm12Operand(llvm::MCInst &Inst, unsigned Val,
1463 uint64_t Address, const void *Decoder) {
1464 DecodeStatus S = Success;
1466 unsigned add = fieldFromInstruction32(Val, 12, 1);
1467 unsigned imm = fieldFromInstruction32(Val, 0, 12);
1468 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1470 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1472 if (!add) imm *= -1;
1473 if (imm == 0 && !add) imm = INT32_MIN;
1474 Inst.addOperand(MCOperand::CreateImm(imm));
1479 static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
1480 uint64_t Address, const void *Decoder) {
1481 DecodeStatus S = Success;
1483 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
1484 unsigned U = fieldFromInstruction32(Val, 8, 1);
1485 unsigned imm = fieldFromInstruction32(Val, 0, 8);
1487 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
1490 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
1492 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
1497 static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
1498 uint64_t Address, const void *Decoder) {
1499 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
1503 DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
1504 uint64_t Address, const void *Decoder) {
1505 DecodeStatus S = Success;
1507 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1508 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
1511 Inst.setOpcode(ARM::BLXi);
1512 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
1513 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1517 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
1518 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
1524 static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
1525 uint64_t Address, const void *Decoder) {
1526 Inst.addOperand(MCOperand::CreateImm(64 - Val));
1530 static DecodeStatus DecodeAddrMode6Operand(llvm::MCInst &Inst, unsigned Val,
1531 uint64_t Address, const void *Decoder) {
1532 DecodeStatus S = Success;
1534 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1535 unsigned align = fieldFromInstruction32(Val, 4, 2);
1537 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1539 Inst.addOperand(MCOperand::CreateImm(0));
1541 Inst.addOperand(MCOperand::CreateImm(4 << align));
1546 static DecodeStatus DecodeVLDInstruction(llvm::MCInst &Inst, unsigned Insn,
1547 uint64_t Address, const void *Decoder) {
1548 DecodeStatus S = Success;
1550 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1551 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1552 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1553 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1554 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1555 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1557 // First output register
1558 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1560 // Second output register
1561 switch (Inst.getOpcode()) {
1566 case ARM::VLD1q8_UPD:
1567 case ARM::VLD1q16_UPD:
1568 case ARM::VLD1q32_UPD:
1569 case ARM::VLD1q64_UPD:
1574 case ARM::VLD1d8T_UPD:
1575 case ARM::VLD1d16T_UPD:
1576 case ARM::VLD1d32T_UPD:
1577 case ARM::VLD1d64T_UPD:
1582 case ARM::VLD1d8Q_UPD:
1583 case ARM::VLD1d16Q_UPD:
1584 case ARM::VLD1d32Q_UPD:
1585 case ARM::VLD1d64Q_UPD:
1589 case ARM::VLD2d8_UPD:
1590 case ARM::VLD2d16_UPD:
1591 case ARM::VLD2d32_UPD:
1595 case ARM::VLD2q8_UPD:
1596 case ARM::VLD2q16_UPD:
1597 case ARM::VLD2q32_UPD:
1601 case ARM::VLD3d8_UPD:
1602 case ARM::VLD3d16_UPD:
1603 case ARM::VLD3d32_UPD:
1607 case ARM::VLD4d8_UPD:
1608 case ARM::VLD4d16_UPD:
1609 case ARM::VLD4d32_UPD:
1610 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1615 case ARM::VLD2b8_UPD:
1616 case ARM::VLD2b16_UPD:
1617 case ARM::VLD2b32_UPD:
1621 case ARM::VLD3q8_UPD:
1622 case ARM::VLD3q16_UPD:
1623 case ARM::VLD3q32_UPD:
1627 case ARM::VLD4q8_UPD:
1628 case ARM::VLD4q16_UPD:
1629 case ARM::VLD4q32_UPD:
1630 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1635 // Third output register
1636 switch(Inst.getOpcode()) {
1641 case ARM::VLD1d8T_UPD:
1642 case ARM::VLD1d16T_UPD:
1643 case ARM::VLD1d32T_UPD:
1644 case ARM::VLD1d64T_UPD:
1649 case ARM::VLD1d8Q_UPD:
1650 case ARM::VLD1d16Q_UPD:
1651 case ARM::VLD1d32Q_UPD:
1652 case ARM::VLD1d64Q_UPD:
1656 case ARM::VLD2q8_UPD:
1657 case ARM::VLD2q16_UPD:
1658 case ARM::VLD2q32_UPD:
1662 case ARM::VLD3d8_UPD:
1663 case ARM::VLD3d16_UPD:
1664 case ARM::VLD3d32_UPD:
1668 case ARM::VLD4d8_UPD:
1669 case ARM::VLD4d16_UPD:
1670 case ARM::VLD4d32_UPD:
1671 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1676 case ARM::VLD3q8_UPD:
1677 case ARM::VLD3q16_UPD:
1678 case ARM::VLD3q32_UPD:
1682 case ARM::VLD4q8_UPD:
1683 case ARM::VLD4q16_UPD:
1684 case ARM::VLD4q32_UPD:
1685 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1691 // Fourth output register
1692 switch (Inst.getOpcode()) {
1697 case ARM::VLD1d8Q_UPD:
1698 case ARM::VLD1d16Q_UPD:
1699 case ARM::VLD1d32Q_UPD:
1700 case ARM::VLD1d64Q_UPD:
1704 case ARM::VLD2q8_UPD:
1705 case ARM::VLD2q16_UPD:
1706 case ARM::VLD2q32_UPD:
1710 case ARM::VLD4d8_UPD:
1711 case ARM::VLD4d16_UPD:
1712 case ARM::VLD4d32_UPD:
1713 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
1718 case ARM::VLD4q8_UPD:
1719 case ARM::VLD4q16_UPD:
1720 case ARM::VLD4q32_UPD:
1721 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
1727 // Writeback operand
1728 switch (Inst.getOpcode()) {
1729 case ARM::VLD1d8_UPD:
1730 case ARM::VLD1d16_UPD:
1731 case ARM::VLD1d32_UPD:
1732 case ARM::VLD1d64_UPD:
1733 case ARM::VLD1q8_UPD:
1734 case ARM::VLD1q16_UPD:
1735 case ARM::VLD1q32_UPD:
1736 case ARM::VLD1q64_UPD:
1737 case ARM::VLD1d8T_UPD:
1738 case ARM::VLD1d16T_UPD:
1739 case ARM::VLD1d32T_UPD:
1740 case ARM::VLD1d64T_UPD:
1741 case ARM::VLD1d8Q_UPD:
1742 case ARM::VLD1d16Q_UPD:
1743 case ARM::VLD1d32Q_UPD:
1744 case ARM::VLD1d64Q_UPD:
1745 case ARM::VLD2d8_UPD:
1746 case ARM::VLD2d16_UPD:
1747 case ARM::VLD2d32_UPD:
1748 case ARM::VLD2q8_UPD:
1749 case ARM::VLD2q16_UPD:
1750 case ARM::VLD2q32_UPD:
1751 case ARM::VLD2b8_UPD:
1752 case ARM::VLD2b16_UPD:
1753 case ARM::VLD2b32_UPD:
1754 case ARM::VLD3d8_UPD:
1755 case ARM::VLD3d16_UPD:
1756 case ARM::VLD3d32_UPD:
1757 case ARM::VLD3q8_UPD:
1758 case ARM::VLD3q16_UPD:
1759 case ARM::VLD3q32_UPD:
1760 case ARM::VLD4d8_UPD:
1761 case ARM::VLD4d16_UPD:
1762 case ARM::VLD4d32_UPD:
1763 case ARM::VLD4q8_UPD:
1764 case ARM::VLD4q16_UPD:
1765 case ARM::VLD4q32_UPD:
1766 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1772 // AddrMode6 Base (register+alignment)
1773 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1775 // AddrMode6 Offset (register)
1777 Inst.addOperand(MCOperand::CreateReg(0));
1778 else if (Rm != 0xF) {
1779 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1785 static DecodeStatus DecodeVSTInstruction(llvm::MCInst &Inst, unsigned Insn,
1786 uint64_t Address, const void *Decoder) {
1787 DecodeStatus S = Success;
1789 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1790 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
1791 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
1792 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1793 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
1794 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1796 // Writeback Operand
1797 switch (Inst.getOpcode()) {
1798 case ARM::VST1d8_UPD:
1799 case ARM::VST1d16_UPD:
1800 case ARM::VST1d32_UPD:
1801 case ARM::VST1d64_UPD:
1802 case ARM::VST1q8_UPD:
1803 case ARM::VST1q16_UPD:
1804 case ARM::VST1q32_UPD:
1805 case ARM::VST1q64_UPD:
1806 case ARM::VST1d8T_UPD:
1807 case ARM::VST1d16T_UPD:
1808 case ARM::VST1d32T_UPD:
1809 case ARM::VST1d64T_UPD:
1810 case ARM::VST1d8Q_UPD:
1811 case ARM::VST1d16Q_UPD:
1812 case ARM::VST1d32Q_UPD:
1813 case ARM::VST1d64Q_UPD:
1814 case ARM::VST2d8_UPD:
1815 case ARM::VST2d16_UPD:
1816 case ARM::VST2d32_UPD:
1817 case ARM::VST2q8_UPD:
1818 case ARM::VST2q16_UPD:
1819 case ARM::VST2q32_UPD:
1820 case ARM::VST2b8_UPD:
1821 case ARM::VST2b16_UPD:
1822 case ARM::VST2b32_UPD:
1823 case ARM::VST3d8_UPD:
1824 case ARM::VST3d16_UPD:
1825 case ARM::VST3d32_UPD:
1826 case ARM::VST3q8_UPD:
1827 case ARM::VST3q16_UPD:
1828 case ARM::VST3q32_UPD:
1829 case ARM::VST4d8_UPD:
1830 case ARM::VST4d16_UPD:
1831 case ARM::VST4d32_UPD:
1832 case ARM::VST4q8_UPD:
1833 case ARM::VST4q16_UPD:
1834 case ARM::VST4q32_UPD:
1835 CHECK(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder));
1841 // AddrMode6 Base (register+alignment)
1842 CHECK(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder));
1844 // AddrMode6 Offset (register)
1846 Inst.addOperand(MCOperand::CreateReg(0));
1847 else if (Rm != 0xF) {
1848 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
1851 // First input register
1852 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
1854 // Second input register
1855 switch (Inst.getOpcode()) {
1860 case ARM::VST1q8_UPD:
1861 case ARM::VST1q16_UPD:
1862 case ARM::VST1q32_UPD:
1863 case ARM::VST1q64_UPD:
1868 case ARM::VST1d8T_UPD:
1869 case ARM::VST1d16T_UPD:
1870 case ARM::VST1d32T_UPD:
1871 case ARM::VST1d64T_UPD:
1876 case ARM::VST1d8Q_UPD:
1877 case ARM::VST1d16Q_UPD:
1878 case ARM::VST1d32Q_UPD:
1879 case ARM::VST1d64Q_UPD:
1883 case ARM::VST2d8_UPD:
1884 case ARM::VST2d16_UPD:
1885 case ARM::VST2d32_UPD:
1889 case ARM::VST2q8_UPD:
1890 case ARM::VST2q16_UPD:
1891 case ARM::VST2q32_UPD:
1895 case ARM::VST3d8_UPD:
1896 case ARM::VST3d16_UPD:
1897 case ARM::VST3d32_UPD:
1901 case ARM::VST4d8_UPD:
1902 case ARM::VST4d16_UPD:
1903 case ARM::VST4d32_UPD:
1904 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
1909 case ARM::VST2b8_UPD:
1910 case ARM::VST2b16_UPD:
1911 case ARM::VST2b32_UPD:
1915 case ARM::VST3q8_UPD:
1916 case ARM::VST3q16_UPD:
1917 case ARM::VST3q32_UPD:
1921 case ARM::VST4q8_UPD:
1922 case ARM::VST4q16_UPD:
1923 case ARM::VST4q32_UPD:
1924 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1930 // Third input register
1931 switch (Inst.getOpcode()) {
1936 case ARM::VST1d8T_UPD:
1937 case ARM::VST1d16T_UPD:
1938 case ARM::VST1d32T_UPD:
1939 case ARM::VST1d64T_UPD:
1944 case ARM::VST1d8Q_UPD:
1945 case ARM::VST1d16Q_UPD:
1946 case ARM::VST1d32Q_UPD:
1947 case ARM::VST1d64Q_UPD:
1951 case ARM::VST2q8_UPD:
1952 case ARM::VST2q16_UPD:
1953 case ARM::VST2q32_UPD:
1957 case ARM::VST3d8_UPD:
1958 case ARM::VST3d16_UPD:
1959 case ARM::VST3d32_UPD:
1963 case ARM::VST4d8_UPD:
1964 case ARM::VST4d16_UPD:
1965 case ARM::VST4d32_UPD:
1966 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder));
1971 case ARM::VST3q8_UPD:
1972 case ARM::VST3q16_UPD:
1973 case ARM::VST3q32_UPD:
1977 case ARM::VST4q8_UPD:
1978 case ARM::VST4q16_UPD:
1979 case ARM::VST4q32_UPD:
1980 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder));
1986 // Fourth input register
1987 switch (Inst.getOpcode()) {
1992 case ARM::VST1d8Q_UPD:
1993 case ARM::VST1d16Q_UPD:
1994 case ARM::VST1d32Q_UPD:
1995 case ARM::VST1d64Q_UPD:
1999 case ARM::VST2q8_UPD:
2000 case ARM::VST2q16_UPD:
2001 case ARM::VST2q32_UPD:
2005 case ARM::VST4d8_UPD:
2006 case ARM::VST4d16_UPD:
2007 case ARM::VST4d32_UPD:
2008 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder));
2013 case ARM::VST4q8_UPD:
2014 case ARM::VST4q16_UPD:
2015 case ARM::VST4q32_UPD:
2016 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder));
2025 static DecodeStatus DecodeVLD1DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2026 uint64_t Address, const void *Decoder) {
2027 DecodeStatus S = Success;
2029 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2030 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2031 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2032 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2033 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2034 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2035 unsigned regs = fieldFromInstruction32(Insn, 5, 1) + 1;
2037 align *= (1 << size);
2039 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2041 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder));
2044 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2047 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2048 Inst.addOperand(MCOperand::CreateImm(align));
2051 Inst.addOperand(MCOperand::CreateReg(0));
2052 else if (Rm != 0xF) {
2053 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2059 static DecodeStatus DecodeVLD2DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2060 uint64_t Address, const void *Decoder) {
2061 DecodeStatus S = Success;
2063 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2064 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2065 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2066 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2067 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2068 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2069 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2072 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2073 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2075 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2078 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2079 Inst.addOperand(MCOperand::CreateImm(align));
2082 Inst.addOperand(MCOperand::CreateReg(0));
2083 else if (Rm != 0xF) {
2084 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2090 static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2091 uint64_t Address, const void *Decoder) {
2092 DecodeStatus S = Success;
2094 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2095 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2096 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2097 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2098 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2100 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2101 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2102 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2104 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2107 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2108 Inst.addOperand(MCOperand::CreateImm(0));
2111 Inst.addOperand(MCOperand::CreateReg(0));
2112 else if (Rm != 0xF) {
2113 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2119 static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
2120 uint64_t Address, const void *Decoder) {
2121 DecodeStatus S = Success;
2123 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2124 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2125 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2126 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2127 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2128 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2129 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2144 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2145 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder));
2146 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder));
2147 CHECK(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder));
2149 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2152 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2153 Inst.addOperand(MCOperand::CreateImm(align));
2156 Inst.addOperand(MCOperand::CreateReg(0));
2157 else if (Rm != 0xF) {
2158 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2165 DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
2166 uint64_t Address, const void *Decoder) {
2167 DecodeStatus S = Success;
2169 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2170 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2171 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2172 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2173 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2174 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2175 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2176 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2179 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2181 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2184 Inst.addOperand(MCOperand::CreateImm(imm));
2186 switch (Inst.getOpcode()) {
2187 case ARM::VORRiv4i16:
2188 case ARM::VORRiv2i32:
2189 case ARM::VBICiv4i16:
2190 case ARM::VBICiv2i32:
2191 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2193 case ARM::VORRiv8i16:
2194 case ARM::VORRiv4i32:
2195 case ARM::VBICiv8i16:
2196 case ARM::VBICiv4i32:
2197 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2206 static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Insn,
2207 uint64_t Address, const void *Decoder) {
2208 DecodeStatus S = Success;
2210 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2211 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2212 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2213 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2214 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2216 CHECK(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder));
2217 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2218 Inst.addOperand(MCOperand::CreateImm(8 << size));
2223 static DecodeStatus DecodeShiftRight8Imm(llvm::MCInst &Inst, unsigned Val,
2224 uint64_t Address, const void *Decoder) {
2225 Inst.addOperand(MCOperand::CreateImm(8 - Val));
2229 static DecodeStatus DecodeShiftRight16Imm(llvm::MCInst &Inst, unsigned Val,
2230 uint64_t Address, const void *Decoder) {
2231 Inst.addOperand(MCOperand::CreateImm(16 - Val));
2235 static DecodeStatus DecodeShiftRight32Imm(llvm::MCInst &Inst, unsigned Val,
2236 uint64_t Address, const void *Decoder) {
2237 Inst.addOperand(MCOperand::CreateImm(32 - Val));
2241 static DecodeStatus DecodeShiftRight64Imm(llvm::MCInst &Inst, unsigned Val,
2242 uint64_t Address, const void *Decoder) {
2243 Inst.addOperand(MCOperand::CreateImm(64 - Val));
2247 static DecodeStatus DecodeTBLInstruction(llvm::MCInst &Inst, unsigned Insn,
2248 uint64_t Address, const void *Decoder) {
2249 DecodeStatus S = Success;
2251 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2252 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2253 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2254 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2255 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2256 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2257 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2258 unsigned length = fieldFromInstruction32(Insn, 8, 2) + 1;
2260 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2262 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)); // Writeback
2265 for (unsigned i = 0; i < length; ++i) {
2266 CHECK(S, DecodeDPRRegisterClass(Inst, (Rn+i)%32, Address, Decoder));
2269 CHECK(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder));
2274 static DecodeStatus DecodeVFPfpImm(llvm::MCInst &Inst, unsigned Val,
2275 uint64_t Address, const void *Decoder) {
2276 // The immediate needs to be a fully instantiated float. However, the
2277 // auto-generated decoder is only able to fill in some of the bits
2278 // necessary. For instance, the 'b' bit is replicated multiple times,
2279 // and is even present in inverted form in one bit. We do a little
2280 // binary parsing here to fill in those missing bits, and then
2281 // reinterpret it all as a float.
2287 fp_conv.integer = Val;
2288 uint32_t b = fieldFromInstruction32(Val, 25, 1);
2289 fp_conv.integer |= b << 26;
2290 fp_conv.integer |= b << 27;
2291 fp_conv.integer |= b << 28;
2292 fp_conv.integer |= b << 29;
2293 fp_conv.integer |= (~b & 0x1) << 30;
2295 Inst.addOperand(MCOperand::CreateFPImm(fp_conv.fp));
2299 static DecodeStatus DecodeThumbAddSpecialReg(llvm::MCInst &Inst, uint16_t Insn,
2300 uint64_t Address, const void *Decoder) {
2301 DecodeStatus S = Success;
2303 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2304 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
2306 CHECK(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder));
2308 if (Inst.getOpcode() == ARM::tADR)
2309 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2310 else if (Inst.getOpcode() == ARM::tADDrSPi)
2311 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2315 Inst.addOperand(MCOperand::CreateImm(imm));
2319 static DecodeStatus DecodeThumbBROperand(llvm::MCInst &Inst, unsigned Val,
2320 uint64_t Address, const void *Decoder) {
2321 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
2325 static DecodeStatus DecodeT2BROperand(llvm::MCInst &Inst, unsigned Val,
2326 uint64_t Address, const void *Decoder) {
2327 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
2331 static DecodeStatus DecodeThumbCmpBROperand(llvm::MCInst &Inst, unsigned Val,
2332 uint64_t Address, const void *Decoder) {
2333 Inst.addOperand(MCOperand::CreateImm(SignExtend32<7>(Val << 1)));
2337 static DecodeStatus DecodeThumbAddrModeRR(llvm::MCInst &Inst, unsigned Val,
2338 uint64_t Address, const void *Decoder) {
2339 DecodeStatus S = Success;
2341 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2342 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
2344 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2345 CHECK(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder));
2350 static DecodeStatus DecodeThumbAddrModeIS(llvm::MCInst &Inst, unsigned Val,
2351 uint64_t Address, const void *Decoder) {
2352 DecodeStatus S = Success;
2354 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
2355 unsigned imm = fieldFromInstruction32(Val, 3, 5);
2357 CHECK(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder));
2358 Inst.addOperand(MCOperand::CreateImm(imm));
2363 static DecodeStatus DecodeThumbAddrModePC(llvm::MCInst &Inst, unsigned Val,
2364 uint64_t Address, const void *Decoder) {
2365 Inst.addOperand(MCOperand::CreateImm(Val << 2));
2370 static DecodeStatus DecodeThumbAddrModeSP(llvm::MCInst &Inst, unsigned Val,
2371 uint64_t Address, const void *Decoder) {
2372 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2373 Inst.addOperand(MCOperand::CreateImm(Val));
2378 static DecodeStatus DecodeT2AddrModeSOReg(llvm::MCInst &Inst, unsigned Val,
2379 uint64_t Address, const void *Decoder) {
2380 DecodeStatus S = Success;
2382 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
2383 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
2384 unsigned imm = fieldFromInstruction32(Val, 0, 2);
2386 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2387 CHECK(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder));
2388 Inst.addOperand(MCOperand::CreateImm(imm));
2393 static DecodeStatus DecodeT2LoadShift(llvm::MCInst &Inst, unsigned Insn,
2394 uint64_t Address, const void *Decoder) {
2395 DecodeStatus S = Success;
2397 switch (Inst.getOpcode()) {
2403 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2404 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2408 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2410 switch (Inst.getOpcode()) {
2412 Inst.setOpcode(ARM::t2LDRBpci);
2415 Inst.setOpcode(ARM::t2LDRHpci);
2418 Inst.setOpcode(ARM::t2LDRSHpci);
2421 Inst.setOpcode(ARM::t2LDRSBpci);
2424 Inst.setOpcode(ARM::t2PLDi12);
2425 Inst.addOperand(MCOperand::CreateReg(ARM::PC));
2431 int imm = fieldFromInstruction32(Insn, 0, 12);
2432 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
2433 Inst.addOperand(MCOperand::CreateImm(imm));
2438 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
2439 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
2440 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
2441 CHECK(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder));
2446 static DecodeStatus DecodeT2Imm8S4(llvm::MCInst &Inst, unsigned Val,
2447 uint64_t Address, const void *Decoder) {
2448 int imm = Val & 0xFF;
2449 if (!(Val & 0x100)) imm *= -1;
2450 Inst.addOperand(MCOperand::CreateImm(imm << 2));
2455 static DecodeStatus DecodeT2AddrModeImm8s4(llvm::MCInst &Inst, unsigned Val,
2456 uint64_t Address, const void *Decoder) {
2457 DecodeStatus S = Success;
2459 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2460 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2462 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2463 CHECK(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder));
2468 static DecodeStatus DecodeT2Imm8(llvm::MCInst &Inst, unsigned Val,
2469 uint64_t Address, const void *Decoder) {
2470 int imm = Val & 0xFF;
2471 if (!(Val & 0x100)) imm *= -1;
2472 Inst.addOperand(MCOperand::CreateImm(imm));
2478 static DecodeStatus DecodeT2AddrModeImm8(llvm::MCInst &Inst, unsigned Val,
2479 uint64_t Address, const void *Decoder) {
2480 DecodeStatus S = Success;
2482 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2483 unsigned imm = fieldFromInstruction32(Val, 0, 9);
2485 // Some instructions always use an additive offset.
2486 switch (Inst.getOpcode()) {
2498 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2499 CHECK(S, DecodeT2Imm8(Inst, imm, Address, Decoder));
2505 static DecodeStatus DecodeT2AddrModeImm12(llvm::MCInst &Inst, unsigned Val,
2506 uint64_t Address, const void *Decoder) {
2507 DecodeStatus S = Success;
2509 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2510 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2512 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2513 Inst.addOperand(MCOperand::CreateImm(imm));
2519 static DecodeStatus DecodeThumbAddSPImm(llvm::MCInst &Inst, uint16_t Insn,
2520 uint64_t Address, const void *Decoder) {
2521 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
2523 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2524 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2525 Inst.addOperand(MCOperand::CreateImm(imm));
2530 static DecodeStatus DecodeThumbAddSPReg(llvm::MCInst &Inst, uint16_t Insn,
2531 uint64_t Address, const void *Decoder) {
2532 DecodeStatus S = Success;
2534 if (Inst.getOpcode() == ARM::tADDrSP) {
2535 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
2536 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
2538 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2539 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2540 CHECK(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder));
2541 } else if (Inst.getOpcode() == ARM::tADDspr) {
2542 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
2544 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2545 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
2546 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2552 static DecodeStatus DecodeThumbCPS(llvm::MCInst &Inst, uint16_t Insn,
2553 uint64_t Address, const void *Decoder) {
2554 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
2555 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
2557 Inst.addOperand(MCOperand::CreateImm(imod));
2558 Inst.addOperand(MCOperand::CreateImm(flags));
2563 static DecodeStatus DecodePostIdxReg(llvm::MCInst &Inst, unsigned Insn,
2564 uint64_t Address, const void *Decoder) {
2565 DecodeStatus S = Success;
2566 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2567 unsigned add = fieldFromInstruction32(Insn, 4, 1);
2569 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)) ;
2570 Inst.addOperand(MCOperand::CreateImm(add));
2575 static DecodeStatus DecodeThumbBLXOffset(llvm::MCInst &Inst, unsigned Val,
2576 uint64_t Address, const void *Decoder) {
2577 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2581 static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
2582 uint64_t Address, const void *Decoder) {
2583 if (Val == 0xA || Val == 0xB)
2586 Inst.addOperand(MCOperand::CreateImm(Val));
2591 DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
2592 uint64_t Address, const void *Decoder) {
2593 DecodeStatus S = Success;
2595 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
2596 if (pred == 0xE || pred == 0xF) {
2597 unsigned opc = fieldFromInstruction32(Insn, 4, 2);
2602 Inst.setOpcode(ARM::t2DSB);
2605 Inst.setOpcode(ARM::t2DMB);
2608 Inst.setOpcode(ARM::t2ISB);
2612 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2613 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
2616 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
2617 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
2618 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
2619 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
2620 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
2622 CHECK(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder));
2623 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2628 // Decode a shifted immediate operand. These basically consist
2629 // of an 8-bit value, and a 4-bit directive that specifies either
2630 // a splat operation or a rotation.
2631 static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
2632 uint64_t Address, const void *Decoder) {
2633 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
2635 unsigned byte = fieldFromInstruction32(Val, 8, 2);
2636 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2639 Inst.addOperand(MCOperand::CreateImm(imm));
2642 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
2645 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
2648 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
2653 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
2654 unsigned rot = fieldFromInstruction32(Val, 7, 5);
2655 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
2656 Inst.addOperand(MCOperand::CreateImm(imm));
2663 DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
2664 uint64_t Address, const void *Decoder){
2665 Inst.addOperand(MCOperand::CreateImm(Val << 1));
2669 static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
2670 uint64_t Address, const void *Decoder){
2671 Inst.addOperand(MCOperand::CreateImm(SignExtend32<22>(Val << 1)));
2675 static DecodeStatus DecodeMemBarrierOption(llvm::MCInst &Inst, unsigned Val,
2676 uint64_t Address, const void *Decoder) {
2691 Inst.addOperand(MCOperand::CreateImm(Val));
2695 static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
2696 uint64_t Address, const void *Decoder) {
2697 if (!Val) return Fail;
2698 Inst.addOperand(MCOperand::CreateImm(Val));
2702 static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
2703 uint64_t Address, const void *Decoder) {
2704 DecodeStatus S = Success;
2706 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2707 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2708 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2710 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2712 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2713 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2714 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2715 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2721 static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
2722 uint64_t Address, const void *Decoder){
2723 DecodeStatus S = Success;
2725 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2726 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
2727 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2728 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2730 CHECK(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder));
2732 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return Fail;
2733 if (Rd == Rn || Rd == Rt || Rd == Rt+1) return Fail;
2735 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2736 CHECK(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder));
2737 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2738 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2743 static DecodeStatus DecodeSTRPreImm(llvm::MCInst &Inst, unsigned Insn,
2744 uint64_t Address, const void *Decoder) {
2745 DecodeStatus S = Success;
2747 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2748 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2749 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2750 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2751 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2752 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2754 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2756 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2757 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2758 CHECK(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder));
2759 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2764 static DecodeStatus DecodeSTRPreReg(llvm::MCInst &Inst, unsigned Insn,
2765 uint64_t Address, const void *Decoder) {
2766 DecodeStatus S = Success;
2768 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2769 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
2770 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
2771 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
2772 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
2773 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2775 if (Rn == 0xF || Rn == Rt) CHECK(S, Unpredictable);
2777 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2778 CHECK(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
2779 CHECK(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder));
2780 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
2785 static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
2786 uint64_t Address, const void *Decoder) {
2787 DecodeStatus S = Success;
2789 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2790 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2791 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2792 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2793 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2801 if (fieldFromInstruction32(Insn, 4, 1))
2802 return Fail; // UNDEFINED
2803 index = fieldFromInstruction32(Insn, 5, 3);
2806 if (fieldFromInstruction32(Insn, 5, 1))
2807 return Fail; // UNDEFINED
2808 index = fieldFromInstruction32(Insn, 6, 2);
2809 if (fieldFromInstruction32(Insn, 4, 1))
2813 if (fieldFromInstruction32(Insn, 6, 1))
2814 return Fail; // UNDEFINED
2815 index = fieldFromInstruction32(Insn, 7, 1);
2816 if (fieldFromInstruction32(Insn, 4, 2) != 0)
2820 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2821 if (Rm != 0xF) { // Writeback
2822 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2824 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2825 Inst.addOperand(MCOperand::CreateImm(align));
2828 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2830 Inst.addOperand(MCOperand::CreateReg(0));
2833 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2834 Inst.addOperand(MCOperand::CreateImm(index));
2839 static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
2840 uint64_t Address, const void *Decoder) {
2841 DecodeStatus S = Success;
2843 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2844 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2845 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2846 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2847 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2855 if (fieldFromInstruction32(Insn, 4, 1))
2856 return Fail; // UNDEFINED
2857 index = fieldFromInstruction32(Insn, 5, 3);
2860 if (fieldFromInstruction32(Insn, 5, 1))
2861 return Fail; // UNDEFINED
2862 index = fieldFromInstruction32(Insn, 6, 2);
2863 if (fieldFromInstruction32(Insn, 4, 1))
2867 if (fieldFromInstruction32(Insn, 6, 1))
2868 return Fail; // UNDEFINED
2869 index = fieldFromInstruction32(Insn, 7, 1);
2870 if (fieldFromInstruction32(Insn, 4, 2) != 0)
2874 if (Rm != 0xF) { // Writeback
2875 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2877 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2878 Inst.addOperand(MCOperand::CreateImm(align));
2881 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2883 Inst.addOperand(MCOperand::CreateReg(0));
2886 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2887 Inst.addOperand(MCOperand::CreateImm(index));
2893 static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
2894 uint64_t Address, const void *Decoder) {
2895 DecodeStatus S = Success;
2897 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2898 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2899 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2900 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2901 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2910 index = fieldFromInstruction32(Insn, 5, 3);
2911 if (fieldFromInstruction32(Insn, 4, 1))
2915 index = fieldFromInstruction32(Insn, 6, 2);
2916 if (fieldFromInstruction32(Insn, 4, 1))
2918 if (fieldFromInstruction32(Insn, 5, 1))
2922 if (fieldFromInstruction32(Insn, 5, 1))
2923 return Fail; // UNDEFINED
2924 index = fieldFromInstruction32(Insn, 7, 1);
2925 if (fieldFromInstruction32(Insn, 4, 1) != 0)
2927 if (fieldFromInstruction32(Insn, 6, 1))
2932 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2933 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2934 if (Rm != 0xF) { // Writeback
2935 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2937 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2938 Inst.addOperand(MCOperand::CreateImm(align));
2941 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
2943 Inst.addOperand(MCOperand::CreateReg(0));
2946 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
2947 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
2948 Inst.addOperand(MCOperand::CreateImm(index));
2953 static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
2954 uint64_t Address, const void *Decoder) {
2955 DecodeStatus S = Success;
2957 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2958 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2959 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2960 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2961 unsigned size = fieldFromInstruction32(Insn, 10, 2);
2970 index = fieldFromInstruction32(Insn, 5, 3);
2971 if (fieldFromInstruction32(Insn, 4, 1))
2975 index = fieldFromInstruction32(Insn, 6, 2);
2976 if (fieldFromInstruction32(Insn, 4, 1))
2978 if (fieldFromInstruction32(Insn, 5, 1))
2982 if (fieldFromInstruction32(Insn, 5, 1))
2983 return Fail; // UNDEFINED
2984 index = fieldFromInstruction32(Insn, 7, 1);
2985 if (fieldFromInstruction32(Insn, 4, 1) != 0)
2987 if (fieldFromInstruction32(Insn, 6, 1))
2992 if (Rm != 0xF) { // Writeback
2993 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2995 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
2996 Inst.addOperand(MCOperand::CreateImm(align));
2999 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3001 Inst.addOperand(MCOperand::CreateReg(0));
3004 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3005 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3006 Inst.addOperand(MCOperand::CreateImm(index));
3012 static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
3013 uint64_t Address, const void *Decoder) {
3014 DecodeStatus S = Success;
3016 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3017 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3018 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3019 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3020 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3029 if (fieldFromInstruction32(Insn, 4, 1))
3030 return Fail; // UNDEFINED
3031 index = fieldFromInstruction32(Insn, 5, 3);
3034 if (fieldFromInstruction32(Insn, 4, 1))
3035 return Fail; // UNDEFINED
3036 index = fieldFromInstruction32(Insn, 6, 2);
3037 if (fieldFromInstruction32(Insn, 5, 1))
3041 if (fieldFromInstruction32(Insn, 4, 2))
3042 return Fail; // UNDEFINED
3043 index = fieldFromInstruction32(Insn, 7, 1);
3044 if (fieldFromInstruction32(Insn, 6, 1))
3049 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3050 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3051 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3053 if (Rm != 0xF) { // Writeback
3054 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3056 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3057 Inst.addOperand(MCOperand::CreateImm(align));
3060 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3062 Inst.addOperand(MCOperand::CreateReg(0));
3065 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3066 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3067 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3068 Inst.addOperand(MCOperand::CreateImm(index));
3073 static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
3074 uint64_t Address, const void *Decoder) {
3075 DecodeStatus S = Success;
3077 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3078 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3079 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3080 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3081 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3090 if (fieldFromInstruction32(Insn, 4, 1))
3091 return Fail; // UNDEFINED
3092 index = fieldFromInstruction32(Insn, 5, 3);
3095 if (fieldFromInstruction32(Insn, 4, 1))
3096 return Fail; // UNDEFINED
3097 index = fieldFromInstruction32(Insn, 6, 2);
3098 if (fieldFromInstruction32(Insn, 5, 1))
3102 if (fieldFromInstruction32(Insn, 4, 2))
3103 return Fail; // UNDEFINED
3104 index = fieldFromInstruction32(Insn, 7, 1);
3105 if (fieldFromInstruction32(Insn, 6, 1))
3110 if (Rm != 0xF) { // Writeback
3111 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3113 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3114 Inst.addOperand(MCOperand::CreateImm(align));
3117 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3119 Inst.addOperand(MCOperand::CreateReg(0));
3122 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3123 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3124 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3125 Inst.addOperand(MCOperand::CreateImm(index));
3131 static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
3132 uint64_t Address, const void *Decoder) {
3133 DecodeStatus S = Success;
3135 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3136 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3137 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3138 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3139 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3148 if (fieldFromInstruction32(Insn, 4, 1))
3150 index = fieldFromInstruction32(Insn, 5, 3);
3153 if (fieldFromInstruction32(Insn, 4, 1))
3155 index = fieldFromInstruction32(Insn, 6, 2);
3156 if (fieldFromInstruction32(Insn, 5, 1))
3160 if (fieldFromInstruction32(Insn, 4, 2))
3161 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3162 index = fieldFromInstruction32(Insn, 7, 1);
3163 if (fieldFromInstruction32(Insn, 6, 1))
3168 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3169 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3170 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3171 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3173 if (Rm != 0xF) { // Writeback
3174 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3176 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3177 Inst.addOperand(MCOperand::CreateImm(align));
3180 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3182 Inst.addOperand(MCOperand::CreateReg(0));
3185 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3186 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3187 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3188 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3189 Inst.addOperand(MCOperand::CreateImm(index));
3194 static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
3195 uint64_t Address, const void *Decoder) {
3196 DecodeStatus S = Success;
3198 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3199 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3200 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3201 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3202 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3211 if (fieldFromInstruction32(Insn, 4, 1))
3213 index = fieldFromInstruction32(Insn, 5, 3);
3216 if (fieldFromInstruction32(Insn, 4, 1))
3218 index = fieldFromInstruction32(Insn, 6, 2);
3219 if (fieldFromInstruction32(Insn, 5, 1))
3223 if (fieldFromInstruction32(Insn, 4, 2))
3224 align = 4 << fieldFromInstruction32(Insn, 4, 2);
3225 index = fieldFromInstruction32(Insn, 7, 1);
3226 if (fieldFromInstruction32(Insn, 6, 1))
3231 if (Rm != 0xF) { // Writeback
3232 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3234 CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
3235 Inst.addOperand(MCOperand::CreateImm(align));
3238 CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
3240 Inst.addOperand(MCOperand::CreateReg(0));
3243 CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
3244 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder));
3245 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder));
3246 CHECK(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder));
3247 Inst.addOperand(MCOperand::CreateImm(index));
3252 static DecodeStatus DecodeVMOVSRR(llvm::MCInst &Inst, unsigned Insn,
3253 uint64_t Address, const void *Decoder) {
3254 DecodeStatus S = Success;
3255 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3256 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3257 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3258 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3259 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3261 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3262 CHECK(S, Unpredictable);
3264 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
3265 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3266 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
3267 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3268 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3273 static DecodeStatus DecodeVMOVRRS(llvm::MCInst &Inst, unsigned Insn,
3274 uint64_t Address, const void *Decoder) {
3275 DecodeStatus S = Success;
3276 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3277 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
3278 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3279 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3280 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
3282 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
3283 CHECK(S, Unpredictable);
3285 CHECK(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder));
3286 CHECK(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder));
3287 CHECK(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder));
3288 CHECK(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder));
3289 CHECK(S, DecodePredicateOperand(Inst, pred, Address, Decoder));
3294 static DecodeStatus DecodeITCond(llvm::MCInst &Inst, unsigned Cond,
3295 uint64_t Address, const void *Decoder) {
3296 DecodeStatus S = Success;
3299 CHECK(S, Unpredictable);
3302 Inst.addOperand(MCOperand::CreateImm(Cond));