1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/raw_ostream.h"
30 #define DEBUG_TYPE "arm-disassembler"
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
35 // Handles the condition code status of instructions in IT blocks
39 // Returns the condition code for instruction in IT block
41 unsigned CC = ARMCC::AL;
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 ITStates.push_back(CCBits);
77 ITStates.push_back(CCBits ^ 1);
79 ITStates.push_back(CCBits);
83 std::vector<unsigned char> ITStates;
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
91 /// Constructor - Initializes the disassembler.
93 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
94 MCDisassembler(STI, Ctx) {
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
102 const MemoryObject ®ion, uint64_t address,
103 raw_ostream &vStream,
104 raw_ostream &cStream) const override;
107 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
108 class ThumbDisassembler : public MCDisassembler {
110 /// Constructor - Initializes the disassembler.
112 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
113 MCDisassembler(STI, Ctx) {
116 ~ThumbDisassembler() {
119 /// getInstruction - See MCDisassembler.
120 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
121 const MemoryObject ®ion, uint64_t address,
122 raw_ostream &vStream,
123 raw_ostream &cStream) const override;
126 mutable ITStatus ITBlock;
127 DecodeStatus AddThumbPredicate(MCInst&) const;
128 void UpdateThumbVFPPredicate(MCInst&) const;
132 static bool Check(DecodeStatus &Out, DecodeStatus In) {
134 case MCDisassembler::Success:
135 // Out stays the same.
137 case MCDisassembler::SoftFail:
140 case MCDisassembler::Fail:
144 llvm_unreachable("Invalid DecodeStatus!");
148 // Forward declare these because the autogenerated code will reference them.
149 // Definitions are further down.
150 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
153 unsigned RegNo, uint64_t Address,
154 const void *Decoder);
155 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
156 unsigned RegNo, uint64_t Address,
157 const void *Decoder);
158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
175 const void *Decoder);
176 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
181 unsigned RegNo, uint64_t Address,
182 const void *Decoder);
184 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
204 const void *Decoder);
205 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
217 const void *Decoder);
218 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
323 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
347 uint64_t Address, const void* Decoder);
348 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
349 uint64_t Address, const void* Decoder);
350 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
353 uint64_t Address, const void* Decoder);
354 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
395 uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
397 uint64_t Address, const void *Decoder);
399 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
400 uint64_t Address, const void *Decoder);
401 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
402 uint64_t Address, const void *Decoder);
403 #include "ARMGenDisassemblerTables.inc"
405 static MCDisassembler *createARMDisassembler(const Target &T,
406 const MCSubtargetInfo &STI,
408 return new ARMDisassembler(STI, Ctx);
411 static MCDisassembler *createThumbDisassembler(const Target &T,
412 const MCSubtargetInfo &STI,
414 return new ThumbDisassembler(STI, Ctx);
417 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
418 const MemoryObject &Region,
421 raw_ostream &cs) const {
426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
429 // We want to read exactly 4 bytes of data.
430 if (Region.readBytes(Address, 4, bytes) == -1) {
432 return MCDisassembler::Fail;
435 // Encoded as a small-endian 32-bit word in the stream.
436 uint32_t insn = (bytes[3] << 24) |
441 // Calling the auto-generated decoder function.
442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
444 if (result != MCDisassembler::Fail) {
449 // VFP and NEON instructions, similarly, are shared between ARM
452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
453 if (result != MCDisassembler::Fail) {
459 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
460 if (result != MCDisassembler::Fail) {
466 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
468 if (result != MCDisassembler::Fail) {
470 // Add a fake predicate operand, because we share these instruction
471 // definitions with Thumb2 where these instructions are predicable.
472 if (!DecodePredicateOperand(MI, 0xE, Address, this))
473 return MCDisassembler::Fail;
478 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
480 if (result != MCDisassembler::Fail) {
482 // Add a fake predicate operand, because we share these instruction
483 // definitions with Thumb2 where these instructions are predicable.
484 if (!DecodePredicateOperand(MI, 0xE, Address, this))
485 return MCDisassembler::Fail;
490 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
492 if (result != MCDisassembler::Fail) {
494 // Add a fake predicate operand, because we share these instruction
495 // definitions with Thumb2 where these instructions are predicable.
496 if (!DecodePredicateOperand(MI, 0xE, Address, this))
497 return MCDisassembler::Fail;
502 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address,
504 if (result != MCDisassembler::Fail) {
510 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address,
512 if (result != MCDisassembler::Fail) {
519 return MCDisassembler::Fail;
523 extern const MCInstrDesc ARMInsts[];
526 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
527 /// immediate Value in the MCInst. The immediate Value has had any PC
528 /// adjustment made by the caller. If the instruction is a branch instruction
529 /// then isBranch is true, else false. If the getOpInfo() function was set as
530 /// part of the setupForSymbolicDisassembly() call then that function is called
531 /// to get any symbolic information at the Address for this instruction. If
532 /// that returns non-zero then the symbolic information it returns is used to
533 /// create an MCExpr and that is added as an operand to the MCInst. If
534 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
535 /// Value is done and if a symbol is found an MCExpr is created with that, else
536 /// an MCExpr with Value is created. This function returns true if it adds an
537 /// operand to the MCInst and false otherwise.
538 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
539 bool isBranch, uint64_t InstSize,
540 MCInst &MI, const void *Decoder) {
541 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
542 // FIXME: Does it make sense for value to be negative?
543 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
544 /* Offset */ 0, InstSize);
547 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
548 /// referenced by a load instruction with the base register that is the Pc.
549 /// These can often be values in a literal pool near the Address of the
550 /// instruction. The Address of the instruction and its immediate Value are
551 /// used as a possible literal pool entry. The SymbolLookUp call back will
552 /// return the name of a symbol referenced by the literal pool's entry if
553 /// the referenced address is that of a symbol. Or it will return a pointer to
554 /// a literal 'C' string if the referenced address of the literal pool's entry
555 /// is an address into a section with 'C' string literals.
556 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
557 const void *Decoder) {
558 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
559 Dis->tryAddingPcLoadReferenceComment(Value, Address);
562 // Thumb1 instructions don't have explicit S bits. Rather, they
563 // implicitly set CPSR. Since it's not represented in the encoding, the
564 // auto-generated decoder won't inject the CPSR operand. We need to fix
565 // that as a post-pass.
566 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
567 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
568 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
569 MCInst::iterator I = MI.begin();
570 for (unsigned i = 0; i < NumOps; ++i, ++I) {
571 if (I == MI.end()) break;
572 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
573 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
574 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
579 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
582 // Most Thumb instructions don't have explicit predicates in the
583 // encoding, but rather get their predicates from IT context. We need
584 // to fix up the predicate operands using this context information as a
586 MCDisassembler::DecodeStatus
587 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
588 MCDisassembler::DecodeStatus S = Success;
590 // A few instructions actually have predicates encoded in them. Don't
591 // try to overwrite it if we're seeing one of those.
592 switch (MI.getOpcode()) {
603 // Some instructions (mostly conditional branches) are not
604 // allowed in IT blocks.
605 if (ITBlock.instrInITBlock())
614 // Some instructions (mostly unconditional branches) can
615 // only appears at the end of, or outside of, an IT.
616 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
623 // If we're in an IT block, base the predicate on that. Otherwise,
624 // assume a predicate of AL.
626 CC = ITBlock.getITCC();
629 if (ITBlock.instrInITBlock())
630 ITBlock.advanceITState();
632 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
633 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
634 MCInst::iterator I = MI.begin();
635 for (unsigned i = 0; i < NumOps; ++i, ++I) {
636 if (I == MI.end()) break;
637 if (OpInfo[i].isPredicate()) {
638 I = MI.insert(I, MCOperand::CreateImm(CC));
641 MI.insert(I, MCOperand::CreateReg(0));
643 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
648 I = MI.insert(I, MCOperand::CreateImm(CC));
651 MI.insert(I, MCOperand::CreateReg(0));
653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
658 // Thumb VFP instructions are a special case. Because we share their
659 // encodings between ARM and Thumb modes, and they are predicable in ARM
660 // mode, the auto-generated decoder will give them an (incorrect)
661 // predicate operand. We need to rewrite these operands based on the IT
662 // context as a post-pass.
663 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
665 CC = ITBlock.getITCC();
666 if (ITBlock.instrInITBlock())
667 ITBlock.advanceITState();
669 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
670 MCInst::iterator I = MI.begin();
671 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
672 for (unsigned i = 0; i < NumOps; ++i, ++I) {
673 if (OpInfo[i].isPredicate() ) {
679 I->setReg(ARM::CPSR);
685 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
686 const MemoryObject &Region,
689 raw_ostream &cs) const {
694 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
695 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
697 // We want to read exactly 2 bytes of data.
698 if (Region.readBytes(Address, 2, bytes) == -1) {
700 return MCDisassembler::Fail;
703 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
704 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
706 if (result != MCDisassembler::Fail) {
708 Check(result, AddThumbPredicate(MI));
713 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
717 bool InITBlock = ITBlock.instrInITBlock();
718 Check(result, AddThumbPredicate(MI));
719 AddThumb1SBit(MI, InITBlock);
724 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
726 if (result != MCDisassembler::Fail) {
729 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
730 // the Thumb predicate.
731 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
732 result = MCDisassembler::SoftFail;
734 Check(result, AddThumbPredicate(MI));
736 // If we find an IT instruction, we need to parse its condition
737 // code and mask operands so that we can apply them correctly
738 // to the subsequent instructions.
739 if (MI.getOpcode() == ARM::t2IT) {
741 unsigned Firstcond = MI.getOperand(0).getImm();
742 unsigned Mask = MI.getOperand(1).getImm();
743 ITBlock.setITState(Firstcond, Mask);
749 // We want to read exactly 4 bytes of data.
750 if (Region.readBytes(Address, 4, bytes) == -1) {
752 return MCDisassembler::Fail;
755 uint32_t insn32 = (bytes[3] << 8) |
760 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
762 if (result != MCDisassembler::Fail) {
764 bool InITBlock = ITBlock.instrInITBlock();
765 Check(result, AddThumbPredicate(MI));
766 AddThumb1SBit(MI, InITBlock);
771 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
773 if (result != MCDisassembler::Fail) {
775 Check(result, AddThumbPredicate(MI));
779 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
781 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
782 if (result != MCDisassembler::Fail) {
784 UpdateThumbVFPPredicate(MI);
790 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
791 if (result != MCDisassembler::Fail) {
796 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
798 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
800 if (result != MCDisassembler::Fail) {
802 Check(result, AddThumbPredicate(MI));
807 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
809 uint32_t NEONLdStInsn = insn32;
810 NEONLdStInsn &= 0xF0FFFFFF;
811 NEONLdStInsn |= 0x04000000;
812 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
814 if (result != MCDisassembler::Fail) {
816 Check(result, AddThumbPredicate(MI));
821 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
823 uint32_t NEONDataInsn = insn32;
824 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
825 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
826 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
827 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
829 if (result != MCDisassembler::Fail) {
831 Check(result, AddThumbPredicate(MI));
836 uint32_t NEONCryptoInsn = insn32;
837 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
838 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
839 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
840 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
842 if (result != MCDisassembler::Fail) {
848 uint32_t NEONv8Insn = insn32;
849 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
850 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
852 if (result != MCDisassembler::Fail) {
860 return MCDisassembler::Fail;
864 extern "C" void LLVMInitializeARMDisassembler() {
865 TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
866 createARMDisassembler);
867 TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
868 createARMDisassembler);
869 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
870 createThumbDisassembler);
871 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
872 createThumbDisassembler);
875 static const uint16_t GPRDecoderTable[] = {
876 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
877 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
878 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
879 ARM::R12, ARM::SP, ARM::LR, ARM::PC
882 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
883 uint64_t Address, const void *Decoder) {
885 return MCDisassembler::Fail;
887 unsigned Register = GPRDecoderTable[RegNo];
888 Inst.addOperand(MCOperand::CreateReg(Register));
889 return MCDisassembler::Success;
893 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
894 uint64_t Address, const void *Decoder) {
895 DecodeStatus S = MCDisassembler::Success;
898 S = MCDisassembler::SoftFail;
900 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
906 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
907 uint64_t Address, const void *Decoder) {
908 DecodeStatus S = MCDisassembler::Success;
912 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
913 return MCDisassembler::Success;
916 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
920 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
921 uint64_t Address, const void *Decoder) {
923 return MCDisassembler::Fail;
924 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
927 static const uint16_t GPRPairDecoderTable[] = {
928 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
929 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
932 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
933 uint64_t Address, const void *Decoder) {
934 DecodeStatus S = MCDisassembler::Success;
937 return MCDisassembler::Fail;
939 if ((RegNo & 1) || RegNo == 0xe)
940 S = MCDisassembler::SoftFail;
942 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
943 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
947 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
948 uint64_t Address, const void *Decoder) {
949 unsigned Register = 0;
970 return MCDisassembler::Fail;
973 Inst.addOperand(MCOperand::CreateReg(Register));
974 return MCDisassembler::Success;
977 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
978 uint64_t Address, const void *Decoder) {
979 DecodeStatus S = MCDisassembler::Success;
980 if (RegNo == 13 || RegNo == 15)
981 S = MCDisassembler::SoftFail;
982 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
986 static const uint16_t SPRDecoderTable[] = {
987 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
988 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
989 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
990 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
991 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
992 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
993 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
994 ARM::S28, ARM::S29, ARM::S30, ARM::S31
997 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
998 uint64_t Address, const void *Decoder) {
1000 return MCDisassembler::Fail;
1002 unsigned Register = SPRDecoderTable[RegNo];
1003 Inst.addOperand(MCOperand::CreateReg(Register));
1004 return MCDisassembler::Success;
1007 static const uint16_t DPRDecoderTable[] = {
1008 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1009 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1010 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1011 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1012 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1013 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1014 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1015 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1018 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1019 uint64_t Address, const void *Decoder) {
1020 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1022 bool hasD16 = featureBits & ARM::FeatureD16;
1024 if (RegNo > 31 || (hasD16 && RegNo > 15))
1025 return MCDisassembler::Fail;
1027 unsigned Register = DPRDecoderTable[RegNo];
1028 Inst.addOperand(MCOperand::CreateReg(Register));
1029 return MCDisassembler::Success;
1032 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1033 uint64_t Address, const void *Decoder) {
1035 return MCDisassembler::Fail;
1036 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1040 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1041 uint64_t Address, const void *Decoder) {
1043 return MCDisassembler::Fail;
1044 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1047 static const uint16_t QPRDecoderTable[] = {
1048 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1049 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1050 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1051 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1055 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1056 uint64_t Address, const void *Decoder) {
1057 if (RegNo > 31 || (RegNo & 1) != 0)
1058 return MCDisassembler::Fail;
1061 unsigned Register = QPRDecoderTable[RegNo];
1062 Inst.addOperand(MCOperand::CreateReg(Register));
1063 return MCDisassembler::Success;
1066 static const uint16_t DPairDecoderTable[] = {
1067 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1068 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1069 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1070 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1071 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1075 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1076 uint64_t Address, const void *Decoder) {
1078 return MCDisassembler::Fail;
1080 unsigned Register = DPairDecoderTable[RegNo];
1081 Inst.addOperand(MCOperand::CreateReg(Register));
1082 return MCDisassembler::Success;
1085 static const uint16_t DPairSpacedDecoderTable[] = {
1086 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1087 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1088 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1089 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1090 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1091 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1092 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1093 ARM::D28_D30, ARM::D29_D31
1096 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1099 const void *Decoder) {
1101 return MCDisassembler::Fail;
1103 unsigned Register = DPairSpacedDecoderTable[RegNo];
1104 Inst.addOperand(MCOperand::CreateReg(Register));
1105 return MCDisassembler::Success;
1108 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1109 uint64_t Address, const void *Decoder) {
1110 if (Val == 0xF) return MCDisassembler::Fail;
1111 // AL predicate is not allowed on Thumb1 branches.
1112 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1113 return MCDisassembler::Fail;
1114 Inst.addOperand(MCOperand::CreateImm(Val));
1115 if (Val == ARMCC::AL) {
1116 Inst.addOperand(MCOperand::CreateReg(0));
1118 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1119 return MCDisassembler::Success;
1122 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1123 uint64_t Address, const void *Decoder) {
1125 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1127 Inst.addOperand(MCOperand::CreateReg(0));
1128 return MCDisassembler::Success;
1131 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1132 uint64_t Address, const void *Decoder) {
1133 uint32_t imm = Val & 0xFF;
1134 uint32_t rot = (Val & 0xF00) >> 7;
1135 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1136 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1137 return MCDisassembler::Success;
1140 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1141 uint64_t Address, const void *Decoder) {
1142 DecodeStatus S = MCDisassembler::Success;
1144 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1145 unsigned type = fieldFromInstruction(Val, 5, 2);
1146 unsigned imm = fieldFromInstruction(Val, 7, 5);
1148 // Register-immediate
1149 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1150 return MCDisassembler::Fail;
1152 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1155 Shift = ARM_AM::lsl;
1158 Shift = ARM_AM::lsr;
1161 Shift = ARM_AM::asr;
1164 Shift = ARM_AM::ror;
1168 if (Shift == ARM_AM::ror && imm == 0)
1169 Shift = ARM_AM::rrx;
1171 unsigned Op = Shift | (imm << 3);
1172 Inst.addOperand(MCOperand::CreateImm(Op));
1177 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1178 uint64_t Address, const void *Decoder) {
1179 DecodeStatus S = MCDisassembler::Success;
1181 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1182 unsigned type = fieldFromInstruction(Val, 5, 2);
1183 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1185 // Register-register
1186 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1187 return MCDisassembler::Fail;
1188 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1189 return MCDisassembler::Fail;
1191 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1194 Shift = ARM_AM::lsl;
1197 Shift = ARM_AM::lsr;
1200 Shift = ARM_AM::asr;
1203 Shift = ARM_AM::ror;
1207 Inst.addOperand(MCOperand::CreateImm(Shift));
1212 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1213 uint64_t Address, const void *Decoder) {
1214 DecodeStatus S = MCDisassembler::Success;
1216 bool NeedDisjointWriteback = false;
1217 unsigned WritebackReg = 0;
1218 switch (Inst.getOpcode()) {
1221 case ARM::LDMIA_UPD:
1222 case ARM::LDMDB_UPD:
1223 case ARM::LDMIB_UPD:
1224 case ARM::LDMDA_UPD:
1225 case ARM::t2LDMIA_UPD:
1226 case ARM::t2LDMDB_UPD:
1227 case ARM::t2STMIA_UPD:
1228 case ARM::t2STMDB_UPD:
1229 NeedDisjointWriteback = true;
1230 WritebackReg = Inst.getOperand(0).getReg();
1234 // Empty register lists are not allowed.
1235 if (Val == 0) return MCDisassembler::Fail;
1236 for (unsigned i = 0; i < 16; ++i) {
1237 if (Val & (1 << i)) {
1238 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1239 return MCDisassembler::Fail;
1240 // Writeback not allowed if Rn is in the target list.
1241 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1242 Check(S, MCDisassembler::SoftFail);
1249 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1250 uint64_t Address, const void *Decoder) {
1251 DecodeStatus S = MCDisassembler::Success;
1253 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1254 unsigned regs = fieldFromInstruction(Val, 0, 8);
1256 // In case of unpredictable encoding, tweak the operands.
1257 if (regs == 0 || (Vd + regs) > 32) {
1258 regs = Vd + regs > 32 ? 32 - Vd : regs;
1259 regs = std::max( 1u, regs);
1260 S = MCDisassembler::SoftFail;
1263 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1264 return MCDisassembler::Fail;
1265 for (unsigned i = 0; i < (regs - 1); ++i) {
1266 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1267 return MCDisassembler::Fail;
1273 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1274 uint64_t Address, const void *Decoder) {
1275 DecodeStatus S = MCDisassembler::Success;
1277 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1278 unsigned regs = fieldFromInstruction(Val, 1, 7);
1280 // In case of unpredictable encoding, tweak the operands.
1281 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1282 regs = Vd + regs > 32 ? 32 - Vd : regs;
1283 regs = std::max( 1u, regs);
1284 regs = std::min(16u, regs);
1285 S = MCDisassembler::SoftFail;
1288 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1289 return MCDisassembler::Fail;
1290 for (unsigned i = 0; i < (regs - 1); ++i) {
1291 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1292 return MCDisassembler::Fail;
1298 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1299 uint64_t Address, const void *Decoder) {
1300 // This operand encodes a mask of contiguous zeros between a specified MSB
1301 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1302 // the mask of all bits LSB-and-lower, and then xor them to create
1303 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1304 // create the final mask.
1305 unsigned msb = fieldFromInstruction(Val, 5, 5);
1306 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1308 DecodeStatus S = MCDisassembler::Success;
1310 Check(S, MCDisassembler::SoftFail);
1311 // The check above will cause the warning for the "potentially undefined
1312 // instruction encoding" but we can't build a bad MCOperand value here
1313 // with a lsb > msb or else printing the MCInst will cause a crash.
1317 uint32_t msb_mask = 0xFFFFFFFF;
1318 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1319 uint32_t lsb_mask = (1U << lsb) - 1;
1321 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1325 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1326 uint64_t Address, const void *Decoder) {
1327 DecodeStatus S = MCDisassembler::Success;
1329 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1330 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1331 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1332 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1333 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1334 unsigned U = fieldFromInstruction(Insn, 23, 1);
1336 switch (Inst.getOpcode()) {
1337 case ARM::LDC_OFFSET:
1340 case ARM::LDC_OPTION:
1341 case ARM::LDCL_OFFSET:
1343 case ARM::LDCL_POST:
1344 case ARM::LDCL_OPTION:
1345 case ARM::STC_OFFSET:
1348 case ARM::STC_OPTION:
1349 case ARM::STCL_OFFSET:
1351 case ARM::STCL_POST:
1352 case ARM::STCL_OPTION:
1353 case ARM::t2LDC_OFFSET:
1354 case ARM::t2LDC_PRE:
1355 case ARM::t2LDC_POST:
1356 case ARM::t2LDC_OPTION:
1357 case ARM::t2LDCL_OFFSET:
1358 case ARM::t2LDCL_PRE:
1359 case ARM::t2LDCL_POST:
1360 case ARM::t2LDCL_OPTION:
1361 case ARM::t2STC_OFFSET:
1362 case ARM::t2STC_PRE:
1363 case ARM::t2STC_POST:
1364 case ARM::t2STC_OPTION:
1365 case ARM::t2STCL_OFFSET:
1366 case ARM::t2STCL_PRE:
1367 case ARM::t2STCL_POST:
1368 case ARM::t2STCL_OPTION:
1369 if (coproc == 0xA || coproc == 0xB)
1370 return MCDisassembler::Fail;
1376 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1378 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1379 return MCDisassembler::Fail;
1381 Inst.addOperand(MCOperand::CreateImm(coproc));
1382 Inst.addOperand(MCOperand::CreateImm(CRd));
1383 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1384 return MCDisassembler::Fail;
1386 switch (Inst.getOpcode()) {
1387 case ARM::t2LDC2_OFFSET:
1388 case ARM::t2LDC2L_OFFSET:
1389 case ARM::t2LDC2_PRE:
1390 case ARM::t2LDC2L_PRE:
1391 case ARM::t2STC2_OFFSET:
1392 case ARM::t2STC2L_OFFSET:
1393 case ARM::t2STC2_PRE:
1394 case ARM::t2STC2L_PRE:
1395 case ARM::LDC2_OFFSET:
1396 case ARM::LDC2L_OFFSET:
1398 case ARM::LDC2L_PRE:
1399 case ARM::STC2_OFFSET:
1400 case ARM::STC2L_OFFSET:
1402 case ARM::STC2L_PRE:
1403 case ARM::t2LDC_OFFSET:
1404 case ARM::t2LDCL_OFFSET:
1405 case ARM::t2LDC_PRE:
1406 case ARM::t2LDCL_PRE:
1407 case ARM::t2STC_OFFSET:
1408 case ARM::t2STCL_OFFSET:
1409 case ARM::t2STC_PRE:
1410 case ARM::t2STCL_PRE:
1411 case ARM::LDC_OFFSET:
1412 case ARM::LDCL_OFFSET:
1415 case ARM::STC_OFFSET:
1416 case ARM::STCL_OFFSET:
1419 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1420 Inst.addOperand(MCOperand::CreateImm(imm));
1422 case ARM::t2LDC2_POST:
1423 case ARM::t2LDC2L_POST:
1424 case ARM::t2STC2_POST:
1425 case ARM::t2STC2L_POST:
1426 case ARM::LDC2_POST:
1427 case ARM::LDC2L_POST:
1428 case ARM::STC2_POST:
1429 case ARM::STC2L_POST:
1430 case ARM::t2LDC_POST:
1431 case ARM::t2LDCL_POST:
1432 case ARM::t2STC_POST:
1433 case ARM::t2STCL_POST:
1435 case ARM::LDCL_POST:
1437 case ARM::STCL_POST:
1441 // The 'option' variant doesn't encode 'U' in the immediate since
1442 // the immediate is unsigned [0,255].
1443 Inst.addOperand(MCOperand::CreateImm(imm));
1447 switch (Inst.getOpcode()) {
1448 case ARM::LDC_OFFSET:
1451 case ARM::LDC_OPTION:
1452 case ARM::LDCL_OFFSET:
1454 case ARM::LDCL_POST:
1455 case ARM::LDCL_OPTION:
1456 case ARM::STC_OFFSET:
1459 case ARM::STC_OPTION:
1460 case ARM::STCL_OFFSET:
1462 case ARM::STCL_POST:
1463 case ARM::STCL_OPTION:
1464 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1465 return MCDisassembler::Fail;
1475 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1476 uint64_t Address, const void *Decoder) {
1477 DecodeStatus S = MCDisassembler::Success;
1479 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1480 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1481 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1482 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1483 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1484 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1485 unsigned P = fieldFromInstruction(Insn, 24, 1);
1486 unsigned W = fieldFromInstruction(Insn, 21, 1);
1488 // On stores, the writeback operand precedes Rt.
1489 switch (Inst.getOpcode()) {
1490 case ARM::STR_POST_IMM:
1491 case ARM::STR_POST_REG:
1492 case ARM::STRB_POST_IMM:
1493 case ARM::STRB_POST_REG:
1494 case ARM::STRT_POST_REG:
1495 case ARM::STRT_POST_IMM:
1496 case ARM::STRBT_POST_REG:
1497 case ARM::STRBT_POST_IMM:
1498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1499 return MCDisassembler::Fail;
1505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1506 return MCDisassembler::Fail;
1508 // On loads, the writeback operand comes after Rt.
1509 switch (Inst.getOpcode()) {
1510 case ARM::LDR_POST_IMM:
1511 case ARM::LDR_POST_REG:
1512 case ARM::LDRB_POST_IMM:
1513 case ARM::LDRB_POST_REG:
1514 case ARM::LDRBT_POST_REG:
1515 case ARM::LDRBT_POST_IMM:
1516 case ARM::LDRT_POST_REG:
1517 case ARM::LDRT_POST_IMM:
1518 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1519 return MCDisassembler::Fail;
1525 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1526 return MCDisassembler::Fail;
1528 ARM_AM::AddrOpc Op = ARM_AM::add;
1529 if (!fieldFromInstruction(Insn, 23, 1))
1532 bool writeback = (P == 0) || (W == 1);
1533 unsigned idx_mode = 0;
1535 idx_mode = ARMII::IndexModePre;
1536 else if (!P && writeback)
1537 idx_mode = ARMII::IndexModePost;
1539 if (writeback && (Rn == 15 || Rn == Rt))
1540 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1543 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1544 return MCDisassembler::Fail;
1545 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1546 switch( fieldFromInstruction(Insn, 5, 2)) {
1560 return MCDisassembler::Fail;
1562 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1563 if (Opc == ARM_AM::ror && amt == 0)
1565 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1567 Inst.addOperand(MCOperand::CreateImm(imm));
1569 Inst.addOperand(MCOperand::CreateReg(0));
1570 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1571 Inst.addOperand(MCOperand::CreateImm(tmp));
1574 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1575 return MCDisassembler::Fail;
1580 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1581 uint64_t Address, const void *Decoder) {
1582 DecodeStatus S = MCDisassembler::Success;
1584 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1585 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1586 unsigned type = fieldFromInstruction(Val, 5, 2);
1587 unsigned imm = fieldFromInstruction(Val, 7, 5);
1588 unsigned U = fieldFromInstruction(Val, 12, 1);
1590 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1606 if (ShOp == ARM_AM::ror && imm == 0)
1609 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1610 return MCDisassembler::Fail;
1611 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1612 return MCDisassembler::Fail;
1615 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1617 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1618 Inst.addOperand(MCOperand::CreateImm(shift));
1624 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1625 uint64_t Address, const void *Decoder) {
1626 DecodeStatus S = MCDisassembler::Success;
1628 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1629 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1630 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1631 unsigned type = fieldFromInstruction(Insn, 22, 1);
1632 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1633 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1634 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1635 unsigned W = fieldFromInstruction(Insn, 21, 1);
1636 unsigned P = fieldFromInstruction(Insn, 24, 1);
1637 unsigned Rt2 = Rt + 1;
1639 bool writeback = (W == 1) | (P == 0);
1641 // For {LD,ST}RD, Rt must be even, else undefined.
1642 switch (Inst.getOpcode()) {
1645 case ARM::STRD_POST:
1648 case ARM::LDRD_POST:
1649 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1654 switch (Inst.getOpcode()) {
1657 case ARM::STRD_POST:
1658 if (P == 0 && W == 1)
1659 S = MCDisassembler::SoftFail;
1661 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1662 S = MCDisassembler::SoftFail;
1663 if (type && Rm == 15)
1664 S = MCDisassembler::SoftFail;
1666 S = MCDisassembler::SoftFail;
1667 if (!type && fieldFromInstruction(Insn, 8, 4))
1668 S = MCDisassembler::SoftFail;
1672 case ARM::STRH_POST:
1674 S = MCDisassembler::SoftFail;
1675 if (writeback && (Rn == 15 || Rn == Rt))
1676 S = MCDisassembler::SoftFail;
1677 if (!type && Rm == 15)
1678 S = MCDisassembler::SoftFail;
1682 case ARM::LDRD_POST:
1683 if (type && Rn == 15){
1685 S = MCDisassembler::SoftFail;
1688 if (P == 0 && W == 1)
1689 S = MCDisassembler::SoftFail;
1690 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1691 S = MCDisassembler::SoftFail;
1692 if (!type && writeback && Rn == 15)
1693 S = MCDisassembler::SoftFail;
1694 if (writeback && (Rn == Rt || Rn == Rt2))
1695 S = MCDisassembler::SoftFail;
1699 case ARM::LDRH_POST:
1700 if (type && Rn == 15){
1702 S = MCDisassembler::SoftFail;
1706 S = MCDisassembler::SoftFail;
1707 if (!type && Rm == 15)
1708 S = MCDisassembler::SoftFail;
1709 if (!type && writeback && (Rn == 15 || Rn == Rt))
1710 S = MCDisassembler::SoftFail;
1713 case ARM::LDRSH_PRE:
1714 case ARM::LDRSH_POST:
1716 case ARM::LDRSB_PRE:
1717 case ARM::LDRSB_POST:
1718 if (type && Rn == 15){
1720 S = MCDisassembler::SoftFail;
1723 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1724 S = MCDisassembler::SoftFail;
1725 if (!type && (Rt == 15 || Rm == 15))
1726 S = MCDisassembler::SoftFail;
1727 if (!type && writeback && (Rn == 15 || Rn == Rt))
1728 S = MCDisassembler::SoftFail;
1734 if (writeback) { // Writeback
1736 U |= ARMII::IndexModePre << 9;
1738 U |= ARMII::IndexModePost << 9;
1740 // On stores, the writeback operand precedes Rt.
1741 switch (Inst.getOpcode()) {
1744 case ARM::STRD_POST:
1747 case ARM::STRH_POST:
1748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1749 return MCDisassembler::Fail;
1756 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1757 return MCDisassembler::Fail;
1758 switch (Inst.getOpcode()) {
1761 case ARM::STRD_POST:
1764 case ARM::LDRD_POST:
1765 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1766 return MCDisassembler::Fail;
1773 // On loads, the writeback operand comes after Rt.
1774 switch (Inst.getOpcode()) {
1777 case ARM::LDRD_POST:
1780 case ARM::LDRH_POST:
1782 case ARM::LDRSH_PRE:
1783 case ARM::LDRSH_POST:
1785 case ARM::LDRSB_PRE:
1786 case ARM::LDRSB_POST:
1789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1790 return MCDisassembler::Fail;
1797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1798 return MCDisassembler::Fail;
1801 Inst.addOperand(MCOperand::CreateReg(0));
1802 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1804 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1805 return MCDisassembler::Fail;
1806 Inst.addOperand(MCOperand::CreateImm(U));
1809 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1810 return MCDisassembler::Fail;
1815 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1816 uint64_t Address, const void *Decoder) {
1817 DecodeStatus S = MCDisassembler::Success;
1819 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1820 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1837 Inst.addOperand(MCOperand::CreateImm(mode));
1838 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1839 return MCDisassembler::Fail;
1844 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1845 uint64_t Address, const void *Decoder) {
1846 DecodeStatus S = MCDisassembler::Success;
1848 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1849 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1850 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1851 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1854 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1857 return MCDisassembler::Fail;
1858 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1859 return MCDisassembler::Fail;
1860 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1861 return MCDisassembler::Fail;
1862 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1863 return MCDisassembler::Fail;
1867 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1869 uint64_t Address, const void *Decoder) {
1870 DecodeStatus S = MCDisassembler::Success;
1872 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1873 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1874 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1877 // Ambiguous with RFE and SRS
1878 switch (Inst.getOpcode()) {
1880 Inst.setOpcode(ARM::RFEDA);
1882 case ARM::LDMDA_UPD:
1883 Inst.setOpcode(ARM::RFEDA_UPD);
1886 Inst.setOpcode(ARM::RFEDB);
1888 case ARM::LDMDB_UPD:
1889 Inst.setOpcode(ARM::RFEDB_UPD);
1892 Inst.setOpcode(ARM::RFEIA);
1894 case ARM::LDMIA_UPD:
1895 Inst.setOpcode(ARM::RFEIA_UPD);
1898 Inst.setOpcode(ARM::RFEIB);
1900 case ARM::LDMIB_UPD:
1901 Inst.setOpcode(ARM::RFEIB_UPD);
1904 Inst.setOpcode(ARM::SRSDA);
1906 case ARM::STMDA_UPD:
1907 Inst.setOpcode(ARM::SRSDA_UPD);
1910 Inst.setOpcode(ARM::SRSDB);
1912 case ARM::STMDB_UPD:
1913 Inst.setOpcode(ARM::SRSDB_UPD);
1916 Inst.setOpcode(ARM::SRSIA);
1918 case ARM::STMIA_UPD:
1919 Inst.setOpcode(ARM::SRSIA_UPD);
1922 Inst.setOpcode(ARM::SRSIB);
1924 case ARM::STMIB_UPD:
1925 Inst.setOpcode(ARM::SRSIB_UPD);
1928 return MCDisassembler::Fail;
1931 // For stores (which become SRS's, the only operand is the mode.
1932 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1933 // Check SRS encoding constraints
1934 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1935 fieldFromInstruction(Insn, 20, 1) == 0))
1936 return MCDisassembler::Fail;
1939 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1943 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1946 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1947 return MCDisassembler::Fail;
1948 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1949 return MCDisassembler::Fail; // Tied
1950 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1951 return MCDisassembler::Fail;
1952 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1953 return MCDisassembler::Fail;
1958 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1959 uint64_t Address, const void *Decoder) {
1960 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1961 unsigned M = fieldFromInstruction(Insn, 17, 1);
1962 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1963 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1965 DecodeStatus S = MCDisassembler::Success;
1967 // This decoder is called from multiple location that do not check
1968 // the full encoding is valid before they do.
1969 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1970 fieldFromInstruction(Insn, 16, 1) != 0 ||
1971 fieldFromInstruction(Insn, 20, 8) != 0x10)
1972 return MCDisassembler::Fail;
1974 // imod == '01' --> UNPREDICTABLE
1975 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1976 // return failure here. The '01' imod value is unprintable, so there's
1977 // nothing useful we could do even if we returned UNPREDICTABLE.
1979 if (imod == 1) return MCDisassembler::Fail;
1982 Inst.setOpcode(ARM::CPS3p);
1983 Inst.addOperand(MCOperand::CreateImm(imod));
1984 Inst.addOperand(MCOperand::CreateImm(iflags));
1985 Inst.addOperand(MCOperand::CreateImm(mode));
1986 } else if (imod && !M) {
1987 Inst.setOpcode(ARM::CPS2p);
1988 Inst.addOperand(MCOperand::CreateImm(imod));
1989 Inst.addOperand(MCOperand::CreateImm(iflags));
1990 if (mode) S = MCDisassembler::SoftFail;
1991 } else if (!imod && M) {
1992 Inst.setOpcode(ARM::CPS1p);
1993 Inst.addOperand(MCOperand::CreateImm(mode));
1994 if (iflags) S = MCDisassembler::SoftFail;
1996 // imod == '00' && M == '0' --> UNPREDICTABLE
1997 Inst.setOpcode(ARM::CPS1p);
1998 Inst.addOperand(MCOperand::CreateImm(mode));
1999 S = MCDisassembler::SoftFail;
2005 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2006 uint64_t Address, const void *Decoder) {
2007 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2008 unsigned M = fieldFromInstruction(Insn, 8, 1);
2009 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2010 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2012 DecodeStatus S = MCDisassembler::Success;
2014 // imod == '01' --> UNPREDICTABLE
2015 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2016 // return failure here. The '01' imod value is unprintable, so there's
2017 // nothing useful we could do even if we returned UNPREDICTABLE.
2019 if (imod == 1) return MCDisassembler::Fail;
2022 Inst.setOpcode(ARM::t2CPS3p);
2023 Inst.addOperand(MCOperand::CreateImm(imod));
2024 Inst.addOperand(MCOperand::CreateImm(iflags));
2025 Inst.addOperand(MCOperand::CreateImm(mode));
2026 } else if (imod && !M) {
2027 Inst.setOpcode(ARM::t2CPS2p);
2028 Inst.addOperand(MCOperand::CreateImm(imod));
2029 Inst.addOperand(MCOperand::CreateImm(iflags));
2030 if (mode) S = MCDisassembler::SoftFail;
2031 } else if (!imod && M) {
2032 Inst.setOpcode(ARM::t2CPS1p);
2033 Inst.addOperand(MCOperand::CreateImm(mode));
2034 if (iflags) S = MCDisassembler::SoftFail;
2036 // imod == '00' && M == '0' --> this is a HINT instruction
2037 int imm = fieldFromInstruction(Insn, 0, 8);
2038 // HINT are defined only for immediate in [0..4]
2039 if(imm > 4) return MCDisassembler::Fail;
2040 Inst.setOpcode(ARM::t2HINT);
2041 Inst.addOperand(MCOperand::CreateImm(imm));
2047 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2048 uint64_t Address, const void *Decoder) {
2049 DecodeStatus S = MCDisassembler::Success;
2051 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2054 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2055 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2056 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2057 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2059 if (Inst.getOpcode() == ARM::t2MOVTi16)
2060 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2061 return MCDisassembler::Fail;
2062 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2063 return MCDisassembler::Fail;
2065 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2066 Inst.addOperand(MCOperand::CreateImm(imm));
2071 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2072 uint64_t Address, const void *Decoder) {
2073 DecodeStatus S = MCDisassembler::Success;
2075 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2076 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2079 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2080 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2082 if (Inst.getOpcode() == ARM::MOVTi16)
2083 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2084 return MCDisassembler::Fail;
2086 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2087 return MCDisassembler::Fail;
2089 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2090 Inst.addOperand(MCOperand::CreateImm(imm));
2092 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2093 return MCDisassembler::Fail;
2098 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2099 uint64_t Address, const void *Decoder) {
2100 DecodeStatus S = MCDisassembler::Success;
2102 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2103 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2104 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2105 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2106 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2109 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2112 return MCDisassembler::Fail;
2113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2114 return MCDisassembler::Fail;
2115 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2116 return MCDisassembler::Fail;
2117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2118 return MCDisassembler::Fail;
2120 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2121 return MCDisassembler::Fail;
2126 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2127 uint64_t Address, const void *Decoder) {
2128 DecodeStatus S = MCDisassembler::Success;
2130 unsigned add = fieldFromInstruction(Val, 12, 1);
2131 unsigned imm = fieldFromInstruction(Val, 0, 12);
2132 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2134 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2135 return MCDisassembler::Fail;
2137 if (!add) imm *= -1;
2138 if (imm == 0 && !add) imm = INT32_MIN;
2139 Inst.addOperand(MCOperand::CreateImm(imm));
2141 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2146 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2147 uint64_t Address, const void *Decoder) {
2148 DecodeStatus S = MCDisassembler::Success;
2150 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2151 unsigned U = fieldFromInstruction(Val, 8, 1);
2152 unsigned imm = fieldFromInstruction(Val, 0, 8);
2154 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2155 return MCDisassembler::Fail;
2158 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2160 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2165 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2166 uint64_t Address, const void *Decoder) {
2167 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2171 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2172 uint64_t Address, const void *Decoder) {
2173 DecodeStatus Status = MCDisassembler::Success;
2175 // Note the J1 and J2 values are from the encoded instruction. So here
2176 // change them to I1 and I2 values via as documented:
2177 // I1 = NOT(J1 EOR S);
2178 // I2 = NOT(J2 EOR S);
2179 // and build the imm32 with one trailing zero as documented:
2180 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2181 unsigned S = fieldFromInstruction(Insn, 26, 1);
2182 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2183 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2184 unsigned I1 = !(J1 ^ S);
2185 unsigned I2 = !(J2 ^ S);
2186 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2187 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2188 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2189 int imm32 = SignExtend32<25>(tmp << 1);
2190 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2191 true, 4, Inst, Decoder))
2192 Inst.addOperand(MCOperand::CreateImm(imm32));
2198 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2199 uint64_t Address, const void *Decoder) {
2200 DecodeStatus S = MCDisassembler::Success;
2202 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2203 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2206 Inst.setOpcode(ARM::BLXi);
2207 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2208 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2209 true, 4, Inst, Decoder))
2210 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2214 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2215 true, 4, Inst, Decoder))
2216 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2217 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2218 return MCDisassembler::Fail;
2224 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2225 uint64_t Address, const void *Decoder) {
2226 DecodeStatus S = MCDisassembler::Success;
2228 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2229 unsigned align = fieldFromInstruction(Val, 4, 2);
2231 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2232 return MCDisassembler::Fail;
2234 Inst.addOperand(MCOperand::CreateImm(0));
2236 Inst.addOperand(MCOperand::CreateImm(4 << align));
2241 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2242 uint64_t Address, const void *Decoder) {
2243 DecodeStatus S = MCDisassembler::Success;
2245 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2246 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2247 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2248 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2249 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2250 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2252 // First output register
2253 switch (Inst.getOpcode()) {
2254 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2255 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2256 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2257 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2258 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2259 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2260 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2261 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2262 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2263 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2264 return MCDisassembler::Fail;
2269 case ARM::VLD2b16wb_fixed:
2270 case ARM::VLD2b16wb_register:
2271 case ARM::VLD2b32wb_fixed:
2272 case ARM::VLD2b32wb_register:
2273 case ARM::VLD2b8wb_fixed:
2274 case ARM::VLD2b8wb_register:
2275 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2276 return MCDisassembler::Fail;
2279 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2280 return MCDisassembler::Fail;
2283 // Second output register
2284 switch (Inst.getOpcode()) {
2288 case ARM::VLD3d8_UPD:
2289 case ARM::VLD3d16_UPD:
2290 case ARM::VLD3d32_UPD:
2294 case ARM::VLD4d8_UPD:
2295 case ARM::VLD4d16_UPD:
2296 case ARM::VLD4d32_UPD:
2297 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2298 return MCDisassembler::Fail;
2303 case ARM::VLD3q8_UPD:
2304 case ARM::VLD3q16_UPD:
2305 case ARM::VLD3q32_UPD:
2309 case ARM::VLD4q8_UPD:
2310 case ARM::VLD4q16_UPD:
2311 case ARM::VLD4q32_UPD:
2312 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2313 return MCDisassembler::Fail;
2318 // Third output register
2319 switch(Inst.getOpcode()) {
2323 case ARM::VLD3d8_UPD:
2324 case ARM::VLD3d16_UPD:
2325 case ARM::VLD3d32_UPD:
2329 case ARM::VLD4d8_UPD:
2330 case ARM::VLD4d16_UPD:
2331 case ARM::VLD4d32_UPD:
2332 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2333 return MCDisassembler::Fail;
2338 case ARM::VLD3q8_UPD:
2339 case ARM::VLD3q16_UPD:
2340 case ARM::VLD3q32_UPD:
2344 case ARM::VLD4q8_UPD:
2345 case ARM::VLD4q16_UPD:
2346 case ARM::VLD4q32_UPD:
2347 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2348 return MCDisassembler::Fail;
2354 // Fourth output register
2355 switch (Inst.getOpcode()) {
2359 case ARM::VLD4d8_UPD:
2360 case ARM::VLD4d16_UPD:
2361 case ARM::VLD4d32_UPD:
2362 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2363 return MCDisassembler::Fail;
2368 case ARM::VLD4q8_UPD:
2369 case ARM::VLD4q16_UPD:
2370 case ARM::VLD4q32_UPD:
2371 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2372 return MCDisassembler::Fail;
2378 // Writeback operand
2379 switch (Inst.getOpcode()) {
2380 case ARM::VLD1d8wb_fixed:
2381 case ARM::VLD1d16wb_fixed:
2382 case ARM::VLD1d32wb_fixed:
2383 case ARM::VLD1d64wb_fixed:
2384 case ARM::VLD1d8wb_register:
2385 case ARM::VLD1d16wb_register:
2386 case ARM::VLD1d32wb_register:
2387 case ARM::VLD1d64wb_register:
2388 case ARM::VLD1q8wb_fixed:
2389 case ARM::VLD1q16wb_fixed:
2390 case ARM::VLD1q32wb_fixed:
2391 case ARM::VLD1q64wb_fixed:
2392 case ARM::VLD1q8wb_register:
2393 case ARM::VLD1q16wb_register:
2394 case ARM::VLD1q32wb_register:
2395 case ARM::VLD1q64wb_register:
2396 case ARM::VLD1d8Twb_fixed:
2397 case ARM::VLD1d8Twb_register:
2398 case ARM::VLD1d16Twb_fixed:
2399 case ARM::VLD1d16Twb_register:
2400 case ARM::VLD1d32Twb_fixed:
2401 case ARM::VLD1d32Twb_register:
2402 case ARM::VLD1d64Twb_fixed:
2403 case ARM::VLD1d64Twb_register:
2404 case ARM::VLD1d8Qwb_fixed:
2405 case ARM::VLD1d8Qwb_register:
2406 case ARM::VLD1d16Qwb_fixed:
2407 case ARM::VLD1d16Qwb_register:
2408 case ARM::VLD1d32Qwb_fixed:
2409 case ARM::VLD1d32Qwb_register:
2410 case ARM::VLD1d64Qwb_fixed:
2411 case ARM::VLD1d64Qwb_register:
2412 case ARM::VLD2d8wb_fixed:
2413 case ARM::VLD2d16wb_fixed:
2414 case ARM::VLD2d32wb_fixed:
2415 case ARM::VLD2q8wb_fixed:
2416 case ARM::VLD2q16wb_fixed:
2417 case ARM::VLD2q32wb_fixed:
2418 case ARM::VLD2d8wb_register:
2419 case ARM::VLD2d16wb_register:
2420 case ARM::VLD2d32wb_register:
2421 case ARM::VLD2q8wb_register:
2422 case ARM::VLD2q16wb_register:
2423 case ARM::VLD2q32wb_register:
2424 case ARM::VLD2b8wb_fixed:
2425 case ARM::VLD2b16wb_fixed:
2426 case ARM::VLD2b32wb_fixed:
2427 case ARM::VLD2b8wb_register:
2428 case ARM::VLD2b16wb_register:
2429 case ARM::VLD2b32wb_register:
2430 Inst.addOperand(MCOperand::CreateImm(0));
2432 case ARM::VLD3d8_UPD:
2433 case ARM::VLD3d16_UPD:
2434 case ARM::VLD3d32_UPD:
2435 case ARM::VLD3q8_UPD:
2436 case ARM::VLD3q16_UPD:
2437 case ARM::VLD3q32_UPD:
2438 case ARM::VLD4d8_UPD:
2439 case ARM::VLD4d16_UPD:
2440 case ARM::VLD4d32_UPD:
2441 case ARM::VLD4q8_UPD:
2442 case ARM::VLD4q16_UPD:
2443 case ARM::VLD4q32_UPD:
2444 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2445 return MCDisassembler::Fail;
2451 // AddrMode6 Base (register+alignment)
2452 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2453 return MCDisassembler::Fail;
2455 // AddrMode6 Offset (register)
2456 switch (Inst.getOpcode()) {
2458 // The below have been updated to have explicit am6offset split
2459 // between fixed and register offset. For those instructions not
2460 // yet updated, we need to add an additional reg0 operand for the
2463 // The fixed offset encodes as Rm == 0xd, so we check for that.
2465 Inst.addOperand(MCOperand::CreateReg(0));
2468 // Fall through to handle the register offset variant.
2469 case ARM::VLD1d8wb_fixed:
2470 case ARM::VLD1d16wb_fixed:
2471 case ARM::VLD1d32wb_fixed:
2472 case ARM::VLD1d64wb_fixed:
2473 case ARM::VLD1d8Twb_fixed:
2474 case ARM::VLD1d16Twb_fixed:
2475 case ARM::VLD1d32Twb_fixed:
2476 case ARM::VLD1d64Twb_fixed:
2477 case ARM::VLD1d8Qwb_fixed:
2478 case ARM::VLD1d16Qwb_fixed:
2479 case ARM::VLD1d32Qwb_fixed:
2480 case ARM::VLD1d64Qwb_fixed:
2481 case ARM::VLD1d8wb_register:
2482 case ARM::VLD1d16wb_register:
2483 case ARM::VLD1d32wb_register:
2484 case ARM::VLD1d64wb_register:
2485 case ARM::VLD1q8wb_fixed:
2486 case ARM::VLD1q16wb_fixed:
2487 case ARM::VLD1q32wb_fixed:
2488 case ARM::VLD1q64wb_fixed:
2489 case ARM::VLD1q8wb_register:
2490 case ARM::VLD1q16wb_register:
2491 case ARM::VLD1q32wb_register:
2492 case ARM::VLD1q64wb_register:
2493 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2494 // variant encodes Rm == 0xf. Anything else is a register offset post-
2495 // increment and we need to add the register operand to the instruction.
2496 if (Rm != 0xD && Rm != 0xF &&
2497 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2498 return MCDisassembler::Fail;
2500 case ARM::VLD2d8wb_fixed:
2501 case ARM::VLD2d16wb_fixed:
2502 case ARM::VLD2d32wb_fixed:
2503 case ARM::VLD2b8wb_fixed:
2504 case ARM::VLD2b16wb_fixed:
2505 case ARM::VLD2b32wb_fixed:
2506 case ARM::VLD2q8wb_fixed:
2507 case ARM::VLD2q16wb_fixed:
2508 case ARM::VLD2q32wb_fixed:
2515 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2516 uint64_t Address, const void *Decoder) {
2517 unsigned type = fieldFromInstruction(Insn, 8, 4);
2518 unsigned align = fieldFromInstruction(Insn, 4, 2);
2519 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2520 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2521 if (type == 10 && align == 3) return MCDisassembler::Fail;
2523 unsigned load = fieldFromInstruction(Insn, 21, 1);
2524 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2525 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2528 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2529 uint64_t Address, const void *Decoder) {
2530 unsigned size = fieldFromInstruction(Insn, 6, 2);
2531 if (size == 3) return MCDisassembler::Fail;
2533 unsigned type = fieldFromInstruction(Insn, 8, 4);
2534 unsigned align = fieldFromInstruction(Insn, 4, 2);
2535 if (type == 8 && align == 3) return MCDisassembler::Fail;
2536 if (type == 9 && align == 3) return MCDisassembler::Fail;
2538 unsigned load = fieldFromInstruction(Insn, 21, 1);
2539 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2540 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2543 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2544 uint64_t Address, const void *Decoder) {
2545 unsigned size = fieldFromInstruction(Insn, 6, 2);
2546 if (size == 3) return MCDisassembler::Fail;
2548 unsigned align = fieldFromInstruction(Insn, 4, 2);
2549 if (align & 2) return MCDisassembler::Fail;
2551 unsigned load = fieldFromInstruction(Insn, 21, 1);
2552 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2553 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2556 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2557 uint64_t Address, const void *Decoder) {
2558 unsigned size = fieldFromInstruction(Insn, 6, 2);
2559 if (size == 3) return MCDisassembler::Fail;
2561 unsigned load = fieldFromInstruction(Insn, 21, 1);
2562 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2563 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2566 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2567 uint64_t Address, const void *Decoder) {
2568 DecodeStatus S = MCDisassembler::Success;
2570 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2571 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2572 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2573 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2574 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2575 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2577 // Writeback Operand
2578 switch (Inst.getOpcode()) {
2579 case ARM::VST1d8wb_fixed:
2580 case ARM::VST1d16wb_fixed:
2581 case ARM::VST1d32wb_fixed:
2582 case ARM::VST1d64wb_fixed:
2583 case ARM::VST1d8wb_register:
2584 case ARM::VST1d16wb_register:
2585 case ARM::VST1d32wb_register:
2586 case ARM::VST1d64wb_register:
2587 case ARM::VST1q8wb_fixed:
2588 case ARM::VST1q16wb_fixed:
2589 case ARM::VST1q32wb_fixed:
2590 case ARM::VST1q64wb_fixed:
2591 case ARM::VST1q8wb_register:
2592 case ARM::VST1q16wb_register:
2593 case ARM::VST1q32wb_register:
2594 case ARM::VST1q64wb_register:
2595 case ARM::VST1d8Twb_fixed:
2596 case ARM::VST1d16Twb_fixed:
2597 case ARM::VST1d32Twb_fixed:
2598 case ARM::VST1d64Twb_fixed:
2599 case ARM::VST1d8Twb_register:
2600 case ARM::VST1d16Twb_register:
2601 case ARM::VST1d32Twb_register:
2602 case ARM::VST1d64Twb_register:
2603 case ARM::VST1d8Qwb_fixed:
2604 case ARM::VST1d16Qwb_fixed:
2605 case ARM::VST1d32Qwb_fixed:
2606 case ARM::VST1d64Qwb_fixed:
2607 case ARM::VST1d8Qwb_register:
2608 case ARM::VST1d16Qwb_register:
2609 case ARM::VST1d32Qwb_register:
2610 case ARM::VST1d64Qwb_register:
2611 case ARM::VST2d8wb_fixed:
2612 case ARM::VST2d16wb_fixed:
2613 case ARM::VST2d32wb_fixed:
2614 case ARM::VST2d8wb_register:
2615 case ARM::VST2d16wb_register:
2616 case ARM::VST2d32wb_register:
2617 case ARM::VST2q8wb_fixed:
2618 case ARM::VST2q16wb_fixed:
2619 case ARM::VST2q32wb_fixed:
2620 case ARM::VST2q8wb_register:
2621 case ARM::VST2q16wb_register:
2622 case ARM::VST2q32wb_register:
2623 case ARM::VST2b8wb_fixed:
2624 case ARM::VST2b16wb_fixed:
2625 case ARM::VST2b32wb_fixed:
2626 case ARM::VST2b8wb_register:
2627 case ARM::VST2b16wb_register:
2628 case ARM::VST2b32wb_register:
2630 return MCDisassembler::Fail;
2631 Inst.addOperand(MCOperand::CreateImm(0));
2633 case ARM::VST3d8_UPD:
2634 case ARM::VST3d16_UPD:
2635 case ARM::VST3d32_UPD:
2636 case ARM::VST3q8_UPD:
2637 case ARM::VST3q16_UPD:
2638 case ARM::VST3q32_UPD:
2639 case ARM::VST4d8_UPD:
2640 case ARM::VST4d16_UPD:
2641 case ARM::VST4d32_UPD:
2642 case ARM::VST4q8_UPD:
2643 case ARM::VST4q16_UPD:
2644 case ARM::VST4q32_UPD:
2645 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2646 return MCDisassembler::Fail;
2652 // AddrMode6 Base (register+alignment)
2653 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2654 return MCDisassembler::Fail;
2656 // AddrMode6 Offset (register)
2657 switch (Inst.getOpcode()) {
2660 Inst.addOperand(MCOperand::CreateReg(0));
2661 else if (Rm != 0xF) {
2662 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2663 return MCDisassembler::Fail;
2666 case ARM::VST1d8wb_fixed:
2667 case ARM::VST1d16wb_fixed:
2668 case ARM::VST1d32wb_fixed:
2669 case ARM::VST1d64wb_fixed:
2670 case ARM::VST1q8wb_fixed:
2671 case ARM::VST1q16wb_fixed:
2672 case ARM::VST1q32wb_fixed:
2673 case ARM::VST1q64wb_fixed:
2674 case ARM::VST1d8Twb_fixed:
2675 case ARM::VST1d16Twb_fixed:
2676 case ARM::VST1d32Twb_fixed:
2677 case ARM::VST1d64Twb_fixed:
2678 case ARM::VST1d8Qwb_fixed:
2679 case ARM::VST1d16Qwb_fixed:
2680 case ARM::VST1d32Qwb_fixed:
2681 case ARM::VST1d64Qwb_fixed:
2682 case ARM::VST2d8wb_fixed:
2683 case ARM::VST2d16wb_fixed:
2684 case ARM::VST2d32wb_fixed:
2685 case ARM::VST2q8wb_fixed:
2686 case ARM::VST2q16wb_fixed:
2687 case ARM::VST2q32wb_fixed:
2688 case ARM::VST2b8wb_fixed:
2689 case ARM::VST2b16wb_fixed:
2690 case ARM::VST2b32wb_fixed:
2695 // First input register
2696 switch (Inst.getOpcode()) {
2701 case ARM::VST1q16wb_fixed:
2702 case ARM::VST1q16wb_register:
2703 case ARM::VST1q32wb_fixed:
2704 case ARM::VST1q32wb_register:
2705 case ARM::VST1q64wb_fixed:
2706 case ARM::VST1q64wb_register:
2707 case ARM::VST1q8wb_fixed:
2708 case ARM::VST1q8wb_register:
2712 case ARM::VST2d16wb_fixed:
2713 case ARM::VST2d16wb_register:
2714 case ARM::VST2d32wb_fixed:
2715 case ARM::VST2d32wb_register:
2716 case ARM::VST2d8wb_fixed:
2717 case ARM::VST2d8wb_register:
2718 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2719 return MCDisassembler::Fail;
2724 case ARM::VST2b16wb_fixed:
2725 case ARM::VST2b16wb_register:
2726 case ARM::VST2b32wb_fixed:
2727 case ARM::VST2b32wb_register:
2728 case ARM::VST2b8wb_fixed:
2729 case ARM::VST2b8wb_register:
2730 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2731 return MCDisassembler::Fail;
2734 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2735 return MCDisassembler::Fail;
2738 // Second input register
2739 switch (Inst.getOpcode()) {
2743 case ARM::VST3d8_UPD:
2744 case ARM::VST3d16_UPD:
2745 case ARM::VST3d32_UPD:
2749 case ARM::VST4d8_UPD:
2750 case ARM::VST4d16_UPD:
2751 case ARM::VST4d32_UPD:
2752 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2753 return MCDisassembler::Fail;
2758 case ARM::VST3q8_UPD:
2759 case ARM::VST3q16_UPD:
2760 case ARM::VST3q32_UPD:
2764 case ARM::VST4q8_UPD:
2765 case ARM::VST4q16_UPD:
2766 case ARM::VST4q32_UPD:
2767 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2768 return MCDisassembler::Fail;
2774 // Third input register
2775 switch (Inst.getOpcode()) {
2779 case ARM::VST3d8_UPD:
2780 case ARM::VST3d16_UPD:
2781 case ARM::VST3d32_UPD:
2785 case ARM::VST4d8_UPD:
2786 case ARM::VST4d16_UPD:
2787 case ARM::VST4d32_UPD:
2788 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2789 return MCDisassembler::Fail;
2794 case ARM::VST3q8_UPD:
2795 case ARM::VST3q16_UPD:
2796 case ARM::VST3q32_UPD:
2800 case ARM::VST4q8_UPD:
2801 case ARM::VST4q16_UPD:
2802 case ARM::VST4q32_UPD:
2803 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2804 return MCDisassembler::Fail;
2810 // Fourth input register
2811 switch (Inst.getOpcode()) {
2815 case ARM::VST4d8_UPD:
2816 case ARM::VST4d16_UPD:
2817 case ARM::VST4d32_UPD:
2818 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2819 return MCDisassembler::Fail;
2824 case ARM::VST4q8_UPD:
2825 case ARM::VST4q16_UPD:
2826 case ARM::VST4q32_UPD:
2827 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2828 return MCDisassembler::Fail;
2837 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2838 uint64_t Address, const void *Decoder) {
2839 DecodeStatus S = MCDisassembler::Success;
2841 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2842 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2843 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2844 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2845 unsigned align = fieldFromInstruction(Insn, 4, 1);
2846 unsigned size = fieldFromInstruction(Insn, 6, 2);
2848 if (size == 0 && align == 1)
2849 return MCDisassembler::Fail;
2850 align *= (1 << size);
2852 switch (Inst.getOpcode()) {
2853 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2854 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2855 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2856 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2857 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2858 return MCDisassembler::Fail;
2861 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2862 return MCDisassembler::Fail;
2866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2867 return MCDisassembler::Fail;
2870 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2871 return MCDisassembler::Fail;
2872 Inst.addOperand(MCOperand::CreateImm(align));
2874 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2875 // variant encodes Rm == 0xf. Anything else is a register offset post-
2876 // increment and we need to add the register operand to the instruction.
2877 if (Rm != 0xD && Rm != 0xF &&
2878 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2879 return MCDisassembler::Fail;
2884 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2885 uint64_t Address, const void *Decoder) {
2886 DecodeStatus S = MCDisassembler::Success;
2888 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2889 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2890 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2891 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2892 unsigned align = fieldFromInstruction(Insn, 4, 1);
2893 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2896 switch (Inst.getOpcode()) {
2897 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2898 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2899 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2900 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2901 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2902 return MCDisassembler::Fail;
2904 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2905 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2906 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2907 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2908 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2909 return MCDisassembler::Fail;
2912 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2913 return MCDisassembler::Fail;
2918 Inst.addOperand(MCOperand::CreateImm(0));
2920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2921 return MCDisassembler::Fail;
2922 Inst.addOperand(MCOperand::CreateImm(align));
2924 if (Rm != 0xD && Rm != 0xF) {
2925 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2926 return MCDisassembler::Fail;
2932 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2933 uint64_t Address, const void *Decoder) {
2934 DecodeStatus S = MCDisassembler::Success;
2936 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2937 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2938 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2939 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2940 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2942 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2943 return MCDisassembler::Fail;
2944 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2945 return MCDisassembler::Fail;
2946 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2947 return MCDisassembler::Fail;
2949 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2950 return MCDisassembler::Fail;
2953 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2954 return MCDisassembler::Fail;
2955 Inst.addOperand(MCOperand::CreateImm(0));
2958 Inst.addOperand(MCOperand::CreateReg(0));
2959 else if (Rm != 0xF) {
2960 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2961 return MCDisassembler::Fail;
2967 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2968 uint64_t Address, const void *Decoder) {
2969 DecodeStatus S = MCDisassembler::Success;
2971 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2972 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2973 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2974 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2975 unsigned size = fieldFromInstruction(Insn, 6, 2);
2976 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2977 unsigned align = fieldFromInstruction(Insn, 4, 1);
2981 return MCDisassembler::Fail;
2994 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2995 return MCDisassembler::Fail;
2996 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2997 return MCDisassembler::Fail;
2998 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2999 return MCDisassembler::Fail;
3000 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3001 return MCDisassembler::Fail;
3003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3004 return MCDisassembler::Fail;
3007 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3008 return MCDisassembler::Fail;
3009 Inst.addOperand(MCOperand::CreateImm(align));
3012 Inst.addOperand(MCOperand::CreateReg(0));
3013 else if (Rm != 0xF) {
3014 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3015 return MCDisassembler::Fail;
3022 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3023 uint64_t Address, const void *Decoder) {
3024 DecodeStatus S = MCDisassembler::Success;
3026 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3027 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3028 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3029 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3030 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3031 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3032 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3033 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3036 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3037 return MCDisassembler::Fail;
3039 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3040 return MCDisassembler::Fail;
3043 Inst.addOperand(MCOperand::CreateImm(imm));
3045 switch (Inst.getOpcode()) {
3046 case ARM::VORRiv4i16:
3047 case ARM::VORRiv2i32:
3048 case ARM::VBICiv4i16:
3049 case ARM::VBICiv2i32:
3050 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3051 return MCDisassembler::Fail;
3053 case ARM::VORRiv8i16:
3054 case ARM::VORRiv4i32:
3055 case ARM::VBICiv8i16:
3056 case ARM::VBICiv4i32:
3057 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3058 return MCDisassembler::Fail;
3067 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3068 uint64_t Address, const void *Decoder) {
3069 DecodeStatus S = MCDisassembler::Success;
3071 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3072 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3073 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3074 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3075 unsigned size = fieldFromInstruction(Insn, 18, 2);
3077 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3078 return MCDisassembler::Fail;
3079 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3080 return MCDisassembler::Fail;
3081 Inst.addOperand(MCOperand::CreateImm(8 << size));
3086 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3087 uint64_t Address, const void *Decoder) {
3088 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3089 return MCDisassembler::Success;
3092 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3093 uint64_t Address, const void *Decoder) {
3094 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3095 return MCDisassembler::Success;
3098 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3099 uint64_t Address, const void *Decoder) {
3100 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3101 return MCDisassembler::Success;
3104 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3105 uint64_t Address, const void *Decoder) {
3106 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3107 return MCDisassembler::Success;
3110 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3111 uint64_t Address, const void *Decoder) {
3112 DecodeStatus S = MCDisassembler::Success;
3114 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3115 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3116 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3117 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3118 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3119 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3120 unsigned op = fieldFromInstruction(Insn, 6, 1);
3122 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3123 return MCDisassembler::Fail;
3125 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3126 return MCDisassembler::Fail; // Writeback
3129 switch (Inst.getOpcode()) {
3132 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3133 return MCDisassembler::Fail;
3136 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3137 return MCDisassembler::Fail;
3140 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3141 return MCDisassembler::Fail;
3146 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3147 uint64_t Address, const void *Decoder) {
3148 DecodeStatus S = MCDisassembler::Success;
3150 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3151 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3153 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3154 return MCDisassembler::Fail;
3156 switch(Inst.getOpcode()) {
3158 return MCDisassembler::Fail;
3160 break; // tADR does not explicitly represent the PC as an operand.
3162 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3166 Inst.addOperand(MCOperand::CreateImm(imm));
3170 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3171 uint64_t Address, const void *Decoder) {
3172 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3173 true, 2, Inst, Decoder))
3174 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3175 return MCDisassembler::Success;
3178 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3179 uint64_t Address, const void *Decoder) {
3180 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3181 true, 4, Inst, Decoder))
3182 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3183 return MCDisassembler::Success;
3186 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3187 uint64_t Address, const void *Decoder) {
3188 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3189 true, 2, Inst, Decoder))
3190 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3191 return MCDisassembler::Success;
3194 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3195 uint64_t Address, const void *Decoder) {
3196 DecodeStatus S = MCDisassembler::Success;
3198 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3199 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3201 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3202 return MCDisassembler::Fail;
3203 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3204 return MCDisassembler::Fail;
3209 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3210 uint64_t Address, const void *Decoder) {
3211 DecodeStatus S = MCDisassembler::Success;
3213 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3214 unsigned imm = fieldFromInstruction(Val, 3, 5);
3216 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3217 return MCDisassembler::Fail;
3218 Inst.addOperand(MCOperand::CreateImm(imm));
3223 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3224 uint64_t Address, const void *Decoder) {
3225 unsigned imm = Val << 2;
3227 Inst.addOperand(MCOperand::CreateImm(imm));
3228 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3230 return MCDisassembler::Success;
3233 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3234 uint64_t Address, const void *Decoder) {
3235 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3236 Inst.addOperand(MCOperand::CreateImm(Val));
3238 return MCDisassembler::Success;
3241 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3242 uint64_t Address, const void *Decoder) {
3243 DecodeStatus S = MCDisassembler::Success;
3245 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3246 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3247 unsigned imm = fieldFromInstruction(Val, 0, 2);
3249 // Thumb stores cannot use PC as dest register.
3250 switch (Inst.getOpcode()) {
3255 return MCDisassembler::Fail;
3260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3261 return MCDisassembler::Fail;
3262 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3263 return MCDisassembler::Fail;
3264 Inst.addOperand(MCOperand::CreateImm(imm));
3269 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3270 uint64_t Address, const void *Decoder) {
3271 DecodeStatus S = MCDisassembler::Success;
3273 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3274 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3276 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3278 bool hasMP = featureBits & ARM::FeatureMP;
3279 bool hasV7Ops = featureBits & ARM::HasV7Ops;
3282 switch (Inst.getOpcode()) {
3284 Inst.setOpcode(ARM::t2LDRBpci);
3287 Inst.setOpcode(ARM::t2LDRHpci);
3290 Inst.setOpcode(ARM::t2LDRSHpci);
3293 Inst.setOpcode(ARM::t2LDRSBpci);
3296 Inst.setOpcode(ARM::t2LDRpci);
3299 Inst.setOpcode(ARM::t2PLDpci);
3302 Inst.setOpcode(ARM::t2PLIpci);
3305 return MCDisassembler::Fail;
3308 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3312 switch (Inst.getOpcode()) {
3314 return MCDisassembler::Fail;
3316 Inst.setOpcode(ARM::t2PLDWs);
3319 Inst.setOpcode(ARM::t2PLIs);
3325 switch (Inst.getOpcode()) {
3330 return MCDisassembler::Fail;
3333 if (!hasV7Ops || !hasMP)
3334 return MCDisassembler::Fail;
3337 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3338 return MCDisassembler::Fail;
3341 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3342 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3343 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3344 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3345 return MCDisassembler::Fail;
3350 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3351 uint64_t Address, const void* Decoder) {
3352 DecodeStatus S = MCDisassembler::Success;
3354 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3355 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3356 unsigned U = fieldFromInstruction(Insn, 9, 1);
3357 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3360 unsigned add = fieldFromInstruction(Insn, 9, 1);
3362 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3364 bool hasMP = featureBits & ARM::FeatureMP;
3365 bool hasV7Ops = featureBits & ARM::HasV7Ops;
3368 switch (Inst.getOpcode()) {
3370 Inst.setOpcode(ARM::t2LDRpci);
3373 Inst.setOpcode(ARM::t2LDRBpci);
3375 case ARM::t2LDRSBi8:
3376 Inst.setOpcode(ARM::t2LDRSBpci);
3379 Inst.setOpcode(ARM::t2LDRHpci);
3381 case ARM::t2LDRSHi8:
3382 Inst.setOpcode(ARM::t2LDRSHpci);
3385 Inst.setOpcode(ARM::t2PLDpci);
3388 Inst.setOpcode(ARM::t2PLIpci);
3391 return MCDisassembler::Fail;
3393 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3397 switch (Inst.getOpcode()) {
3398 case ARM::t2LDRSHi8:
3399 return MCDisassembler::Fail;
3402 Inst.setOpcode(ARM::t2PLDWi8);
3404 case ARM::t2LDRSBi8:
3405 Inst.setOpcode(ARM::t2PLIi8);
3412 switch (Inst.getOpcode()) {
3417 return MCDisassembler::Fail;
3420 if (!hasV7Ops || !hasMP)
3421 return MCDisassembler::Fail;
3424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3425 return MCDisassembler::Fail;
3428 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3429 return MCDisassembler::Fail;
3433 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3434 uint64_t Address, const void* Decoder) {
3435 DecodeStatus S = MCDisassembler::Success;
3437 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3438 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3439 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3442 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3444 bool hasMP = (featureBits & ARM::FeatureMP);
3445 bool hasV7Ops = (featureBits & ARM::HasV7Ops);
3448 switch (Inst.getOpcode()) {
3450 Inst.setOpcode(ARM::t2LDRpci);
3452 case ARM::t2LDRHi12:
3453 Inst.setOpcode(ARM::t2LDRHpci);
3455 case ARM::t2LDRSHi12:
3456 Inst.setOpcode(ARM::t2LDRSHpci);
3458 case ARM::t2LDRBi12:
3459 Inst.setOpcode(ARM::t2LDRBpci);
3461 case ARM::t2LDRSBi12:
3462 Inst.setOpcode(ARM::t2LDRSBpci);
3465 Inst.setOpcode(ARM::t2PLDpci);
3468 Inst.setOpcode(ARM::t2PLIpci);
3471 return MCDisassembler::Fail;
3473 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3477 switch (Inst.getOpcode()) {
3478 case ARM::t2LDRSHi12:
3479 return MCDisassembler::Fail;
3480 case ARM::t2LDRHi12:
3481 Inst.setOpcode(ARM::t2PLDWi12);
3483 case ARM::t2LDRSBi12:
3484 Inst.setOpcode(ARM::t2PLIi12);
3491 switch (Inst.getOpcode()) {
3496 return MCDisassembler::Fail;
3498 case ARM::t2PLDWi12:
3499 if (!hasV7Ops || !hasMP)
3500 return MCDisassembler::Fail;
3503 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3504 return MCDisassembler::Fail;
3507 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3508 return MCDisassembler::Fail;
3512 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3513 uint64_t Address, const void* Decoder) {
3514 DecodeStatus S = MCDisassembler::Success;
3516 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3517 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3518 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3522 switch (Inst.getOpcode()) {
3524 Inst.setOpcode(ARM::t2LDRpci);
3527 Inst.setOpcode(ARM::t2LDRBpci);
3530 Inst.setOpcode(ARM::t2LDRHpci);
3533 Inst.setOpcode(ARM::t2LDRSBpci);
3536 Inst.setOpcode(ARM::t2LDRSHpci);
3539 return MCDisassembler::Fail;
3541 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3544 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3545 return MCDisassembler::Fail;
3546 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3547 return MCDisassembler::Fail;
3551 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3552 uint64_t Address, const void* Decoder) {
3553 DecodeStatus S = MCDisassembler::Success;
3555 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3556 unsigned U = fieldFromInstruction(Insn, 23, 1);
3557 int imm = fieldFromInstruction(Insn, 0, 12);
3559 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3561 bool hasV7Ops = (featureBits & ARM::HasV7Ops);
3564 switch (Inst.getOpcode()) {
3565 case ARM::t2LDRBpci:
3566 case ARM::t2LDRHpci:
3567 Inst.setOpcode(ARM::t2PLDpci);
3569 case ARM::t2LDRSBpci:
3570 Inst.setOpcode(ARM::t2PLIpci);
3572 case ARM::t2LDRSHpci:
3573 return MCDisassembler::Fail;
3579 switch(Inst.getOpcode()) {
3584 return MCDisassembler::Fail;
3587 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3588 return MCDisassembler::Fail;
3592 // Special case for #-0.
3598 Inst.addOperand(MCOperand::CreateImm(imm));
3603 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3604 uint64_t Address, const void *Decoder) {
3606 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3608 int imm = Val & 0xFF;
3610 if (!(Val & 0x100)) imm *= -1;
3611 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3614 return MCDisassembler::Success;
3617 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3618 uint64_t Address, const void *Decoder) {
3619 DecodeStatus S = MCDisassembler::Success;
3621 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3622 unsigned imm = fieldFromInstruction(Val, 0, 9);
3624 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3625 return MCDisassembler::Fail;
3626 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3627 return MCDisassembler::Fail;
3632 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3633 uint64_t Address, const void *Decoder) {
3634 DecodeStatus S = MCDisassembler::Success;
3636 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3637 unsigned imm = fieldFromInstruction(Val, 0, 8);
3639 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3640 return MCDisassembler::Fail;
3642 Inst.addOperand(MCOperand::CreateImm(imm));
3647 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3648 uint64_t Address, const void *Decoder) {
3649 int imm = Val & 0xFF;
3652 else if (!(Val & 0x100))
3654 Inst.addOperand(MCOperand::CreateImm(imm));
3656 return MCDisassembler::Success;
3660 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3661 uint64_t Address, const void *Decoder) {
3662 DecodeStatus S = MCDisassembler::Success;
3664 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3665 unsigned imm = fieldFromInstruction(Val, 0, 9);
3667 // Thumb stores cannot use PC as dest register.
3668 switch (Inst.getOpcode()) {
3676 return MCDisassembler::Fail;
3682 // Some instructions always use an additive offset.
3683 switch (Inst.getOpcode()) {
3698 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3699 return MCDisassembler::Fail;
3700 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3701 return MCDisassembler::Fail;
3706 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3707 uint64_t Address, const void *Decoder) {
3708 DecodeStatus S = MCDisassembler::Success;
3710 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3711 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3712 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3713 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3715 unsigned load = fieldFromInstruction(Insn, 20, 1);
3718 switch (Inst.getOpcode()) {
3719 case ARM::t2LDR_PRE:
3720 case ARM::t2LDR_POST:
3721 Inst.setOpcode(ARM::t2LDRpci);
3723 case ARM::t2LDRB_PRE:
3724 case ARM::t2LDRB_POST:
3725 Inst.setOpcode(ARM::t2LDRBpci);
3727 case ARM::t2LDRH_PRE:
3728 case ARM::t2LDRH_POST:
3729 Inst.setOpcode(ARM::t2LDRHpci);
3731 case ARM::t2LDRSB_PRE:
3732 case ARM::t2LDRSB_POST:
3734 Inst.setOpcode(ARM::t2PLIpci);
3736 Inst.setOpcode(ARM::t2LDRSBpci);
3738 case ARM::t2LDRSH_PRE:
3739 case ARM::t2LDRSH_POST:
3740 Inst.setOpcode(ARM::t2LDRSHpci);
3743 return MCDisassembler::Fail;
3745 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3749 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3750 return MCDisassembler::Fail;
3753 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3754 return MCDisassembler::Fail;
3757 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3758 return MCDisassembler::Fail;
3761 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3762 return MCDisassembler::Fail;
3767 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3768 uint64_t Address, const void *Decoder) {
3769 DecodeStatus S = MCDisassembler::Success;
3771 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3772 unsigned imm = fieldFromInstruction(Val, 0, 12);
3774 // Thumb stores cannot use PC as dest register.
3775 switch (Inst.getOpcode()) {
3777 case ARM::t2STRBi12:
3778 case ARM::t2STRHi12:
3780 return MCDisassembler::Fail;
3785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3786 return MCDisassembler::Fail;
3787 Inst.addOperand(MCOperand::CreateImm(imm));
3793 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3794 uint64_t Address, const void *Decoder) {
3795 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3797 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3798 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3799 Inst.addOperand(MCOperand::CreateImm(imm));
3801 return MCDisassembler::Success;
3804 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3805 uint64_t Address, const void *Decoder) {
3806 DecodeStatus S = MCDisassembler::Success;
3808 if (Inst.getOpcode() == ARM::tADDrSP) {
3809 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3810 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3812 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3813 return MCDisassembler::Fail;
3814 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3815 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3816 return MCDisassembler::Fail;
3817 } else if (Inst.getOpcode() == ARM::tADDspr) {
3818 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3820 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3821 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3822 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3823 return MCDisassembler::Fail;
3829 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3830 uint64_t Address, const void *Decoder) {
3831 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3832 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3834 Inst.addOperand(MCOperand::CreateImm(imod));
3835 Inst.addOperand(MCOperand::CreateImm(flags));
3837 return MCDisassembler::Success;
3840 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3841 uint64_t Address, const void *Decoder) {
3842 DecodeStatus S = MCDisassembler::Success;
3843 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3844 unsigned add = fieldFromInstruction(Insn, 4, 1);
3846 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3847 return MCDisassembler::Fail;
3848 Inst.addOperand(MCOperand::CreateImm(add));
3853 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3854 uint64_t Address, const void *Decoder) {
3855 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3856 // Note only one trailing zero not two. Also the J1 and J2 values are from
3857 // the encoded instruction. So here change to I1 and I2 values via:
3858 // I1 = NOT(J1 EOR S);
3859 // I2 = NOT(J2 EOR S);
3860 // and build the imm32 with two trailing zeros as documented:
3861 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3862 unsigned S = (Val >> 23) & 1;
3863 unsigned J1 = (Val >> 22) & 1;
3864 unsigned J2 = (Val >> 21) & 1;
3865 unsigned I1 = !(J1 ^ S);
3866 unsigned I2 = !(J2 ^ S);
3867 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3868 int imm32 = SignExtend32<25>(tmp << 1);
3870 if (!tryAddingSymbolicOperand(Address,
3871 (Address & ~2u) + imm32 + 4,
3872 true, 4, Inst, Decoder))
3873 Inst.addOperand(MCOperand::CreateImm(imm32));
3874 return MCDisassembler::Success;
3877 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3878 uint64_t Address, const void *Decoder) {
3879 if (Val == 0xA || Val == 0xB)
3880 return MCDisassembler::Fail;
3882 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3884 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3885 return MCDisassembler::Fail;
3887 Inst.addOperand(MCOperand::CreateImm(Val));
3888 return MCDisassembler::Success;
3892 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3893 uint64_t Address, const void *Decoder) {
3894 DecodeStatus S = MCDisassembler::Success;
3896 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3897 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3899 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3900 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3901 return MCDisassembler::Fail;
3902 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3903 return MCDisassembler::Fail;
3908 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3909 uint64_t Address, const void *Decoder) {
3910 DecodeStatus S = MCDisassembler::Success;
3912 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3913 if (pred == 0xE || pred == 0xF) {
3914 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3917 return MCDisassembler::Fail;
3919 Inst.setOpcode(ARM::t2DSB);
3922 Inst.setOpcode(ARM::t2DMB);
3925 Inst.setOpcode(ARM::t2ISB);
3929 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3930 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3933 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3934 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3935 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3936 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3937 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3939 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3940 return MCDisassembler::Fail;
3941 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3942 return MCDisassembler::Fail;
3947 // Decode a shifted immediate operand. These basically consist
3948 // of an 8-bit value, and a 4-bit directive that specifies either
3949 // a splat operation or a rotation.
3950 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3951 uint64_t Address, const void *Decoder) {
3952 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3954 unsigned byte = fieldFromInstruction(Val, 8, 2);
3955 unsigned imm = fieldFromInstruction(Val, 0, 8);
3958 Inst.addOperand(MCOperand::CreateImm(imm));
3961 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3964 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3967 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3972 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3973 unsigned rot = fieldFromInstruction(Val, 7, 5);
3974 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3975 Inst.addOperand(MCOperand::CreateImm(imm));
3978 return MCDisassembler::Success;
3982 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3983 uint64_t Address, const void *Decoder){
3984 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3985 true, 2, Inst, Decoder))
3986 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3987 return MCDisassembler::Success;
3990 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3991 uint64_t Address, const void *Decoder){
3992 // Val is passed in as S:J1:J2:imm10:imm11
3993 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3994 // the encoded instruction. So here change to I1 and I2 values via:
3995 // I1 = NOT(J1 EOR S);
3996 // I2 = NOT(J2 EOR S);
3997 // and build the imm32 with one trailing zero as documented:
3998 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3999 unsigned S = (Val >> 23) & 1;
4000 unsigned J1 = (Val >> 22) & 1;
4001 unsigned J2 = (Val >> 21) & 1;
4002 unsigned I1 = !(J1 ^ S);
4003 unsigned I2 = !(J2 ^ S);
4004 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
4005 int imm32 = SignExtend32<25>(tmp << 1);
4007 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
4008 true, 4, Inst, Decoder))
4009 Inst.addOperand(MCOperand::CreateImm(imm32));
4010 return MCDisassembler::Success;
4013 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4014 uint64_t Address, const void *Decoder) {
4016 return MCDisassembler::Fail;
4018 Inst.addOperand(MCOperand::CreateImm(Val));
4019 return MCDisassembler::Success;
4022 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4023 uint64_t Address, const void *Decoder) {
4025 return MCDisassembler::Fail;
4027 Inst.addOperand(MCOperand::CreateImm(Val));
4028 return MCDisassembler::Success;
4031 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
4032 uint64_t Address, const void *Decoder) {
4033 DecodeStatus S = MCDisassembler::Success;
4034 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
4036 if (FeatureBits & ARM::FeatureMClass) {
4037 unsigned ValLow = Val & 0xff;
4039 // Validate the SYSm value first.
4054 case 18: // basepri_max
4055 case 19: // faultmask
4056 if (!(FeatureBits & ARM::HasV7Ops))
4057 // Values basepri, basepri_max and faultmask are only valid for v7m.
4058 return MCDisassembler::Fail;
4061 return MCDisassembler::Fail;
4064 if (Inst.getOpcode() == ARM::t2MSR_M) {
4065 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4066 if (!(FeatureBits & ARM::HasV7Ops)) {
4067 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4070 S = MCDisassembler::SoftFail;
4073 // The ARMv7-M architecture stores an additional 2-bit mask value in
4074 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4075 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4076 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4077 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4078 // only if the processor includes the DSP extension.
4079 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4080 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
4081 S = MCDisassembler::SoftFail;
4087 return MCDisassembler::Fail;
4089 Inst.addOperand(MCOperand::CreateImm(Val));
4093 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4094 uint64_t Address, const void *Decoder) {
4096 unsigned R = fieldFromInstruction(Val, 5, 1);
4097 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4099 // The table of encodings for these banked registers comes from B9.2.3 of the
4100 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4101 // neater. So by fiat, these values are UNPREDICTABLE:
4103 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4104 SysM == 0x1a || SysM == 0x1b)
4105 return MCDisassembler::SoftFail;
4107 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4108 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4109 return MCDisassembler::SoftFail;
4112 Inst.addOperand(MCOperand::CreateImm(Val));
4113 return MCDisassembler::Success;
4116 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4117 uint64_t Address, const void *Decoder) {
4118 DecodeStatus S = MCDisassembler::Success;
4120 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4121 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4122 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4125 S = MCDisassembler::SoftFail;
4127 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4128 return MCDisassembler::Fail;
4129 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4130 return MCDisassembler::Fail;
4131 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4132 return MCDisassembler::Fail;
4137 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4138 uint64_t Address, const void *Decoder){
4139 DecodeStatus S = MCDisassembler::Success;
4141 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4142 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4143 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4144 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4146 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4147 return MCDisassembler::Fail;
4149 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4150 S = MCDisassembler::SoftFail;
4152 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4153 return MCDisassembler::Fail;
4154 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4155 return MCDisassembler::Fail;
4156 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4157 return MCDisassembler::Fail;
4162 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4163 uint64_t Address, const void *Decoder) {
4164 DecodeStatus S = MCDisassembler::Success;
4166 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4167 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4168 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4169 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4170 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4171 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4173 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4176 return MCDisassembler::Fail;
4177 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4178 return MCDisassembler::Fail;
4179 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4180 return MCDisassembler::Fail;
4181 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4182 return MCDisassembler::Fail;
4187 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4188 uint64_t Address, const void *Decoder) {
4189 DecodeStatus S = MCDisassembler::Success;
4191 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4192 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4193 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4194 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4195 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4196 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4197 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4199 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4200 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4202 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4203 return MCDisassembler::Fail;
4204 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4205 return MCDisassembler::Fail;
4206 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4207 return MCDisassembler::Fail;
4208 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4209 return MCDisassembler::Fail;
4215 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4216 uint64_t Address, const void *Decoder) {
4217 DecodeStatus S = MCDisassembler::Success;
4219 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4220 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4221 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4222 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4223 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4224 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4226 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4228 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4229 return MCDisassembler::Fail;
4230 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4231 return MCDisassembler::Fail;
4232 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4233 return MCDisassembler::Fail;
4234 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4235 return MCDisassembler::Fail;
4240 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4241 uint64_t Address, const void *Decoder) {
4242 DecodeStatus S = MCDisassembler::Success;
4244 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4245 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4246 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4247 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4248 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4249 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4251 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4254 return MCDisassembler::Fail;
4255 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4256 return MCDisassembler::Fail;
4257 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4258 return MCDisassembler::Fail;
4259 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4260 return MCDisassembler::Fail;
4265 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4266 uint64_t Address, const void *Decoder) {
4267 DecodeStatus S = MCDisassembler::Success;
4269 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4270 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4271 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4272 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4273 unsigned size = fieldFromInstruction(Insn, 10, 2);
4279 return MCDisassembler::Fail;
4281 if (fieldFromInstruction(Insn, 4, 1))
4282 return MCDisassembler::Fail; // UNDEFINED
4283 index = fieldFromInstruction(Insn, 5, 3);
4286 if (fieldFromInstruction(Insn, 5, 1))
4287 return MCDisassembler::Fail; // UNDEFINED
4288 index = fieldFromInstruction(Insn, 6, 2);
4289 if (fieldFromInstruction(Insn, 4, 1))
4293 if (fieldFromInstruction(Insn, 6, 1))
4294 return MCDisassembler::Fail; // UNDEFINED
4295 index = fieldFromInstruction(Insn, 7, 1);
4297 switch (fieldFromInstruction(Insn, 4, 2)) {
4303 return MCDisassembler::Fail;
4308 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4309 return MCDisassembler::Fail;
4310 if (Rm != 0xF) { // Writeback
4311 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4312 return MCDisassembler::Fail;
4314 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4315 return MCDisassembler::Fail;
4316 Inst.addOperand(MCOperand::CreateImm(align));
4319 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4320 return MCDisassembler::Fail;
4322 Inst.addOperand(MCOperand::CreateReg(0));
4325 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4326 return MCDisassembler::Fail;
4327 Inst.addOperand(MCOperand::CreateImm(index));
4332 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4333 uint64_t Address, const void *Decoder) {
4334 DecodeStatus S = MCDisassembler::Success;
4336 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4337 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4338 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4339 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4340 unsigned size = fieldFromInstruction(Insn, 10, 2);
4346 return MCDisassembler::Fail;
4348 if (fieldFromInstruction(Insn, 4, 1))
4349 return MCDisassembler::Fail; // UNDEFINED
4350 index = fieldFromInstruction(Insn, 5, 3);
4353 if (fieldFromInstruction(Insn, 5, 1))
4354 return MCDisassembler::Fail; // UNDEFINED
4355 index = fieldFromInstruction(Insn, 6, 2);
4356 if (fieldFromInstruction(Insn, 4, 1))
4360 if (fieldFromInstruction(Insn, 6, 1))
4361 return MCDisassembler::Fail; // UNDEFINED
4362 index = fieldFromInstruction(Insn, 7, 1);
4364 switch (fieldFromInstruction(Insn, 4, 2)) {
4370 return MCDisassembler::Fail;
4375 if (Rm != 0xF) { // Writeback
4376 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4377 return MCDisassembler::Fail;
4379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4380 return MCDisassembler::Fail;
4381 Inst.addOperand(MCOperand::CreateImm(align));
4384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4385 return MCDisassembler::Fail;
4387 Inst.addOperand(MCOperand::CreateReg(0));
4390 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4391 return MCDisassembler::Fail;
4392 Inst.addOperand(MCOperand::CreateImm(index));
4398 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4399 uint64_t Address, const void *Decoder) {
4400 DecodeStatus S = MCDisassembler::Success;
4402 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4403 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4404 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4405 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4406 unsigned size = fieldFromInstruction(Insn, 10, 2);
4413 return MCDisassembler::Fail;
4415 index = fieldFromInstruction(Insn, 5, 3);
4416 if (fieldFromInstruction(Insn, 4, 1))
4420 index = fieldFromInstruction(Insn, 6, 2);
4421 if (fieldFromInstruction(Insn, 4, 1))
4423 if (fieldFromInstruction(Insn, 5, 1))
4427 if (fieldFromInstruction(Insn, 5, 1))
4428 return MCDisassembler::Fail; // UNDEFINED
4429 index = fieldFromInstruction(Insn, 7, 1);
4430 if (fieldFromInstruction(Insn, 4, 1) != 0)
4432 if (fieldFromInstruction(Insn, 6, 1))
4437 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4438 return MCDisassembler::Fail;
4439 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4440 return MCDisassembler::Fail;
4441 if (Rm != 0xF) { // Writeback
4442 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4443 return MCDisassembler::Fail;
4445 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4446 return MCDisassembler::Fail;
4447 Inst.addOperand(MCOperand::CreateImm(align));
4450 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4451 return MCDisassembler::Fail;
4453 Inst.addOperand(MCOperand::CreateReg(0));
4456 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4457 return MCDisassembler::Fail;
4458 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4459 return MCDisassembler::Fail;
4460 Inst.addOperand(MCOperand::CreateImm(index));
4465 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4466 uint64_t Address, const void *Decoder) {
4467 DecodeStatus S = MCDisassembler::Success;
4469 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4470 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4471 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4472 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4473 unsigned size = fieldFromInstruction(Insn, 10, 2);
4480 return MCDisassembler::Fail;
4482 index = fieldFromInstruction(Insn, 5, 3);
4483 if (fieldFromInstruction(Insn, 4, 1))
4487 index = fieldFromInstruction(Insn, 6, 2);
4488 if (fieldFromInstruction(Insn, 4, 1))
4490 if (fieldFromInstruction(Insn, 5, 1))
4494 if (fieldFromInstruction(Insn, 5, 1))
4495 return MCDisassembler::Fail; // UNDEFINED
4496 index = fieldFromInstruction(Insn, 7, 1);
4497 if (fieldFromInstruction(Insn, 4, 1) != 0)
4499 if (fieldFromInstruction(Insn, 6, 1))
4504 if (Rm != 0xF) { // Writeback
4505 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4506 return MCDisassembler::Fail;
4508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4509 return MCDisassembler::Fail;
4510 Inst.addOperand(MCOperand::CreateImm(align));
4513 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4514 return MCDisassembler::Fail;
4516 Inst.addOperand(MCOperand::CreateReg(0));
4519 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4520 return MCDisassembler::Fail;
4521 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4522 return MCDisassembler::Fail;
4523 Inst.addOperand(MCOperand::CreateImm(index));
4529 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4530 uint64_t Address, const void *Decoder) {
4531 DecodeStatus S = MCDisassembler::Success;
4533 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4534 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4535 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4536 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4537 unsigned size = fieldFromInstruction(Insn, 10, 2);
4544 return MCDisassembler::Fail;
4546 if (fieldFromInstruction(Insn, 4, 1))
4547 return MCDisassembler::Fail; // UNDEFINED
4548 index = fieldFromInstruction(Insn, 5, 3);
4551 if (fieldFromInstruction(Insn, 4, 1))
4552 return MCDisassembler::Fail; // UNDEFINED
4553 index = fieldFromInstruction(Insn, 6, 2);
4554 if (fieldFromInstruction(Insn, 5, 1))
4558 if (fieldFromInstruction(Insn, 4, 2))
4559 return MCDisassembler::Fail; // UNDEFINED
4560 index = fieldFromInstruction(Insn, 7, 1);
4561 if (fieldFromInstruction(Insn, 6, 1))
4566 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4567 return MCDisassembler::Fail;
4568 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4569 return MCDisassembler::Fail;
4570 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4571 return MCDisassembler::Fail;
4573 if (Rm != 0xF) { // Writeback
4574 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4575 return MCDisassembler::Fail;
4577 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4578 return MCDisassembler::Fail;
4579 Inst.addOperand(MCOperand::CreateImm(align));
4582 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4583 return MCDisassembler::Fail;
4585 Inst.addOperand(MCOperand::CreateReg(0));
4588 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4589 return MCDisassembler::Fail;
4590 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4591 return MCDisassembler::Fail;
4592 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4593 return MCDisassembler::Fail;
4594 Inst.addOperand(MCOperand::CreateImm(index));
4599 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4600 uint64_t Address, const void *Decoder) {
4601 DecodeStatus S = MCDisassembler::Success;
4603 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4604 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4605 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4606 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4607 unsigned size = fieldFromInstruction(Insn, 10, 2);
4614 return MCDisassembler::Fail;
4616 if (fieldFromInstruction(Insn, 4, 1))
4617 return MCDisassembler::Fail; // UNDEFINED
4618 index = fieldFromInstruction(Insn, 5, 3);
4621 if (fieldFromInstruction(Insn, 4, 1))
4622 return MCDisassembler::Fail; // UNDEFINED
4623 index = fieldFromInstruction(Insn, 6, 2);
4624 if (fieldFromInstruction(Insn, 5, 1))
4628 if (fieldFromInstruction(Insn, 4, 2))
4629 return MCDisassembler::Fail; // UNDEFINED
4630 index = fieldFromInstruction(Insn, 7, 1);
4631 if (fieldFromInstruction(Insn, 6, 1))
4636 if (Rm != 0xF) { // Writeback
4637 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4638 return MCDisassembler::Fail;
4640 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4641 return MCDisassembler::Fail;
4642 Inst.addOperand(MCOperand::CreateImm(align));
4645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4646 return MCDisassembler::Fail;
4648 Inst.addOperand(MCOperand::CreateReg(0));
4651 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4652 return MCDisassembler::Fail;
4653 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4654 return MCDisassembler::Fail;
4655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4656 return MCDisassembler::Fail;
4657 Inst.addOperand(MCOperand::CreateImm(index));
4663 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4664 uint64_t Address, const void *Decoder) {
4665 DecodeStatus S = MCDisassembler::Success;
4667 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4668 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4669 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4670 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4671 unsigned size = fieldFromInstruction(Insn, 10, 2);
4678 return MCDisassembler::Fail;
4680 if (fieldFromInstruction(Insn, 4, 1))
4682 index = fieldFromInstruction(Insn, 5, 3);
4685 if (fieldFromInstruction(Insn, 4, 1))
4687 index = fieldFromInstruction(Insn, 6, 2);
4688 if (fieldFromInstruction(Insn, 5, 1))
4692 switch (fieldFromInstruction(Insn, 4, 2)) {
4696 return MCDisassembler::Fail;
4698 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4701 index = fieldFromInstruction(Insn, 7, 1);
4702 if (fieldFromInstruction(Insn, 6, 1))
4707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4708 return MCDisassembler::Fail;
4709 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4710 return MCDisassembler::Fail;
4711 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4712 return MCDisassembler::Fail;
4713 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4714 return MCDisassembler::Fail;
4716 if (Rm != 0xF) { // Writeback
4717 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4718 return MCDisassembler::Fail;
4720 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4721 return MCDisassembler::Fail;
4722 Inst.addOperand(MCOperand::CreateImm(align));
4725 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4726 return MCDisassembler::Fail;
4728 Inst.addOperand(MCOperand::CreateReg(0));
4731 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4732 return MCDisassembler::Fail;
4733 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4734 return MCDisassembler::Fail;
4735 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4736 return MCDisassembler::Fail;
4737 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4738 return MCDisassembler::Fail;
4739 Inst.addOperand(MCOperand::CreateImm(index));
4744 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4745 uint64_t Address, const void *Decoder) {
4746 DecodeStatus S = MCDisassembler::Success;
4748 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4749 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4750 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4751 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4752 unsigned size = fieldFromInstruction(Insn, 10, 2);
4759 return MCDisassembler::Fail;
4761 if (fieldFromInstruction(Insn, 4, 1))
4763 index = fieldFromInstruction(Insn, 5, 3);
4766 if (fieldFromInstruction(Insn, 4, 1))
4768 index = fieldFromInstruction(Insn, 6, 2);
4769 if (fieldFromInstruction(Insn, 5, 1))
4773 switch (fieldFromInstruction(Insn, 4, 2)) {
4777 return MCDisassembler::Fail;
4779 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4782 index = fieldFromInstruction(Insn, 7, 1);
4783 if (fieldFromInstruction(Insn, 6, 1))
4788 if (Rm != 0xF) { // Writeback
4789 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4790 return MCDisassembler::Fail;
4792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4793 return MCDisassembler::Fail;
4794 Inst.addOperand(MCOperand::CreateImm(align));
4797 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4798 return MCDisassembler::Fail;
4800 Inst.addOperand(MCOperand::CreateReg(0));
4803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4804 return MCDisassembler::Fail;
4805 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4806 return MCDisassembler::Fail;
4807 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4808 return MCDisassembler::Fail;
4809 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4810 return MCDisassembler::Fail;
4811 Inst.addOperand(MCOperand::CreateImm(index));
4816 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4817 uint64_t Address, const void *Decoder) {
4818 DecodeStatus S = MCDisassembler::Success;
4819 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4820 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4821 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4822 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4823 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4825 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4826 S = MCDisassembler::SoftFail;
4828 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4829 return MCDisassembler::Fail;
4830 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4831 return MCDisassembler::Fail;
4832 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4833 return MCDisassembler::Fail;
4834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4835 return MCDisassembler::Fail;
4836 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4837 return MCDisassembler::Fail;
4842 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4843 uint64_t Address, const void *Decoder) {
4844 DecodeStatus S = MCDisassembler::Success;
4845 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4846 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4847 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4848 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4849 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4851 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4852 S = MCDisassembler::SoftFail;
4854 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4855 return MCDisassembler::Fail;
4856 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4857 return MCDisassembler::Fail;
4858 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4859 return MCDisassembler::Fail;
4860 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4861 return MCDisassembler::Fail;
4862 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4863 return MCDisassembler::Fail;
4868 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4869 uint64_t Address, const void *Decoder) {
4870 DecodeStatus S = MCDisassembler::Success;
4871 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4872 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4876 S = MCDisassembler::SoftFail;
4880 return MCDisassembler::Fail;
4882 Inst.addOperand(MCOperand::CreateImm(pred));
4883 Inst.addOperand(MCOperand::CreateImm(mask));
4888 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4889 uint64_t Address, const void *Decoder) {
4890 DecodeStatus S = MCDisassembler::Success;
4892 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4893 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4894 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4895 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4896 unsigned W = fieldFromInstruction(Insn, 21, 1);
4897 unsigned U = fieldFromInstruction(Insn, 23, 1);
4898 unsigned P = fieldFromInstruction(Insn, 24, 1);
4899 bool writeback = (W == 1) | (P == 0);
4901 addr |= (U << 8) | (Rn << 9);
4903 if (writeback && (Rn == Rt || Rn == Rt2))
4904 Check(S, MCDisassembler::SoftFail);
4906 Check(S, MCDisassembler::SoftFail);
4909 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4910 return MCDisassembler::Fail;
4912 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4913 return MCDisassembler::Fail;
4914 // Writeback operand
4915 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4916 return MCDisassembler::Fail;
4918 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4919 return MCDisassembler::Fail;
4925 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4926 uint64_t Address, const void *Decoder) {
4927 DecodeStatus S = MCDisassembler::Success;
4929 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4930 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4931 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4932 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4933 unsigned W = fieldFromInstruction(Insn, 21, 1);
4934 unsigned U = fieldFromInstruction(Insn, 23, 1);
4935 unsigned P = fieldFromInstruction(Insn, 24, 1);
4936 bool writeback = (W == 1) | (P == 0);
4938 addr |= (U << 8) | (Rn << 9);
4940 if (writeback && (Rn == Rt || Rn == Rt2))
4941 Check(S, MCDisassembler::SoftFail);
4943 // Writeback operand
4944 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4945 return MCDisassembler::Fail;
4947 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4948 return MCDisassembler::Fail;
4950 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4951 return MCDisassembler::Fail;
4953 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4954 return MCDisassembler::Fail;
4959 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4960 uint64_t Address, const void *Decoder) {
4961 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4962 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4963 if (sign1 != sign2) return MCDisassembler::Fail;
4965 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4966 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4967 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4969 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4971 return MCDisassembler::Success;
4974 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4976 const void *Decoder) {
4977 DecodeStatus S = MCDisassembler::Success;
4979 // Shift of "asr #32" is not allowed in Thumb2 mode.
4980 if (Val == 0x20) S = MCDisassembler::SoftFail;
4981 Inst.addOperand(MCOperand::CreateImm(Val));
4985 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4986 uint64_t Address, const void *Decoder) {
4987 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4988 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4989 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4990 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4993 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4995 DecodeStatus S = MCDisassembler::Success;
4997 if (Rt == Rn || Rn == Rt2)
4998 S = MCDisassembler::SoftFail;
5000 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5001 return MCDisassembler::Fail;
5002 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5003 return MCDisassembler::Fail;
5004 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5005 return MCDisassembler::Fail;
5006 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5007 return MCDisassembler::Fail;
5012 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
5013 uint64_t Address, const void *Decoder) {
5014 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5015 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5016 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5017 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5018 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5019 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5020 unsigned op = fieldFromInstruction(Insn, 5, 1);
5022 DecodeStatus S = MCDisassembler::Success;
5024 // VMOVv2f32 is ambiguous with these decodings.
5025 if (!(imm & 0x38) && cmode == 0xF) {
5026 if (op == 1) return MCDisassembler::Fail;
5027 Inst.setOpcode(ARM::VMOVv2f32);
5028 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5031 if (!(imm & 0x20)) return MCDisassembler::Fail;
5033 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
5034 return MCDisassembler::Fail;
5035 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
5036 return MCDisassembler::Fail;
5037 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5042 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
5043 uint64_t Address, const void *Decoder) {
5044 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
5045 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
5046 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
5047 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
5048 unsigned imm = fieldFromInstruction(Insn, 16, 6);
5049 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
5050 unsigned op = fieldFromInstruction(Insn, 5, 1);
5052 DecodeStatus S = MCDisassembler::Success;
5054 // VMOVv4f32 is ambiguous with these decodings.
5055 if (!(imm & 0x38) && cmode == 0xF) {
5056 if (op == 1) return MCDisassembler::Fail;
5057 Inst.setOpcode(ARM::VMOVv4f32);
5058 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5061 if (!(imm & 0x20)) return MCDisassembler::Fail;
5063 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5064 return MCDisassembler::Fail;
5065 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5066 return MCDisassembler::Fail;
5067 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5072 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5073 uint64_t Address, const void *Decoder) {
5074 DecodeStatus S = MCDisassembler::Success;
5076 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5077 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5078 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5079 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5080 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5082 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5083 S = MCDisassembler::SoftFail;
5085 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5086 return MCDisassembler::Fail;
5087 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5088 return MCDisassembler::Fail;
5089 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5090 return MCDisassembler::Fail;
5091 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5092 return MCDisassembler::Fail;
5093 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5094 return MCDisassembler::Fail;
5099 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
5100 uint64_t Address, const void *Decoder) {
5102 DecodeStatus S = MCDisassembler::Success;
5104 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5105 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5106 unsigned cop = fieldFromInstruction(Val, 8, 4);
5107 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5108 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5110 if ((cop & ~0x1) == 0xa)
5111 return MCDisassembler::Fail;
5114 S = MCDisassembler::SoftFail;
5116 Inst.addOperand(MCOperand::CreateImm(cop));
5117 Inst.addOperand(MCOperand::CreateImm(opc1));
5118 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5119 return MCDisassembler::Fail;
5120 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5121 return MCDisassembler::Fail;
5122 Inst.addOperand(MCOperand::CreateImm(CRm));