1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "arm-disassembler"
12 #include "llvm/MC/MCDisassembler.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/LEB128.h"
25 #include "llvm/Support/MemoryObject.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
35 // Handles the condition code status of instructions in IT blocks
39 // Returns the condition code for instruction in IT block
41 unsigned CC = ARMCC::AL;
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 ITStates.push_back(CCBits);
77 ITStates.push_back(CCBits ^ 1);
79 ITStates.push_back(CCBits);
83 std::vector<unsigned char> ITStates;
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
91 /// Constructor - Initializes the disassembler.
93 ARMDisassembler(const MCSubtargetInfo &STI) :
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr,
103 const MemoryObject ®ion,
105 raw_ostream &vStream,
106 raw_ostream &cStream) const;
109 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
110 class ThumbDisassembler : public MCDisassembler {
112 /// Constructor - Initializes the disassembler.
114 ThumbDisassembler(const MCSubtargetInfo &STI) :
115 MCDisassembler(STI) {
118 ~ThumbDisassembler() {
121 /// getInstruction - See MCDisassembler.
122 DecodeStatus getInstruction(MCInst &instr,
124 const MemoryObject ®ion,
126 raw_ostream &vStream,
127 raw_ostream &cStream) const;
130 mutable ITStatus ITBlock;
131 DecodeStatus AddThumbPredicate(MCInst&) const;
132 void UpdateThumbVFPPredicate(MCInst&) const;
136 static bool Check(DecodeStatus &Out, DecodeStatus In) {
138 case MCDisassembler::Success:
139 // Out stays the same.
141 case MCDisassembler::SoftFail:
144 case MCDisassembler::Fail:
148 llvm_unreachable("Invalid DecodeStatus!");
152 // Forward declare these because the autogenerated code will reference them.
153 // Definitions are further down.
154 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 uint64_t Address, const void *Decoder);
156 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
157 unsigned RegNo, uint64_t Address,
158 const void *Decoder);
159 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
160 unsigned RegNo, uint64_t Address,
161 const void *Decoder);
162 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
173 uint64_t Address, const void *Decoder);
174 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
175 uint64_t Address, const void *Decoder);
176 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
179 const void *Decoder);
180 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
181 uint64_t Address, const void *Decoder);
182 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
183 uint64_t Address, const void *Decoder);
184 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
185 unsigned RegNo, uint64_t Address,
186 const void *Decoder);
188 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
196 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
197 uint64_t Address, const void *Decoder);
198 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
199 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
202 uint64_t Address, const void *Decoder);
203 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
204 uint64_t Address, const void *Decoder);
205 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
208 const void *Decoder);
209 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
212 uint64_t Address, const void *Decoder);
213 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
214 uint64_t Address, const void *Decoder);
215 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
216 uint64_t Address, const void *Decoder);
218 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
221 const void *Decoder);
222 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
323 uint64_t Address, const void *Decoder);
324 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
325 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
327 const void *Decoder);
330 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
347 uint64_t Address, const void *Decoder);
348 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
349 uint64_t Address, const void *Decoder);
350 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
353 uint64_t Address, const void* Decoder);
354 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
355 uint64_t Address, const void* Decoder);
356 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
357 uint64_t Address, const void* Decoder);
358 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
395 uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
397 uint64_t Address, const void *Decoder);
398 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
399 uint64_t Address, const void *Decoder);
400 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
401 uint64_t Address, const void *Decoder);
403 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
404 uint64_t Address, const void *Decoder);
405 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
406 uint64_t Address, const void *Decoder);
407 #include "ARMGenDisassemblerTables.inc"
409 static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
410 return new ARMDisassembler(STI);
413 static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
414 return new ThumbDisassembler(STI);
417 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
418 const MemoryObject &Region,
421 raw_ostream &cs) const {
426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
429 // We want to read exactly 4 bytes of data.
430 if (Region.readBytes(Address, 4, bytes) == -1) {
432 return MCDisassembler::Fail;
435 // Encoded as a small-endian 32-bit word in the stream.
436 uint32_t insn = (bytes[3] << 24) |
441 // Calling the auto-generated decoder function.
442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
444 if (result != MCDisassembler::Fail) {
449 // VFP and NEON instructions, similarly, are shared between ARM
452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
453 if (result != MCDisassembler::Fail) {
459 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
461 if (result != MCDisassembler::Fail) {
463 // Add a fake predicate operand, because we share these instruction
464 // definitions with Thumb2 where these instructions are predicable.
465 if (!DecodePredicateOperand(MI, 0xE, Address, this))
466 return MCDisassembler::Fail;
471 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
473 if (result != MCDisassembler::Fail) {
475 // Add a fake predicate operand, because we share these instruction
476 // definitions with Thumb2 where these instructions are predicable.
477 if (!DecodePredicateOperand(MI, 0xE, Address, this))
478 return MCDisassembler::Fail;
483 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
485 if (result != MCDisassembler::Fail) {
487 // Add a fake predicate operand, because we share these instruction
488 // definitions with Thumb2 where these instructions are predicable.
489 if (!DecodePredicateOperand(MI, 0xE, Address, this))
490 return MCDisassembler::Fail;
497 return MCDisassembler::Fail;
501 extern const MCInstrDesc ARMInsts[];
504 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
505 /// immediate Value in the MCInst. The immediate Value has had any PC
506 /// adjustment made by the caller. If the instruction is a branch instruction
507 /// then isBranch is true, else false. If the getOpInfo() function was set as
508 /// part of the setupForSymbolicDisassembly() call then that function is called
509 /// to get any symbolic information at the Address for this instruction. If
510 /// that returns non-zero then the symbolic information it returns is used to
511 /// create an MCExpr and that is added as an operand to the MCInst. If
512 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
513 /// Value is done and if a symbol is found an MCExpr is created with that, else
514 /// an MCExpr with Value is created. This function returns true if it adds an
515 /// operand to the MCInst and false otherwise.
516 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
517 bool isBranch, uint64_t InstSize,
518 MCInst &MI, const void *Decoder) {
519 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
520 // FIXME: Does it make sense for value to be negative?
521 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
522 /* Offset */ 0, InstSize);
525 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
526 /// referenced by a load instruction with the base register that is the Pc.
527 /// These can often be values in a literal pool near the Address of the
528 /// instruction. The Address of the instruction and its immediate Value are
529 /// used as a possible literal pool entry. The SymbolLookUp call back will
530 /// return the name of a symbol referenced by the literal pool's entry if
531 /// the referenced address is that of a symbol. Or it will return a pointer to
532 /// a literal 'C' string if the referenced address of the literal pool's entry
533 /// is an address into a section with 'C' string literals.
534 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
535 const void *Decoder) {
536 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
537 Dis->tryAddingPcLoadReferenceComment(Value, Address);
540 // Thumb1 instructions don't have explicit S bits. Rather, they
541 // implicitly set CPSR. Since it's not represented in the encoding, the
542 // auto-generated decoder won't inject the CPSR operand. We need to fix
543 // that as a post-pass.
544 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
545 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
546 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
547 MCInst::iterator I = MI.begin();
548 for (unsigned i = 0; i < NumOps; ++i, ++I) {
549 if (I == MI.end()) break;
550 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
551 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
552 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
557 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
560 // Most Thumb instructions don't have explicit predicates in the
561 // encoding, but rather get their predicates from IT context. We need
562 // to fix up the predicate operands using this context information as a
564 MCDisassembler::DecodeStatus
565 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
566 MCDisassembler::DecodeStatus S = Success;
568 // A few instructions actually have predicates encoded in them. Don't
569 // try to overwrite it if we're seeing one of those.
570 switch (MI.getOpcode()) {
581 // Some instructions (mostly conditional branches) are not
582 // allowed in IT blocks.
583 if (ITBlock.instrInITBlock())
592 // Some instructions (mostly unconditional branches) can
593 // only appears at the end of, or outside of, an IT.
594 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
601 // If we're in an IT block, base the predicate on that. Otherwise,
602 // assume a predicate of AL.
604 CC = ITBlock.getITCC();
607 if (ITBlock.instrInITBlock())
608 ITBlock.advanceITState();
610 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
611 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
612 MCInst::iterator I = MI.begin();
613 for (unsigned i = 0; i < NumOps; ++i, ++I) {
614 if (I == MI.end()) break;
615 if (OpInfo[i].isPredicate()) {
616 I = MI.insert(I, MCOperand::CreateImm(CC));
619 MI.insert(I, MCOperand::CreateReg(0));
621 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
626 I = MI.insert(I, MCOperand::CreateImm(CC));
629 MI.insert(I, MCOperand::CreateReg(0));
631 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
636 // Thumb VFP instructions are a special case. Because we share their
637 // encodings between ARM and Thumb modes, and they are predicable in ARM
638 // mode, the auto-generated decoder will give them an (incorrect)
639 // predicate operand. We need to rewrite these operands based on the IT
640 // context as a post-pass.
641 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
643 CC = ITBlock.getITCC();
644 if (ITBlock.instrInITBlock())
645 ITBlock.advanceITState();
647 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
648 MCInst::iterator I = MI.begin();
649 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
650 for (unsigned i = 0; i < NumOps; ++i, ++I) {
651 if (OpInfo[i].isPredicate() ) {
657 I->setReg(ARM::CPSR);
663 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
664 const MemoryObject &Region,
667 raw_ostream &cs) const {
672 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
673 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
675 // We want to read exactly 2 bytes of data.
676 if (Region.readBytes(Address, 2, bytes) == -1) {
678 return MCDisassembler::Fail;
681 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
682 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
684 if (result != MCDisassembler::Fail) {
686 Check(result, AddThumbPredicate(MI));
691 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
695 bool InITBlock = ITBlock.instrInITBlock();
696 Check(result, AddThumbPredicate(MI));
697 AddThumb1SBit(MI, InITBlock);
702 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
704 if (result != MCDisassembler::Fail) {
707 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
708 // the Thumb predicate.
709 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
710 result = MCDisassembler::SoftFail;
712 Check(result, AddThumbPredicate(MI));
714 // If we find an IT instruction, we need to parse its condition
715 // code and mask operands so that we can apply them correctly
716 // to the subsequent instructions.
717 if (MI.getOpcode() == ARM::t2IT) {
719 unsigned Firstcond = MI.getOperand(0).getImm();
720 unsigned Mask = MI.getOperand(1).getImm();
721 ITBlock.setITState(Firstcond, Mask);
727 // We want to read exactly 4 bytes of data.
728 if (Region.readBytes(Address, 4, bytes) == -1) {
730 return MCDisassembler::Fail;
733 uint32_t insn32 = (bytes[3] << 8) |
738 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
740 if (result != MCDisassembler::Fail) {
742 bool InITBlock = ITBlock.instrInITBlock();
743 Check(result, AddThumbPredicate(MI));
744 AddThumb1SBit(MI, InITBlock);
749 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
751 if (result != MCDisassembler::Fail) {
753 Check(result, AddThumbPredicate(MI));
758 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
759 if (result != MCDisassembler::Fail) {
761 UpdateThumbVFPPredicate(MI);
766 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
768 if (result != MCDisassembler::Fail) {
770 Check(result, AddThumbPredicate(MI));
774 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
776 uint32_t NEONLdStInsn = insn32;
777 NEONLdStInsn &= 0xF0FFFFFF;
778 NEONLdStInsn |= 0x04000000;
779 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
781 if (result != MCDisassembler::Fail) {
783 Check(result, AddThumbPredicate(MI));
788 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
790 uint32_t NEONDataInsn = insn32;
791 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
792 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
793 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
794 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
796 if (result != MCDisassembler::Fail) {
798 Check(result, AddThumbPredicate(MI));
804 return MCDisassembler::Fail;
808 extern "C" void LLVMInitializeARMDisassembler() {
809 TargetRegistry::RegisterMCDisassembler(TheARMTarget,
810 createARMDisassembler);
811 TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
812 createThumbDisassembler);
815 static const uint16_t GPRDecoderTable[] = {
816 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
817 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
818 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
819 ARM::R12, ARM::SP, ARM::LR, ARM::PC
822 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
823 uint64_t Address, const void *Decoder) {
825 return MCDisassembler::Fail;
827 unsigned Register = GPRDecoderTable[RegNo];
828 Inst.addOperand(MCOperand::CreateReg(Register));
829 return MCDisassembler::Success;
833 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
834 uint64_t Address, const void *Decoder) {
835 DecodeStatus S = MCDisassembler::Success;
838 S = MCDisassembler::SoftFail;
840 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
846 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
847 uint64_t Address, const void *Decoder) {
848 DecodeStatus S = MCDisassembler::Success;
852 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
853 return MCDisassembler::Success;
856 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
860 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
861 uint64_t Address, const void *Decoder) {
863 return MCDisassembler::Fail;
864 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
867 static const uint16_t GPRPairDecoderTable[] = {
868 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
869 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
872 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
873 uint64_t Address, const void *Decoder) {
874 DecodeStatus S = MCDisassembler::Success;
877 return MCDisassembler::Fail;
879 if ((RegNo & 1) || RegNo == 0xe)
880 S = MCDisassembler::SoftFail;
882 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
883 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
887 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
888 uint64_t Address, const void *Decoder) {
889 unsigned Register = 0;
910 return MCDisassembler::Fail;
913 Inst.addOperand(MCOperand::CreateReg(Register));
914 return MCDisassembler::Success;
917 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
918 uint64_t Address, const void *Decoder) {
919 if (RegNo == 13 || RegNo == 15) return MCDisassembler::Fail;
920 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
923 static const uint16_t SPRDecoderTable[] = {
924 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
925 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
926 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
927 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
928 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
929 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
930 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
931 ARM::S28, ARM::S29, ARM::S30, ARM::S31
934 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
935 uint64_t Address, const void *Decoder) {
937 return MCDisassembler::Fail;
939 unsigned Register = SPRDecoderTable[RegNo];
940 Inst.addOperand(MCOperand::CreateReg(Register));
941 return MCDisassembler::Success;
944 static const uint16_t DPRDecoderTable[] = {
945 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
946 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
947 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
948 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
949 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
950 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
951 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
952 ARM::D28, ARM::D29, ARM::D30, ARM::D31
955 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
956 uint64_t Address, const void *Decoder) {
958 return MCDisassembler::Fail;
960 unsigned Register = DPRDecoderTable[RegNo];
961 Inst.addOperand(MCOperand::CreateReg(Register));
962 return MCDisassembler::Success;
965 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
966 uint64_t Address, const void *Decoder) {
968 return MCDisassembler::Fail;
969 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
973 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
974 uint64_t Address, const void *Decoder) {
976 return MCDisassembler::Fail;
977 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
980 static const uint16_t QPRDecoderTable[] = {
981 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
982 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
983 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
984 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
988 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
989 uint64_t Address, const void *Decoder) {
990 if (RegNo > 31 || (RegNo & 1) != 0)
991 return MCDisassembler::Fail;
994 unsigned Register = QPRDecoderTable[RegNo];
995 Inst.addOperand(MCOperand::CreateReg(Register));
996 return MCDisassembler::Success;
999 static const uint16_t DPairDecoderTable[] = {
1000 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1001 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1002 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1003 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1004 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1008 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1009 uint64_t Address, const void *Decoder) {
1011 return MCDisassembler::Fail;
1013 unsigned Register = DPairDecoderTable[RegNo];
1014 Inst.addOperand(MCOperand::CreateReg(Register));
1015 return MCDisassembler::Success;
1018 static const uint16_t DPairSpacedDecoderTable[] = {
1019 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1020 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1021 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1022 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1023 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1024 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1025 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1026 ARM::D28_D30, ARM::D29_D31
1029 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1032 const void *Decoder) {
1034 return MCDisassembler::Fail;
1036 unsigned Register = DPairSpacedDecoderTable[RegNo];
1037 Inst.addOperand(MCOperand::CreateReg(Register));
1038 return MCDisassembler::Success;
1041 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1042 uint64_t Address, const void *Decoder) {
1043 if (Val == 0xF) return MCDisassembler::Fail;
1044 // AL predicate is not allowed on Thumb1 branches.
1045 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1046 return MCDisassembler::Fail;
1047 Inst.addOperand(MCOperand::CreateImm(Val));
1048 if (Val == ARMCC::AL) {
1049 Inst.addOperand(MCOperand::CreateReg(0));
1051 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1052 return MCDisassembler::Success;
1055 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1056 uint64_t Address, const void *Decoder) {
1058 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1060 Inst.addOperand(MCOperand::CreateReg(0));
1061 return MCDisassembler::Success;
1064 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1065 uint64_t Address, const void *Decoder) {
1066 uint32_t imm = Val & 0xFF;
1067 uint32_t rot = (Val & 0xF00) >> 7;
1068 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1069 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1070 return MCDisassembler::Success;
1073 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1074 uint64_t Address, const void *Decoder) {
1075 DecodeStatus S = MCDisassembler::Success;
1077 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1078 unsigned type = fieldFromInstruction(Val, 5, 2);
1079 unsigned imm = fieldFromInstruction(Val, 7, 5);
1081 // Register-immediate
1082 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1083 return MCDisassembler::Fail;
1085 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1088 Shift = ARM_AM::lsl;
1091 Shift = ARM_AM::lsr;
1094 Shift = ARM_AM::asr;
1097 Shift = ARM_AM::ror;
1101 if (Shift == ARM_AM::ror && imm == 0)
1102 Shift = ARM_AM::rrx;
1104 unsigned Op = Shift | (imm << 3);
1105 Inst.addOperand(MCOperand::CreateImm(Op));
1110 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1111 uint64_t Address, const void *Decoder) {
1112 DecodeStatus S = MCDisassembler::Success;
1114 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1115 unsigned type = fieldFromInstruction(Val, 5, 2);
1116 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1118 // Register-register
1119 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1120 return MCDisassembler::Fail;
1121 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1122 return MCDisassembler::Fail;
1124 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1127 Shift = ARM_AM::lsl;
1130 Shift = ARM_AM::lsr;
1133 Shift = ARM_AM::asr;
1136 Shift = ARM_AM::ror;
1140 Inst.addOperand(MCOperand::CreateImm(Shift));
1145 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1146 uint64_t Address, const void *Decoder) {
1147 DecodeStatus S = MCDisassembler::Success;
1149 bool writebackLoad = false;
1150 unsigned writebackReg = 0;
1151 switch (Inst.getOpcode()) {
1154 case ARM::LDMIA_UPD:
1155 case ARM::LDMDB_UPD:
1156 case ARM::LDMIB_UPD:
1157 case ARM::LDMDA_UPD:
1158 case ARM::t2LDMIA_UPD:
1159 case ARM::t2LDMDB_UPD:
1160 writebackLoad = true;
1161 writebackReg = Inst.getOperand(0).getReg();
1165 // Empty register lists are not allowed.
1166 if (Val == 0) return MCDisassembler::Fail;
1167 for (unsigned i = 0; i < 16; ++i) {
1168 if (Val & (1 << i)) {
1169 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1170 return MCDisassembler::Fail;
1171 // Writeback not allowed if Rn is in the target list.
1172 if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
1173 Check(S, MCDisassembler::SoftFail);
1180 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1181 uint64_t Address, const void *Decoder) {
1182 DecodeStatus S = MCDisassembler::Success;
1184 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1185 unsigned regs = fieldFromInstruction(Val, 0, 8);
1187 // In case of unpredictable encoding, tweak the operands.
1188 if (regs == 0 || (Vd + regs) > 32) {
1189 regs = Vd + regs > 32 ? 32 - Vd : regs;
1190 regs = std::max( 1u, regs);
1191 S = MCDisassembler::SoftFail;
1194 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1195 return MCDisassembler::Fail;
1196 for (unsigned i = 0; i < (regs - 1); ++i) {
1197 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1198 return MCDisassembler::Fail;
1204 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1205 uint64_t Address, const void *Decoder) {
1206 DecodeStatus S = MCDisassembler::Success;
1208 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1209 unsigned regs = fieldFromInstruction(Val, 1, 7);
1211 // In case of unpredictable encoding, tweak the operands.
1212 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1213 regs = Vd + regs > 32 ? 32 - Vd : regs;
1214 regs = std::max( 1u, regs);
1215 regs = std::min(16u, regs);
1216 S = MCDisassembler::SoftFail;
1219 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1220 return MCDisassembler::Fail;
1221 for (unsigned i = 0; i < (regs - 1); ++i) {
1222 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1223 return MCDisassembler::Fail;
1229 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1230 uint64_t Address, const void *Decoder) {
1231 // This operand encodes a mask of contiguous zeros between a specified MSB
1232 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1233 // the mask of all bits LSB-and-lower, and then xor them to create
1234 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1235 // create the final mask.
1236 unsigned msb = fieldFromInstruction(Val, 5, 5);
1237 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1239 DecodeStatus S = MCDisassembler::Success;
1241 Check(S, MCDisassembler::SoftFail);
1242 // The check above will cause the warning for the "potentially undefined
1243 // instruction encoding" but we can't build a bad MCOperand value here
1244 // with a lsb > msb or else printing the MCInst will cause a crash.
1248 uint32_t msb_mask = 0xFFFFFFFF;
1249 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1250 uint32_t lsb_mask = (1U << lsb) - 1;
1252 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1256 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1257 uint64_t Address, const void *Decoder) {
1258 DecodeStatus S = MCDisassembler::Success;
1260 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1261 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1262 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1263 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1264 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1265 unsigned U = fieldFromInstruction(Insn, 23, 1);
1267 switch (Inst.getOpcode()) {
1268 case ARM::LDC_OFFSET:
1271 case ARM::LDC_OPTION:
1272 case ARM::LDCL_OFFSET:
1274 case ARM::LDCL_POST:
1275 case ARM::LDCL_OPTION:
1276 case ARM::STC_OFFSET:
1279 case ARM::STC_OPTION:
1280 case ARM::STCL_OFFSET:
1282 case ARM::STCL_POST:
1283 case ARM::STCL_OPTION:
1284 case ARM::t2LDC_OFFSET:
1285 case ARM::t2LDC_PRE:
1286 case ARM::t2LDC_POST:
1287 case ARM::t2LDC_OPTION:
1288 case ARM::t2LDCL_OFFSET:
1289 case ARM::t2LDCL_PRE:
1290 case ARM::t2LDCL_POST:
1291 case ARM::t2LDCL_OPTION:
1292 case ARM::t2STC_OFFSET:
1293 case ARM::t2STC_PRE:
1294 case ARM::t2STC_POST:
1295 case ARM::t2STC_OPTION:
1296 case ARM::t2STCL_OFFSET:
1297 case ARM::t2STCL_PRE:
1298 case ARM::t2STCL_POST:
1299 case ARM::t2STCL_OPTION:
1300 if (coproc == 0xA || coproc == 0xB)
1301 return MCDisassembler::Fail;
1307 Inst.addOperand(MCOperand::CreateImm(coproc));
1308 Inst.addOperand(MCOperand::CreateImm(CRd));
1309 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1310 return MCDisassembler::Fail;
1312 switch (Inst.getOpcode()) {
1313 case ARM::t2LDC2_OFFSET:
1314 case ARM::t2LDC2L_OFFSET:
1315 case ARM::t2LDC2_PRE:
1316 case ARM::t2LDC2L_PRE:
1317 case ARM::t2STC2_OFFSET:
1318 case ARM::t2STC2L_OFFSET:
1319 case ARM::t2STC2_PRE:
1320 case ARM::t2STC2L_PRE:
1321 case ARM::LDC2_OFFSET:
1322 case ARM::LDC2L_OFFSET:
1324 case ARM::LDC2L_PRE:
1325 case ARM::STC2_OFFSET:
1326 case ARM::STC2L_OFFSET:
1328 case ARM::STC2L_PRE:
1329 case ARM::t2LDC_OFFSET:
1330 case ARM::t2LDCL_OFFSET:
1331 case ARM::t2LDC_PRE:
1332 case ARM::t2LDCL_PRE:
1333 case ARM::t2STC_OFFSET:
1334 case ARM::t2STCL_OFFSET:
1335 case ARM::t2STC_PRE:
1336 case ARM::t2STCL_PRE:
1337 case ARM::LDC_OFFSET:
1338 case ARM::LDCL_OFFSET:
1341 case ARM::STC_OFFSET:
1342 case ARM::STCL_OFFSET:
1345 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1346 Inst.addOperand(MCOperand::CreateImm(imm));
1348 case ARM::t2LDC2_POST:
1349 case ARM::t2LDC2L_POST:
1350 case ARM::t2STC2_POST:
1351 case ARM::t2STC2L_POST:
1352 case ARM::LDC2_POST:
1353 case ARM::LDC2L_POST:
1354 case ARM::STC2_POST:
1355 case ARM::STC2L_POST:
1356 case ARM::t2LDC_POST:
1357 case ARM::t2LDCL_POST:
1358 case ARM::t2STC_POST:
1359 case ARM::t2STCL_POST:
1361 case ARM::LDCL_POST:
1363 case ARM::STCL_POST:
1367 // The 'option' variant doesn't encode 'U' in the immediate since
1368 // the immediate is unsigned [0,255].
1369 Inst.addOperand(MCOperand::CreateImm(imm));
1373 switch (Inst.getOpcode()) {
1374 case ARM::LDC_OFFSET:
1377 case ARM::LDC_OPTION:
1378 case ARM::LDCL_OFFSET:
1380 case ARM::LDCL_POST:
1381 case ARM::LDCL_OPTION:
1382 case ARM::STC_OFFSET:
1385 case ARM::STC_OPTION:
1386 case ARM::STCL_OFFSET:
1388 case ARM::STCL_POST:
1389 case ARM::STCL_OPTION:
1390 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1391 return MCDisassembler::Fail;
1401 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1402 uint64_t Address, const void *Decoder) {
1403 DecodeStatus S = MCDisassembler::Success;
1405 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1406 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1407 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1408 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1409 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1410 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1411 unsigned P = fieldFromInstruction(Insn, 24, 1);
1412 unsigned W = fieldFromInstruction(Insn, 21, 1);
1414 // On stores, the writeback operand precedes Rt.
1415 switch (Inst.getOpcode()) {
1416 case ARM::STR_POST_IMM:
1417 case ARM::STR_POST_REG:
1418 case ARM::STRB_POST_IMM:
1419 case ARM::STRB_POST_REG:
1420 case ARM::STRT_POST_REG:
1421 case ARM::STRT_POST_IMM:
1422 case ARM::STRBT_POST_REG:
1423 case ARM::STRBT_POST_IMM:
1424 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1425 return MCDisassembler::Fail;
1431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1432 return MCDisassembler::Fail;
1434 // On loads, the writeback operand comes after Rt.
1435 switch (Inst.getOpcode()) {
1436 case ARM::LDR_POST_IMM:
1437 case ARM::LDR_POST_REG:
1438 case ARM::LDRB_POST_IMM:
1439 case ARM::LDRB_POST_REG:
1440 case ARM::LDRBT_POST_REG:
1441 case ARM::LDRBT_POST_IMM:
1442 case ARM::LDRT_POST_REG:
1443 case ARM::LDRT_POST_IMM:
1444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1445 return MCDisassembler::Fail;
1451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1452 return MCDisassembler::Fail;
1454 ARM_AM::AddrOpc Op = ARM_AM::add;
1455 if (!fieldFromInstruction(Insn, 23, 1))
1458 bool writeback = (P == 0) || (W == 1);
1459 unsigned idx_mode = 0;
1461 idx_mode = ARMII::IndexModePre;
1462 else if (!P && writeback)
1463 idx_mode = ARMII::IndexModePost;
1465 if (writeback && (Rn == 15 || Rn == Rt))
1466 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1469 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1470 return MCDisassembler::Fail;
1471 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1472 switch( fieldFromInstruction(Insn, 5, 2)) {
1486 return MCDisassembler::Fail;
1488 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1489 if (Opc == ARM_AM::ror && amt == 0)
1491 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1493 Inst.addOperand(MCOperand::CreateImm(imm));
1495 Inst.addOperand(MCOperand::CreateReg(0));
1496 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1497 Inst.addOperand(MCOperand::CreateImm(tmp));
1500 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1501 return MCDisassembler::Fail;
1506 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1507 uint64_t Address, const void *Decoder) {
1508 DecodeStatus S = MCDisassembler::Success;
1510 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1511 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1512 unsigned type = fieldFromInstruction(Val, 5, 2);
1513 unsigned imm = fieldFromInstruction(Val, 7, 5);
1514 unsigned U = fieldFromInstruction(Val, 12, 1);
1516 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1532 if (ShOp == ARM_AM::ror && imm == 0)
1535 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1536 return MCDisassembler::Fail;
1537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1538 return MCDisassembler::Fail;
1541 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1543 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1544 Inst.addOperand(MCOperand::CreateImm(shift));
1550 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1551 uint64_t Address, const void *Decoder) {
1552 DecodeStatus S = MCDisassembler::Success;
1554 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1555 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1556 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1557 unsigned type = fieldFromInstruction(Insn, 22, 1);
1558 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1559 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1560 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1561 unsigned W = fieldFromInstruction(Insn, 21, 1);
1562 unsigned P = fieldFromInstruction(Insn, 24, 1);
1563 unsigned Rt2 = Rt + 1;
1565 bool writeback = (W == 1) | (P == 0);
1567 // For {LD,ST}RD, Rt must be even, else undefined.
1568 switch (Inst.getOpcode()) {
1571 case ARM::STRD_POST:
1574 case ARM::LDRD_POST:
1575 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1580 switch (Inst.getOpcode()) {
1583 case ARM::STRD_POST:
1584 if (P == 0 && W == 1)
1585 S = MCDisassembler::SoftFail;
1587 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1588 S = MCDisassembler::SoftFail;
1589 if (type && Rm == 15)
1590 S = MCDisassembler::SoftFail;
1592 S = MCDisassembler::SoftFail;
1593 if (!type && fieldFromInstruction(Insn, 8, 4))
1594 S = MCDisassembler::SoftFail;
1598 case ARM::STRH_POST:
1600 S = MCDisassembler::SoftFail;
1601 if (writeback && (Rn == 15 || Rn == Rt))
1602 S = MCDisassembler::SoftFail;
1603 if (!type && Rm == 15)
1604 S = MCDisassembler::SoftFail;
1608 case ARM::LDRD_POST:
1609 if (type && Rn == 15){
1611 S = MCDisassembler::SoftFail;
1614 if (P == 0 && W == 1)
1615 S = MCDisassembler::SoftFail;
1616 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1617 S = MCDisassembler::SoftFail;
1618 if (!type && writeback && Rn == 15)
1619 S = MCDisassembler::SoftFail;
1620 if (writeback && (Rn == Rt || Rn == Rt2))
1621 S = MCDisassembler::SoftFail;
1625 case ARM::LDRH_POST:
1626 if (type && Rn == 15){
1628 S = MCDisassembler::SoftFail;
1632 S = MCDisassembler::SoftFail;
1633 if (!type && Rm == 15)
1634 S = MCDisassembler::SoftFail;
1635 if (!type && writeback && (Rn == 15 || Rn == Rt))
1636 S = MCDisassembler::SoftFail;
1639 case ARM::LDRSH_PRE:
1640 case ARM::LDRSH_POST:
1642 case ARM::LDRSB_PRE:
1643 case ARM::LDRSB_POST:
1644 if (type && Rn == 15){
1646 S = MCDisassembler::SoftFail;
1649 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1650 S = MCDisassembler::SoftFail;
1651 if (!type && (Rt == 15 || Rm == 15))
1652 S = MCDisassembler::SoftFail;
1653 if (!type && writeback && (Rn == 15 || Rn == Rt))
1654 S = MCDisassembler::SoftFail;
1660 if (writeback) { // Writeback
1662 U |= ARMII::IndexModePre << 9;
1664 U |= ARMII::IndexModePost << 9;
1666 // On stores, the writeback operand precedes Rt.
1667 switch (Inst.getOpcode()) {
1670 case ARM::STRD_POST:
1673 case ARM::STRH_POST:
1674 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1675 return MCDisassembler::Fail;
1682 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1683 return MCDisassembler::Fail;
1684 switch (Inst.getOpcode()) {
1687 case ARM::STRD_POST:
1690 case ARM::LDRD_POST:
1691 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1692 return MCDisassembler::Fail;
1699 // On loads, the writeback operand comes after Rt.
1700 switch (Inst.getOpcode()) {
1703 case ARM::LDRD_POST:
1706 case ARM::LDRH_POST:
1708 case ARM::LDRSH_PRE:
1709 case ARM::LDRSH_POST:
1711 case ARM::LDRSB_PRE:
1712 case ARM::LDRSB_POST:
1715 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1716 return MCDisassembler::Fail;
1723 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1724 return MCDisassembler::Fail;
1727 Inst.addOperand(MCOperand::CreateReg(0));
1728 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1730 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1731 return MCDisassembler::Fail;
1732 Inst.addOperand(MCOperand::CreateImm(U));
1735 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1736 return MCDisassembler::Fail;
1741 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1742 uint64_t Address, const void *Decoder) {
1743 DecodeStatus S = MCDisassembler::Success;
1745 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1746 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1763 Inst.addOperand(MCOperand::CreateImm(mode));
1764 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1765 return MCDisassembler::Fail;
1770 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1771 uint64_t Address, const void *Decoder) {
1772 DecodeStatus S = MCDisassembler::Success;
1774 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1775 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1776 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1777 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1780 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1782 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1783 return MCDisassembler::Fail;
1784 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1785 return MCDisassembler::Fail;
1786 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1787 return MCDisassembler::Fail;
1788 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1789 return MCDisassembler::Fail;
1793 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1795 uint64_t Address, const void *Decoder) {
1796 DecodeStatus S = MCDisassembler::Success;
1798 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1799 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1800 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1803 // Ambiguous with RFE and SRS
1804 switch (Inst.getOpcode()) {
1806 Inst.setOpcode(ARM::RFEDA);
1808 case ARM::LDMDA_UPD:
1809 Inst.setOpcode(ARM::RFEDA_UPD);
1812 Inst.setOpcode(ARM::RFEDB);
1814 case ARM::LDMDB_UPD:
1815 Inst.setOpcode(ARM::RFEDB_UPD);
1818 Inst.setOpcode(ARM::RFEIA);
1820 case ARM::LDMIA_UPD:
1821 Inst.setOpcode(ARM::RFEIA_UPD);
1824 Inst.setOpcode(ARM::RFEIB);
1826 case ARM::LDMIB_UPD:
1827 Inst.setOpcode(ARM::RFEIB_UPD);
1830 Inst.setOpcode(ARM::SRSDA);
1832 case ARM::STMDA_UPD:
1833 Inst.setOpcode(ARM::SRSDA_UPD);
1836 Inst.setOpcode(ARM::SRSDB);
1838 case ARM::STMDB_UPD:
1839 Inst.setOpcode(ARM::SRSDB_UPD);
1842 Inst.setOpcode(ARM::SRSIA);
1844 case ARM::STMIA_UPD:
1845 Inst.setOpcode(ARM::SRSIA_UPD);
1848 Inst.setOpcode(ARM::SRSIB);
1850 case ARM::STMIB_UPD:
1851 Inst.setOpcode(ARM::SRSIB_UPD);
1854 return MCDisassembler::Fail;
1857 // For stores (which become SRS's, the only operand is the mode.
1858 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1859 // Check SRS encoding constraints
1860 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1861 fieldFromInstruction(Insn, 20, 1) == 0))
1862 return MCDisassembler::Fail;
1865 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1869 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1872 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1873 return MCDisassembler::Fail;
1874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1875 return MCDisassembler::Fail; // Tied
1876 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1877 return MCDisassembler::Fail;
1878 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1879 return MCDisassembler::Fail;
1884 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1885 uint64_t Address, const void *Decoder) {
1886 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1887 unsigned M = fieldFromInstruction(Insn, 17, 1);
1888 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1889 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1891 DecodeStatus S = MCDisassembler::Success;
1893 // This decoder is called from multiple location that do not check
1894 // the full encoding is valid before they do.
1895 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1896 fieldFromInstruction(Insn, 16, 1) != 0 ||
1897 fieldFromInstruction(Insn, 20, 8) != 0x10)
1898 return MCDisassembler::Fail;
1900 // imod == '01' --> UNPREDICTABLE
1901 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1902 // return failure here. The '01' imod value is unprintable, so there's
1903 // nothing useful we could do even if we returned UNPREDICTABLE.
1905 if (imod == 1) return MCDisassembler::Fail;
1908 Inst.setOpcode(ARM::CPS3p);
1909 Inst.addOperand(MCOperand::CreateImm(imod));
1910 Inst.addOperand(MCOperand::CreateImm(iflags));
1911 Inst.addOperand(MCOperand::CreateImm(mode));
1912 } else if (imod && !M) {
1913 Inst.setOpcode(ARM::CPS2p);
1914 Inst.addOperand(MCOperand::CreateImm(imod));
1915 Inst.addOperand(MCOperand::CreateImm(iflags));
1916 if (mode) S = MCDisassembler::SoftFail;
1917 } else if (!imod && M) {
1918 Inst.setOpcode(ARM::CPS1p);
1919 Inst.addOperand(MCOperand::CreateImm(mode));
1920 if (iflags) S = MCDisassembler::SoftFail;
1922 // imod == '00' && M == '0' --> UNPREDICTABLE
1923 Inst.setOpcode(ARM::CPS1p);
1924 Inst.addOperand(MCOperand::CreateImm(mode));
1925 S = MCDisassembler::SoftFail;
1931 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
1932 uint64_t Address, const void *Decoder) {
1933 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1934 unsigned M = fieldFromInstruction(Insn, 8, 1);
1935 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1936 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1938 DecodeStatus S = MCDisassembler::Success;
1940 // imod == '01' --> UNPREDICTABLE
1941 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1942 // return failure here. The '01' imod value is unprintable, so there's
1943 // nothing useful we could do even if we returned UNPREDICTABLE.
1945 if (imod == 1) return MCDisassembler::Fail;
1948 Inst.setOpcode(ARM::t2CPS3p);
1949 Inst.addOperand(MCOperand::CreateImm(imod));
1950 Inst.addOperand(MCOperand::CreateImm(iflags));
1951 Inst.addOperand(MCOperand::CreateImm(mode));
1952 } else if (imod && !M) {
1953 Inst.setOpcode(ARM::t2CPS2p);
1954 Inst.addOperand(MCOperand::CreateImm(imod));
1955 Inst.addOperand(MCOperand::CreateImm(iflags));
1956 if (mode) S = MCDisassembler::SoftFail;
1957 } else if (!imod && M) {
1958 Inst.setOpcode(ARM::t2CPS1p);
1959 Inst.addOperand(MCOperand::CreateImm(mode));
1960 if (iflags) S = MCDisassembler::SoftFail;
1962 // imod == '00' && M == '0' --> this is a HINT instruction
1963 int imm = fieldFromInstruction(Insn, 0, 8);
1964 // HINT are defined only for immediate in [0..4]
1965 if(imm > 4) return MCDisassembler::Fail;
1966 Inst.setOpcode(ARM::t2HINT);
1967 Inst.addOperand(MCOperand::CreateImm(imm));
1973 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
1974 uint64_t Address, const void *Decoder) {
1975 DecodeStatus S = MCDisassembler::Success;
1977 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
1980 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1981 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1982 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1983 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
1985 if (Inst.getOpcode() == ARM::t2MOVTi16)
1986 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1987 return MCDisassembler::Fail;
1988 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
1989 return MCDisassembler::Fail;
1991 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
1992 Inst.addOperand(MCOperand::CreateImm(imm));
1997 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
1998 uint64_t Address, const void *Decoder) {
1999 DecodeStatus S = MCDisassembler::Success;
2001 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2002 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2005 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2006 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2008 if (Inst.getOpcode() == ARM::MOVTi16)
2009 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2010 return MCDisassembler::Fail;
2012 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2013 return MCDisassembler::Fail;
2015 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2016 Inst.addOperand(MCOperand::CreateImm(imm));
2018 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2019 return MCDisassembler::Fail;
2024 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2025 uint64_t Address, const void *Decoder) {
2026 DecodeStatus S = MCDisassembler::Success;
2028 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2029 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2030 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2031 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2032 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2035 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2037 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2038 return MCDisassembler::Fail;
2039 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2040 return MCDisassembler::Fail;
2041 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2042 return MCDisassembler::Fail;
2043 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2044 return MCDisassembler::Fail;
2046 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2047 return MCDisassembler::Fail;
2052 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2053 uint64_t Address, const void *Decoder) {
2054 DecodeStatus S = MCDisassembler::Success;
2056 unsigned add = fieldFromInstruction(Val, 12, 1);
2057 unsigned imm = fieldFromInstruction(Val, 0, 12);
2058 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2060 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2061 return MCDisassembler::Fail;
2063 if (!add) imm *= -1;
2064 if (imm == 0 && !add) imm = INT32_MIN;
2065 Inst.addOperand(MCOperand::CreateImm(imm));
2067 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2072 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2073 uint64_t Address, const void *Decoder) {
2074 DecodeStatus S = MCDisassembler::Success;
2076 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2077 unsigned U = fieldFromInstruction(Val, 8, 1);
2078 unsigned imm = fieldFromInstruction(Val, 0, 8);
2080 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2081 return MCDisassembler::Fail;
2084 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2086 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2091 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2092 uint64_t Address, const void *Decoder) {
2093 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2097 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2098 uint64_t Address, const void *Decoder) {
2099 DecodeStatus Status = MCDisassembler::Success;
2101 // Note the J1 and J2 values are from the encoded instruction. So here
2102 // change them to I1 and I2 values via as documented:
2103 // I1 = NOT(J1 EOR S);
2104 // I2 = NOT(J2 EOR S);
2105 // and build the imm32 with one trailing zero as documented:
2106 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2107 unsigned S = fieldFromInstruction(Insn, 26, 1);
2108 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2109 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2110 unsigned I1 = !(J1 ^ S);
2111 unsigned I2 = !(J2 ^ S);
2112 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2113 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2114 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2115 int imm32 = SignExtend32<25>(tmp << 1);
2116 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2117 true, 4, Inst, Decoder))
2118 Inst.addOperand(MCOperand::CreateImm(imm32));
2124 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2125 uint64_t Address, const void *Decoder) {
2126 DecodeStatus S = MCDisassembler::Success;
2128 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2129 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2132 Inst.setOpcode(ARM::BLXi);
2133 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2134 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2135 true, 4, Inst, Decoder))
2136 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2140 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2141 true, 4, Inst, Decoder))
2142 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2143 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2144 return MCDisassembler::Fail;
2150 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2151 uint64_t Address, const void *Decoder) {
2152 DecodeStatus S = MCDisassembler::Success;
2154 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2155 unsigned align = fieldFromInstruction(Val, 4, 2);
2157 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2158 return MCDisassembler::Fail;
2160 Inst.addOperand(MCOperand::CreateImm(0));
2162 Inst.addOperand(MCOperand::CreateImm(4 << align));
2167 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2168 uint64_t Address, const void *Decoder) {
2169 DecodeStatus S = MCDisassembler::Success;
2171 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2172 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2173 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2174 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2175 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2176 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2178 // First output register
2179 switch (Inst.getOpcode()) {
2180 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2181 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2182 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2183 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2184 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2185 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2186 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2187 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2188 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2189 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2190 return MCDisassembler::Fail;
2195 case ARM::VLD2b16wb_fixed:
2196 case ARM::VLD2b16wb_register:
2197 case ARM::VLD2b32wb_fixed:
2198 case ARM::VLD2b32wb_register:
2199 case ARM::VLD2b8wb_fixed:
2200 case ARM::VLD2b8wb_register:
2201 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2202 return MCDisassembler::Fail;
2205 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2206 return MCDisassembler::Fail;
2209 // Second output register
2210 switch (Inst.getOpcode()) {
2214 case ARM::VLD3d8_UPD:
2215 case ARM::VLD3d16_UPD:
2216 case ARM::VLD3d32_UPD:
2220 case ARM::VLD4d8_UPD:
2221 case ARM::VLD4d16_UPD:
2222 case ARM::VLD4d32_UPD:
2223 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2224 return MCDisassembler::Fail;
2229 case ARM::VLD3q8_UPD:
2230 case ARM::VLD3q16_UPD:
2231 case ARM::VLD3q32_UPD:
2235 case ARM::VLD4q8_UPD:
2236 case ARM::VLD4q16_UPD:
2237 case ARM::VLD4q32_UPD:
2238 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2239 return MCDisassembler::Fail;
2244 // Third output register
2245 switch(Inst.getOpcode()) {
2249 case ARM::VLD3d8_UPD:
2250 case ARM::VLD3d16_UPD:
2251 case ARM::VLD3d32_UPD:
2255 case ARM::VLD4d8_UPD:
2256 case ARM::VLD4d16_UPD:
2257 case ARM::VLD4d32_UPD:
2258 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2259 return MCDisassembler::Fail;
2264 case ARM::VLD3q8_UPD:
2265 case ARM::VLD3q16_UPD:
2266 case ARM::VLD3q32_UPD:
2270 case ARM::VLD4q8_UPD:
2271 case ARM::VLD4q16_UPD:
2272 case ARM::VLD4q32_UPD:
2273 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2274 return MCDisassembler::Fail;
2280 // Fourth output register
2281 switch (Inst.getOpcode()) {
2285 case ARM::VLD4d8_UPD:
2286 case ARM::VLD4d16_UPD:
2287 case ARM::VLD4d32_UPD:
2288 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2289 return MCDisassembler::Fail;
2294 case ARM::VLD4q8_UPD:
2295 case ARM::VLD4q16_UPD:
2296 case ARM::VLD4q32_UPD:
2297 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2298 return MCDisassembler::Fail;
2304 // Writeback operand
2305 switch (Inst.getOpcode()) {
2306 case ARM::VLD1d8wb_fixed:
2307 case ARM::VLD1d16wb_fixed:
2308 case ARM::VLD1d32wb_fixed:
2309 case ARM::VLD1d64wb_fixed:
2310 case ARM::VLD1d8wb_register:
2311 case ARM::VLD1d16wb_register:
2312 case ARM::VLD1d32wb_register:
2313 case ARM::VLD1d64wb_register:
2314 case ARM::VLD1q8wb_fixed:
2315 case ARM::VLD1q16wb_fixed:
2316 case ARM::VLD1q32wb_fixed:
2317 case ARM::VLD1q64wb_fixed:
2318 case ARM::VLD1q8wb_register:
2319 case ARM::VLD1q16wb_register:
2320 case ARM::VLD1q32wb_register:
2321 case ARM::VLD1q64wb_register:
2322 case ARM::VLD1d8Twb_fixed:
2323 case ARM::VLD1d8Twb_register:
2324 case ARM::VLD1d16Twb_fixed:
2325 case ARM::VLD1d16Twb_register:
2326 case ARM::VLD1d32Twb_fixed:
2327 case ARM::VLD1d32Twb_register:
2328 case ARM::VLD1d64Twb_fixed:
2329 case ARM::VLD1d64Twb_register:
2330 case ARM::VLD1d8Qwb_fixed:
2331 case ARM::VLD1d8Qwb_register:
2332 case ARM::VLD1d16Qwb_fixed:
2333 case ARM::VLD1d16Qwb_register:
2334 case ARM::VLD1d32Qwb_fixed:
2335 case ARM::VLD1d32Qwb_register:
2336 case ARM::VLD1d64Qwb_fixed:
2337 case ARM::VLD1d64Qwb_register:
2338 case ARM::VLD2d8wb_fixed:
2339 case ARM::VLD2d16wb_fixed:
2340 case ARM::VLD2d32wb_fixed:
2341 case ARM::VLD2q8wb_fixed:
2342 case ARM::VLD2q16wb_fixed:
2343 case ARM::VLD2q32wb_fixed:
2344 case ARM::VLD2d8wb_register:
2345 case ARM::VLD2d16wb_register:
2346 case ARM::VLD2d32wb_register:
2347 case ARM::VLD2q8wb_register:
2348 case ARM::VLD2q16wb_register:
2349 case ARM::VLD2q32wb_register:
2350 case ARM::VLD2b8wb_fixed:
2351 case ARM::VLD2b16wb_fixed:
2352 case ARM::VLD2b32wb_fixed:
2353 case ARM::VLD2b8wb_register:
2354 case ARM::VLD2b16wb_register:
2355 case ARM::VLD2b32wb_register:
2356 Inst.addOperand(MCOperand::CreateImm(0));
2358 case ARM::VLD3d8_UPD:
2359 case ARM::VLD3d16_UPD:
2360 case ARM::VLD3d32_UPD:
2361 case ARM::VLD3q8_UPD:
2362 case ARM::VLD3q16_UPD:
2363 case ARM::VLD3q32_UPD:
2364 case ARM::VLD4d8_UPD:
2365 case ARM::VLD4d16_UPD:
2366 case ARM::VLD4d32_UPD:
2367 case ARM::VLD4q8_UPD:
2368 case ARM::VLD4q16_UPD:
2369 case ARM::VLD4q32_UPD:
2370 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2371 return MCDisassembler::Fail;
2377 // AddrMode6 Base (register+alignment)
2378 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2379 return MCDisassembler::Fail;
2381 // AddrMode6 Offset (register)
2382 switch (Inst.getOpcode()) {
2384 // The below have been updated to have explicit am6offset split
2385 // between fixed and register offset. For those instructions not
2386 // yet updated, we need to add an additional reg0 operand for the
2389 // The fixed offset encodes as Rm == 0xd, so we check for that.
2391 Inst.addOperand(MCOperand::CreateReg(0));
2394 // Fall through to handle the register offset variant.
2395 case ARM::VLD1d8wb_fixed:
2396 case ARM::VLD1d16wb_fixed:
2397 case ARM::VLD1d32wb_fixed:
2398 case ARM::VLD1d64wb_fixed:
2399 case ARM::VLD1d8Twb_fixed:
2400 case ARM::VLD1d16Twb_fixed:
2401 case ARM::VLD1d32Twb_fixed:
2402 case ARM::VLD1d64Twb_fixed:
2403 case ARM::VLD1d8Qwb_fixed:
2404 case ARM::VLD1d16Qwb_fixed:
2405 case ARM::VLD1d32Qwb_fixed:
2406 case ARM::VLD1d64Qwb_fixed:
2407 case ARM::VLD1d8wb_register:
2408 case ARM::VLD1d16wb_register:
2409 case ARM::VLD1d32wb_register:
2410 case ARM::VLD1d64wb_register:
2411 case ARM::VLD1q8wb_fixed:
2412 case ARM::VLD1q16wb_fixed:
2413 case ARM::VLD1q32wb_fixed:
2414 case ARM::VLD1q64wb_fixed:
2415 case ARM::VLD1q8wb_register:
2416 case ARM::VLD1q16wb_register:
2417 case ARM::VLD1q32wb_register:
2418 case ARM::VLD1q64wb_register:
2419 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2420 // variant encodes Rm == 0xf. Anything else is a register offset post-
2421 // increment and we need to add the register operand to the instruction.
2422 if (Rm != 0xD && Rm != 0xF &&
2423 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2424 return MCDisassembler::Fail;
2426 case ARM::VLD2d8wb_fixed:
2427 case ARM::VLD2d16wb_fixed:
2428 case ARM::VLD2d32wb_fixed:
2429 case ARM::VLD2b8wb_fixed:
2430 case ARM::VLD2b16wb_fixed:
2431 case ARM::VLD2b32wb_fixed:
2432 case ARM::VLD2q8wb_fixed:
2433 case ARM::VLD2q16wb_fixed:
2434 case ARM::VLD2q32wb_fixed:
2441 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2442 uint64_t Address, const void *Decoder) {
2443 unsigned type = fieldFromInstruction(Insn, 8, 4);
2444 unsigned align = fieldFromInstruction(Insn, 4, 2);
2445 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2446 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2447 if (type == 10 && align == 3) return MCDisassembler::Fail;
2449 unsigned load = fieldFromInstruction(Insn, 21, 1);
2450 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2451 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2454 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2455 uint64_t Address, const void *Decoder) {
2456 unsigned size = fieldFromInstruction(Insn, 6, 2);
2457 if (size == 3) return MCDisassembler::Fail;
2459 unsigned type = fieldFromInstruction(Insn, 8, 4);
2460 unsigned align = fieldFromInstruction(Insn, 4, 2);
2461 if (type == 8 && align == 3) return MCDisassembler::Fail;
2462 if (type == 9 && align == 3) return MCDisassembler::Fail;
2464 unsigned load = fieldFromInstruction(Insn, 21, 1);
2465 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2466 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2469 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2470 uint64_t Address, const void *Decoder) {
2471 unsigned size = fieldFromInstruction(Insn, 6, 2);
2472 if (size == 3) return MCDisassembler::Fail;
2474 unsigned align = fieldFromInstruction(Insn, 4, 2);
2475 if (align & 2) return MCDisassembler::Fail;
2477 unsigned load = fieldFromInstruction(Insn, 21, 1);
2478 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2479 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2482 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2483 uint64_t Address, const void *Decoder) {
2484 unsigned size = fieldFromInstruction(Insn, 6, 2);
2485 if (size == 3) return MCDisassembler::Fail;
2487 unsigned load = fieldFromInstruction(Insn, 21, 1);
2488 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2489 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2492 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2493 uint64_t Address, const void *Decoder) {
2494 DecodeStatus S = MCDisassembler::Success;
2496 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2497 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2498 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2499 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2500 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2501 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2503 // Writeback Operand
2504 switch (Inst.getOpcode()) {
2505 case ARM::VST1d8wb_fixed:
2506 case ARM::VST1d16wb_fixed:
2507 case ARM::VST1d32wb_fixed:
2508 case ARM::VST1d64wb_fixed:
2509 case ARM::VST1d8wb_register:
2510 case ARM::VST1d16wb_register:
2511 case ARM::VST1d32wb_register:
2512 case ARM::VST1d64wb_register:
2513 case ARM::VST1q8wb_fixed:
2514 case ARM::VST1q16wb_fixed:
2515 case ARM::VST1q32wb_fixed:
2516 case ARM::VST1q64wb_fixed:
2517 case ARM::VST1q8wb_register:
2518 case ARM::VST1q16wb_register:
2519 case ARM::VST1q32wb_register:
2520 case ARM::VST1q64wb_register:
2521 case ARM::VST1d8Twb_fixed:
2522 case ARM::VST1d16Twb_fixed:
2523 case ARM::VST1d32Twb_fixed:
2524 case ARM::VST1d64Twb_fixed:
2525 case ARM::VST1d8Twb_register:
2526 case ARM::VST1d16Twb_register:
2527 case ARM::VST1d32Twb_register:
2528 case ARM::VST1d64Twb_register:
2529 case ARM::VST1d8Qwb_fixed:
2530 case ARM::VST1d16Qwb_fixed:
2531 case ARM::VST1d32Qwb_fixed:
2532 case ARM::VST1d64Qwb_fixed:
2533 case ARM::VST1d8Qwb_register:
2534 case ARM::VST1d16Qwb_register:
2535 case ARM::VST1d32Qwb_register:
2536 case ARM::VST1d64Qwb_register:
2537 case ARM::VST2d8wb_fixed:
2538 case ARM::VST2d16wb_fixed:
2539 case ARM::VST2d32wb_fixed:
2540 case ARM::VST2d8wb_register:
2541 case ARM::VST2d16wb_register:
2542 case ARM::VST2d32wb_register:
2543 case ARM::VST2q8wb_fixed:
2544 case ARM::VST2q16wb_fixed:
2545 case ARM::VST2q32wb_fixed:
2546 case ARM::VST2q8wb_register:
2547 case ARM::VST2q16wb_register:
2548 case ARM::VST2q32wb_register:
2549 case ARM::VST2b8wb_fixed:
2550 case ARM::VST2b16wb_fixed:
2551 case ARM::VST2b32wb_fixed:
2552 case ARM::VST2b8wb_register:
2553 case ARM::VST2b16wb_register:
2554 case ARM::VST2b32wb_register:
2556 return MCDisassembler::Fail;
2557 Inst.addOperand(MCOperand::CreateImm(0));
2559 case ARM::VST3d8_UPD:
2560 case ARM::VST3d16_UPD:
2561 case ARM::VST3d32_UPD:
2562 case ARM::VST3q8_UPD:
2563 case ARM::VST3q16_UPD:
2564 case ARM::VST3q32_UPD:
2565 case ARM::VST4d8_UPD:
2566 case ARM::VST4d16_UPD:
2567 case ARM::VST4d32_UPD:
2568 case ARM::VST4q8_UPD:
2569 case ARM::VST4q16_UPD:
2570 case ARM::VST4q32_UPD:
2571 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2572 return MCDisassembler::Fail;
2578 // AddrMode6 Base (register+alignment)
2579 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2580 return MCDisassembler::Fail;
2582 // AddrMode6 Offset (register)
2583 switch (Inst.getOpcode()) {
2586 Inst.addOperand(MCOperand::CreateReg(0));
2587 else if (Rm != 0xF) {
2588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2589 return MCDisassembler::Fail;
2592 case ARM::VST1d8wb_fixed:
2593 case ARM::VST1d16wb_fixed:
2594 case ARM::VST1d32wb_fixed:
2595 case ARM::VST1d64wb_fixed:
2596 case ARM::VST1q8wb_fixed:
2597 case ARM::VST1q16wb_fixed:
2598 case ARM::VST1q32wb_fixed:
2599 case ARM::VST1q64wb_fixed:
2600 case ARM::VST1d8Twb_fixed:
2601 case ARM::VST1d16Twb_fixed:
2602 case ARM::VST1d32Twb_fixed:
2603 case ARM::VST1d64Twb_fixed:
2604 case ARM::VST1d8Qwb_fixed:
2605 case ARM::VST1d16Qwb_fixed:
2606 case ARM::VST1d32Qwb_fixed:
2607 case ARM::VST1d64Qwb_fixed:
2608 case ARM::VST2d8wb_fixed:
2609 case ARM::VST2d16wb_fixed:
2610 case ARM::VST2d32wb_fixed:
2611 case ARM::VST2q8wb_fixed:
2612 case ARM::VST2q16wb_fixed:
2613 case ARM::VST2q32wb_fixed:
2614 case ARM::VST2b8wb_fixed:
2615 case ARM::VST2b16wb_fixed:
2616 case ARM::VST2b32wb_fixed:
2621 // First input register
2622 switch (Inst.getOpcode()) {
2627 case ARM::VST1q16wb_fixed:
2628 case ARM::VST1q16wb_register:
2629 case ARM::VST1q32wb_fixed:
2630 case ARM::VST1q32wb_register:
2631 case ARM::VST1q64wb_fixed:
2632 case ARM::VST1q64wb_register:
2633 case ARM::VST1q8wb_fixed:
2634 case ARM::VST1q8wb_register:
2638 case ARM::VST2d16wb_fixed:
2639 case ARM::VST2d16wb_register:
2640 case ARM::VST2d32wb_fixed:
2641 case ARM::VST2d32wb_register:
2642 case ARM::VST2d8wb_fixed:
2643 case ARM::VST2d8wb_register:
2644 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2645 return MCDisassembler::Fail;
2650 case ARM::VST2b16wb_fixed:
2651 case ARM::VST2b16wb_register:
2652 case ARM::VST2b32wb_fixed:
2653 case ARM::VST2b32wb_register:
2654 case ARM::VST2b8wb_fixed:
2655 case ARM::VST2b8wb_register:
2656 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2657 return MCDisassembler::Fail;
2660 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2661 return MCDisassembler::Fail;
2664 // Second input register
2665 switch (Inst.getOpcode()) {
2669 case ARM::VST3d8_UPD:
2670 case ARM::VST3d16_UPD:
2671 case ARM::VST3d32_UPD:
2675 case ARM::VST4d8_UPD:
2676 case ARM::VST4d16_UPD:
2677 case ARM::VST4d32_UPD:
2678 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2679 return MCDisassembler::Fail;
2684 case ARM::VST3q8_UPD:
2685 case ARM::VST3q16_UPD:
2686 case ARM::VST3q32_UPD:
2690 case ARM::VST4q8_UPD:
2691 case ARM::VST4q16_UPD:
2692 case ARM::VST4q32_UPD:
2693 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2694 return MCDisassembler::Fail;
2700 // Third input register
2701 switch (Inst.getOpcode()) {
2705 case ARM::VST3d8_UPD:
2706 case ARM::VST3d16_UPD:
2707 case ARM::VST3d32_UPD:
2711 case ARM::VST4d8_UPD:
2712 case ARM::VST4d16_UPD:
2713 case ARM::VST4d32_UPD:
2714 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2715 return MCDisassembler::Fail;
2720 case ARM::VST3q8_UPD:
2721 case ARM::VST3q16_UPD:
2722 case ARM::VST3q32_UPD:
2726 case ARM::VST4q8_UPD:
2727 case ARM::VST4q16_UPD:
2728 case ARM::VST4q32_UPD:
2729 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2730 return MCDisassembler::Fail;
2736 // Fourth input register
2737 switch (Inst.getOpcode()) {
2741 case ARM::VST4d8_UPD:
2742 case ARM::VST4d16_UPD:
2743 case ARM::VST4d32_UPD:
2744 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2745 return MCDisassembler::Fail;
2750 case ARM::VST4q8_UPD:
2751 case ARM::VST4q16_UPD:
2752 case ARM::VST4q32_UPD:
2753 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2754 return MCDisassembler::Fail;
2763 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2764 uint64_t Address, const void *Decoder) {
2765 DecodeStatus S = MCDisassembler::Success;
2767 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2768 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2769 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2770 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2771 unsigned align = fieldFromInstruction(Insn, 4, 1);
2772 unsigned size = fieldFromInstruction(Insn, 6, 2);
2774 if (size == 0 && align == 1)
2775 return MCDisassembler::Fail;
2776 align *= (1 << size);
2778 switch (Inst.getOpcode()) {
2779 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2780 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2781 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2782 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2783 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2784 return MCDisassembler::Fail;
2787 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2788 return MCDisassembler::Fail;
2792 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2793 return MCDisassembler::Fail;
2796 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2797 return MCDisassembler::Fail;
2798 Inst.addOperand(MCOperand::CreateImm(align));
2800 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2801 // variant encodes Rm == 0xf. Anything else is a register offset post-
2802 // increment and we need to add the register operand to the instruction.
2803 if (Rm != 0xD && Rm != 0xF &&
2804 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2805 return MCDisassembler::Fail;
2810 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2811 uint64_t Address, const void *Decoder) {
2812 DecodeStatus S = MCDisassembler::Success;
2814 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2815 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2816 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2817 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2818 unsigned align = fieldFromInstruction(Insn, 4, 1);
2819 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2822 switch (Inst.getOpcode()) {
2823 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2824 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2825 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2826 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2827 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2828 return MCDisassembler::Fail;
2830 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2831 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2832 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2833 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2834 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2835 return MCDisassembler::Fail;
2838 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2839 return MCDisassembler::Fail;
2844 Inst.addOperand(MCOperand::CreateImm(0));
2846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2847 return MCDisassembler::Fail;
2848 Inst.addOperand(MCOperand::CreateImm(align));
2850 if (Rm != 0xD && Rm != 0xF) {
2851 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2852 return MCDisassembler::Fail;
2858 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2859 uint64_t Address, const void *Decoder) {
2860 DecodeStatus S = MCDisassembler::Success;
2862 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2863 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2864 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2865 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2866 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2868 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2869 return MCDisassembler::Fail;
2870 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2871 return MCDisassembler::Fail;
2872 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2873 return MCDisassembler::Fail;
2875 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2876 return MCDisassembler::Fail;
2879 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2880 return MCDisassembler::Fail;
2881 Inst.addOperand(MCOperand::CreateImm(0));
2884 Inst.addOperand(MCOperand::CreateReg(0));
2885 else if (Rm != 0xF) {
2886 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2887 return MCDisassembler::Fail;
2893 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2894 uint64_t Address, const void *Decoder) {
2895 DecodeStatus S = MCDisassembler::Success;
2897 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2898 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2899 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2900 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2901 unsigned size = fieldFromInstruction(Insn, 6, 2);
2902 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2903 unsigned align = fieldFromInstruction(Insn, 4, 1);
2907 return MCDisassembler::Fail;
2920 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2921 return MCDisassembler::Fail;
2922 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2923 return MCDisassembler::Fail;
2924 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2925 return MCDisassembler::Fail;
2926 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2927 return MCDisassembler::Fail;
2929 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2930 return MCDisassembler::Fail;
2933 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2934 return MCDisassembler::Fail;
2935 Inst.addOperand(MCOperand::CreateImm(align));
2938 Inst.addOperand(MCOperand::CreateReg(0));
2939 else if (Rm != 0xF) {
2940 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2941 return MCDisassembler::Fail;
2948 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
2949 uint64_t Address, const void *Decoder) {
2950 DecodeStatus S = MCDisassembler::Success;
2952 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2953 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2954 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2955 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2956 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2957 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2958 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2959 unsigned Q = fieldFromInstruction(Insn, 6, 1);
2962 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2963 return MCDisassembler::Fail;
2965 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2966 return MCDisassembler::Fail;
2969 Inst.addOperand(MCOperand::CreateImm(imm));
2971 switch (Inst.getOpcode()) {
2972 case ARM::VORRiv4i16:
2973 case ARM::VORRiv2i32:
2974 case ARM::VBICiv4i16:
2975 case ARM::VBICiv2i32:
2976 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2977 return MCDisassembler::Fail;
2979 case ARM::VORRiv8i16:
2980 case ARM::VORRiv4i32:
2981 case ARM::VBICiv8i16:
2982 case ARM::VBICiv4i32:
2983 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
2984 return MCDisassembler::Fail;
2993 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
2994 uint64_t Address, const void *Decoder) {
2995 DecodeStatus S = MCDisassembler::Success;
2997 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2998 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2999 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3000 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3001 unsigned size = fieldFromInstruction(Insn, 18, 2);
3003 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3004 return MCDisassembler::Fail;
3005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3006 return MCDisassembler::Fail;
3007 Inst.addOperand(MCOperand::CreateImm(8 << size));
3012 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3013 uint64_t Address, const void *Decoder) {
3014 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3015 return MCDisassembler::Success;
3018 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3019 uint64_t Address, const void *Decoder) {
3020 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3021 return MCDisassembler::Success;
3024 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3025 uint64_t Address, const void *Decoder) {
3026 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3027 return MCDisassembler::Success;
3030 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3031 uint64_t Address, const void *Decoder) {
3032 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3033 return MCDisassembler::Success;
3036 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3037 uint64_t Address, const void *Decoder) {
3038 DecodeStatus S = MCDisassembler::Success;
3040 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3041 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3042 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3043 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3044 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3045 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3046 unsigned op = fieldFromInstruction(Insn, 6, 1);
3048 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3049 return MCDisassembler::Fail;
3051 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3052 return MCDisassembler::Fail; // Writeback
3055 switch (Inst.getOpcode()) {
3058 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3059 return MCDisassembler::Fail;
3062 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3063 return MCDisassembler::Fail;
3066 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3067 return MCDisassembler::Fail;
3072 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3073 uint64_t Address, const void *Decoder) {
3074 DecodeStatus S = MCDisassembler::Success;
3076 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3077 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3079 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3080 return MCDisassembler::Fail;
3082 switch(Inst.getOpcode()) {
3084 return MCDisassembler::Fail;
3086 break; // tADR does not explicitly represent the PC as an operand.
3088 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3092 Inst.addOperand(MCOperand::CreateImm(imm));
3096 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3097 uint64_t Address, const void *Decoder) {
3098 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3099 true, 2, Inst, Decoder))
3100 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3101 return MCDisassembler::Success;
3104 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3105 uint64_t Address, const void *Decoder) {
3106 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3107 true, 4, Inst, Decoder))
3108 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3109 return MCDisassembler::Success;
3112 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3113 uint64_t Address, const void *Decoder) {
3114 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3115 true, 2, Inst, Decoder))
3116 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3117 return MCDisassembler::Success;
3120 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3121 uint64_t Address, const void *Decoder) {
3122 DecodeStatus S = MCDisassembler::Success;
3124 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3125 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3127 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3128 return MCDisassembler::Fail;
3129 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3130 return MCDisassembler::Fail;
3135 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3136 uint64_t Address, const void *Decoder) {
3137 DecodeStatus S = MCDisassembler::Success;
3139 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3140 unsigned imm = fieldFromInstruction(Val, 3, 5);
3142 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3143 return MCDisassembler::Fail;
3144 Inst.addOperand(MCOperand::CreateImm(imm));
3149 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3150 uint64_t Address, const void *Decoder) {
3151 unsigned imm = Val << 2;
3153 Inst.addOperand(MCOperand::CreateImm(imm));
3154 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3156 return MCDisassembler::Success;
3159 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3160 uint64_t Address, const void *Decoder) {
3161 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3162 Inst.addOperand(MCOperand::CreateImm(Val));
3164 return MCDisassembler::Success;
3167 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3168 uint64_t Address, const void *Decoder) {
3169 DecodeStatus S = MCDisassembler::Success;
3171 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3172 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3173 unsigned imm = fieldFromInstruction(Val, 0, 2);
3175 // Thumb stores cannot use PC as dest register.
3176 switch (Inst.getOpcode()) {
3181 return MCDisassembler::Fail;
3186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3187 return MCDisassembler::Fail;
3188 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3189 return MCDisassembler::Fail;
3190 Inst.addOperand(MCOperand::CreateImm(imm));
3195 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3196 uint64_t Address, const void *Decoder) {
3197 DecodeStatus S = MCDisassembler::Success;
3199 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3200 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3203 switch (Inst.getOpcode()) {
3205 Inst.setOpcode(ARM::t2LDRBpci);
3208 Inst.setOpcode(ARM::t2LDRHpci);
3211 Inst.setOpcode(ARM::t2LDRSHpci);
3214 Inst.setOpcode(ARM::t2LDRSBpci);
3217 Inst.setOpcode(ARM::t2LDRpci);
3220 Inst.setOpcode(ARM::t2PLDpci);
3223 Inst.setOpcode(ARM::t2PLIpci);
3226 return MCDisassembler::Fail;
3229 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3233 switch (Inst.getOpcode()) {
3235 return MCDisassembler::Fail;
3237 // FIXME: this instruction is only available with MP extensions,
3238 // this should be checked first but we don't have access to the
3239 // feature bits here.
3240 Inst.setOpcode(ARM::t2PLDWs);
3247 switch (Inst.getOpcode()) {
3253 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3254 return MCDisassembler::Fail;
3257 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3258 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3259 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3260 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3261 return MCDisassembler::Fail;
3266 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3267 uint64_t Address, const void* Decoder) {
3268 DecodeStatus S = MCDisassembler::Success;
3270 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3271 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3272 unsigned U = fieldFromInstruction(Insn, 9, 1);
3273 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3278 switch (Inst.getOpcode()) {
3280 Inst.setOpcode(ARM::t2LDRpci);
3283 Inst.setOpcode(ARM::t2LDRBpci);
3285 case ARM::t2LDRSBi8:
3286 Inst.setOpcode(ARM::t2LDRSBpci);
3289 Inst.setOpcode(ARM::t2LDRHpci);
3291 case ARM::t2LDRSHi8:
3292 Inst.setOpcode(ARM::t2LDRSHpci);
3295 Inst.setOpcode(ARM::t2PLDpci);
3298 Inst.setOpcode(ARM::t2PLIpci);
3301 return MCDisassembler::Fail;
3303 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3307 switch (Inst.getOpcode()) {
3308 case ARM::t2LDRSHi8:
3309 return MCDisassembler::Fail;
3315 switch (Inst.getOpcode()) {
3320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3321 return MCDisassembler::Fail;
3324 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3325 return MCDisassembler::Fail;
3329 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3330 uint64_t Address, const void* Decoder) {
3331 DecodeStatus S = MCDisassembler::Success;
3333 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3334 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3335 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3339 switch (Inst.getOpcode()) {
3341 Inst.setOpcode(ARM::t2LDRpci);
3343 case ARM::t2LDRHi12:
3344 Inst.setOpcode(ARM::t2LDRHpci);
3346 case ARM::t2LDRSHi12:
3347 Inst.setOpcode(ARM::t2LDRSHpci);
3349 case ARM::t2LDRBi12:
3350 Inst.setOpcode(ARM::t2LDRBpci);
3352 case ARM::t2LDRSBi12:
3353 Inst.setOpcode(ARM::t2LDRSBpci);
3356 Inst.setOpcode(ARM::t2PLDpci);
3359 Inst.setOpcode(ARM::t2PLIpci);
3362 return MCDisassembler::Fail;
3364 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3368 switch (Inst.getOpcode()) {
3369 case ARM::t2LDRSHi12:
3370 return MCDisassembler::Fail;
3371 case ARM::t2LDRHi12:
3372 Inst.setOpcode(ARM::t2PLDi12);
3379 switch (Inst.getOpcode()) {
3384 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3385 return MCDisassembler::Fail;
3388 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3389 return MCDisassembler::Fail;
3393 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3394 uint64_t Address, const void* Decoder) {
3395 DecodeStatus S = MCDisassembler::Success;
3397 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3398 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3399 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3403 switch (Inst.getOpcode()) {
3405 Inst.setOpcode(ARM::t2LDRpci);
3408 Inst.setOpcode(ARM::t2LDRBpci);
3411 Inst.setOpcode(ARM::t2LDRHpci);
3414 Inst.setOpcode(ARM::t2LDRSBpci);
3417 Inst.setOpcode(ARM::t2LDRSHpci);
3420 return MCDisassembler::Fail;
3422 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3425 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3426 return MCDisassembler::Fail;
3427 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3428 return MCDisassembler::Fail;
3432 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3433 uint64_t Address, const void* Decoder) {
3434 DecodeStatus S = MCDisassembler::Success;
3436 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3437 unsigned U = fieldFromInstruction(Insn, 23, 1);
3438 int imm = fieldFromInstruction(Insn, 0, 12);
3441 switch (Inst.getOpcode()) {
3442 case ARM::t2LDRBpci:
3443 case ARM::t2LDRHpci:
3444 Inst.setOpcode(ARM::t2PLDpci);
3446 case ARM::t2LDRSBpci:
3447 Inst.setOpcode(ARM::t2PLIpci);
3449 case ARM::t2LDRSHpci:
3450 return MCDisassembler::Fail;
3456 switch(Inst.getOpcode()) {
3461 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3462 return MCDisassembler::Fail;
3466 // Special case for #-0.
3472 Inst.addOperand(MCOperand::CreateImm(imm));
3477 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3478 uint64_t Address, const void *Decoder) {
3480 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3482 int imm = Val & 0xFF;
3484 if (!(Val & 0x100)) imm *= -1;
3485 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3488 return MCDisassembler::Success;
3491 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3492 uint64_t Address, const void *Decoder) {
3493 DecodeStatus S = MCDisassembler::Success;
3495 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3496 unsigned imm = fieldFromInstruction(Val, 0, 9);
3498 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3499 return MCDisassembler::Fail;
3500 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3501 return MCDisassembler::Fail;
3506 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3507 uint64_t Address, const void *Decoder) {
3508 DecodeStatus S = MCDisassembler::Success;
3510 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3511 unsigned imm = fieldFromInstruction(Val, 0, 8);
3513 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3514 return MCDisassembler::Fail;
3516 Inst.addOperand(MCOperand::CreateImm(imm));
3521 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3522 uint64_t Address, const void *Decoder) {
3523 int imm = Val & 0xFF;
3526 else if (!(Val & 0x100))
3528 Inst.addOperand(MCOperand::CreateImm(imm));
3530 return MCDisassembler::Success;
3534 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3535 uint64_t Address, const void *Decoder) {
3536 DecodeStatus S = MCDisassembler::Success;
3538 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3539 unsigned imm = fieldFromInstruction(Val, 0, 9);
3541 // Thumb stores cannot use PC as dest register.
3542 switch (Inst.getOpcode()) {
3550 return MCDisassembler::Fail;
3556 // Some instructions always use an additive offset.
3557 switch (Inst.getOpcode()) {
3572 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3573 return MCDisassembler::Fail;
3574 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3575 return MCDisassembler::Fail;
3580 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3581 uint64_t Address, const void *Decoder) {
3582 DecodeStatus S = MCDisassembler::Success;
3584 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3585 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3586 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3587 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3589 unsigned load = fieldFromInstruction(Insn, 20, 1);
3592 switch (Inst.getOpcode()) {
3593 case ARM::t2LDR_PRE:
3594 case ARM::t2LDR_POST:
3595 Inst.setOpcode(ARM::t2LDRpci);
3597 case ARM::t2LDRB_PRE:
3598 case ARM::t2LDRB_POST:
3599 Inst.setOpcode(ARM::t2LDRBpci);
3601 case ARM::t2LDRH_PRE:
3602 case ARM::t2LDRH_POST:
3603 Inst.setOpcode(ARM::t2LDRHpci);
3605 case ARM::t2LDRSB_PRE:
3606 case ARM::t2LDRSB_POST:
3608 Inst.setOpcode(ARM::t2PLIpci);
3610 Inst.setOpcode(ARM::t2LDRSBpci);
3612 case ARM::t2LDRSH_PRE:
3613 case ARM::t2LDRSH_POST:
3614 Inst.setOpcode(ARM::t2LDRSHpci);
3617 return MCDisassembler::Fail;
3619 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3624 return MCDisassembler::Fail;
3627 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3628 return MCDisassembler::Fail;
3631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3632 return MCDisassembler::Fail;
3635 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3636 return MCDisassembler::Fail;
3641 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3642 uint64_t Address, const void *Decoder) {
3643 DecodeStatus S = MCDisassembler::Success;
3645 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3646 unsigned imm = fieldFromInstruction(Val, 0, 12);
3648 // Thumb stores cannot use PC as dest register.
3649 switch (Inst.getOpcode()) {
3651 case ARM::t2STRBi12:
3652 case ARM::t2STRHi12:
3654 return MCDisassembler::Fail;
3659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3660 return MCDisassembler::Fail;
3661 Inst.addOperand(MCOperand::CreateImm(imm));
3667 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3668 uint64_t Address, const void *Decoder) {
3669 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3671 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3672 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3673 Inst.addOperand(MCOperand::CreateImm(imm));
3675 return MCDisassembler::Success;
3678 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3679 uint64_t Address, const void *Decoder) {
3680 DecodeStatus S = MCDisassembler::Success;
3682 if (Inst.getOpcode() == ARM::tADDrSP) {
3683 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3684 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3687 return MCDisassembler::Fail;
3688 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3689 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3690 return MCDisassembler::Fail;
3691 } else if (Inst.getOpcode() == ARM::tADDspr) {
3692 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3694 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3695 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3696 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3697 return MCDisassembler::Fail;
3703 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3704 uint64_t Address, const void *Decoder) {
3705 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3706 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3708 Inst.addOperand(MCOperand::CreateImm(imod));
3709 Inst.addOperand(MCOperand::CreateImm(flags));
3711 return MCDisassembler::Success;
3714 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3715 uint64_t Address, const void *Decoder) {
3716 DecodeStatus S = MCDisassembler::Success;
3717 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3718 unsigned add = fieldFromInstruction(Insn, 4, 1);
3720 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3721 return MCDisassembler::Fail;
3722 Inst.addOperand(MCOperand::CreateImm(add));
3727 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3728 uint64_t Address, const void *Decoder) {
3729 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3730 // Note only one trailing zero not two. Also the J1 and J2 values are from
3731 // the encoded instruction. So here change to I1 and I2 values via:
3732 // I1 = NOT(J1 EOR S);
3733 // I2 = NOT(J2 EOR S);
3734 // and build the imm32 with two trailing zeros as documented:
3735 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3736 unsigned S = (Val >> 23) & 1;
3737 unsigned J1 = (Val >> 22) & 1;
3738 unsigned J2 = (Val >> 21) & 1;
3739 unsigned I1 = !(J1 ^ S);
3740 unsigned I2 = !(J2 ^ S);
3741 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3742 int imm32 = SignExtend32<25>(tmp << 1);
3744 if (!tryAddingSymbolicOperand(Address,
3745 (Address & ~2u) + imm32 + 4,
3746 true, 4, Inst, Decoder))
3747 Inst.addOperand(MCOperand::CreateImm(imm32));
3748 return MCDisassembler::Success;
3751 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3752 uint64_t Address, const void *Decoder) {
3753 if (Val == 0xA || Val == 0xB)
3754 return MCDisassembler::Fail;
3756 Inst.addOperand(MCOperand::CreateImm(Val));
3757 return MCDisassembler::Success;
3761 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3762 uint64_t Address, const void *Decoder) {
3763 DecodeStatus S = MCDisassembler::Success;
3765 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3766 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3768 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3769 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3770 return MCDisassembler::Fail;
3771 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3772 return MCDisassembler::Fail;
3777 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3778 uint64_t Address, const void *Decoder) {
3779 DecodeStatus S = MCDisassembler::Success;
3781 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3782 if (pred == 0xE || pred == 0xF) {
3783 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3786 return MCDisassembler::Fail;
3788 Inst.setOpcode(ARM::t2DSB);
3791 Inst.setOpcode(ARM::t2DMB);
3794 Inst.setOpcode(ARM::t2ISB);
3798 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3799 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3802 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3803 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3804 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3805 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3806 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3808 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3809 return MCDisassembler::Fail;
3810 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3811 return MCDisassembler::Fail;
3816 // Decode a shifted immediate operand. These basically consist
3817 // of an 8-bit value, and a 4-bit directive that specifies either
3818 // a splat operation or a rotation.
3819 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3820 uint64_t Address, const void *Decoder) {
3821 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3823 unsigned byte = fieldFromInstruction(Val, 8, 2);
3824 unsigned imm = fieldFromInstruction(Val, 0, 8);
3827 Inst.addOperand(MCOperand::CreateImm(imm));
3830 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3833 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3836 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3841 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3842 unsigned rot = fieldFromInstruction(Val, 7, 5);
3843 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3844 Inst.addOperand(MCOperand::CreateImm(imm));
3847 return MCDisassembler::Success;
3851 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3852 uint64_t Address, const void *Decoder){
3853 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3854 true, 2, Inst, Decoder))
3855 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3856 return MCDisassembler::Success;
3859 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3860 uint64_t Address, const void *Decoder){
3861 // Val is passed in as S:J1:J2:imm10:imm11
3862 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3863 // the encoded instruction. So here change to I1 and I2 values via:
3864 // I1 = NOT(J1 EOR S);
3865 // I2 = NOT(J2 EOR S);
3866 // and build the imm32 with one trailing zero as documented:
3867 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3868 unsigned S = (Val >> 23) & 1;
3869 unsigned J1 = (Val >> 22) & 1;
3870 unsigned J2 = (Val >> 21) & 1;
3871 unsigned I1 = !(J1 ^ S);
3872 unsigned I2 = !(J2 ^ S);
3873 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3874 int imm32 = SignExtend32<25>(tmp << 1);
3876 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3877 true, 4, Inst, Decoder))
3878 Inst.addOperand(MCOperand::CreateImm(imm32));
3879 return MCDisassembler::Success;
3882 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3883 uint64_t Address, const void *Decoder) {
3885 return MCDisassembler::Fail;
3887 Inst.addOperand(MCOperand::CreateImm(Val));
3888 return MCDisassembler::Success;
3891 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
3892 uint64_t Address, const void *Decoder) {
3894 return MCDisassembler::Fail;
3896 Inst.addOperand(MCOperand::CreateImm(Val));
3897 return MCDisassembler::Success;
3900 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3901 uint64_t Address, const void *Decoder) {
3902 if (!Val) return MCDisassembler::Fail;
3903 Inst.addOperand(MCOperand::CreateImm(Val));
3904 return MCDisassembler::Success;
3907 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
3908 uint64_t Address, const void *Decoder) {
3909 DecodeStatus S = MCDisassembler::Success;
3911 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3912 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3913 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3916 S = MCDisassembler::SoftFail;
3918 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
3919 return MCDisassembler::Fail;
3920 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3921 return MCDisassembler::Fail;
3922 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3923 return MCDisassembler::Fail;
3928 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
3929 uint64_t Address, const void *Decoder){
3930 DecodeStatus S = MCDisassembler::Success;
3932 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3933 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3934 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3935 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3937 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
3938 return MCDisassembler::Fail;
3940 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
3941 S = MCDisassembler::SoftFail;
3943 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
3944 return MCDisassembler::Fail;
3945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3946 return MCDisassembler::Fail;
3947 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3948 return MCDisassembler::Fail;
3953 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
3954 uint64_t Address, const void *Decoder) {
3955 DecodeStatus S = MCDisassembler::Success;
3957 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3958 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3959 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3960 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3961 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3962 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3964 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3966 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3967 return MCDisassembler::Fail;
3968 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3969 return MCDisassembler::Fail;
3970 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
3971 return MCDisassembler::Fail;
3972 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3973 return MCDisassembler::Fail;
3978 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
3979 uint64_t Address, const void *Decoder) {
3980 DecodeStatus S = MCDisassembler::Success;
3982 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3983 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3984 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3985 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3986 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3987 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3988 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3990 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
3991 if (Rm == 0xF) S = MCDisassembler::SoftFail;
3993 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3994 return MCDisassembler::Fail;
3995 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3996 return MCDisassembler::Fail;
3997 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
3998 return MCDisassembler::Fail;
3999 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4000 return MCDisassembler::Fail;
4006 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4007 uint64_t Address, const void *Decoder) {
4008 DecodeStatus S = MCDisassembler::Success;
4010 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4011 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4012 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4013 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4014 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4015 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4017 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4019 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4020 return MCDisassembler::Fail;
4021 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4022 return MCDisassembler::Fail;
4023 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4024 return MCDisassembler::Fail;
4025 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4026 return MCDisassembler::Fail;
4031 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4032 uint64_t Address, const void *Decoder) {
4033 DecodeStatus S = MCDisassembler::Success;
4035 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4036 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4037 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4038 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4039 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4040 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4042 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4044 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4045 return MCDisassembler::Fail;
4046 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4047 return MCDisassembler::Fail;
4048 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4049 return MCDisassembler::Fail;
4050 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4051 return MCDisassembler::Fail;
4056 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4057 uint64_t Address, const void *Decoder) {
4058 DecodeStatus S = MCDisassembler::Success;
4060 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4061 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4062 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4063 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4064 unsigned size = fieldFromInstruction(Insn, 10, 2);
4070 return MCDisassembler::Fail;
4072 if (fieldFromInstruction(Insn, 4, 1))
4073 return MCDisassembler::Fail; // UNDEFINED
4074 index = fieldFromInstruction(Insn, 5, 3);
4077 if (fieldFromInstruction(Insn, 5, 1))
4078 return MCDisassembler::Fail; // UNDEFINED
4079 index = fieldFromInstruction(Insn, 6, 2);
4080 if (fieldFromInstruction(Insn, 4, 1))
4084 if (fieldFromInstruction(Insn, 6, 1))
4085 return MCDisassembler::Fail; // UNDEFINED
4086 index = fieldFromInstruction(Insn, 7, 1);
4088 switch (fieldFromInstruction(Insn, 4, 2)) {
4094 return MCDisassembler::Fail;
4099 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4100 return MCDisassembler::Fail;
4101 if (Rm != 0xF) { // Writeback
4102 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4103 return MCDisassembler::Fail;
4105 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4106 return MCDisassembler::Fail;
4107 Inst.addOperand(MCOperand::CreateImm(align));
4110 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4111 return MCDisassembler::Fail;
4113 Inst.addOperand(MCOperand::CreateReg(0));
4116 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4117 return MCDisassembler::Fail;
4118 Inst.addOperand(MCOperand::CreateImm(index));
4123 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4124 uint64_t Address, const void *Decoder) {
4125 DecodeStatus S = MCDisassembler::Success;
4127 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4128 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4129 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4130 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4131 unsigned size = fieldFromInstruction(Insn, 10, 2);
4137 return MCDisassembler::Fail;
4139 if (fieldFromInstruction(Insn, 4, 1))
4140 return MCDisassembler::Fail; // UNDEFINED
4141 index = fieldFromInstruction(Insn, 5, 3);
4144 if (fieldFromInstruction(Insn, 5, 1))
4145 return MCDisassembler::Fail; // UNDEFINED
4146 index = fieldFromInstruction(Insn, 6, 2);
4147 if (fieldFromInstruction(Insn, 4, 1))
4151 if (fieldFromInstruction(Insn, 6, 1))
4152 return MCDisassembler::Fail; // UNDEFINED
4153 index = fieldFromInstruction(Insn, 7, 1);
4155 switch (fieldFromInstruction(Insn, 4, 2)) {
4161 return MCDisassembler::Fail;
4166 if (Rm != 0xF) { // Writeback
4167 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4168 return MCDisassembler::Fail;
4170 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4171 return MCDisassembler::Fail;
4172 Inst.addOperand(MCOperand::CreateImm(align));
4175 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4176 return MCDisassembler::Fail;
4178 Inst.addOperand(MCOperand::CreateReg(0));
4181 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4182 return MCDisassembler::Fail;
4183 Inst.addOperand(MCOperand::CreateImm(index));
4189 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4190 uint64_t Address, const void *Decoder) {
4191 DecodeStatus S = MCDisassembler::Success;
4193 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4194 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4195 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4196 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4197 unsigned size = fieldFromInstruction(Insn, 10, 2);
4204 return MCDisassembler::Fail;
4206 index = fieldFromInstruction(Insn, 5, 3);
4207 if (fieldFromInstruction(Insn, 4, 1))
4211 index = fieldFromInstruction(Insn, 6, 2);
4212 if (fieldFromInstruction(Insn, 4, 1))
4214 if (fieldFromInstruction(Insn, 5, 1))
4218 if (fieldFromInstruction(Insn, 5, 1))
4219 return MCDisassembler::Fail; // UNDEFINED
4220 index = fieldFromInstruction(Insn, 7, 1);
4221 if (fieldFromInstruction(Insn, 4, 1) != 0)
4223 if (fieldFromInstruction(Insn, 6, 1))
4228 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4229 return MCDisassembler::Fail;
4230 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4231 return MCDisassembler::Fail;
4232 if (Rm != 0xF) { // Writeback
4233 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4234 return MCDisassembler::Fail;
4236 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4237 return MCDisassembler::Fail;
4238 Inst.addOperand(MCOperand::CreateImm(align));
4241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4242 return MCDisassembler::Fail;
4244 Inst.addOperand(MCOperand::CreateReg(0));
4247 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4248 return MCDisassembler::Fail;
4249 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4250 return MCDisassembler::Fail;
4251 Inst.addOperand(MCOperand::CreateImm(index));
4256 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4257 uint64_t Address, const void *Decoder) {
4258 DecodeStatus S = MCDisassembler::Success;
4260 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4261 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4262 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4263 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4264 unsigned size = fieldFromInstruction(Insn, 10, 2);
4271 return MCDisassembler::Fail;
4273 index = fieldFromInstruction(Insn, 5, 3);
4274 if (fieldFromInstruction(Insn, 4, 1))
4278 index = fieldFromInstruction(Insn, 6, 2);
4279 if (fieldFromInstruction(Insn, 4, 1))
4281 if (fieldFromInstruction(Insn, 5, 1))
4285 if (fieldFromInstruction(Insn, 5, 1))
4286 return MCDisassembler::Fail; // UNDEFINED
4287 index = fieldFromInstruction(Insn, 7, 1);
4288 if (fieldFromInstruction(Insn, 4, 1) != 0)
4290 if (fieldFromInstruction(Insn, 6, 1))
4295 if (Rm != 0xF) { // Writeback
4296 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4297 return MCDisassembler::Fail;
4299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4300 return MCDisassembler::Fail;
4301 Inst.addOperand(MCOperand::CreateImm(align));
4304 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4305 return MCDisassembler::Fail;
4307 Inst.addOperand(MCOperand::CreateReg(0));
4310 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4311 return MCDisassembler::Fail;
4312 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4313 return MCDisassembler::Fail;
4314 Inst.addOperand(MCOperand::CreateImm(index));
4320 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4321 uint64_t Address, const void *Decoder) {
4322 DecodeStatus S = MCDisassembler::Success;
4324 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4325 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4326 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4327 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4328 unsigned size = fieldFromInstruction(Insn, 10, 2);
4335 return MCDisassembler::Fail;
4337 if (fieldFromInstruction(Insn, 4, 1))
4338 return MCDisassembler::Fail; // UNDEFINED
4339 index = fieldFromInstruction(Insn, 5, 3);
4342 if (fieldFromInstruction(Insn, 4, 1))
4343 return MCDisassembler::Fail; // UNDEFINED
4344 index = fieldFromInstruction(Insn, 6, 2);
4345 if (fieldFromInstruction(Insn, 5, 1))
4349 if (fieldFromInstruction(Insn, 4, 2))
4350 return MCDisassembler::Fail; // UNDEFINED
4351 index = fieldFromInstruction(Insn, 7, 1);
4352 if (fieldFromInstruction(Insn, 6, 1))
4357 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4358 return MCDisassembler::Fail;
4359 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4360 return MCDisassembler::Fail;
4361 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4362 return MCDisassembler::Fail;
4364 if (Rm != 0xF) { // Writeback
4365 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4366 return MCDisassembler::Fail;
4368 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4369 return MCDisassembler::Fail;
4370 Inst.addOperand(MCOperand::CreateImm(align));
4373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4374 return MCDisassembler::Fail;
4376 Inst.addOperand(MCOperand::CreateReg(0));
4379 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4380 return MCDisassembler::Fail;
4381 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4382 return MCDisassembler::Fail;
4383 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4384 return MCDisassembler::Fail;
4385 Inst.addOperand(MCOperand::CreateImm(index));
4390 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4391 uint64_t Address, const void *Decoder) {
4392 DecodeStatus S = MCDisassembler::Success;
4394 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4395 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4396 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4397 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4398 unsigned size = fieldFromInstruction(Insn, 10, 2);
4405 return MCDisassembler::Fail;
4407 if (fieldFromInstruction(Insn, 4, 1))
4408 return MCDisassembler::Fail; // UNDEFINED
4409 index = fieldFromInstruction(Insn, 5, 3);
4412 if (fieldFromInstruction(Insn, 4, 1))
4413 return MCDisassembler::Fail; // UNDEFINED
4414 index = fieldFromInstruction(Insn, 6, 2);
4415 if (fieldFromInstruction(Insn, 5, 1))
4419 if (fieldFromInstruction(Insn, 4, 2))
4420 return MCDisassembler::Fail; // UNDEFINED
4421 index = fieldFromInstruction(Insn, 7, 1);
4422 if (fieldFromInstruction(Insn, 6, 1))
4427 if (Rm != 0xF) { // Writeback
4428 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4429 return MCDisassembler::Fail;
4431 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4432 return MCDisassembler::Fail;
4433 Inst.addOperand(MCOperand::CreateImm(align));
4436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4437 return MCDisassembler::Fail;
4439 Inst.addOperand(MCOperand::CreateReg(0));
4442 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4443 return MCDisassembler::Fail;
4444 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4445 return MCDisassembler::Fail;
4446 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4447 return MCDisassembler::Fail;
4448 Inst.addOperand(MCOperand::CreateImm(index));
4454 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4455 uint64_t Address, const void *Decoder) {
4456 DecodeStatus S = MCDisassembler::Success;
4458 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4459 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4460 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4461 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4462 unsigned size = fieldFromInstruction(Insn, 10, 2);
4469 return MCDisassembler::Fail;
4471 if (fieldFromInstruction(Insn, 4, 1))
4473 index = fieldFromInstruction(Insn, 5, 3);
4476 if (fieldFromInstruction(Insn, 4, 1))
4478 index = fieldFromInstruction(Insn, 6, 2);
4479 if (fieldFromInstruction(Insn, 5, 1))
4483 switch (fieldFromInstruction(Insn, 4, 2)) {
4487 return MCDisassembler::Fail;
4489 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4492 index = fieldFromInstruction(Insn, 7, 1);
4493 if (fieldFromInstruction(Insn, 6, 1))
4498 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4499 return MCDisassembler::Fail;
4500 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4501 return MCDisassembler::Fail;
4502 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4503 return MCDisassembler::Fail;
4504 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4505 return MCDisassembler::Fail;
4507 if (Rm != 0xF) { // Writeback
4508 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4509 return MCDisassembler::Fail;
4511 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4512 return MCDisassembler::Fail;
4513 Inst.addOperand(MCOperand::CreateImm(align));
4516 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4517 return MCDisassembler::Fail;
4519 Inst.addOperand(MCOperand::CreateReg(0));
4522 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4523 return MCDisassembler::Fail;
4524 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4525 return MCDisassembler::Fail;
4526 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4527 return MCDisassembler::Fail;
4528 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4529 return MCDisassembler::Fail;
4530 Inst.addOperand(MCOperand::CreateImm(index));
4535 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4536 uint64_t Address, const void *Decoder) {
4537 DecodeStatus S = MCDisassembler::Success;
4539 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4540 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4541 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4542 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4543 unsigned size = fieldFromInstruction(Insn, 10, 2);
4550 return MCDisassembler::Fail;
4552 if (fieldFromInstruction(Insn, 4, 1))
4554 index = fieldFromInstruction(Insn, 5, 3);
4557 if (fieldFromInstruction(Insn, 4, 1))
4559 index = fieldFromInstruction(Insn, 6, 2);
4560 if (fieldFromInstruction(Insn, 5, 1))
4564 switch (fieldFromInstruction(Insn, 4, 2)) {
4568 return MCDisassembler::Fail;
4570 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4573 index = fieldFromInstruction(Insn, 7, 1);
4574 if (fieldFromInstruction(Insn, 6, 1))
4579 if (Rm != 0xF) { // Writeback
4580 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4581 return MCDisassembler::Fail;
4583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4584 return MCDisassembler::Fail;
4585 Inst.addOperand(MCOperand::CreateImm(align));
4588 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4589 return MCDisassembler::Fail;
4591 Inst.addOperand(MCOperand::CreateReg(0));
4594 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4595 return MCDisassembler::Fail;
4596 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4597 return MCDisassembler::Fail;
4598 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4599 return MCDisassembler::Fail;
4600 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4601 return MCDisassembler::Fail;
4602 Inst.addOperand(MCOperand::CreateImm(index));
4607 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4608 uint64_t Address, const void *Decoder) {
4609 DecodeStatus S = MCDisassembler::Success;
4610 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4611 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4612 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4613 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4614 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4616 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4617 S = MCDisassembler::SoftFail;
4619 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4620 return MCDisassembler::Fail;
4621 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4622 return MCDisassembler::Fail;
4623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4624 return MCDisassembler::Fail;
4625 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4626 return MCDisassembler::Fail;
4627 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4628 return MCDisassembler::Fail;
4633 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4634 uint64_t Address, const void *Decoder) {
4635 DecodeStatus S = MCDisassembler::Success;
4636 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4637 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4638 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4639 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4640 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4642 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4643 S = MCDisassembler::SoftFail;
4645 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4646 return MCDisassembler::Fail;
4647 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4648 return MCDisassembler::Fail;
4649 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4650 return MCDisassembler::Fail;
4651 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4652 return MCDisassembler::Fail;
4653 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4654 return MCDisassembler::Fail;
4659 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4660 uint64_t Address, const void *Decoder) {
4661 DecodeStatus S = MCDisassembler::Success;
4662 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4663 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4667 S = MCDisassembler::SoftFail;
4672 S = MCDisassembler::SoftFail;
4675 Inst.addOperand(MCOperand::CreateImm(pred));
4676 Inst.addOperand(MCOperand::CreateImm(mask));
4681 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4682 uint64_t Address, const void *Decoder) {
4683 DecodeStatus S = MCDisassembler::Success;
4685 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4686 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4687 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4688 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4689 unsigned W = fieldFromInstruction(Insn, 21, 1);
4690 unsigned U = fieldFromInstruction(Insn, 23, 1);
4691 unsigned P = fieldFromInstruction(Insn, 24, 1);
4692 bool writeback = (W == 1) | (P == 0);
4694 addr |= (U << 8) | (Rn << 9);
4696 if (writeback && (Rn == Rt || Rn == Rt2))
4697 Check(S, MCDisassembler::SoftFail);
4699 Check(S, MCDisassembler::SoftFail);
4702 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4703 return MCDisassembler::Fail;
4705 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4706 return MCDisassembler::Fail;
4707 // Writeback operand
4708 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4709 return MCDisassembler::Fail;
4711 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4712 return MCDisassembler::Fail;
4718 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4719 uint64_t Address, const void *Decoder) {
4720 DecodeStatus S = MCDisassembler::Success;
4722 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4723 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4724 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4725 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4726 unsigned W = fieldFromInstruction(Insn, 21, 1);
4727 unsigned U = fieldFromInstruction(Insn, 23, 1);
4728 unsigned P = fieldFromInstruction(Insn, 24, 1);
4729 bool writeback = (W == 1) | (P == 0);
4731 addr |= (U << 8) | (Rn << 9);
4733 if (writeback && (Rn == Rt || Rn == Rt2))
4734 Check(S, MCDisassembler::SoftFail);
4736 // Writeback operand
4737 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4738 return MCDisassembler::Fail;
4740 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4741 return MCDisassembler::Fail;
4743 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4744 return MCDisassembler::Fail;
4746 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4747 return MCDisassembler::Fail;
4752 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4753 uint64_t Address, const void *Decoder) {
4754 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4755 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4756 if (sign1 != sign2) return MCDisassembler::Fail;
4758 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4759 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4760 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4762 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4764 return MCDisassembler::Success;
4767 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4769 const void *Decoder) {
4770 DecodeStatus S = MCDisassembler::Success;
4772 // Shift of "asr #32" is not allowed in Thumb2 mode.
4773 if (Val == 0x20) S = MCDisassembler::SoftFail;
4774 Inst.addOperand(MCOperand::CreateImm(Val));
4778 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4779 uint64_t Address, const void *Decoder) {
4780 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4781 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4782 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4783 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4786 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4788 DecodeStatus S = MCDisassembler::Success;
4790 if (Rt == Rn || Rn == Rt2)
4791 S = MCDisassembler::SoftFail;
4793 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4794 return MCDisassembler::Fail;
4795 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4796 return MCDisassembler::Fail;
4797 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4798 return MCDisassembler::Fail;
4799 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4800 return MCDisassembler::Fail;
4805 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4806 uint64_t Address, const void *Decoder) {
4807 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4808 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4809 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4810 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4811 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4812 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4813 unsigned op = fieldFromInstruction(Insn, 5, 1);
4815 DecodeStatus S = MCDisassembler::Success;
4817 // VMOVv2f32 is ambiguous with these decodings.
4818 if (!(imm & 0x38) && cmode == 0xF) {
4819 if (op == 1) return MCDisassembler::Fail;
4820 Inst.setOpcode(ARM::VMOVv2f32);
4821 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4824 if (!(imm & 0x20)) return MCDisassembler::Fail;
4826 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4827 return MCDisassembler::Fail;
4828 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4829 return MCDisassembler::Fail;
4830 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4835 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4836 uint64_t Address, const void *Decoder) {
4837 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4838 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4839 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4840 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4841 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4842 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4843 unsigned op = fieldFromInstruction(Insn, 5, 1);
4845 DecodeStatus S = MCDisassembler::Success;
4847 // VMOVv4f32 is ambiguous with these decodings.
4848 if (!(imm & 0x38) && cmode == 0xF) {
4849 if (op == 1) return MCDisassembler::Fail;
4850 Inst.setOpcode(ARM::VMOVv4f32);
4851 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4854 if (!(imm & 0x20)) return MCDisassembler::Fail;
4856 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
4857 return MCDisassembler::Fail;
4858 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
4859 return MCDisassembler::Fail;
4860 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4865 static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
4866 const void *Decoder)
4868 unsigned Imm = fieldFromInstruction(Insn, 0, 3);
4869 if (Imm > 4) return MCDisassembler::Fail;
4870 Inst.addOperand(MCOperand::CreateImm(Imm));
4871 return MCDisassembler::Success;
4874 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
4875 uint64_t Address, const void *Decoder) {
4876 DecodeStatus S = MCDisassembler::Success;
4878 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4879 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4880 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4881 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4882 unsigned Cond = fieldFromInstruction(Val, 28, 4);
4884 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
4885 S = MCDisassembler::SoftFail;
4887 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4888 return MCDisassembler::Fail;
4889 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4890 return MCDisassembler::Fail;
4891 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
4892 return MCDisassembler::Fail;
4893 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
4894 return MCDisassembler::Fail;
4895 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
4896 return MCDisassembler::Fail;
4901 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4902 uint64_t Address, const void *Decoder) {
4904 DecodeStatus S = MCDisassembler::Success;
4906 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4907 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4908 unsigned cop = fieldFromInstruction(Val, 8, 4);
4909 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4910 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
4912 if ((cop & ~0x1) == 0xa)
4913 return MCDisassembler::Fail;
4916 S = MCDisassembler::SoftFail;
4918 Inst.addOperand(MCOperand::CreateImm(cop));
4919 Inst.addOperand(MCOperand::CreateImm(opc1));
4920 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4921 return MCDisassembler::Fail;
4922 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4923 return MCDisassembler::Fail;
4924 Inst.addOperand(MCOperand::CreateImm(CRm));