1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCDisassembler.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/MC/MCContext.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCFixedLenDisassembler.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/MC/MCSubtargetInfo.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/LEB128.h"
23 #include "llvm/Support/MemoryObject.h"
24 #include "llvm/Support/TargetRegistry.h"
25 #include "llvm/Support/raw_ostream.h"
30 #define DEBUG_TYPE "arm-disassembler"
32 typedef MCDisassembler::DecodeStatus DecodeStatus;
35 // Handles the condition code status of instructions in IT blocks
39 // Returns the condition code for instruction in IT block
41 unsigned CC = ARMCC::AL;
47 // Advances the IT block state to the next T or E
48 void advanceITState() {
52 // Returns true if the current instruction is in an IT block
53 bool instrInITBlock() {
54 return !ITStates.empty();
57 // Returns true if current instruction is the last instruction in an IT block
58 bool instrLastInITBlock() {
59 return ITStates.size() == 1;
62 // Called when decoding an IT instruction. Sets the IT state for the following
63 // instructions that for the IT block. Firstcond and Mask correspond to the
64 // fields in the IT instruction encoding.
65 void setITState(char Firstcond, char Mask) {
66 // (3 - the number of trailing zeros) is the number of then / else.
67 unsigned CondBit0 = Firstcond & 1;
68 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
69 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
70 assert(NumTZ <= 3 && "Invalid IT mask!");
71 // push condition codes onto the stack the correct order for the pops
72 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
73 bool T = ((Mask >> Pos) & 1) == CondBit0;
75 ITStates.push_back(CCBits);
77 ITStates.push_back(CCBits ^ 1);
79 ITStates.push_back(CCBits);
83 std::vector<unsigned char> ITStates;
88 /// ARMDisassembler - ARM disassembler for all ARM platforms.
89 class ARMDisassembler : public MCDisassembler {
91 /// Constructor - Initializes the disassembler.
93 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
94 MCDisassembler(STI, Ctx) {
100 /// getInstruction - See MCDisassembler.
101 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
102 const MemoryObject ®ion, uint64_t address,
103 raw_ostream &vStream,
104 raw_ostream &cStream) const override;
107 /// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
108 class ThumbDisassembler : public MCDisassembler {
110 /// Constructor - Initializes the disassembler.
112 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
113 MCDisassembler(STI, Ctx) {
116 ~ThumbDisassembler() {
119 /// getInstruction - See MCDisassembler.
120 DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
121 const MemoryObject ®ion, uint64_t address,
122 raw_ostream &vStream,
123 raw_ostream &cStream) const override;
126 mutable ITStatus ITBlock;
127 DecodeStatus AddThumbPredicate(MCInst&) const;
128 void UpdateThumbVFPPredicate(MCInst&) const;
132 static bool Check(DecodeStatus &Out, DecodeStatus In) {
134 case MCDisassembler::Success:
135 // Out stays the same.
137 case MCDisassembler::SoftFail:
140 case MCDisassembler::Fail:
144 llvm_unreachable("Invalid DecodeStatus!");
148 // Forward declare these because the autogenerated code will reference them.
149 // Definitions are further down.
150 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 uint64_t Address, const void *Decoder);
152 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
153 unsigned RegNo, uint64_t Address,
154 const void *Decoder);
155 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
156 unsigned RegNo, uint64_t Address,
157 const void *Decoder);
158 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 uint64_t Address, const void *Decoder);
160 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 uint64_t Address, const void *Decoder);
162 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
163 uint64_t Address, const void *Decoder);
164 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
165 uint64_t Address, const void *Decoder);
166 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
167 uint64_t Address, const void *Decoder);
168 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
169 uint64_t Address, const void *Decoder);
170 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
171 uint64_t Address, const void *Decoder);
172 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
175 const void *Decoder);
176 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
177 uint64_t Address, const void *Decoder);
178 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
179 uint64_t Address, const void *Decoder);
180 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
181 unsigned RegNo, uint64_t Address,
182 const void *Decoder);
184 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
185 uint64_t Address, const void *Decoder);
186 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
187 uint64_t Address, const void *Decoder);
188 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
189 uint64_t Address, const void *Decoder);
190 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
191 uint64_t Address, const void *Decoder);
192 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
193 uint64_t Address, const void *Decoder);
194 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
195 uint64_t Address, const void *Decoder);
197 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
198 uint64_t Address, const void *Decoder);
199 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
200 uint64_t Address, const void *Decoder);
201 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
204 const void *Decoder);
205 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
206 uint64_t Address, const void *Decoder);
207 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
208 uint64_t Address, const void *Decoder);
209 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
210 uint64_t Address, const void *Decoder);
211 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
212 uint64_t Address, const void *Decoder);
214 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
217 const void *Decoder);
218 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
219 uint64_t Address, const void *Decoder);
220 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
221 uint64_t Address, const void *Decoder);
222 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
223 uint64_t Address, const void *Decoder);
224 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
225 uint64_t Address, const void *Decoder);
226 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
227 uint64_t Address, const void *Decoder);
228 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
229 uint64_t Address, const void *Decoder);
230 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
231 uint64_t Address, const void *Decoder);
232 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
233 uint64_t Address, const void *Decoder);
234 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
235 uint64_t Address, const void *Decoder);
236 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
237 uint64_t Address, const void *Decoder);
238 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
239 uint64_t Address, const void *Decoder);
240 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
241 uint64_t Address, const void *Decoder);
242 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
243 uint64_t Address, const void *Decoder);
244 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
245 uint64_t Address, const void *Decoder);
246 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
247 uint64_t Address, const void *Decoder);
248 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
249 uint64_t Address, const void *Decoder);
250 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
251 uint64_t Address, const void *Decoder);
252 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
253 uint64_t Address, const void *Decoder);
254 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
255 uint64_t Address, const void *Decoder);
256 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
257 uint64_t Address, const void *Decoder);
258 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
259 uint64_t Address, const void *Decoder);
260 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
261 uint64_t Address, const void *Decoder);
262 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
263 uint64_t Address, const void *Decoder);
264 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
265 uint64_t Address, const void *Decoder);
266 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
267 uint64_t Address, const void *Decoder);
268 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
269 uint64_t Address, const void *Decoder);
270 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
271 uint64_t Address, const void *Decoder);
272 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
273 uint64_t Address, const void *Decoder);
274 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
275 uint64_t Address, const void *Decoder);
276 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
277 uint64_t Address, const void *Decoder);
278 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
279 uint64_t Address, const void *Decoder);
280 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
281 uint64_t Address, const void *Decoder);
282 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
283 uint64_t Address, const void *Decoder);
284 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
285 uint64_t Address, const void *Decoder);
286 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
287 uint64_t Address, const void *Decoder);
288 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
289 uint64_t Address, const void *Decoder);
290 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
291 uint64_t Address, const void *Decoder);
292 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
293 uint64_t Address, const void *Decoder);
294 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
295 uint64_t Address, const void *Decoder);
296 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
297 uint64_t Address, const void *Decoder);
298 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
299 uint64_t Address, const void *Decoder);
300 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
301 uint64_t Address, const void *Decoder);
302 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
303 uint64_t Address, const void *Decoder);
304 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
305 uint64_t Address, const void *Decoder);
306 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
307 uint64_t Address, const void *Decoder);
308 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
309 uint64_t Address, const void *Decoder);
310 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
311 uint64_t Address, const void *Decoder);
312 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
313 uint64_t Address, const void *Decoder);
314 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
315 uint64_t Address, const void *Decoder);
316 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
317 uint64_t Address, const void *Decoder);
318 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
319 uint64_t Address, const void *Decoder);
320 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
321 uint64_t Address, const void *Decoder);
322 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
323 uint64_t Address, const void *Decoder);
326 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
329 uint64_t Address, const void *Decoder);
330 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
331 uint64_t Address, const void *Decoder);
332 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
333 uint64_t Address, const void *Decoder);
334 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
335 uint64_t Address, const void *Decoder);
336 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
337 uint64_t Address, const void *Decoder);
338 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
339 uint64_t Address, const void *Decoder);
340 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
341 uint64_t Address, const void *Decoder);
342 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
343 uint64_t Address, const void *Decoder);
344 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
345 uint64_t Address, const void *Decoder);
346 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
347 uint64_t Address, const void* Decoder);
348 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
349 uint64_t Address, const void* Decoder);
350 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
351 uint64_t Address, const void* Decoder);
352 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
353 uint64_t Address, const void* Decoder);
354 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
355 uint64_t Address, const void *Decoder);
356 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
357 uint64_t Address, const void *Decoder);
358 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
359 uint64_t Address, const void *Decoder);
360 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
361 uint64_t Address, const void *Decoder);
362 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
363 uint64_t Address, const void *Decoder);
364 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
365 uint64_t Address, const void *Decoder);
366 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
367 uint64_t Address, const void *Decoder);
368 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
369 uint64_t Address, const void *Decoder);
370 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
371 uint64_t Address, const void *Decoder);
372 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
373 uint64_t Address, const void *Decoder);
374 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
375 uint64_t Address, const void *Decoder);
376 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
377 uint64_t Address, const void *Decoder);
378 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
379 uint64_t Address, const void *Decoder);
380 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
381 uint64_t Address, const void *Decoder);
382 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
383 uint64_t Address, const void *Decoder);
384 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
385 uint64_t Address, const void *Decoder);
386 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
387 uint64_t Address, const void *Decoder);
388 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
389 uint64_t Address, const void *Decoder);
390 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
391 uint64_t Address, const void *Decoder);
392 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
393 uint64_t Address, const void *Decoder);
394 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
395 uint64_t Address, const void *Decoder);
396 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
397 uint64_t Address, const void *Decoder);
399 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
400 uint64_t Address, const void *Decoder);
401 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
402 uint64_t Address, const void *Decoder);
403 #include "ARMGenDisassemblerTables.inc"
405 static MCDisassembler *createARMDisassembler(const Target &T,
406 const MCSubtargetInfo &STI,
408 return new ARMDisassembler(STI, Ctx);
411 static MCDisassembler *createThumbDisassembler(const Target &T,
412 const MCSubtargetInfo &STI,
414 return new ThumbDisassembler(STI, Ctx);
417 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
418 const MemoryObject &Region,
421 raw_ostream &cs) const {
426 assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
427 "Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
429 // We want to read exactly 4 bytes of data.
430 if (Region.readBytes(Address, 4, bytes) == -1) {
432 return MCDisassembler::Fail;
435 // Encoded as a small-endian 32-bit word in the stream.
436 uint32_t insn = (bytes[3] << 24) |
441 // Calling the auto-generated decoder function.
442 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
444 if (result != MCDisassembler::Fail) {
449 // VFP and NEON instructions, similarly, are shared between ARM
452 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
453 if (result != MCDisassembler::Fail) {
459 result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
460 if (result != MCDisassembler::Fail) {
466 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
468 if (result != MCDisassembler::Fail) {
470 // Add a fake predicate operand, because we share these instruction
471 // definitions with Thumb2 where these instructions are predicable.
472 if (!DecodePredicateOperand(MI, 0xE, Address, this))
473 return MCDisassembler::Fail;
478 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
480 if (result != MCDisassembler::Fail) {
482 // Add a fake predicate operand, because we share these instruction
483 // definitions with Thumb2 where these instructions are predicable.
484 if (!DecodePredicateOperand(MI, 0xE, Address, this))
485 return MCDisassembler::Fail;
490 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
492 if (result != MCDisassembler::Fail) {
494 // Add a fake predicate operand, because we share these instruction
495 // definitions with Thumb2 where these instructions are predicable.
496 if (!DecodePredicateOperand(MI, 0xE, Address, this))
497 return MCDisassembler::Fail;
502 result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address,
504 if (result != MCDisassembler::Fail) {
510 result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address,
512 if (result != MCDisassembler::Fail) {
519 return MCDisassembler::Fail;
523 extern const MCInstrDesc ARMInsts[];
526 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
527 /// immediate Value in the MCInst. The immediate Value has had any PC
528 /// adjustment made by the caller. If the instruction is a branch instruction
529 /// then isBranch is true, else false. If the getOpInfo() function was set as
530 /// part of the setupForSymbolicDisassembly() call then that function is called
531 /// to get any symbolic information at the Address for this instruction. If
532 /// that returns non-zero then the symbolic information it returns is used to
533 /// create an MCExpr and that is added as an operand to the MCInst. If
534 /// getOpInfo() returns zero and isBranch is true then a symbol look up for
535 /// Value is done and if a symbol is found an MCExpr is created with that, else
536 /// an MCExpr with Value is created. This function returns true if it adds an
537 /// operand to the MCInst and false otherwise.
538 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
539 bool isBranch, uint64_t InstSize,
540 MCInst &MI, const void *Decoder) {
541 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
542 // FIXME: Does it make sense for value to be negative?
543 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
544 /* Offset */ 0, InstSize);
547 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
548 /// referenced by a load instruction with the base register that is the Pc.
549 /// These can often be values in a literal pool near the Address of the
550 /// instruction. The Address of the instruction and its immediate Value are
551 /// used as a possible literal pool entry. The SymbolLookUp call back will
552 /// return the name of a symbol referenced by the literal pool's entry if
553 /// the referenced address is that of a symbol. Or it will return a pointer to
554 /// a literal 'C' string if the referenced address of the literal pool's entry
555 /// is an address into a section with 'C' string literals.
556 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
557 const void *Decoder) {
558 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder);
559 Dis->tryAddingPcLoadReferenceComment(Value, Address);
562 // Thumb1 instructions don't have explicit S bits. Rather, they
563 // implicitly set CPSR. Since it's not represented in the encoding, the
564 // auto-generated decoder won't inject the CPSR operand. We need to fix
565 // that as a post-pass.
566 static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
567 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
568 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
569 MCInst::iterator I = MI.begin();
570 for (unsigned i = 0; i < NumOps; ++i, ++I) {
571 if (I == MI.end()) break;
572 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
573 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
574 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
579 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
582 // Most Thumb instructions don't have explicit predicates in the
583 // encoding, but rather get their predicates from IT context. We need
584 // to fix up the predicate operands using this context information as a
586 MCDisassembler::DecodeStatus
587 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
588 MCDisassembler::DecodeStatus S = Success;
590 // A few instructions actually have predicates encoded in them. Don't
591 // try to overwrite it if we're seeing one of those.
592 switch (MI.getOpcode()) {
603 // Some instructions (mostly conditional branches) are not
604 // allowed in IT blocks.
605 if (ITBlock.instrInITBlock())
614 // Some instructions (mostly unconditional branches) can
615 // only appears at the end of, or outside of, an IT.
616 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
623 // If we're in an IT block, base the predicate on that. Otherwise,
624 // assume a predicate of AL.
626 CC = ITBlock.getITCC();
629 if (ITBlock.instrInITBlock())
630 ITBlock.advanceITState();
632 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
633 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
634 MCInst::iterator I = MI.begin();
635 for (unsigned i = 0; i < NumOps; ++i, ++I) {
636 if (I == MI.end()) break;
637 if (OpInfo[i].isPredicate()) {
638 I = MI.insert(I, MCOperand::CreateImm(CC));
641 MI.insert(I, MCOperand::CreateReg(0));
643 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
648 I = MI.insert(I, MCOperand::CreateImm(CC));
651 MI.insert(I, MCOperand::CreateReg(0));
653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
658 // Thumb VFP instructions are a special case. Because we share their
659 // encodings between ARM and Thumb modes, and they are predicable in ARM
660 // mode, the auto-generated decoder will give them an (incorrect)
661 // predicate operand. We need to rewrite these operands based on the IT
662 // context as a post-pass.
663 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
665 CC = ITBlock.getITCC();
666 if (ITBlock.instrInITBlock())
667 ITBlock.advanceITState();
669 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
670 MCInst::iterator I = MI.begin();
671 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
672 for (unsigned i = 0; i < NumOps; ++i, ++I) {
673 if (OpInfo[i].isPredicate() ) {
679 I->setReg(ARM::CPSR);
685 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
686 const MemoryObject &Region,
689 raw_ostream &cs) const {
694 assert((STI.getFeatureBits() & ARM::ModeThumb) &&
695 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
697 // We want to read exactly 2 bytes of data.
698 if (Region.readBytes(Address, 2, bytes) == -1) {
700 return MCDisassembler::Fail;
703 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
704 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
706 if (result != MCDisassembler::Fail) {
708 Check(result, AddThumbPredicate(MI));
713 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
717 bool InITBlock = ITBlock.instrInITBlock();
718 Check(result, AddThumbPredicate(MI));
719 AddThumb1SBit(MI, InITBlock);
724 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
726 if (result != MCDisassembler::Fail) {
729 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add
730 // the Thumb predicate.
731 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
732 result = MCDisassembler::SoftFail;
734 Check(result, AddThumbPredicate(MI));
736 // If we find an IT instruction, we need to parse its condition
737 // code and mask operands so that we can apply them correctly
738 // to the subsequent instructions.
739 if (MI.getOpcode() == ARM::t2IT) {
741 unsigned Firstcond = MI.getOperand(0).getImm();
742 unsigned Mask = MI.getOperand(1).getImm();
743 ITBlock.setITState(Firstcond, Mask);
749 // We want to read exactly 4 bytes of data.
750 if (Region.readBytes(Address, 4, bytes) == -1) {
752 return MCDisassembler::Fail;
755 uint32_t insn32 = (bytes[3] << 8) |
760 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
762 if (result != MCDisassembler::Fail) {
764 bool InITBlock = ITBlock.instrInITBlock();
765 Check(result, AddThumbPredicate(MI));
766 AddThumb1SBit(MI, InITBlock);
771 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
773 if (result != MCDisassembler::Fail) {
775 Check(result, AddThumbPredicate(MI));
779 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
781 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
782 if (result != MCDisassembler::Fail) {
784 UpdateThumbVFPPredicate(MI);
790 result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
791 if (result != MCDisassembler::Fail) {
796 if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
798 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
800 if (result != MCDisassembler::Fail) {
802 Check(result, AddThumbPredicate(MI));
807 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
809 uint32_t NEONLdStInsn = insn32;
810 NEONLdStInsn &= 0xF0FFFFFF;
811 NEONLdStInsn |= 0x04000000;
812 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
814 if (result != MCDisassembler::Fail) {
816 Check(result, AddThumbPredicate(MI));
821 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
823 uint32_t NEONDataInsn = insn32;
824 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
825 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
826 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
827 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
829 if (result != MCDisassembler::Fail) {
831 Check(result, AddThumbPredicate(MI));
836 uint32_t NEONCryptoInsn = insn32;
837 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
838 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
839 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25
840 result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
842 if (result != MCDisassembler::Fail) {
848 uint32_t NEONv8Insn = insn32;
849 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
850 result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
852 if (result != MCDisassembler::Fail) {
860 return MCDisassembler::Fail;
864 extern "C" void LLVMInitializeARMDisassembler() {
865 TargetRegistry::RegisterMCDisassembler(TheARMLETarget,
866 createARMDisassembler);
867 TargetRegistry::RegisterMCDisassembler(TheARMBETarget,
868 createARMDisassembler);
869 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget,
870 createThumbDisassembler);
871 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget,
872 createThumbDisassembler);
875 static const uint16_t GPRDecoderTable[] = {
876 ARM::R0, ARM::R1, ARM::R2, ARM::R3,
877 ARM::R4, ARM::R5, ARM::R6, ARM::R7,
878 ARM::R8, ARM::R9, ARM::R10, ARM::R11,
879 ARM::R12, ARM::SP, ARM::LR, ARM::PC
882 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
883 uint64_t Address, const void *Decoder) {
885 return MCDisassembler::Fail;
887 unsigned Register = GPRDecoderTable[RegNo];
888 Inst.addOperand(MCOperand::CreateReg(Register));
889 return MCDisassembler::Success;
893 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
894 uint64_t Address, const void *Decoder) {
895 DecodeStatus S = MCDisassembler::Success;
898 S = MCDisassembler::SoftFail;
900 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
906 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
907 uint64_t Address, const void *Decoder) {
908 DecodeStatus S = MCDisassembler::Success;
912 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
913 return MCDisassembler::Success;
916 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
920 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
921 uint64_t Address, const void *Decoder) {
923 return MCDisassembler::Fail;
924 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
927 static const uint16_t GPRPairDecoderTable[] = {
928 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
929 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
932 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
933 uint64_t Address, const void *Decoder) {
934 DecodeStatus S = MCDisassembler::Success;
937 return MCDisassembler::Fail;
939 if ((RegNo & 1) || RegNo == 0xe)
940 S = MCDisassembler::SoftFail;
942 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
943 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
947 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
948 uint64_t Address, const void *Decoder) {
949 unsigned Register = 0;
970 return MCDisassembler::Fail;
973 Inst.addOperand(MCOperand::CreateReg(Register));
974 return MCDisassembler::Success;
977 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
978 uint64_t Address, const void *Decoder) {
979 DecodeStatus S = MCDisassembler::Success;
980 if (RegNo == 13 || RegNo == 15)
981 S = MCDisassembler::SoftFail;
982 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
986 static const uint16_t SPRDecoderTable[] = {
987 ARM::S0, ARM::S1, ARM::S2, ARM::S3,
988 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
989 ARM::S8, ARM::S9, ARM::S10, ARM::S11,
990 ARM::S12, ARM::S13, ARM::S14, ARM::S15,
991 ARM::S16, ARM::S17, ARM::S18, ARM::S19,
992 ARM::S20, ARM::S21, ARM::S22, ARM::S23,
993 ARM::S24, ARM::S25, ARM::S26, ARM::S27,
994 ARM::S28, ARM::S29, ARM::S30, ARM::S31
997 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
998 uint64_t Address, const void *Decoder) {
1000 return MCDisassembler::Fail;
1002 unsigned Register = SPRDecoderTable[RegNo];
1003 Inst.addOperand(MCOperand::CreateReg(Register));
1004 return MCDisassembler::Success;
1007 static const uint16_t DPRDecoderTable[] = {
1008 ARM::D0, ARM::D1, ARM::D2, ARM::D3,
1009 ARM::D4, ARM::D5, ARM::D6, ARM::D7,
1010 ARM::D8, ARM::D9, ARM::D10, ARM::D11,
1011 ARM::D12, ARM::D13, ARM::D14, ARM::D15,
1012 ARM::D16, ARM::D17, ARM::D18, ARM::D19,
1013 ARM::D20, ARM::D21, ARM::D22, ARM::D23,
1014 ARM::D24, ARM::D25, ARM::D26, ARM::D27,
1015 ARM::D28, ARM::D29, ARM::D30, ARM::D31
1018 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1019 uint64_t Address, const void *Decoder) {
1021 return MCDisassembler::Fail;
1023 unsigned Register = DPRDecoderTable[RegNo];
1024 Inst.addOperand(MCOperand::CreateReg(Register));
1025 return MCDisassembler::Success;
1028 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1029 uint64_t Address, const void *Decoder) {
1031 return MCDisassembler::Fail;
1032 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1036 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1037 uint64_t Address, const void *Decoder) {
1039 return MCDisassembler::Fail;
1040 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1043 static const uint16_t QPRDecoderTable[] = {
1044 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
1045 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
1046 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
1047 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
1051 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1052 uint64_t Address, const void *Decoder) {
1053 if (RegNo > 31 || (RegNo & 1) != 0)
1054 return MCDisassembler::Fail;
1057 unsigned Register = QPRDecoderTable[RegNo];
1058 Inst.addOperand(MCOperand::CreateReg(Register));
1059 return MCDisassembler::Success;
1062 static const uint16_t DPairDecoderTable[] = {
1063 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
1064 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
1065 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
1066 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
1067 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
1071 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1072 uint64_t Address, const void *Decoder) {
1074 return MCDisassembler::Fail;
1076 unsigned Register = DPairDecoderTable[RegNo];
1077 Inst.addOperand(MCOperand::CreateReg(Register));
1078 return MCDisassembler::Success;
1081 static const uint16_t DPairSpacedDecoderTable[] = {
1082 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
1083 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
1084 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
1085 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
1086 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
1087 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
1088 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
1089 ARM::D28_D30, ARM::D29_D31
1092 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
1095 const void *Decoder) {
1097 return MCDisassembler::Fail;
1099 unsigned Register = DPairSpacedDecoderTable[RegNo];
1100 Inst.addOperand(MCOperand::CreateReg(Register));
1101 return MCDisassembler::Success;
1104 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1105 uint64_t Address, const void *Decoder) {
1106 if (Val == 0xF) return MCDisassembler::Fail;
1107 // AL predicate is not allowed on Thumb1 branches.
1108 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1109 return MCDisassembler::Fail;
1110 Inst.addOperand(MCOperand::CreateImm(Val));
1111 if (Val == ARMCC::AL) {
1112 Inst.addOperand(MCOperand::CreateReg(0));
1114 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1115 return MCDisassembler::Success;
1118 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1119 uint64_t Address, const void *Decoder) {
1121 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1123 Inst.addOperand(MCOperand::CreateReg(0));
1124 return MCDisassembler::Success;
1127 static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
1128 uint64_t Address, const void *Decoder) {
1129 uint32_t imm = Val & 0xFF;
1130 uint32_t rot = (Val & 0xF00) >> 7;
1131 uint32_t rot_imm = (imm >> rot) | (imm << ((32-rot) & 0x1F));
1132 Inst.addOperand(MCOperand::CreateImm(rot_imm));
1133 return MCDisassembler::Success;
1136 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1137 uint64_t Address, const void *Decoder) {
1138 DecodeStatus S = MCDisassembler::Success;
1140 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1141 unsigned type = fieldFromInstruction(Val, 5, 2);
1142 unsigned imm = fieldFromInstruction(Val, 7, 5);
1144 // Register-immediate
1145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1146 return MCDisassembler::Fail;
1148 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1151 Shift = ARM_AM::lsl;
1154 Shift = ARM_AM::lsr;
1157 Shift = ARM_AM::asr;
1160 Shift = ARM_AM::ror;
1164 if (Shift == ARM_AM::ror && imm == 0)
1165 Shift = ARM_AM::rrx;
1167 unsigned Op = Shift | (imm << 3);
1168 Inst.addOperand(MCOperand::CreateImm(Op));
1173 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1174 uint64_t Address, const void *Decoder) {
1175 DecodeStatus S = MCDisassembler::Success;
1177 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1178 unsigned type = fieldFromInstruction(Val, 5, 2);
1179 unsigned Rs = fieldFromInstruction(Val, 8, 4);
1181 // Register-register
1182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1183 return MCDisassembler::Fail;
1184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1185 return MCDisassembler::Fail;
1187 ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
1190 Shift = ARM_AM::lsl;
1193 Shift = ARM_AM::lsr;
1196 Shift = ARM_AM::asr;
1199 Shift = ARM_AM::ror;
1203 Inst.addOperand(MCOperand::CreateImm(Shift));
1208 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1209 uint64_t Address, const void *Decoder) {
1210 DecodeStatus S = MCDisassembler::Success;
1212 bool NeedDisjointWriteback = false;
1213 unsigned WritebackReg = 0;
1214 switch (Inst.getOpcode()) {
1217 case ARM::LDMIA_UPD:
1218 case ARM::LDMDB_UPD:
1219 case ARM::LDMIB_UPD:
1220 case ARM::LDMDA_UPD:
1221 case ARM::t2LDMIA_UPD:
1222 case ARM::t2LDMDB_UPD:
1223 case ARM::t2STMIA_UPD:
1224 case ARM::t2STMDB_UPD:
1225 NeedDisjointWriteback = true;
1226 WritebackReg = Inst.getOperand(0).getReg();
1230 // Empty register lists are not allowed.
1231 if (Val == 0) return MCDisassembler::Fail;
1232 for (unsigned i = 0; i < 16; ++i) {
1233 if (Val & (1 << i)) {
1234 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1235 return MCDisassembler::Fail;
1236 // Writeback not allowed if Rn is in the target list.
1237 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1238 Check(S, MCDisassembler::SoftFail);
1245 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1246 uint64_t Address, const void *Decoder) {
1247 DecodeStatus S = MCDisassembler::Success;
1249 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1250 unsigned regs = fieldFromInstruction(Val, 0, 8);
1252 // In case of unpredictable encoding, tweak the operands.
1253 if (regs == 0 || (Vd + regs) > 32) {
1254 regs = Vd + regs > 32 ? 32 - Vd : regs;
1255 regs = std::max( 1u, regs);
1256 S = MCDisassembler::SoftFail;
1259 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1260 return MCDisassembler::Fail;
1261 for (unsigned i = 0; i < (regs - 1); ++i) {
1262 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1263 return MCDisassembler::Fail;
1269 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1270 uint64_t Address, const void *Decoder) {
1271 DecodeStatus S = MCDisassembler::Success;
1273 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1274 unsigned regs = fieldFromInstruction(Val, 1, 7);
1276 // In case of unpredictable encoding, tweak the operands.
1277 if (regs == 0 || regs > 16 || (Vd + regs) > 32) {
1278 regs = Vd + regs > 32 ? 32 - Vd : regs;
1279 regs = std::max( 1u, regs);
1280 regs = std::min(16u, regs);
1281 S = MCDisassembler::SoftFail;
1284 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1285 return MCDisassembler::Fail;
1286 for (unsigned i = 0; i < (regs - 1); ++i) {
1287 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1288 return MCDisassembler::Fail;
1294 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1295 uint64_t Address, const void *Decoder) {
1296 // This operand encodes a mask of contiguous zeros between a specified MSB
1297 // and LSB. To decode it, we create the mask of all bits MSB-and-lower,
1298 // the mask of all bits LSB-and-lower, and then xor them to create
1299 // the mask of that's all ones on [msb, lsb]. Finally we not it to
1300 // create the final mask.
1301 unsigned msb = fieldFromInstruction(Val, 5, 5);
1302 unsigned lsb = fieldFromInstruction(Val, 0, 5);
1304 DecodeStatus S = MCDisassembler::Success;
1306 Check(S, MCDisassembler::SoftFail);
1307 // The check above will cause the warning for the "potentially undefined
1308 // instruction encoding" but we can't build a bad MCOperand value here
1309 // with a lsb > msb or else printing the MCInst will cause a crash.
1313 uint32_t msb_mask = 0xFFFFFFFF;
1314 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
1315 uint32_t lsb_mask = (1U << lsb) - 1;
1317 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1321 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1322 uint64_t Address, const void *Decoder) {
1323 DecodeStatus S = MCDisassembler::Success;
1325 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1326 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1327 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1328 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1329 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1330 unsigned U = fieldFromInstruction(Insn, 23, 1);
1332 switch (Inst.getOpcode()) {
1333 case ARM::LDC_OFFSET:
1336 case ARM::LDC_OPTION:
1337 case ARM::LDCL_OFFSET:
1339 case ARM::LDCL_POST:
1340 case ARM::LDCL_OPTION:
1341 case ARM::STC_OFFSET:
1344 case ARM::STC_OPTION:
1345 case ARM::STCL_OFFSET:
1347 case ARM::STCL_POST:
1348 case ARM::STCL_OPTION:
1349 case ARM::t2LDC_OFFSET:
1350 case ARM::t2LDC_PRE:
1351 case ARM::t2LDC_POST:
1352 case ARM::t2LDC_OPTION:
1353 case ARM::t2LDCL_OFFSET:
1354 case ARM::t2LDCL_PRE:
1355 case ARM::t2LDCL_POST:
1356 case ARM::t2LDCL_OPTION:
1357 case ARM::t2STC_OFFSET:
1358 case ARM::t2STC_PRE:
1359 case ARM::t2STC_POST:
1360 case ARM::t2STC_OPTION:
1361 case ARM::t2STCL_OFFSET:
1362 case ARM::t2STCL_PRE:
1363 case ARM::t2STCL_POST:
1364 case ARM::t2STCL_OPTION:
1365 if (coproc == 0xA || coproc == 0xB)
1366 return MCDisassembler::Fail;
1372 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1374 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1375 return MCDisassembler::Fail;
1377 Inst.addOperand(MCOperand::CreateImm(coproc));
1378 Inst.addOperand(MCOperand::CreateImm(CRd));
1379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1380 return MCDisassembler::Fail;
1382 switch (Inst.getOpcode()) {
1383 case ARM::t2LDC2_OFFSET:
1384 case ARM::t2LDC2L_OFFSET:
1385 case ARM::t2LDC2_PRE:
1386 case ARM::t2LDC2L_PRE:
1387 case ARM::t2STC2_OFFSET:
1388 case ARM::t2STC2L_OFFSET:
1389 case ARM::t2STC2_PRE:
1390 case ARM::t2STC2L_PRE:
1391 case ARM::LDC2_OFFSET:
1392 case ARM::LDC2L_OFFSET:
1394 case ARM::LDC2L_PRE:
1395 case ARM::STC2_OFFSET:
1396 case ARM::STC2L_OFFSET:
1398 case ARM::STC2L_PRE:
1399 case ARM::t2LDC_OFFSET:
1400 case ARM::t2LDCL_OFFSET:
1401 case ARM::t2LDC_PRE:
1402 case ARM::t2LDCL_PRE:
1403 case ARM::t2STC_OFFSET:
1404 case ARM::t2STCL_OFFSET:
1405 case ARM::t2STC_PRE:
1406 case ARM::t2STCL_PRE:
1407 case ARM::LDC_OFFSET:
1408 case ARM::LDCL_OFFSET:
1411 case ARM::STC_OFFSET:
1412 case ARM::STCL_OFFSET:
1415 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1416 Inst.addOperand(MCOperand::CreateImm(imm));
1418 case ARM::t2LDC2_POST:
1419 case ARM::t2LDC2L_POST:
1420 case ARM::t2STC2_POST:
1421 case ARM::t2STC2L_POST:
1422 case ARM::LDC2_POST:
1423 case ARM::LDC2L_POST:
1424 case ARM::STC2_POST:
1425 case ARM::STC2L_POST:
1426 case ARM::t2LDC_POST:
1427 case ARM::t2LDCL_POST:
1428 case ARM::t2STC_POST:
1429 case ARM::t2STCL_POST:
1431 case ARM::LDCL_POST:
1433 case ARM::STCL_POST:
1437 // The 'option' variant doesn't encode 'U' in the immediate since
1438 // the immediate is unsigned [0,255].
1439 Inst.addOperand(MCOperand::CreateImm(imm));
1443 switch (Inst.getOpcode()) {
1444 case ARM::LDC_OFFSET:
1447 case ARM::LDC_OPTION:
1448 case ARM::LDCL_OFFSET:
1450 case ARM::LDCL_POST:
1451 case ARM::LDCL_OPTION:
1452 case ARM::STC_OFFSET:
1455 case ARM::STC_OPTION:
1456 case ARM::STCL_OFFSET:
1458 case ARM::STCL_POST:
1459 case ARM::STCL_OPTION:
1460 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1461 return MCDisassembler::Fail;
1471 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
1472 uint64_t Address, const void *Decoder) {
1473 DecodeStatus S = MCDisassembler::Success;
1475 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1476 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1477 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1478 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1479 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1480 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1481 unsigned P = fieldFromInstruction(Insn, 24, 1);
1482 unsigned W = fieldFromInstruction(Insn, 21, 1);
1484 // On stores, the writeback operand precedes Rt.
1485 switch (Inst.getOpcode()) {
1486 case ARM::STR_POST_IMM:
1487 case ARM::STR_POST_REG:
1488 case ARM::STRB_POST_IMM:
1489 case ARM::STRB_POST_REG:
1490 case ARM::STRT_POST_REG:
1491 case ARM::STRT_POST_IMM:
1492 case ARM::STRBT_POST_REG:
1493 case ARM::STRBT_POST_IMM:
1494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1495 return MCDisassembler::Fail;
1501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1502 return MCDisassembler::Fail;
1504 // On loads, the writeback operand comes after Rt.
1505 switch (Inst.getOpcode()) {
1506 case ARM::LDR_POST_IMM:
1507 case ARM::LDR_POST_REG:
1508 case ARM::LDRB_POST_IMM:
1509 case ARM::LDRB_POST_REG:
1510 case ARM::LDRBT_POST_REG:
1511 case ARM::LDRBT_POST_IMM:
1512 case ARM::LDRT_POST_REG:
1513 case ARM::LDRT_POST_IMM:
1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1515 return MCDisassembler::Fail;
1521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1522 return MCDisassembler::Fail;
1524 ARM_AM::AddrOpc Op = ARM_AM::add;
1525 if (!fieldFromInstruction(Insn, 23, 1))
1528 bool writeback = (P == 0) || (W == 1);
1529 unsigned idx_mode = 0;
1531 idx_mode = ARMII::IndexModePre;
1532 else if (!P && writeback)
1533 idx_mode = ARMII::IndexModePost;
1535 if (writeback && (Rn == 15 || Rn == Rt))
1536 S = MCDisassembler::SoftFail; // UNPREDICTABLE
1539 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1540 return MCDisassembler::Fail;
1541 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1542 switch( fieldFromInstruction(Insn, 5, 2)) {
1556 return MCDisassembler::Fail;
1558 unsigned amt = fieldFromInstruction(Insn, 7, 5);
1559 if (Opc == ARM_AM::ror && amt == 0)
1561 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
1563 Inst.addOperand(MCOperand::CreateImm(imm));
1565 Inst.addOperand(MCOperand::CreateReg(0));
1566 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1567 Inst.addOperand(MCOperand::CreateImm(tmp));
1570 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1571 return MCDisassembler::Fail;
1576 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
1577 uint64_t Address, const void *Decoder) {
1578 DecodeStatus S = MCDisassembler::Success;
1580 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1581 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1582 unsigned type = fieldFromInstruction(Val, 5, 2);
1583 unsigned imm = fieldFromInstruction(Val, 7, 5);
1584 unsigned U = fieldFromInstruction(Val, 12, 1);
1586 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
1602 if (ShOp == ARM_AM::ror && imm == 0)
1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1606 return MCDisassembler::Fail;
1607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1608 return MCDisassembler::Fail;
1611 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
1613 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1614 Inst.addOperand(MCOperand::CreateImm(shift));
1620 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
1621 uint64_t Address, const void *Decoder) {
1622 DecodeStatus S = MCDisassembler::Success;
1624 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1625 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1626 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1627 unsigned type = fieldFromInstruction(Insn, 22, 1);
1628 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1629 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1630 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1631 unsigned W = fieldFromInstruction(Insn, 21, 1);
1632 unsigned P = fieldFromInstruction(Insn, 24, 1);
1633 unsigned Rt2 = Rt + 1;
1635 bool writeback = (W == 1) | (P == 0);
1637 // For {LD,ST}RD, Rt must be even, else undefined.
1638 switch (Inst.getOpcode()) {
1641 case ARM::STRD_POST:
1644 case ARM::LDRD_POST:
1645 if (Rt & 0x1) S = MCDisassembler::SoftFail;
1650 switch (Inst.getOpcode()) {
1653 case ARM::STRD_POST:
1654 if (P == 0 && W == 1)
1655 S = MCDisassembler::SoftFail;
1657 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2))
1658 S = MCDisassembler::SoftFail;
1659 if (type && Rm == 15)
1660 S = MCDisassembler::SoftFail;
1662 S = MCDisassembler::SoftFail;
1663 if (!type && fieldFromInstruction(Insn, 8, 4))
1664 S = MCDisassembler::SoftFail;
1668 case ARM::STRH_POST:
1670 S = MCDisassembler::SoftFail;
1671 if (writeback && (Rn == 15 || Rn == Rt))
1672 S = MCDisassembler::SoftFail;
1673 if (!type && Rm == 15)
1674 S = MCDisassembler::SoftFail;
1678 case ARM::LDRD_POST:
1679 if (type && Rn == 15){
1681 S = MCDisassembler::SoftFail;
1684 if (P == 0 && W == 1)
1685 S = MCDisassembler::SoftFail;
1686 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2))
1687 S = MCDisassembler::SoftFail;
1688 if (!type && writeback && Rn == 15)
1689 S = MCDisassembler::SoftFail;
1690 if (writeback && (Rn == Rt || Rn == Rt2))
1691 S = MCDisassembler::SoftFail;
1695 case ARM::LDRH_POST:
1696 if (type && Rn == 15){
1698 S = MCDisassembler::SoftFail;
1702 S = MCDisassembler::SoftFail;
1703 if (!type && Rm == 15)
1704 S = MCDisassembler::SoftFail;
1705 if (!type && writeback && (Rn == 15 || Rn == Rt))
1706 S = MCDisassembler::SoftFail;
1709 case ARM::LDRSH_PRE:
1710 case ARM::LDRSH_POST:
1712 case ARM::LDRSB_PRE:
1713 case ARM::LDRSB_POST:
1714 if (type && Rn == 15){
1716 S = MCDisassembler::SoftFail;
1719 if (type && (Rt == 15 || (writeback && Rn == Rt)))
1720 S = MCDisassembler::SoftFail;
1721 if (!type && (Rt == 15 || Rm == 15))
1722 S = MCDisassembler::SoftFail;
1723 if (!type && writeback && (Rn == 15 || Rn == Rt))
1724 S = MCDisassembler::SoftFail;
1730 if (writeback) { // Writeback
1732 U |= ARMII::IndexModePre << 9;
1734 U |= ARMII::IndexModePost << 9;
1736 // On stores, the writeback operand precedes Rt.
1737 switch (Inst.getOpcode()) {
1740 case ARM::STRD_POST:
1743 case ARM::STRH_POST:
1744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1745 return MCDisassembler::Fail;
1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
1753 return MCDisassembler::Fail;
1754 switch (Inst.getOpcode()) {
1757 case ARM::STRD_POST:
1760 case ARM::LDRD_POST:
1761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
1762 return MCDisassembler::Fail;
1769 // On loads, the writeback operand comes after Rt.
1770 switch (Inst.getOpcode()) {
1773 case ARM::LDRD_POST:
1776 case ARM::LDRH_POST:
1778 case ARM::LDRSH_PRE:
1779 case ARM::LDRSH_POST:
1781 case ARM::LDRSB_PRE:
1782 case ARM::LDRSB_POST:
1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1786 return MCDisassembler::Fail;
1793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1794 return MCDisassembler::Fail;
1797 Inst.addOperand(MCOperand::CreateReg(0));
1798 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
1801 return MCDisassembler::Fail;
1802 Inst.addOperand(MCOperand::CreateImm(U));
1805 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1806 return MCDisassembler::Fail;
1811 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
1812 uint64_t Address, const void *Decoder) {
1813 DecodeStatus S = MCDisassembler::Success;
1815 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1816 unsigned mode = fieldFromInstruction(Insn, 23, 2);
1833 Inst.addOperand(MCOperand::CreateImm(mode));
1834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1835 return MCDisassembler::Fail;
1840 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
1841 uint64_t Address, const void *Decoder) {
1842 DecodeStatus S = MCDisassembler::Success;
1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1845 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1846 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1847 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1850 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
1853 return MCDisassembler::Fail;
1854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1855 return MCDisassembler::Fail;
1856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
1857 return MCDisassembler::Fail;
1858 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1859 return MCDisassembler::Fail;
1863 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
1865 uint64_t Address, const void *Decoder) {
1866 DecodeStatus S = MCDisassembler::Success;
1868 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1869 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1870 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
1873 // Ambiguous with RFE and SRS
1874 switch (Inst.getOpcode()) {
1876 Inst.setOpcode(ARM::RFEDA);
1878 case ARM::LDMDA_UPD:
1879 Inst.setOpcode(ARM::RFEDA_UPD);
1882 Inst.setOpcode(ARM::RFEDB);
1884 case ARM::LDMDB_UPD:
1885 Inst.setOpcode(ARM::RFEDB_UPD);
1888 Inst.setOpcode(ARM::RFEIA);
1890 case ARM::LDMIA_UPD:
1891 Inst.setOpcode(ARM::RFEIA_UPD);
1894 Inst.setOpcode(ARM::RFEIB);
1896 case ARM::LDMIB_UPD:
1897 Inst.setOpcode(ARM::RFEIB_UPD);
1900 Inst.setOpcode(ARM::SRSDA);
1902 case ARM::STMDA_UPD:
1903 Inst.setOpcode(ARM::SRSDA_UPD);
1906 Inst.setOpcode(ARM::SRSDB);
1908 case ARM::STMDB_UPD:
1909 Inst.setOpcode(ARM::SRSDB_UPD);
1912 Inst.setOpcode(ARM::SRSIA);
1914 case ARM::STMIA_UPD:
1915 Inst.setOpcode(ARM::SRSIA_UPD);
1918 Inst.setOpcode(ARM::SRSIB);
1920 case ARM::STMIB_UPD:
1921 Inst.setOpcode(ARM::SRSIB_UPD);
1924 return MCDisassembler::Fail;
1927 // For stores (which become SRS's, the only operand is the mode.
1928 if (fieldFromInstruction(Insn, 20, 1) == 0) {
1929 // Check SRS encoding constraints
1930 if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
1931 fieldFromInstruction(Insn, 20, 1) == 0))
1932 return MCDisassembler::Fail;
1935 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1939 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
1942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1943 return MCDisassembler::Fail;
1944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1945 return MCDisassembler::Fail; // Tied
1946 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
1947 return MCDisassembler::Fail;
1948 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
1949 return MCDisassembler::Fail;
1954 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
1955 uint64_t Address, const void *Decoder) {
1956 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1957 unsigned M = fieldFromInstruction(Insn, 17, 1);
1958 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1959 unsigned mode = fieldFromInstruction(Insn, 0, 5);
1961 DecodeStatus S = MCDisassembler::Success;
1963 // This decoder is called from multiple location that do not check
1964 // the full encoding is valid before they do.
1965 if (fieldFromInstruction(Insn, 5, 1) != 0 ||
1966 fieldFromInstruction(Insn, 16, 1) != 0 ||
1967 fieldFromInstruction(Insn, 20, 8) != 0x10)
1968 return MCDisassembler::Fail;
1970 // imod == '01' --> UNPREDICTABLE
1971 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
1972 // return failure here. The '01' imod value is unprintable, so there's
1973 // nothing useful we could do even if we returned UNPREDICTABLE.
1975 if (imod == 1) return MCDisassembler::Fail;
1978 Inst.setOpcode(ARM::CPS3p);
1979 Inst.addOperand(MCOperand::CreateImm(imod));
1980 Inst.addOperand(MCOperand::CreateImm(iflags));
1981 Inst.addOperand(MCOperand::CreateImm(mode));
1982 } else if (imod && !M) {
1983 Inst.setOpcode(ARM::CPS2p);
1984 Inst.addOperand(MCOperand::CreateImm(imod));
1985 Inst.addOperand(MCOperand::CreateImm(iflags));
1986 if (mode) S = MCDisassembler::SoftFail;
1987 } else if (!imod && M) {
1988 Inst.setOpcode(ARM::CPS1p);
1989 Inst.addOperand(MCOperand::CreateImm(mode));
1990 if (iflags) S = MCDisassembler::SoftFail;
1992 // imod == '00' && M == '0' --> UNPREDICTABLE
1993 Inst.setOpcode(ARM::CPS1p);
1994 Inst.addOperand(MCOperand::CreateImm(mode));
1995 S = MCDisassembler::SoftFail;
2001 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2002 uint64_t Address, const void *Decoder) {
2003 unsigned imod = fieldFromInstruction(Insn, 9, 2);
2004 unsigned M = fieldFromInstruction(Insn, 8, 1);
2005 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
2006 unsigned mode = fieldFromInstruction(Insn, 0, 5);
2008 DecodeStatus S = MCDisassembler::Success;
2010 // imod == '01' --> UNPREDICTABLE
2011 // NOTE: Even though this is technically UNPREDICTABLE, we choose to
2012 // return failure here. The '01' imod value is unprintable, so there's
2013 // nothing useful we could do even if we returned UNPREDICTABLE.
2015 if (imod == 1) return MCDisassembler::Fail;
2018 Inst.setOpcode(ARM::t2CPS3p);
2019 Inst.addOperand(MCOperand::CreateImm(imod));
2020 Inst.addOperand(MCOperand::CreateImm(iflags));
2021 Inst.addOperand(MCOperand::CreateImm(mode));
2022 } else if (imod && !M) {
2023 Inst.setOpcode(ARM::t2CPS2p);
2024 Inst.addOperand(MCOperand::CreateImm(imod));
2025 Inst.addOperand(MCOperand::CreateImm(iflags));
2026 if (mode) S = MCDisassembler::SoftFail;
2027 } else if (!imod && M) {
2028 Inst.setOpcode(ARM::t2CPS1p);
2029 Inst.addOperand(MCOperand::CreateImm(mode));
2030 if (iflags) S = MCDisassembler::SoftFail;
2032 // imod == '00' && M == '0' --> this is a HINT instruction
2033 int imm = fieldFromInstruction(Insn, 0, 8);
2034 // HINT are defined only for immediate in [0..4]
2035 if(imm > 4) return MCDisassembler::Fail;
2036 Inst.setOpcode(ARM::t2HINT);
2037 Inst.addOperand(MCOperand::CreateImm(imm));
2043 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2044 uint64_t Address, const void *Decoder) {
2045 DecodeStatus S = MCDisassembler::Success;
2047 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
2050 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
2051 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
2052 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2053 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
2055 if (Inst.getOpcode() == ARM::t2MOVTi16)
2056 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2057 return MCDisassembler::Fail;
2058 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2059 return MCDisassembler::Fail;
2061 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2062 Inst.addOperand(MCOperand::CreateImm(imm));
2067 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2068 uint64_t Address, const void *Decoder) {
2069 DecodeStatus S = MCDisassembler::Success;
2071 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2072 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2075 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2076 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
2078 if (Inst.getOpcode() == ARM::MOVTi16)
2079 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2080 return MCDisassembler::Fail;
2082 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2083 return MCDisassembler::Fail;
2085 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2086 Inst.addOperand(MCOperand::CreateImm(imm));
2088 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2089 return MCDisassembler::Fail;
2094 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2095 uint64_t Address, const void *Decoder) {
2096 DecodeStatus S = MCDisassembler::Success;
2098 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2099 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2100 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2101 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2102 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2105 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2107 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2108 return MCDisassembler::Fail;
2109 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2110 return MCDisassembler::Fail;
2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2112 return MCDisassembler::Fail;
2113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2114 return MCDisassembler::Fail;
2116 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2117 return MCDisassembler::Fail;
2122 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2123 uint64_t Address, const void *Decoder) {
2124 DecodeStatus S = MCDisassembler::Success;
2126 unsigned add = fieldFromInstruction(Val, 12, 1);
2127 unsigned imm = fieldFromInstruction(Val, 0, 12);
2128 unsigned Rn = fieldFromInstruction(Val, 13, 4);
2130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2131 return MCDisassembler::Fail;
2133 if (!add) imm *= -1;
2134 if (imm == 0 && !add) imm = INT32_MIN;
2135 Inst.addOperand(MCOperand::CreateImm(imm));
2137 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
2142 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2143 uint64_t Address, const void *Decoder) {
2144 DecodeStatus S = MCDisassembler::Success;
2146 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2147 unsigned U = fieldFromInstruction(Val, 8, 1);
2148 unsigned imm = fieldFromInstruction(Val, 0, 8);
2150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2151 return MCDisassembler::Fail;
2154 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2156 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2161 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2162 uint64_t Address, const void *Decoder) {
2163 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2167 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2168 uint64_t Address, const void *Decoder) {
2169 DecodeStatus Status = MCDisassembler::Success;
2171 // Note the J1 and J2 values are from the encoded instruction. So here
2172 // change them to I1 and I2 values via as documented:
2173 // I1 = NOT(J1 EOR S);
2174 // I2 = NOT(J2 EOR S);
2175 // and build the imm32 with one trailing zero as documented:
2176 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
2177 unsigned S = fieldFromInstruction(Insn, 26, 1);
2178 unsigned J1 = fieldFromInstruction(Insn, 13, 1);
2179 unsigned J2 = fieldFromInstruction(Insn, 11, 1);
2180 unsigned I1 = !(J1 ^ S);
2181 unsigned I2 = !(J2 ^ S);
2182 unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
2183 unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
2184 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11;
2185 int imm32 = SignExtend32<25>(tmp << 1);
2186 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
2187 true, 4, Inst, Decoder))
2188 Inst.addOperand(MCOperand::CreateImm(imm32));
2194 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2195 uint64_t Address, const void *Decoder) {
2196 DecodeStatus S = MCDisassembler::Success;
2198 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2199 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
2202 Inst.setOpcode(ARM::BLXi);
2203 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
2204 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2205 true, 4, Inst, Decoder))
2206 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2210 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
2211 true, 4, Inst, Decoder))
2212 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
2213 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2214 return MCDisassembler::Fail;
2220 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2221 uint64_t Address, const void *Decoder) {
2222 DecodeStatus S = MCDisassembler::Success;
2224 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2225 unsigned align = fieldFromInstruction(Val, 4, 2);
2227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2228 return MCDisassembler::Fail;
2230 Inst.addOperand(MCOperand::CreateImm(0));
2232 Inst.addOperand(MCOperand::CreateImm(4 << align));
2237 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2238 uint64_t Address, const void *Decoder) {
2239 DecodeStatus S = MCDisassembler::Success;
2241 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2242 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2243 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2244 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2245 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2246 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2248 // First output register
2249 switch (Inst.getOpcode()) {
2250 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
2251 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
2252 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
2253 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
2254 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
2255 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
2256 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
2257 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
2258 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
2259 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2260 return MCDisassembler::Fail;
2265 case ARM::VLD2b16wb_fixed:
2266 case ARM::VLD2b16wb_register:
2267 case ARM::VLD2b32wb_fixed:
2268 case ARM::VLD2b32wb_register:
2269 case ARM::VLD2b8wb_fixed:
2270 case ARM::VLD2b8wb_register:
2271 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2272 return MCDisassembler::Fail;
2275 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2276 return MCDisassembler::Fail;
2279 // Second output register
2280 switch (Inst.getOpcode()) {
2284 case ARM::VLD3d8_UPD:
2285 case ARM::VLD3d16_UPD:
2286 case ARM::VLD3d32_UPD:
2290 case ARM::VLD4d8_UPD:
2291 case ARM::VLD4d16_UPD:
2292 case ARM::VLD4d32_UPD:
2293 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2294 return MCDisassembler::Fail;
2299 case ARM::VLD3q8_UPD:
2300 case ARM::VLD3q16_UPD:
2301 case ARM::VLD3q32_UPD:
2305 case ARM::VLD4q8_UPD:
2306 case ARM::VLD4q16_UPD:
2307 case ARM::VLD4q32_UPD:
2308 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2309 return MCDisassembler::Fail;
2314 // Third output register
2315 switch(Inst.getOpcode()) {
2319 case ARM::VLD3d8_UPD:
2320 case ARM::VLD3d16_UPD:
2321 case ARM::VLD3d32_UPD:
2325 case ARM::VLD4d8_UPD:
2326 case ARM::VLD4d16_UPD:
2327 case ARM::VLD4d32_UPD:
2328 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2329 return MCDisassembler::Fail;
2334 case ARM::VLD3q8_UPD:
2335 case ARM::VLD3q16_UPD:
2336 case ARM::VLD3q32_UPD:
2340 case ARM::VLD4q8_UPD:
2341 case ARM::VLD4q16_UPD:
2342 case ARM::VLD4q32_UPD:
2343 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2344 return MCDisassembler::Fail;
2350 // Fourth output register
2351 switch (Inst.getOpcode()) {
2355 case ARM::VLD4d8_UPD:
2356 case ARM::VLD4d16_UPD:
2357 case ARM::VLD4d32_UPD:
2358 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2359 return MCDisassembler::Fail;
2364 case ARM::VLD4q8_UPD:
2365 case ARM::VLD4q16_UPD:
2366 case ARM::VLD4q32_UPD:
2367 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2368 return MCDisassembler::Fail;
2374 // Writeback operand
2375 switch (Inst.getOpcode()) {
2376 case ARM::VLD1d8wb_fixed:
2377 case ARM::VLD1d16wb_fixed:
2378 case ARM::VLD1d32wb_fixed:
2379 case ARM::VLD1d64wb_fixed:
2380 case ARM::VLD1d8wb_register:
2381 case ARM::VLD1d16wb_register:
2382 case ARM::VLD1d32wb_register:
2383 case ARM::VLD1d64wb_register:
2384 case ARM::VLD1q8wb_fixed:
2385 case ARM::VLD1q16wb_fixed:
2386 case ARM::VLD1q32wb_fixed:
2387 case ARM::VLD1q64wb_fixed:
2388 case ARM::VLD1q8wb_register:
2389 case ARM::VLD1q16wb_register:
2390 case ARM::VLD1q32wb_register:
2391 case ARM::VLD1q64wb_register:
2392 case ARM::VLD1d8Twb_fixed:
2393 case ARM::VLD1d8Twb_register:
2394 case ARM::VLD1d16Twb_fixed:
2395 case ARM::VLD1d16Twb_register:
2396 case ARM::VLD1d32Twb_fixed:
2397 case ARM::VLD1d32Twb_register:
2398 case ARM::VLD1d64Twb_fixed:
2399 case ARM::VLD1d64Twb_register:
2400 case ARM::VLD1d8Qwb_fixed:
2401 case ARM::VLD1d8Qwb_register:
2402 case ARM::VLD1d16Qwb_fixed:
2403 case ARM::VLD1d16Qwb_register:
2404 case ARM::VLD1d32Qwb_fixed:
2405 case ARM::VLD1d32Qwb_register:
2406 case ARM::VLD1d64Qwb_fixed:
2407 case ARM::VLD1d64Qwb_register:
2408 case ARM::VLD2d8wb_fixed:
2409 case ARM::VLD2d16wb_fixed:
2410 case ARM::VLD2d32wb_fixed:
2411 case ARM::VLD2q8wb_fixed:
2412 case ARM::VLD2q16wb_fixed:
2413 case ARM::VLD2q32wb_fixed:
2414 case ARM::VLD2d8wb_register:
2415 case ARM::VLD2d16wb_register:
2416 case ARM::VLD2d32wb_register:
2417 case ARM::VLD2q8wb_register:
2418 case ARM::VLD2q16wb_register:
2419 case ARM::VLD2q32wb_register:
2420 case ARM::VLD2b8wb_fixed:
2421 case ARM::VLD2b16wb_fixed:
2422 case ARM::VLD2b32wb_fixed:
2423 case ARM::VLD2b8wb_register:
2424 case ARM::VLD2b16wb_register:
2425 case ARM::VLD2b32wb_register:
2426 Inst.addOperand(MCOperand::CreateImm(0));
2428 case ARM::VLD3d8_UPD:
2429 case ARM::VLD3d16_UPD:
2430 case ARM::VLD3d32_UPD:
2431 case ARM::VLD3q8_UPD:
2432 case ARM::VLD3q16_UPD:
2433 case ARM::VLD3q32_UPD:
2434 case ARM::VLD4d8_UPD:
2435 case ARM::VLD4d16_UPD:
2436 case ARM::VLD4d32_UPD:
2437 case ARM::VLD4q8_UPD:
2438 case ARM::VLD4q16_UPD:
2439 case ARM::VLD4q32_UPD:
2440 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2441 return MCDisassembler::Fail;
2447 // AddrMode6 Base (register+alignment)
2448 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2449 return MCDisassembler::Fail;
2451 // AddrMode6 Offset (register)
2452 switch (Inst.getOpcode()) {
2454 // The below have been updated to have explicit am6offset split
2455 // between fixed and register offset. For those instructions not
2456 // yet updated, we need to add an additional reg0 operand for the
2459 // The fixed offset encodes as Rm == 0xd, so we check for that.
2461 Inst.addOperand(MCOperand::CreateReg(0));
2464 // Fall through to handle the register offset variant.
2465 case ARM::VLD1d8wb_fixed:
2466 case ARM::VLD1d16wb_fixed:
2467 case ARM::VLD1d32wb_fixed:
2468 case ARM::VLD1d64wb_fixed:
2469 case ARM::VLD1d8Twb_fixed:
2470 case ARM::VLD1d16Twb_fixed:
2471 case ARM::VLD1d32Twb_fixed:
2472 case ARM::VLD1d64Twb_fixed:
2473 case ARM::VLD1d8Qwb_fixed:
2474 case ARM::VLD1d16Qwb_fixed:
2475 case ARM::VLD1d32Qwb_fixed:
2476 case ARM::VLD1d64Qwb_fixed:
2477 case ARM::VLD1d8wb_register:
2478 case ARM::VLD1d16wb_register:
2479 case ARM::VLD1d32wb_register:
2480 case ARM::VLD1d64wb_register:
2481 case ARM::VLD1q8wb_fixed:
2482 case ARM::VLD1q16wb_fixed:
2483 case ARM::VLD1q32wb_fixed:
2484 case ARM::VLD1q64wb_fixed:
2485 case ARM::VLD1q8wb_register:
2486 case ARM::VLD1q16wb_register:
2487 case ARM::VLD1q32wb_register:
2488 case ARM::VLD1q64wb_register:
2489 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2490 // variant encodes Rm == 0xf. Anything else is a register offset post-
2491 // increment and we need to add the register operand to the instruction.
2492 if (Rm != 0xD && Rm != 0xF &&
2493 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2494 return MCDisassembler::Fail;
2496 case ARM::VLD2d8wb_fixed:
2497 case ARM::VLD2d16wb_fixed:
2498 case ARM::VLD2d32wb_fixed:
2499 case ARM::VLD2b8wb_fixed:
2500 case ARM::VLD2b16wb_fixed:
2501 case ARM::VLD2b32wb_fixed:
2502 case ARM::VLD2q8wb_fixed:
2503 case ARM::VLD2q16wb_fixed:
2504 case ARM::VLD2q32wb_fixed:
2511 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
2512 uint64_t Address, const void *Decoder) {
2513 unsigned type = fieldFromInstruction(Insn, 8, 4);
2514 unsigned align = fieldFromInstruction(Insn, 4, 2);
2515 if (type == 6 && (align & 2)) return MCDisassembler::Fail;
2516 if (type == 7 && (align & 2)) return MCDisassembler::Fail;
2517 if (type == 10 && align == 3) return MCDisassembler::Fail;
2519 unsigned load = fieldFromInstruction(Insn, 21, 1);
2520 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2521 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2524 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
2525 uint64_t Address, const void *Decoder) {
2526 unsigned size = fieldFromInstruction(Insn, 6, 2);
2527 if (size == 3) return MCDisassembler::Fail;
2529 unsigned type = fieldFromInstruction(Insn, 8, 4);
2530 unsigned align = fieldFromInstruction(Insn, 4, 2);
2531 if (type == 8 && align == 3) return MCDisassembler::Fail;
2532 if (type == 9 && align == 3) return MCDisassembler::Fail;
2534 unsigned load = fieldFromInstruction(Insn, 21, 1);
2535 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2536 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2539 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
2540 uint64_t Address, const void *Decoder) {
2541 unsigned size = fieldFromInstruction(Insn, 6, 2);
2542 if (size == 3) return MCDisassembler::Fail;
2544 unsigned align = fieldFromInstruction(Insn, 4, 2);
2545 if (align & 2) return MCDisassembler::Fail;
2547 unsigned load = fieldFromInstruction(Insn, 21, 1);
2548 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2549 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2552 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
2553 uint64_t Address, const void *Decoder) {
2554 unsigned size = fieldFromInstruction(Insn, 6, 2);
2555 if (size == 3) return MCDisassembler::Fail;
2557 unsigned load = fieldFromInstruction(Insn, 21, 1);
2558 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
2559 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
2562 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
2563 uint64_t Address, const void *Decoder) {
2564 DecodeStatus S = MCDisassembler::Success;
2566 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2567 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2568 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2569 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2570 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2571 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2573 // Writeback Operand
2574 switch (Inst.getOpcode()) {
2575 case ARM::VST1d8wb_fixed:
2576 case ARM::VST1d16wb_fixed:
2577 case ARM::VST1d32wb_fixed:
2578 case ARM::VST1d64wb_fixed:
2579 case ARM::VST1d8wb_register:
2580 case ARM::VST1d16wb_register:
2581 case ARM::VST1d32wb_register:
2582 case ARM::VST1d64wb_register:
2583 case ARM::VST1q8wb_fixed:
2584 case ARM::VST1q16wb_fixed:
2585 case ARM::VST1q32wb_fixed:
2586 case ARM::VST1q64wb_fixed:
2587 case ARM::VST1q8wb_register:
2588 case ARM::VST1q16wb_register:
2589 case ARM::VST1q32wb_register:
2590 case ARM::VST1q64wb_register:
2591 case ARM::VST1d8Twb_fixed:
2592 case ARM::VST1d16Twb_fixed:
2593 case ARM::VST1d32Twb_fixed:
2594 case ARM::VST1d64Twb_fixed:
2595 case ARM::VST1d8Twb_register:
2596 case ARM::VST1d16Twb_register:
2597 case ARM::VST1d32Twb_register:
2598 case ARM::VST1d64Twb_register:
2599 case ARM::VST1d8Qwb_fixed:
2600 case ARM::VST1d16Qwb_fixed:
2601 case ARM::VST1d32Qwb_fixed:
2602 case ARM::VST1d64Qwb_fixed:
2603 case ARM::VST1d8Qwb_register:
2604 case ARM::VST1d16Qwb_register:
2605 case ARM::VST1d32Qwb_register:
2606 case ARM::VST1d64Qwb_register:
2607 case ARM::VST2d8wb_fixed:
2608 case ARM::VST2d16wb_fixed:
2609 case ARM::VST2d32wb_fixed:
2610 case ARM::VST2d8wb_register:
2611 case ARM::VST2d16wb_register:
2612 case ARM::VST2d32wb_register:
2613 case ARM::VST2q8wb_fixed:
2614 case ARM::VST2q16wb_fixed:
2615 case ARM::VST2q32wb_fixed:
2616 case ARM::VST2q8wb_register:
2617 case ARM::VST2q16wb_register:
2618 case ARM::VST2q32wb_register:
2619 case ARM::VST2b8wb_fixed:
2620 case ARM::VST2b16wb_fixed:
2621 case ARM::VST2b32wb_fixed:
2622 case ARM::VST2b8wb_register:
2623 case ARM::VST2b16wb_register:
2624 case ARM::VST2b32wb_register:
2626 return MCDisassembler::Fail;
2627 Inst.addOperand(MCOperand::CreateImm(0));
2629 case ARM::VST3d8_UPD:
2630 case ARM::VST3d16_UPD:
2631 case ARM::VST3d32_UPD:
2632 case ARM::VST3q8_UPD:
2633 case ARM::VST3q16_UPD:
2634 case ARM::VST3q32_UPD:
2635 case ARM::VST4d8_UPD:
2636 case ARM::VST4d16_UPD:
2637 case ARM::VST4d32_UPD:
2638 case ARM::VST4q8_UPD:
2639 case ARM::VST4q16_UPD:
2640 case ARM::VST4q32_UPD:
2641 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
2642 return MCDisassembler::Fail;
2648 // AddrMode6 Base (register+alignment)
2649 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
2650 return MCDisassembler::Fail;
2652 // AddrMode6 Offset (register)
2653 switch (Inst.getOpcode()) {
2656 Inst.addOperand(MCOperand::CreateReg(0));
2657 else if (Rm != 0xF) {
2658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2659 return MCDisassembler::Fail;
2662 case ARM::VST1d8wb_fixed:
2663 case ARM::VST1d16wb_fixed:
2664 case ARM::VST1d32wb_fixed:
2665 case ARM::VST1d64wb_fixed:
2666 case ARM::VST1q8wb_fixed:
2667 case ARM::VST1q16wb_fixed:
2668 case ARM::VST1q32wb_fixed:
2669 case ARM::VST1q64wb_fixed:
2670 case ARM::VST1d8Twb_fixed:
2671 case ARM::VST1d16Twb_fixed:
2672 case ARM::VST1d32Twb_fixed:
2673 case ARM::VST1d64Twb_fixed:
2674 case ARM::VST1d8Qwb_fixed:
2675 case ARM::VST1d16Qwb_fixed:
2676 case ARM::VST1d32Qwb_fixed:
2677 case ARM::VST1d64Qwb_fixed:
2678 case ARM::VST2d8wb_fixed:
2679 case ARM::VST2d16wb_fixed:
2680 case ARM::VST2d32wb_fixed:
2681 case ARM::VST2q8wb_fixed:
2682 case ARM::VST2q16wb_fixed:
2683 case ARM::VST2q32wb_fixed:
2684 case ARM::VST2b8wb_fixed:
2685 case ARM::VST2b16wb_fixed:
2686 case ARM::VST2b32wb_fixed:
2691 // First input register
2692 switch (Inst.getOpcode()) {
2697 case ARM::VST1q16wb_fixed:
2698 case ARM::VST1q16wb_register:
2699 case ARM::VST1q32wb_fixed:
2700 case ARM::VST1q32wb_register:
2701 case ARM::VST1q64wb_fixed:
2702 case ARM::VST1q64wb_register:
2703 case ARM::VST1q8wb_fixed:
2704 case ARM::VST1q8wb_register:
2708 case ARM::VST2d16wb_fixed:
2709 case ARM::VST2d16wb_register:
2710 case ARM::VST2d32wb_fixed:
2711 case ARM::VST2d32wb_register:
2712 case ARM::VST2d8wb_fixed:
2713 case ARM::VST2d8wb_register:
2714 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2715 return MCDisassembler::Fail;
2720 case ARM::VST2b16wb_fixed:
2721 case ARM::VST2b16wb_register:
2722 case ARM::VST2b32wb_fixed:
2723 case ARM::VST2b32wb_register:
2724 case ARM::VST2b8wb_fixed:
2725 case ARM::VST2b8wb_register:
2726 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2727 return MCDisassembler::Fail;
2730 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2731 return MCDisassembler::Fail;
2734 // Second input register
2735 switch (Inst.getOpcode()) {
2739 case ARM::VST3d8_UPD:
2740 case ARM::VST3d16_UPD:
2741 case ARM::VST3d32_UPD:
2745 case ARM::VST4d8_UPD:
2746 case ARM::VST4d16_UPD:
2747 case ARM::VST4d32_UPD:
2748 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
2749 return MCDisassembler::Fail;
2754 case ARM::VST3q8_UPD:
2755 case ARM::VST3q16_UPD:
2756 case ARM::VST3q32_UPD:
2760 case ARM::VST4q8_UPD:
2761 case ARM::VST4q16_UPD:
2762 case ARM::VST4q32_UPD:
2763 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2764 return MCDisassembler::Fail;
2770 // Third input register
2771 switch (Inst.getOpcode()) {
2775 case ARM::VST3d8_UPD:
2776 case ARM::VST3d16_UPD:
2777 case ARM::VST3d32_UPD:
2781 case ARM::VST4d8_UPD:
2782 case ARM::VST4d16_UPD:
2783 case ARM::VST4d32_UPD:
2784 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
2785 return MCDisassembler::Fail;
2790 case ARM::VST3q8_UPD:
2791 case ARM::VST3q16_UPD:
2792 case ARM::VST3q32_UPD:
2796 case ARM::VST4q8_UPD:
2797 case ARM::VST4q16_UPD:
2798 case ARM::VST4q32_UPD:
2799 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
2800 return MCDisassembler::Fail;
2806 // Fourth input register
2807 switch (Inst.getOpcode()) {
2811 case ARM::VST4d8_UPD:
2812 case ARM::VST4d16_UPD:
2813 case ARM::VST4d32_UPD:
2814 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
2815 return MCDisassembler::Fail;
2820 case ARM::VST4q8_UPD:
2821 case ARM::VST4q16_UPD:
2822 case ARM::VST4q32_UPD:
2823 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
2824 return MCDisassembler::Fail;
2833 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
2834 uint64_t Address, const void *Decoder) {
2835 DecodeStatus S = MCDisassembler::Success;
2837 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2838 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2839 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2840 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2841 unsigned align = fieldFromInstruction(Insn, 4, 1);
2842 unsigned size = fieldFromInstruction(Insn, 6, 2);
2844 if (size == 0 && align == 1)
2845 return MCDisassembler::Fail;
2846 align *= (1 << size);
2848 switch (Inst.getOpcode()) {
2849 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
2850 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
2851 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
2852 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
2853 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2854 return MCDisassembler::Fail;
2857 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2858 return MCDisassembler::Fail;
2862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2863 return MCDisassembler::Fail;
2866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2867 return MCDisassembler::Fail;
2868 Inst.addOperand(MCOperand::CreateImm(align));
2870 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback
2871 // variant encodes Rm == 0xf. Anything else is a register offset post-
2872 // increment and we need to add the register operand to the instruction.
2873 if (Rm != 0xD && Rm != 0xF &&
2874 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2875 return MCDisassembler::Fail;
2880 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
2881 uint64_t Address, const void *Decoder) {
2882 DecodeStatus S = MCDisassembler::Success;
2884 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2885 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2886 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2887 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2888 unsigned align = fieldFromInstruction(Insn, 4, 1);
2889 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
2892 switch (Inst.getOpcode()) {
2893 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
2894 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
2895 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
2896 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
2897 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
2898 return MCDisassembler::Fail;
2900 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
2901 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
2902 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
2903 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
2904 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
2905 return MCDisassembler::Fail;
2908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2909 return MCDisassembler::Fail;
2914 Inst.addOperand(MCOperand::CreateImm(0));
2916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2917 return MCDisassembler::Fail;
2918 Inst.addOperand(MCOperand::CreateImm(align));
2920 if (Rm != 0xD && Rm != 0xF) {
2921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2922 return MCDisassembler::Fail;
2928 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
2929 uint64_t Address, const void *Decoder) {
2930 DecodeStatus S = MCDisassembler::Success;
2932 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2933 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2934 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2935 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2936 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2938 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2939 return MCDisassembler::Fail;
2940 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2941 return MCDisassembler::Fail;
2942 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2943 return MCDisassembler::Fail;
2945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2946 return MCDisassembler::Fail;
2949 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2950 return MCDisassembler::Fail;
2951 Inst.addOperand(MCOperand::CreateImm(0));
2954 Inst.addOperand(MCOperand::CreateReg(0));
2955 else if (Rm != 0xF) {
2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2957 return MCDisassembler::Fail;
2963 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
2964 uint64_t Address, const void *Decoder) {
2965 DecodeStatus S = MCDisassembler::Success;
2967 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2968 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2969 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2970 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2971 unsigned size = fieldFromInstruction(Insn, 6, 2);
2972 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2973 unsigned align = fieldFromInstruction(Insn, 4, 1);
2977 return MCDisassembler::Fail;
2990 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
2991 return MCDisassembler::Fail;
2992 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
2993 return MCDisassembler::Fail;
2994 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
2995 return MCDisassembler::Fail;
2996 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
2997 return MCDisassembler::Fail;
2999 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3000 return MCDisassembler::Fail;
3003 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3004 return MCDisassembler::Fail;
3005 Inst.addOperand(MCOperand::CreateImm(align));
3008 Inst.addOperand(MCOperand::CreateReg(0));
3009 else if (Rm != 0xF) {
3010 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3011 return MCDisassembler::Fail;
3018 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
3019 uint64_t Address, const void *Decoder) {
3020 DecodeStatus S = MCDisassembler::Success;
3022 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3023 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3024 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3025 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
3026 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
3027 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
3028 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
3029 unsigned Q = fieldFromInstruction(Insn, 6, 1);
3032 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3033 return MCDisassembler::Fail;
3035 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3036 return MCDisassembler::Fail;
3039 Inst.addOperand(MCOperand::CreateImm(imm));
3041 switch (Inst.getOpcode()) {
3042 case ARM::VORRiv4i16:
3043 case ARM::VORRiv2i32:
3044 case ARM::VBICiv4i16:
3045 case ARM::VBICiv2i32:
3046 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3047 return MCDisassembler::Fail;
3049 case ARM::VORRiv8i16:
3050 case ARM::VORRiv4i32:
3051 case ARM::VBICiv8i16:
3052 case ARM::VBICiv4i32:
3053 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3054 return MCDisassembler::Fail;
3063 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3064 uint64_t Address, const void *Decoder) {
3065 DecodeStatus S = MCDisassembler::Success;
3067 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3068 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3069 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3070 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3071 unsigned size = fieldFromInstruction(Insn, 18, 2);
3073 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3074 return MCDisassembler::Fail;
3075 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3076 return MCDisassembler::Fail;
3077 Inst.addOperand(MCOperand::CreateImm(8 << size));
3082 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3083 uint64_t Address, const void *Decoder) {
3084 Inst.addOperand(MCOperand::CreateImm(8 - Val));
3085 return MCDisassembler::Success;
3088 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3089 uint64_t Address, const void *Decoder) {
3090 Inst.addOperand(MCOperand::CreateImm(16 - Val));
3091 return MCDisassembler::Success;
3094 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3095 uint64_t Address, const void *Decoder) {
3096 Inst.addOperand(MCOperand::CreateImm(32 - Val));
3097 return MCDisassembler::Success;
3100 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3101 uint64_t Address, const void *Decoder) {
3102 Inst.addOperand(MCOperand::CreateImm(64 - Val));
3103 return MCDisassembler::Success;
3106 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3107 uint64_t Address, const void *Decoder) {
3108 DecodeStatus S = MCDisassembler::Success;
3110 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3111 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3112 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3113 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
3114 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3115 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
3116 unsigned op = fieldFromInstruction(Insn, 6, 1);
3118 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3119 return MCDisassembler::Fail;
3121 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3122 return MCDisassembler::Fail; // Writeback
3125 switch (Inst.getOpcode()) {
3128 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3129 return MCDisassembler::Fail;
3132 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3133 return MCDisassembler::Fail;
3136 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3137 return MCDisassembler::Fail;
3142 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3143 uint64_t Address, const void *Decoder) {
3144 DecodeStatus S = MCDisassembler::Success;
3146 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3147 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3149 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3150 return MCDisassembler::Fail;
3152 switch(Inst.getOpcode()) {
3154 return MCDisassembler::Fail;
3156 break; // tADR does not explicitly represent the PC as an operand.
3158 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3162 Inst.addOperand(MCOperand::CreateImm(imm));
3166 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3167 uint64_t Address, const void *Decoder) {
3168 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
3169 true, 2, Inst, Decoder))
3170 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
3171 return MCDisassembler::Success;
3174 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3175 uint64_t Address, const void *Decoder) {
3176 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
3177 true, 4, Inst, Decoder))
3178 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
3179 return MCDisassembler::Success;
3182 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3183 uint64_t Address, const void *Decoder) {
3184 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
3185 true, 2, Inst, Decoder))
3186 Inst.addOperand(MCOperand::CreateImm(Val << 1));
3187 return MCDisassembler::Success;
3190 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
3191 uint64_t Address, const void *Decoder) {
3192 DecodeStatus S = MCDisassembler::Success;
3194 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3195 unsigned Rm = fieldFromInstruction(Val, 3, 3);
3197 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3198 return MCDisassembler::Fail;
3199 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
3200 return MCDisassembler::Fail;
3205 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
3206 uint64_t Address, const void *Decoder) {
3207 DecodeStatus S = MCDisassembler::Success;
3209 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3210 unsigned imm = fieldFromInstruction(Val, 3, 5);
3212 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
3213 return MCDisassembler::Fail;
3214 Inst.addOperand(MCOperand::CreateImm(imm));
3219 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
3220 uint64_t Address, const void *Decoder) {
3221 unsigned imm = Val << 2;
3223 Inst.addOperand(MCOperand::CreateImm(imm));
3224 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
3226 return MCDisassembler::Success;
3229 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
3230 uint64_t Address, const void *Decoder) {
3231 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3232 Inst.addOperand(MCOperand::CreateImm(Val));
3234 return MCDisassembler::Success;
3237 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
3238 uint64_t Address, const void *Decoder) {
3239 DecodeStatus S = MCDisassembler::Success;
3241 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3242 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3243 unsigned imm = fieldFromInstruction(Val, 0, 2);
3245 // Thumb stores cannot use PC as dest register.
3246 switch (Inst.getOpcode()) {
3251 return MCDisassembler::Fail;
3256 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3257 return MCDisassembler::Fail;
3258 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3259 return MCDisassembler::Fail;
3260 Inst.addOperand(MCOperand::CreateImm(imm));
3265 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
3266 uint64_t Address, const void *Decoder) {
3267 DecodeStatus S = MCDisassembler::Success;
3269 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3270 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3273 switch (Inst.getOpcode()) {
3275 Inst.setOpcode(ARM::t2LDRBpci);
3278 Inst.setOpcode(ARM::t2LDRHpci);
3281 Inst.setOpcode(ARM::t2LDRSHpci);
3284 Inst.setOpcode(ARM::t2LDRSBpci);
3287 Inst.setOpcode(ARM::t2LDRpci);
3290 Inst.setOpcode(ARM::t2PLDpci);
3293 Inst.setOpcode(ARM::t2PLIpci);
3296 return MCDisassembler::Fail;
3299 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3303 switch (Inst.getOpcode()) {
3305 return MCDisassembler::Fail;
3307 // FIXME: this instruction is only available with MP extensions,
3308 // this should be checked first but we don't have access to the
3309 // feature bits here.
3310 Inst.setOpcode(ARM::t2PLDWs);
3317 switch (Inst.getOpcode()) {
3323 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3324 return MCDisassembler::Fail;
3327 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3328 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3329 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
3330 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
3331 return MCDisassembler::Fail;
3336 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
3337 uint64_t Address, const void* Decoder) {
3338 DecodeStatus S = MCDisassembler::Success;
3340 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3341 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3342 unsigned U = fieldFromInstruction(Insn, 9, 1);
3343 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3348 switch (Inst.getOpcode()) {
3350 Inst.setOpcode(ARM::t2LDRpci);
3353 Inst.setOpcode(ARM::t2LDRBpci);
3355 case ARM::t2LDRSBi8:
3356 Inst.setOpcode(ARM::t2LDRSBpci);
3359 Inst.setOpcode(ARM::t2LDRHpci);
3361 case ARM::t2LDRSHi8:
3362 Inst.setOpcode(ARM::t2LDRSHpci);
3365 Inst.setOpcode(ARM::t2PLDpci);
3368 Inst.setOpcode(ARM::t2PLIpci);
3371 return MCDisassembler::Fail;
3373 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3377 switch (Inst.getOpcode()) {
3378 case ARM::t2LDRSHi8:
3379 return MCDisassembler::Fail;
3385 switch (Inst.getOpcode()) {
3391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3392 return MCDisassembler::Fail;
3395 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3396 return MCDisassembler::Fail;
3400 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
3401 uint64_t Address, const void* Decoder) {
3402 DecodeStatus S = MCDisassembler::Success;
3404 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3405 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3406 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3410 switch (Inst.getOpcode()) {
3412 Inst.setOpcode(ARM::t2LDRpci);
3414 case ARM::t2LDRHi12:
3415 Inst.setOpcode(ARM::t2LDRHpci);
3417 case ARM::t2LDRSHi12:
3418 Inst.setOpcode(ARM::t2LDRSHpci);
3420 case ARM::t2LDRBi12:
3421 Inst.setOpcode(ARM::t2LDRBpci);
3423 case ARM::t2LDRSBi12:
3424 Inst.setOpcode(ARM::t2LDRSBpci);
3427 Inst.setOpcode(ARM::t2PLDpci);
3430 Inst.setOpcode(ARM::t2PLIpci);
3433 return MCDisassembler::Fail;
3435 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3439 switch (Inst.getOpcode()) {
3440 case ARM::t2LDRSHi12:
3441 return MCDisassembler::Fail;
3442 case ARM::t2LDRHi12:
3443 Inst.setOpcode(ARM::t2PLDi12);
3450 switch (Inst.getOpcode()) {
3452 case ARM::t2PLDWi12:
3456 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3457 return MCDisassembler::Fail;
3460 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
3461 return MCDisassembler::Fail;
3465 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
3466 uint64_t Address, const void* Decoder) {
3467 DecodeStatus S = MCDisassembler::Success;
3469 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3470 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3471 unsigned imm = fieldFromInstruction(Insn, 0, 8);
3475 switch (Inst.getOpcode()) {
3477 Inst.setOpcode(ARM::t2LDRpci);
3480 Inst.setOpcode(ARM::t2LDRBpci);
3483 Inst.setOpcode(ARM::t2LDRHpci);
3486 Inst.setOpcode(ARM::t2LDRSBpci);
3489 Inst.setOpcode(ARM::t2LDRSHpci);
3492 return MCDisassembler::Fail;
3494 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3497 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
3498 return MCDisassembler::Fail;
3499 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
3500 return MCDisassembler::Fail;
3504 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
3505 uint64_t Address, const void* Decoder) {
3506 DecodeStatus S = MCDisassembler::Success;
3508 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3509 unsigned U = fieldFromInstruction(Insn, 23, 1);
3510 int imm = fieldFromInstruction(Insn, 0, 12);
3513 switch (Inst.getOpcode()) {
3514 case ARM::t2LDRBpci:
3515 case ARM::t2LDRHpci:
3516 Inst.setOpcode(ARM::t2PLDpci);
3518 case ARM::t2LDRSBpci:
3519 Inst.setOpcode(ARM::t2PLIpci);
3521 case ARM::t2LDRSHpci:
3522 return MCDisassembler::Fail;
3528 switch(Inst.getOpcode()) {
3533 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3534 return MCDisassembler::Fail;
3538 // Special case for #-0.
3544 Inst.addOperand(MCOperand::CreateImm(imm));
3549 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
3550 uint64_t Address, const void *Decoder) {
3552 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3554 int imm = Val & 0xFF;
3556 if (!(Val & 0x100)) imm *= -1;
3557 Inst.addOperand(MCOperand::CreateImm(imm * 4));
3560 return MCDisassembler::Success;
3563 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
3564 uint64_t Address, const void *Decoder) {
3565 DecodeStatus S = MCDisassembler::Success;
3567 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3568 unsigned imm = fieldFromInstruction(Val, 0, 9);
3570 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3571 return MCDisassembler::Fail;
3572 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
3573 return MCDisassembler::Fail;
3578 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
3579 uint64_t Address, const void *Decoder) {
3580 DecodeStatus S = MCDisassembler::Success;
3582 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3583 unsigned imm = fieldFromInstruction(Val, 0, 8);
3585 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
3586 return MCDisassembler::Fail;
3588 Inst.addOperand(MCOperand::CreateImm(imm));
3593 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
3594 uint64_t Address, const void *Decoder) {
3595 int imm = Val & 0xFF;
3598 else if (!(Val & 0x100))
3600 Inst.addOperand(MCOperand::CreateImm(imm));
3602 return MCDisassembler::Success;
3606 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
3607 uint64_t Address, const void *Decoder) {
3608 DecodeStatus S = MCDisassembler::Success;
3610 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3611 unsigned imm = fieldFromInstruction(Val, 0, 9);
3613 // Thumb stores cannot use PC as dest register.
3614 switch (Inst.getOpcode()) {
3622 return MCDisassembler::Fail;
3628 // Some instructions always use an additive offset.
3629 switch (Inst.getOpcode()) {
3644 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3645 return MCDisassembler::Fail;
3646 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
3647 return MCDisassembler::Fail;
3652 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
3653 uint64_t Address, const void *Decoder) {
3654 DecodeStatus S = MCDisassembler::Success;
3656 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3657 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3658 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3659 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
3661 unsigned load = fieldFromInstruction(Insn, 20, 1);
3664 switch (Inst.getOpcode()) {
3665 case ARM::t2LDR_PRE:
3666 case ARM::t2LDR_POST:
3667 Inst.setOpcode(ARM::t2LDRpci);
3669 case ARM::t2LDRB_PRE:
3670 case ARM::t2LDRB_POST:
3671 Inst.setOpcode(ARM::t2LDRBpci);
3673 case ARM::t2LDRH_PRE:
3674 case ARM::t2LDRH_POST:
3675 Inst.setOpcode(ARM::t2LDRHpci);
3677 case ARM::t2LDRSB_PRE:
3678 case ARM::t2LDRSB_POST:
3680 Inst.setOpcode(ARM::t2PLIpci);
3682 Inst.setOpcode(ARM::t2LDRSBpci);
3684 case ARM::t2LDRSH_PRE:
3685 case ARM::t2LDRSH_POST:
3686 Inst.setOpcode(ARM::t2LDRSHpci);
3689 return MCDisassembler::Fail;
3691 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
3695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3696 return MCDisassembler::Fail;
3699 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
3700 return MCDisassembler::Fail;
3703 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3704 return MCDisassembler::Fail;
3707 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
3708 return MCDisassembler::Fail;
3713 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
3714 uint64_t Address, const void *Decoder) {
3715 DecodeStatus S = MCDisassembler::Success;
3717 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3718 unsigned imm = fieldFromInstruction(Val, 0, 12);
3720 // Thumb stores cannot use PC as dest register.
3721 switch (Inst.getOpcode()) {
3723 case ARM::t2STRBi12:
3724 case ARM::t2STRHi12:
3726 return MCDisassembler::Fail;
3731 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3732 return MCDisassembler::Fail;
3733 Inst.addOperand(MCOperand::CreateImm(imm));
3739 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
3740 uint64_t Address, const void *Decoder) {
3741 unsigned imm = fieldFromInstruction(Insn, 0, 7);
3743 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3744 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3745 Inst.addOperand(MCOperand::CreateImm(imm));
3747 return MCDisassembler::Success;
3750 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
3751 uint64_t Address, const void *Decoder) {
3752 DecodeStatus S = MCDisassembler::Success;
3754 if (Inst.getOpcode() == ARM::tADDrSP) {
3755 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3756 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
3758 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3759 return MCDisassembler::Fail;
3760 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
3762 return MCDisassembler::Fail;
3763 } else if (Inst.getOpcode() == ARM::tADDspr) {
3764 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
3766 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3767 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
3768 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3769 return MCDisassembler::Fail;
3775 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
3776 uint64_t Address, const void *Decoder) {
3777 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3778 unsigned flags = fieldFromInstruction(Insn, 0, 3);
3780 Inst.addOperand(MCOperand::CreateImm(imod));
3781 Inst.addOperand(MCOperand::CreateImm(flags));
3783 return MCDisassembler::Success;
3786 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
3787 uint64_t Address, const void *Decoder) {
3788 DecodeStatus S = MCDisassembler::Success;
3789 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3790 unsigned add = fieldFromInstruction(Insn, 4, 1);
3792 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
3793 return MCDisassembler::Fail;
3794 Inst.addOperand(MCOperand::CreateImm(add));
3799 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
3800 uint64_t Address, const void *Decoder) {
3801 // Val is passed in as S:J1:J2:imm10H:imm10L:'0'
3802 // Note only one trailing zero not two. Also the J1 and J2 values are from
3803 // the encoded instruction. So here change to I1 and I2 values via:
3804 // I1 = NOT(J1 EOR S);
3805 // I2 = NOT(J2 EOR S);
3806 // and build the imm32 with two trailing zeros as documented:
3807 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
3808 unsigned S = (Val >> 23) & 1;
3809 unsigned J1 = (Val >> 22) & 1;
3810 unsigned J2 = (Val >> 21) & 1;
3811 unsigned I1 = !(J1 ^ S);
3812 unsigned I2 = !(J2 ^ S);
3813 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3814 int imm32 = SignExtend32<25>(tmp << 1);
3816 if (!tryAddingSymbolicOperand(Address,
3817 (Address & ~2u) + imm32 + 4,
3818 true, 4, Inst, Decoder))
3819 Inst.addOperand(MCOperand::CreateImm(imm32));
3820 return MCDisassembler::Success;
3823 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
3824 uint64_t Address, const void *Decoder) {
3825 if (Val == 0xA || Val == 0xB)
3826 return MCDisassembler::Fail;
3828 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3830 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3831 return MCDisassembler::Fail;
3833 Inst.addOperand(MCOperand::CreateImm(Val));
3834 return MCDisassembler::Success;
3838 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
3839 uint64_t Address, const void *Decoder) {
3840 DecodeStatus S = MCDisassembler::Success;
3842 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3843 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3845 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
3846 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3847 return MCDisassembler::Fail;
3848 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
3849 return MCDisassembler::Fail;
3854 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
3855 uint64_t Address, const void *Decoder) {
3856 DecodeStatus S = MCDisassembler::Success;
3858 unsigned pred = fieldFromInstruction(Insn, 22, 4);
3859 if (pred == 0xE || pred == 0xF) {
3860 unsigned opc = fieldFromInstruction(Insn, 4, 28);
3863 return MCDisassembler::Fail;
3865 Inst.setOpcode(ARM::t2DSB);
3868 Inst.setOpcode(ARM::t2DMB);
3871 Inst.setOpcode(ARM::t2ISB);
3875 unsigned imm = fieldFromInstruction(Insn, 0, 4);
3876 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
3879 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3880 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3881 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3882 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3883 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
3885 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
3886 return MCDisassembler::Fail;
3887 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
3888 return MCDisassembler::Fail;
3893 // Decode a shifted immediate operand. These basically consist
3894 // of an 8-bit value, and a 4-bit directive that specifies either
3895 // a splat operation or a rotation.
3896 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
3897 uint64_t Address, const void *Decoder) {
3898 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
3900 unsigned byte = fieldFromInstruction(Val, 8, 2);
3901 unsigned imm = fieldFromInstruction(Val, 0, 8);
3904 Inst.addOperand(MCOperand::CreateImm(imm));
3907 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
3910 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
3913 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
3918 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3919 unsigned rot = fieldFromInstruction(Val, 7, 5);
3920 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
3921 Inst.addOperand(MCOperand::CreateImm(imm));
3924 return MCDisassembler::Success;
3928 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
3929 uint64_t Address, const void *Decoder){
3930 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
3931 true, 2, Inst, Decoder))
3932 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
3933 return MCDisassembler::Success;
3936 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
3937 uint64_t Address, const void *Decoder){
3938 // Val is passed in as S:J1:J2:imm10:imm11
3939 // Note no trailing zero after imm11. Also the J1 and J2 values are from
3940 // the encoded instruction. So here change to I1 and I2 values via:
3941 // I1 = NOT(J1 EOR S);
3942 // I2 = NOT(J2 EOR S);
3943 // and build the imm32 with one trailing zero as documented:
3944 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
3945 unsigned S = (Val >> 23) & 1;
3946 unsigned J1 = (Val >> 22) & 1;
3947 unsigned J2 = (Val >> 21) & 1;
3948 unsigned I1 = !(J1 ^ S);
3949 unsigned I2 = !(J2 ^ S);
3950 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21);
3951 int imm32 = SignExtend32<25>(tmp << 1);
3953 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
3954 true, 4, Inst, Decoder))
3955 Inst.addOperand(MCOperand::CreateImm(imm32));
3956 return MCDisassembler::Success;
3959 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
3960 uint64_t Address, const void *Decoder) {
3962 return MCDisassembler::Fail;
3964 Inst.addOperand(MCOperand::CreateImm(Val));
3965 return MCDisassembler::Success;
3968 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
3969 uint64_t Address, const void *Decoder) {
3971 return MCDisassembler::Fail;
3973 Inst.addOperand(MCOperand::CreateImm(Val));
3974 return MCDisassembler::Success;
3977 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
3978 uint64_t Address, const void *Decoder) {
3979 DecodeStatus S = MCDisassembler::Success;
3980 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3982 if (FeatureBits & ARM::FeatureMClass) {
3983 unsigned ValLow = Val & 0xff;
3985 // Validate the SYSm value first.
4000 case 18: // basepri_max
4001 case 19: // faultmask
4002 if (!(FeatureBits & ARM::HasV7Ops))
4003 // Values basepri, basepri_max and faultmask are only valid for v7m.
4004 return MCDisassembler::Fail;
4007 return MCDisassembler::Fail;
4010 if (Inst.getOpcode() == ARM::t2MSR_M) {
4011 unsigned Mask = fieldFromInstruction(Val, 10, 2);
4012 if (!(FeatureBits & ARM::HasV7Ops)) {
4013 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are
4016 S = MCDisassembler::SoftFail;
4019 // The ARMv7-M architecture stores an additional 2-bit mask value in
4020 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and
4021 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if
4022 // the NZCVQ bits should be moved by the instruction. Bit mask{0}
4023 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set
4024 // only if the processor includes the DSP extension.
4025 if (Mask == 0 || (Mask != 2 && ValLow > 3) ||
4026 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1)))
4027 S = MCDisassembler::SoftFail;
4033 return MCDisassembler::Fail;
4035 Inst.addOperand(MCOperand::CreateImm(Val));
4039 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
4040 uint64_t Address, const void *Decoder) {
4042 unsigned R = fieldFromInstruction(Val, 5, 1);
4043 unsigned SysM = fieldFromInstruction(Val, 0, 5);
4045 // The table of encodings for these banked registers comes from B9.2.3 of the
4046 // ARM ARM. There are patterns, but nothing regular enough to make this logic
4047 // neater. So by fiat, these values are UNPREDICTABLE:
4049 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 ||
4050 SysM == 0x1a || SysM == 0x1b)
4051 return MCDisassembler::SoftFail;
4053 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 &&
4054 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e)
4055 return MCDisassembler::SoftFail;
4058 Inst.addOperand(MCOperand::CreateImm(Val));
4059 return MCDisassembler::Success;
4062 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
4063 uint64_t Address, const void *Decoder) {
4064 DecodeStatus S = MCDisassembler::Success;
4066 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4067 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4068 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4071 S = MCDisassembler::SoftFail;
4073 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4074 return MCDisassembler::Fail;
4075 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4076 return MCDisassembler::Fail;
4077 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4078 return MCDisassembler::Fail;
4083 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
4084 uint64_t Address, const void *Decoder){
4085 DecodeStatus S = MCDisassembler::Success;
4087 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4088 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
4089 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4090 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4092 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
4093 return MCDisassembler::Fail;
4095 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1)
4096 S = MCDisassembler::SoftFail;
4098 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
4099 return MCDisassembler::Fail;
4100 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4101 return MCDisassembler::Fail;
4102 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4103 return MCDisassembler::Fail;
4108 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
4109 uint64_t Address, const void *Decoder) {
4110 DecodeStatus S = MCDisassembler::Success;
4112 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4113 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4114 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4115 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4116 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4117 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4119 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4121 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4122 return MCDisassembler::Fail;
4123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4124 return MCDisassembler::Fail;
4125 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4126 return MCDisassembler::Fail;
4127 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4128 return MCDisassembler::Fail;
4133 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
4134 uint64_t Address, const void *Decoder) {
4135 DecodeStatus S = MCDisassembler::Success;
4137 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4138 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4139 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4140 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4141 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4142 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4143 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4145 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4146 if (Rm == 0xF) S = MCDisassembler::SoftFail;
4148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4149 return MCDisassembler::Fail;
4150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4151 return MCDisassembler::Fail;
4152 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4153 return MCDisassembler::Fail;
4154 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4155 return MCDisassembler::Fail;
4161 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
4162 uint64_t Address, const void *Decoder) {
4163 DecodeStatus S = MCDisassembler::Success;
4165 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4166 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4167 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4168 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4169 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4170 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4172 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4174 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4175 return MCDisassembler::Fail;
4176 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4177 return MCDisassembler::Fail;
4178 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
4179 return MCDisassembler::Fail;
4180 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4181 return MCDisassembler::Fail;
4186 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
4187 uint64_t Address, const void *Decoder) {
4188 DecodeStatus S = MCDisassembler::Success;
4190 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4191 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4192 unsigned imm = fieldFromInstruction(Insn, 0, 12);
4193 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
4194 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
4195 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4197 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
4199 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4200 return MCDisassembler::Fail;
4201 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4202 return MCDisassembler::Fail;
4203 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
4204 return MCDisassembler::Fail;
4205 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4206 return MCDisassembler::Fail;
4211 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
4212 uint64_t Address, const void *Decoder) {
4213 DecodeStatus S = MCDisassembler::Success;
4215 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4216 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4217 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4218 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4219 unsigned size = fieldFromInstruction(Insn, 10, 2);
4225 return MCDisassembler::Fail;
4227 if (fieldFromInstruction(Insn, 4, 1))
4228 return MCDisassembler::Fail; // UNDEFINED
4229 index = fieldFromInstruction(Insn, 5, 3);
4232 if (fieldFromInstruction(Insn, 5, 1))
4233 return MCDisassembler::Fail; // UNDEFINED
4234 index = fieldFromInstruction(Insn, 6, 2);
4235 if (fieldFromInstruction(Insn, 4, 1))
4239 if (fieldFromInstruction(Insn, 6, 1))
4240 return MCDisassembler::Fail; // UNDEFINED
4241 index = fieldFromInstruction(Insn, 7, 1);
4243 switch (fieldFromInstruction(Insn, 4, 2)) {
4249 return MCDisassembler::Fail;
4254 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4255 return MCDisassembler::Fail;
4256 if (Rm != 0xF) { // Writeback
4257 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4258 return MCDisassembler::Fail;
4260 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4261 return MCDisassembler::Fail;
4262 Inst.addOperand(MCOperand::CreateImm(align));
4265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4266 return MCDisassembler::Fail;
4268 Inst.addOperand(MCOperand::CreateReg(0));
4271 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4272 return MCDisassembler::Fail;
4273 Inst.addOperand(MCOperand::CreateImm(index));
4278 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
4279 uint64_t Address, const void *Decoder) {
4280 DecodeStatus S = MCDisassembler::Success;
4282 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4283 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4284 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4285 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4286 unsigned size = fieldFromInstruction(Insn, 10, 2);
4292 return MCDisassembler::Fail;
4294 if (fieldFromInstruction(Insn, 4, 1))
4295 return MCDisassembler::Fail; // UNDEFINED
4296 index = fieldFromInstruction(Insn, 5, 3);
4299 if (fieldFromInstruction(Insn, 5, 1))
4300 return MCDisassembler::Fail; // UNDEFINED
4301 index = fieldFromInstruction(Insn, 6, 2);
4302 if (fieldFromInstruction(Insn, 4, 1))
4306 if (fieldFromInstruction(Insn, 6, 1))
4307 return MCDisassembler::Fail; // UNDEFINED
4308 index = fieldFromInstruction(Insn, 7, 1);
4310 switch (fieldFromInstruction(Insn, 4, 2)) {
4316 return MCDisassembler::Fail;
4321 if (Rm != 0xF) { // Writeback
4322 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4323 return MCDisassembler::Fail;
4325 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4326 return MCDisassembler::Fail;
4327 Inst.addOperand(MCOperand::CreateImm(align));
4330 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4331 return MCDisassembler::Fail;
4333 Inst.addOperand(MCOperand::CreateReg(0));
4336 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4337 return MCDisassembler::Fail;
4338 Inst.addOperand(MCOperand::CreateImm(index));
4344 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
4345 uint64_t Address, const void *Decoder) {
4346 DecodeStatus S = MCDisassembler::Success;
4348 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4349 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4350 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4351 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4352 unsigned size = fieldFromInstruction(Insn, 10, 2);
4359 return MCDisassembler::Fail;
4361 index = fieldFromInstruction(Insn, 5, 3);
4362 if (fieldFromInstruction(Insn, 4, 1))
4366 index = fieldFromInstruction(Insn, 6, 2);
4367 if (fieldFromInstruction(Insn, 4, 1))
4369 if (fieldFromInstruction(Insn, 5, 1))
4373 if (fieldFromInstruction(Insn, 5, 1))
4374 return MCDisassembler::Fail; // UNDEFINED
4375 index = fieldFromInstruction(Insn, 7, 1);
4376 if (fieldFromInstruction(Insn, 4, 1) != 0)
4378 if (fieldFromInstruction(Insn, 6, 1))
4383 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4384 return MCDisassembler::Fail;
4385 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4386 return MCDisassembler::Fail;
4387 if (Rm != 0xF) { // Writeback
4388 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4389 return MCDisassembler::Fail;
4391 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4392 return MCDisassembler::Fail;
4393 Inst.addOperand(MCOperand::CreateImm(align));
4396 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4397 return MCDisassembler::Fail;
4399 Inst.addOperand(MCOperand::CreateReg(0));
4402 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4403 return MCDisassembler::Fail;
4404 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4405 return MCDisassembler::Fail;
4406 Inst.addOperand(MCOperand::CreateImm(index));
4411 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
4412 uint64_t Address, const void *Decoder) {
4413 DecodeStatus S = MCDisassembler::Success;
4415 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4416 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4417 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4418 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4419 unsigned size = fieldFromInstruction(Insn, 10, 2);
4426 return MCDisassembler::Fail;
4428 index = fieldFromInstruction(Insn, 5, 3);
4429 if (fieldFromInstruction(Insn, 4, 1))
4433 index = fieldFromInstruction(Insn, 6, 2);
4434 if (fieldFromInstruction(Insn, 4, 1))
4436 if (fieldFromInstruction(Insn, 5, 1))
4440 if (fieldFromInstruction(Insn, 5, 1))
4441 return MCDisassembler::Fail; // UNDEFINED
4442 index = fieldFromInstruction(Insn, 7, 1);
4443 if (fieldFromInstruction(Insn, 4, 1) != 0)
4445 if (fieldFromInstruction(Insn, 6, 1))
4450 if (Rm != 0xF) { // Writeback
4451 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4452 return MCDisassembler::Fail;
4454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4455 return MCDisassembler::Fail;
4456 Inst.addOperand(MCOperand::CreateImm(align));
4459 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4460 return MCDisassembler::Fail;
4462 Inst.addOperand(MCOperand::CreateReg(0));
4465 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4466 return MCDisassembler::Fail;
4467 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4468 return MCDisassembler::Fail;
4469 Inst.addOperand(MCOperand::CreateImm(index));
4475 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
4476 uint64_t Address, const void *Decoder) {
4477 DecodeStatus S = MCDisassembler::Success;
4479 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4480 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4481 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4482 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4483 unsigned size = fieldFromInstruction(Insn, 10, 2);
4490 return MCDisassembler::Fail;
4492 if (fieldFromInstruction(Insn, 4, 1))
4493 return MCDisassembler::Fail; // UNDEFINED
4494 index = fieldFromInstruction(Insn, 5, 3);
4497 if (fieldFromInstruction(Insn, 4, 1))
4498 return MCDisassembler::Fail; // UNDEFINED
4499 index = fieldFromInstruction(Insn, 6, 2);
4500 if (fieldFromInstruction(Insn, 5, 1))
4504 if (fieldFromInstruction(Insn, 4, 2))
4505 return MCDisassembler::Fail; // UNDEFINED
4506 index = fieldFromInstruction(Insn, 7, 1);
4507 if (fieldFromInstruction(Insn, 6, 1))
4512 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4513 return MCDisassembler::Fail;
4514 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4515 return MCDisassembler::Fail;
4516 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4517 return MCDisassembler::Fail;
4519 if (Rm != 0xF) { // Writeback
4520 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4521 return MCDisassembler::Fail;
4523 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4524 return MCDisassembler::Fail;
4525 Inst.addOperand(MCOperand::CreateImm(align));
4528 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4529 return MCDisassembler::Fail;
4531 Inst.addOperand(MCOperand::CreateReg(0));
4534 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4535 return MCDisassembler::Fail;
4536 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4537 return MCDisassembler::Fail;
4538 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4539 return MCDisassembler::Fail;
4540 Inst.addOperand(MCOperand::CreateImm(index));
4545 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
4546 uint64_t Address, const void *Decoder) {
4547 DecodeStatus S = MCDisassembler::Success;
4549 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4550 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4551 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4552 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4553 unsigned size = fieldFromInstruction(Insn, 10, 2);
4560 return MCDisassembler::Fail;
4562 if (fieldFromInstruction(Insn, 4, 1))
4563 return MCDisassembler::Fail; // UNDEFINED
4564 index = fieldFromInstruction(Insn, 5, 3);
4567 if (fieldFromInstruction(Insn, 4, 1))
4568 return MCDisassembler::Fail; // UNDEFINED
4569 index = fieldFromInstruction(Insn, 6, 2);
4570 if (fieldFromInstruction(Insn, 5, 1))
4574 if (fieldFromInstruction(Insn, 4, 2))
4575 return MCDisassembler::Fail; // UNDEFINED
4576 index = fieldFromInstruction(Insn, 7, 1);
4577 if (fieldFromInstruction(Insn, 6, 1))
4582 if (Rm != 0xF) { // Writeback
4583 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4584 return MCDisassembler::Fail;
4586 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4587 return MCDisassembler::Fail;
4588 Inst.addOperand(MCOperand::CreateImm(align));
4591 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4592 return MCDisassembler::Fail;
4594 Inst.addOperand(MCOperand::CreateReg(0));
4597 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4598 return MCDisassembler::Fail;
4599 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4600 return MCDisassembler::Fail;
4601 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4602 return MCDisassembler::Fail;
4603 Inst.addOperand(MCOperand::CreateImm(index));
4609 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
4610 uint64_t Address, const void *Decoder) {
4611 DecodeStatus S = MCDisassembler::Success;
4613 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4614 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4615 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4616 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4617 unsigned size = fieldFromInstruction(Insn, 10, 2);
4624 return MCDisassembler::Fail;
4626 if (fieldFromInstruction(Insn, 4, 1))
4628 index = fieldFromInstruction(Insn, 5, 3);
4631 if (fieldFromInstruction(Insn, 4, 1))
4633 index = fieldFromInstruction(Insn, 6, 2);
4634 if (fieldFromInstruction(Insn, 5, 1))
4638 switch (fieldFromInstruction(Insn, 4, 2)) {
4642 return MCDisassembler::Fail;
4644 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4647 index = fieldFromInstruction(Insn, 7, 1);
4648 if (fieldFromInstruction(Insn, 6, 1))
4653 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4654 return MCDisassembler::Fail;
4655 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4656 return MCDisassembler::Fail;
4657 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4658 return MCDisassembler::Fail;
4659 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4660 return MCDisassembler::Fail;
4662 if (Rm != 0xF) { // Writeback
4663 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4664 return MCDisassembler::Fail;
4666 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4667 return MCDisassembler::Fail;
4668 Inst.addOperand(MCOperand::CreateImm(align));
4671 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4672 return MCDisassembler::Fail;
4674 Inst.addOperand(MCOperand::CreateReg(0));
4677 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4678 return MCDisassembler::Fail;
4679 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4680 return MCDisassembler::Fail;
4681 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4682 return MCDisassembler::Fail;
4683 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4684 return MCDisassembler::Fail;
4685 Inst.addOperand(MCOperand::CreateImm(index));
4690 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
4691 uint64_t Address, const void *Decoder) {
4692 DecodeStatus S = MCDisassembler::Success;
4694 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4695 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4696 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4697 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4698 unsigned size = fieldFromInstruction(Insn, 10, 2);
4705 return MCDisassembler::Fail;
4707 if (fieldFromInstruction(Insn, 4, 1))
4709 index = fieldFromInstruction(Insn, 5, 3);
4712 if (fieldFromInstruction(Insn, 4, 1))
4714 index = fieldFromInstruction(Insn, 6, 2);
4715 if (fieldFromInstruction(Insn, 5, 1))
4719 switch (fieldFromInstruction(Insn, 4, 2)) {
4723 return MCDisassembler::Fail;
4725 align = 4 << fieldFromInstruction(Insn, 4, 2); break;
4728 index = fieldFromInstruction(Insn, 7, 1);
4729 if (fieldFromInstruction(Insn, 6, 1))
4734 if (Rm != 0xF) { // Writeback
4735 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4736 return MCDisassembler::Fail;
4738 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4739 return MCDisassembler::Fail;
4740 Inst.addOperand(MCOperand::CreateImm(align));
4743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4744 return MCDisassembler::Fail;
4746 Inst.addOperand(MCOperand::CreateReg(0));
4749 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
4750 return MCDisassembler::Fail;
4751 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
4752 return MCDisassembler::Fail;
4753 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
4754 return MCDisassembler::Fail;
4755 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
4756 return MCDisassembler::Fail;
4757 Inst.addOperand(MCOperand::CreateImm(index));
4762 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
4763 uint64_t Address, const void *Decoder) {
4764 DecodeStatus S = MCDisassembler::Success;
4765 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4766 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4767 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4768 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4769 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4771 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4772 S = MCDisassembler::SoftFail;
4774 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4775 return MCDisassembler::Fail;
4776 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4777 return MCDisassembler::Fail;
4778 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4779 return MCDisassembler::Fail;
4780 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4781 return MCDisassembler::Fail;
4782 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4783 return MCDisassembler::Fail;
4788 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
4789 uint64_t Address, const void *Decoder) {
4790 DecodeStatus S = MCDisassembler::Success;
4791 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4792 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4793 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4794 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4795 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
4797 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
4798 S = MCDisassembler::SoftFail;
4800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
4801 return MCDisassembler::Fail;
4802 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
4803 return MCDisassembler::Fail;
4804 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
4805 return MCDisassembler::Fail;
4806 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
4807 return MCDisassembler::Fail;
4808 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4809 return MCDisassembler::Fail;
4814 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
4815 uint64_t Address, const void *Decoder) {
4816 DecodeStatus S = MCDisassembler::Success;
4817 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4818 unsigned mask = fieldFromInstruction(Insn, 0, 4);
4822 S = MCDisassembler::SoftFail;
4826 return MCDisassembler::Fail;
4828 Inst.addOperand(MCOperand::CreateImm(pred));
4829 Inst.addOperand(MCOperand::CreateImm(mask));
4834 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
4835 uint64_t Address, const void *Decoder) {
4836 DecodeStatus S = MCDisassembler::Success;
4838 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4839 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4840 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4841 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4842 unsigned W = fieldFromInstruction(Insn, 21, 1);
4843 unsigned U = fieldFromInstruction(Insn, 23, 1);
4844 unsigned P = fieldFromInstruction(Insn, 24, 1);
4845 bool writeback = (W == 1) | (P == 0);
4847 addr |= (U << 8) | (Rn << 9);
4849 if (writeback && (Rn == Rt || Rn == Rt2))
4850 Check(S, MCDisassembler::SoftFail);
4852 Check(S, MCDisassembler::SoftFail);
4855 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4856 return MCDisassembler::Fail;
4858 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4859 return MCDisassembler::Fail;
4860 // Writeback operand
4861 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4862 return MCDisassembler::Fail;
4864 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4865 return MCDisassembler::Fail;
4871 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
4872 uint64_t Address, const void *Decoder) {
4873 DecodeStatus S = MCDisassembler::Success;
4875 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4876 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4877 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4878 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4879 unsigned W = fieldFromInstruction(Insn, 21, 1);
4880 unsigned U = fieldFromInstruction(Insn, 23, 1);
4881 unsigned P = fieldFromInstruction(Insn, 24, 1);
4882 bool writeback = (W == 1) | (P == 0);
4884 addr |= (U << 8) | (Rn << 9);
4886 if (writeback && (Rn == Rt || Rn == Rt2))
4887 Check(S, MCDisassembler::SoftFail);
4889 // Writeback operand
4890 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4891 return MCDisassembler::Fail;
4893 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4894 return MCDisassembler::Fail;
4896 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
4897 return MCDisassembler::Fail;
4899 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
4900 return MCDisassembler::Fail;
4905 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
4906 uint64_t Address, const void *Decoder) {
4907 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4908 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
4909 if (sign1 != sign2) return MCDisassembler::Fail;
4911 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4912 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4913 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
4915 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
4917 return MCDisassembler::Success;
4920 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
4922 const void *Decoder) {
4923 DecodeStatus S = MCDisassembler::Success;
4925 // Shift of "asr #32" is not allowed in Thumb2 mode.
4926 if (Val == 0x20) S = MCDisassembler::SoftFail;
4927 Inst.addOperand(MCOperand::CreateImm(Val));
4931 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
4932 uint64_t Address, const void *Decoder) {
4933 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4934 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4935 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4936 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4939 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
4941 DecodeStatus S = MCDisassembler::Success;
4943 if (Rt == Rn || Rn == Rt2)
4944 S = MCDisassembler::SoftFail;
4946 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4947 return MCDisassembler::Fail;
4948 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4949 return MCDisassembler::Fail;
4950 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4951 return MCDisassembler::Fail;
4952 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4953 return MCDisassembler::Fail;
4958 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
4959 uint64_t Address, const void *Decoder) {
4960 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4961 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4962 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4963 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4964 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4965 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4966 unsigned op = fieldFromInstruction(Insn, 5, 1);
4968 DecodeStatus S = MCDisassembler::Success;
4970 // VMOVv2f32 is ambiguous with these decodings.
4971 if (!(imm & 0x38) && cmode == 0xF) {
4972 if (op == 1) return MCDisassembler::Fail;
4973 Inst.setOpcode(ARM::VMOVv2f32);
4974 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
4977 if (!(imm & 0x20)) return MCDisassembler::Fail;
4979 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
4980 return MCDisassembler::Fail;
4981 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
4982 return MCDisassembler::Fail;
4983 Inst.addOperand(MCOperand::CreateImm(64 - imm));
4988 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
4989 uint64_t Address, const void *Decoder) {
4990 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4991 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4992 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4993 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4994 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4995 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
4996 unsigned op = fieldFromInstruction(Insn, 5, 1);
4998 DecodeStatus S = MCDisassembler::Success;
5000 // VMOVv4f32 is ambiguous with these decodings.
5001 if (!(imm & 0x38) && cmode == 0xF) {
5002 if (op == 1) return MCDisassembler::Fail;
5003 Inst.setOpcode(ARM::VMOVv4f32);
5004 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
5007 if (!(imm & 0x20)) return MCDisassembler::Fail;
5009 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
5010 return MCDisassembler::Fail;
5011 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
5012 return MCDisassembler::Fail;
5013 Inst.addOperand(MCOperand::CreateImm(64 - imm));
5018 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
5019 uint64_t Address, const void *Decoder) {
5020 DecodeStatus S = MCDisassembler::Success;
5022 unsigned Rn = fieldFromInstruction(Val, 16, 4);
5023 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5024 unsigned Rm = fieldFromInstruction(Val, 0, 4);
5025 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
5026 unsigned Cond = fieldFromInstruction(Val, 28, 4);
5028 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
5029 S = MCDisassembler::SoftFail;
5031 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5032 return MCDisassembler::Fail;
5033 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
5034 return MCDisassembler::Fail;
5035 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
5036 return MCDisassembler::Fail;
5037 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
5038 return MCDisassembler::Fail;
5039 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
5040 return MCDisassembler::Fail;
5045 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
5046 uint64_t Address, const void *Decoder) {
5048 DecodeStatus S = MCDisassembler::Success;
5050 unsigned CRm = fieldFromInstruction(Val, 0, 4);
5051 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
5052 unsigned cop = fieldFromInstruction(Val, 8, 4);
5053 unsigned Rt = fieldFromInstruction(Val, 12, 4);
5054 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
5056 if ((cop & ~0x1) == 0xa)
5057 return MCDisassembler::Fail;
5060 S = MCDisassembler::SoftFail;
5062 Inst.addOperand(MCOperand::CreateImm(cop));
5063 Inst.addOperand(MCOperand::CreateImm(opc1));
5064 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
5065 return MCDisassembler::Fail;
5066 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
5067 return MCDisassembler::Fail;
5068 Inst.addOperand(MCOperand::CreateImm(CRm));