1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARM.h" // FIXME: FACTOR ENUMS BETTER.
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/Support/raw_ostream.h"
24 // Include the auto-generated portion of the assembly writer.
25 #define MachineInstr MCInst
26 #define ARMAsmPrinter ARMInstPrinter // FIXME: REMOVE.
27 #include "ARMGenAsmWriter.inc"
31 static unsigned NextReg(unsigned Reg) {
97 assert(0 && "Unexpected register enum");
101 void ARMInstPrinter::printInst(const MCInst *MI) {
102 // Check for MOVs and print canonical forms, instead.
103 if (MI->getOpcode() == ARM::MOVs) {
104 const MCOperand &Dst = MI->getOperand(0);
105 const MCOperand &MO1 = MI->getOperand(1);
106 const MCOperand &MO2 = MI->getOperand(2);
107 const MCOperand &MO3 = MI->getOperand(3);
109 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
110 printSBitModifierOperand(MI, 6);
111 printPredicateOperand(MI, 4);
113 O << '\t' << getRegisterName(Dst.getReg())
114 << ", " << getRegisterName(MO1.getReg());
116 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
122 O << getRegisterName(MO2.getReg());
123 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
125 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
131 if ((MI->getOpcode() == ARM::STM || MI->getOpcode() == ARM::t2STM_UPD) &&
132 MI->getOperand(0).getReg() == ARM::SP) {
133 const unsigned IdxOffset = MI->getOpcode() == ARM::STM ? 0 : 1;
134 const MCOperand &MO1 = MI->getOperand(IdxOffset + 1);
135 if (ARM_AM::getAM4WBFlag(MO1.getImm()) &&
136 ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
138 printPredicateOperand(MI, IdxOffset + 2);
140 printRegisterList(MI, IdxOffset + 4);
146 if ((MI->getOpcode() == ARM::LDM || MI->getOpcode() == ARM::t2LDM_UPD) &&
147 MI->getOperand(0).getReg() == ARM::SP) {
148 const unsigned IdxOffset = MI->getOpcode() == ARM::LDM ? 0 : 1;
149 const MCOperand &MO1 = MI->getOperand(IdxOffset + 1);
150 if (ARM_AM::getAM4WBFlag(MO1.getImm()) &&
151 ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
153 printPredicateOperand(MI, IdxOffset + 2);
155 printRegisterList(MI, IdxOffset + 4);
161 if ((MI->getOpcode() == ARM::VSTMS || MI->getOpcode() == ARM::VSTMD) &&
162 MI->getOperand(0).getReg() == ARM::SP) {
163 const MCOperand &MO1 = MI->getOperand(1);
164 if (ARM_AM::getAM5WBFlag(MO1.getImm()) &&
165 ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::db) {
166 O << '\t' << "vpush";
167 printPredicateOperand(MI, 2);
169 printRegisterList(MI, 4);
175 if ((MI->getOpcode() == ARM::VLDMS || MI->getOpcode() == ARM::VLDMD) &&
176 MI->getOperand(0).getReg() == ARM::SP) {
177 const MCOperand &MO1 = MI->getOperand(1);
178 if (ARM_AM::getAM5WBFlag(MO1.getImm()) &&
179 ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::ia) {
181 printPredicateOperand(MI, 2);
183 printRegisterList(MI, 4);
188 printInstruction(MI);
191 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
192 const char *Modifier) {
193 const MCOperand &Op = MI->getOperand(OpNo);
195 unsigned Reg = Op.getReg();
196 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
197 O << '{' << getRegisterName(Reg) << ", "
198 << getRegisterName(NextReg(Reg)) << '}';
200 // FIXME: Breaks e.g. ARM/vmul.ll.
203 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
204 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
206 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
209 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
212 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
213 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
214 &ARM::DPR_VFP2RegClass);
215 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
218 O << getRegisterName(Reg);
220 } else if (Op.isImm()) {
221 bool isCallOp = Modifier && !strcmp(Modifier, "call");
223 ((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"));
224 O << '#' << Op.getImm();
226 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
227 assert(Op.isExpr() && "unknown operand kind in printOperand");
232 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
233 const MCAsmInfo *MAI) {
234 // Break it up into two parts that make up a shifter immediate.
235 V = ARM_AM::getSOImmVal(V);
236 assert(V != -1 && "Not a valid so_imm value!");
238 unsigned Imm = ARM_AM::getSOImmValImm(V);
239 unsigned Rot = ARM_AM::getSOImmValRot(V);
241 // Print low-level immediate formation info, per
242 // A5.1.3: "Data-processing operands - Immediate".
244 O << "#" << Imm << ", " << Rot;
245 // Pretty printed version.
247 O << ' ' << MAI->getCommentString()
248 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
255 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
256 /// immediate in bits 0-7.
257 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum) {
258 const MCOperand &MO = MI->getOperand(OpNum);
259 assert(MO.isImm() && "Not a valid so_imm value!");
260 printSOImm(O, MO.getImm(), VerboseAsm, &MAI);
263 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
264 /// followed by an 'orr' to materialize.
265 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum) {
266 // FIXME: REMOVE this method.
270 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
271 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
273 // REG REG 0,SH_OPC - e.g. R5, ROR R3
274 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
275 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum) {
276 const MCOperand &MO1 = MI->getOperand(OpNum);
277 const MCOperand &MO2 = MI->getOperand(OpNum+1);
278 const MCOperand &MO3 = MI->getOperand(OpNum+2);
280 O << getRegisterName(MO1.getReg());
282 // Print the shift opc.
284 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
288 O << getRegisterName(MO2.getReg());
289 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
291 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
296 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op) {
297 const MCOperand &MO1 = MI->getOperand(Op);
298 const MCOperand &MO2 = MI->getOperand(Op+1);
299 const MCOperand &MO3 = MI->getOperand(Op+2);
301 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
302 printOperand(MI, Op);
306 O << "[" << getRegisterName(MO1.getReg());
309 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
311 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
312 << ARM_AM::getAM2Offset(MO3.getImm());
318 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
319 << getRegisterName(MO2.getReg());
321 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
323 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
328 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
330 const MCOperand &MO1 = MI->getOperand(OpNum);
331 const MCOperand &MO2 = MI->getOperand(OpNum+1);
334 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
335 assert(ImmOffs && "Malformed indexed load / store!");
337 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
342 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
343 << getRegisterName(MO1.getReg());
345 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
347 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
351 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum) {
352 const MCOperand &MO1 = MI->getOperand(OpNum);
353 const MCOperand &MO2 = MI->getOperand(OpNum+1);
354 const MCOperand &MO3 = MI->getOperand(OpNum+2);
356 O << '[' << getRegisterName(MO1.getReg());
359 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
360 << getRegisterName(MO2.getReg()) << ']';
364 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
366 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
371 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
373 const MCOperand &MO1 = MI->getOperand(OpNum);
374 const MCOperand &MO2 = MI->getOperand(OpNum+1);
377 O << (char)ARM_AM::getAM3Op(MO2.getImm())
378 << getRegisterName(MO1.getReg());
382 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
383 assert(ImmOffs && "Malformed indexed load / store!");
385 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
390 void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
391 const char *Modifier) {
392 const MCOperand &MO1 = MI->getOperand(OpNum);
393 const MCOperand &MO2 = MI->getOperand(OpNum+1);
394 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
395 if (Modifier && strcmp(Modifier, "submode") == 0) {
396 O << ARM_AM::getAMSubModeStr(Mode);
397 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
398 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
399 if (Mode == ARM_AM::ia)
402 printOperand(MI, OpNum);
403 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
408 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
409 const char *Modifier) {
410 const MCOperand &MO1 = MI->getOperand(OpNum);
411 const MCOperand &MO2 = MI->getOperand(OpNum+1);
413 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
414 printOperand(MI, OpNum);
418 if (Modifier && strcmp(Modifier, "submode") == 0) {
419 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
420 O << ARM_AM::getAMSubModeStr(Mode);
422 } else if (Modifier && strcmp(Modifier, "base") == 0) {
423 // Used for FSTM{D|S} and LSTM{D|S} operations.
424 O << getRegisterName(MO1.getReg());
425 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
430 O << "[" << getRegisterName(MO1.getReg());
432 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
434 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
440 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum) {
441 const MCOperand &MO1 = MI->getOperand(OpNum);
442 const MCOperand &MO2 = MI->getOperand(OpNum+1);
443 const MCOperand &MO3 = MI->getOperand(OpNum+2);
445 // FIXME: No support yet for specifying alignment.
446 O << '[' << getRegisterName(MO1.getReg()) << ']';
448 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
449 if (MO2.getReg() == 0)
452 O << ", " << getRegisterName(MO2.getReg());
456 void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
457 const char *Modifier) {
458 assert(0 && "FIXME: Implement printAddrModePCOperand");
461 void ARMInstPrinter::printBitfieldInvMaskImmOperand (const MCInst *MI,
463 const MCOperand &MO = MI->getOperand(OpNum);
464 uint32_t v = ~MO.getImm();
465 int32_t lsb = CountTrailingZeros_32(v);
466 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
467 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
468 O << '#' << lsb << ", #" << width;
471 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) {
473 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
474 if (i != OpNum) O << ", ";
475 O << getRegisterName(MI->getOperand(i).getReg());
480 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum) {
481 const MCOperand &Op = MI->getOperand(OpNum);
482 unsigned option = Op.getImm();
483 unsigned mode = option & 31;
484 bool changemode = option >> 5 & 1;
485 unsigned AIF = option >> 6 & 7;
486 unsigned imod = option >> 9 & 3;
493 if (AIF & 4) O << 'a';
494 if (AIF & 2) O << 'i';
495 if (AIF & 1) O << 'f';
496 if (AIF > 0 && changemode) O << ", ";
502 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum) {
503 const MCOperand &Op = MI->getOperand(OpNum);
504 unsigned Mask = Op.getImm();
507 if (Mask & 8) O << 'f';
508 if (Mask & 4) O << 's';
509 if (Mask & 2) O << 'x';
510 if (Mask & 1) O << 'c';
514 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum){
515 const MCOperand &Op = MI->getOperand(OpNum);
518 O << '-' << (-Op.getImm() - 1);
523 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum) {
524 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
526 O << ARMCondCodeToString(CC);
529 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
531 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
532 O << ARMCondCodeToString(CC);
535 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum){
536 if (MI->getOperand(OpNum).getReg()) {
537 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
538 "Expect ARM CPSR register!");
545 void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
546 const char *Modifier) {
547 // FIXME: remove this.
551 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum) {
552 O << MI->getOperand(OpNum).getImm();
556 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum) {
557 // FIXME: remove this.
561 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum) {
562 O << "#" << MI->getOperand(OpNum).getImm() * 4;
565 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum) {
566 // (3 - the number of trailing zeros) is the number of then / else.
567 unsigned Mask = MI->getOperand(OpNum).getImm();
568 unsigned CondBit0 = Mask >> 4 & 1;
569 unsigned NumTZ = CountTrailingZeros_32(Mask);
570 assert(NumTZ <= 3 && "Invalid IT mask!");
571 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
572 bool T = ((Mask >> Pos) & 1) == CondBit0;
580 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op)
582 const MCOperand &MO1 = MI->getOperand(Op);
583 const MCOperand &MO2 = MI->getOperand(Op+1);
584 O << "[" << getRegisterName(MO1.getReg());
585 O << ", " << getRegisterName(MO2.getReg()) << "]";
588 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
590 const MCOperand &MO1 = MI->getOperand(Op);
591 const MCOperand &MO2 = MI->getOperand(Op+1);
592 const MCOperand &MO3 = MI->getOperand(Op+2);
594 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
595 printOperand(MI, Op);
599 O << "[" << getRegisterName(MO1.getReg());
601 O << ", " << getRegisterName(MO3.getReg());
602 else if (unsigned ImmOffs = MO2.getImm())
603 O << ", #" << ImmOffs * Scale;
607 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op)
609 printThumbAddrModeRI5Operand(MI, Op, 1);
612 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op)
614 printThumbAddrModeRI5Operand(MI, Op, 2);
617 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op)
619 printThumbAddrModeRI5Operand(MI, Op, 4);
622 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI,unsigned Op) {
623 const MCOperand &MO1 = MI->getOperand(Op);
624 const MCOperand &MO2 = MI->getOperand(Op+1);
625 O << "[" << getRegisterName(MO1.getReg());
626 if (unsigned ImmOffs = MO2.getImm())
627 O << ", #" << ImmOffs*4;
631 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum) {
632 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
633 if (MI->getOpcode() == ARM::t2TBH)
638 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
639 // register with shift forms.
641 // REG IMM, SH_OPC - e.g. R5, LSL #3
642 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum) {
643 const MCOperand &MO1 = MI->getOperand(OpNum);
644 const MCOperand &MO2 = MI->getOperand(OpNum+1);
646 unsigned Reg = MO1.getReg();
647 O << getRegisterName(Reg);
649 // Print the shift opc.
651 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
654 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
655 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
658 void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI,
660 const MCOperand &MO1 = MI->getOperand(OpNum);
661 const MCOperand &MO2 = MI->getOperand(OpNum+1);
663 O << "[" << getRegisterName(MO1.getReg());
665 unsigned OffImm = MO2.getImm();
666 if (OffImm) // Don't print +0.
667 O << ", #" << OffImm;
671 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
673 const MCOperand &MO1 = MI->getOperand(OpNum);
674 const MCOperand &MO2 = MI->getOperand(OpNum+1);
676 O << "[" << getRegisterName(MO1.getReg());
678 int32_t OffImm = (int32_t)MO2.getImm();
681 O << ", #-" << -OffImm;
683 O << ", #" << OffImm;
687 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
689 const MCOperand &MO1 = MI->getOperand(OpNum);
690 const MCOperand &MO2 = MI->getOperand(OpNum+1);
692 O << "[" << getRegisterName(MO1.getReg());
694 int32_t OffImm = (int32_t)MO2.getImm() / 4;
697 O << ", #-" << -OffImm * 4;
699 O << ", #" << OffImm * 4;
703 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
705 const MCOperand &MO1 = MI->getOperand(OpNum);
706 int32_t OffImm = (int32_t)MO1.getImm();
709 O << "#-" << -OffImm;
714 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
716 const MCOperand &MO1 = MI->getOperand(OpNum);
717 int32_t OffImm = (int32_t)MO1.getImm() / 4;
720 O << "#-" << -OffImm * 4;
722 O << "#" << OffImm * 4;
725 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
727 const MCOperand &MO1 = MI->getOperand(OpNum);
728 const MCOperand &MO2 = MI->getOperand(OpNum+1);
729 const MCOperand &MO3 = MI->getOperand(OpNum+2);
731 O << "[" << getRegisterName(MO1.getReg());
733 assert(MO2.getReg() && "Invalid so_reg load / store address!");
734 O << ", " << getRegisterName(MO2.getReg());
736 unsigned ShAmt = MO3.getImm();
738 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
739 O << ", lsl #" << ShAmt;
744 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum) {
745 O << '#' << MI->getOperand(OpNum).getImm();
748 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum) {
749 O << '#' << MI->getOperand(OpNum).getImm();