1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBaseInfo.h"
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the auto-generated portion of the assembly writer.
26 #define MachineInstr MCInst
27 #define ARMAsmPrinter ARMInstPrinter // FIXME: REMOVE.
28 #include "ARMGenAsmWriter.inc"
32 // Get the constituent sub-regs for a dregpair from a Q register.
33 static std::pair<unsigned, unsigned> GetDRegPair(unsigned QReg) {
36 assert(0 && "Unexpected register enum");
37 case ARM::Q0: return std::pair<unsigned, unsigned>(ARM::D0, ARM::D1);
38 case ARM::Q1: return std::pair<unsigned, unsigned>(ARM::D2, ARM::D3);
39 case ARM::Q2: return std::pair<unsigned, unsigned>(ARM::D4, ARM::D5);
40 case ARM::Q3: return std::pair<unsigned, unsigned>(ARM::D6, ARM::D7);
41 case ARM::Q4: return std::pair<unsigned, unsigned>(ARM::D8, ARM::D9);
42 case ARM::Q5: return std::pair<unsigned, unsigned>(ARM::D10, ARM::D11);
43 case ARM::Q6: return std::pair<unsigned, unsigned>(ARM::D12, ARM::D13);
44 case ARM::Q7: return std::pair<unsigned, unsigned>(ARM::D14, ARM::D15);
45 case ARM::Q8: return std::pair<unsigned, unsigned>(ARM::D16, ARM::D17);
46 case ARM::Q9: return std::pair<unsigned, unsigned>(ARM::D18, ARM::D19);
47 case ARM::Q10: return std::pair<unsigned, unsigned>(ARM::D20, ARM::D21);
48 case ARM::Q11: return std::pair<unsigned, unsigned>(ARM::D22, ARM::D23);
49 case ARM::Q12: return std::pair<unsigned, unsigned>(ARM::D24, ARM::D25);
50 case ARM::Q13: return std::pair<unsigned, unsigned>(ARM::D26, ARM::D27);
51 case ARM::Q14: return std::pair<unsigned, unsigned>(ARM::D28, ARM::D29);
52 case ARM::Q15: return std::pair<unsigned, unsigned>(ARM::D30, ARM::D31);
56 static unsigned getDPRSuperRegForSPR(unsigned Reg) {
59 assert(0 && "Unexpected register enum");
60 case ARM::S0: case ARM::S1: return ARM::D0;
61 case ARM::S2: case ARM::S3: return ARM::D1;
62 case ARM::S4: case ARM::S5: return ARM::D2;
63 case ARM::S6: case ARM::S7: return ARM::D3;
64 case ARM::S8: case ARM::S9: return ARM::D4;
65 case ARM::S10: case ARM::S11: return ARM::D5;
66 case ARM::S12: case ARM::S13: return ARM::D6;
67 case ARM::S14: case ARM::S15: return ARM::D7;
68 case ARM::S16: case ARM::S17: return ARM::D8;
69 case ARM::S18: case ARM::S19: return ARM::D9;
70 case ARM::S20: case ARM::S21: return ARM::D10;
71 case ARM::S22: case ARM::S23: return ARM::D11;
72 case ARM::S24: case ARM::S25: return ARM::D12;
73 case ARM::S26: case ARM::S27: return ARM::D13;
74 case ARM::S28: case ARM::S29: return ARM::D14;
75 case ARM::S30: case ARM::S31: return ARM::D15;
79 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
80 // Check for MOVs and print canonical forms, instead.
81 if (MI->getOpcode() == ARM::MOVs) {
82 const MCOperand &Dst = MI->getOperand(0);
83 const MCOperand &MO1 = MI->getOperand(1);
84 const MCOperand &MO2 = MI->getOperand(2);
85 const MCOperand &MO3 = MI->getOperand(3);
87 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
88 printSBitModifierOperand(MI, 6, O);
89 printPredicateOperand(MI, 4, O);
91 O << '\t' << getRegisterName(Dst.getReg())
92 << ", " << getRegisterName(MO1.getReg());
94 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
100 O << getRegisterName(MO2.getReg());
101 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
103 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
109 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
110 MI->getOperand(0).getReg() == ARM::SP) {
111 const MCOperand &MO1 = MI->getOperand(2);
112 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
114 printPredicateOperand(MI, 3, O);
116 printRegisterList(MI, 5, O);
122 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
123 MI->getOperand(0).getReg() == ARM::SP) {
124 const MCOperand &MO1 = MI->getOperand(2);
125 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
127 printPredicateOperand(MI, 3, O);
129 printRegisterList(MI, 5, O);
135 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
136 MI->getOperand(0).getReg() == ARM::SP) {
137 const MCOperand &MO1 = MI->getOperand(2);
138 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
139 O << '\t' << "vpush";
140 printPredicateOperand(MI, 3, O);
142 printRegisterList(MI, 5, O);
148 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
149 MI->getOperand(0).getReg() == ARM::SP) {
150 const MCOperand &MO1 = MI->getOperand(2);
151 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
153 printPredicateOperand(MI, 3, O);
155 printRegisterList(MI, 5, O);
160 printInstruction(MI, O);
163 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
164 raw_ostream &O, const char *Modifier) {
165 const MCOperand &Op = MI->getOperand(OpNo);
167 unsigned Reg = Op.getReg();
168 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
169 std::pair<unsigned, unsigned> dregpair = GetDRegPair(Reg);
170 O << '{' << getRegisterName(dregpair.first) << ", "
171 << getRegisterName(dregpair.second) << '}';
172 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
173 unsigned RegNum = getARMRegisterNumbering(Reg);
174 unsigned DReg = getDPRSuperRegForSPR(Reg);
175 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
177 O << getRegisterName(Reg);
179 } else if (Op.isImm()) {
180 assert((Modifier && !strcmp(Modifier, "call")) ||
181 ((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"));
182 O << '#' << Op.getImm();
184 if (Modifier && Modifier[0] != 0 && strcmp(Modifier, "call") != 0)
185 llvm_unreachable("Unsupported modifier");
186 assert(Op.isExpr() && "unknown operand kind in printOperand");
191 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
192 const MCAsmInfo *MAI) {
193 // Break it up into two parts that make up a shifter immediate.
194 V = ARM_AM::getSOImmVal(V);
195 assert(V != -1 && "Not a valid so_imm value!");
197 unsigned Imm = ARM_AM::getSOImmValImm(V);
198 unsigned Rot = ARM_AM::getSOImmValRot(V);
200 // Print low-level immediate formation info, per
201 // A5.1.3: "Data-processing operands - Immediate".
203 O << "#" << Imm << ", " << Rot;
204 // Pretty printed version.
206 O << ' ' << MAI->getCommentString()
207 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
214 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
215 /// immediate in bits 0-7.
216 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
218 const MCOperand &MO = MI->getOperand(OpNum);
219 assert(MO.isImm() && "Not a valid so_imm value!");
220 printSOImm(O, MO.getImm(), VerboseAsm, &MAI);
223 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
224 /// followed by an 'orr' to materialize.
225 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum,
227 // FIXME: REMOVE this method.
231 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
232 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
234 // REG REG 0,SH_OPC - e.g. R5, ROR R3
235 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
236 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
238 const MCOperand &MO1 = MI->getOperand(OpNum);
239 const MCOperand &MO2 = MI->getOperand(OpNum+1);
240 const MCOperand &MO3 = MI->getOperand(OpNum+2);
242 O << getRegisterName(MO1.getReg());
244 // Print the shift opc.
245 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO3.getImm());
246 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
248 O << ' ' << getRegisterName(MO2.getReg());
249 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
250 } else if (ShOpc != ARM_AM::rrx) {
251 O << " #" << ARM_AM::getSORegOffset(MO3.getImm());
256 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
258 const MCOperand &MO1 = MI->getOperand(Op);
259 const MCOperand &MO2 = MI->getOperand(Op+1);
260 const MCOperand &MO3 = MI->getOperand(Op+2);
262 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
263 printOperand(MI, Op, O);
267 O << "[" << getRegisterName(MO1.getReg());
270 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
272 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
273 << ARM_AM::getAM2Offset(MO3.getImm());
279 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
280 << getRegisterName(MO2.getReg());
282 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
284 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
289 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
292 const MCOperand &MO1 = MI->getOperand(OpNum);
293 const MCOperand &MO2 = MI->getOperand(OpNum+1);
296 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
298 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
303 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
304 << getRegisterName(MO1.getReg());
306 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
308 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
312 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
314 const MCOperand &MO1 = MI->getOperand(OpNum);
315 const MCOperand &MO2 = MI->getOperand(OpNum+1);
316 const MCOperand &MO3 = MI->getOperand(OpNum+2);
318 O << '[' << getRegisterName(MO1.getReg());
321 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
322 << getRegisterName(MO2.getReg()) << ']';
326 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
328 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
333 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
336 const MCOperand &MO1 = MI->getOperand(OpNum);
337 const MCOperand &MO2 = MI->getOperand(OpNum+1);
340 O << (char)ARM_AM::getAM3Op(MO2.getImm())
341 << getRegisterName(MO1.getReg());
345 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
347 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
352 void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
354 const char *Modifier) {
355 const MCOperand &MO2 = MI->getOperand(OpNum+1);
356 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
357 if (Modifier && strcmp(Modifier, "submode") == 0) {
358 O << ARM_AM::getAMSubModeStr(Mode);
359 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
360 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
361 if (Mode == ARM_AM::ia)
364 printOperand(MI, OpNum, O);
368 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
370 const char *Modifier) {
371 const MCOperand &MO1 = MI->getOperand(OpNum);
372 const MCOperand &MO2 = MI->getOperand(OpNum+1);
374 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
375 printOperand(MI, OpNum, O);
379 O << "[" << getRegisterName(MO1.getReg());
381 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
383 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
389 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
391 const MCOperand &MO1 = MI->getOperand(OpNum);
392 const MCOperand &MO2 = MI->getOperand(OpNum+1);
394 O << "[" << getRegisterName(MO1.getReg());
396 // FIXME: Both darwin as and GNU as violate ARM docs here.
397 O << ", :" << (MO2.getImm() << 3);
402 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
405 const MCOperand &MO = MI->getOperand(OpNum);
406 if (MO.getReg() == 0)
409 O << ", " << getRegisterName(MO.getReg());
412 void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
414 const char *Modifier) {
415 assert(0 && "FIXME: Implement printAddrModePCOperand");
418 void ARMInstPrinter::printBitfieldInvMaskImmOperand(const MCInst *MI,
421 const MCOperand &MO = MI->getOperand(OpNum);
422 uint32_t v = ~MO.getImm();
423 int32_t lsb = CountTrailingZeros_32(v);
424 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
425 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
426 O << '#' << lsb << ", #" << width;
429 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
431 unsigned val = MI->getOperand(OpNum).getImm();
432 O << ARM_MB::MemBOptToString(val);
435 void ARMInstPrinter::printShiftImmOperand(const MCInst *MI, unsigned OpNum,
437 unsigned ShiftOp = MI->getOperand(OpNum).getImm();
438 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
440 case ARM_AM::no_shift:
449 assert(0 && "unexpected shift opcode for shift immediate operand");
451 O << ARM_AM::getSORegOffset(ShiftOp);
454 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
457 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
458 if (i != OpNum) O << ", ";
459 O << getRegisterName(MI->getOperand(i).getReg());
464 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
466 const MCOperand &Op = MI->getOperand(OpNum);
467 unsigned option = Op.getImm();
468 unsigned mode = option & 31;
469 bool changemode = option >> 5 & 1;
470 unsigned AIF = option >> 6 & 7;
471 unsigned imod = option >> 9 & 3;
478 if (AIF & 4) O << 'a';
479 if (AIF & 2) O << 'i';
480 if (AIF & 1) O << 'f';
481 if (AIF > 0 && changemode) O << ", ";
487 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
489 const MCOperand &Op = MI->getOperand(OpNum);
490 unsigned Mask = Op.getImm();
493 if (Mask & 8) O << 'f';
494 if (Mask & 4) O << 's';
495 if (Mask & 2) O << 'x';
496 if (Mask & 1) O << 'c';
500 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
502 const MCOperand &Op = MI->getOperand(OpNum);
505 O << '-' << (-Op.getImm() - 1);
510 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
512 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
514 O << ARMCondCodeToString(CC);
517 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
520 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
521 O << ARMCondCodeToString(CC);
524 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
526 if (MI->getOperand(OpNum).getReg()) {
527 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
528 "Expect ARM CPSR register!");
535 void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
537 const char *Modifier) {
538 // FIXME: remove this.
542 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
544 O << MI->getOperand(OpNum).getImm();
548 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
550 // FIXME: remove this.
554 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
556 O << "#" << MI->getOperand(OpNum).getImm() * 4;
559 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
561 // (3 - the number of trailing zeros) is the number of then / else.
562 unsigned Mask = MI->getOperand(OpNum).getImm();
563 unsigned CondBit0 = Mask >> 4 & 1;
564 unsigned NumTZ = CountTrailingZeros_32(Mask);
565 assert(NumTZ <= 3 && "Invalid IT mask!");
566 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
567 bool T = ((Mask >> Pos) & 1) == CondBit0;
575 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
577 const MCOperand &MO1 = MI->getOperand(Op);
578 const MCOperand &MO2 = MI->getOperand(Op+1);
579 O << "[" << getRegisterName(MO1.getReg());
580 O << ", " << getRegisterName(MO2.getReg()) << "]";
583 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
586 const MCOperand &MO1 = MI->getOperand(Op);
587 const MCOperand &MO2 = MI->getOperand(Op+1);
588 const MCOperand &MO3 = MI->getOperand(Op+2);
590 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
591 printOperand(MI, Op, O);
595 O << "[" << getRegisterName(MO1.getReg());
597 O << ", " << getRegisterName(MO3.getReg());
598 else if (unsigned ImmOffs = MO2.getImm())
599 O << ", #" << ImmOffs * Scale;
603 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
605 printThumbAddrModeRI5Operand(MI, Op, O, 1);
608 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
610 printThumbAddrModeRI5Operand(MI, Op, O, 2);
613 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
615 printThumbAddrModeRI5Operand(MI, Op, O, 4);
618 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
620 const MCOperand &MO1 = MI->getOperand(Op);
621 const MCOperand &MO2 = MI->getOperand(Op+1);
622 O << "[" << getRegisterName(MO1.getReg());
623 if (unsigned ImmOffs = MO2.getImm())
624 O << ", #" << ImmOffs*4;
628 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
630 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
631 if (MI->getOpcode() == ARM::t2TBH)
636 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
637 // register with shift forms.
639 // REG IMM, SH_OPC - e.g. R5, LSL #3
640 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
642 const MCOperand &MO1 = MI->getOperand(OpNum);
643 const MCOperand &MO2 = MI->getOperand(OpNum+1);
645 unsigned Reg = MO1.getReg();
646 O << getRegisterName(Reg);
648 // Print the shift opc.
649 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
650 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm());
651 O << ", " << ARM_AM::getShiftOpcStr(ShOpc);
652 if (ShOpc != ARM_AM::rrx)
653 O << " #" << ARM_AM::getSORegOffset(MO2.getImm());
656 void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI,
659 const MCOperand &MO1 = MI->getOperand(OpNum);
660 const MCOperand &MO2 = MI->getOperand(OpNum+1);
662 O << "[" << getRegisterName(MO1.getReg());
664 unsigned OffImm = MO2.getImm();
665 if (OffImm) // Don't print +0.
666 O << ", #" << OffImm;
670 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
673 const MCOperand &MO1 = MI->getOperand(OpNum);
674 const MCOperand &MO2 = MI->getOperand(OpNum+1);
676 O << "[" << getRegisterName(MO1.getReg());
678 int32_t OffImm = (int32_t)MO2.getImm();
681 O << ", #-" << -OffImm;
683 O << ", #" << OffImm;
687 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
690 const MCOperand &MO1 = MI->getOperand(OpNum);
691 const MCOperand &MO2 = MI->getOperand(OpNum+1);
693 O << "[" << getRegisterName(MO1.getReg());
695 int32_t OffImm = (int32_t)MO2.getImm() / 4;
698 O << ", #-" << -OffImm * 4;
700 O << ", #" << OffImm * 4;
704 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
707 const MCOperand &MO1 = MI->getOperand(OpNum);
708 int32_t OffImm = (int32_t)MO1.getImm();
711 O << "#-" << -OffImm;
716 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
719 const MCOperand &MO1 = MI->getOperand(OpNum);
720 int32_t OffImm = (int32_t)MO1.getImm() / 4;
723 O << "#-" << -OffImm * 4;
725 O << "#" << OffImm * 4;
728 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
731 const MCOperand &MO1 = MI->getOperand(OpNum);
732 const MCOperand &MO2 = MI->getOperand(OpNum+1);
733 const MCOperand &MO3 = MI->getOperand(OpNum+2);
735 O << "[" << getRegisterName(MO1.getReg());
737 assert(MO2.getReg() && "Invalid so_reg load / store address!");
738 O << ", " << getRegisterName(MO2.getReg());
740 unsigned ShAmt = MO3.getImm();
742 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
743 O << ", lsl #" << ShAmt;
748 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
750 O << '#' << (float)MI->getOperand(OpNum).getFPImm();
753 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
755 O << '#' << MI->getOperand(OpNum).getFPImm();
758 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
760 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
762 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
763 O << "#0x" << utohexstr(Val);