1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARMInstPrinter.h"
16 #include "ARMAddressingModes.h"
17 #include "llvm/MC/MCInst.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "ARMGenInstrNames.inc"
22 #include "ARMGenRegisterNames.inc"
25 // Include the auto-generated portion of the assembly writer.
26 #define MachineInstr MCInst
27 #define ARMAsmPrinter ARMInstPrinter // FIXME: REMOVE.
28 #define NO_ASM_WRITER_BOILERPLATE
29 #include "ARMGenAsmWriter.inc"
33 void ARMInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
35 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
36 const char *Modifier) {
37 // FIXME: TURN ASSERT ON.
38 //assert((Modifier == 0 || Modifier[0] == 0) && "Cannot print modifiers");
40 const MCOperand &Op = MI->getOperand(OpNo);
42 O << getRegisterName(Op.getReg());
43 } else if (Op.isImm()) {
44 O << '#' << Op.getImm();
46 assert(Op.isExpr() && "unknown operand kind in printOperand");
47 Op.getExpr()->print(O, &MAI);
51 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
52 const MCAsmInfo *MAI) {
53 // Break it up into two parts that make up a shifter immediate.
54 V = ARM_AM::getSOImmVal(V);
55 assert(V != -1 && "Not a valid so_imm value!");
57 unsigned Imm = ARM_AM::getSOImmValImm(V);
58 unsigned Rot = ARM_AM::getSOImmValRot(V);
60 // Print low-level immediate formation info, per
61 // A5.1.3: "Data-processing operands - Immediate".
63 O << "#" << Imm << ", " << Rot;
64 // Pretty printed version.
66 O << ' ' << MAI->getCommentString()
67 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
74 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
75 /// immediate in bits 0-7.
76 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum) {
77 const MCOperand &MO = MI->getOperand(OpNum);
78 assert(MO.isImm() && "Not a valid so_imm value!");
79 printSOImm(O, MO.getImm(), VerboseAsm, &MAI);
82 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
83 /// followed by an 'orr' to materialize.
84 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum) {
85 // FIXME: REMOVE this method.
89 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
90 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
92 // REG REG 0,SH_OPC - e.g. R5, ROR R3
93 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
94 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum) {
95 const MCOperand &MO1 = MI->getOperand(OpNum);
96 const MCOperand &MO2 = MI->getOperand(OpNum+1);
97 const MCOperand &MO3 = MI->getOperand(OpNum+2);
99 O << getRegisterName(MO1.getReg());
101 // Print the shift opc.
103 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
107 O << getRegisterName(MO2.getReg());
108 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
110 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
115 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op) {
116 const MCOperand &MO1 = MI->getOperand(Op);
117 const MCOperand &MO2 = MI->getOperand(Op+1);
118 const MCOperand &MO3 = MI->getOperand(Op+2);
120 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
121 printOperand(MI, Op);
125 O << "[" << getRegisterName(MO1.getReg());
128 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
130 << (char)ARM_AM::getAM2Op(MO3.getImm())
131 << ARM_AM::getAM2Offset(MO3.getImm());
137 << (char)ARM_AM::getAM2Op(MO3.getImm())
138 << getRegisterName(MO2.getReg());
140 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
142 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
148 void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
149 const char *Modifier) {
150 const MCOperand &MO1 = MI->getOperand(OpNum);
151 const MCOperand &MO2 = MI->getOperand(OpNum+1);
152 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
153 if (Modifier && strcmp(Modifier, "submode") == 0) {
154 if (MO1.getReg() == ARM::SP) {
156 bool isLDM = (MI->getOpcode() == ARM::LDM ||
157 MI->getOpcode() == ARM::LDM_RET ||
158 MI->getOpcode() == ARM::t2LDM ||
159 MI->getOpcode() == ARM::t2LDM_RET);
160 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
162 O << ARM_AM::getAMSubModeStr(Mode);
163 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
164 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
165 if (Mode == ARM_AM::ia)
168 printOperand(MI, OpNum);
169 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
174 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) {
176 // Always skip the first operand, it's the optional (and implicit writeback).
177 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
178 if (i != OpNum+1) O << ", ";
179 O << getRegisterName(MI->getOperand(i).getReg());
185 void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
186 const char *Modifier) {
187 // FIXME: remove this.
191 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum) {
192 // FIXME: remove this.