1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARM.h" // FIXME: FACTOR ENUMS BETTER.
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/Support/raw_ostream.h"
24 // Include the auto-generated portion of the assembly writer.
25 #define MachineInstr MCInst
26 #define ARMAsmPrinter ARMInstPrinter // FIXME: REMOVE.
27 #define NO_ASM_WRITER_BOILERPLATE
28 #include "ARMGenAsmWriter.inc"
32 void ARMInstPrinter::printInst(const MCInst *MI) { printInstruction(MI); }
34 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
35 const char *Modifier) {
36 const MCOperand &Op = MI->getOperand(OpNo);
38 unsigned Reg = Op.getReg();
39 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
40 // FIXME: Breaks e.g. ARM/vmul.ll.
43 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
44 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
46 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
48 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
51 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
52 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
53 &ARM::DPR_VFP2RegClass);
54 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
57 O << getRegisterName(Reg);
59 } else if (Op.isImm()) {
60 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
61 O << '#' << Op.getImm();
63 assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
64 assert(Op.isExpr() && "unknown operand kind in printOperand");
69 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
70 const MCAsmInfo *MAI) {
71 // Break it up into two parts that make up a shifter immediate.
72 V = ARM_AM::getSOImmVal(V);
73 assert(V != -1 && "Not a valid so_imm value!");
75 unsigned Imm = ARM_AM::getSOImmValImm(V);
76 unsigned Rot = ARM_AM::getSOImmValRot(V);
78 // Print low-level immediate formation info, per
79 // A5.1.3: "Data-processing operands - Immediate".
81 O << "#" << Imm << ", " << Rot;
82 // Pretty printed version.
84 O << ' ' << MAI->getCommentString()
85 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
92 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
93 /// immediate in bits 0-7.
94 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum) {
95 const MCOperand &MO = MI->getOperand(OpNum);
96 assert(MO.isImm() && "Not a valid so_imm value!");
97 printSOImm(O, MO.getImm(), VerboseAsm, &MAI);
100 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
101 /// followed by an 'orr' to materialize.
102 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum) {
103 // FIXME: REMOVE this method.
107 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
108 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
110 // REG REG 0,SH_OPC - e.g. R5, ROR R3
111 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
112 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum) {
113 const MCOperand &MO1 = MI->getOperand(OpNum);
114 const MCOperand &MO2 = MI->getOperand(OpNum+1);
115 const MCOperand &MO3 = MI->getOperand(OpNum+2);
117 O << getRegisterName(MO1.getReg());
119 // Print the shift opc.
121 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
125 O << getRegisterName(MO2.getReg());
126 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
128 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
133 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op) {
134 const MCOperand &MO1 = MI->getOperand(Op);
135 const MCOperand &MO2 = MI->getOperand(Op+1);
136 const MCOperand &MO3 = MI->getOperand(Op+2);
138 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
139 printOperand(MI, Op);
143 O << "[" << getRegisterName(MO1.getReg());
146 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
148 << (char)ARM_AM::getAM2Op(MO3.getImm())
149 << ARM_AM::getAM2Offset(MO3.getImm());
155 << (char)ARM_AM::getAM2Op(MO3.getImm())
156 << getRegisterName(MO2.getReg());
158 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
160 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
165 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
167 const MCOperand &MO1 = MI->getOperand(OpNum);
168 const MCOperand &MO2 = MI->getOperand(OpNum+1);
171 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
172 assert(ImmOffs && "Malformed indexed load / store!");
173 O << '#' << (char)ARM_AM::getAM2Op(MO2.getImm()) << ImmOffs;
177 O << (char)ARM_AM::getAM2Op(MO2.getImm()) << getRegisterName(MO1.getReg());
179 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
181 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
185 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum) {
186 const MCOperand &MO1 = MI->getOperand(OpNum);
187 const MCOperand &MO2 = MI->getOperand(OpNum+1);
188 const MCOperand &MO3 = MI->getOperand(OpNum+2);
190 O << '[' << getRegisterName(MO1.getReg());
193 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
194 << getRegisterName(MO2.getReg()) << ']';
198 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
200 << (char)ARM_AM::getAM3Op(MO3.getImm())
205 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
207 const MCOperand &MO1 = MI->getOperand(OpNum);
208 const MCOperand &MO2 = MI->getOperand(OpNum+1);
211 O << (char)ARM_AM::getAM3Op(MO2.getImm())
212 << getRegisterName(MO1.getReg());
216 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
217 assert(ImmOffs && "Malformed indexed load / store!");
219 << (char)ARM_AM::getAM3Op(MO2.getImm())
224 void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
225 const char *Modifier) {
226 const MCOperand &MO1 = MI->getOperand(OpNum);
227 const MCOperand &MO2 = MI->getOperand(OpNum+1);
228 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
229 if (Modifier && strcmp(Modifier, "submode") == 0) {
230 if (MO1.getReg() == ARM::SP) {
232 bool isLDM = (MI->getOpcode() == ARM::LDM ||
233 MI->getOpcode() == ARM::LDM_RET ||
234 MI->getOpcode() == ARM::t2LDM ||
235 MI->getOpcode() == ARM::t2LDM_RET);
236 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
238 O << ARM_AM::getAMSubModeStr(Mode);
239 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
240 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
241 if (Mode == ARM_AM::ia)
244 printOperand(MI, OpNum);
245 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
250 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
251 const char *Modifier) {
252 const MCOperand &MO1 = MI->getOperand(OpNum);
253 const MCOperand &MO2 = MI->getOperand(OpNum+1);
255 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
256 printOperand(MI, OpNum);
260 if (Modifier && strcmp(Modifier, "submode") == 0) {
261 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
262 O << ARM_AM::getAMSubModeStr(Mode);
264 } else if (Modifier && strcmp(Modifier, "base") == 0) {
265 // Used for FSTM{D|S} and LSTM{D|S} operations.
266 O << getRegisterName(MO1.getReg());
267 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
272 O << "[" << getRegisterName(MO1.getReg());
274 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
276 << (char)ARM_AM::getAM5Op(MO2.getImm())
282 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum) {
283 const MCOperand &MO1 = MI->getOperand(OpNum);
284 const MCOperand &MO2 = MI->getOperand(OpNum+1);
285 const MCOperand &MO3 = MI->getOperand(OpNum+2);
287 // FIXME: No support yet for specifying alignment.
288 O << '[' << getRegisterName(MO1.getReg()) << ']';
290 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
291 if (MO2.getReg() == 0)
294 O << ", " << getRegisterName(MO2.getReg());
298 void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
299 const char *Modifier) {
300 assert(0 && "FIXME: Implement printAddrModePCOperand");
303 void ARMInstPrinter::printBitfieldInvMaskImmOperand (const MCInst *MI,
305 const MCOperand &MO = MI->getOperand(OpNum);
306 uint32_t v = ~MO.getImm();
307 int32_t lsb = CountTrailingZeros_32(v);
308 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
309 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
310 O << '#' << lsb << ", #" << width;
313 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum) {
315 // Always skip the first operand, it's the optional (and implicit writeback).
316 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
317 if (i != OpNum+1) O << ", ";
318 O << getRegisterName(MI->getOperand(i).getReg());
323 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum) {
324 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
326 O << ARMCondCodeToString(CC);
329 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum){
330 if (MI->getOperand(OpNum).getReg()) {
331 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
332 "Expect ARM CPSR register!");
339 void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
340 const char *Modifier) {
341 // FIXME: remove this.
345 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum) {
346 O << MI->getOperand(OpNum).getImm();
350 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum) {
351 // FIXME: remove this.
355 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum) {
356 // FIXME: remove this.