1 //===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARM.h" // FIXME: FACTOR ENUMS BETTER.
16 #include "ARMInstPrinter.h"
17 #include "ARMAddressingModes.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/Support/raw_ostream.h"
25 // Include the auto-generated portion of the assembly writer.
26 #define MachineInstr MCInst
27 #define ARMAsmPrinter ARMInstPrinter // FIXME: REMOVE.
28 #include "ARMGenAsmWriter.inc"
32 static unsigned NextReg(unsigned Reg) {
35 assert(0 && "Unexpected register enum");
102 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
103 // Check for MOVs and print canonical forms, instead.
104 if (MI->getOpcode() == ARM::MOVs) {
105 const MCOperand &Dst = MI->getOperand(0);
106 const MCOperand &MO1 = MI->getOperand(1);
107 const MCOperand &MO2 = MI->getOperand(2);
108 const MCOperand &MO3 = MI->getOperand(3);
110 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
111 printSBitModifierOperand(MI, 6, O);
112 printPredicateOperand(MI, 4, O);
114 O << '\t' << getRegisterName(Dst.getReg())
115 << ", " << getRegisterName(MO1.getReg());
117 if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
123 O << getRegisterName(MO2.getReg());
124 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
126 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
132 if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
133 MI->getOperand(0).getReg() == ARM::SP) {
134 const MCOperand &MO1 = MI->getOperand(2);
135 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
137 printPredicateOperand(MI, 3, O);
139 printRegisterList(MI, 5, O);
145 if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
146 MI->getOperand(0).getReg() == ARM::SP) {
147 const MCOperand &MO1 = MI->getOperand(2);
148 if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
150 printPredicateOperand(MI, 3, O);
152 printRegisterList(MI, 5, O);
158 if ((MI->getOpcode() == ARM::VSTMS_UPD || MI->getOpcode() ==ARM::VSTMD_UPD) &&
159 MI->getOperand(0).getReg() == ARM::SP) {
160 const MCOperand &MO1 = MI->getOperand(2);
161 if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::db) {
162 O << '\t' << "vpush";
163 printPredicateOperand(MI, 3, O);
165 printRegisterList(MI, 5, O);
171 if ((MI->getOpcode() == ARM::VLDMS_UPD || MI->getOpcode() ==ARM::VLDMD_UPD) &&
172 MI->getOperand(0).getReg() == ARM::SP) {
173 const MCOperand &MO1 = MI->getOperand(2);
174 if (ARM_AM::getAM5SubMode(MO1.getImm()) == ARM_AM::ia) {
176 printPredicateOperand(MI, 3, O);
178 printRegisterList(MI, 5, O);
183 printInstruction(MI, O);
186 void ARMInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
187 raw_ostream &O, const char *Modifier) {
188 const MCOperand &Op = MI->getOperand(OpNo);
190 unsigned Reg = Op.getReg();
191 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
192 O << '{' << getRegisterName(Reg) << ", "
193 << getRegisterName(NextReg(Reg)) << '}';
195 // FIXME: Breaks e.g. ARM/vmul.ll.
198 unsigned DRegLo = TRI->getSubReg(Reg, ARM::dsub_0);
199 unsigned DRegHi = TRI->getSubReg(Reg, ARM::dsub_1);
201 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
204 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
207 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
208 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
209 &ARM::DPR_VFP2RegClass);
210 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
213 O << getRegisterName(Reg);
215 } else if (Op.isImm()) {
216 assert((Modifier && !strcmp(Modifier, "call")) ||
217 ((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported"));
218 O << '#' << Op.getImm();
220 if (Modifier && Modifier[0] != 0 && strcmp(Modifier, "call") != 0)
221 llvm_unreachable("Unsupported modifier");
222 assert(Op.isExpr() && "unknown operand kind in printOperand");
227 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
228 const MCAsmInfo *MAI) {
229 // Break it up into two parts that make up a shifter immediate.
230 V = ARM_AM::getSOImmVal(V);
231 assert(V != -1 && "Not a valid so_imm value!");
233 unsigned Imm = ARM_AM::getSOImmValImm(V);
234 unsigned Rot = ARM_AM::getSOImmValRot(V);
236 // Print low-level immediate formation info, per
237 // A5.1.3: "Data-processing operands - Immediate".
239 O << "#" << Imm << ", " << Rot;
240 // Pretty printed version.
242 O << ' ' << MAI->getCommentString()
243 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
250 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
251 /// immediate in bits 0-7.
252 void ARMInstPrinter::printSOImmOperand(const MCInst *MI, unsigned OpNum,
254 const MCOperand &MO = MI->getOperand(OpNum);
255 assert(MO.isImm() && "Not a valid so_imm value!");
256 printSOImm(O, MO.getImm(), VerboseAsm, &MAI);
259 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
260 /// followed by an 'orr' to materialize.
261 void ARMInstPrinter::printSOImm2PartOperand(const MCInst *MI, unsigned OpNum,
263 // FIXME: REMOVE this method.
267 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
268 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
270 // REG REG 0,SH_OPC - e.g. R5, ROR R3
271 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
272 void ARMInstPrinter::printSORegOperand(const MCInst *MI, unsigned OpNum,
274 const MCOperand &MO1 = MI->getOperand(OpNum);
275 const MCOperand &MO2 = MI->getOperand(OpNum+1);
276 const MCOperand &MO3 = MI->getOperand(OpNum+2);
278 O << getRegisterName(MO1.getReg());
280 // Print the shift opc.
282 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
286 O << getRegisterName(MO2.getReg());
287 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
289 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
294 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
296 const MCOperand &MO1 = MI->getOperand(Op);
297 const MCOperand &MO2 = MI->getOperand(Op+1);
298 const MCOperand &MO3 = MI->getOperand(Op+2);
300 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
301 printOperand(MI, Op, O);
305 O << "[" << getRegisterName(MO1.getReg());
308 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
310 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
311 << ARM_AM::getAM2Offset(MO3.getImm());
317 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
318 << getRegisterName(MO2.getReg());
320 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
322 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
327 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
330 const MCOperand &MO1 = MI->getOperand(OpNum);
331 const MCOperand &MO2 = MI->getOperand(OpNum+1);
334 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
336 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
341 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
342 << getRegisterName(MO1.getReg());
344 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
346 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
350 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
352 const MCOperand &MO1 = MI->getOperand(OpNum);
353 const MCOperand &MO2 = MI->getOperand(OpNum+1);
354 const MCOperand &MO3 = MI->getOperand(OpNum+2);
356 O << '[' << getRegisterName(MO1.getReg());
359 O << ", " << (char)ARM_AM::getAM3Op(MO3.getImm())
360 << getRegisterName(MO2.getReg()) << ']';
364 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
366 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
371 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
374 const MCOperand &MO1 = MI->getOperand(OpNum);
375 const MCOperand &MO2 = MI->getOperand(OpNum+1);
378 O << (char)ARM_AM::getAM3Op(MO2.getImm())
379 << getRegisterName(MO1.getReg());
383 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
385 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
390 void ARMInstPrinter::printAddrMode4Operand(const MCInst *MI, unsigned OpNum,
392 const char *Modifier) {
393 const MCOperand &MO2 = MI->getOperand(OpNum+1);
394 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
395 if (Modifier && strcmp(Modifier, "submode") == 0) {
396 O << ARM_AM::getAMSubModeStr(Mode);
397 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
398 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
399 if (Mode == ARM_AM::ia)
402 printOperand(MI, OpNum, O);
406 void ARMInstPrinter::printAddrMode5Operand(const MCInst *MI, unsigned OpNum,
408 const char *Modifier) {
409 const MCOperand &MO1 = MI->getOperand(OpNum);
410 const MCOperand &MO2 = MI->getOperand(OpNum+1);
412 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
413 printOperand(MI, OpNum, O);
417 if (Modifier && strcmp(Modifier, "submode") == 0) {
418 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
419 O << ARM_AM::getAMSubModeStr(Mode);
421 } else if (Modifier && strcmp(Modifier, "base") == 0) {
422 // Used for FSTM{D|S} and LSTM{D|S} operations.
423 O << getRegisterName(MO1.getReg());
427 O << "[" << getRegisterName(MO1.getReg());
429 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
431 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
437 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
439 const MCOperand &MO1 = MI->getOperand(OpNum);
440 const MCOperand &MO2 = MI->getOperand(OpNum+1);
442 O << "[" << getRegisterName(MO1.getReg());
444 // FIXME: Both darwin as and GNU as violate ARM docs here.
445 O << ", :" << MO2.getImm();
450 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
453 const MCOperand &MO = MI->getOperand(OpNum);
454 if (MO.getReg() == 0)
457 O << ", " << getRegisterName(MO.getReg());
460 void ARMInstPrinter::printAddrModePCOperand(const MCInst *MI, unsigned OpNum,
462 const char *Modifier) {
463 assert(0 && "FIXME: Implement printAddrModePCOperand");
466 void ARMInstPrinter::printBitfieldInvMaskImmOperand (const MCInst *MI,
469 const MCOperand &MO = MI->getOperand(OpNum);
470 uint32_t v = ~MO.getImm();
471 int32_t lsb = CountTrailingZeros_32(v);
472 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
473 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
474 O << '#' << lsb << ", #" << width;
477 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
480 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
481 if (i != OpNum) O << ", ";
482 O << getRegisterName(MI->getOperand(i).getReg());
487 void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum,
489 const MCOperand &Op = MI->getOperand(OpNum);
490 unsigned option = Op.getImm();
491 unsigned mode = option & 31;
492 bool changemode = option >> 5 & 1;
493 unsigned AIF = option >> 6 & 7;
494 unsigned imod = option >> 9 & 3;
501 if (AIF & 4) O << 'a';
502 if (AIF & 2) O << 'i';
503 if (AIF & 1) O << 'f';
504 if (AIF > 0 && changemode) O << ", ";
510 void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum,
512 const MCOperand &Op = MI->getOperand(OpNum);
513 unsigned Mask = Op.getImm();
516 if (Mask & 8) O << 'f';
517 if (Mask & 4) O << 's';
518 if (Mask & 2) O << 'x';
519 if (Mask & 1) O << 'c';
523 void ARMInstPrinter::printNegZeroOperand(const MCInst *MI, unsigned OpNum,
525 const MCOperand &Op = MI->getOperand(OpNum);
528 O << '-' << (-Op.getImm() - 1);
533 void ARMInstPrinter::printPredicateOperand(const MCInst *MI, unsigned OpNum,
535 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
537 O << ARMCondCodeToString(CC);
540 void ARMInstPrinter::printMandatoryPredicateOperand(const MCInst *MI,
543 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
544 O << ARMCondCodeToString(CC);
547 void ARMInstPrinter::printSBitModifierOperand(const MCInst *MI, unsigned OpNum,
549 if (MI->getOperand(OpNum).getReg()) {
550 assert(MI->getOperand(OpNum).getReg() == ARM::CPSR &&
551 "Expect ARM CPSR register!");
558 void ARMInstPrinter::printCPInstOperand(const MCInst *MI, unsigned OpNum,
560 const char *Modifier) {
561 // FIXME: remove this.
565 void ARMInstPrinter::printNoHashImmediate(const MCInst *MI, unsigned OpNum,
567 O << MI->getOperand(OpNum).getImm();
571 void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum,
573 // FIXME: remove this.
577 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
579 O << "#" << MI->getOperand(OpNum).getImm() * 4;
582 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
584 // (3 - the number of trailing zeros) is the number of then / else.
585 unsigned Mask = MI->getOperand(OpNum).getImm();
586 unsigned CondBit0 = Mask >> 4 & 1;
587 unsigned NumTZ = CountTrailingZeros_32(Mask);
588 assert(NumTZ <= 3 && "Invalid IT mask!");
589 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
590 bool T = ((Mask >> Pos) & 1) == CondBit0;
598 void ARMInstPrinter::printThumbAddrModeRROperand(const MCInst *MI, unsigned Op,
600 const MCOperand &MO1 = MI->getOperand(Op);
601 const MCOperand &MO2 = MI->getOperand(Op+1);
602 O << "[" << getRegisterName(MO1.getReg());
603 O << ", " << getRegisterName(MO2.getReg()) << "]";
606 void ARMInstPrinter::printThumbAddrModeRI5Operand(const MCInst *MI, unsigned Op,
609 const MCOperand &MO1 = MI->getOperand(Op);
610 const MCOperand &MO2 = MI->getOperand(Op+1);
611 const MCOperand &MO3 = MI->getOperand(Op+2);
613 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
614 printOperand(MI, Op, O);
618 O << "[" << getRegisterName(MO1.getReg());
620 O << ", " << getRegisterName(MO3.getReg());
621 else if (unsigned ImmOffs = MO2.getImm())
622 O << ", #" << ImmOffs * Scale;
626 void ARMInstPrinter::printThumbAddrModeS1Operand(const MCInst *MI, unsigned Op,
628 printThumbAddrModeRI5Operand(MI, Op, O, 1);
631 void ARMInstPrinter::printThumbAddrModeS2Operand(const MCInst *MI, unsigned Op,
633 printThumbAddrModeRI5Operand(MI, Op, O, 2);
636 void ARMInstPrinter::printThumbAddrModeS4Operand(const MCInst *MI, unsigned Op,
638 printThumbAddrModeRI5Operand(MI, Op, O, 4);
641 void ARMInstPrinter::printThumbAddrModeSPOperand(const MCInst *MI, unsigned Op,
643 const MCOperand &MO1 = MI->getOperand(Op);
644 const MCOperand &MO2 = MI->getOperand(Op+1);
645 O << "[" << getRegisterName(MO1.getReg());
646 if (unsigned ImmOffs = MO2.getImm())
647 O << ", #" << ImmOffs*4;
651 void ARMInstPrinter::printTBAddrMode(const MCInst *MI, unsigned OpNum,
653 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
654 if (MI->getOpcode() == ARM::t2TBH)
659 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
660 // register with shift forms.
662 // REG IMM, SH_OPC - e.g. R5, LSL #3
663 void ARMInstPrinter::printT2SOOperand(const MCInst *MI, unsigned OpNum,
665 const MCOperand &MO1 = MI->getOperand(OpNum);
666 const MCOperand &MO2 = MI->getOperand(OpNum+1);
668 unsigned Reg = MO1.getReg();
669 O << getRegisterName(Reg);
671 // Print the shift opc.
673 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
676 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
677 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
680 void ARMInstPrinter::printT2AddrModeImm12Operand(const MCInst *MI,
683 const MCOperand &MO1 = MI->getOperand(OpNum);
684 const MCOperand &MO2 = MI->getOperand(OpNum+1);
686 O << "[" << getRegisterName(MO1.getReg());
688 unsigned OffImm = MO2.getImm();
689 if (OffImm) // Don't print +0.
690 O << ", #" << OffImm;
694 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
697 const MCOperand &MO1 = MI->getOperand(OpNum);
698 const MCOperand &MO2 = MI->getOperand(OpNum+1);
700 O << "[" << getRegisterName(MO1.getReg());
702 int32_t OffImm = (int32_t)MO2.getImm();
705 O << ", #-" << -OffImm;
707 O << ", #" << OffImm;
711 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
714 const MCOperand &MO1 = MI->getOperand(OpNum);
715 const MCOperand &MO2 = MI->getOperand(OpNum+1);
717 O << "[" << getRegisterName(MO1.getReg());
719 int32_t OffImm = (int32_t)MO2.getImm() / 4;
722 O << ", #-" << -OffImm * 4;
724 O << ", #" << OffImm * 4;
728 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
731 const MCOperand &MO1 = MI->getOperand(OpNum);
732 int32_t OffImm = (int32_t)MO1.getImm();
735 O << "#-" << -OffImm;
740 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
743 const MCOperand &MO1 = MI->getOperand(OpNum);
744 int32_t OffImm = (int32_t)MO1.getImm() / 4;
747 O << "#-" << -OffImm * 4;
749 O << "#" << OffImm * 4;
752 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
755 const MCOperand &MO1 = MI->getOperand(OpNum);
756 const MCOperand &MO2 = MI->getOperand(OpNum+1);
757 const MCOperand &MO3 = MI->getOperand(OpNum+2);
759 O << "[" << getRegisterName(MO1.getReg());
761 assert(MO2.getReg() && "Invalid so_reg load / store address!");
762 O << ", " << getRegisterName(MO2.getReg());
764 unsigned ShAmt = MO3.getImm();
766 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
767 O << ", lsl #" << ShAmt;
772 void ARMInstPrinter::printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum,
774 O << '#' << MI->getOperand(OpNum).getImm();
777 void ARMInstPrinter::printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum,
779 O << '#' << MI->getOperand(OpNum).getImm();
782 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
784 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
786 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
787 O << "#0x" << utohexstr(Val);