1 //===-- ARMAsmPrinter.cpp - ARM LLVM assembly writer ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMAddressingModes.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Module.h"
24 #include "llvm/CodeGen/AsmPrinter.h"
25 #include "llvm/CodeGen/DwarfWriter.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/MC/MCSection.h"
30 #include "llvm/Target/TargetAsmInfo.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetLoweringObjectFile.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Target/TargetRegistry.h"
36 #include "llvm/ADT/SmallPtrSet.h"
37 #include "llvm/ADT/Statistic.h"
38 #include "llvm/ADT/StringSet.h"
39 #include "llvm/Support/Compiler.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/Mangler.h"
42 #include "llvm/Support/MathExtras.h"
43 #include "llvm/Support/FormattedStream.h"
47 STATISTIC(EmittedInsts, "Number of machine instrs printed");
50 class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
53 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
54 /// make the right decision when printing asm code for different targets.
55 const ARMSubtarget *Subtarget;
57 /// AFI - Keep a pointer to ARMFunctionInfo for the current
61 /// MCP - Keep a pointer to constantpool entries of the current
63 const MachineConstantPool *MCP;
65 /// We name each basic block in a Function with a unique number, so
66 /// that we can consistently refer to them later. This is cleared
67 /// at the beginning of each call to runOnMachineFunction().
69 typedef std::map<const Value *, unsigned> ValueMapTy;
70 ValueMapTy NumberForBB;
72 /// GVNonLazyPtrs - Keeps the set of GlobalValues that require
73 /// non-lazy-pointers for indirect access.
74 StringMap<std::string> GVNonLazyPtrs;
76 /// HiddenGVNonLazyPtrs - Keeps the set of GlobalValues with hidden
77 /// visibility that require non-lazy-pointers for indirect access.
78 StringMap<std::string> HiddenGVNonLazyPtrs;
81 std::string Stub, LazyPtr, SLP, SCV;
85 void Init(const GlobalValue *GV, Mangler *Mang) {
86 // Already initialized.
87 if (!Stub.empty()) return;
88 Stub = Mang->getMangledName(GV, "$stub", true);
89 LazyPtr = Mang->getMangledName(GV, "$lazy_ptr", true);
90 SLP = Mang->getMangledName(GV, "$slp", true);
91 SCV = Mang->getMangledName(GV, "$scv", true);
94 void Init(const std::string &GV, Mangler *Mang) {
95 // Already initialized.
96 if (!Stub.empty()) return;
97 Stub = Mang->makeNameProper(GV + "$stub", Mangler::Private);
98 LazyPtr = Mang->makeNameProper(GV + "$lazy_ptr", Mangler::Private);
99 SLP = Mang->makeNameProper(GV + "$slp", Mangler::Private);
100 SCV = Mang->makeNameProper(GV + "$scv", Mangler::Private);
104 /// FnStubs - Keeps the set of external function GlobalAddresses that the
105 /// asm printer should generate stubs for.
106 StringMap<FnStubInfo> FnStubs;
108 /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
111 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
112 const TargetAsmInfo *T, bool V)
113 : AsmPrinter(O, TM, T, V), DW(0), AFI(NULL), MCP(NULL),
115 Subtarget = &TM.getSubtarget<ARMSubtarget>();
118 virtual const char *getPassName() const {
119 return "ARM Assembly Printer";
122 void printOperand(const MachineInstr *MI, int OpNum,
123 const char *Modifier = 0);
124 void printSOImmOperand(const MachineInstr *MI, int OpNum);
125 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
126 void printSORegOperand(const MachineInstr *MI, int OpNum);
127 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
128 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
129 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
130 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
131 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
132 const char *Modifier = 0);
133 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
134 const char *Modifier = 0);
135 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
136 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
137 const char *Modifier = 0);
138 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
140 void printThumbITMask(const MachineInstr *MI, int OpNum);
141 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
142 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
144 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
145 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
146 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
147 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
149 void printT2SOOperand(const MachineInstr *MI, int OpNum);
150 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
151 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
152 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
153 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
154 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
156 void printPredicateOperand(const MachineInstr *MI, int OpNum);
157 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
158 void printPCLabel(const MachineInstr *MI, int OpNum);
159 void printRegisterList(const MachineInstr *MI, int OpNum);
160 void printCPInstOperand(const MachineInstr *MI, int OpNum,
161 const char *Modifier);
162 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
163 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
164 void printTBAddrMode(const MachineInstr *MI, int OpNum);
165 void printLaneOperand(const MachineInstr *MI, int OpNum);
167 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
168 unsigned AsmVariant, const char *ExtraCode);
169 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
171 const char *ExtraCode);
173 void PrintGlobalVariable(const GlobalVariable* GVar);
174 void printInstruction(const MachineInstr *MI); // autogenerated.
175 void printMachineInstruction(const MachineInstr *MI);
176 bool runOnMachineFunction(MachineFunction &F);
177 bool doInitialization(Module &M);
178 bool doFinalization(Module &M);
180 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
182 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
183 printDataDirective(MCPV->getType());
185 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
186 GlobalValue *GV = ACPV->getGV();
190 if (ACPV->isNonLazyPointer()) {
191 std::string SymName = Mang->getMangledName(GV);
192 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
194 if (GV->hasHiddenVisibility())
195 HiddenGVNonLazyPtrs[SymName] = Name;
197 GVNonLazyPtrs[SymName] = Name;
198 } else if (ACPV->isStub()) {
200 FnStubInfo &FnInfo = FnStubs[Mang->getMangledName(GV)];
201 FnInfo.Init(GV, Mang);
204 FnStubInfo &FnInfo = FnStubs[Mang->makeNameProper(ACPV->getSymbol())];
205 FnInfo.Init(ACPV->getSymbol(), Mang);
210 Name = Mang->getMangledName(GV);
212 Name = Mang->makeNameProper(ACPV->getSymbol());
218 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
219 if (ACPV->getPCAdjustment() != 0) {
220 O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
221 << ACPV->getLabelId()
222 << "+" << (unsigned)ACPV->getPCAdjustment();
223 if (ACPV->mustAddCurrentAddress())
230 void getAnalysisUsage(AnalysisUsage &AU) const {
231 AsmPrinter::getAnalysisUsage(AU);
232 AU.setPreservesAll();
233 AU.addRequired<MachineModuleInfo>();
234 AU.addRequired<DwarfWriter>();
237 } // end of anonymous namespace
239 #include "ARMGenAsmWriter.inc"
241 /// runOnMachineFunction - This uses the printInstruction()
242 /// method to print assembly for each instruction.
244 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
247 AFI = MF.getInfo<ARMFunctionInfo>();
248 MCP = MF.getConstantPool();
250 SetupMachineFunction(MF);
253 // NOTE: we don't print out constant pools here, they are handled as
258 // Print out labels for the function.
259 const Function *F = MF.getFunction();
260 SwitchToSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
262 switch (F->getLinkage()) {
263 default: llvm_unreachable("Unknown linkage type!");
264 case Function::PrivateLinkage:
265 case Function::LinkerPrivateLinkage:
266 case Function::InternalLinkage:
268 case Function::ExternalLinkage:
269 O << "\t.globl\t" << CurrentFnName << "\n";
271 case Function::WeakAnyLinkage:
272 case Function::WeakODRLinkage:
273 case Function::LinkOnceAnyLinkage:
274 case Function::LinkOnceODRLinkage:
275 if (Subtarget->isTargetDarwin()) {
276 O << "\t.globl\t" << CurrentFnName << "\n";
277 O << "\t.weak_definition\t" << CurrentFnName << "\n";
279 O << TAI->getWeakRefDirective() << CurrentFnName << "\n";
284 printVisibility(CurrentFnName, F->getVisibility());
286 if (AFI->isThumbFunction()) {
287 EmitAlignment(MF.getAlignment(), F, AFI->getAlign());
288 O << "\t.code\t16\n";
289 O << "\t.thumb_func";
290 if (Subtarget->isTargetDarwin())
291 O << "\t" << CurrentFnName;
295 EmitAlignment(MF.getAlignment(), F);
298 O << CurrentFnName << ":\n";
299 // Emit pre-function debug information.
300 DW->BeginFunction(&MF);
302 if (Subtarget->isTargetDarwin()) {
303 // If the function is empty, then we need to emit *something*. Otherwise,
304 // the function's label might be associated with something that it wasn't
305 // meant to be associated with. We emit a noop in this situation.
306 MachineFunction::iterator I = MF.begin();
308 if (++I == MF.end() && MF.front().empty())
312 // Print out code for the function.
313 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
315 // Print a label for the basic block.
316 if (I != MF.begin()) {
317 printBasicBlockLabel(I, true, true, VerboseAsm);
320 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
322 // Print the assembly for the instruction.
323 printMachineInstruction(II);
327 if (TAI->hasDotTypeDotSizeDirective())
328 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
330 // Emit post-function debug information.
331 DW->EndFunction(&MF);
336 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
337 const char *Modifier) {
338 const MachineOperand &MO = MI->getOperand(OpNum);
339 switch (MO.getType()) {
340 case MachineOperand::MO_Register: {
341 unsigned Reg = MO.getReg();
342 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
343 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
344 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
345 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
347 << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
349 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
350 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
351 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 0 : 1,
353 O << TRI->getAsmName(DReg) << '[' << (RegNum & 1) << ']';
355 O << TRI->getAsmName(Reg);
358 llvm_unreachable("not implemented");
361 case MachineOperand::MO_Immediate: {
362 O << '#' << MO.getImm();
365 case MachineOperand::MO_MachineBasicBlock:
366 printBasicBlockLabel(MO.getMBB());
368 case MachineOperand::MO_GlobalAddress: {
369 bool isCallOp = Modifier && !strcmp(Modifier, "call");
370 GlobalValue *GV = MO.getGlobal();
372 bool isExt = GV->isDeclaration() || GV->isWeakForLinker();
373 if (isExt && isCallOp && Subtarget->isTargetDarwin() &&
374 TM.getRelocationModel() != Reloc::Static) {
375 FnStubInfo &FnInfo = FnStubs[Mang->getMangledName(GV)];
376 FnInfo.Init(GV, Mang);
379 Name = Mang->getMangledName(GV);
384 printOffset(MO.getOffset());
386 if (isCallOp && Subtarget->isTargetELF() &&
387 TM.getRelocationModel() == Reloc::PIC_)
391 case MachineOperand::MO_ExternalSymbol: {
392 bool isCallOp = Modifier && !strcmp(Modifier, "call");
394 if (isCallOp && Subtarget->isTargetDarwin() &&
395 TM.getRelocationModel() != Reloc::Static) {
396 FnStubInfo &FnInfo = FnStubs[Mang->makeNameProper(MO.getSymbolName())];
397 FnInfo.Init(MO.getSymbolName(), Mang);
400 Name = Mang->makeNameProper(MO.getSymbolName());
403 if (isCallOp && Subtarget->isTargetELF() &&
404 TM.getRelocationModel() == Reloc::PIC_)
408 case MachineOperand::MO_ConstantPoolIndex:
409 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
410 << '_' << MO.getIndex();
412 case MachineOperand::MO_JumpTableIndex:
413 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
414 << '_' << MO.getIndex();
417 O << "<unknown operand type>"; abort (); break;
421 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
422 const TargetAsmInfo *TAI) {
423 // Break it up into two parts that make up a shifter immediate.
424 V = ARM_AM::getSOImmVal(V);
425 assert(V != -1 && "Not a valid so_imm value!");
427 unsigned Imm = ARM_AM::getSOImmValImm(V);
428 unsigned Rot = ARM_AM::getSOImmValRot(V);
430 // Print low-level immediate formation info, per
431 // A5.1.3: "Data-processing operands - Immediate".
433 O << "#" << Imm << ", " << Rot;
434 // Pretty printed version.
436 O << ' ' << TAI->getCommentString()
437 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
443 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
444 /// immediate in bits 0-7.
445 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
446 const MachineOperand &MO = MI->getOperand(OpNum);
447 assert(MO.isImm() && "Not a valid so_imm value!");
448 printSOImm(O, MO.getImm(), VerboseAsm, TAI);
451 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
452 /// followed by an 'orr' to materialize.
453 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
454 const MachineOperand &MO = MI->getOperand(OpNum);
455 assert(MO.isImm() && "Not a valid so_imm value!");
456 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
457 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
458 printSOImm(O, V1, VerboseAsm, TAI);
460 printPredicateOperand(MI, 2);
466 printSOImm(O, V2, VerboseAsm, TAI);
469 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
470 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
472 // REG REG 0,SH_OPC - e.g. R5, ROR R3
473 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
474 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
475 const MachineOperand &MO1 = MI->getOperand(Op);
476 const MachineOperand &MO2 = MI->getOperand(Op+1);
477 const MachineOperand &MO3 = MI->getOperand(Op+2);
479 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
480 O << TRI->getAsmName(MO1.getReg());
482 // Print the shift opc.
484 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
488 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
489 O << TRI->getAsmName(MO2.getReg());
490 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
492 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
496 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
497 const MachineOperand &MO1 = MI->getOperand(Op);
498 const MachineOperand &MO2 = MI->getOperand(Op+1);
499 const MachineOperand &MO3 = MI->getOperand(Op+2);
501 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
502 printOperand(MI, Op);
506 O << "[" << TRI->getAsmName(MO1.getReg());
509 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
511 << (char)ARM_AM::getAM2Op(MO3.getImm())
512 << ARM_AM::getAM2Offset(MO3.getImm());
518 << (char)ARM_AM::getAM2Op(MO3.getImm())
519 << TRI->getAsmName(MO2.getReg());
521 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
523 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
528 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
529 const MachineOperand &MO1 = MI->getOperand(Op);
530 const MachineOperand &MO2 = MI->getOperand(Op+1);
533 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
534 assert(ImmOffs && "Malformed indexed load / store!");
536 << (char)ARM_AM::getAM2Op(MO2.getImm())
541 O << (char)ARM_AM::getAM2Op(MO2.getImm())
542 << TRI->getAsmName(MO1.getReg());
544 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
546 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
550 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
551 const MachineOperand &MO1 = MI->getOperand(Op);
552 const MachineOperand &MO2 = MI->getOperand(Op+1);
553 const MachineOperand &MO3 = MI->getOperand(Op+2);
555 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
556 O << "[" << TRI->getAsmName(MO1.getReg());
560 << (char)ARM_AM::getAM3Op(MO3.getImm())
561 << TRI->getAsmName(MO2.getReg())
566 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
568 << (char)ARM_AM::getAM3Op(MO3.getImm())
573 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
574 const MachineOperand &MO1 = MI->getOperand(Op);
575 const MachineOperand &MO2 = MI->getOperand(Op+1);
578 O << (char)ARM_AM::getAM3Op(MO2.getImm())
579 << TRI->getAsmName(MO1.getReg());
583 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
584 assert(ImmOffs && "Malformed indexed load / store!");
586 << (char)ARM_AM::getAM3Op(MO2.getImm())
590 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
591 const char *Modifier) {
592 const MachineOperand &MO1 = MI->getOperand(Op);
593 const MachineOperand &MO2 = MI->getOperand(Op+1);
594 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
595 if (Modifier && strcmp(Modifier, "submode") == 0) {
596 if (MO1.getReg() == ARM::SP) {
598 bool isLDM = (MI->getOpcode() == ARM::LDM ||
599 MI->getOpcode() == ARM::LDM_RET ||
600 MI->getOpcode() == ARM::t2LDM ||
601 MI->getOpcode() == ARM::t2LDM_RET);
602 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
604 O << ARM_AM::getAMSubModeStr(Mode);
605 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
606 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
607 if (Mode == ARM_AM::ia)
610 printOperand(MI, Op);
611 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
616 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
617 const char *Modifier) {
618 const MachineOperand &MO1 = MI->getOperand(Op);
619 const MachineOperand &MO2 = MI->getOperand(Op+1);
621 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
622 printOperand(MI, Op);
626 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
628 if (Modifier && strcmp(Modifier, "submode") == 0) {
629 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
630 if (MO1.getReg() == ARM::SP) {
631 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
632 MI->getOpcode() == ARM::FLDMS);
633 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
635 O << ARM_AM::getAMSubModeStr(Mode);
637 } else if (Modifier && strcmp(Modifier, "base") == 0) {
638 // Used for FSTM{D|S} and LSTM{D|S} operations.
639 O << TRI->getAsmName(MO1.getReg());
640 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
645 O << "[" << TRI->getAsmName(MO1.getReg());
647 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
649 << (char)ARM_AM::getAM5Op(MO2.getImm())
655 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
656 const MachineOperand &MO1 = MI->getOperand(Op);
657 const MachineOperand &MO2 = MI->getOperand(Op+1);
658 const MachineOperand &MO3 = MI->getOperand(Op+2);
660 // FIXME: No support yet for specifying alignment.
661 O << "[" << TRI->getAsmName(MO1.getReg()) << "]";
663 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
664 if (MO2.getReg() == 0)
667 O << ", " << TRI->getAsmName(MO2.getReg());
671 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
672 const char *Modifier) {
673 if (Modifier && strcmp(Modifier, "label") == 0) {
674 printPCLabel(MI, Op+1);
678 const MachineOperand &MO1 = MI->getOperand(Op);
679 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
680 O << "[pc, +" << TRI->getAsmName(MO1.getReg()) << "]";
684 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
685 const MachineOperand &MO = MI->getOperand(Op);
686 uint32_t v = ~MO.getImm();
687 int32_t lsb = CountTrailingZeros_32(v);
688 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
689 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
690 O << "#" << lsb << ", #" << width;
693 //===--------------------------------------------------------------------===//
696 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
697 // (3 - the number of trailing zeros) is the number of then / else.
698 unsigned Mask = MI->getOperand(Op).getImm();
699 unsigned NumTZ = CountTrailingZeros_32(Mask);
700 assert(NumTZ <= 3 && "Invalid IT mask!");
701 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
702 bool T = (Mask & (1 << Pos)) != 0;
711 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
712 const MachineOperand &MO1 = MI->getOperand(Op);
713 const MachineOperand &MO2 = MI->getOperand(Op+1);
714 O << "[" << TRI->getAsmName(MO1.getReg());
715 O << ", " << TRI->getAsmName(MO2.getReg()) << "]";
719 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
721 const MachineOperand &MO1 = MI->getOperand(Op);
722 const MachineOperand &MO2 = MI->getOperand(Op+1);
723 const MachineOperand &MO3 = MI->getOperand(Op+2);
725 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
726 printOperand(MI, Op);
730 O << "[" << TRI->getAsmName(MO1.getReg());
732 O << ", " << TRI->getAsmName(MO3.getReg());
733 else if (unsigned ImmOffs = MO2.getImm()) {
734 O << ", #" << ImmOffs;
742 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
743 printThumbAddrModeRI5Operand(MI, Op, 1);
746 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
747 printThumbAddrModeRI5Operand(MI, Op, 2);
750 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
751 printThumbAddrModeRI5Operand(MI, Op, 4);
754 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
755 const MachineOperand &MO1 = MI->getOperand(Op);
756 const MachineOperand &MO2 = MI->getOperand(Op+1);
757 O << "[" << TRI->getAsmName(MO1.getReg());
758 if (unsigned ImmOffs = MO2.getImm())
759 O << ", #" << ImmOffs << " * 4";
763 //===--------------------------------------------------------------------===//
765 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
766 // register with shift forms.
768 // REG IMM, SH_OPC - e.g. R5, LSL #3
769 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
770 const MachineOperand &MO1 = MI->getOperand(OpNum);
771 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
773 unsigned Reg = MO1.getReg();
774 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
775 O << TRI->getAsmName(Reg);
777 // Print the shift opc.
779 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
782 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
783 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
786 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
788 const MachineOperand &MO1 = MI->getOperand(OpNum);
789 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
791 O << "[" << TRI->getAsmName(MO1.getReg());
793 unsigned OffImm = MO2.getImm();
794 if (OffImm) // Don't print +0.
795 O << ", #+" << OffImm;
799 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
801 const MachineOperand &MO1 = MI->getOperand(OpNum);
802 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
804 O << "[" << TRI->getAsmName(MO1.getReg());
806 int32_t OffImm = (int32_t)MO2.getImm();
809 O << ", #-" << -OffImm;
811 O << ", #+" << OffImm;
815 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
817 const MachineOperand &MO1 = MI->getOperand(OpNum);
818 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
820 O << "[" << TRI->getAsmName(MO1.getReg());
822 int32_t OffImm = (int32_t)MO2.getImm() / 4;
825 O << ", #-" << -OffImm << " * 4";
827 O << ", #+" << OffImm << " * 4";
831 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
833 const MachineOperand &MO1 = MI->getOperand(OpNum);
834 int32_t OffImm = (int32_t)MO1.getImm();
837 O << "#-" << -OffImm;
842 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
844 const MachineOperand &MO1 = MI->getOperand(OpNum);
845 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
846 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
848 O << "[" << TRI->getAsmName(MO1.getReg());
851 O << ", +" << TRI->getAsmName(MO2.getReg());
853 unsigned ShAmt = MO3.getImm();
855 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
856 O << ", lsl #" << ShAmt;
863 //===--------------------------------------------------------------------===//
865 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
866 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
868 O << ARMCondCodeToString(CC);
871 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
872 unsigned Reg = MI->getOperand(OpNum).getReg();
874 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
879 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
880 int Id = (int)MI->getOperand(OpNum).getImm();
881 O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
884 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
886 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
888 if (i != e-1) O << ", ";
893 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
894 const char *Modifier) {
895 assert(Modifier && "This operand only works with a modifier!");
896 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
898 if (!strcmp(Modifier, "label")) {
899 unsigned ID = MI->getOperand(OpNum).getImm();
900 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
901 << '_' << ID << ":\n";
903 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
904 unsigned CPI = MI->getOperand(OpNum).getIndex();
906 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
908 if (MCPE.isMachineConstantPoolEntry()) {
909 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
911 EmitGlobalConstant(MCPE.Val.ConstVal);
916 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
917 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
919 const MachineOperand &MO1 = MI->getOperand(OpNum);
920 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
921 unsigned JTI = MO1.getIndex();
922 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
923 << '_' << JTI << '_' << MO2.getImm() << ":\n";
925 const char *JTEntryDirective = TAI->getJumpTableDirective();
926 if (!JTEntryDirective)
927 JTEntryDirective = TAI->getData32bitsDirective();
929 const MachineFunction *MF = MI->getParent()->getParent();
930 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
931 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
932 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
933 bool UseSet= TAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
934 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
935 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
936 MachineBasicBlock *MBB = JTBBs[i];
937 bool isNew = JTSets.insert(MBB);
940 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
942 O << JTEntryDirective << ' ';
944 O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
945 << '_' << JTI << '_' << MO2.getImm()
946 << "_set_" << MBB->getNumber();
947 else if (TM.getRelocationModel() == Reloc::PIC_) {
948 printBasicBlockLabel(MBB, false, false, false);
949 // If the arch uses custom Jump Table directives, don't calc relative to JT
950 if (!TAI->getJumpTableDirective())
951 O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
952 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
954 printBasicBlockLabel(MBB, false, false, false);
961 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
962 const MachineOperand &MO1 = MI->getOperand(OpNum);
963 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
964 unsigned JTI = MO1.getIndex();
965 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
966 << '_' << JTI << '_' << MO2.getImm() << ":\n";
968 const MachineFunction *MF = MI->getParent()->getParent();
969 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
970 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
971 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
972 bool ByteOffset = false, HalfWordOffset = false;
973 if (MI->getOpcode() == ARM::t2TBB)
975 else if (MI->getOpcode() == ARM::t2TBH)
976 HalfWordOffset = true;
978 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
979 MachineBasicBlock *MBB = JTBBs[i];
981 O << TAI->getData8bitsDirective();
982 else if (HalfWordOffset)
983 O << TAI->getData16bitsDirective();
984 if (ByteOffset || HalfWordOffset) {
986 printBasicBlockLabel(MBB, false, false, false);
987 O << "-" << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
988 << '_' << JTI << '_' << MO2.getImm() << ")/2";
991 printBasicBlockLabel(MBB, false, false, false);
997 // Make sure the instruction that follows TBB is 2-byte aligned.
998 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
999 if (ByteOffset && (JTBBs.size() & 1)) {
1005 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
1006 O << "[pc, " << TRI->getAsmName(MI->getOperand(OpNum).getReg());
1007 if (MI->getOpcode() == ARM::t2TBH)
1012 void ARMAsmPrinter::printLaneOperand(const MachineInstr *MI, int OpNum) {
1013 O << MI->getOperand(OpNum).getImm();
1016 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1017 unsigned AsmVariant, const char *ExtraCode){
1018 // Does this asm operand have a single letter operand modifier?
1019 if (ExtraCode && ExtraCode[0]) {
1020 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1022 switch (ExtraCode[0]) {
1023 default: return true; // Unknown modifier.
1024 case 'a': // Print as a memory address.
1025 if (MI->getOperand(OpNum).isReg()) {
1026 O << "[" << TRI->getAsmName(MI->getOperand(OpNum).getReg()) << "]";
1030 case 'c': // Don't print "#" before an immediate operand.
1031 printLaneOperand(MI, OpNum);
1033 case 'P': // Print a VFP double precision register.
1034 printOperand(MI, OpNum);
1037 if (TM.getTargetData()->isLittleEndian())
1041 if (TM.getTargetData()->isBigEndian())
1044 case 'H': // Write second word of DI / DF reference.
1045 // Verify that this operand has two consecutive registers.
1046 if (!MI->getOperand(OpNum).isReg() ||
1047 OpNum+1 == MI->getNumOperands() ||
1048 !MI->getOperand(OpNum+1).isReg())
1050 ++OpNum; // Return the high-part.
1054 printOperand(MI, OpNum);
1058 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1059 unsigned OpNum, unsigned AsmVariant,
1060 const char *ExtraCode) {
1061 if (ExtraCode && ExtraCode[0])
1062 return true; // Unknown modifier.
1063 printAddrMode2Operand(MI, OpNum);
1067 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1070 int Opc = MI->getOpcode();
1072 case ARM::CONSTPOOL_ENTRY:
1073 if (!InCPMode && AFI->isThumbFunction()) {
1079 if (InCPMode && AFI->isThumbFunction())
1083 // Call the autogenerated instruction printer routines.
1084 printInstruction(MI);
1087 bool ARMAsmPrinter::doInitialization(Module &M) {
1089 bool Result = AsmPrinter::doInitialization(M);
1090 DW = getAnalysisIfAvailable<DwarfWriter>();
1092 // Use unified assembler syntax mode for Thumb.
1093 if (Subtarget->isThumb())
1094 O << "\t.syntax unified\n";
1096 // Emit ARM Build Attributes
1097 if (Subtarget->isTargetELF()) {
1099 std::string CPUString = Subtarget->getCPUString();
1100 if (CPUString != "generic")
1101 O << "\t.cpu " << CPUString << '\n';
1103 // FIXME: Emit FPU type
1104 if (Subtarget->hasVFP2())
1105 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1107 // Signal various FP modes.
1109 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1110 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1112 if (FiniteOnlyFPMath())
1113 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1115 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1117 // 8-bytes alignment stuff.
1118 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1119 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1121 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1122 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1123 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1124 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1126 // FIXME: Should we signal R9 usage?
1132 /// PrintUnmangledNameSafely - Print out the printable characters in the name.
1133 /// Don't print things like \\n or \\0.
1134 static void PrintUnmangledNameSafely(const Value *V,
1135 formatted_raw_ostream &OS) {
1136 for (StringRef::iterator it = V->getName().begin(),
1137 ie = V->getName().end(); it != ie; ++it)
1142 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1143 const TargetData *TD = TM.getTargetData();
1145 if (!GVar->hasInitializer()) // External global require no code
1148 // Check to see if this is a special global used by LLVM, if so, emit it.
1150 if (EmitSpecialLLVMGlobal(GVar)) {
1151 if (Subtarget->isTargetDarwin() &&
1152 TM.getRelocationModel() == Reloc::Static) {
1153 if (GVar->getName() == "llvm.global_ctors")
1154 O << ".reference .constructors_used\n";
1155 else if (GVar->getName() == "llvm.global_dtors")
1156 O << ".reference .destructors_used\n";
1161 std::string name = Mang->getMangledName(GVar);
1162 Constant *C = GVar->getInitializer();
1163 const Type *Type = C->getType();
1164 unsigned Size = TD->getTypeAllocSize(Type);
1165 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1166 bool isDarwin = Subtarget->isTargetDarwin();
1168 printVisibility(name, GVar->getVisibility());
1170 if (Subtarget->isTargetELF())
1171 O << "\t.type " << name << ",%object\n";
1173 const MCSection *TheSection =
1174 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1175 SwitchToSection(TheSection);
1177 // FIXME: get this stuff from section kind flags.
1178 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1179 // Don't put things that should go in the cstring section into "comm".
1180 !TheSection->getKind().isMergeableCString()) {
1181 if (GVar->hasExternalLinkage()) {
1182 if (const char *Directive = TAI->getZeroFillDirective()) {
1183 O << "\t.globl\t" << name << "\n";
1184 O << Directive << "__DATA, __common, " << name << ", "
1185 << Size << ", " << Align << "\n";
1190 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1191 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1194 if (GVar->hasLocalLinkage()) {
1195 O << TAI->getLCOMMDirective() << name << "," << Size
1197 } else if (GVar->hasCommonLinkage()) {
1198 O << TAI->getCOMMDirective() << name << "," << Size
1201 SwitchToSection(getObjFileLowering().SectionForGlobal(GVar, Mang,TM));
1202 O << "\t.globl " << name << '\n'
1203 << TAI->getWeakDefDirective() << name << '\n';
1204 EmitAlignment(Align, GVar);
1207 O << "\t\t\t\t" << TAI->getCommentString() << ' ';
1208 PrintUnmangledNameSafely(GVar, O);
1211 EmitGlobalConstant(C);
1214 } else if (TAI->getLCOMMDirective() != NULL) {
1215 if (GVar->hasLocalLinkage()) {
1216 O << TAI->getLCOMMDirective() << name << "," << Size;
1218 O << TAI->getCOMMDirective() << name << "," << Size;
1219 if (TAI->getCOMMDirectiveTakesAlignment())
1220 O << ',' << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1223 if (GVar->hasLocalLinkage())
1224 O << "\t.local\t" << name << "\n";
1225 O << TAI->getCOMMDirective() << name << "," << Size;
1226 if (TAI->getCOMMDirectiveTakesAlignment())
1227 O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1230 O << "\t\t" << TAI->getCommentString() << " ";
1231 PrintUnmangledNameSafely(GVar, O);
1238 switch (GVar->getLinkage()) {
1239 case GlobalValue::CommonLinkage:
1240 case GlobalValue::LinkOnceAnyLinkage:
1241 case GlobalValue::LinkOnceODRLinkage:
1242 case GlobalValue::WeakAnyLinkage:
1243 case GlobalValue::WeakODRLinkage:
1245 O << "\t.globl " << name << "\n"
1246 << "\t.weak_definition " << name << "\n";
1248 O << "\t.weak " << name << "\n";
1251 case GlobalValue::AppendingLinkage:
1252 // FIXME: appending linkage variables should go into a section of
1253 // their name or something. For now, just emit them as external.
1254 case GlobalValue::ExternalLinkage:
1255 O << "\t.globl " << name << "\n";
1257 case GlobalValue::PrivateLinkage:
1258 case GlobalValue::LinkerPrivateLinkage:
1259 case GlobalValue::InternalLinkage:
1262 llvm_unreachable("Unknown linkage type!");
1265 EmitAlignment(Align, GVar);
1268 O << "\t\t\t\t" << TAI->getCommentString() << " ";
1269 PrintUnmangledNameSafely(GVar, O);
1272 if (TAI->hasDotTypeDotSizeDirective())
1273 O << "\t.size " << name << ", " << Size << "\n";
1275 EmitGlobalConstant(C);
1280 bool ARMAsmPrinter::doFinalization(Module &M) {
1281 if (Subtarget->isTargetDarwin()) {
1282 // All darwin targets use mach-o.
1283 TargetLoweringObjectFileMachO &TLOFMacho =
1284 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1288 if (!FnStubs.empty()) {
1289 unsigned StubSize = 12;
1290 const char *StubSectionName = "__symbol_stub4";
1292 if (TM.getRelocationModel() == Reloc::PIC_) {
1294 StubSectionName = "__picsymbolstub4";
1297 const MCSection *StubSection
1298 = TLOFMacho.getMachOSection("__TEXT", StubSectionName,
1299 MCSectionMachO::S_SYMBOL_STUBS,
1300 StubSize, SectionKind::getText());
1302 const MCSection *LazySymbolPointerSection
1303 = TLOFMacho.getLazySymbolPointerSection();
1305 // Output stubs for dynamically-linked functions
1306 for (StringMap<FnStubInfo>::iterator I = FnStubs.begin(),
1307 E = FnStubs.end(); I != E; ++I) {
1308 const FnStubInfo &Info = I->second;
1310 SwitchToSection(StubSection);
1312 O << "\t.code\t32\n";
1314 O << Info.Stub << ":\n";
1315 O << "\t.indirect_symbol " << I->getKeyData() << '\n';
1316 O << "\tldr ip, " << Info.SLP << '\n';
1317 if (TM.getRelocationModel() == Reloc::PIC_) {
1318 O << Info.SCV << ":\n";
1319 O << "\tadd ip, pc, ip\n";
1321 O << "\tldr pc, [ip, #0]\n";
1322 O << Info.SLP << ":\n";
1323 O << "\t.long\t" << Info.LazyPtr;
1324 if (TM.getRelocationModel() == Reloc::PIC_)
1325 O << "-(" << Info.SCV << "+8)";
1328 SwitchToSection(LazySymbolPointerSection);
1329 O << Info.LazyPtr << ":\n";
1330 O << "\t.indirect_symbol " << I->getKeyData() << "\n";
1331 O << "\t.long\tdyld_stub_binding_helper\n";
1336 // Output non-lazy-pointers for external and common global variables.
1337 if (!GVNonLazyPtrs.empty()) {
1338 // Switch with ".non_lazy_symbol_pointer" directive.
1339 SwitchToSection(TLOFMacho.getNonLazySymbolPointerSection());
1340 for (StringMap<std::string>::iterator I = GVNonLazyPtrs.begin(),
1341 E = GVNonLazyPtrs.end(); I != E; ++I) {
1342 O << I->second << ":\n";
1343 O << "\t.indirect_symbol " << I->getKeyData() << "\n";
1344 O << "\t.long\t0\n";
1348 if (!HiddenGVNonLazyPtrs.empty()) {
1349 SwitchToSection(getObjFileLowering().getDataSection());
1350 for (StringMap<std::string>::iterator I = HiddenGVNonLazyPtrs.begin(),
1351 E = HiddenGVNonLazyPtrs.end(); I != E; ++I) {
1353 O << I->second << ":\n";
1354 O << "\t.long " << I->getKeyData() << "\n";
1359 // Funny Darwin hack: This flag tells the linker that no global symbols
1360 // contain code that falls through to other global symbols (e.g. the obvious
1361 // implementation of multiple entry points). If this doesn't occur, the
1362 // linker can safely perform dead code stripping. Since LLVM never
1363 // generates code that does this, it is always safe to set.
1364 O << "\t.subsections_via_symbols\n";
1367 return AsmPrinter::doFinalization(M);
1370 // Force static initialization.
1371 extern "C" void LLVMInitializeARMAsmPrinter() {
1372 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1373 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);