1 //===-- ARMAsmPrinter.cpp - ARM LLVM assembly writer ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMTargetMachine.h"
19 #include "ARMAddressingModes.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Module.h"
24 #include "llvm/MDNode.h"
25 #include "llvm/CodeGen/AsmPrinter.h"
26 #include "llvm/CodeGen/DwarfWriter.h"
27 #include "llvm/CodeGen/MachineModuleInfo.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/Target/TargetAsmInfo.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetMachine.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/ADT/Statistic.h"
35 #include "llvm/ADT/StringExtras.h"
36 #include "llvm/ADT/StringSet.h"
37 #include "llvm/Support/Compiler.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/Mangler.h"
40 #include "llvm/Support/MathExtras.h"
41 #include "llvm/Support/raw_ostream.h"
45 STATISTIC(EmittedInsts, "Number of machine instrs printed");
48 class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
51 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
52 /// make the right decision when printing asm code for different targets.
53 const ARMSubtarget *Subtarget;
55 /// AFI - Keep a pointer to ARMFunctionInfo for the current
59 /// MCP - Keep a pointer to constantpool entries of the current
61 const MachineConstantPool *MCP;
63 /// We name each basic block in a Function with a unique number, so
64 /// that we can consistently refer to them later. This is cleared
65 /// at the beginning of each call to runOnMachineFunction().
67 typedef std::map<const Value *, unsigned> ValueMapTy;
68 ValueMapTy NumberForBB;
70 /// GVNonLazyPtrs - Keeps the set of GlobalValues that require
71 /// non-lazy-pointers for indirect access.
72 StringSet<> GVNonLazyPtrs;
74 /// HiddenGVNonLazyPtrs - Keeps the set of GlobalValues with hidden
75 /// visibility that require non-lazy-pointers for indirect access.
76 StringSet<> HiddenGVNonLazyPtrs;
78 /// FnStubs - Keeps the set of external function GlobalAddresses that the
79 /// asm printer should generate stubs for.
82 /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
85 explicit ARMAsmPrinter(raw_ostream &O, TargetMachine &TM,
86 const TargetAsmInfo *T, bool V)
87 : AsmPrinter(O, TM, T, V), DW(0), AFI(NULL), MCP(NULL),
89 Subtarget = &TM.getSubtarget<ARMSubtarget>();
92 virtual const char *getPassName() const {
93 return "ARM Assembly Printer";
96 void printOperand(const MachineInstr *MI, int OpNum,
97 const char *Modifier = 0);
98 void printSOImmOperand(const MachineInstr *MI, int OpNum);
99 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
100 void printSORegOperand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
102 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
104 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
105 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
106 const char *Modifier = 0);
107 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
108 const char *Modifier = 0);
109 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
110 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
111 const char *Modifier = 0);
112 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
117 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
122 void printT2SOOperand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
129 void printPredicateOperand(const MachineInstr *MI, int OpNum);
130 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
131 void printPCLabel(const MachineInstr *MI, int OpNum);
132 void printRegisterList(const MachineInstr *MI, int OpNum);
133 void printCPInstOperand(const MachineInstr *MI, int OpNum,
134 const char *Modifier);
135 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
137 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
138 unsigned AsmVariant, const char *ExtraCode);
139 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
141 const char *ExtraCode);
143 void printModuleLevelGV(const GlobalVariable* GVar);
144 bool printInstruction(const MachineInstr *MI); // autogenerated.
145 void printMachineInstruction(const MachineInstr *MI);
146 bool runOnMachineFunction(MachineFunction &F);
147 bool doInitialization(Module &M);
148 bool doFinalization(Module &M);
150 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
152 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
153 printDataDirective(MCPV->getType());
155 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
156 GlobalValue *GV = ACPV->getGV();
157 std::string Name = GV ? Mang->getValueName(GV) : TAI->getGlobalPrefix();
159 Name += ACPV->getSymbol();
160 if (ACPV->isNonLazyPointer()) {
161 if (GV->hasHiddenVisibility())
162 HiddenGVNonLazyPtrs.insert(Name);
164 GVNonLazyPtrs.insert(Name);
165 printSuffixedName(Name, "$non_lazy_ptr");
166 } else if (ACPV->isStub()) {
167 FnStubs.insert(Name);
168 printSuffixedName(Name, "$stub");
171 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
172 if (ACPV->getPCAdjustment() != 0) {
173 O << "-(" << TAI->getPrivateGlobalPrefix() << "PC"
174 << utostr(ACPV->getLabelId())
175 << "+" << (unsigned)ACPV->getPCAdjustment();
176 if (ACPV->mustAddCurrentAddress())
183 void getAnalysisUsage(AnalysisUsage &AU) const {
184 AsmPrinter::getAnalysisUsage(AU);
185 AU.setPreservesAll();
186 AU.addRequired<MachineModuleInfo>();
187 AU.addRequired<DwarfWriter>();
190 } // end of anonymous namespace
192 #include "ARMGenAsmWriter.inc"
194 /// runOnMachineFunction - This uses the printInstruction()
195 /// method to print assembly for each instruction.
197 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
200 AFI = MF.getInfo<ARMFunctionInfo>();
201 MCP = MF.getConstantPool();
203 SetupMachineFunction(MF);
206 // NOTE: we don't print out constant pools here, they are handled as
210 // Print out labels for the function.
211 const Function *F = MF.getFunction();
212 switch (F->getLinkage()) {
213 default: LLVM_UNREACHABLE("Unknown linkage type!");
214 case Function::PrivateLinkage:
215 case Function::InternalLinkage:
216 SwitchToTextSection("\t.text", F);
218 case Function::ExternalLinkage:
219 SwitchToTextSection("\t.text", F);
220 O << "\t.globl\t" << CurrentFnName << "\n";
222 case Function::WeakAnyLinkage:
223 case Function::WeakODRLinkage:
224 case Function::LinkOnceAnyLinkage:
225 case Function::LinkOnceODRLinkage:
226 if (Subtarget->isTargetDarwin()) {
228 ".section __TEXT,__textcoal_nt,coalesced,pure_instructions", F);
229 O << "\t.globl\t" << CurrentFnName << "\n";
230 O << "\t.weak_definition\t" << CurrentFnName << "\n";
232 O << TAI->getWeakRefDirective() << CurrentFnName << "\n";
237 printVisibility(CurrentFnName, F->getVisibility());
239 if (AFI->isThumbFunction()) {
240 EmitAlignment(MF.getAlignment(), F, AFI->getAlign());
241 O << "\t.code\t16\n";
242 O << "\t.thumb_func";
243 if (Subtarget->isTargetDarwin())
244 O << "\t" << CurrentFnName;
248 EmitAlignment(MF.getAlignment(), F);
251 O << CurrentFnName << ":\n";
252 // Emit pre-function debug information.
253 DW->BeginFunction(&MF);
255 if (Subtarget->isTargetDarwin()) {
256 // If the function is empty, then we need to emit *something*. Otherwise,
257 // the function's label might be associated with something that it wasn't
258 // meant to be associated with. We emit a noop in this situation.
259 MachineFunction::iterator I = MF.begin();
261 if (++I == MF.end() && MF.front().empty())
265 // Print out code for the function.
266 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
268 // Print a label for the basic block.
269 if (I != MF.begin()) {
270 printBasicBlockLabel(I, true, true, VerboseAsm);
273 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
275 // Print the assembly for the instruction.
276 printMachineInstruction(II);
280 if (TAI->hasDotTypeDotSizeDirective())
281 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
283 // Emit post-function debug information.
284 DW->EndFunction(&MF);
291 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
292 const char *Modifier) {
293 const MachineOperand &MO = MI->getOperand(OpNum);
294 switch (MO.getType()) {
295 case MachineOperand::MO_Register: {
296 unsigned Reg = MO.getReg();
297 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
298 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
299 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
300 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
302 << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
304 } else if (Modifier && strcmp(Modifier, "dregsingle") == 0) {
305 O << '{' << TRI->getAsmName(Reg) << '}';
307 O << TRI->getAsmName(Reg);
310 LLVM_UNREACHABLE("not implemented");
313 case MachineOperand::MO_Immediate: {
314 if (!Modifier || strcmp(Modifier, "no_hash") != 0)
320 case MachineOperand::MO_MachineBasicBlock:
321 printBasicBlockLabel(MO.getMBB());
323 case MachineOperand::MO_GlobalAddress: {
324 bool isCallOp = Modifier && !strcmp(Modifier, "call");
325 GlobalValue *GV = MO.getGlobal();
326 std::string Name = Mang->getValueName(GV);
327 bool isExt = (GV->isDeclaration() || GV->hasWeakLinkage() ||
328 GV->hasLinkOnceLinkage());
329 if (isExt && isCallOp && Subtarget->isTargetDarwin() &&
330 TM.getRelocationModel() != Reloc::Static) {
331 printSuffixedName(Name, "$stub");
332 FnStubs.insert(Name);
336 printOffset(MO.getOffset());
338 if (isCallOp && Subtarget->isTargetELF() &&
339 TM.getRelocationModel() == Reloc::PIC_)
343 case MachineOperand::MO_ExternalSymbol: {
344 bool isCallOp = Modifier && !strcmp(Modifier, "call");
345 std::string Name(TAI->getGlobalPrefix());
346 Name += MO.getSymbolName();
347 if (isCallOp && Subtarget->isTargetDarwin() &&
348 TM.getRelocationModel() != Reloc::Static) {
349 printSuffixedName(Name, "$stub");
350 FnStubs.insert(Name);
353 if (isCallOp && Subtarget->isTargetELF() &&
354 TM.getRelocationModel() == Reloc::PIC_)
358 case MachineOperand::MO_ConstantPoolIndex:
359 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
360 << '_' << MO.getIndex();
362 case MachineOperand::MO_JumpTableIndex:
363 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
364 << '_' << MO.getIndex();
367 O << "<unknown operand type>"; abort (); break;
371 static void printSOImm(raw_ostream &O, int64_t V, bool VerboseAsm,
372 const TargetAsmInfo *TAI) {
373 // Break it up into two parts that make up a shifter immediate.
374 V = ARM_AM::getSOImmVal(V);
375 assert(V != -1 && "Not a valid so_imm value!");
377 unsigned Imm = ARM_AM::getSOImmValImm(V);
378 unsigned Rot = ARM_AM::getSOImmValRot(V);
380 // Print low-level immediate formation info, per
381 // A5.1.3: "Data-processing operands - Immediate".
383 O << "#" << Imm << ", " << Rot;
384 // Pretty printed version.
386 O << ' ' << TAI->getCommentString()
387 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
393 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
394 /// immediate in bits 0-7.
395 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
396 const MachineOperand &MO = MI->getOperand(OpNum);
397 assert(MO.isImm() && "Not a valid so_imm value!");
398 printSOImm(O, MO.getImm(), VerboseAsm, TAI);
401 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
402 /// followed by an 'orr' to materialize.
403 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
404 const MachineOperand &MO = MI->getOperand(OpNum);
405 assert(MO.isImm() && "Not a valid so_imm value!");
406 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
407 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
408 printSOImm(O, V1, VerboseAsm, TAI);
410 printPredicateOperand(MI, 2);
416 printSOImm(O, V2, VerboseAsm, TAI);
419 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
420 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
422 // REG REG 0,SH_OPC - e.g. R5, ROR R3
423 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
424 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
425 const MachineOperand &MO1 = MI->getOperand(Op);
426 const MachineOperand &MO2 = MI->getOperand(Op+1);
427 const MachineOperand &MO3 = MI->getOperand(Op+2);
429 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
430 O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
432 // Print the shift opc.
434 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
438 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
439 O << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
440 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
442 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
446 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
447 const MachineOperand &MO1 = MI->getOperand(Op);
448 const MachineOperand &MO2 = MI->getOperand(Op+1);
449 const MachineOperand &MO3 = MI->getOperand(Op+2);
451 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
452 printOperand(MI, Op);
456 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
459 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
461 << (char)ARM_AM::getAM2Op(MO3.getImm())
462 << ARM_AM::getAM2Offset(MO3.getImm());
468 << (char)ARM_AM::getAM2Op(MO3.getImm())
469 << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
471 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
473 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
478 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
479 const MachineOperand &MO1 = MI->getOperand(Op);
480 const MachineOperand &MO2 = MI->getOperand(Op+1);
483 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
484 assert(ImmOffs && "Malformed indexed load / store!");
486 << (char)ARM_AM::getAM2Op(MO2.getImm())
491 O << (char)ARM_AM::getAM2Op(MO2.getImm())
492 << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
494 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
496 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
500 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
501 const MachineOperand &MO1 = MI->getOperand(Op);
502 const MachineOperand &MO2 = MI->getOperand(Op+1);
503 const MachineOperand &MO3 = MI->getOperand(Op+2);
505 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
506 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
510 << (char)ARM_AM::getAM3Op(MO3.getImm())
511 << TM.getRegisterInfo()->get(MO2.getReg()).AsmName
516 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
518 << (char)ARM_AM::getAM3Op(MO3.getImm())
523 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
524 const MachineOperand &MO1 = MI->getOperand(Op);
525 const MachineOperand &MO2 = MI->getOperand(Op+1);
528 O << (char)ARM_AM::getAM3Op(MO2.getImm())
529 << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
533 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
534 assert(ImmOffs && "Malformed indexed load / store!");
536 << (char)ARM_AM::getAM3Op(MO2.getImm())
540 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
541 const char *Modifier) {
542 const MachineOperand &MO1 = MI->getOperand(Op);
543 const MachineOperand &MO2 = MI->getOperand(Op+1);
544 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
545 if (Modifier && strcmp(Modifier, "submode") == 0) {
546 if (MO1.getReg() == ARM::SP) {
547 bool isLDM = (MI->getOpcode() == ARM::LDM ||
548 MI->getOpcode() == ARM::LDM_RET);
549 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
551 O << ARM_AM::getAMSubModeStr(Mode);
553 printOperand(MI, Op);
554 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
559 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
560 const char *Modifier) {
561 const MachineOperand &MO1 = MI->getOperand(Op);
562 const MachineOperand &MO2 = MI->getOperand(Op+1);
564 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
565 printOperand(MI, Op);
569 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
571 if (Modifier && strcmp(Modifier, "submode") == 0) {
572 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
573 if (MO1.getReg() == ARM::SP) {
574 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
575 MI->getOpcode() == ARM::FLDMS);
576 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
578 O << ARM_AM::getAMSubModeStr(Mode);
580 } else if (Modifier && strcmp(Modifier, "base") == 0) {
581 // Used for FSTM{D|S} and LSTM{D|S} operations.
582 O << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
583 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
588 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
590 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
592 << (char)ARM_AM::getAM5Op(MO2.getImm())
598 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
599 const MachineOperand &MO1 = MI->getOperand(Op);
600 const MachineOperand &MO2 = MI->getOperand(Op+1);
601 const MachineOperand &MO3 = MI->getOperand(Op+2);
603 // FIXME: No support yet for specifying alignment.
604 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
606 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
607 if (MO2.getReg() == 0)
610 O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
614 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
615 const char *Modifier) {
616 if (Modifier && strcmp(Modifier, "label") == 0) {
617 printPCLabel(MI, Op+1);
621 const MachineOperand &MO1 = MI->getOperand(Op);
622 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
623 O << "[pc, +" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName << "]";
627 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
628 const MachineOperand &MO = MI->getOperand(Op);
629 uint32_t v = ~MO.getImm();
630 int32_t lsb = CountTrailingZeros_32(v);
631 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
632 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
633 O << "#" << lsb << ", #" << width;
636 //===--------------------------------------------------------------------===//
639 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
640 const MachineOperand &MO1 = MI->getOperand(Op);
641 const MachineOperand &MO2 = MI->getOperand(Op+1);
642 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
643 O << ", " << TM.getRegisterInfo()->get(MO2.getReg()).AsmName << "]";
647 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
649 const MachineOperand &MO1 = MI->getOperand(Op);
650 const MachineOperand &MO2 = MI->getOperand(Op+1);
651 const MachineOperand &MO3 = MI->getOperand(Op+2);
653 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
654 printOperand(MI, Op);
658 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
660 O << ", " << TM.getRegisterInfo()->get(MO3.getReg()).AsmName;
661 else if (unsigned ImmOffs = MO2.getImm()) {
662 O << ", #" << ImmOffs;
670 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
671 printThumbAddrModeRI5Operand(MI, Op, 1);
674 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
675 printThumbAddrModeRI5Operand(MI, Op, 2);
678 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
679 printThumbAddrModeRI5Operand(MI, Op, 4);
682 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
683 const MachineOperand &MO1 = MI->getOperand(Op);
684 const MachineOperand &MO2 = MI->getOperand(Op+1);
685 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
686 if (unsigned ImmOffs = MO2.getImm())
687 O << ", #" << ImmOffs << " * 4";
691 //===--------------------------------------------------------------------===//
693 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
694 // register with shift forms.
696 // REG IMM, SH_OPC - e.g. R5, LSL #3
697 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
698 const MachineOperand &MO1 = MI->getOperand(OpNum);
699 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
701 unsigned Reg = MO1.getReg();
702 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
703 O << TM.getRegisterInfo()->getAsmName(Reg);
705 // Print the shift opc.
707 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
710 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
711 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
714 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
716 const MachineOperand &MO1 = MI->getOperand(OpNum);
717 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
719 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
721 unsigned OffImm = MO2.getImm();
722 if (OffImm) // Don't print +0.
723 O << ", #+" << OffImm;
727 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
729 const MachineOperand &MO1 = MI->getOperand(OpNum);
730 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
732 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
734 int32_t OffImm = (int32_t)MO2.getImm();
737 O << ", #-" << -OffImm;
739 O << ", #+" << OffImm;
743 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
745 const MachineOperand &MO1 = MI->getOperand(OpNum);
746 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
748 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
750 int32_t OffImm = (int32_t)MO2.getImm() / 4;
753 O << ", #-" << -OffImm << " * 4";
755 O << ", #+" << OffImm << " * 4";
759 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
761 const MachineOperand &MO1 = MI->getOperand(OpNum);
762 int32_t OffImm = (int32_t)MO1.getImm();
765 O << "#-" << -OffImm;
770 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
772 const MachineOperand &MO1 = MI->getOperand(OpNum);
773 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
774 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
776 O << "[" << TM.getRegisterInfo()->get(MO1.getReg()).AsmName;
780 << TM.getRegisterInfo()->get(MO2.getReg()).AsmName;
782 unsigned ShAmt = MO3.getImm();
784 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
785 O << ", lsl #" << ShAmt;
792 //===--------------------------------------------------------------------===//
794 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
795 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
797 O << ARMCondCodeToString(CC);
800 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
801 unsigned Reg = MI->getOperand(OpNum).getReg();
803 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
808 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
809 int Id = (int)MI->getOperand(OpNum).getImm();
810 O << TAI->getPrivateGlobalPrefix() << "PC" << Id;
813 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
815 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
817 if (i != e-1) O << ", ";
822 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
823 const char *Modifier) {
824 assert(Modifier && "This operand only works with a modifier!");
825 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
827 if (!strcmp(Modifier, "label")) {
828 unsigned ID = MI->getOperand(OpNum).getImm();
829 O << TAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
830 << '_' << ID << ":\n";
832 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
833 unsigned CPI = MI->getOperand(OpNum).getIndex();
835 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
837 if (MCPE.isMachineConstantPoolEntry()) {
838 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
840 EmitGlobalConstant(MCPE.Val.ConstVal);
845 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
846 const MachineOperand &MO1 = MI->getOperand(OpNum);
847 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
848 unsigned JTI = MO1.getIndex();
849 O << TAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
850 << '_' << JTI << '_' << MO2.getImm() << ":\n";
852 const char *JTEntryDirective = TAI->getJumpTableDirective();
853 if (!JTEntryDirective)
854 JTEntryDirective = TAI->getData32bitsDirective();
856 const MachineFunction *MF = MI->getParent()->getParent();
857 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
858 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
859 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
860 bool UseSet= TAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
861 std::set<MachineBasicBlock*> JTSets;
862 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
863 MachineBasicBlock *MBB = JTBBs[i];
864 if (UseSet && JTSets.insert(MBB).second)
865 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
867 O << JTEntryDirective << ' ';
869 O << TAI->getPrivateGlobalPrefix() << getFunctionNumber()
870 << '_' << JTI << '_' << MO2.getImm()
871 << "_set_" << MBB->getNumber();
872 else if (TM.getRelocationModel() == Reloc::PIC_) {
873 printBasicBlockLabel(MBB, false, false, false);
874 // If the arch uses custom Jump Table directives, don't calc relative to JT
875 if (!TAI->getJumpTableDirective())
876 O << '-' << TAI->getPrivateGlobalPrefix() << "JTI"
877 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
879 printBasicBlockLabel(MBB, false, false, false);
886 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
887 unsigned AsmVariant, const char *ExtraCode){
888 // Does this asm operand have a single letter operand modifier?
889 if (ExtraCode && ExtraCode[0]) {
890 if (ExtraCode[1] != 0) return true; // Unknown modifier.
892 switch (ExtraCode[0]) {
893 default: return true; // Unknown modifier.
894 case 'a': // Don't print "#" before a global var name or constant.
895 case 'c': // Don't print "$" before a global var name or constant.
896 printOperand(MI, OpNum, "no_hash");
898 case 'P': // Print a VFP double precision register.
899 printOperand(MI, OpNum);
902 if (TM.getTargetData()->isLittleEndian())
906 if (TM.getTargetData()->isBigEndian())
909 case 'H': // Write second word of DI / DF reference.
910 // Verify that this operand has two consecutive registers.
911 if (!MI->getOperand(OpNum).isReg() ||
912 OpNum+1 == MI->getNumOperands() ||
913 !MI->getOperand(OpNum+1).isReg())
915 ++OpNum; // Return the high-part.
919 printOperand(MI, OpNum);
923 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
924 unsigned OpNum, unsigned AsmVariant,
925 const char *ExtraCode) {
926 if (ExtraCode && ExtraCode[0])
927 return true; // Unknown modifier.
928 printAddrMode2Operand(MI, OpNum);
932 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
935 int Opc = MI->getOpcode();
937 case ARM::CONSTPOOL_ENTRY:
938 if (!InCPMode && AFI->isThumbFunction()) {
944 if (InCPMode && AFI->isThumbFunction())
948 // Call the autogenerated instruction printer routines.
949 printInstruction(MI);
952 bool ARMAsmPrinter::doInitialization(Module &M) {
954 bool Result = AsmPrinter::doInitialization(M);
955 DW = getAnalysisIfAvailable<DwarfWriter>();
957 // Thumb-2 instructions are supported only in unified assembler syntax mode.
958 if (Subtarget->hasThumb2())
959 O << "\t.syntax unified\n";
961 // Emit ARM Build Attributes
962 if (Subtarget->isTargetELF()) {
964 std::string CPUString = Subtarget->getCPUString();
965 if (CPUString != "generic")
966 O << "\t.cpu " << CPUString << '\n';
968 // FIXME: Emit FPU type
969 if (Subtarget->hasVFP2())
970 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
972 // Signal various FP modes.
974 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
975 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
977 if (FiniteOnlyFPMath())
978 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
980 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
982 // 8-bytes alignment stuff.
983 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
984 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
986 // FIXME: Should we signal R9 usage?
992 /// PrintUnmangledNameSafely - Print out the printable characters in the name.
993 /// Don't print things like \\n or \\0.
994 static void PrintUnmangledNameSafely(const Value *V, raw_ostream &OS) {
995 for (const char *Name = V->getNameStart(), *E = Name+V->getNameLen();
1001 void ARMAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) {
1002 const TargetData *TD = TM.getTargetData();
1004 if (!GVar->hasInitializer()) // External global require no code
1007 // Check to see if this is a special global used by LLVM, if so, emit it.
1009 if (EmitSpecialLLVMGlobal(GVar)) {
1010 if (Subtarget->isTargetDarwin() &&
1011 TM.getRelocationModel() == Reloc::Static) {
1012 if (GVar->getName() == "llvm.global_ctors")
1013 O << ".reference .constructors_used\n";
1014 else if (GVar->getName() == "llvm.global_dtors")
1015 O << ".reference .destructors_used\n";
1020 std::string name = Mang->getValueName(GVar);
1021 Constant *C = GVar->getInitializer();
1022 if (isa<MDNode>(C) || isa<MDString>(C))
1024 const Type *Type = C->getType();
1025 unsigned Size = TD->getTypeAllocSize(Type);
1026 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1027 bool isDarwin = Subtarget->isTargetDarwin();
1029 printVisibility(name, GVar->getVisibility());
1031 if (Subtarget->isTargetELF())
1032 O << "\t.type " << name << ",%object\n";
1034 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1036 TAI->SectionKindForGlobal(GVar) == SectionKind::RODataMergeStr)) {
1037 // FIXME: This seems to be pretty darwin-specific
1039 if (GVar->hasExternalLinkage()) {
1040 SwitchToSection(TAI->SectionForGlobal(GVar));
1041 if (const char *Directive = TAI->getZeroFillDirective()) {
1042 O << "\t.globl\t" << name << "\n";
1043 O << Directive << "__DATA, __common, " << name << ", "
1044 << Size << ", " << Align << "\n";
1049 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1050 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1053 if (GVar->hasLocalLinkage()) {
1054 O << TAI->getLCOMMDirective() << name << "," << Size
1056 } else if (GVar->hasCommonLinkage()) {
1057 O << TAI->getCOMMDirective() << name << "," << Size
1060 SwitchToSection(TAI->SectionForGlobal(GVar));
1061 O << "\t.globl " << name << '\n'
1062 << TAI->getWeakDefDirective() << name << '\n';
1063 EmitAlignment(Align, GVar);
1066 O << "\t\t\t\t" << TAI->getCommentString() << ' ';
1067 PrintUnmangledNameSafely(GVar, O);
1070 EmitGlobalConstant(C);
1073 } else if (TAI->getLCOMMDirective() != NULL) {
1074 if (GVar->hasLocalLinkage()) {
1075 O << TAI->getLCOMMDirective() << name << "," << Size;
1077 O << TAI->getCOMMDirective() << name << "," << Size;
1078 if (TAI->getCOMMDirectiveTakesAlignment())
1079 O << ',' << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1082 SwitchToSection(TAI->SectionForGlobal(GVar));
1083 if (GVar->hasLocalLinkage())
1084 O << "\t.local\t" << name << "\n";
1085 O << TAI->getCOMMDirective() << name << "," << Size;
1086 if (TAI->getCOMMDirectiveTakesAlignment())
1087 O << "," << (TAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1090 O << "\t\t" << TAI->getCommentString() << " ";
1091 PrintUnmangledNameSafely(GVar, O);
1098 SwitchToSection(TAI->SectionForGlobal(GVar));
1099 switch (GVar->getLinkage()) {
1100 case GlobalValue::CommonLinkage:
1101 case GlobalValue::LinkOnceAnyLinkage:
1102 case GlobalValue::LinkOnceODRLinkage:
1103 case GlobalValue::WeakAnyLinkage:
1104 case GlobalValue::WeakODRLinkage:
1106 O << "\t.globl " << name << "\n"
1107 << "\t.weak_definition " << name << "\n";
1109 O << "\t.weak " << name << "\n";
1112 case GlobalValue::AppendingLinkage:
1113 // FIXME: appending linkage variables should go into a section of
1114 // their name or something. For now, just emit them as external.
1115 case GlobalValue::ExternalLinkage:
1116 O << "\t.globl " << name << "\n";
1118 case GlobalValue::PrivateLinkage:
1119 case GlobalValue::InternalLinkage:
1122 LLVM_UNREACHABLE("Unknown linkage type!");
1125 EmitAlignment(Align, GVar);
1128 O << "\t\t\t\t" << TAI->getCommentString() << " ";
1129 PrintUnmangledNameSafely(GVar, O);
1132 if (TAI->hasDotTypeDotSizeDirective())
1133 O << "\t.size " << name << ", " << Size << "\n";
1135 EmitGlobalConstant(C);
1140 bool ARMAsmPrinter::doFinalization(Module &M) {
1141 for (Module::const_global_iterator I = M.global_begin(), E = M.global_end();
1143 printModuleLevelGV(I);
1145 if (Subtarget->isTargetDarwin()) {
1146 SwitchToDataSection("");
1148 // Output stubs for dynamically-linked functions
1149 for (StringSet<>::iterator i = FnStubs.begin(), e = FnStubs.end();
1151 if (TM.getRelocationModel() == Reloc::PIC_)
1152 SwitchToTextSection(".section __TEXT,__picsymbolstub4,symbol_stubs,"
1155 SwitchToTextSection(".section __TEXT,__symbol_stub4,symbol_stubs,"
1159 O << "\t.code\t32\n";
1161 const char *p = i->getKeyData();
1162 printSuffixedName(p, "$stub");
1164 O << "\t.indirect_symbol " << p << "\n";
1166 printSuffixedName(p, "$slp");
1168 if (TM.getRelocationModel() == Reloc::PIC_) {
1169 printSuffixedName(p, "$scv");
1171 O << "\tadd ip, pc, ip\n";
1173 O << "\tldr pc, [ip, #0]\n";
1174 printSuffixedName(p, "$slp");
1177 printSuffixedName(p, "$lazy_ptr");
1178 if (TM.getRelocationModel() == Reloc::PIC_) {
1180 printSuffixedName(p, "$scv");
1184 SwitchToDataSection(".lazy_symbol_pointer", 0);
1185 printSuffixedName(p, "$lazy_ptr");
1187 O << "\t.indirect_symbol " << p << "\n";
1188 O << "\t.long\tdyld_stub_binding_helper\n";
1192 // Output non-lazy-pointers for external and common global variables.
1193 if (!GVNonLazyPtrs.empty()) {
1194 SwitchToDataSection("\t.non_lazy_symbol_pointer", 0);
1195 for (StringSet<>::iterator i = GVNonLazyPtrs.begin(),
1196 e = GVNonLazyPtrs.end(); i != e; ++i) {
1197 const char *p = i->getKeyData();
1198 printSuffixedName(p, "$non_lazy_ptr");
1200 O << "\t.indirect_symbol " << p << "\n";
1201 O << "\t.long\t0\n";
1205 if (!HiddenGVNonLazyPtrs.empty()) {
1206 SwitchToSection(TAI->getDataSection());
1207 for (StringSet<>::iterator i = HiddenGVNonLazyPtrs.begin(),
1208 e = HiddenGVNonLazyPtrs.end(); i != e; ++i) {
1209 const char *p = i->getKeyData();
1211 printSuffixedName(p, "$non_lazy_ptr");
1213 O << "\t.long " << p << "\n";
1218 // Funny Darwin hack: This flag tells the linker that no global symbols
1219 // contain code that falls through to other global symbols (e.g. the obvious
1220 // implementation of multiple entry points). If this doesn't occur, the
1221 // linker can safely perform dead code stripping. Since LLVM never
1222 // generates code that does this, it is always safe to set.
1223 O << "\t.subsections_via_symbols\n";
1226 return AsmPrinter::doFinalization(M);
1229 /// createARMCodePrinterPass - Returns a pass that prints the ARM
1230 /// assembly code for a MachineFunction to the given output stream,
1231 /// using the given target machine description. This should work
1232 /// regardless of whether the function is in SSA form.
1234 FunctionPass *llvm::createARMCodePrinterPass(raw_ostream &o,
1235 ARMBaseTargetMachine &tm,
1237 return new ARMAsmPrinter(o, tm, tm.getTargetAsmInfo(), verbose);
1241 static struct Register {
1243 ARMBaseTargetMachine::registerAsmPrinter(createARMCodePrinterPass);
1248 // Force static initialization.
1249 extern "C" void LLVMInitializeARMAsmPrinter() { }