1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSectionMachO.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegistry.h"
44 #include "llvm/ADT/SmallPtrSet.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/StringSet.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/FormattedStream.h"
52 #include "llvm/Support/MathExtras.h"
56 STATISTIC(EmittedInsts, "Number of machine instrs printed");
59 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
60 cl::desc("enable experimental asmprinter gunk in the arm backend"));
63 class ARMAsmPrinter : public AsmPrinter {
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when printing asm code for different targets.
67 const ARMSubtarget *Subtarget;
69 /// AFI - Keep a pointer to ARMFunctionInfo for the current
73 /// MCP - Keep a pointer to constantpool entries of the current
75 const MachineConstantPool *MCP;
78 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 const MCAsmInfo *T, bool V)
80 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printMCInst(const MCInst *MI) {
89 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
92 void printInstructionThroughMCStreamer(const MachineInstr *MI);
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
114 void printThumbITMask(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
118 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
121 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
128 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
132 void printPCLabel(const MachineInstr *MI, int OpNum);
133 void printRegisterList(const MachineInstr *MI, int OpNum);
134 void printCPInstOperand(const MachineInstr *MI, int OpNum,
135 const char *Modifier);
136 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
137 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
138 void printTBAddrMode(const MachineInstr *MI, int OpNum);
139 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
141 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
143 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
144 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
146 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
147 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
149 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
150 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
152 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
153 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
156 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
157 unsigned AsmVariant, const char *ExtraCode);
158 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
160 const char *ExtraCode);
162 void printInstruction(const MachineInstr *MI); // autogenerated.
163 static const char *getRegisterName(unsigned RegNo);
165 void printMachineInstruction(const MachineInstr *MI);
166 bool runOnMachineFunction(MachineFunction &F);
167 void EmitStartOfAsmFile(Module &M);
168 void EmitEndOfAsmFile(Module &M);
170 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
172 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
173 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
174 case 1: O << MAI->getData8bitsDirective(0); break;
175 case 2: O << MAI->getData16bitsDirective(0); break;
176 case 4: O << MAI->getData32bitsDirective(0); break;
177 default: assert(0 && "Unknown CPV size");
180 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
181 SmallString<128> TmpNameStr;
183 if (ACPV->isLSDA()) {
184 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
185 "_LSDA_" << getFunctionNumber();
186 O << TmpNameStr.str();
187 } else if (ACPV->isBlockAddress()) {
188 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
189 } else if (ACPV->isGlobalValue()) {
190 GlobalValue *GV = ACPV->getGV();
191 bool isIndirect = Subtarget->isTargetDarwin() &&
192 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
194 O << *GetGlobalValueSymbol(GV);
196 // FIXME: Remove this when Darwin transition to @GOT like syntax.
197 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
200 MachineModuleInfoMachO &MMIMachO =
201 MMI->getObjFileInfo<MachineModuleInfoMachO>();
202 const MCSymbol *&StubSym =
203 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
204 MMIMachO.getGVStubEntry(Sym);
206 StubSym = GetGlobalValueSymbol(GV);
209 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
210 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
213 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
214 if (ACPV->getPCAdjustment() != 0) {
215 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
216 << getFunctionNumber() << "_" << ACPV->getLabelId()
217 << "+" << (unsigned)ACPV->getPCAdjustment();
218 if (ACPV->mustAddCurrentAddress())
225 void getAnalysisUsage(AnalysisUsage &AU) const {
226 AsmPrinter::getAnalysisUsage(AU);
227 AU.setPreservesAll();
228 AU.addRequired<MachineModuleInfo>();
229 AU.addRequired<DwarfWriter>();
232 } // end of anonymous namespace
234 #include "ARMGenAsmWriter.inc"
236 /// runOnMachineFunction - This uses the printInstruction()
237 /// method to print assembly for each instruction.
239 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
242 AFI = MF.getInfo<ARMFunctionInfo>();
243 MCP = MF.getConstantPool();
245 SetupMachineFunction(MF);
248 // NOTE: we don't print out constant pools here, they are handled as
253 // Print out labels for the function.
254 const Function *F = MF.getFunction();
255 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
257 switch (F->getLinkage()) {
258 default: llvm_unreachable("Unknown linkage type!");
259 case Function::PrivateLinkage:
260 case Function::InternalLinkage:
262 case Function::ExternalLinkage:
263 O << "\t.globl\t" << *CurrentFnSym << "\n";
265 case Function::LinkerPrivateLinkage:
266 case Function::WeakAnyLinkage:
267 case Function::WeakODRLinkage:
268 case Function::LinkOnceAnyLinkage:
269 case Function::LinkOnceODRLinkage:
270 if (Subtarget->isTargetDarwin()) {
271 O << "\t.globl\t" << *CurrentFnSym << "\n";
272 O << "\t.weak_definition\t" << *CurrentFnSym << "\n";
274 O << MAI->getWeakRefDirective() << *CurrentFnSym << "\n";
279 printVisibility(CurrentFnSym, F->getVisibility());
281 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
282 if (AFI->isThumbFunction()) {
283 EmitAlignment(FnAlign, F, AFI->getAlign());
284 O << "\t.code\t16\n";
285 O << "\t.thumb_func";
286 if (Subtarget->isTargetDarwin())
287 O << "\t" << *CurrentFnSym;
290 EmitAlignment(FnAlign, F);
293 O << *CurrentFnSym << ":\n";
294 // Emit pre-function debug information.
295 DW->BeginFunction(&MF);
297 if (Subtarget->isTargetDarwin()) {
298 // If the function is empty, then we need to emit *something*. Otherwise,
299 // the function's label might be associated with something that it wasn't
300 // meant to be associated with. We emit a noop in this situation.
301 MachineFunction::iterator I = MF.begin();
303 if (++I == MF.end() && MF.front().empty())
307 // Print out code for the function.
308 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
310 // Print a label for the basic block.
312 EmitBasicBlockStart(I);
314 // Print the assembly for the instruction.
315 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
317 printMachineInstruction(II);
320 if (MAI->hasDotTypeDotSizeDirective())
321 O << "\t.size " << *CurrentFnSym << ", .-" << *CurrentFnSym << "\n";
323 // Emit post-function debug information.
324 DW->EndFunction(&MF);
329 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
330 const char *Modifier) {
331 const MachineOperand &MO = MI->getOperand(OpNum);
332 unsigned TF = MO.getTargetFlags();
334 switch (MO.getType()) {
336 assert(0 && "<unknown operand type>");
337 case MachineOperand::MO_Register: {
338 unsigned Reg = MO.getReg();
339 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
340 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
341 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
342 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
344 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
346 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
347 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
348 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
349 &ARM::DPR_VFP2RegClass);
350 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
352 assert(!MO.getSubReg() && "Subregs should be eliminated!");
353 O << getRegisterName(Reg);
357 case MachineOperand::MO_Immediate: {
358 int64_t Imm = MO.getImm();
360 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
361 (TF & ARMII::MO_LO16))
363 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
364 (TF & ARMII::MO_HI16))
369 case MachineOperand::MO_MachineBasicBlock:
370 O << *GetMBBSymbol(MO.getMBB()->getNumber());
372 case MachineOperand::MO_GlobalAddress: {
373 bool isCallOp = Modifier && !strcmp(Modifier, "call");
374 GlobalValue *GV = MO.getGlobal();
376 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
377 (TF & ARMII::MO_LO16))
379 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
380 (TF & ARMII::MO_HI16))
382 O << *GetGlobalValueSymbol(GV);
384 printOffset(MO.getOffset());
386 if (isCallOp && Subtarget->isTargetELF() &&
387 TM.getRelocationModel() == Reloc::PIC_)
391 case MachineOperand::MO_ExternalSymbol: {
392 bool isCallOp = Modifier && !strcmp(Modifier, "call");
393 O << *GetExternalSymbolSymbol(MO.getSymbolName());
395 if (isCallOp && Subtarget->isTargetELF() &&
396 TM.getRelocationModel() == Reloc::PIC_)
400 case MachineOperand::MO_ConstantPoolIndex:
401 O << *GetCPISymbol(MO.getIndex());
403 case MachineOperand::MO_JumpTableIndex:
404 O << *GetJTISymbol(MO.getIndex());
409 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
410 const MCAsmInfo *MAI) {
411 // Break it up into two parts that make up a shifter immediate.
412 V = ARM_AM::getSOImmVal(V);
413 assert(V != -1 && "Not a valid so_imm value!");
415 unsigned Imm = ARM_AM::getSOImmValImm(V);
416 unsigned Rot = ARM_AM::getSOImmValRot(V);
418 // Print low-level immediate formation info, per
419 // A5.1.3: "Data-processing operands - Immediate".
421 O << "#" << Imm << ", " << Rot;
422 // Pretty printed version.
424 O.PadToColumn(MAI->getCommentColumn());
425 O << MAI->getCommentString() << ' ';
426 O << (int)ARM_AM::rotr32(Imm, Rot);
433 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
434 /// immediate in bits 0-7.
435 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
436 const MachineOperand &MO = MI->getOperand(OpNum);
437 assert(MO.isImm() && "Not a valid so_imm value!");
438 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
441 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
442 /// followed by an 'orr' to materialize.
443 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
444 const MachineOperand &MO = MI->getOperand(OpNum);
445 assert(MO.isImm() && "Not a valid so_imm value!");
446 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
447 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
448 printSOImm(O, V1, VerboseAsm, MAI);
450 printPredicateOperand(MI, 2);
456 printSOImm(O, V2, VerboseAsm, MAI);
459 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
460 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
462 // REG REG 0,SH_OPC - e.g. R5, ROR R3
463 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
464 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
465 const MachineOperand &MO1 = MI->getOperand(Op);
466 const MachineOperand &MO2 = MI->getOperand(Op+1);
467 const MachineOperand &MO3 = MI->getOperand(Op+2);
469 O << getRegisterName(MO1.getReg());
471 // Print the shift opc.
473 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
477 O << getRegisterName(MO2.getReg());
478 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
480 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
484 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
485 const MachineOperand &MO1 = MI->getOperand(Op);
486 const MachineOperand &MO2 = MI->getOperand(Op+1);
487 const MachineOperand &MO3 = MI->getOperand(Op+2);
489 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
490 printOperand(MI, Op);
494 O << "[" << getRegisterName(MO1.getReg());
497 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
499 << (char)ARM_AM::getAM2Op(MO3.getImm())
500 << ARM_AM::getAM2Offset(MO3.getImm());
506 << (char)ARM_AM::getAM2Op(MO3.getImm())
507 << getRegisterName(MO2.getReg());
509 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
511 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
516 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
517 const MachineOperand &MO1 = MI->getOperand(Op);
518 const MachineOperand &MO2 = MI->getOperand(Op+1);
521 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
522 assert(ImmOffs && "Malformed indexed load / store!");
524 << (char)ARM_AM::getAM2Op(MO2.getImm())
529 O << (char)ARM_AM::getAM2Op(MO2.getImm())
530 << getRegisterName(MO1.getReg());
532 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
534 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
538 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
539 const MachineOperand &MO1 = MI->getOperand(Op);
540 const MachineOperand &MO2 = MI->getOperand(Op+1);
541 const MachineOperand &MO3 = MI->getOperand(Op+2);
543 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
544 O << "[" << getRegisterName(MO1.getReg());
548 << (char)ARM_AM::getAM3Op(MO3.getImm())
549 << getRegisterName(MO2.getReg())
554 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
556 << (char)ARM_AM::getAM3Op(MO3.getImm())
561 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
562 const MachineOperand &MO1 = MI->getOperand(Op);
563 const MachineOperand &MO2 = MI->getOperand(Op+1);
566 O << (char)ARM_AM::getAM3Op(MO2.getImm())
567 << getRegisterName(MO1.getReg());
571 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
572 assert(ImmOffs && "Malformed indexed load / store!");
574 << (char)ARM_AM::getAM3Op(MO2.getImm())
578 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
579 const char *Modifier) {
580 const MachineOperand &MO1 = MI->getOperand(Op);
581 const MachineOperand &MO2 = MI->getOperand(Op+1);
582 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
583 if (Modifier && strcmp(Modifier, "submode") == 0) {
584 if (MO1.getReg() == ARM::SP) {
586 bool isLDM = (MI->getOpcode() == ARM::LDM ||
587 MI->getOpcode() == ARM::LDM_RET ||
588 MI->getOpcode() == ARM::t2LDM ||
589 MI->getOpcode() == ARM::t2LDM_RET);
590 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
592 O << ARM_AM::getAMSubModeStr(Mode);
593 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
594 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
595 if (Mode == ARM_AM::ia)
598 printOperand(MI, Op);
599 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
604 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
605 const char *Modifier) {
606 const MachineOperand &MO1 = MI->getOperand(Op);
607 const MachineOperand &MO2 = MI->getOperand(Op+1);
609 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
610 printOperand(MI, Op);
614 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
616 if (Modifier && strcmp(Modifier, "submode") == 0) {
617 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
618 O << ARM_AM::getAMSubModeStr(Mode);
620 } else if (Modifier && strcmp(Modifier, "base") == 0) {
621 // Used for FSTM{D|S} and LSTM{D|S} operations.
622 O << getRegisterName(MO1.getReg());
623 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
628 O << "[" << getRegisterName(MO1.getReg());
630 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
632 << (char)ARM_AM::getAM5Op(MO2.getImm())
638 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
639 const MachineOperand &MO1 = MI->getOperand(Op);
640 const MachineOperand &MO2 = MI->getOperand(Op+1);
641 const MachineOperand &MO3 = MI->getOperand(Op+2);
642 const MachineOperand &MO4 = MI->getOperand(Op+3);
644 O << "[" << getRegisterName(MO1.getReg());
646 // FIXME: Both darwin as and GNU as violate ARM docs here.
647 O << ", :" << MO4.getImm();
651 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
652 if (MO2.getReg() == 0)
655 O << ", " << getRegisterName(MO2.getReg());
659 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
660 const char *Modifier) {
661 if (Modifier && strcmp(Modifier, "label") == 0) {
662 printPCLabel(MI, Op+1);
666 const MachineOperand &MO1 = MI->getOperand(Op);
667 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
668 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
672 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
673 const MachineOperand &MO = MI->getOperand(Op);
674 uint32_t v = ~MO.getImm();
675 int32_t lsb = CountTrailingZeros_32(v);
676 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
677 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
678 O << "#" << lsb << ", #" << width;
681 //===--------------------------------------------------------------------===//
683 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
684 O << "#" << MI->getOperand(Op).getImm() * 4;
688 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
689 // (3 - the number of trailing zeros) is the number of then / else.
690 unsigned Mask = MI->getOperand(Op).getImm();
691 unsigned NumTZ = CountTrailingZeros_32(Mask);
692 assert(NumTZ <= 3 && "Invalid IT mask!");
693 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
694 bool T = (Mask & (1 << Pos)) == 0;
703 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
704 const MachineOperand &MO1 = MI->getOperand(Op);
705 const MachineOperand &MO2 = MI->getOperand(Op+1);
706 O << "[" << getRegisterName(MO1.getReg());
707 O << ", " << getRegisterName(MO2.getReg()) << "]";
711 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
713 const MachineOperand &MO1 = MI->getOperand(Op);
714 const MachineOperand &MO2 = MI->getOperand(Op+1);
715 const MachineOperand &MO3 = MI->getOperand(Op+2);
717 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
718 printOperand(MI, Op);
722 O << "[" << getRegisterName(MO1.getReg());
724 O << ", " << getRegisterName(MO3.getReg());
725 else if (unsigned ImmOffs = MO2.getImm())
726 O << ", #+" << ImmOffs * Scale;
731 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
732 printThumbAddrModeRI5Operand(MI, Op, 1);
735 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
736 printThumbAddrModeRI5Operand(MI, Op, 2);
739 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
740 printThumbAddrModeRI5Operand(MI, Op, 4);
743 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
744 const MachineOperand &MO1 = MI->getOperand(Op);
745 const MachineOperand &MO2 = MI->getOperand(Op+1);
746 O << "[" << getRegisterName(MO1.getReg());
747 if (unsigned ImmOffs = MO2.getImm())
748 O << ", #+" << ImmOffs*4;
752 //===--------------------------------------------------------------------===//
754 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
755 // register with shift forms.
757 // REG IMM, SH_OPC - e.g. R5, LSL #3
758 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
759 const MachineOperand &MO1 = MI->getOperand(OpNum);
760 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
762 unsigned Reg = MO1.getReg();
763 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
764 O << getRegisterName(Reg);
766 // Print the shift opc.
768 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
771 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
772 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
775 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
777 const MachineOperand &MO1 = MI->getOperand(OpNum);
778 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
780 O << "[" << getRegisterName(MO1.getReg());
782 unsigned OffImm = MO2.getImm();
783 if (OffImm) // Don't print +0.
784 O << ", #+" << OffImm;
788 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
790 const MachineOperand &MO1 = MI->getOperand(OpNum);
791 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
793 O << "[" << getRegisterName(MO1.getReg());
795 int32_t OffImm = (int32_t)MO2.getImm();
798 O << ", #-" << -OffImm;
800 O << ", #+" << OffImm;
804 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
806 const MachineOperand &MO1 = MI->getOperand(OpNum);
807 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
809 O << "[" << getRegisterName(MO1.getReg());
811 int32_t OffImm = (int32_t)MO2.getImm() / 4;
814 O << ", #-" << -OffImm * 4;
816 O << ", #+" << OffImm * 4;
820 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
822 const MachineOperand &MO1 = MI->getOperand(OpNum);
823 int32_t OffImm = (int32_t)MO1.getImm();
826 O << "#-" << -OffImm;
831 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
833 const MachineOperand &MO1 = MI->getOperand(OpNum);
834 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
835 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
837 O << "[" << getRegisterName(MO1.getReg());
839 assert(MO2.getReg() && "Invalid so_reg load / store address!");
840 O << ", " << getRegisterName(MO2.getReg());
842 unsigned ShAmt = MO3.getImm();
844 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
845 O << ", lsl #" << ShAmt;
851 //===--------------------------------------------------------------------===//
853 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
854 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
856 O << ARMCondCodeToString(CC);
859 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
860 unsigned Reg = MI->getOperand(OpNum).getReg();
862 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
867 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
868 int Id = (int)MI->getOperand(OpNum).getImm();
869 O << MAI->getPrivateGlobalPrefix()
870 << "PC" << getFunctionNumber() << "_" << Id;
873 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
875 // Always skip the first operand, it's the optional (and implicit writeback).
876 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
877 if (MI->getOperand(i).isImplicit())
879 if ((int)i != OpNum+1) O << ", ";
885 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
886 const char *Modifier) {
887 assert(Modifier && "This operand only works with a modifier!");
888 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
890 if (!strcmp(Modifier, "label")) {
891 unsigned ID = MI->getOperand(OpNum).getImm();
892 O << *GetCPISymbol(ID) << ":\n";
894 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
895 unsigned CPI = MI->getOperand(OpNum).getIndex();
897 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
899 if (MCPE.isMachineConstantPoolEntry()) {
900 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
902 EmitGlobalConstant(MCPE.Val.ConstVal);
907 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
908 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
910 const MachineOperand &MO1 = MI->getOperand(OpNum);
911 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
913 unsigned JTI = MO1.getIndex();
914 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
915 << '_' << JTI << '_' << MO2.getImm() << ":\n";
917 const char *JTEntryDirective = MAI->getData32bitsDirective();
919 const MachineFunction *MF = MI->getParent()->getParent();
920 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
921 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
922 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
923 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
924 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
925 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
926 MachineBasicBlock *MBB = JTBBs[i];
927 bool isNew = JTSets.insert(MBB);
930 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
932 O << JTEntryDirective << ' ';
934 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
935 << '_' << JTI << '_' << MO2.getImm()
936 << "_set_" << MBB->getNumber();
937 else if (TM.getRelocationModel() == Reloc::PIC_) {
938 O << *GetMBBSymbol(MBB->getNumber())
939 << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
940 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
942 O << *GetMBBSymbol(MBB->getNumber());
949 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
950 const MachineOperand &MO1 = MI->getOperand(OpNum);
951 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
952 unsigned JTI = MO1.getIndex();
953 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
954 << '_' << JTI << '_' << MO2.getImm() << ":\n";
956 const MachineFunction *MF = MI->getParent()->getParent();
957 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
958 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
959 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
960 bool ByteOffset = false, HalfWordOffset = false;
961 if (MI->getOpcode() == ARM::t2TBB)
963 else if (MI->getOpcode() == ARM::t2TBH)
964 HalfWordOffset = true;
966 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
967 MachineBasicBlock *MBB = JTBBs[i];
969 O << MAI->getData8bitsDirective();
970 else if (HalfWordOffset)
971 O << MAI->getData16bitsDirective();
972 if (ByteOffset || HalfWordOffset) {
973 O << '(' << *GetMBBSymbol(MBB->getNumber());
974 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
975 << '_' << JTI << '_' << MO2.getImm() << ")/2";
977 O << "\tb.w " << *GetMBBSymbol(MBB->getNumber());
983 // Make sure the instruction that follows TBB is 2-byte aligned.
984 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
985 if (ByteOffset && (JTBBs.size() & 1)) {
991 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
992 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
993 if (MI->getOpcode() == ARM::t2TBH)
998 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
999 O << MI->getOperand(OpNum).getImm();
1002 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
1003 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1004 O << '#' << FP->getValueAPF().convertToFloat();
1006 O.PadToColumn(MAI->getCommentColumn());
1007 O << MAI->getCommentString() << ' ';
1008 WriteAsOperand(O, FP, /*PrintType=*/false);
1012 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
1013 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1014 O << '#' << FP->getValueAPF().convertToDouble();
1016 O.PadToColumn(MAI->getCommentColumn());
1017 O << MAI->getCommentString() << ' ';
1018 WriteAsOperand(O, FP, /*PrintType=*/false);
1022 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1023 unsigned AsmVariant, const char *ExtraCode){
1024 // Does this asm operand have a single letter operand modifier?
1025 if (ExtraCode && ExtraCode[0]) {
1026 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1028 switch (ExtraCode[0]) {
1029 default: return true; // Unknown modifier.
1030 case 'a': // Print as a memory address.
1031 if (MI->getOperand(OpNum).isReg()) {
1032 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1036 case 'c': // Don't print "#" before an immediate operand.
1037 if (!MI->getOperand(OpNum).isImm())
1039 printNoHashImmediate(MI, OpNum);
1041 case 'P': // Print a VFP double precision register.
1042 case 'q': // Print a NEON quad precision register.
1043 printOperand(MI, OpNum);
1046 if (TM.getTargetData()->isLittleEndian())
1050 if (TM.getTargetData()->isBigEndian())
1053 case 'H': // Write second word of DI / DF reference.
1054 // Verify that this operand has two consecutive registers.
1055 if (!MI->getOperand(OpNum).isReg() ||
1056 OpNum+1 == MI->getNumOperands() ||
1057 !MI->getOperand(OpNum+1).isReg())
1059 ++OpNum; // Return the high-part.
1063 printOperand(MI, OpNum);
1067 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1068 unsigned OpNum, unsigned AsmVariant,
1069 const char *ExtraCode) {
1070 if (ExtraCode && ExtraCode[0])
1071 return true; // Unknown modifier.
1073 const MachineOperand &MO = MI->getOperand(OpNum);
1074 assert(MO.isReg() && "unexpected inline asm memory operand");
1075 O << "[" << getRegisterName(MO.getReg()) << "]";
1079 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1082 // Call the autogenerated instruction printer routines.
1083 processDebugLoc(MI, true);
1086 printInstructionThroughMCStreamer(MI);
1088 int Opc = MI->getOpcode();
1089 if (Opc == ARM::CONSTPOOL_ENTRY)
1092 printInstruction(MI);
1098 processDebugLoc(MI, false);
1101 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1102 if (Subtarget->isTargetDarwin()) {
1103 Reloc::Model RelocM = TM.getRelocationModel();
1104 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1105 // Declare all the text sections up front (before the DWARF sections
1106 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1107 // them together at the beginning of the object file. This helps
1108 // avoid out-of-range branches that are due a fundamental limitation of
1109 // the way symbol offsets are encoded with the current Darwin ARM
1111 TargetLoweringObjectFileMachO &TLOFMacho =
1112 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1113 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1114 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1115 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1116 if (RelocM == Reloc::DynamicNoPIC) {
1117 const MCSection *sect =
1118 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1119 MCSectionMachO::S_SYMBOL_STUBS,
1120 12, SectionKind::getText());
1121 OutStreamer.SwitchSection(sect);
1123 const MCSection *sect =
1124 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1125 MCSectionMachO::S_SYMBOL_STUBS,
1126 16, SectionKind::getText());
1127 OutStreamer.SwitchSection(sect);
1132 // Use unified assembler syntax.
1133 O << "\t.syntax unified\n";
1135 // Emit ARM Build Attributes
1136 if (Subtarget->isTargetELF()) {
1138 std::string CPUString = Subtarget->getCPUString();
1139 if (CPUString != "generic")
1140 O << "\t.cpu " << CPUString << '\n';
1142 // FIXME: Emit FPU type
1143 if (Subtarget->hasVFP2())
1144 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1146 // Signal various FP modes.
1148 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1149 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1151 if (FiniteOnlyFPMath())
1152 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1154 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1156 // 8-bytes alignment stuff.
1157 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1158 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1160 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1161 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1162 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1163 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1165 // FIXME: Should we signal R9 usage?
1170 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1171 if (Subtarget->isTargetDarwin()) {
1172 // All darwin targets use mach-o.
1173 TargetLoweringObjectFileMachO &TLOFMacho =
1174 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1175 MachineModuleInfoMachO &MMIMacho =
1176 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1180 // Output non-lazy-pointers for external and common global variables.
1181 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1183 if (!Stubs.empty()) {
1184 // Switch with ".non_lazy_symbol_pointer" directive.
1185 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1187 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1188 O << *Stubs[i].first << ":\n\t.indirect_symbol ";
1189 O << *Stubs[i].second << "\n\t.long\t0\n";
1193 Stubs = MMIMacho.GetHiddenGVStubList();
1194 if (!Stubs.empty()) {
1195 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1197 for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
1198 O << *Stubs[i].first << ":\n\t.long " << *Stubs[i].second << "\n";
1201 // Funny Darwin hack: This flag tells the linker that no global symbols
1202 // contain code that falls through to other global symbols (e.g. the obvious
1203 // implementation of multiple entry points). If this doesn't occur, the
1204 // linker can safely perform dead code stripping. Since LLVM never
1205 // generates code that does this, it is always safe to set.
1206 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1210 //===----------------------------------------------------------------------===//
1212 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1213 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1214 switch (MI->getOpcode()) {
1215 case ARM::t2MOVi32imm:
1216 assert(0 && "Should be lowered by thumb2it pass");
1218 case TargetInstrInfo::DBG_LABEL:
1219 case TargetInstrInfo::EH_LABEL:
1220 case TargetInstrInfo::GC_LABEL:
1223 case TargetInstrInfo::KILL:
1226 case TargetInstrInfo::INLINEASM:
1229 case TargetInstrInfo::IMPLICIT_DEF:
1230 printImplicitDef(MI);
1232 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1233 // This is a pseudo op for a label + instruction sequence, which looks like:
1236 // This adds the address of LPC0 to r0.
1239 // FIXME: MOVE TO SHARED PLACE.
1240 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1241 const char *Prefix = MAI->getPrivateGlobalPrefix();
1242 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1243 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1244 OutStreamer.EmitLabel(Label);
1247 // Form and emit tha dd.
1249 AddInst.setOpcode(ARM::ADDrr);
1250 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1251 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1252 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1253 printMCInst(&AddInst);
1256 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1257 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1258 /// in the function. The first operand is the ID# for this instruction, the
1259 /// second is the index into the MachineConstantPool that this is, the third
1260 /// is the size in bytes of this constant pool entry.
1261 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1262 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1265 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1267 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1268 if (MCPE.isMachineConstantPoolEntry())
1269 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1271 EmitGlobalConstant(MCPE.Val.ConstVal);
1275 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1276 // This is a hack that lowers as a two instruction sequence.
1277 unsigned DstReg = MI->getOperand(0).getReg();
1278 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1280 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1281 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1285 TmpInst.setOpcode(ARM::MOVi);
1286 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1287 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1290 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1291 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1293 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1294 printMCInst(&TmpInst);
1300 TmpInst.setOpcode(ARM::ORRri);
1301 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1302 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1303 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1305 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1306 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1308 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1309 printMCInst(&TmpInst);
1313 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1314 // This is a hack that lowers as a two instruction sequence.
1315 unsigned DstReg = MI->getOperand(0).getReg();
1316 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1320 TmpInst.setOpcode(ARM::MOVi16);
1321 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1322 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1325 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1326 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1328 printMCInst(&TmpInst);
1334 TmpInst.setOpcode(ARM::MOVTi16);
1335 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1336 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1337 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1340 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1341 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1343 printMCInst(&TmpInst);
1351 MCInstLowering.Lower(MI, TmpInst);
1353 printMCInst(&TmpInst);
1356 //===----------------------------------------------------------------------===//
1357 // Target Registry Stuff
1358 //===----------------------------------------------------------------------===//
1360 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1361 unsigned SyntaxVariant,
1362 const MCAsmInfo &MAI,
1364 if (SyntaxVariant == 0)
1365 return new ARMInstPrinter(O, MAI, false);
1369 // Force static initialization.
1370 extern "C" void LLVMInitializeARMAsmPrinter() {
1371 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1372 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1374 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1375 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);