1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
34 #include "llvm/MC/MCAsmInfo.h"
35 #include "llvm/MC/MCContext.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/MC/MCInst.h"
38 #include "llvm/MC/MCSectionMachO.h"
39 #include "llvm/MC/MCStreamer.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/Target/Mangler.h"
42 #include "llvm/Target/TargetData.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegistry.h"
46 #include "llvm/ADT/SmallPtrSet.h"
47 #include "llvm/ADT/SmallString.h"
48 #include "llvm/ADT/StringExtras.h"
49 #include "llvm/ADT/StringSet.h"
50 #include "llvm/Support/CommandLine.h"
51 #include "llvm/Support/ErrorHandling.h"
52 #include "llvm/Support/FormattedStream.h"
53 #include "llvm/Support/MathExtras.h"
58 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
59 cl::desc("enable experimental asmprinter gunk in the arm backend"));
62 class ARMAsmPrinter : public AsmPrinter {
64 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
65 /// make the right decision when printing asm code for different targets.
66 const ARMSubtarget *Subtarget;
68 /// AFI - Keep a pointer to ARMFunctionInfo for the current
72 /// MCP - Keep a pointer to constantpool entries of the current
74 const MachineConstantPool *MCP;
77 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 : AsmPrinter(O, TM, Streamer), AFI(NULL), MCP(NULL) {
80 Subtarget = &TM.getSubtarget<ARMSubtarget>();
83 virtual const char *getPassName() const {
84 return "ARM Assembly Printer";
87 void printInstructionThroughMCStreamer(const MachineInstr *MI);
90 void printOperand(const MachineInstr *MI, int OpNum,
91 const char *Modifier = 0);
92 void printSOImmOperand(const MachineInstr *MI, int OpNum);
93 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
94 void printSORegOperand(const MachineInstr *MI, int OpNum);
95 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
96 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
97 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
98 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
99 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
100 const char *Modifier = 0);
101 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
102 const char *Modifier = 0);
103 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
104 void printAddrMode6OffsetOperand(const MachineInstr *MI, int OpNum);
105 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
106 const char *Modifier = 0);
107 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
109 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
110 void printThumbITMask(const MachineInstr *MI, int OpNum);
111 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
112 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
114 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
117 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
119 void printT2SOOperand(const MachineInstr *MI, int OpNum);
120 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
121 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
122 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8s4OffsetOperand(const MachineInstr *MI, int OpNum) {}
125 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
127 void printCPSOptionOperand(const MachineInstr *MI, int OpNum) {}
128 void printMSRMaskOperand(const MachineInstr *MI, int OpNum) {}
129 void printNegZeroOperand(const MachineInstr *MI, int OpNum) {}
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printMandatoryPredicateOperand(const MachineInstr *MI, int OpNum);
132 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
133 void printPCLabel(const MachineInstr *MI, int OpNum);
134 void printRegisterList(const MachineInstr *MI, int OpNum);
135 void printCPInstOperand(const MachineInstr *MI, int OpNum,
136 const char *Modifier);
137 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
138 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
139 void printTBAddrMode(const MachineInstr *MI, int OpNum);
140 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
141 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
142 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
144 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
145 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
147 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
148 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
150 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
151 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
153 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
154 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
157 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
158 unsigned AsmVariant, const char *ExtraCode);
159 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
161 const char *ExtraCode);
163 void printInstruction(const MachineInstr *MI); // autogenerated.
164 static const char *getRegisterName(unsigned RegNo);
166 virtual void EmitInstruction(const MachineInstr *MI);
167 bool runOnMachineFunction(MachineFunction &F);
169 virtual void EmitConstantPool() {} // we emit constant pools customly!
170 virtual void EmitFunctionEntryLabel();
171 void EmitStartOfAsmFile(Module &M);
172 void EmitEndOfAsmFile(Module &M);
174 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
175 const MachineBasicBlock *MBB) const;
176 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
178 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
180 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
181 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
182 case 1: O << MAI->getData8bitsDirective(0); break;
183 case 2: O << MAI->getData16bitsDirective(0); break;
184 case 4: O << MAI->getData32bitsDirective(0); break;
185 default: assert(0 && "Unknown CPV size");
188 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
189 SmallString<128> TmpNameStr;
191 if (ACPV->isLSDA()) {
192 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
193 "_LSDA_" << getFunctionNumber();
194 O << TmpNameStr.str();
195 } else if (ACPV->isBlockAddress()) {
196 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
197 } else if (ACPV->isGlobalValue()) {
198 GlobalValue *GV = ACPV->getGV();
199 bool isIndirect = Subtarget->isTargetDarwin() &&
200 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
202 O << *Mang->getSymbol(GV);
204 // FIXME: Remove this when Darwin transition to @GOT like syntax.
205 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
208 MachineModuleInfoMachO &MMIMachO =
209 MMI->getObjFileInfo<MachineModuleInfoMachO>();
210 MachineModuleInfoImpl::StubValueTy &StubSym =
211 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
212 MMIMachO.getGVStubEntry(Sym);
213 if (StubSym.getPointer() == 0)
214 StubSym = MachineModuleInfoImpl::
215 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
218 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
219 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
222 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
223 if (ACPV->getPCAdjustment() != 0) {
224 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
225 << getFunctionNumber() << "_" << ACPV->getLabelId()
226 << "+" << (unsigned)ACPV->getPCAdjustment();
227 if (ACPV->mustAddCurrentAddress())
231 OutStreamer.AddBlankLine();
234 void getAnalysisUsage(AnalysisUsage &AU) const {
235 AsmPrinter::getAnalysisUsage(AU);
236 AU.setPreservesAll();
237 AU.addRequired<MachineModuleInfo>();
238 AU.addRequired<DwarfWriter>();
241 } // end of anonymous namespace
243 #include "ARMGenAsmWriter.inc"
245 void ARMAsmPrinter::EmitFunctionEntryLabel() {
246 if (AFI->isThumbFunction()) {
247 O << "\t.code\t16\n";
248 O << "\t.thumb_func";
249 if (Subtarget->isTargetDarwin())
250 O << '\t' << *CurrentFnSym;
254 OutStreamer.EmitLabel(CurrentFnSym);
257 /// runOnMachineFunction - This uses the printInstruction()
258 /// method to print assembly for each instruction.
260 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
261 AFI = MF.getInfo<ARMFunctionInfo>();
262 MCP = MF.getConstantPool();
264 return AsmPrinter::runOnMachineFunction(MF);
267 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
268 const char *Modifier) {
269 const MachineOperand &MO = MI->getOperand(OpNum);
270 unsigned TF = MO.getTargetFlags();
272 switch (MO.getType()) {
274 assert(0 && "<unknown operand type>");
275 case MachineOperand::MO_Register: {
276 unsigned Reg = MO.getReg();
277 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
278 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
279 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
280 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
282 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
284 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
285 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
286 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
287 &ARM::DPR_VFP2RegClass);
288 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
290 assert(!MO.getSubReg() && "Subregs should be eliminated!");
291 O << getRegisterName(Reg);
295 case MachineOperand::MO_Immediate: {
296 int64_t Imm = MO.getImm();
298 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
299 (TF & ARMII::MO_LO16))
301 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
302 (TF & ARMII::MO_HI16))
307 case MachineOperand::MO_MachineBasicBlock:
308 O << *MO.getMBB()->getSymbol();
310 case MachineOperand::MO_GlobalAddress: {
311 bool isCallOp = Modifier && !strcmp(Modifier, "call");
312 GlobalValue *GV = MO.getGlobal();
314 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
315 (TF & ARMII::MO_LO16))
317 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
318 (TF & ARMII::MO_HI16))
320 O << *Mang->getSymbol(GV);
322 printOffset(MO.getOffset(), O);
324 if (isCallOp && Subtarget->isTargetELF() &&
325 TM.getRelocationModel() == Reloc::PIC_)
329 case MachineOperand::MO_ExternalSymbol: {
330 bool isCallOp = Modifier && !strcmp(Modifier, "call");
331 O << *GetExternalSymbolSymbol(MO.getSymbolName());
333 if (isCallOp && Subtarget->isTargetELF() &&
334 TM.getRelocationModel() == Reloc::PIC_)
338 case MachineOperand::MO_ConstantPoolIndex:
339 O << *GetCPISymbol(MO.getIndex());
341 case MachineOperand::MO_JumpTableIndex:
342 O << *GetJTISymbol(MO.getIndex());
347 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
348 const MCAsmInfo *MAI) {
349 // Break it up into two parts that make up a shifter immediate.
350 V = ARM_AM::getSOImmVal(V);
351 assert(V != -1 && "Not a valid so_imm value!");
353 unsigned Imm = ARM_AM::getSOImmValImm(V);
354 unsigned Rot = ARM_AM::getSOImmValRot(V);
356 // Print low-level immediate formation info, per
357 // A5.1.3: "Data-processing operands - Immediate".
359 O << "#" << Imm << ", " << Rot;
360 // Pretty printed version.
362 O.PadToColumn(MAI->getCommentColumn());
363 O << MAI->getCommentString() << ' ';
364 O << (int)ARM_AM::rotr32(Imm, Rot);
371 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
372 /// immediate in bits 0-7.
373 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
374 const MachineOperand &MO = MI->getOperand(OpNum);
375 assert(MO.isImm() && "Not a valid so_imm value!");
376 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
379 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
380 /// followed by an 'orr' to materialize.
381 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
382 const MachineOperand &MO = MI->getOperand(OpNum);
383 assert(MO.isImm() && "Not a valid so_imm value!");
384 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
385 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
386 printSOImm(O, V1, VerboseAsm, MAI);
388 printPredicateOperand(MI, 2);
394 printSOImm(O, V2, VerboseAsm, MAI);
397 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
398 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
400 // REG REG 0,SH_OPC - e.g. R5, ROR R3
401 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
402 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
403 const MachineOperand &MO1 = MI->getOperand(Op);
404 const MachineOperand &MO2 = MI->getOperand(Op+1);
405 const MachineOperand &MO3 = MI->getOperand(Op+2);
407 O << getRegisterName(MO1.getReg());
409 // Print the shift opc.
411 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
415 O << getRegisterName(MO2.getReg());
416 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
418 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
422 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
423 const MachineOperand &MO1 = MI->getOperand(Op);
424 const MachineOperand &MO2 = MI->getOperand(Op+1);
425 const MachineOperand &MO3 = MI->getOperand(Op+2);
427 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
428 printOperand(MI, Op);
432 O << "[" << getRegisterName(MO1.getReg());
435 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
437 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
438 << ARM_AM::getAM2Offset(MO3.getImm());
444 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
445 << getRegisterName(MO2.getReg());
447 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
449 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
454 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
455 const MachineOperand &MO1 = MI->getOperand(Op);
456 const MachineOperand &MO2 = MI->getOperand(Op+1);
459 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
460 assert(ImmOffs && "Malformed indexed load / store!");
462 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
467 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
468 << getRegisterName(MO1.getReg());
470 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
472 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
476 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
477 const MachineOperand &MO1 = MI->getOperand(Op);
478 const MachineOperand &MO2 = MI->getOperand(Op+1);
479 const MachineOperand &MO3 = MI->getOperand(Op+2);
481 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
482 O << "[" << getRegisterName(MO1.getReg());
486 << (char)ARM_AM::getAM3Op(MO3.getImm())
487 << getRegisterName(MO2.getReg())
492 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
494 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
499 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
500 const MachineOperand &MO1 = MI->getOperand(Op);
501 const MachineOperand &MO2 = MI->getOperand(Op+1);
504 O << (char)ARM_AM::getAM3Op(MO2.getImm())
505 << getRegisterName(MO1.getReg());
509 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
510 assert(ImmOffs && "Malformed indexed load / store!");
512 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
516 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
517 const char *Modifier) {
518 const MachineOperand &MO2 = MI->getOperand(Op+1);
519 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
520 if (Modifier && strcmp(Modifier, "submode") == 0) {
521 O << ARM_AM::getAMSubModeStr(Mode);
522 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
523 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
524 if (Mode == ARM_AM::ia)
527 printOperand(MI, Op);
531 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
532 const char *Modifier) {
533 const MachineOperand &MO1 = MI->getOperand(Op);
534 const MachineOperand &MO2 = MI->getOperand(Op+1);
536 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
537 printOperand(MI, Op);
541 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
543 if (Modifier && strcmp(Modifier, "submode") == 0) {
544 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
545 O << ARM_AM::getAMSubModeStr(Mode);
547 } else if (Modifier && strcmp(Modifier, "base") == 0) {
548 // Used for FSTM{D|S} and LSTM{D|S} operations.
549 O << getRegisterName(MO1.getReg());
553 O << "[" << getRegisterName(MO1.getReg());
555 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
557 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
563 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
564 const MachineOperand &MO1 = MI->getOperand(Op);
565 const MachineOperand &MO2 = MI->getOperand(Op+1);
567 O << "[" << getRegisterName(MO1.getReg());
569 // FIXME: Both darwin as and GNU as violate ARM docs here.
570 O << ", :" << MO2.getImm();
575 void ARMAsmPrinter::printAddrMode6OffsetOperand(const MachineInstr *MI, int Op){
576 const MachineOperand &MO = MI->getOperand(Op);
577 if (MO.getReg() == 0)
580 O << ", " << getRegisterName(MO.getReg());
583 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
584 const char *Modifier) {
585 if (Modifier && strcmp(Modifier, "label") == 0) {
586 printPCLabel(MI, Op+1);
590 const MachineOperand &MO1 = MI->getOperand(Op);
591 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
592 O << "[pc, " << getRegisterName(MO1.getReg()) << "]";
596 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
597 const MachineOperand &MO = MI->getOperand(Op);
598 uint32_t v = ~MO.getImm();
599 int32_t lsb = CountTrailingZeros_32(v);
600 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
601 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
602 O << "#" << lsb << ", #" << width;
605 //===--------------------------------------------------------------------===//
607 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
608 O << "#" << MI->getOperand(Op).getImm() * 4;
612 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
613 // (3 - the number of trailing zeros) is the number of then / else.
614 unsigned Mask = MI->getOperand(Op).getImm();
615 unsigned CondBit0 = Mask >> 4 & 1;
616 unsigned NumTZ = CountTrailingZeros_32(Mask);
617 assert(NumTZ <= 3 && "Invalid IT mask!");
618 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
619 bool T = ((Mask >> Pos) & 1) == CondBit0;
628 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
629 const MachineOperand &MO1 = MI->getOperand(Op);
630 const MachineOperand &MO2 = MI->getOperand(Op+1);
631 O << "[" << getRegisterName(MO1.getReg());
632 O << ", " << getRegisterName(MO2.getReg()) << "]";
636 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
638 const MachineOperand &MO1 = MI->getOperand(Op);
639 const MachineOperand &MO2 = MI->getOperand(Op+1);
640 const MachineOperand &MO3 = MI->getOperand(Op+2);
642 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
643 printOperand(MI, Op);
647 O << "[" << getRegisterName(MO1.getReg());
649 O << ", " << getRegisterName(MO3.getReg());
650 else if (unsigned ImmOffs = MO2.getImm())
651 O << ", #" << ImmOffs * Scale;
656 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
657 printThumbAddrModeRI5Operand(MI, Op, 1);
660 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
661 printThumbAddrModeRI5Operand(MI, Op, 2);
664 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
665 printThumbAddrModeRI5Operand(MI, Op, 4);
668 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
669 const MachineOperand &MO1 = MI->getOperand(Op);
670 const MachineOperand &MO2 = MI->getOperand(Op+1);
671 O << "[" << getRegisterName(MO1.getReg());
672 if (unsigned ImmOffs = MO2.getImm())
673 O << ", #" << ImmOffs*4;
677 //===--------------------------------------------------------------------===//
679 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
680 // register with shift forms.
682 // REG IMM, SH_OPC - e.g. R5, LSL #3
683 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
684 const MachineOperand &MO1 = MI->getOperand(OpNum);
685 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
687 unsigned Reg = MO1.getReg();
688 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
689 O << getRegisterName(Reg);
691 // Print the shift opc.
693 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
696 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
697 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
700 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
702 const MachineOperand &MO1 = MI->getOperand(OpNum);
703 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
705 O << "[" << getRegisterName(MO1.getReg());
707 unsigned OffImm = MO2.getImm();
708 if (OffImm) // Don't print +0.
709 O << ", #" << OffImm;
713 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
715 const MachineOperand &MO1 = MI->getOperand(OpNum);
716 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
718 O << "[" << getRegisterName(MO1.getReg());
720 int32_t OffImm = (int32_t)MO2.getImm();
723 O << ", #-" << -OffImm;
725 O << ", #" << OffImm;
729 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
731 const MachineOperand &MO1 = MI->getOperand(OpNum);
732 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
734 O << "[" << getRegisterName(MO1.getReg());
736 int32_t OffImm = (int32_t)MO2.getImm() / 4;
739 O << ", #-" << -OffImm * 4;
741 O << ", #" << OffImm * 4;
745 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
747 const MachineOperand &MO1 = MI->getOperand(OpNum);
748 int32_t OffImm = (int32_t)MO1.getImm();
751 O << "#-" << -OffImm;
756 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
758 const MachineOperand &MO1 = MI->getOperand(OpNum);
759 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
760 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
762 O << "[" << getRegisterName(MO1.getReg());
764 assert(MO2.getReg() && "Invalid so_reg load / store address!");
765 O << ", " << getRegisterName(MO2.getReg());
767 unsigned ShAmt = MO3.getImm();
769 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
770 O << ", lsl #" << ShAmt;
776 //===--------------------------------------------------------------------===//
778 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
779 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
781 O << ARMCondCodeToString(CC);
784 void ARMAsmPrinter::printMandatoryPredicateOperand(const MachineInstr *MI,
786 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
787 O << ARMCondCodeToString(CC);
790 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
791 unsigned Reg = MI->getOperand(OpNum).getReg();
793 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
798 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
799 int Id = (int)MI->getOperand(OpNum).getImm();
800 O << MAI->getPrivateGlobalPrefix()
801 << "PC" << getFunctionNumber() << "_" << Id;
804 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
806 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
807 if (MI->getOperand(i).isImplicit())
809 if ((int)i != OpNum) O << ", ";
815 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
816 const char *Modifier) {
817 assert(Modifier && "This operand only works with a modifier!");
818 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
820 if (!strcmp(Modifier, "label")) {
821 unsigned ID = MI->getOperand(OpNum).getImm();
822 OutStreamer.EmitLabel(GetCPISymbol(ID));
824 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
825 unsigned CPI = MI->getOperand(OpNum).getIndex();
827 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
829 if (MCPE.isMachineConstantPoolEntry()) {
830 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
832 EmitGlobalConstant(MCPE.Val.ConstVal);
837 MCSymbol *ARMAsmPrinter::
838 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
839 const MachineBasicBlock *MBB) const {
840 SmallString<60> Name;
841 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
842 << getFunctionNumber() << '_' << uid << '_' << uid2
843 << "_set_" << MBB->getNumber();
844 return OutContext.GetOrCreateSymbol(Name.str());
847 MCSymbol *ARMAsmPrinter::
848 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
849 SmallString<60> Name;
850 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
851 << getFunctionNumber() << '_' << uid << '_' << uid2;
852 return OutContext.GetOrCreateSymbol(Name.str());
855 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
856 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
858 const MachineOperand &MO1 = MI->getOperand(OpNum);
859 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
861 unsigned JTI = MO1.getIndex();
862 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
863 OutStreamer.EmitLabel(JTISymbol);
865 const char *JTEntryDirective = MAI->getData32bitsDirective();
867 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
868 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
869 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
870 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
871 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
872 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
873 MachineBasicBlock *MBB = JTBBs[i];
874 bool isNew = JTSets.insert(MBB);
876 if (UseSet && isNew) {
878 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
879 << *MBB->getSymbol() << '-' << *JTISymbol << '\n';
882 O << JTEntryDirective << ' ';
884 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
885 else if (TM.getRelocationModel() == Reloc::PIC_)
886 O << *MBB->getSymbol() << '-' << *JTISymbol;
888 O << *MBB->getSymbol();
895 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
896 const MachineOperand &MO1 = MI->getOperand(OpNum);
897 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
898 unsigned JTI = MO1.getIndex();
900 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
901 OutStreamer.EmitLabel(JTISymbol);
903 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
904 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
905 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
906 bool ByteOffset = false, HalfWordOffset = false;
907 if (MI->getOpcode() == ARM::t2TBB)
909 else if (MI->getOpcode() == ARM::t2TBH)
910 HalfWordOffset = true;
912 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
913 MachineBasicBlock *MBB = JTBBs[i];
915 O << MAI->getData8bitsDirective();
916 else if (HalfWordOffset)
917 O << MAI->getData16bitsDirective();
919 if (ByteOffset || HalfWordOffset)
920 O << '(' << *MBB->getSymbol() << "-" << *JTISymbol << ")/2";
922 O << "\tb.w " << *MBB->getSymbol();
928 // Make sure the instruction that follows TBB is 2-byte aligned.
929 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
930 if (ByteOffset && (JTBBs.size() & 1)) {
936 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
937 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
938 if (MI->getOpcode() == ARM::t2TBH)
943 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
944 O << MI->getOperand(OpNum).getImm();
947 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
948 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
949 O << '#' << FP->getValueAPF().convertToFloat();
951 O.PadToColumn(MAI->getCommentColumn());
952 O << MAI->getCommentString() << ' ';
953 WriteAsOperand(O, FP, /*PrintType=*/false);
957 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
958 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
959 O << '#' << FP->getValueAPF().convertToDouble();
961 O.PadToColumn(MAI->getCommentColumn());
962 O << MAI->getCommentString() << ' ';
963 WriteAsOperand(O, FP, /*PrintType=*/false);
967 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
968 unsigned AsmVariant, const char *ExtraCode){
969 // Does this asm operand have a single letter operand modifier?
970 if (ExtraCode && ExtraCode[0]) {
971 if (ExtraCode[1] != 0) return true; // Unknown modifier.
973 switch (ExtraCode[0]) {
974 default: return true; // Unknown modifier.
975 case 'a': // Print as a memory address.
976 if (MI->getOperand(OpNum).isReg()) {
977 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
981 case 'c': // Don't print "#" before an immediate operand.
982 if (!MI->getOperand(OpNum).isImm())
984 printNoHashImmediate(MI, OpNum);
986 case 'P': // Print a VFP double precision register.
987 case 'q': // Print a NEON quad precision register.
988 printOperand(MI, OpNum);
991 if (TM.getTargetData()->isLittleEndian())
995 if (TM.getTargetData()->isBigEndian())
998 case 'H': // Write second word of DI / DF reference.
999 // Verify that this operand has two consecutive registers.
1000 if (!MI->getOperand(OpNum).isReg() ||
1001 OpNum+1 == MI->getNumOperands() ||
1002 !MI->getOperand(OpNum+1).isReg())
1004 ++OpNum; // Return the high-part.
1008 printOperand(MI, OpNum);
1012 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1013 unsigned OpNum, unsigned AsmVariant,
1014 const char *ExtraCode) {
1015 if (ExtraCode && ExtraCode[0])
1016 return true; // Unknown modifier.
1018 const MachineOperand &MO = MI->getOperand(OpNum);
1019 assert(MO.isReg() && "unexpected inline asm memory operand");
1020 O << "[" << getRegisterName(MO.getReg()) << "]";
1024 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1026 printInstructionThroughMCStreamer(MI);
1028 int Opc = MI->getOpcode();
1029 if (Opc == ARM::CONSTPOOL_ENTRY)
1032 printInstruction(MI);
1033 OutStreamer.AddBlankLine();
1037 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1038 if (Subtarget->isTargetDarwin()) {
1039 Reloc::Model RelocM = TM.getRelocationModel();
1040 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1041 // Declare all the text sections up front (before the DWARF sections
1042 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1043 // them together at the beginning of the object file. This helps
1044 // avoid out-of-range branches that are due a fundamental limitation of
1045 // the way symbol offsets are encoded with the current Darwin ARM
1047 TargetLoweringObjectFileMachO &TLOFMacho =
1048 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1049 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1050 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1051 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1052 if (RelocM == Reloc::DynamicNoPIC) {
1053 const MCSection *sect =
1054 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1055 MCSectionMachO::S_SYMBOL_STUBS,
1056 12, SectionKind::getText());
1057 OutStreamer.SwitchSection(sect);
1059 const MCSection *sect =
1060 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1061 MCSectionMachO::S_SYMBOL_STUBS,
1062 16, SectionKind::getText());
1063 OutStreamer.SwitchSection(sect);
1068 // Use unified assembler syntax.
1069 O << "\t.syntax unified\n";
1071 // Emit ARM Build Attributes
1072 if (Subtarget->isTargetELF()) {
1074 std::string CPUString = Subtarget->getCPUString();
1075 if (CPUString != "generic")
1076 O << "\t.cpu " << CPUString << '\n';
1078 // FIXME: Emit FPU type
1079 if (Subtarget->hasVFP2())
1080 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1082 // Signal various FP modes.
1084 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1085 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1087 if (FiniteOnlyFPMath())
1088 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1090 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1092 // 8-bytes alignment stuff.
1093 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1094 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1096 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1097 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1098 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1099 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1101 // FIXME: Should we signal R9 usage?
1106 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1107 if (Subtarget->isTargetDarwin()) {
1108 // All darwin targets use mach-o.
1109 TargetLoweringObjectFileMachO &TLOFMacho =
1110 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1111 MachineModuleInfoMachO &MMIMacho =
1112 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1116 // Output non-lazy-pointers for external and common global variables.
1117 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1119 if (!Stubs.empty()) {
1120 // Switch with ".non_lazy_symbol_pointer" directive.
1121 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1123 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1125 OutStreamer.EmitLabel(Stubs[i].first);
1126 // .indirect_symbol _foo
1127 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
1128 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
1131 // External to current translation unit.
1132 OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
1134 // Internal to current translation unit.
1136 // When we place the LSDA into the TEXT section, the type info pointers
1137 // need to be indirect and pc-rel. We accomplish this by using NLPs.
1138 // However, sometimes the types are local to the file. So we need to
1139 // fill in the value for the NLP in those cases.
1140 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
1142 4/*size*/, 0/*addrspace*/);
1146 OutStreamer.AddBlankLine();
1149 Stubs = MMIMacho.GetHiddenGVStubList();
1150 if (!Stubs.empty()) {
1151 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1153 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1155 OutStreamer.EmitLabel(Stubs[i].first);
1157 OutStreamer.EmitValue(MCSymbolRefExpr::
1158 Create(Stubs[i].second.getPointer(),
1160 4/*size*/, 0/*addrspace*/);
1164 OutStreamer.AddBlankLine();
1167 // Funny Darwin hack: This flag tells the linker that no global symbols
1168 // contain code that falls through to other global symbols (e.g. the obvious
1169 // implementation of multiple entry points). If this doesn't occur, the
1170 // linker can safely perform dead code stripping. Since LLVM never
1171 // generates code that does this, it is always safe to set.
1172 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1176 //===----------------------------------------------------------------------===//
1178 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1179 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1180 switch (MI->getOpcode()) {
1181 case ARM::t2MOVi32imm:
1182 assert(0 && "Should be lowered by thumb2it pass");
1184 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1185 // This is a pseudo op for a label + instruction sequence, which looks like:
1188 // This adds the address of LPC0 to r0.
1191 // FIXME: MOVE TO SHARED PLACE.
1192 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1193 const char *Prefix = MAI->getPrivateGlobalPrefix();
1194 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1195 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1196 OutStreamer.EmitLabel(Label);
1199 // Form and emit tha dd.
1201 AddInst.setOpcode(ARM::ADDrr);
1202 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1203 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1204 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1205 OutStreamer.EmitInstruction(AddInst);
1208 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1209 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1210 /// in the function. The first operand is the ID# for this instruction, the
1211 /// second is the index into the MachineConstantPool that this is, the third
1212 /// is the size in bytes of this constant pool entry.
1213 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1214 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1217 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1219 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1220 if (MCPE.isMachineConstantPoolEntry())
1221 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1223 EmitGlobalConstant(MCPE.Val.ConstVal);
1227 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1228 // This is a hack that lowers as a two instruction sequence.
1229 unsigned DstReg = MI->getOperand(0).getReg();
1230 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1232 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1233 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1237 TmpInst.setOpcode(ARM::MOVi);
1238 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1239 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1242 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1243 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1245 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1246 OutStreamer.EmitInstruction(TmpInst);
1251 TmpInst.setOpcode(ARM::ORRri);
1252 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1253 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1254 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1256 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1257 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1259 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1260 OutStreamer.EmitInstruction(TmpInst);
1264 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1265 // This is a hack that lowers as a two instruction sequence.
1266 unsigned DstReg = MI->getOperand(0).getReg();
1267 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1271 TmpInst.setOpcode(ARM::MOVi16);
1272 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1273 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1276 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1277 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1279 OutStreamer.EmitInstruction(TmpInst);
1284 TmpInst.setOpcode(ARM::MOVTi16);
1285 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1286 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1287 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1290 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1291 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1293 OutStreamer.EmitInstruction(TmpInst);
1301 MCInstLowering.Lower(MI, TmpInst);
1302 OutStreamer.EmitInstruction(TmpInst);
1305 //===----------------------------------------------------------------------===//
1306 // Target Registry Stuff
1307 //===----------------------------------------------------------------------===//
1309 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1310 unsigned SyntaxVariant,
1311 const MCAsmInfo &MAI,
1313 if (SyntaxVariant == 0)
1314 return new ARMInstPrinter(O, MAI, false);
1318 // Force static initialization.
1319 extern "C" void LLVMInitializeARMAsmPrinter() {
1320 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1321 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1323 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1324 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);