1 // The LLVM Compiler Infrastructure
3 // This file is distributed under the University of Illinois Open Source
4 // License. See LICENSE.TXT for details.
6 //===----------------------------------------------------------------------===//
8 // This file contains a printer that converts from our internal representation
9 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBuildAttrs.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMInstPrinter.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Module.h"
23 #include "llvm/Assembly/Writer.h"
24 #include "llvm/CodeGen/AsmPrinter.h"
25 #include "llvm/CodeGen/DwarfWriter.h"
26 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
28 #include "llvm/CodeGen/MachineJumpTableInfo.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCContext.h"
31 #include "llvm/MC/MCSectionMachO.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSymbol.h"
34 #include "llvm/Target/TargetData.h"
35 #include "llvm/Target/TargetLoweringObjectFile.h"
36 #include "llvm/Target/TargetMachine.h"
37 #include "llvm/Target/TargetOptions.h"
38 #include "llvm/Target/TargetRegistry.h"
39 #include "llvm/ADT/SmallPtrSet.h"
40 #include "llvm/ADT/SmallString.h"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/ADT/StringSet.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/Mangler.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/FormattedStream.h"
50 STATISTIC(EmittedInsts, "Number of machine instrs printed");
53 class ARMAsmPrinter : public AsmPrinter {
55 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
56 /// make the right decision when printing asm code for different targets.
57 const ARMSubtarget *Subtarget;
59 /// AFI - Keep a pointer to ARMFunctionInfo for the current
63 /// MCP - Keep a pointer to constantpool entries of the current
65 const MachineConstantPool *MCP;
68 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
69 const MCAsmInfo *T, bool V)
70 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
71 Subtarget = &TM.getSubtarget<ARMSubtarget>();
74 virtual const char *getPassName() const {
75 return "ARM Assembly Printer";
78 void printMCInst(const MCInst *MI) {
79 ARMInstPrinter(O, *MAI).printInstruction(MI);
82 void printOperand(const MachineInstr *MI, int OpNum,
83 const char *Modifier = 0);
84 void printSOImmOperand(const MachineInstr *MI, int OpNum);
85 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
86 void printSORegOperand(const MachineInstr *MI, int OpNum);
87 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
88 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
89 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
90 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
91 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
92 const char *Modifier = 0);
93 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
94 const char *Modifier = 0);
95 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
96 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
97 const char *Modifier = 0);
98 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
100 void printThumbITMask(const MachineInstr *MI, int OpNum);
101 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
102 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
104 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
105 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
106 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
107 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
109 void printT2SOOperand(const MachineInstr *MI, int OpNum);
110 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
111 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
112 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
113 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
114 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
116 void printPredicateOperand(const MachineInstr *MI, int OpNum);
117 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
118 void printPCLabel(const MachineInstr *MI, int OpNum);
119 void printRegisterList(const MachineInstr *MI, int OpNum);
120 void printCPInstOperand(const MachineInstr *MI, int OpNum,
121 const char *Modifier);
122 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
123 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
124 void printTBAddrMode(const MachineInstr *MI, int OpNum);
125 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
127 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
128 unsigned AsmVariant, const char *ExtraCode);
129 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
131 const char *ExtraCode);
133 void PrintGlobalVariable(const GlobalVariable* GVar);
134 void printInstruction(const MachineInstr *MI); // autogenerated.
135 static const char *getRegisterName(unsigned RegNo);
137 void printMachineInstruction(const MachineInstr *MI);
138 bool runOnMachineFunction(MachineFunction &F);
139 void EmitStartOfAsmFile(Module &M);
140 void EmitEndOfAsmFile(Module &M);
142 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
144 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
145 printDataDirective(MCPV->getType());
147 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
148 GlobalValue *GV = ACPV->getGV();
151 if (ACPV->isLSDA()) {
152 SmallString<16> LSDAName;
153 raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
154 "_LSDA_" << getFunctionNumber();
155 Name = LSDAName.str();
157 bool isIndirect = Subtarget->isTargetDarwin() &&
158 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
160 Name = Mang->getMangledName(GV);
162 // FIXME: Remove this when Darwin transition to @GOT like syntax.
163 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
164 MCSymbol *Sym = OutContext.GetOrCreateSymbol(Name.c_str());
166 MachineModuleInfoMachO &MMIMachO =
167 MMI->getObjFileInfo<MachineModuleInfoMachO>();
168 const MCSymbol *&StubSym =
169 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
170 MMIMachO.getGVStubEntry(Sym);
172 SmallString<128> NameStr;
173 Mang->getNameWithPrefix(NameStr, GV, false);
174 StubSym = OutContext.GetOrCreateSymbol(NameStr.str());
178 Name = Mang->makeNameProper(ACPV->getSymbol());
181 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
182 if (ACPV->getPCAdjustment() != 0) {
183 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
184 << ACPV->getLabelId()
185 << "+" << (unsigned)ACPV->getPCAdjustment();
186 if (ACPV->mustAddCurrentAddress())
193 void getAnalysisUsage(AnalysisUsage &AU) const {
194 AsmPrinter::getAnalysisUsage(AU);
195 AU.setPreservesAll();
196 AU.addRequired<MachineModuleInfo>();
197 AU.addRequired<DwarfWriter>();
200 } // end of anonymous namespace
202 #include "ARMGenAsmWriter.inc"
204 /// runOnMachineFunction - This uses the printInstruction()
205 /// method to print assembly for each instruction.
207 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
210 AFI = MF.getInfo<ARMFunctionInfo>();
211 MCP = MF.getConstantPool();
213 SetupMachineFunction(MF);
216 // NOTE: we don't print out constant pools here, they are handled as
221 // Print out labels for the function.
222 const Function *F = MF.getFunction();
223 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
225 switch (F->getLinkage()) {
226 default: llvm_unreachable("Unknown linkage type!");
227 case Function::PrivateLinkage:
228 case Function::InternalLinkage:
230 case Function::ExternalLinkage:
231 O << "\t.globl\t" << CurrentFnName << "\n";
233 case Function::LinkerPrivateLinkage:
234 case Function::WeakAnyLinkage:
235 case Function::WeakODRLinkage:
236 case Function::LinkOnceAnyLinkage:
237 case Function::LinkOnceODRLinkage:
238 if (Subtarget->isTargetDarwin()) {
239 O << "\t.globl\t" << CurrentFnName << "\n";
240 O << "\t.weak_definition\t" << CurrentFnName << "\n";
242 O << MAI->getWeakRefDirective() << CurrentFnName << "\n";
247 printVisibility(CurrentFnName, F->getVisibility());
249 unsigned FnAlign = 1 << MF.getAlignment(); // MF alignment is log2.
250 if (AFI->isThumbFunction()) {
251 EmitAlignment(FnAlign, F, AFI->getAlign());
252 O << "\t.code\t16\n";
253 O << "\t.thumb_func";
254 if (Subtarget->isTargetDarwin())
255 O << "\t" << CurrentFnName;
258 EmitAlignment(FnAlign, F);
261 O << CurrentFnName << ":\n";
262 // Emit pre-function debug information.
263 DW->BeginFunction(&MF);
265 if (Subtarget->isTargetDarwin()) {
266 // If the function is empty, then we need to emit *something*. Otherwise,
267 // the function's label might be associated with something that it wasn't
268 // meant to be associated with. We emit a noop in this situation.
269 MachineFunction::iterator I = MF.begin();
271 if (++I == MF.end() && MF.front().empty())
275 // Print out code for the function.
276 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
278 // Print a label for the basic block.
279 if (I != MF.begin()) {
280 EmitBasicBlockStart(I);
282 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
284 // Print the assembly for the instruction.
285 printMachineInstruction(II);
289 if (MAI->hasDotTypeDotSizeDirective())
290 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
292 // Emit post-function debug information.
293 DW->EndFunction(&MF);
298 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
299 const char *Modifier) {
300 const MachineOperand &MO = MI->getOperand(OpNum);
301 switch (MO.getType()) {
302 case MachineOperand::MO_Register: {
303 unsigned Reg = MO.getReg();
304 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
305 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
306 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
307 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
309 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
311 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
312 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
313 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
314 &ARM::DPR_VFP2RegClass);
315 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
317 O << getRegisterName(Reg);
320 llvm_unreachable("not implemented");
323 case MachineOperand::MO_Immediate: {
324 int64_t Imm = MO.getImm();
327 if (strcmp(Modifier, "lo16") == 0)
329 else if (strcmp(Modifier, "hi16") == 0)
335 case MachineOperand::MO_MachineBasicBlock:
336 GetMBBSymbol(MO.getMBB()->getNumber())->print(O, MAI);
338 case MachineOperand::MO_GlobalAddress: {
339 bool isCallOp = Modifier && !strcmp(Modifier, "call");
340 GlobalValue *GV = MO.getGlobal();
341 O << Mang->getMangledName(GV);
343 printOffset(MO.getOffset());
345 if (isCallOp && Subtarget->isTargetELF() &&
346 TM.getRelocationModel() == Reloc::PIC_)
350 case MachineOperand::MO_ExternalSymbol: {
351 bool isCallOp = Modifier && !strcmp(Modifier, "call");
352 std::string Name = Mang->makeNameProper(MO.getSymbolName());
355 if (isCallOp && Subtarget->isTargetELF() &&
356 TM.getRelocationModel() == Reloc::PIC_)
360 case MachineOperand::MO_ConstantPoolIndex:
361 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
362 << '_' << MO.getIndex();
364 case MachineOperand::MO_JumpTableIndex:
365 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
366 << '_' << MO.getIndex();
369 O << "<unknown operand type>"; abort (); break;
373 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
374 const MCAsmInfo *MAI) {
375 // Break it up into two parts that make up a shifter immediate.
376 V = ARM_AM::getSOImmVal(V);
377 assert(V != -1 && "Not a valid so_imm value!");
379 unsigned Imm = ARM_AM::getSOImmValImm(V);
380 unsigned Rot = ARM_AM::getSOImmValRot(V);
382 // Print low-level immediate formation info, per
383 // A5.1.3: "Data-processing operands - Immediate".
385 O << "#" << Imm << ", " << Rot;
386 // Pretty printed version.
388 O << ' ' << MAI->getCommentString()
389 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
395 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
396 /// immediate in bits 0-7.
397 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
398 const MachineOperand &MO = MI->getOperand(OpNum);
399 assert(MO.isImm() && "Not a valid so_imm value!");
400 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
403 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
404 /// followed by an 'orr' to materialize.
405 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
406 const MachineOperand &MO = MI->getOperand(OpNum);
407 assert(MO.isImm() && "Not a valid so_imm value!");
408 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
409 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
410 printSOImm(O, V1, VerboseAsm, MAI);
412 printPredicateOperand(MI, 2);
418 printSOImm(O, V2, VerboseAsm, MAI);
421 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
422 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
424 // REG REG 0,SH_OPC - e.g. R5, ROR R3
425 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
426 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
427 const MachineOperand &MO1 = MI->getOperand(Op);
428 const MachineOperand &MO2 = MI->getOperand(Op+1);
429 const MachineOperand &MO3 = MI->getOperand(Op+2);
431 O << getRegisterName(MO1.getReg());
433 // Print the shift opc.
435 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
439 O << getRegisterName(MO2.getReg());
440 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
442 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
446 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
447 const MachineOperand &MO1 = MI->getOperand(Op);
448 const MachineOperand &MO2 = MI->getOperand(Op+1);
449 const MachineOperand &MO3 = MI->getOperand(Op+2);
451 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
452 printOperand(MI, Op);
456 O << "[" << getRegisterName(MO1.getReg());
459 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
461 << (char)ARM_AM::getAM2Op(MO3.getImm())
462 << ARM_AM::getAM2Offset(MO3.getImm());
468 << (char)ARM_AM::getAM2Op(MO3.getImm())
469 << getRegisterName(MO2.getReg());
471 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
473 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
478 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
479 const MachineOperand &MO1 = MI->getOperand(Op);
480 const MachineOperand &MO2 = MI->getOperand(Op+1);
483 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
484 assert(ImmOffs && "Malformed indexed load / store!");
486 << (char)ARM_AM::getAM2Op(MO2.getImm())
491 O << (char)ARM_AM::getAM2Op(MO2.getImm())
492 << getRegisterName(MO1.getReg());
494 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
496 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
500 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
501 const MachineOperand &MO1 = MI->getOperand(Op);
502 const MachineOperand &MO2 = MI->getOperand(Op+1);
503 const MachineOperand &MO3 = MI->getOperand(Op+2);
505 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
506 O << "[" << getRegisterName(MO1.getReg());
510 << (char)ARM_AM::getAM3Op(MO3.getImm())
511 << getRegisterName(MO2.getReg())
516 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
518 << (char)ARM_AM::getAM3Op(MO3.getImm())
523 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
524 const MachineOperand &MO1 = MI->getOperand(Op);
525 const MachineOperand &MO2 = MI->getOperand(Op+1);
528 O << (char)ARM_AM::getAM3Op(MO2.getImm())
529 << getRegisterName(MO1.getReg());
533 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
534 assert(ImmOffs && "Malformed indexed load / store!");
536 << (char)ARM_AM::getAM3Op(MO2.getImm())
540 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
541 const char *Modifier) {
542 const MachineOperand &MO1 = MI->getOperand(Op);
543 const MachineOperand &MO2 = MI->getOperand(Op+1);
544 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
545 if (Modifier && strcmp(Modifier, "submode") == 0) {
546 if (MO1.getReg() == ARM::SP) {
548 bool isLDM = (MI->getOpcode() == ARM::LDM ||
549 MI->getOpcode() == ARM::LDM_RET ||
550 MI->getOpcode() == ARM::t2LDM ||
551 MI->getOpcode() == ARM::t2LDM_RET);
552 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
554 O << ARM_AM::getAMSubModeStr(Mode);
555 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
556 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
557 if (Mode == ARM_AM::ia)
560 printOperand(MI, Op);
561 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
566 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
567 const char *Modifier) {
568 const MachineOperand &MO1 = MI->getOperand(Op);
569 const MachineOperand &MO2 = MI->getOperand(Op+1);
571 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
572 printOperand(MI, Op);
576 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
578 if (Modifier && strcmp(Modifier, "submode") == 0) {
579 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
580 if (MO1.getReg() == ARM::SP) {
581 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
582 MI->getOpcode() == ARM::FLDMS);
583 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
585 O << ARM_AM::getAMSubModeStr(Mode);
587 } else if (Modifier && strcmp(Modifier, "base") == 0) {
588 // Used for FSTM{D|S} and LSTM{D|S} operations.
589 O << getRegisterName(MO1.getReg());
590 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
595 O << "[" << getRegisterName(MO1.getReg());
597 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
599 << (char)ARM_AM::getAM5Op(MO2.getImm())
605 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
606 const MachineOperand &MO1 = MI->getOperand(Op);
607 const MachineOperand &MO2 = MI->getOperand(Op+1);
608 const MachineOperand &MO3 = MI->getOperand(Op+2);
610 // FIXME: No support yet for specifying alignment.
611 O << "[" << getRegisterName(MO1.getReg()) << "]";
613 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
614 if (MO2.getReg() == 0)
617 O << ", " << getRegisterName(MO2.getReg());
621 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
622 const char *Modifier) {
623 if (Modifier && strcmp(Modifier, "label") == 0) {
624 printPCLabel(MI, Op+1);
628 const MachineOperand &MO1 = MI->getOperand(Op);
629 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
630 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
634 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
635 const MachineOperand &MO = MI->getOperand(Op);
636 uint32_t v = ~MO.getImm();
637 int32_t lsb = CountTrailingZeros_32(v);
638 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
639 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
640 O << "#" << lsb << ", #" << width;
643 //===--------------------------------------------------------------------===//
646 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
647 // (3 - the number of trailing zeros) is the number of then / else.
648 unsigned Mask = MI->getOperand(Op).getImm();
649 unsigned NumTZ = CountTrailingZeros_32(Mask);
650 assert(NumTZ <= 3 && "Invalid IT mask!");
651 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
652 bool T = (Mask & (1 << Pos)) == 0;
661 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
662 const MachineOperand &MO1 = MI->getOperand(Op);
663 const MachineOperand &MO2 = MI->getOperand(Op+1);
664 O << "[" << getRegisterName(MO1.getReg());
665 O << ", " << getRegisterName(MO2.getReg()) << "]";
669 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
671 const MachineOperand &MO1 = MI->getOperand(Op);
672 const MachineOperand &MO2 = MI->getOperand(Op+1);
673 const MachineOperand &MO3 = MI->getOperand(Op+2);
675 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
676 printOperand(MI, Op);
680 O << "[" << getRegisterName(MO1.getReg());
682 O << ", " << getRegisterName(MO3.getReg());
683 else if (unsigned ImmOffs = MO2.getImm()) {
684 O << ", #" << ImmOffs;
692 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
693 printThumbAddrModeRI5Operand(MI, Op, 1);
696 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
697 printThumbAddrModeRI5Operand(MI, Op, 2);
700 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
701 printThumbAddrModeRI5Operand(MI, Op, 4);
704 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
705 const MachineOperand &MO1 = MI->getOperand(Op);
706 const MachineOperand &MO2 = MI->getOperand(Op+1);
707 O << "[" << getRegisterName(MO1.getReg());
708 if (unsigned ImmOffs = MO2.getImm())
709 O << ", #" << ImmOffs << " * 4";
713 //===--------------------------------------------------------------------===//
715 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
716 // register with shift forms.
718 // REG IMM, SH_OPC - e.g. R5, LSL #3
719 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
720 const MachineOperand &MO1 = MI->getOperand(OpNum);
721 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
723 unsigned Reg = MO1.getReg();
724 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
725 O << getRegisterName(Reg);
727 // Print the shift opc.
729 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
732 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
733 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
736 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
738 const MachineOperand &MO1 = MI->getOperand(OpNum);
739 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
741 O << "[" << getRegisterName(MO1.getReg());
743 unsigned OffImm = MO2.getImm();
744 if (OffImm) // Don't print +0.
745 O << ", #+" << OffImm;
749 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
751 const MachineOperand &MO1 = MI->getOperand(OpNum);
752 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
754 O << "[" << getRegisterName(MO1.getReg());
756 int32_t OffImm = (int32_t)MO2.getImm();
759 O << ", #-" << -OffImm;
761 O << ", #+" << OffImm;
765 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
767 const MachineOperand &MO1 = MI->getOperand(OpNum);
768 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
770 O << "[" << getRegisterName(MO1.getReg());
772 int32_t OffImm = (int32_t)MO2.getImm() / 4;
775 O << ", #-" << -OffImm << " * 4";
777 O << ", #+" << OffImm << " * 4";
781 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
783 const MachineOperand &MO1 = MI->getOperand(OpNum);
784 int32_t OffImm = (int32_t)MO1.getImm();
787 O << "#-" << -OffImm;
792 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
794 const MachineOperand &MO1 = MI->getOperand(OpNum);
795 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
796 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
798 O << "[" << getRegisterName(MO1.getReg());
800 assert(MO2.getReg() && "Invalid so_reg load / store address!");
801 O << ", " << getRegisterName(MO2.getReg());
803 unsigned ShAmt = MO3.getImm();
805 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
806 O << ", lsl #" << ShAmt;
812 //===--------------------------------------------------------------------===//
814 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
815 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
817 O << ARMCondCodeToString(CC);
820 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
821 unsigned Reg = MI->getOperand(OpNum).getReg();
823 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
828 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
829 int Id = (int)MI->getOperand(OpNum).getImm();
830 O << MAI->getPrivateGlobalPrefix() << "PC" << Id;
833 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
835 // Always skip the first operand, it's the optional (and implicit writeback).
836 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
837 if (MI->getOperand(i).isImplicit())
839 if ((int)i != OpNum+1) O << ", ";
845 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
846 const char *Modifier) {
847 assert(Modifier && "This operand only works with a modifier!");
848 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
850 if (!strcmp(Modifier, "label")) {
851 unsigned ID = MI->getOperand(OpNum).getImm();
852 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
853 << '_' << ID << ":\n";
855 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
856 unsigned CPI = MI->getOperand(OpNum).getIndex();
858 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
860 if (MCPE.isMachineConstantPoolEntry()) {
861 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
863 EmitGlobalConstant(MCPE.Val.ConstVal);
868 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
869 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
871 const MachineOperand &MO1 = MI->getOperand(OpNum);
872 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
873 unsigned JTI = MO1.getIndex();
874 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
875 << '_' << JTI << '_' << MO2.getImm() << ":\n";
877 const char *JTEntryDirective = MAI->getData32bitsDirective();
879 const MachineFunction *MF = MI->getParent()->getParent();
880 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
881 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
882 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
883 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
884 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
885 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
886 MachineBasicBlock *MBB = JTBBs[i];
887 bool isNew = JTSets.insert(MBB);
890 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
892 O << JTEntryDirective << ' ';
894 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
895 << '_' << JTI << '_' << MO2.getImm()
896 << "_set_" << MBB->getNumber();
897 else if (TM.getRelocationModel() == Reloc::PIC_) {
898 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
899 O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
900 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
902 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
909 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
910 const MachineOperand &MO1 = MI->getOperand(OpNum);
911 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
912 unsigned JTI = MO1.getIndex();
913 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
914 << '_' << JTI << '_' << MO2.getImm() << ":\n";
916 const MachineFunction *MF = MI->getParent()->getParent();
917 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
918 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
919 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
920 bool ByteOffset = false, HalfWordOffset = false;
921 if (MI->getOpcode() == ARM::t2TBB)
923 else if (MI->getOpcode() == ARM::t2TBH)
924 HalfWordOffset = true;
926 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
927 MachineBasicBlock *MBB = JTBBs[i];
929 O << MAI->getData8bitsDirective();
930 else if (HalfWordOffset)
931 O << MAI->getData16bitsDirective();
932 if (ByteOffset || HalfWordOffset) {
934 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
935 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
936 << '_' << JTI << '_' << MO2.getImm() << ")/2";
939 GetMBBSymbol(MBB->getNumber())->print(O, MAI);
945 // Make sure the instruction that follows TBB is 2-byte aligned.
946 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
947 if (ByteOffset && (JTBBs.size() & 1)) {
953 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
954 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
955 if (MI->getOpcode() == ARM::t2TBH)
960 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
961 O << MI->getOperand(OpNum).getImm();
964 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
965 unsigned AsmVariant, const char *ExtraCode){
966 // Does this asm operand have a single letter operand modifier?
967 if (ExtraCode && ExtraCode[0]) {
968 if (ExtraCode[1] != 0) return true; // Unknown modifier.
970 switch (ExtraCode[0]) {
971 default: return true; // Unknown modifier.
972 case 'a': // Print as a memory address.
973 if (MI->getOperand(OpNum).isReg()) {
974 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
978 case 'c': // Don't print "#" before an immediate operand.
979 if (!MI->getOperand(OpNum).isImm())
981 printNoHashImmediate(MI, OpNum);
983 case 'P': // Print a VFP double precision register.
984 printOperand(MI, OpNum);
987 if (TM.getTargetData()->isLittleEndian())
991 if (TM.getTargetData()->isBigEndian())
994 case 'H': // Write second word of DI / DF reference.
995 // Verify that this operand has two consecutive registers.
996 if (!MI->getOperand(OpNum).isReg() ||
997 OpNum+1 == MI->getNumOperands() ||
998 !MI->getOperand(OpNum+1).isReg())
1000 ++OpNum; // Return the high-part.
1004 printOperand(MI, OpNum);
1008 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1009 unsigned OpNum, unsigned AsmVariant,
1010 const char *ExtraCode) {
1011 if (ExtraCode && ExtraCode[0])
1012 return true; // Unknown modifier.
1014 const MachineOperand &MO = MI->getOperand(OpNum);
1015 assert(MO.isReg() && "unexpected inline asm memory operand");
1016 O << "[" << getRegisterName(MO.getReg()) << "]";
1020 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1023 int Opc = MI->getOpcode();
1024 if (Opc == ARM::CONSTPOOL_ENTRY)
1027 // Call the autogenerated instruction printer routines.
1028 processDebugLoc(MI, true);
1029 printInstruction(MI);
1030 if (VerboseAsm && !MI->getDebugLoc().isUnknown())
1033 processDebugLoc(MI, false);
1036 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1037 if (Subtarget->isTargetDarwin()) {
1038 Reloc::Model RelocM = TM.getRelocationModel();
1039 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1040 // Declare all the text sections up front (before the DWARF sections
1041 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1042 // them together at the beginning of the object file. This helps
1043 // avoid out-of-range branches that are due a fundamental limitation of
1044 // the way symbol offsets are encoded with the current Darwin ARM
1046 TargetLoweringObjectFileMachO &TLOFMacho =
1047 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1048 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1049 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1050 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1051 if (RelocM == Reloc::DynamicNoPIC) {
1052 const MCSection *sect =
1053 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1054 MCSectionMachO::S_SYMBOL_STUBS,
1055 12, SectionKind::getText());
1056 OutStreamer.SwitchSection(sect);
1058 const MCSection *sect =
1059 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1060 MCSectionMachO::S_SYMBOL_STUBS,
1061 16, SectionKind::getText());
1062 OutStreamer.SwitchSection(sect);
1067 // Use unified assembler syntax mode for Thumb.
1068 if (Subtarget->isThumb())
1069 O << "\t.syntax unified\n";
1071 // Emit ARM Build Attributes
1072 if (Subtarget->isTargetELF()) {
1074 std::string CPUString = Subtarget->getCPUString();
1075 if (CPUString != "generic")
1076 O << "\t.cpu " << CPUString << '\n';
1078 // FIXME: Emit FPU type
1079 if (Subtarget->hasVFP2())
1080 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1082 // Signal various FP modes.
1084 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1085 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1087 if (FiniteOnlyFPMath())
1088 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1090 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1092 // 8-bytes alignment stuff.
1093 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1094 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1096 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1097 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1098 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1099 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1101 // FIXME: Should we signal R9 usage?
1105 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1106 const TargetData *TD = TM.getTargetData();
1108 if (!GVar->hasInitializer()) // External global require no code
1111 // Check to see if this is a special global used by LLVM, if so, emit it.
1113 if (EmitSpecialLLVMGlobal(GVar)) {
1114 if (Subtarget->isTargetDarwin() &&
1115 TM.getRelocationModel() == Reloc::Static) {
1116 if (GVar->getName() == "llvm.global_ctors")
1117 O << ".reference .constructors_used\n";
1118 else if (GVar->getName() == "llvm.global_dtors")
1119 O << ".reference .destructors_used\n";
1124 std::string name = Mang->getMangledName(GVar);
1125 Constant *C = GVar->getInitializer();
1126 const Type *Type = C->getType();
1127 unsigned Size = TD->getTypeAllocSize(Type);
1128 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1129 bool isDarwin = Subtarget->isTargetDarwin();
1131 printVisibility(name, GVar->getVisibility());
1133 if (Subtarget->isTargetELF())
1134 O << "\t.type " << name << ",%object\n";
1136 const MCSection *TheSection =
1137 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1138 OutStreamer.SwitchSection(TheSection);
1140 // FIXME: get this stuff from section kind flags.
1141 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1142 // Don't put things that should go in the cstring section into "comm".
1143 !TheSection->getKind().isMergeableCString()) {
1144 if (GVar->hasExternalLinkage()) {
1145 if (const char *Directive = MAI->getZeroFillDirective()) {
1146 O << "\t.globl\t" << name << "\n";
1147 O << Directive << "__DATA, __common, " << name << ", "
1148 << Size << ", " << Align << "\n";
1153 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1154 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1157 if (GVar->hasLocalLinkage()) {
1158 O << MAI->getLCOMMDirective() << name << "," << Size
1160 } else if (GVar->hasCommonLinkage()) {
1161 O << MAI->getCOMMDirective() << name << "," << Size
1164 OutStreamer.SwitchSection(TheSection);
1165 O << "\t.globl " << name << '\n'
1166 << MAI->getWeakDefDirective() << name << '\n';
1167 EmitAlignment(Align, GVar);
1170 O << "\t\t\t\t" << MAI->getCommentString() << ' ';
1171 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1174 EmitGlobalConstant(C);
1177 } else if (MAI->getLCOMMDirective() != NULL) {
1178 if (GVar->hasLocalLinkage()) {
1179 O << MAI->getLCOMMDirective() << name << "," << Size;
1181 O << MAI->getCOMMDirective() << name << "," << Size;
1182 if (MAI->getCOMMDirectiveTakesAlignment())
1183 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1186 if (GVar->hasLocalLinkage())
1187 O << "\t.local\t" << name << "\n";
1188 O << MAI->getCOMMDirective() << name << "," << Size;
1189 if (MAI->getCOMMDirectiveTakesAlignment())
1190 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1193 O << "\t\t" << MAI->getCommentString() << " ";
1194 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1201 switch (GVar->getLinkage()) {
1202 case GlobalValue::CommonLinkage:
1203 case GlobalValue::LinkOnceAnyLinkage:
1204 case GlobalValue::LinkOnceODRLinkage:
1205 case GlobalValue::WeakAnyLinkage:
1206 case GlobalValue::WeakODRLinkage:
1207 case GlobalValue::LinkerPrivateLinkage:
1209 O << "\t.globl " << name << "\n"
1210 << "\t.weak_definition " << name << "\n";
1212 O << "\t.weak " << name << "\n";
1215 case GlobalValue::AppendingLinkage:
1216 // FIXME: appending linkage variables should go into a section of
1217 // their name or something. For now, just emit them as external.
1218 case GlobalValue::ExternalLinkage:
1219 O << "\t.globl " << name << "\n";
1221 case GlobalValue::PrivateLinkage:
1222 case GlobalValue::InternalLinkage:
1225 llvm_unreachable("Unknown linkage type!");
1228 EmitAlignment(Align, GVar);
1231 O << "\t\t\t\t" << MAI->getCommentString() << " ";
1232 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1235 if (MAI->hasDotTypeDotSizeDirective())
1236 O << "\t.size " << name << ", " << Size << "\n";
1238 EmitGlobalConstant(C);
1243 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1244 if (Subtarget->isTargetDarwin()) {
1245 // All darwin targets use mach-o.
1246 TargetLoweringObjectFileMachO &TLOFMacho =
1247 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1248 MachineModuleInfoMachO &MMIMacho =
1249 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1253 // Output non-lazy-pointers for external and common global variables.
1254 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1256 if (!Stubs.empty()) {
1257 // Switch with ".non_lazy_symbol_pointer" directive.
1258 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1260 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1261 Stubs[i].first->print(O, MAI);
1262 O << ":\n\t.indirect_symbol ";
1263 Stubs[i].second->print(O, MAI);
1264 O << "\n\t.long\t0\n";
1268 Stubs = MMIMacho.GetHiddenGVStubList();
1269 if (!Stubs.empty()) {
1270 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1272 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1273 Stubs[i].first->print(O, MAI);
1275 Stubs[i].second->print(O, MAI);
1280 // Funny Darwin hack: This flag tells the linker that no global symbols
1281 // contain code that falls through to other global symbols (e.g. the obvious
1282 // implementation of multiple entry points). If this doesn't occur, the
1283 // linker can safely perform dead code stripping. Since LLVM never
1284 // generates code that does this, it is always safe to set.
1285 OutStreamer.EmitAssemblerFlag(MCStreamer::SubsectionsViaSymbols);
1289 // Force static initialization.
1290 extern "C" void LLVMInitializeARMAsmPrinter() {
1291 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1292 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);