1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "asm-printer"
17 #include "ARMBuildAttrs.h"
18 #include "ARMAddressingModes.h"
19 #include "ARMConstantPoolValue.h"
20 #include "ARMInstPrinter.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMMCInstLower.h"
23 #include "ARMTargetMachine.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Module.h"
26 #include "llvm/Type.h"
27 #include "llvm/Assembly/Writer.h"
28 #include "llvm/CodeGen/AsmPrinter.h"
29 #include "llvm/CodeGen/DwarfWriter.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/CodeGen/MachineFunctionPass.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/MC/MCAsmInfo.h"
34 #include "llvm/MC/MCContext.h"
35 #include "llvm/MC/MCInst.h"
36 #include "llvm/MC/MCSectionMachO.h"
37 #include "llvm/MC/MCStreamer.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/Target/TargetData.h"
40 #include "llvm/Target/TargetLoweringObjectFile.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetOptions.h"
43 #include "llvm/Target/TargetRegistry.h"
44 #include "llvm/ADT/SmallPtrSet.h"
45 #include "llvm/ADT/SmallString.h"
46 #include "llvm/ADT/Statistic.h"
47 #include "llvm/ADT/StringExtras.h"
48 #include "llvm/ADT/StringSet.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/ErrorHandling.h"
51 #include "llvm/Support/FormattedStream.h"
52 #include "llvm/Support/MathExtras.h"
56 STATISTIC(EmittedInsts, "Number of machine instrs printed");
59 EnableMCInst("enable-arm-mcinst-printer", cl::Hidden,
60 cl::desc("enable experimental asmprinter gunk in the arm backend"));
63 class ARMAsmPrinter : public AsmPrinter {
65 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
66 /// make the right decision when printing asm code for different targets.
67 const ARMSubtarget *Subtarget;
69 /// AFI - Keep a pointer to ARMFunctionInfo for the current
73 /// MCP - Keep a pointer to constantpool entries of the current
75 const MachineConstantPool *MCP;
78 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
79 const MCAsmInfo *T, bool V)
80 : AsmPrinter(O, TM, T, V), AFI(NULL), MCP(NULL) {
81 Subtarget = &TM.getSubtarget<ARMSubtarget>();
84 virtual const char *getPassName() const {
85 return "ARM Assembly Printer";
88 void printMCInst(const MCInst *MI) {
89 ARMInstPrinter(O, *MAI, VerboseAsm).printInstruction(MI);
92 void printInstructionThroughMCStreamer(const MachineInstr *MI);
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbS4ImmOperand(const MachineInstr *MI, int OpNum);
114 void printThumbITMask(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
116 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
118 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
121 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
123 void printT2SOOperand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
128 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
130 void printPredicateOperand(const MachineInstr *MI, int OpNum);
131 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
132 void printPCLabel(const MachineInstr *MI, int OpNum);
133 void printRegisterList(const MachineInstr *MI, int OpNum);
134 void printCPInstOperand(const MachineInstr *MI, int OpNum,
135 const char *Modifier);
136 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
137 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
138 void printTBAddrMode(const MachineInstr *MI, int OpNum);
139 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 void printVFPf32ImmOperand(const MachineInstr *MI, int OpNum);
141 void printVFPf64ImmOperand(const MachineInstr *MI, int OpNum);
143 void printHex8ImmOperand(const MachineInstr *MI, int OpNum) {
144 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xff);
146 void printHex16ImmOperand(const MachineInstr *MI, int OpNum) {
147 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffff);
149 void printHex32ImmOperand(const MachineInstr *MI, int OpNum) {
150 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm() & 0xffffffff);
152 void printHex64ImmOperand(const MachineInstr *MI, int OpNum) {
153 O << "#0x" << utohexstr(MI->getOperand(OpNum).getImm());
156 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
157 unsigned AsmVariant, const char *ExtraCode);
158 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
160 const char *ExtraCode);
162 void printInstruction(const MachineInstr *MI); // autogenerated.
163 static const char *getRegisterName(unsigned RegNo);
165 void printMachineInstruction(const MachineInstr *MI);
166 bool runOnMachineFunction(MachineFunction &F);
168 virtual void EmitConstantPool() {} // we emit constant pools customly!
169 virtual void EmitFunctionEntryLabel();
170 void EmitStartOfAsmFile(Module &M);
171 void EmitEndOfAsmFile(Module &M);
173 MCSymbol *GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
174 const MachineBasicBlock *MBB) const;
175 MCSymbol *GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const;
177 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
179 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
180 switch (TM.getTargetData()->getTypeAllocSize(MCPV->getType())) {
181 case 1: O << MAI->getData8bitsDirective(0); break;
182 case 2: O << MAI->getData16bitsDirective(0); break;
183 case 4: O << MAI->getData32bitsDirective(0); break;
184 default: assert(0 && "Unknown CPV size");
187 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
188 SmallString<128> TmpNameStr;
190 if (ACPV->isLSDA()) {
191 raw_svector_ostream(TmpNameStr) << MAI->getPrivateGlobalPrefix() <<
192 "_LSDA_" << getFunctionNumber();
193 O << TmpNameStr.str();
194 } else if (ACPV->isBlockAddress()) {
195 O << GetBlockAddressSymbol(ACPV->getBlockAddress())->getName();
196 } else if (ACPV->isGlobalValue()) {
197 GlobalValue *GV = ACPV->getGV();
198 bool isIndirect = Subtarget->isTargetDarwin() &&
199 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
201 O << *GetGlobalValueSymbol(GV);
203 // FIXME: Remove this when Darwin transition to @GOT like syntax.
204 MCSymbol *Sym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
207 MachineModuleInfoMachO &MMIMachO =
208 MMI->getObjFileInfo<MachineModuleInfoMachO>();
209 const MCSymbol *&StubSym =
210 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(Sym) :
211 MMIMachO.getGVStubEntry(Sym);
213 StubSym = GetGlobalValueSymbol(GV);
216 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
217 O << *GetExternalSymbolSymbol(ACPV->getSymbol());
220 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
221 if (ACPV->getPCAdjustment() != 0) {
222 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
223 << getFunctionNumber() << "_" << ACPV->getLabelId()
224 << "+" << (unsigned)ACPV->getPCAdjustment();
225 if (ACPV->mustAddCurrentAddress())
232 void getAnalysisUsage(AnalysisUsage &AU) const {
233 AsmPrinter::getAnalysisUsage(AU);
234 AU.setPreservesAll();
235 AU.addRequired<MachineModuleInfo>();
236 AU.addRequired<DwarfWriter>();
239 } // end of anonymous namespace
241 #include "ARMGenAsmWriter.inc"
243 void ARMAsmPrinter::EmitFunctionEntryLabel() {
244 if (AFI->isThumbFunction()) {
245 O << "\t.code\t16\n";
246 O << "\t.thumb_func";
247 if (Subtarget->isTargetDarwin())
248 O << '\t' << *CurrentFnSym;
252 OutStreamer.EmitLabel(CurrentFnSym);
255 /// runOnMachineFunction - This uses the printInstruction()
256 /// method to print assembly for each instruction.
258 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
259 AFI = MF.getInfo<ARMFunctionInfo>();
260 MCP = MF.getConstantPool();
262 SetupMachineFunction(MF);
265 // NOTE: we don't print out constant pools here, they are handled as
267 EmitFunctionHeader();
269 if (Subtarget->isTargetDarwin()) {
270 // If the function is empty, then we need to emit *something*. Otherwise,
271 // the function's label might be associated with something that it wasn't
272 // meant to be associated with. We emit a noop in this situation.
273 MachineFunction::iterator I = MF.begin();
275 if (++I == MF.end() && MF.front().empty())
279 // Print out code for the function.
280 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
282 // Print a label for the basic block.
284 EmitBasicBlockStart(I);
286 // Print the assembly for the instruction.
287 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
289 printMachineInstruction(II);
292 if (MAI->hasDotTypeDotSizeDirective())
293 O << "\t.size " << *CurrentFnSym << ", .-" << *CurrentFnSym << "\n";
295 // Emit post-function debug information.
296 DW->EndFunction(&MF);
301 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
302 const char *Modifier) {
303 const MachineOperand &MO = MI->getOperand(OpNum);
304 unsigned TF = MO.getTargetFlags();
306 switch (MO.getType()) {
308 assert(0 && "<unknown operand type>");
309 case MachineOperand::MO_Register: {
310 unsigned Reg = MO.getReg();
311 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
312 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
313 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
314 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
316 << getRegisterName(DRegLo) << ',' << getRegisterName(DRegHi)
318 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
319 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
320 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 2 : 1,
321 &ARM::DPR_VFP2RegClass);
322 O << getRegisterName(DReg) << '[' << (RegNum & 1) << ']';
324 assert(!MO.getSubReg() && "Subregs should be eliminated!");
325 O << getRegisterName(Reg);
329 case MachineOperand::MO_Immediate: {
330 int64_t Imm = MO.getImm();
332 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
333 (TF & ARMII::MO_LO16))
335 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
336 (TF & ARMII::MO_HI16))
341 case MachineOperand::MO_MachineBasicBlock:
342 O << *MO.getMBB()->getSymbol(OutContext);
344 case MachineOperand::MO_GlobalAddress: {
345 bool isCallOp = Modifier && !strcmp(Modifier, "call");
346 GlobalValue *GV = MO.getGlobal();
348 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
349 (TF & ARMII::MO_LO16))
351 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
352 (TF & ARMII::MO_HI16))
354 O << *GetGlobalValueSymbol(GV);
356 printOffset(MO.getOffset());
358 if (isCallOp && Subtarget->isTargetELF() &&
359 TM.getRelocationModel() == Reloc::PIC_)
363 case MachineOperand::MO_ExternalSymbol: {
364 bool isCallOp = Modifier && !strcmp(Modifier, "call");
365 O << *GetExternalSymbolSymbol(MO.getSymbolName());
367 if (isCallOp && Subtarget->isTargetELF() &&
368 TM.getRelocationModel() == Reloc::PIC_)
372 case MachineOperand::MO_ConstantPoolIndex:
373 O << *GetCPISymbol(MO.getIndex());
375 case MachineOperand::MO_JumpTableIndex:
376 O << *GetJTISymbol(MO.getIndex());
381 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
382 const MCAsmInfo *MAI) {
383 // Break it up into two parts that make up a shifter immediate.
384 V = ARM_AM::getSOImmVal(V);
385 assert(V != -1 && "Not a valid so_imm value!");
387 unsigned Imm = ARM_AM::getSOImmValImm(V);
388 unsigned Rot = ARM_AM::getSOImmValRot(V);
390 // Print low-level immediate formation info, per
391 // A5.1.3: "Data-processing operands - Immediate".
393 O << "#" << Imm << ", " << Rot;
394 // Pretty printed version.
396 O.PadToColumn(MAI->getCommentColumn());
397 O << MAI->getCommentString() << ' ';
398 O << (int)ARM_AM::rotr32(Imm, Rot);
405 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
406 /// immediate in bits 0-7.
407 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
408 const MachineOperand &MO = MI->getOperand(OpNum);
409 assert(MO.isImm() && "Not a valid so_imm value!");
410 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
413 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
414 /// followed by an 'orr' to materialize.
415 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
416 const MachineOperand &MO = MI->getOperand(OpNum);
417 assert(MO.isImm() && "Not a valid so_imm value!");
418 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
419 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
420 printSOImm(O, V1, VerboseAsm, MAI);
422 printPredicateOperand(MI, 2);
428 printSOImm(O, V2, VerboseAsm, MAI);
431 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
432 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
434 // REG REG 0,SH_OPC - e.g. R5, ROR R3
435 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
436 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
437 const MachineOperand &MO1 = MI->getOperand(Op);
438 const MachineOperand &MO2 = MI->getOperand(Op+1);
439 const MachineOperand &MO3 = MI->getOperand(Op+2);
441 O << getRegisterName(MO1.getReg());
443 // Print the shift opc.
445 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
449 O << getRegisterName(MO2.getReg());
450 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
452 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
456 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
457 const MachineOperand &MO1 = MI->getOperand(Op);
458 const MachineOperand &MO2 = MI->getOperand(Op+1);
459 const MachineOperand &MO3 = MI->getOperand(Op+2);
461 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
462 printOperand(MI, Op);
466 O << "[" << getRegisterName(MO1.getReg());
469 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
471 << (char)ARM_AM::getAM2Op(MO3.getImm())
472 << ARM_AM::getAM2Offset(MO3.getImm());
478 << (char)ARM_AM::getAM2Op(MO3.getImm())
479 << getRegisterName(MO2.getReg());
481 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
483 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
488 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
489 const MachineOperand &MO1 = MI->getOperand(Op);
490 const MachineOperand &MO2 = MI->getOperand(Op+1);
493 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
494 assert(ImmOffs && "Malformed indexed load / store!");
496 << (char)ARM_AM::getAM2Op(MO2.getImm())
501 O << (char)ARM_AM::getAM2Op(MO2.getImm())
502 << getRegisterName(MO1.getReg());
504 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
506 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
510 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
511 const MachineOperand &MO1 = MI->getOperand(Op);
512 const MachineOperand &MO2 = MI->getOperand(Op+1);
513 const MachineOperand &MO3 = MI->getOperand(Op+2);
515 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
516 O << "[" << getRegisterName(MO1.getReg());
520 << (char)ARM_AM::getAM3Op(MO3.getImm())
521 << getRegisterName(MO2.getReg())
526 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
528 << (char)ARM_AM::getAM3Op(MO3.getImm())
533 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
534 const MachineOperand &MO1 = MI->getOperand(Op);
535 const MachineOperand &MO2 = MI->getOperand(Op+1);
538 O << (char)ARM_AM::getAM3Op(MO2.getImm())
539 << getRegisterName(MO1.getReg());
543 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
544 assert(ImmOffs && "Malformed indexed load / store!");
546 << (char)ARM_AM::getAM3Op(MO2.getImm())
550 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
551 const char *Modifier) {
552 const MachineOperand &MO1 = MI->getOperand(Op);
553 const MachineOperand &MO2 = MI->getOperand(Op+1);
554 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
555 if (Modifier && strcmp(Modifier, "submode") == 0) {
556 if (MO1.getReg() == ARM::SP) {
558 bool isLDM = (MI->getOpcode() == ARM::LDM ||
559 MI->getOpcode() == ARM::LDM_RET ||
560 MI->getOpcode() == ARM::t2LDM ||
561 MI->getOpcode() == ARM::t2LDM_RET);
562 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
564 O << ARM_AM::getAMSubModeStr(Mode);
565 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
566 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
567 if (Mode == ARM_AM::ia)
570 printOperand(MI, Op);
571 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
576 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
577 const char *Modifier) {
578 const MachineOperand &MO1 = MI->getOperand(Op);
579 const MachineOperand &MO2 = MI->getOperand(Op+1);
581 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
582 printOperand(MI, Op);
586 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
588 if (Modifier && strcmp(Modifier, "submode") == 0) {
589 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
590 O << ARM_AM::getAMSubModeStr(Mode);
592 } else if (Modifier && strcmp(Modifier, "base") == 0) {
593 // Used for FSTM{D|S} and LSTM{D|S} operations.
594 O << getRegisterName(MO1.getReg());
595 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
600 O << "[" << getRegisterName(MO1.getReg());
602 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
604 << (char)ARM_AM::getAM5Op(MO2.getImm())
610 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
611 const MachineOperand &MO1 = MI->getOperand(Op);
612 const MachineOperand &MO2 = MI->getOperand(Op+1);
613 const MachineOperand &MO3 = MI->getOperand(Op+2);
614 const MachineOperand &MO4 = MI->getOperand(Op+3);
616 O << "[" << getRegisterName(MO1.getReg());
618 // FIXME: Both darwin as and GNU as violate ARM docs here.
619 O << ", :" << MO4.getImm();
623 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
624 if (MO2.getReg() == 0)
627 O << ", " << getRegisterName(MO2.getReg());
631 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
632 const char *Modifier) {
633 if (Modifier && strcmp(Modifier, "label") == 0) {
634 printPCLabel(MI, Op+1);
638 const MachineOperand &MO1 = MI->getOperand(Op);
639 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
640 O << "[pc, +" << getRegisterName(MO1.getReg()) << "]";
644 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
645 const MachineOperand &MO = MI->getOperand(Op);
646 uint32_t v = ~MO.getImm();
647 int32_t lsb = CountTrailingZeros_32(v);
648 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
649 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
650 O << "#" << lsb << ", #" << width;
653 //===--------------------------------------------------------------------===//
655 void ARMAsmPrinter::printThumbS4ImmOperand(const MachineInstr *MI, int Op) {
656 O << "#" << MI->getOperand(Op).getImm() * 4;
660 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
661 // (3 - the number of trailing zeros) is the number of then / else.
662 unsigned Mask = MI->getOperand(Op).getImm();
663 unsigned NumTZ = CountTrailingZeros_32(Mask);
664 assert(NumTZ <= 3 && "Invalid IT mask!");
665 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
666 bool T = (Mask & (1 << Pos)) == 0;
675 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
676 const MachineOperand &MO1 = MI->getOperand(Op);
677 const MachineOperand &MO2 = MI->getOperand(Op+1);
678 O << "[" << getRegisterName(MO1.getReg());
679 O << ", " << getRegisterName(MO2.getReg()) << "]";
683 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
685 const MachineOperand &MO1 = MI->getOperand(Op);
686 const MachineOperand &MO2 = MI->getOperand(Op+1);
687 const MachineOperand &MO3 = MI->getOperand(Op+2);
689 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
690 printOperand(MI, Op);
694 O << "[" << getRegisterName(MO1.getReg());
696 O << ", " << getRegisterName(MO3.getReg());
697 else if (unsigned ImmOffs = MO2.getImm())
698 O << ", #+" << ImmOffs * Scale;
703 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
704 printThumbAddrModeRI5Operand(MI, Op, 1);
707 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
708 printThumbAddrModeRI5Operand(MI, Op, 2);
711 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
712 printThumbAddrModeRI5Operand(MI, Op, 4);
715 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
716 const MachineOperand &MO1 = MI->getOperand(Op);
717 const MachineOperand &MO2 = MI->getOperand(Op+1);
718 O << "[" << getRegisterName(MO1.getReg());
719 if (unsigned ImmOffs = MO2.getImm())
720 O << ", #+" << ImmOffs*4;
724 //===--------------------------------------------------------------------===//
726 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
727 // register with shift forms.
729 // REG IMM, SH_OPC - e.g. R5, LSL #3
730 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
731 const MachineOperand &MO1 = MI->getOperand(OpNum);
732 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
734 unsigned Reg = MO1.getReg();
735 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
736 O << getRegisterName(Reg);
738 // Print the shift opc.
740 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
743 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
744 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
747 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
749 const MachineOperand &MO1 = MI->getOperand(OpNum);
750 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
752 O << "[" << getRegisterName(MO1.getReg());
754 unsigned OffImm = MO2.getImm();
755 if (OffImm) // Don't print +0.
756 O << ", #+" << OffImm;
760 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
762 const MachineOperand &MO1 = MI->getOperand(OpNum);
763 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
765 O << "[" << getRegisterName(MO1.getReg());
767 int32_t OffImm = (int32_t)MO2.getImm();
770 O << ", #-" << -OffImm;
772 O << ", #+" << OffImm;
776 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
778 const MachineOperand &MO1 = MI->getOperand(OpNum);
779 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
781 O << "[" << getRegisterName(MO1.getReg());
783 int32_t OffImm = (int32_t)MO2.getImm() / 4;
786 O << ", #-" << -OffImm * 4;
788 O << ", #+" << OffImm * 4;
792 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
794 const MachineOperand &MO1 = MI->getOperand(OpNum);
795 int32_t OffImm = (int32_t)MO1.getImm();
798 O << "#-" << -OffImm;
803 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
805 const MachineOperand &MO1 = MI->getOperand(OpNum);
806 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
807 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
809 O << "[" << getRegisterName(MO1.getReg());
811 assert(MO2.getReg() && "Invalid so_reg load / store address!");
812 O << ", " << getRegisterName(MO2.getReg());
814 unsigned ShAmt = MO3.getImm();
816 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
817 O << ", lsl #" << ShAmt;
823 //===--------------------------------------------------------------------===//
825 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
826 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
828 O << ARMCondCodeToString(CC);
831 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
832 unsigned Reg = MI->getOperand(OpNum).getReg();
834 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
839 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
840 int Id = (int)MI->getOperand(OpNum).getImm();
841 O << MAI->getPrivateGlobalPrefix()
842 << "PC" << getFunctionNumber() << "_" << Id;
845 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
847 // Always skip the first operand, it's the optional (and implicit writeback).
848 for (unsigned i = OpNum+1, e = MI->getNumOperands(); i != e; ++i) {
849 if (MI->getOperand(i).isImplicit())
851 if ((int)i != OpNum+1) O << ", ";
857 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
858 const char *Modifier) {
859 assert(Modifier && "This operand only works with a modifier!");
860 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
862 if (!strcmp(Modifier, "label")) {
863 unsigned ID = MI->getOperand(OpNum).getImm();
864 O << *GetCPISymbol(ID) << ":\n";
866 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
867 unsigned CPI = MI->getOperand(OpNum).getIndex();
869 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
871 if (MCPE.isMachineConstantPoolEntry()) {
872 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
874 EmitGlobalConstant(MCPE.Val.ConstVal);
879 MCSymbol *ARMAsmPrinter::
880 GetARMSetPICJumpTableLabel2(unsigned uid, unsigned uid2,
881 const MachineBasicBlock *MBB) const {
882 SmallString<60> Name;
883 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix()
884 << getFunctionNumber() << '_' << uid << '_' << uid2
885 << "_set_" << MBB->getNumber();
886 return OutContext.GetOrCreateSymbol(Name.str());
889 MCSymbol *ARMAsmPrinter::
890 GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
891 SmallString<60> Name;
892 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
893 << getFunctionNumber() << '_' << uid << '_' << uid2;
894 return OutContext.GetOrCreateSymbol(Name.str());
897 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
898 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
900 const MachineOperand &MO1 = MI->getOperand(OpNum);
901 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
903 unsigned JTI = MO1.getIndex();
904 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
905 OutStreamer.EmitLabel(JTISymbol);
907 const char *JTEntryDirective = MAI->getData32bitsDirective();
909 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
910 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
911 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
912 bool UseSet= MAI->hasSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
913 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
914 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
915 MachineBasicBlock *MBB = JTBBs[i];
916 bool isNew = JTSets.insert(MBB);
918 if (UseSet && isNew) {
920 << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB) << ','
921 << *MBB->getSymbol(OutContext) << '-' << *JTISymbol << '\n';
924 O << JTEntryDirective << ' ';
926 O << *GetARMSetPICJumpTableLabel2(JTI, MO2.getImm(), MBB);
927 else if (TM.getRelocationModel() == Reloc::PIC_)
928 O << *MBB->getSymbol(OutContext) << '-' << *JTISymbol;
930 O << *MBB->getSymbol(OutContext);
937 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
938 const MachineOperand &MO1 = MI->getOperand(OpNum);
939 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
940 unsigned JTI = MO1.getIndex();
942 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
943 OutStreamer.EmitLabel(JTISymbol);
945 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
946 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
947 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
948 bool ByteOffset = false, HalfWordOffset = false;
949 if (MI->getOpcode() == ARM::t2TBB)
951 else if (MI->getOpcode() == ARM::t2TBH)
952 HalfWordOffset = true;
954 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
955 MachineBasicBlock *MBB = JTBBs[i];
957 O << MAI->getData8bitsDirective();
958 else if (HalfWordOffset)
959 O << MAI->getData16bitsDirective();
961 if (ByteOffset || HalfWordOffset)
962 O << '(' << *MBB->getSymbol(OutContext) << "-" << *JTISymbol << ")/2";
964 O << "\tb.w " << *MBB->getSymbol(OutContext);
970 // Make sure the instruction that follows TBB is 2-byte aligned.
971 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
972 if (ByteOffset && (JTBBs.size() & 1)) {
978 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
979 O << "[pc, " << getRegisterName(MI->getOperand(OpNum).getReg());
980 if (MI->getOpcode() == ARM::t2TBH)
985 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
986 O << MI->getOperand(OpNum).getImm();
989 void ARMAsmPrinter::printVFPf32ImmOperand(const MachineInstr *MI, int OpNum) {
990 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
991 O << '#' << FP->getValueAPF().convertToFloat();
993 O.PadToColumn(MAI->getCommentColumn());
994 O << MAI->getCommentString() << ' ';
995 WriteAsOperand(O, FP, /*PrintType=*/false);
999 void ARMAsmPrinter::printVFPf64ImmOperand(const MachineInstr *MI, int OpNum) {
1000 const ConstantFP *FP = MI->getOperand(OpNum).getFPImm();
1001 O << '#' << FP->getValueAPF().convertToDouble();
1003 O.PadToColumn(MAI->getCommentColumn());
1004 O << MAI->getCommentString() << ' ';
1005 WriteAsOperand(O, FP, /*PrintType=*/false);
1009 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
1010 unsigned AsmVariant, const char *ExtraCode){
1011 // Does this asm operand have a single letter operand modifier?
1012 if (ExtraCode && ExtraCode[0]) {
1013 if (ExtraCode[1] != 0) return true; // Unknown modifier.
1015 switch (ExtraCode[0]) {
1016 default: return true; // Unknown modifier.
1017 case 'a': // Print as a memory address.
1018 if (MI->getOperand(OpNum).isReg()) {
1019 O << "[" << getRegisterName(MI->getOperand(OpNum).getReg()) << "]";
1023 case 'c': // Don't print "#" before an immediate operand.
1024 if (!MI->getOperand(OpNum).isImm())
1026 printNoHashImmediate(MI, OpNum);
1028 case 'P': // Print a VFP double precision register.
1029 case 'q': // Print a NEON quad precision register.
1030 printOperand(MI, OpNum);
1033 if (TM.getTargetData()->isLittleEndian())
1037 if (TM.getTargetData()->isBigEndian())
1040 case 'H': // Write second word of DI / DF reference.
1041 // Verify that this operand has two consecutive registers.
1042 if (!MI->getOperand(OpNum).isReg() ||
1043 OpNum+1 == MI->getNumOperands() ||
1044 !MI->getOperand(OpNum+1).isReg())
1046 ++OpNum; // Return the high-part.
1050 printOperand(MI, OpNum);
1054 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1055 unsigned OpNum, unsigned AsmVariant,
1056 const char *ExtraCode) {
1057 if (ExtraCode && ExtraCode[0])
1058 return true; // Unknown modifier.
1060 const MachineOperand &MO = MI->getOperand(OpNum);
1061 assert(MO.isReg() && "unexpected inline asm memory operand");
1062 O << "[" << getRegisterName(MO.getReg()) << "]";
1066 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1069 // Call the autogenerated instruction printer routines.
1070 processDebugLoc(MI, true);
1073 printInstructionThroughMCStreamer(MI);
1075 int Opc = MI->getOpcode();
1076 if (Opc == ARM::CONSTPOOL_ENTRY)
1079 printInstruction(MI);
1085 processDebugLoc(MI, false);
1088 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
1089 if (Subtarget->isTargetDarwin()) {
1090 Reloc::Model RelocM = TM.getRelocationModel();
1091 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
1092 // Declare all the text sections up front (before the DWARF sections
1093 // emitted by AsmPrinter::doInitialization) so the assembler will keep
1094 // them together at the beginning of the object file. This helps
1095 // avoid out-of-range branches that are due a fundamental limitation of
1096 // the way symbol offsets are encoded with the current Darwin ARM
1098 TargetLoweringObjectFileMachO &TLOFMacho =
1099 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1100 OutStreamer.SwitchSection(TLOFMacho.getTextSection());
1101 OutStreamer.SwitchSection(TLOFMacho.getTextCoalSection());
1102 OutStreamer.SwitchSection(TLOFMacho.getConstTextCoalSection());
1103 if (RelocM == Reloc::DynamicNoPIC) {
1104 const MCSection *sect =
1105 TLOFMacho.getMachOSection("__TEXT", "__symbol_stub4",
1106 MCSectionMachO::S_SYMBOL_STUBS,
1107 12, SectionKind::getText());
1108 OutStreamer.SwitchSection(sect);
1110 const MCSection *sect =
1111 TLOFMacho.getMachOSection("__TEXT", "__picsymbolstub4",
1112 MCSectionMachO::S_SYMBOL_STUBS,
1113 16, SectionKind::getText());
1114 OutStreamer.SwitchSection(sect);
1119 // Use unified assembler syntax.
1120 O << "\t.syntax unified\n";
1122 // Emit ARM Build Attributes
1123 if (Subtarget->isTargetELF()) {
1125 std::string CPUString = Subtarget->getCPUString();
1126 if (CPUString != "generic")
1127 O << "\t.cpu " << CPUString << '\n';
1129 // FIXME: Emit FPU type
1130 if (Subtarget->hasVFP2())
1131 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1133 // Signal various FP modes.
1135 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1136 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1138 if (FiniteOnlyFPMath())
1139 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1141 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1143 // 8-bytes alignment stuff.
1144 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1145 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1147 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1148 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1149 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1150 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1152 // FIXME: Should we signal R9 usage?
1157 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
1158 if (Subtarget->isTargetDarwin()) {
1159 // All darwin targets use mach-o.
1160 TargetLoweringObjectFileMachO &TLOFMacho =
1161 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1162 MachineModuleInfoMachO &MMIMacho =
1163 MMI->getObjFileInfo<MachineModuleInfoMachO>();
1167 // Output non-lazy-pointers for external and common global variables.
1168 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
1170 if (!Stubs.empty()) {
1171 // Switch with ".non_lazy_symbol_pointer" directive.
1172 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1174 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
1175 O << *Stubs[i].first << ":\n\t.indirect_symbol ";
1176 O << *Stubs[i].second << "\n\t.long\t0\n";
1180 Stubs = MMIMacho.GetHiddenGVStubList();
1181 if (!Stubs.empty()) {
1182 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1184 for (unsigned i = 0, e = Stubs.size(); i != e; ++i)
1185 O << *Stubs[i].first << ":\n\t.long " << *Stubs[i].second << "\n";
1188 // Funny Darwin hack: This flag tells the linker that no global symbols
1189 // contain code that falls through to other global symbols (e.g. the obvious
1190 // implementation of multiple entry points). If this doesn't occur, the
1191 // linker can safely perform dead code stripping. Since LLVM never
1192 // generates code that does this, it is always safe to set.
1193 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
1197 //===----------------------------------------------------------------------===//
1199 void ARMAsmPrinter::printInstructionThroughMCStreamer(const MachineInstr *MI) {
1200 ARMMCInstLower MCInstLowering(OutContext, *Mang, *this);
1201 switch (MI->getOpcode()) {
1202 case ARM::t2MOVi32imm:
1203 assert(0 && "Should be lowered by thumb2it pass");
1205 case TargetInstrInfo::DBG_LABEL:
1206 case TargetInstrInfo::EH_LABEL:
1207 case TargetInstrInfo::GC_LABEL:
1210 case TargetInstrInfo::KILL:
1213 case TargetInstrInfo::INLINEASM:
1216 case TargetInstrInfo::IMPLICIT_DEF:
1217 printImplicitDef(MI);
1219 case ARM::PICADD: { // FIXME: Remove asm string from td file.
1220 // This is a pseudo op for a label + instruction sequence, which looks like:
1223 // This adds the address of LPC0 to r0.
1226 // FIXME: MOVE TO SHARED PLACE.
1227 unsigned Id = (unsigned)MI->getOperand(2).getImm();
1228 const char *Prefix = MAI->getPrivateGlobalPrefix();
1229 MCSymbol *Label =OutContext.GetOrCreateSymbol(Twine(Prefix)
1230 + "PC" + Twine(getFunctionNumber()) + "_" + Twine(Id));
1231 OutStreamer.EmitLabel(Label);
1234 // Form and emit tha dd.
1236 AddInst.setOpcode(ARM::ADDrr);
1237 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1238 AddInst.addOperand(MCOperand::CreateReg(ARM::PC));
1239 AddInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1240 printMCInst(&AddInst);
1243 case ARM::CONSTPOOL_ENTRY: { // FIXME: Remove asm string from td file.
1244 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1245 /// in the function. The first operand is the ID# for this instruction, the
1246 /// second is the index into the MachineConstantPool that this is, the third
1247 /// is the size in bytes of this constant pool entry.
1248 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1249 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1252 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
1254 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1255 if (MCPE.isMachineConstantPoolEntry())
1256 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1258 EmitGlobalConstant(MCPE.Val.ConstVal);
1262 case ARM::MOVi2pieces: { // FIXME: Remove asmstring from td file.
1263 // This is a hack that lowers as a two instruction sequence.
1264 unsigned DstReg = MI->getOperand(0).getReg();
1265 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1267 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
1268 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
1272 TmpInst.setOpcode(ARM::MOVi);
1273 TmpInst.addOperand(MCOperand::CreateReg(DstReg));
1274 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV1));
1277 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1278 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1280 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1281 printMCInst(&TmpInst);
1287 TmpInst.setOpcode(ARM::ORRri);
1288 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1289 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // inreg
1290 TmpInst.addOperand(MCOperand::CreateImm(SOImmValV2)); // so_imm
1292 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1293 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1295 TmpInst.addOperand(MCOperand::CreateReg(0)); // cc_out
1296 printMCInst(&TmpInst);
1300 case ARM::MOVi32imm: { // FIXME: Remove asmstring from td file.
1301 // This is a hack that lowers as a two instruction sequence.
1302 unsigned DstReg = MI->getOperand(0).getReg();
1303 unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
1307 TmpInst.setOpcode(ARM::MOVi16);
1308 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1309 TmpInst.addOperand(MCOperand::CreateImm(ImmVal & 65535)); // lower16(imm)
1312 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1313 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1315 printMCInst(&TmpInst);
1321 TmpInst.setOpcode(ARM::MOVTi16);
1322 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
1323 TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
1324 TmpInst.addOperand(MCOperand::CreateImm(ImmVal >> 16)); // upper16(imm)
1327 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1328 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
1330 printMCInst(&TmpInst);
1338 MCInstLowering.Lower(MI, TmpInst);
1340 printMCInst(&TmpInst);
1343 //===----------------------------------------------------------------------===//
1344 // Target Registry Stuff
1345 //===----------------------------------------------------------------------===//
1347 static MCInstPrinter *createARMMCInstPrinter(const Target &T,
1348 unsigned SyntaxVariant,
1349 const MCAsmInfo &MAI,
1351 if (SyntaxVariant == 0)
1352 return new ARMInstPrinter(O, MAI, false);
1356 // Force static initialization.
1357 extern "C" void LLVMInitializeARMAsmPrinter() {
1358 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1359 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
1361 TargetRegistry::RegisterMCInstPrinter(TheARMTarget, createARMMCInstPrinter);
1362 TargetRegistry::RegisterMCInstPrinter(TheThumbTarget, createARMMCInstPrinter);