1 // The LLVM Compiler Infrastructure
3 // This file is distributed under the University of Illinois Open Source
4 // License. See LICENSE.TXT for details.
6 //===----------------------------------------------------------------------===//
8 // This file contains a printer that converts from our internal representation
9 // of machine-dependent LLVM code to GAS-format ARM assembly language.
11 //===----------------------------------------------------------------------===//
13 #define DEBUG_TYPE "asm-printer"
15 #include "ARMBuildAttrs.h"
16 #include "ARMTargetMachine.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMConstantPoolValue.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Module.h"
22 #include "llvm/Assembly/Writer.h"
23 #include "llvm/CodeGen/AsmPrinter.h"
24 #include "llvm/CodeGen/DwarfWriter.h"
25 #include "llvm/CodeGen/MachineModuleInfo.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/Target/TargetData.h"
32 #include "llvm/Target/TargetLoweringObjectFile.h"
33 #include "llvm/Target/TargetMachine.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Target/TargetRegistry.h"
36 #include "llvm/ADT/SmallPtrSet.h"
37 #include "llvm/ADT/SmallString.h"
38 #include "llvm/ADT/Statistic.h"
39 #include "llvm/ADT/StringSet.h"
40 #include "llvm/Support/Compiler.h"
41 #include "llvm/Support/ErrorHandling.h"
42 #include "llvm/Support/Mangler.h"
43 #include "llvm/Support/MathExtras.h"
44 #include "llvm/Support/FormattedStream.h"
48 STATISTIC(EmittedInsts, "Number of machine instrs printed");
51 class VISIBILITY_HIDDEN ARMAsmPrinter : public AsmPrinter {
54 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
55 /// make the right decision when printing asm code for different targets.
56 const ARMSubtarget *Subtarget;
58 /// AFI - Keep a pointer to ARMFunctionInfo for the current
62 /// MCP - Keep a pointer to constantpool entries of the current
64 const MachineConstantPool *MCP;
66 /// We name each basic block in a Function with a unique number, so
67 /// that we can consistently refer to them later. This is cleared
68 /// at the beginning of each call to runOnMachineFunction().
70 typedef std::map<const Value *, unsigned> ValueMapTy;
71 ValueMapTy NumberForBB;
73 /// GVNonLazyPtrs - Keeps the set of GlobalValues that require
74 /// non-lazy-pointers for indirect access.
75 StringMap<std::string> GVNonLazyPtrs;
77 /// HiddenGVNonLazyPtrs - Keeps the set of GlobalValues with hidden
78 /// visibility that require non-lazy-pointers for indirect access.
79 StringMap<std::string> HiddenGVNonLazyPtrs;
81 /// True if asm printer is printing a series of CONSTPOOL_ENTRY.
84 explicit ARMAsmPrinter(formatted_raw_ostream &O, TargetMachine &TM,
85 const MCAsmInfo *T, bool V)
86 : AsmPrinter(O, TM, T, V), DW(0), AFI(NULL), MCP(NULL),
88 Subtarget = &TM.getSubtarget<ARMSubtarget>();
91 virtual const char *getPassName() const {
92 return "ARM Assembly Printer";
95 void printOperand(const MachineInstr *MI, int OpNum,
96 const char *Modifier = 0);
97 void printSOImmOperand(const MachineInstr *MI, int OpNum);
98 void printSOImm2PartOperand(const MachineInstr *MI, int OpNum);
99 void printSORegOperand(const MachineInstr *MI, int OpNum);
100 void printAddrMode2Operand(const MachineInstr *MI, int OpNum);
101 void printAddrMode2OffsetOperand(const MachineInstr *MI, int OpNum);
102 void printAddrMode3Operand(const MachineInstr *MI, int OpNum);
103 void printAddrMode3OffsetOperand(const MachineInstr *MI, int OpNum);
104 void printAddrMode4Operand(const MachineInstr *MI, int OpNum,
105 const char *Modifier = 0);
106 void printAddrMode5Operand(const MachineInstr *MI, int OpNum,
107 const char *Modifier = 0);
108 void printAddrMode6Operand(const MachineInstr *MI, int OpNum);
109 void printAddrModePCOperand(const MachineInstr *MI, int OpNum,
110 const char *Modifier = 0);
111 void printBitfieldInvMaskImmOperand (const MachineInstr *MI, int OpNum);
113 void printThumbITMask(const MachineInstr *MI, int OpNum);
114 void printThumbAddrModeRROperand(const MachineInstr *MI, int OpNum);
115 void printThumbAddrModeRI5Operand(const MachineInstr *MI, int OpNum,
117 void printThumbAddrModeS1Operand(const MachineInstr *MI, int OpNum);
118 void printThumbAddrModeS2Operand(const MachineInstr *MI, int OpNum);
119 void printThumbAddrModeS4Operand(const MachineInstr *MI, int OpNum);
120 void printThumbAddrModeSPOperand(const MachineInstr *MI, int OpNum);
122 void printT2SOOperand(const MachineInstr *MI, int OpNum);
123 void printT2AddrModeImm12Operand(const MachineInstr *MI, int OpNum);
124 void printT2AddrModeImm8Operand(const MachineInstr *MI, int OpNum);
125 void printT2AddrModeImm8s4Operand(const MachineInstr *MI, int OpNum);
126 void printT2AddrModeImm8OffsetOperand(const MachineInstr *MI, int OpNum);
127 void printT2AddrModeSoRegOperand(const MachineInstr *MI, int OpNum);
129 void printPredicateOperand(const MachineInstr *MI, int OpNum);
130 void printSBitModifierOperand(const MachineInstr *MI, int OpNum);
131 void printPCLabel(const MachineInstr *MI, int OpNum);
132 void printRegisterList(const MachineInstr *MI, int OpNum);
133 void printCPInstOperand(const MachineInstr *MI, int OpNum,
134 const char *Modifier);
135 void printJTBlockOperand(const MachineInstr *MI, int OpNum);
136 void printJT2BlockOperand(const MachineInstr *MI, int OpNum);
137 void printTBAddrMode(const MachineInstr *MI, int OpNum);
138 void printNoHashImmediate(const MachineInstr *MI, int OpNum);
140 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
141 unsigned AsmVariant, const char *ExtraCode);
142 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
144 const char *ExtraCode);
146 void PrintGlobalVariable(const GlobalVariable* GVar);
147 void printInstruction(const MachineInstr *MI); // autogenerated.
148 void printMachineInstruction(const MachineInstr *MI);
149 bool runOnMachineFunction(MachineFunction &F);
150 bool doInitialization(Module &M);
151 bool doFinalization(Module &M);
153 /// EmitMachineConstantPoolValue - Print a machine constantpool value to
155 virtual void EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
156 printDataDirective(MCPV->getType());
158 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
159 GlobalValue *GV = ACPV->getGV();
162 if (ACPV->isLSDA()) {
163 SmallString<256> LSDAName;
164 raw_svector_ostream(LSDAName) << MAI->getPrivateGlobalPrefix() <<
165 "_LSDA_" << getFunctionNumber();
166 Name = LSDAName.str();
168 bool isIndirect = Subtarget->isTargetDarwin() &&
169 Subtarget->GVIsIndirectSymbol(GV,
170 TM.getRelocationModel() == Reloc::Static);
172 Name = Mang->getMangledName(GV);
174 // FIXME: Remove this when Darwin transition to @GOT like syntax.
175 std::string SymName = Mang->getMangledName(GV);
176 Name = Mang->getMangledName(GV, "$non_lazy_ptr", true);
177 if (GV->hasHiddenVisibility())
178 HiddenGVNonLazyPtrs[SymName] = Name;
180 GVNonLazyPtrs[SymName] = Name;
183 Name = Mang->makeNameProper(ACPV->getSymbol());
186 if (ACPV->hasModifier()) O << "(" << ACPV->getModifier() << ")";
187 if (ACPV->getPCAdjustment() != 0) {
188 O << "-(" << MAI->getPrivateGlobalPrefix() << "PC"
189 << ACPV->getLabelId()
190 << "+" << (unsigned)ACPV->getPCAdjustment();
191 if (ACPV->mustAddCurrentAddress())
198 void getAnalysisUsage(AnalysisUsage &AU) const {
199 AsmPrinter::getAnalysisUsage(AU);
200 AU.setPreservesAll();
201 AU.addRequired<MachineModuleInfo>();
202 AU.addRequired<DwarfWriter>();
205 } // end of anonymous namespace
207 #include "ARMGenAsmWriter.inc"
209 /// runOnMachineFunction - This uses the printInstruction()
210 /// method to print assembly for each instruction.
212 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
215 AFI = MF.getInfo<ARMFunctionInfo>();
216 MCP = MF.getConstantPool();
218 SetupMachineFunction(MF);
221 // NOTE: we don't print out constant pools here, they are handled as
226 // Print out labels for the function.
227 const Function *F = MF.getFunction();
228 OutStreamer.SwitchSection(getObjFileLowering().SectionForGlobal(F, Mang, TM));
230 switch (F->getLinkage()) {
231 default: llvm_unreachable("Unknown linkage type!");
232 case Function::PrivateLinkage:
233 case Function::InternalLinkage:
235 case Function::ExternalLinkage:
236 O << "\t.globl\t" << CurrentFnName << "\n";
238 case Function::LinkerPrivateLinkage:
239 case Function::WeakAnyLinkage:
240 case Function::WeakODRLinkage:
241 case Function::LinkOnceAnyLinkage:
242 case Function::LinkOnceODRLinkage:
243 if (Subtarget->isTargetDarwin()) {
244 O << "\t.globl\t" << CurrentFnName << "\n";
245 O << "\t.weak_definition\t" << CurrentFnName << "\n";
247 O << MAI->getWeakRefDirective() << CurrentFnName << "\n";
252 printVisibility(CurrentFnName, F->getVisibility());
254 if (AFI->isThumbFunction()) {
255 EmitAlignment(MF.getAlignment(), F, AFI->getAlign());
256 O << "\t.code\t16\n";
257 O << "\t.thumb_func";
258 if (Subtarget->isTargetDarwin())
259 O << "\t" << CurrentFnName;
263 EmitAlignment(MF.getAlignment(), F);
266 O << CurrentFnName << ":\n";
267 // Emit pre-function debug information.
268 DW->BeginFunction(&MF);
270 if (Subtarget->isTargetDarwin()) {
271 // If the function is empty, then we need to emit *something*. Otherwise,
272 // the function's label might be associated with something that it wasn't
273 // meant to be associated with. We emit a noop in this situation.
274 MachineFunction::iterator I = MF.begin();
276 if (++I == MF.end() && MF.front().empty())
280 // Print out code for the function.
281 for (MachineFunction::const_iterator I = MF.begin(), E = MF.end();
283 // Print a label for the basic block.
284 if (I != MF.begin()) {
285 printBasicBlockLabel(I, true, true, VerboseAsm);
288 for (MachineBasicBlock::const_iterator II = I->begin(), E = I->end();
290 // Print the assembly for the instruction.
291 printMachineInstruction(II);
295 if (MAI->hasDotTypeDotSizeDirective())
296 O << "\t.size " << CurrentFnName << ", .-" << CurrentFnName << "\n";
298 // Emit post-function debug information.
299 DW->EndFunction(&MF);
304 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
305 const char *Modifier) {
306 const MachineOperand &MO = MI->getOperand(OpNum);
307 switch (MO.getType()) {
308 case MachineOperand::MO_Register: {
309 unsigned Reg = MO.getReg();
310 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
311 if (Modifier && strcmp(Modifier, "dregpair") == 0) {
312 unsigned DRegLo = TRI->getSubReg(Reg, 5); // arm_dsubreg_0
313 unsigned DRegHi = TRI->getSubReg(Reg, 6); // arm_dsubreg_1
315 << TRI->getAsmName(DRegLo) << ',' << TRI->getAsmName(DRegHi)
317 } else if (Modifier && strcmp(Modifier, "lane") == 0) {
318 unsigned RegNum = ARMRegisterInfo::getRegisterNumbering(Reg);
319 unsigned DReg = TRI->getMatchingSuperReg(Reg, RegNum & 1 ? 0 : 1,
321 O << TRI->getAsmName(DReg) << '[' << (RegNum & 1) << ']';
323 O << TRI->getAsmName(Reg);
326 llvm_unreachable("not implemented");
329 case MachineOperand::MO_Immediate: {
330 O << '#' << MO.getImm();
333 case MachineOperand::MO_MachineBasicBlock:
334 printBasicBlockLabel(MO.getMBB());
336 case MachineOperand::MO_GlobalAddress: {
337 bool isCallOp = Modifier && !strcmp(Modifier, "call");
338 GlobalValue *GV = MO.getGlobal();
339 O << Mang->getMangledName(GV);
341 printOffset(MO.getOffset());
343 if (isCallOp && Subtarget->isTargetELF() &&
344 TM.getRelocationModel() == Reloc::PIC_)
348 case MachineOperand::MO_ExternalSymbol: {
349 bool isCallOp = Modifier && !strcmp(Modifier, "call");
350 std::string Name = Mang->makeNameProper(MO.getSymbolName());
353 if (isCallOp && Subtarget->isTargetELF() &&
354 TM.getRelocationModel() == Reloc::PIC_)
358 case MachineOperand::MO_ConstantPoolIndex:
359 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
360 << '_' << MO.getIndex();
362 case MachineOperand::MO_JumpTableIndex:
363 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
364 << '_' << MO.getIndex();
367 O << "<unknown operand type>"; abort (); break;
371 static void printSOImm(formatted_raw_ostream &O, int64_t V, bool VerboseAsm,
372 const MCAsmInfo *MAI) {
373 // Break it up into two parts that make up a shifter immediate.
374 V = ARM_AM::getSOImmVal(V);
375 assert(V != -1 && "Not a valid so_imm value!");
377 unsigned Imm = ARM_AM::getSOImmValImm(V);
378 unsigned Rot = ARM_AM::getSOImmValRot(V);
380 // Print low-level immediate formation info, per
381 // A5.1.3: "Data-processing operands - Immediate".
383 O << "#" << Imm << ", " << Rot;
384 // Pretty printed version.
386 O << ' ' << MAI->getCommentString()
387 << ' ' << (int)ARM_AM::rotr32(Imm, Rot);
393 /// printSOImmOperand - SOImm is 4-bit rotate amount in bits 8-11 with 8-bit
394 /// immediate in bits 0-7.
395 void ARMAsmPrinter::printSOImmOperand(const MachineInstr *MI, int OpNum) {
396 const MachineOperand &MO = MI->getOperand(OpNum);
397 assert(MO.isImm() && "Not a valid so_imm value!");
398 printSOImm(O, MO.getImm(), VerboseAsm, MAI);
401 /// printSOImm2PartOperand - SOImm is broken into two pieces using a 'mov'
402 /// followed by an 'orr' to materialize.
403 void ARMAsmPrinter::printSOImm2PartOperand(const MachineInstr *MI, int OpNum) {
404 const MachineOperand &MO = MI->getOperand(OpNum);
405 assert(MO.isImm() && "Not a valid so_imm value!");
406 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO.getImm());
407 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO.getImm());
408 printSOImm(O, V1, VerboseAsm, MAI);
410 printPredicateOperand(MI, 2);
416 printSOImm(O, V2, VerboseAsm, MAI);
419 // so_reg is a 4-operand unit corresponding to register forms of the A5.1
420 // "Addressing Mode 1 - Data-processing operands" forms. This includes:
422 // REG REG 0,SH_OPC - e.g. R5, ROR R3
423 // REG 0 IMM,SH_OPC - e.g. R5, LSL #3
424 void ARMAsmPrinter::printSORegOperand(const MachineInstr *MI, int Op) {
425 const MachineOperand &MO1 = MI->getOperand(Op);
426 const MachineOperand &MO2 = MI->getOperand(Op+1);
427 const MachineOperand &MO3 = MI->getOperand(Op+2);
429 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
430 O << TRI->getAsmName(MO1.getReg());
432 // Print the shift opc.
434 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()))
438 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
439 O << TRI->getAsmName(MO2.getReg());
440 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
442 O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
446 void ARMAsmPrinter::printAddrMode2Operand(const MachineInstr *MI, int Op) {
447 const MachineOperand &MO1 = MI->getOperand(Op);
448 const MachineOperand &MO2 = MI->getOperand(Op+1);
449 const MachineOperand &MO3 = MI->getOperand(Op+2);
451 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
452 printOperand(MI, Op);
456 O << "[" << TRI->getAsmName(MO1.getReg());
459 if (ARM_AM::getAM2Offset(MO3.getImm())) // Don't print +0.
461 << (char)ARM_AM::getAM2Op(MO3.getImm())
462 << ARM_AM::getAM2Offset(MO3.getImm());
468 << (char)ARM_AM::getAM2Op(MO3.getImm())
469 << TRI->getAsmName(MO2.getReg());
471 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
473 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
478 void ARMAsmPrinter::printAddrMode2OffsetOperand(const MachineInstr *MI, int Op){
479 const MachineOperand &MO1 = MI->getOperand(Op);
480 const MachineOperand &MO2 = MI->getOperand(Op+1);
483 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
484 assert(ImmOffs && "Malformed indexed load / store!");
486 << (char)ARM_AM::getAM2Op(MO2.getImm())
491 O << (char)ARM_AM::getAM2Op(MO2.getImm())
492 << TRI->getAsmName(MO1.getReg());
494 if (unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm()))
496 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO2.getImm()))
500 void ARMAsmPrinter::printAddrMode3Operand(const MachineInstr *MI, int Op) {
501 const MachineOperand &MO1 = MI->getOperand(Op);
502 const MachineOperand &MO2 = MI->getOperand(Op+1);
503 const MachineOperand &MO3 = MI->getOperand(Op+2);
505 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
506 O << "[" << TRI->getAsmName(MO1.getReg());
510 << (char)ARM_AM::getAM3Op(MO3.getImm())
511 << TRI->getAsmName(MO2.getReg())
516 if (unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm()))
518 << (char)ARM_AM::getAM3Op(MO3.getImm())
523 void ARMAsmPrinter::printAddrMode3OffsetOperand(const MachineInstr *MI, int Op){
524 const MachineOperand &MO1 = MI->getOperand(Op);
525 const MachineOperand &MO2 = MI->getOperand(Op+1);
528 O << (char)ARM_AM::getAM3Op(MO2.getImm())
529 << TRI->getAsmName(MO1.getReg());
533 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
534 assert(ImmOffs && "Malformed indexed load / store!");
536 << (char)ARM_AM::getAM3Op(MO2.getImm())
540 void ARMAsmPrinter::printAddrMode4Operand(const MachineInstr *MI, int Op,
541 const char *Modifier) {
542 const MachineOperand &MO1 = MI->getOperand(Op);
543 const MachineOperand &MO2 = MI->getOperand(Op+1);
544 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
545 if (Modifier && strcmp(Modifier, "submode") == 0) {
546 if (MO1.getReg() == ARM::SP) {
548 bool isLDM = (MI->getOpcode() == ARM::LDM ||
549 MI->getOpcode() == ARM::LDM_RET ||
550 MI->getOpcode() == ARM::t2LDM ||
551 MI->getOpcode() == ARM::t2LDM_RET);
552 O << ARM_AM::getAMSubModeAltStr(Mode, isLDM);
554 O << ARM_AM::getAMSubModeStr(Mode);
555 } else if (Modifier && strcmp(Modifier, "wide") == 0) {
556 ARM_AM::AMSubMode Mode = ARM_AM::getAM4SubMode(MO2.getImm());
557 if (Mode == ARM_AM::ia)
560 printOperand(MI, Op);
561 if (ARM_AM::getAM4WBFlag(MO2.getImm()))
566 void ARMAsmPrinter::printAddrMode5Operand(const MachineInstr *MI, int Op,
567 const char *Modifier) {
568 const MachineOperand &MO1 = MI->getOperand(Op);
569 const MachineOperand &MO2 = MI->getOperand(Op+1);
571 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
572 printOperand(MI, Op);
576 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
578 if (Modifier && strcmp(Modifier, "submode") == 0) {
579 ARM_AM::AMSubMode Mode = ARM_AM::getAM5SubMode(MO2.getImm());
580 if (MO1.getReg() == ARM::SP) {
581 bool isFLDM = (MI->getOpcode() == ARM::FLDMD ||
582 MI->getOpcode() == ARM::FLDMS);
583 O << ARM_AM::getAMSubModeAltStr(Mode, isFLDM);
585 O << ARM_AM::getAMSubModeStr(Mode);
587 } else if (Modifier && strcmp(Modifier, "base") == 0) {
588 // Used for FSTM{D|S} and LSTM{D|S} operations.
589 O << TRI->getAsmName(MO1.getReg());
590 if (ARM_AM::getAM5WBFlag(MO2.getImm()))
595 O << "[" << TRI->getAsmName(MO1.getReg());
597 if (unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm())) {
599 << (char)ARM_AM::getAM5Op(MO2.getImm())
605 void ARMAsmPrinter::printAddrMode6Operand(const MachineInstr *MI, int Op) {
606 const MachineOperand &MO1 = MI->getOperand(Op);
607 const MachineOperand &MO2 = MI->getOperand(Op+1);
608 const MachineOperand &MO3 = MI->getOperand(Op+2);
610 // FIXME: No support yet for specifying alignment.
611 O << "[" << TRI->getAsmName(MO1.getReg()) << "]";
613 if (ARM_AM::getAM6WBFlag(MO3.getImm())) {
614 if (MO2.getReg() == 0)
617 O << ", " << TRI->getAsmName(MO2.getReg());
621 void ARMAsmPrinter::printAddrModePCOperand(const MachineInstr *MI, int Op,
622 const char *Modifier) {
623 if (Modifier && strcmp(Modifier, "label") == 0) {
624 printPCLabel(MI, Op+1);
628 const MachineOperand &MO1 = MI->getOperand(Op);
629 assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
630 O << "[pc, +" << TRI->getAsmName(MO1.getReg()) << "]";
634 ARMAsmPrinter::printBitfieldInvMaskImmOperand(const MachineInstr *MI, int Op) {
635 const MachineOperand &MO = MI->getOperand(Op);
636 uint32_t v = ~MO.getImm();
637 int32_t lsb = CountTrailingZeros_32(v);
638 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
639 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
640 O << "#" << lsb << ", #" << width;
643 //===--------------------------------------------------------------------===//
646 ARMAsmPrinter::printThumbITMask(const MachineInstr *MI, int Op) {
647 // (3 - the number of trailing zeros) is the number of then / else.
648 unsigned Mask = MI->getOperand(Op).getImm();
649 unsigned NumTZ = CountTrailingZeros_32(Mask);
650 assert(NumTZ <= 3 && "Invalid IT mask!");
651 for (unsigned Pos = 3, e = NumTZ; Pos > e; --Pos) {
652 bool T = (Mask & (1 << Pos)) == 0;
661 ARMAsmPrinter::printThumbAddrModeRROperand(const MachineInstr *MI, int Op) {
662 const MachineOperand &MO1 = MI->getOperand(Op);
663 const MachineOperand &MO2 = MI->getOperand(Op+1);
664 O << "[" << TRI->getAsmName(MO1.getReg());
665 O << ", " << TRI->getAsmName(MO2.getReg()) << "]";
669 ARMAsmPrinter::printThumbAddrModeRI5Operand(const MachineInstr *MI, int Op,
671 const MachineOperand &MO1 = MI->getOperand(Op);
672 const MachineOperand &MO2 = MI->getOperand(Op+1);
673 const MachineOperand &MO3 = MI->getOperand(Op+2);
675 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
676 printOperand(MI, Op);
680 O << "[" << TRI->getAsmName(MO1.getReg());
682 O << ", " << TRI->getAsmName(MO3.getReg());
683 else if (unsigned ImmOffs = MO2.getImm()) {
684 O << ", #" << ImmOffs;
692 ARMAsmPrinter::printThumbAddrModeS1Operand(const MachineInstr *MI, int Op) {
693 printThumbAddrModeRI5Operand(MI, Op, 1);
696 ARMAsmPrinter::printThumbAddrModeS2Operand(const MachineInstr *MI, int Op) {
697 printThumbAddrModeRI5Operand(MI, Op, 2);
700 ARMAsmPrinter::printThumbAddrModeS4Operand(const MachineInstr *MI, int Op) {
701 printThumbAddrModeRI5Operand(MI, Op, 4);
704 void ARMAsmPrinter::printThumbAddrModeSPOperand(const MachineInstr *MI,int Op) {
705 const MachineOperand &MO1 = MI->getOperand(Op);
706 const MachineOperand &MO2 = MI->getOperand(Op+1);
707 O << "[" << TRI->getAsmName(MO1.getReg());
708 if (unsigned ImmOffs = MO2.getImm())
709 O << ", #" << ImmOffs << " * 4";
713 //===--------------------------------------------------------------------===//
715 // Constant shifts t2_so_reg is a 2-operand unit corresponding to the Thumb2
716 // register with shift forms.
718 // REG IMM, SH_OPC - e.g. R5, LSL #3
719 void ARMAsmPrinter::printT2SOOperand(const MachineInstr *MI, int OpNum) {
720 const MachineOperand &MO1 = MI->getOperand(OpNum);
721 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
723 unsigned Reg = MO1.getReg();
724 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
725 O << TRI->getAsmName(Reg);
727 // Print the shift opc.
729 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()))
732 assert(MO2.isImm() && "Not a valid t2_so_reg value!");
733 O << "#" << ARM_AM::getSORegOffset(MO2.getImm());
736 void ARMAsmPrinter::printT2AddrModeImm12Operand(const MachineInstr *MI,
738 const MachineOperand &MO1 = MI->getOperand(OpNum);
739 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
741 O << "[" << TRI->getAsmName(MO1.getReg());
743 unsigned OffImm = MO2.getImm();
744 if (OffImm) // Don't print +0.
745 O << ", #+" << OffImm;
749 void ARMAsmPrinter::printT2AddrModeImm8Operand(const MachineInstr *MI,
751 const MachineOperand &MO1 = MI->getOperand(OpNum);
752 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
754 O << "[" << TRI->getAsmName(MO1.getReg());
756 int32_t OffImm = (int32_t)MO2.getImm();
759 O << ", #-" << -OffImm;
761 O << ", #+" << OffImm;
765 void ARMAsmPrinter::printT2AddrModeImm8s4Operand(const MachineInstr *MI,
767 const MachineOperand &MO1 = MI->getOperand(OpNum);
768 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
770 O << "[" << TRI->getAsmName(MO1.getReg());
772 int32_t OffImm = (int32_t)MO2.getImm() / 4;
775 O << ", #-" << -OffImm << " * 4";
777 O << ", #+" << OffImm << " * 4";
781 void ARMAsmPrinter::printT2AddrModeImm8OffsetOperand(const MachineInstr *MI,
783 const MachineOperand &MO1 = MI->getOperand(OpNum);
784 int32_t OffImm = (int32_t)MO1.getImm();
787 O << "#-" << -OffImm;
792 void ARMAsmPrinter::printT2AddrModeSoRegOperand(const MachineInstr *MI,
794 const MachineOperand &MO1 = MI->getOperand(OpNum);
795 const MachineOperand &MO2 = MI->getOperand(OpNum+1);
796 const MachineOperand &MO3 = MI->getOperand(OpNum+2);
798 O << "[" << TRI->getAsmName(MO1.getReg());
800 assert(MO2.getReg() && "Invalid so_reg load / store address!");
801 O << ", " << TRI->getAsmName(MO2.getReg());
803 unsigned ShAmt = MO3.getImm();
805 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
806 O << ", lsl #" << ShAmt;
812 //===--------------------------------------------------------------------===//
814 void ARMAsmPrinter::printPredicateOperand(const MachineInstr *MI, int OpNum) {
815 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(OpNum).getImm();
817 O << ARMCondCodeToString(CC);
820 void ARMAsmPrinter::printSBitModifierOperand(const MachineInstr *MI, int OpNum){
821 unsigned Reg = MI->getOperand(OpNum).getReg();
823 assert(Reg == ARM::CPSR && "Expect ARM CPSR register!");
828 void ARMAsmPrinter::printPCLabel(const MachineInstr *MI, int OpNum) {
829 int Id = (int)MI->getOperand(OpNum).getImm();
830 O << MAI->getPrivateGlobalPrefix() << "PC" << Id;
833 void ARMAsmPrinter::printRegisterList(const MachineInstr *MI, int OpNum) {
835 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
836 if (MI->getOperand(i).isImplicit())
838 if ((int)i != OpNum) O << ", ";
844 void ARMAsmPrinter::printCPInstOperand(const MachineInstr *MI, int OpNum,
845 const char *Modifier) {
846 assert(Modifier && "This operand only works with a modifier!");
847 // There are two aspects to a CONSTANTPOOL_ENTRY operand, the label and the
849 if (!strcmp(Modifier, "label")) {
850 unsigned ID = MI->getOperand(OpNum).getImm();
851 O << MAI->getPrivateGlobalPrefix() << "CPI" << getFunctionNumber()
852 << '_' << ID << ":\n";
854 assert(!strcmp(Modifier, "cpentry") && "Unknown modifier for CPE");
855 unsigned CPI = MI->getOperand(OpNum).getIndex();
857 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
859 if (MCPE.isMachineConstantPoolEntry()) {
860 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
862 EmitGlobalConstant(MCPE.Val.ConstVal);
867 void ARMAsmPrinter::printJTBlockOperand(const MachineInstr *MI, int OpNum) {
868 assert(!Subtarget->isThumb2() && "Thumb2 should use double-jump jumptables!");
870 const MachineOperand &MO1 = MI->getOperand(OpNum);
871 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
872 unsigned JTI = MO1.getIndex();
873 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
874 << '_' << JTI << '_' << MO2.getImm() << ":\n";
876 const char *JTEntryDirective = MAI->getData32bitsDirective();
878 const MachineFunction *MF = MI->getParent()->getParent();
879 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
880 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
881 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
882 bool UseSet= MAI->getSetDirective() && TM.getRelocationModel() == Reloc::PIC_;
883 SmallPtrSet<MachineBasicBlock*, 8> JTSets;
884 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
885 MachineBasicBlock *MBB = JTBBs[i];
886 bool isNew = JTSets.insert(MBB);
889 printPICJumpTableSetLabel(JTI, MO2.getImm(), MBB);
891 O << JTEntryDirective << ' ';
893 O << MAI->getPrivateGlobalPrefix() << getFunctionNumber()
894 << '_' << JTI << '_' << MO2.getImm()
895 << "_set_" << MBB->getNumber();
896 else if (TM.getRelocationModel() == Reloc::PIC_) {
897 printBasicBlockLabel(MBB, false, false, false);
898 O << '-' << MAI->getPrivateGlobalPrefix() << "JTI"
899 << getFunctionNumber() << '_' << JTI << '_' << MO2.getImm();
901 printBasicBlockLabel(MBB, false, false, false);
908 void ARMAsmPrinter::printJT2BlockOperand(const MachineInstr *MI, int OpNum) {
909 const MachineOperand &MO1 = MI->getOperand(OpNum);
910 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
911 unsigned JTI = MO1.getIndex();
912 O << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
913 << '_' << JTI << '_' << MO2.getImm() << ":\n";
915 const MachineFunction *MF = MI->getParent()->getParent();
916 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
917 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
918 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
919 bool ByteOffset = false, HalfWordOffset = false;
920 if (MI->getOpcode() == ARM::t2TBB)
922 else if (MI->getOpcode() == ARM::t2TBH)
923 HalfWordOffset = true;
925 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
926 MachineBasicBlock *MBB = JTBBs[i];
928 O << MAI->getData8bitsDirective();
929 else if (HalfWordOffset)
930 O << MAI->getData16bitsDirective();
931 if (ByteOffset || HalfWordOffset) {
933 printBasicBlockLabel(MBB, false, false, false);
934 O << "-" << MAI->getPrivateGlobalPrefix() << "JTI" << getFunctionNumber()
935 << '_' << JTI << '_' << MO2.getImm() << ")/2";
938 printBasicBlockLabel(MBB, false, false, false);
944 // Make sure the instruction that follows TBB is 2-byte aligned.
945 // FIXME: Constant island pass should insert an "ALIGN" instruction instead.
946 if (ByteOffset && (JTBBs.size() & 1)) {
952 void ARMAsmPrinter::printTBAddrMode(const MachineInstr *MI, int OpNum) {
953 O << "[pc, " << TRI->getAsmName(MI->getOperand(OpNum).getReg());
954 if (MI->getOpcode() == ARM::t2TBH)
959 void ARMAsmPrinter::printNoHashImmediate(const MachineInstr *MI, int OpNum) {
960 O << MI->getOperand(OpNum).getImm();
963 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
964 unsigned AsmVariant, const char *ExtraCode){
965 // Does this asm operand have a single letter operand modifier?
966 if (ExtraCode && ExtraCode[0]) {
967 if (ExtraCode[1] != 0) return true; // Unknown modifier.
969 switch (ExtraCode[0]) {
970 default: return true; // Unknown modifier.
971 case 'a': // Print as a memory address.
972 if (MI->getOperand(OpNum).isReg()) {
973 O << "[" << TRI->getAsmName(MI->getOperand(OpNum).getReg()) << "]";
977 case 'c': // Don't print "#" before an immediate operand.
978 if (!MI->getOperand(OpNum).isImm())
980 printNoHashImmediate(MI, OpNum);
982 case 'P': // Print a VFP double precision register.
983 printOperand(MI, OpNum);
986 if (TM.getTargetData()->isLittleEndian())
990 if (TM.getTargetData()->isBigEndian())
993 case 'H': // Write second word of DI / DF reference.
994 // Verify that this operand has two consecutive registers.
995 if (!MI->getOperand(OpNum).isReg() ||
996 OpNum+1 == MI->getNumOperands() ||
997 !MI->getOperand(OpNum+1).isReg())
999 ++OpNum; // Return the high-part.
1003 printOperand(MI, OpNum);
1007 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
1008 unsigned OpNum, unsigned AsmVariant,
1009 const char *ExtraCode) {
1010 if (ExtraCode && ExtraCode[0])
1011 return true; // Unknown modifier.
1012 printAddrMode2Operand(MI, OpNum);
1016 void ARMAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
1019 int Opc = MI->getOpcode();
1021 case ARM::CONSTPOOL_ENTRY:
1022 if (!InCPMode && AFI->isThumbFunction()) {
1028 if (InCPMode && AFI->isThumbFunction())
1032 // Call the autogenerated instruction printer routines.
1033 printInstruction(MI);
1036 bool ARMAsmPrinter::doInitialization(Module &M) {
1038 bool Result = AsmPrinter::doInitialization(M);
1039 DW = getAnalysisIfAvailable<DwarfWriter>();
1041 // Use unified assembler syntax mode for Thumb.
1042 if (Subtarget->isThumb())
1043 O << "\t.syntax unified\n";
1045 // Emit ARM Build Attributes
1046 if (Subtarget->isTargetELF()) {
1048 std::string CPUString = Subtarget->getCPUString();
1049 if (CPUString != "generic")
1050 O << "\t.cpu " << CPUString << '\n';
1052 // FIXME: Emit FPU type
1053 if (Subtarget->hasVFP2())
1054 O << "\t.eabi_attribute " << ARMBuildAttrs::VFP_arch << ", 2\n";
1056 // Signal various FP modes.
1058 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_denormal << ", 1\n"
1059 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_exceptions << ", 1\n";
1061 if (FiniteOnlyFPMath())
1062 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 1\n";
1064 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_FP_number_model << ", 3\n";
1066 // 8-bytes alignment stuff.
1067 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_needed << ", 1\n"
1068 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_align8_preserved << ", 1\n";
1070 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
1071 if (Subtarget->isAAPCS_ABI() && FloatABIType == FloatABI::Hard)
1072 O << "\t.eabi_attribute " << ARMBuildAttrs::ABI_HardFP_use << ", 3\n"
1073 << "\t.eabi_attribute " << ARMBuildAttrs::ABI_VFP_args << ", 1\n";
1075 // FIXME: Should we signal R9 usage?
1081 void ARMAsmPrinter::PrintGlobalVariable(const GlobalVariable* GVar) {
1082 const TargetData *TD = TM.getTargetData();
1084 if (!GVar->hasInitializer()) // External global require no code
1087 // Check to see if this is a special global used by LLVM, if so, emit it.
1089 if (EmitSpecialLLVMGlobal(GVar)) {
1090 if (Subtarget->isTargetDarwin() &&
1091 TM.getRelocationModel() == Reloc::Static) {
1092 if (GVar->getName() == "llvm.global_ctors")
1093 O << ".reference .constructors_used\n";
1094 else if (GVar->getName() == "llvm.global_dtors")
1095 O << ".reference .destructors_used\n";
1100 std::string name = Mang->getMangledName(GVar);
1101 Constant *C = GVar->getInitializer();
1102 const Type *Type = C->getType();
1103 unsigned Size = TD->getTypeAllocSize(Type);
1104 unsigned Align = TD->getPreferredAlignmentLog(GVar);
1105 bool isDarwin = Subtarget->isTargetDarwin();
1107 printVisibility(name, GVar->getVisibility());
1109 if (Subtarget->isTargetELF())
1110 O << "\t.type " << name << ",%object\n";
1112 const MCSection *TheSection =
1113 getObjFileLowering().SectionForGlobal(GVar, Mang, TM);
1114 OutStreamer.SwitchSection(TheSection);
1116 // FIXME: get this stuff from section kind flags.
1117 if (C->isNullValue() && !GVar->hasSection() && !GVar->isThreadLocal() &&
1118 // Don't put things that should go in the cstring section into "comm".
1119 !TheSection->getKind().isMergeableCString()) {
1120 if (GVar->hasExternalLinkage()) {
1121 if (const char *Directive = MAI->getZeroFillDirective()) {
1122 O << "\t.globl\t" << name << "\n";
1123 O << Directive << "__DATA, __common, " << name << ", "
1124 << Size << ", " << Align << "\n";
1129 if (GVar->hasLocalLinkage() || GVar->isWeakForLinker()) {
1130 if (Size == 0) Size = 1; // .comm Foo, 0 is undefined, avoid it.
1133 if (GVar->hasLocalLinkage()) {
1134 O << MAI->getLCOMMDirective() << name << "," << Size
1136 } else if (GVar->hasCommonLinkage()) {
1137 O << MAI->getCOMMDirective() << name << "," << Size
1140 OutStreamer.SwitchSection(TheSection);
1141 O << "\t.globl " << name << '\n'
1142 << MAI->getWeakDefDirective() << name << '\n';
1143 EmitAlignment(Align, GVar);
1146 O << "\t\t\t\t" << MAI->getCommentString() << ' ';
1147 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1150 EmitGlobalConstant(C);
1153 } else if (MAI->getLCOMMDirective() != NULL) {
1154 if (GVar->hasLocalLinkage()) {
1155 O << MAI->getLCOMMDirective() << name << "," << Size;
1157 O << MAI->getCOMMDirective() << name << "," << Size;
1158 if (MAI->getCOMMDirectiveTakesAlignment())
1159 O << ',' << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1162 if (GVar->hasLocalLinkage())
1163 O << "\t.local\t" << name << "\n";
1164 O << MAI->getCOMMDirective() << name << "," << Size;
1165 if (MAI->getCOMMDirectiveTakesAlignment())
1166 O << "," << (MAI->getAlignmentIsInBytes() ? (1 << Align) : Align);
1169 O << "\t\t" << MAI->getCommentString() << " ";
1170 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1177 switch (GVar->getLinkage()) {
1178 case GlobalValue::CommonLinkage:
1179 case GlobalValue::LinkOnceAnyLinkage:
1180 case GlobalValue::LinkOnceODRLinkage:
1181 case GlobalValue::WeakAnyLinkage:
1182 case GlobalValue::WeakODRLinkage:
1183 case GlobalValue::LinkerPrivateLinkage:
1185 O << "\t.globl " << name << "\n"
1186 << "\t.weak_definition " << name << "\n";
1188 O << "\t.weak " << name << "\n";
1191 case GlobalValue::AppendingLinkage:
1192 // FIXME: appending linkage variables should go into a section of
1193 // their name or something. For now, just emit them as external.
1194 case GlobalValue::ExternalLinkage:
1195 O << "\t.globl " << name << "\n";
1197 case GlobalValue::PrivateLinkage:
1198 case GlobalValue::InternalLinkage:
1201 llvm_unreachable("Unknown linkage type!");
1204 EmitAlignment(Align, GVar);
1207 O << "\t\t\t\t" << MAI->getCommentString() << " ";
1208 WriteAsOperand(O, GVar, /*PrintType=*/false, GVar->getParent());
1211 if (MAI->hasDotTypeDotSizeDirective())
1212 O << "\t.size " << name << ", " << Size << "\n";
1214 EmitGlobalConstant(C);
1219 bool ARMAsmPrinter::doFinalization(Module &M) {
1220 if (Subtarget->isTargetDarwin()) {
1221 // All darwin targets use mach-o.
1222 TargetLoweringObjectFileMachO &TLOFMacho =
1223 static_cast<TargetLoweringObjectFileMachO &>(getObjFileLowering());
1227 // Output non-lazy-pointers for external and common global variables.
1228 if (!GVNonLazyPtrs.empty()) {
1229 // Switch with ".non_lazy_symbol_pointer" directive.
1230 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
1232 for (StringMap<std::string>::iterator I = GVNonLazyPtrs.begin(),
1233 E = GVNonLazyPtrs.end(); I != E; ++I) {
1234 O << I->second << ":\n";
1235 O << "\t.indirect_symbol " << I->getKeyData() << "\n";
1236 O << "\t.long\t0\n";
1240 if (!HiddenGVNonLazyPtrs.empty()) {
1241 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
1243 for (StringMap<std::string>::iterator I = HiddenGVNonLazyPtrs.begin(),
1244 E = HiddenGVNonLazyPtrs.end(); I != E; ++I) {
1245 O << I->second << ":\n";
1246 O << "\t.long " << I->getKeyData() << "\n";
1250 // Funny Darwin hack: This flag tells the linker that no global symbols
1251 // contain code that falls through to other global symbols (e.g. the obvious
1252 // implementation of multiple entry points). If this doesn't occur, the
1253 // linker can safely perform dead code stripping. Since LLVM never
1254 // generates code that does this, it is always safe to set.
1255 O << "\t.subsections_via_symbols\n";
1258 return AsmPrinter::doFinalization(M);
1261 // Force static initialization.
1262 extern "C" void LLVMInitializeARMAsmPrinter() {
1263 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1264 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);