1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMMCExpr.h"
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARMSubtarget.h"
15 #include "llvm/MC/MCParser/MCAsmLexer.h"
16 #include "llvm/MC/MCParser/MCAsmParser.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/Target/TargetRegistry.h"
23 #include "llvm/Target/TargetAsmParser.h"
24 #include "llvm/Support/SourceMgr.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
29 #include "llvm/ADT/Twine.h"
32 /// Shift types used for register controlled shifts in ARM memory addressing.
45 class ARMAsmParser : public TargetAsmParser {
49 MCAsmParser &getParser() const { return Parser; }
50 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
52 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
53 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
55 int TryParseRegister();
56 bool TryParseMCRName(SmallVectorImpl<MCParsedAsmOperand*>&);
57 bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
58 bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
59 bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
60 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, bool isMCR);
61 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
62 const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
63 MCSymbolRefExpr::VariantKind Variant);
66 bool ParseMemoryOffsetReg(bool &Negative,
67 bool &OffsetRegShifted,
68 enum ShiftType &ShiftType,
69 const MCExpr *&ShiftAmount,
70 const MCExpr *&Offset,
74 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
75 bool ParseDirectiveWord(unsigned Size, SMLoc L);
76 bool ParseDirectiveThumb(SMLoc L);
77 bool ParseDirectiveThumbFunc(SMLoc L);
78 bool ParseDirectiveCode(SMLoc L);
79 bool ParseDirectiveSyntax(SMLoc L);
81 bool MatchAndEmitInstruction(SMLoc IDLoc,
82 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
84 void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
85 bool &CanAcceptPredicationCode);
87 /// @name Auto-generated Match Functions
90 #define GET_ASSEMBLER_HEADER
91 #include "ARMGenAsmMatcher.inc"
96 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
97 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
98 // Initialize the set of available features.
99 setAvailableFeatures(ComputeAvailableFeatures(
100 &TM.getSubtarget<ARMSubtarget>()));
103 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
104 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
105 virtual bool ParseDirective(AsmToken DirectiveID);
107 } // end anonymous namespace
111 /// ARMOperand - Instances of this class represent a parsed ARM machine
113 class ARMOperand : public MCParsedAsmOperand {
126 SMLoc StartLoc, EndLoc;
127 SmallVector<unsigned, 8> Registers;
131 ARMCC::CondCodes Val;
147 /// Combined record for all forms of ARM address expressions.
151 unsigned RegNum; ///< Offset register num, when OffsetIsReg.
152 const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
154 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
155 enum ShiftType ShiftType; // used when OffsetRegShifted is true
156 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
157 unsigned Preindexed : 1;
158 unsigned Postindexed : 1;
159 unsigned OffsetIsReg : 1;
160 unsigned Negative : 1; // only used when OffsetIsReg is true
161 unsigned Writeback : 1;
165 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
167 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
169 StartLoc = o.StartLoc;
183 case DPRRegisterList:
184 case SPRRegisterList:
185 Registers = o.Registers;
196 /// getStartLoc - Get the location of the first token of this operand.
197 SMLoc getStartLoc() const { return StartLoc; }
198 /// getEndLoc - Get the location of the last token of this operand.
199 SMLoc getEndLoc() const { return EndLoc; }
201 ARMCC::CondCodes getCondCode() const {
202 assert(Kind == CondCode && "Invalid access!");
206 StringRef getToken() const {
207 assert(Kind == Token && "Invalid access!");
208 return StringRef(Tok.Data, Tok.Length);
211 unsigned getReg() const {
212 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
216 const SmallVectorImpl<unsigned> &getRegList() const {
217 assert((Kind == RegisterList || Kind == DPRRegisterList ||
218 Kind == SPRRegisterList) && "Invalid access!");
222 const MCExpr *getImm() const {
223 assert(Kind == Immediate && "Invalid access!");
227 /// @name Memory Operand Accessors
230 unsigned getMemBaseRegNum() const {
231 return Mem.BaseRegNum;
233 unsigned getMemOffsetRegNum() const {
234 assert(Mem.OffsetIsReg && "Invalid access!");
235 return Mem.Offset.RegNum;
237 const MCExpr *getMemOffset() const {
238 assert(!Mem.OffsetIsReg && "Invalid access!");
239 return Mem.Offset.Value;
241 unsigned getMemOffsetRegShifted() const {
242 assert(Mem.OffsetIsReg && "Invalid access!");
243 return Mem.OffsetRegShifted;
245 const MCExpr *getMemShiftAmount() const {
246 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
247 return Mem.ShiftAmount;
249 enum ShiftType getMemShiftType() const {
250 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
251 return Mem.ShiftType;
253 bool getMemPreindexed() const { return Mem.Preindexed; }
254 bool getMemPostindexed() const { return Mem.Postindexed; }
255 bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; }
256 bool getMemNegative() const { return Mem.Negative; }
257 bool getMemWriteback() const { return Mem.Writeback; }
261 bool isCondCode() const { return Kind == CondCode; }
262 bool isCCOut() const { return Kind == CCOut; }
263 bool isImm() const { return Kind == Immediate; }
264 bool isReg() const { return Kind == Register; }
265 bool isRegList() const { return Kind == RegisterList; }
266 bool isDPRRegList() const { return Kind == DPRRegisterList; }
267 bool isSPRRegList() const { return Kind == SPRRegisterList; }
268 bool isToken() const { return Kind == Token; }
269 bool isMemory() const { return Kind == Memory; }
270 bool isMemMode5() const {
271 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
275 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
276 if (!CE) return false;
278 // The offset must be a multiple of 4 in the range 0-1020.
279 int64_t Value = CE->getValue();
280 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
282 bool isMemModeRegThumb() const {
283 if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback())
287 bool isMemModeImmThumb() const {
288 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback())
291 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
292 if (!CE) return false;
294 // The offset must be a multiple of 4 in the range 0-124.
295 uint64_t Value = CE->getValue();
296 return ((Value & 0x3) == 0 && Value <= 124);
299 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
300 // Add as immediates when possible. Null MCExpr = 0.
302 Inst.addOperand(MCOperand::CreateImm(0));
303 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
304 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
306 Inst.addOperand(MCOperand::CreateExpr(Expr));
309 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
310 assert(N == 2 && "Invalid number of operands!");
311 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
312 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
313 Inst.addOperand(MCOperand::CreateReg(RegNum));
316 void addCCOutOperands(MCInst &Inst, unsigned N) const {
317 assert(N == 1 && "Invalid number of operands!");
318 Inst.addOperand(MCOperand::CreateReg(getReg()));
321 void addRegOperands(MCInst &Inst, unsigned N) const {
322 assert(N == 1 && "Invalid number of operands!");
323 Inst.addOperand(MCOperand::CreateReg(getReg()));
326 void addRegListOperands(MCInst &Inst, unsigned N) const {
327 assert(N == 1 && "Invalid number of operands!");
328 const SmallVectorImpl<unsigned> &RegList = getRegList();
329 for (SmallVectorImpl<unsigned>::const_iterator
330 I = RegList.begin(), E = RegList.end(); I != E; ++I)
331 Inst.addOperand(MCOperand::CreateReg(*I));
334 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
335 addRegListOperands(Inst, N);
338 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
339 addRegListOperands(Inst, N);
342 void addImmOperands(MCInst &Inst, unsigned N) const {
343 assert(N == 1 && "Invalid number of operands!");
344 addExpr(Inst, getImm());
347 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
348 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
350 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
351 assert(!getMemOffsetIsReg() && "Invalid mode 5 operand");
353 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
355 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
356 assert(CE && "Non-constant mode 5 offset operand!");
358 // The MCInst offset operand doesn't include the low two bits (like
359 // the instruction encoding).
360 int64_t Offset = CE->getValue() / 4;
362 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
365 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
369 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
370 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
371 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
372 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
375 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
376 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
377 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
378 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
379 assert(CE && "Non-constant mode offset operand!");
380 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
383 virtual void dump(raw_ostream &OS) const;
385 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
386 ARMOperand *Op = new ARMOperand(CondCode);
393 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
394 ARMOperand *Op = new ARMOperand(CCOut);
395 Op->Reg.RegNum = RegNum;
401 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
402 ARMOperand *Op = new ARMOperand(Token);
403 Op->Tok.Data = Str.data();
404 Op->Tok.Length = Str.size();
410 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
411 ARMOperand *Op = new ARMOperand(Register);
412 Op->Reg.RegNum = RegNum;
419 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
420 SMLoc StartLoc, SMLoc EndLoc) {
421 KindTy Kind = RegisterList;
423 if (ARM::DPRRegClass.contains(Regs.front().first))
424 Kind = DPRRegisterList;
425 else if (ARM::SPRRegClass.contains(Regs.front().first))
426 Kind = SPRRegisterList;
428 ARMOperand *Op = new ARMOperand(Kind);
429 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
430 I = Regs.begin(), E = Regs.end(); I != E; ++I)
431 Op->Registers.push_back(I->first);
432 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
433 Op->StartLoc = StartLoc;
438 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
439 ARMOperand *Op = new ARMOperand(Immediate);
446 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
447 const MCExpr *Offset, int OffsetRegNum,
448 bool OffsetRegShifted, enum ShiftType ShiftType,
449 const MCExpr *ShiftAmount, bool Preindexed,
450 bool Postindexed, bool Negative, bool Writeback,
452 assert((OffsetRegNum == -1 || OffsetIsReg) &&
453 "OffsetRegNum must imply OffsetIsReg!");
454 assert((!OffsetRegShifted || OffsetIsReg) &&
455 "OffsetRegShifted must imply OffsetIsReg!");
456 assert((Offset || OffsetIsReg) &&
457 "Offset must exists unless register offset is used!");
458 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
459 "Cannot have shift amount without shifted register offset!");
460 assert((!Offset || !OffsetIsReg) &&
461 "Cannot have expression offset and register offset!");
463 ARMOperand *Op = new ARMOperand(Memory);
464 Op->Mem.BaseRegNum = BaseRegNum;
465 Op->Mem.OffsetIsReg = OffsetIsReg;
467 Op->Mem.Offset.RegNum = OffsetRegNum;
469 Op->Mem.Offset.Value = Offset;
470 Op->Mem.OffsetRegShifted = OffsetRegShifted;
471 Op->Mem.ShiftType = ShiftType;
472 Op->Mem.ShiftAmount = ShiftAmount;
473 Op->Mem.Preindexed = Preindexed;
474 Op->Mem.Postindexed = Postindexed;
475 Op->Mem.Negative = Negative;
476 Op->Mem.Writeback = Writeback;
484 } // end anonymous namespace.
486 void ARMOperand::dump(raw_ostream &OS) const {
489 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
492 OS << "<ccout " << getReg() << ">";
499 << "base:" << getMemBaseRegNum();
500 if (getMemOffsetIsReg()) {
501 OS << " offset:<register " << getMemOffsetRegNum();
502 if (getMemOffsetRegShifted()) {
503 OS << " offset-shift-type:" << getMemShiftType();
504 OS << " offset-shift-amount:" << *getMemShiftAmount();
507 OS << " offset:" << *getMemOffset();
509 if (getMemOffsetIsReg())
510 OS << " (offset-is-reg)";
511 if (getMemPreindexed())
512 OS << " (pre-indexed)";
513 if (getMemPostindexed())
514 OS << " (post-indexed)";
515 if (getMemNegative())
517 if (getMemWriteback())
518 OS << " (writeback)";
522 OS << "<register " << getReg() << ">";
525 case DPRRegisterList:
526 case SPRRegisterList: {
527 OS << "<register_list ";
529 const SmallVectorImpl<unsigned> &RegList = getRegList();
530 for (SmallVectorImpl<unsigned>::const_iterator
531 I = RegList.begin(), E = RegList.end(); I != E; ) {
533 if (++I < E) OS << ", ";
540 OS << "'" << getToken() << "'";
545 /// @name Auto-generated Match Functions
548 static unsigned MatchRegisterName(StringRef Name);
552 /// Try to parse a register name. The token must be an Identifier when called,
553 /// and if it is a register name the token is eaten and the register number is
554 /// returned. Otherwise return -1.
556 int ARMAsmParser::TryParseRegister() {
557 const AsmToken &Tok = Parser.getTok();
558 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
560 // FIXME: Validate register for the current architecture; we have to do
561 // validation later, so maybe there is no need for this here.
562 std::string upperCase = Tok.getString().str();
563 std::string lowerCase = LowercaseString(upperCase);
564 unsigned RegNum = MatchRegisterName(lowerCase);
566 RegNum = StringSwitch<unsigned>(lowerCase)
567 .Case("r13", ARM::SP)
568 .Case("r14", ARM::LR)
569 .Case("r15", ARM::PC)
570 .Case("ip", ARM::R12)
573 if (!RegNum) return -1;
575 Parser.Lex(); // Eat identifier token.
580 /// Try to parse a register name. The token must be an Identifier when called.
581 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
582 /// if there is a "writeback". 'true' if it's not a register.
584 /// TODO this is likely to change to allow different register types and or to
585 /// parse for a specific register type.
587 TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
588 SMLoc S = Parser.getTok().getLoc();
589 int RegNo = TryParseRegister();
593 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
595 const AsmToken &ExclaimTok = Parser.getTok();
596 if (ExclaimTok.is(AsmToken::Exclaim)) {
597 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
598 ExclaimTok.getLoc()));
599 Parser.Lex(); // Eat exclaim token
605 static int MatchMCRName(StringRef Name) {
606 // Use the same layout as the tablegen'erated register name matcher. Ugly,
608 switch (Name.size()) {
611 if (Name[0] != 'p' && Name[0] != 'c')
628 if ((Name[0] != 'p' && Name[0] != 'c') || Name[1] != '1')
642 llvm_unreachable("Unhandled coprocessor operand string!");
646 /// TryParseMCRName - Try to parse an MCR/MRC symbolic operand
647 /// name. The token must be an Identifier when called, and if it is a MCR
648 /// operand name, the token is eaten and the operand is added to the
651 TryParseMCRName(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
652 SMLoc S = Parser.getTok().getLoc();
653 const AsmToken &Tok = Parser.getTok();
654 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
656 int Num = MatchMCRName(Tok.getString());
660 Parser.Lex(); // Eat identifier token.
661 Operands.push_back(ARMOperand::CreateImm(
662 MCConstantExpr::Create(Num, getContext()), S, Parser.getTok().getLoc()));
666 /// Parse a register list, return it if successful else return null. The first
667 /// token must be a '{' when called.
669 ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
670 assert(Parser.getTok().is(AsmToken::LCurly) &&
671 "Token is not a Left Curly Brace");
672 SMLoc S = Parser.getTok().getLoc();
674 // Read the rest of the registers in the list.
675 unsigned PrevRegNum = 0;
676 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
679 bool IsRange = Parser.getTok().is(AsmToken::Minus);
680 Parser.Lex(); // Eat non-identifier token.
682 const AsmToken &RegTok = Parser.getTok();
683 SMLoc RegLoc = RegTok.getLoc();
684 if (RegTok.isNot(AsmToken::Identifier)) {
685 Error(RegLoc, "register expected");
689 int RegNum = TryParseRegister();
691 Error(RegLoc, "register expected");
696 int Reg = PrevRegNum;
699 Registers.push_back(std::make_pair(Reg, RegLoc));
700 } while (Reg != RegNum);
702 Registers.push_back(std::make_pair(RegNum, RegLoc));
706 } while (Parser.getTok().is(AsmToken::Comma) ||
707 Parser.getTok().is(AsmToken::Minus));
709 // Process the right curly brace of the list.
710 const AsmToken &RCurlyTok = Parser.getTok();
711 if (RCurlyTok.isNot(AsmToken::RCurly)) {
712 Error(RCurlyTok.getLoc(), "'}' expected");
716 SMLoc E = RCurlyTok.getLoc();
717 Parser.Lex(); // Eat right curly brace token.
719 // Verify the register list.
720 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
721 RI = Registers.begin(), RE = Registers.end();
723 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
724 bool EmittedWarning = false;
726 DenseMap<unsigned, bool> RegMap;
727 RegMap[HighRegNum] = true;
729 for (++RI; RI != RE; ++RI) {
730 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
731 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
734 Error(RegInfo.second, "register duplicated in register list");
738 if (!EmittedWarning && Reg < HighRegNum)
739 Warning(RegInfo.second,
740 "register not in ascending order in register list");
743 HighRegNum = std::max(Reg, HighRegNum);
746 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
750 /// Parse an ARM memory expression, return false if successful else return true
751 /// or an error. The first token must be a '[' when called.
753 /// TODO Only preindexing and postindexing addressing are started, unindexed
754 /// with option, etc are still to do.
756 ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
758 assert(Parser.getTok().is(AsmToken::LBrac) &&
759 "Token is not a Left Bracket");
760 S = Parser.getTok().getLoc();
761 Parser.Lex(); // Eat left bracket token.
763 const AsmToken &BaseRegTok = Parser.getTok();
764 if (BaseRegTok.isNot(AsmToken::Identifier)) {
765 Error(BaseRegTok.getLoc(), "register expected");
768 int BaseRegNum = TryParseRegister();
769 if (BaseRegNum == -1) {
770 Error(BaseRegTok.getLoc(), "register expected");
774 // The next token must either be a comma or a closing bracket.
775 const AsmToken &Tok = Parser.getTok();
776 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
779 bool Preindexed = false;
780 bool Postindexed = false;
781 bool OffsetIsReg = false;
782 bool Negative = false;
783 bool Writeback = false;
784 ARMOperand *WBOp = 0;
785 int OffsetRegNum = -1;
786 bool OffsetRegShifted = false;
787 enum ShiftType ShiftType = Lsl;
788 const MCExpr *ShiftAmount = 0;
789 const MCExpr *Offset = 0;
791 // First look for preindexed address forms, that is after the "[Rn" we now
792 // have to see if the next token is a comma.
793 if (Tok.is(AsmToken::Comma)) {
795 Parser.Lex(); // Eat comma token.
797 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
798 Offset, OffsetIsReg, OffsetRegNum, E))
800 const AsmToken &RBracTok = Parser.getTok();
801 if (RBracTok.isNot(AsmToken::RBrac)) {
802 Error(RBracTok.getLoc(), "']' expected");
805 E = RBracTok.getLoc();
806 Parser.Lex(); // Eat right bracket token.
808 const AsmToken &ExclaimTok = Parser.getTok();
809 if (ExclaimTok.is(AsmToken::Exclaim)) {
810 WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
811 ExclaimTok.getLoc());
813 Parser.Lex(); // Eat exclaim token
816 // The "[Rn" we have so far was not followed by a comma.
818 // If there's anything other than the right brace, this is a post indexing
821 Parser.Lex(); // Eat right bracket token.
823 const AsmToken &NextTok = Parser.getTok();
825 if (NextTok.isNot(AsmToken::EndOfStatement)) {
829 if (NextTok.isNot(AsmToken::Comma)) {
830 Error(NextTok.getLoc(), "',' expected");
834 Parser.Lex(); // Eat comma token.
836 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
837 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
843 // Force Offset to exist if used.
846 Offset = MCConstantExpr::Create(0, getContext());
849 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
850 OffsetRegNum, OffsetRegShifted,
851 ShiftType, ShiftAmount, Preindexed,
852 Postindexed, Negative, Writeback,
855 Operands.push_back(WBOp);
860 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
861 /// we will parse the following (were +/- means that a plus or minus is
866 /// we return false on success or an error otherwise.
867 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
868 bool &OffsetRegShifted,
869 enum ShiftType &ShiftType,
870 const MCExpr *&ShiftAmount,
871 const MCExpr *&Offset,
876 OffsetRegShifted = false;
879 const AsmToken &NextTok = Parser.getTok();
880 E = NextTok.getLoc();
881 if (NextTok.is(AsmToken::Plus))
882 Parser.Lex(); // Eat plus token.
883 else if (NextTok.is(AsmToken::Minus)) {
885 Parser.Lex(); // Eat minus token
887 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
888 const AsmToken &OffsetRegTok = Parser.getTok();
889 if (OffsetRegTok.is(AsmToken::Identifier)) {
890 SMLoc CurLoc = OffsetRegTok.getLoc();
891 OffsetRegNum = TryParseRegister();
892 if (OffsetRegNum != -1) {
898 // If we parsed a register as the offset then there can be a shift after that.
899 if (OffsetRegNum != -1) {
900 // Look for a comma then a shift
901 const AsmToken &Tok = Parser.getTok();
902 if (Tok.is(AsmToken::Comma)) {
903 Parser.Lex(); // Eat comma token.
905 const AsmToken &Tok = Parser.getTok();
906 if (ParseShift(ShiftType, ShiftAmount, E))
907 return Error(Tok.getLoc(), "shift expected");
908 OffsetRegShifted = true;
911 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
912 // Look for #offset following the "[Rn," or "[Rn],"
913 const AsmToken &HashTok = Parser.getTok();
914 if (HashTok.isNot(AsmToken::Hash))
915 return Error(HashTok.getLoc(), "'#' expected");
917 Parser.Lex(); // Eat hash token.
919 if (getParser().ParseExpression(Offset))
921 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
926 /// ParseShift as one of these two:
927 /// ( lsl | lsr | asr | ror ) , # shift_amount
929 /// and returns true if it parses a shift otherwise it returns false.
930 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
932 const AsmToken &Tok = Parser.getTok();
933 if (Tok.isNot(AsmToken::Identifier))
935 StringRef ShiftName = Tok.getString();
936 if (ShiftName == "lsl" || ShiftName == "LSL")
938 else if (ShiftName == "lsr" || ShiftName == "LSR")
940 else if (ShiftName == "asr" || ShiftName == "ASR")
942 else if (ShiftName == "ror" || ShiftName == "ROR")
944 else if (ShiftName == "rrx" || ShiftName == "RRX")
948 Parser.Lex(); // Eat shift type token.
954 // Otherwise, there must be a '#' and a shift amount.
955 const AsmToken &HashTok = Parser.getTok();
956 if (HashTok.isNot(AsmToken::Hash))
957 return Error(HashTok.getLoc(), "'#' expected");
958 Parser.Lex(); // Eat hash token.
960 if (getParser().ParseExpression(ShiftAmount))
966 /// Parse a arm instruction operand. For now this parses the operand regardless
968 bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
971 switch (getLexer().getKind()) {
973 Error(Parser.getTok().getLoc(), "unexpected token in operand");
975 case AsmToken::Identifier:
976 if (!TryParseRegisterWithWriteBack(Operands))
978 if (isMCR && !TryParseMCRName(Operands))
981 // Fall though for the Identifier case that is not a register or a
983 case AsmToken::Integer: // things like 1f and 2b as a branch targets
984 case AsmToken::Dot: { // . as a branch target
985 // This was not a register so parse other operands that start with an
986 // identifier (like labels) as expressions and create them as immediates.
988 S = Parser.getTok().getLoc();
989 if (getParser().ParseExpression(IdVal))
991 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
992 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
995 case AsmToken::LBrac:
996 return ParseMemory(Operands);
997 case AsmToken::LCurly:
998 return ParseRegisterList(Operands);
1000 // #42 -> immediate.
1001 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
1002 S = Parser.getTok().getLoc();
1004 const MCExpr *ImmVal;
1005 if (getParser().ParseExpression(ImmVal))
1007 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1008 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
1010 case AsmToken::Colon: {
1011 // ":lower16:" and ":upper16:" expression prefixes
1012 // FIXME: Check it's an expression prefix,
1013 // e.g. (FOO - :lower16:BAR) isn't legal.
1014 ARMMCExpr::VariantKind RefKind;
1015 if (ParsePrefix(RefKind))
1018 const MCExpr *SubExprVal;
1019 if (getParser().ParseExpression(SubExprVal))
1022 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
1024 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1025 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
1031 // ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
1032 // :lower16: and :upper16:.
1033 bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
1034 RefKind = ARMMCExpr::VK_ARM_None;
1036 // :lower16: and :upper16: modifiers
1037 assert(getLexer().is(AsmToken::Colon) && "expected a :");
1038 Parser.Lex(); // Eat ':'
1040 if (getLexer().isNot(AsmToken::Identifier)) {
1041 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
1045 StringRef IDVal = Parser.getTok().getIdentifier();
1046 if (IDVal == "lower16") {
1047 RefKind = ARMMCExpr::VK_ARM_LO16;
1048 } else if (IDVal == "upper16") {
1049 RefKind = ARMMCExpr::VK_ARM_HI16;
1051 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
1056 if (getLexer().isNot(AsmToken::Colon)) {
1057 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
1060 Parser.Lex(); // Eat the last ':'
1065 ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
1066 MCSymbolRefExpr::VariantKind Variant) {
1067 // Recurse over the given expression, rebuilding it to apply the given variant
1068 // to the leftmost symbol.
1069 if (Variant == MCSymbolRefExpr::VK_None)
1072 switch (E->getKind()) {
1073 case MCExpr::Target:
1074 llvm_unreachable("Can't handle target expr yet");
1075 case MCExpr::Constant:
1076 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
1078 case MCExpr::SymbolRef: {
1079 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1081 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
1084 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
1088 llvm_unreachable("Can't handle unary expressions yet");
1090 case MCExpr::Binary: {
1091 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1092 const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant);
1093 const MCExpr *RHS = BE->getRHS();
1097 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
1101 assert(0 && "Invalid expression kind!");
1105 /// \brief Given a mnemonic, split out possible predication code and carry
1106 /// setting letters to form a canonical mnemonic and flags.
1108 // FIXME: Would be nice to autogen this.
1109 static StringRef SplitMnemonicAndCC(StringRef Mnemonic,
1110 unsigned &PredicationCode,
1111 bool &CarrySetting) {
1112 PredicationCode = ARMCC::AL;
1113 CarrySetting = false;
1115 // Ignore some mnemonics we know aren't predicated forms.
1117 // FIXME: Would be nice to autogen this.
1118 if (Mnemonic == "teq" || Mnemonic == "vceq" ||
1119 Mnemonic == "movs" ||
1120 Mnemonic == "svc" ||
1121 (Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
1122 Mnemonic == "vmls" || Mnemonic == "vnmls") ||
1123 Mnemonic == "vacge" || Mnemonic == "vcge" ||
1124 Mnemonic == "vclt" ||
1125 Mnemonic == "vacgt" || Mnemonic == "vcgt" ||
1126 Mnemonic == "vcle" ||
1127 (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" ||
1128 Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" ||
1129 Mnemonic == "vqdmlal"))
1132 // First, split out any predication code.
1133 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
1134 .Case("eq", ARMCC::EQ)
1135 .Case("ne", ARMCC::NE)
1136 .Case("hs", ARMCC::HS)
1137 .Case("lo", ARMCC::LO)
1138 .Case("mi", ARMCC::MI)
1139 .Case("pl", ARMCC::PL)
1140 .Case("vs", ARMCC::VS)
1141 .Case("vc", ARMCC::VC)
1142 .Case("hi", ARMCC::HI)
1143 .Case("ls", ARMCC::LS)
1144 .Case("ge", ARMCC::GE)
1145 .Case("lt", ARMCC::LT)
1146 .Case("gt", ARMCC::GT)
1147 .Case("le", ARMCC::LE)
1148 .Case("al", ARMCC::AL)
1151 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
1152 PredicationCode = CC;
1155 // Next, determine if we have a carry setting bit. We explicitly ignore all
1156 // the instructions we know end in 's'.
1157 if (Mnemonic.endswith("s") &&
1158 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
1159 Mnemonic == "movs" || Mnemonic == "mrs" || Mnemonic == "smmls" ||
1160 Mnemonic == "vabs" || Mnemonic == "vcls" || Mnemonic == "vmls" ||
1161 Mnemonic == "vmrs" || Mnemonic == "vnmls" || Mnemonic == "vqabs" ||
1162 Mnemonic == "vrecps" || Mnemonic == "vrsqrts")) {
1163 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
1164 CarrySetting = true;
1170 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
1171 /// inclusion of carry set or predication code operands.
1173 // FIXME: It would be nice to autogen this.
1175 GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
1176 bool &CanAcceptPredicationCode) {
1177 bool isThumb = TM.getSubtarget<ARMSubtarget>().isThumb();
1179 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
1180 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
1181 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
1182 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
1183 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mov" ||
1184 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
1185 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
1186 Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "mvn") {
1187 CanAcceptCarrySet = true;
1189 CanAcceptCarrySet = false;
1192 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
1193 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
1194 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
1195 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
1196 Mnemonic == "dsb" || Mnemonic == "movs" ||
1197 (isThumb && Mnemonic == "bkpt")) {
1198 CanAcceptPredicationCode = false;
1200 CanAcceptPredicationCode = true;
1204 /// Parse an arm instruction mnemonic followed by its operands.
1205 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
1206 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1207 // Create the leading tokens for the mnemonic, split by '.' characters.
1208 size_t Start = 0, Next = Name.find('.');
1209 StringRef Head = Name.slice(Start, Next);
1211 // Split out the predication code and carry setting flag from the mnemonic.
1212 unsigned PredicationCode;
1214 Head = SplitMnemonicAndCC(Head, PredicationCode, CarrySetting);
1216 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
1218 // Next, add the CCOut and ConditionCode operands, if needed.
1220 // For mnemonics which can ever incorporate a carry setting bit or predication
1221 // code, our matching model involves us always generating CCOut and
1222 // ConditionCode operands to match the mnemonic "as written" and then we let
1223 // the matcher deal with finding the right instruction or generating an
1224 // appropriate error.
1225 bool CanAcceptCarrySet, CanAcceptPredicationCode;
1226 GetMnemonicAcceptInfo(Head, CanAcceptCarrySet, CanAcceptPredicationCode);
1228 // Add the carry setting operand, if necessary.
1230 // FIXME: It would be awesome if we could somehow invent a location such that
1231 // match errors on this operand would print a nice diagnostic about how the
1232 // 's' character in the mnemonic resulted in a CCOut operand.
1233 if (CanAcceptCarrySet) {
1234 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
1237 // This mnemonic can't ever accept a carry set, but the user wrote one (or
1238 // misspelled another mnemonic).
1240 // FIXME: Issue a nice error.
1243 // Add the predication code operand, if necessary.
1244 if (CanAcceptPredicationCode) {
1245 Operands.push_back(ARMOperand::CreateCondCode(
1246 ARMCC::CondCodes(PredicationCode), NameLoc));
1248 // This mnemonic can't ever accept a predication code, but the user wrote
1249 // one (or misspelled another mnemonic).
1251 // FIXME: Issue a nice error.
1254 // Add the remaining tokens in the mnemonic.
1255 while (Next != StringRef::npos) {
1257 Next = Name.find('.', Start + 1);
1258 Head = Name.slice(Start, Next);
1260 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
1263 bool isMCR = (Head == "mcr" || Head == "mcr2" ||
1264 Head == "mcrr" || Head == "mcrr2" ||
1265 Head == "mrc" || Head == "mrc2" ||
1266 Head == "mrrc" || Head == "mrrc2");
1268 // Read the remaining operands.
1269 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1270 // Read the first operand.
1271 if (ParseOperand(Operands, isMCR)) {
1272 Parser.EatToEndOfStatement();
1276 while (getLexer().is(AsmToken::Comma)) {
1277 Parser.Lex(); // Eat the comma.
1279 // Parse and remember the operand.
1280 if (ParseOperand(Operands, isMCR)) {
1281 Parser.EatToEndOfStatement();
1287 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1288 Parser.EatToEndOfStatement();
1289 return TokError("unexpected token in argument list");
1292 Parser.Lex(); // Consume the EndOfStatement
1297 MatchAndEmitInstruction(SMLoc IDLoc,
1298 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1302 MatchResultTy MatchResult, MatchResult2;
1303 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1304 if (MatchResult != Match_Success) {
1305 // If we get a Match_InvalidOperand it might be some arithmetic instruction
1306 // that does not update the condition codes. So try adding a CCOut operand
1307 // with a value of reg0.
1308 if (MatchResult == Match_InvalidOperand) {
1309 Operands.insert(Operands.begin() + 1,
1310 ARMOperand::CreateCCOut(0,
1311 ((ARMOperand*)Operands[0])->getStartLoc()));
1312 MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1313 if (MatchResult2 == Match_Success)
1314 MatchResult = Match_Success;
1316 ARMOperand *CCOut = ((ARMOperand*)Operands[1]);
1317 Operands.erase(Operands.begin() + 1);
1321 // If we get a Match_MnemonicFail it might be some arithmetic instruction
1322 // that updates the condition codes if it ends in 's'. So see if the
1323 // mnemonic ends in 's' and if so try removing the 's' and adding a CCOut
1324 // operand with a value of CPSR.
1325 else if(MatchResult == Match_MnemonicFail) {
1326 // Get the instruction mnemonic, which is the first token.
1327 StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken();
1328 if (Mnemonic.substr(Mnemonic.size()-1) == "s") {
1329 // removed the 's' from the mnemonic for matching.
1330 StringRef MnemonicNoS = Mnemonic.slice(0, Mnemonic.size() - 1);
1331 SMLoc NameLoc = ((ARMOperand*)Operands[0])->getStartLoc();
1332 ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]);
1333 Operands.erase(Operands.begin());
1335 Operands.insert(Operands.begin(),
1336 ARMOperand::CreateToken(MnemonicNoS, NameLoc));
1337 Operands.insert(Operands.begin() + 1,
1338 ARMOperand::CreateCCOut(ARM::CPSR, NameLoc));
1339 MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1340 if (MatchResult2 == Match_Success)
1341 MatchResult = Match_Success;
1343 ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]);
1344 Operands.erase(Operands.begin());
1346 Operands.insert(Operands.begin(),
1347 ARMOperand::CreateToken(Mnemonic, NameLoc));
1348 ARMOperand *CCOut = ((ARMOperand*)Operands[1]);
1349 Operands.erase(Operands.begin() + 1);
1355 switch (MatchResult) {
1357 Out.EmitInstruction(Inst);
1359 case Match_MissingFeature:
1360 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1362 case Match_InvalidOperand: {
1363 SMLoc ErrorLoc = IDLoc;
1364 if (ErrorInfo != ~0U) {
1365 if (ErrorInfo >= Operands.size())
1366 return Error(IDLoc, "too few operands for instruction");
1368 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
1369 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1372 return Error(ErrorLoc, "invalid operand for instruction");
1374 case Match_MnemonicFail:
1375 return Error(IDLoc, "unrecognized instruction mnemonic");
1378 llvm_unreachable("Implement any new match types added!");
1382 /// ParseDirective parses the arm specific directives
1383 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
1384 StringRef IDVal = DirectiveID.getIdentifier();
1385 if (IDVal == ".word")
1386 return ParseDirectiveWord(4, DirectiveID.getLoc());
1387 else if (IDVal == ".thumb")
1388 return ParseDirectiveThumb(DirectiveID.getLoc());
1389 else if (IDVal == ".thumb_func")
1390 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
1391 else if (IDVal == ".code")
1392 return ParseDirectiveCode(DirectiveID.getLoc());
1393 else if (IDVal == ".syntax")
1394 return ParseDirectiveSyntax(DirectiveID.getLoc());
1398 /// ParseDirectiveWord
1399 /// ::= .word [ expression (, expression)* ]
1400 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1401 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1403 const MCExpr *Value;
1404 if (getParser().ParseExpression(Value))
1407 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
1409 if (getLexer().is(AsmToken::EndOfStatement))
1412 // FIXME: Improve diagnostic.
1413 if (getLexer().isNot(AsmToken::Comma))
1414 return Error(L, "unexpected token in directive");
1423 /// ParseDirectiveThumb
1425 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
1426 if (getLexer().isNot(AsmToken::EndOfStatement))
1427 return Error(L, "unexpected token in directive");
1430 // TODO: set thumb mode
1431 // TODO: tell the MC streamer the mode
1432 // getParser().getStreamer().Emit???();
1436 /// ParseDirectiveThumbFunc
1437 /// ::= .thumbfunc symbol_name
1438 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
1439 const AsmToken &Tok = Parser.getTok();
1440 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
1441 return Error(L, "unexpected token in .thumb_func directive");
1442 StringRef Name = Tok.getString();
1443 Parser.Lex(); // Consume the identifier token.
1444 if (getLexer().isNot(AsmToken::EndOfStatement))
1445 return Error(L, "unexpected token in directive");
1448 // Mark symbol as a thumb symbol.
1449 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
1450 getParser().getStreamer().EmitThumbFunc(Func);
1454 /// ParseDirectiveSyntax
1455 /// ::= .syntax unified | divided
1456 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
1457 const AsmToken &Tok = Parser.getTok();
1458 if (Tok.isNot(AsmToken::Identifier))
1459 return Error(L, "unexpected token in .syntax directive");
1460 StringRef Mode = Tok.getString();
1461 if (Mode == "unified" || Mode == "UNIFIED")
1463 else if (Mode == "divided" || Mode == "DIVIDED")
1466 return Error(L, "unrecognized syntax mode in .syntax directive");
1468 if (getLexer().isNot(AsmToken::EndOfStatement))
1469 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1472 // TODO tell the MC streamer the mode
1473 // getParser().getStreamer().Emit???();
1477 /// ParseDirectiveCode
1478 /// ::= .code 16 | 32
1479 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
1480 const AsmToken &Tok = Parser.getTok();
1481 if (Tok.isNot(AsmToken::Integer))
1482 return Error(L, "unexpected token in .code directive");
1483 int64_t Val = Parser.getTok().getIntVal();
1489 return Error(L, "invalid operand to .code directive");
1491 if (getLexer().isNot(AsmToken::EndOfStatement))
1492 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1495 // FIXME: We need to be able switch subtargets at this point so that
1496 // MatchInstructionImpl() will work when it gets the AvailableFeatures which
1497 // includes Feature_IsThumb or not to match the right instructions. This is
1498 // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine.
1500 assert(TM.getSubtarget<ARMSubtarget>().isThumb() &&
1501 "switching between arm/thumb not yet suppported via .code 16)");
1502 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
1505 assert(!TM.getSubtarget<ARMSubtarget>().isThumb() &&
1506 "switching between thumb/arm not yet suppported via .code 32)");
1507 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1513 extern "C" void LLVMInitializeARMAsmLexer();
1515 /// Force static initialization.
1516 extern "C" void LLVMInitializeARMAsmParser() {
1517 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
1518 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
1519 LLVMInitializeARMAsmLexer();
1522 #define GET_REGISTER_MATCHER
1523 #define GET_MATCHER_IMPLEMENTATION
1524 #include "ARMGenAsmMatcher.inc"