1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringSwitch.h"
34 #include "llvm/ADT/Twine.h"
42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
44 class ARMAsmParser : public MCTargetAsmParser {
49 ARMCC::CondCodes Cond; // Condition for IT block.
50 unsigned Mask:4; // Condition mask for instructions.
51 // Starting at first 1 (from lsb).
52 // '1' condition as indicated in IT.
53 // '0' inverse of condition (else).
54 // Count of instructions in IT block is
55 // 4 - trailingzeroes(mask)
57 bool FirstCond; // Explicit flag for when we're parsing the
58 // First instruction in the IT block. It's
59 // implied in the mask, so needs special
62 unsigned CurPosition; // Current position in parsing of IT
63 // block. In range [0,3]. Initialized
64 // according to count of instructions in block.
65 // ~0U if no active IT block.
67 bool inITBlock() { return ITState.CurPosition != ~0U;}
68 void forwardITPosition() {
69 if (!inITBlock()) return;
70 // Move to the next instruction in the IT block, if there is one. If not,
71 // mark the block as done.
72 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
73 if (++ITState.CurPosition == 5 - TZ)
74 ITState.CurPosition = ~0U; // Done with the IT block after this.
78 MCAsmParser &getParser() const { return Parser; }
79 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
81 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
82 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
84 int tryParseRegister();
85 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
86 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
88 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
89 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
90 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
91 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
92 unsigned &ShiftAmount);
93 bool parseDirectiveWord(unsigned Size, SMLoc L);
94 bool parseDirectiveThumb(SMLoc L);
95 bool parseDirectiveThumbFunc(SMLoc L);
96 bool parseDirectiveCode(SMLoc L);
97 bool parseDirectiveSyntax(SMLoc L);
99 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
100 bool &CarrySetting, unsigned &ProcessorIMod,
102 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
103 bool &CanAcceptPredicationCode);
105 bool isThumb() const {
106 // FIXME: Can tablegen auto-generate this?
107 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
109 bool isThumbOne() const {
110 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
112 bool isThumbTwo() const {
113 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
115 bool hasV6Ops() const {
116 return STI.getFeatureBits() & ARM::HasV6Ops;
118 bool hasV7Ops() const {
119 return STI.getFeatureBits() & ARM::HasV7Ops;
122 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
123 setAvailableFeatures(FB);
125 bool isMClass() const {
126 return STI.getFeatureBits() & ARM::FeatureMClass;
129 /// @name Auto-generated Match Functions
132 #define GET_ASSEMBLER_HEADER
133 #include "ARMGenAsmMatcher.inc"
137 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
138 OperandMatchResultTy parseCoprocNumOperand(
139 SmallVectorImpl<MCParsedAsmOperand*>&);
140 OperandMatchResultTy parseCoprocRegOperand(
141 SmallVectorImpl<MCParsedAsmOperand*>&);
142 OperandMatchResultTy parseCoprocOptionOperand(
143 SmallVectorImpl<MCParsedAsmOperand*>&);
144 OperandMatchResultTy parseMemBarrierOptOperand(
145 SmallVectorImpl<MCParsedAsmOperand*>&);
146 OperandMatchResultTy parseProcIFlagsOperand(
147 SmallVectorImpl<MCParsedAsmOperand*>&);
148 OperandMatchResultTy parseMSRMaskOperand(
149 SmallVectorImpl<MCParsedAsmOperand*>&);
150 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
151 StringRef Op, int Low, int High);
152 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
153 return parsePKHImm(O, "lsl", 0, 31);
155 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
156 return parsePKHImm(O, "asr", 1, 32);
158 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
160 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
162 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
164 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
165 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
166 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index);
168 // Asm Match Converter Methods
169 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
170 const SmallVectorImpl<MCParsedAsmOperand*> &);
171 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
172 const SmallVectorImpl<MCParsedAsmOperand*> &);
173 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
174 const SmallVectorImpl<MCParsedAsmOperand*> &);
175 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
176 const SmallVectorImpl<MCParsedAsmOperand*> &);
177 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
178 const SmallVectorImpl<MCParsedAsmOperand*> &);
179 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
180 const SmallVectorImpl<MCParsedAsmOperand*> &);
181 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
182 const SmallVectorImpl<MCParsedAsmOperand*> &);
183 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl<MCParsedAsmOperand*> &);
185 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
186 const SmallVectorImpl<MCParsedAsmOperand*> &);
187 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
188 const SmallVectorImpl<MCParsedAsmOperand*> &);
189 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
190 const SmallVectorImpl<MCParsedAsmOperand*> &);
191 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
192 const SmallVectorImpl<MCParsedAsmOperand*> &);
193 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
194 const SmallVectorImpl<MCParsedAsmOperand*> &);
195 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
196 const SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
198 const SmallVectorImpl<MCParsedAsmOperand*> &);
199 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
200 const SmallVectorImpl<MCParsedAsmOperand*> &);
201 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
202 const SmallVectorImpl<MCParsedAsmOperand*> &);
203 bool cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
204 const SmallVectorImpl<MCParsedAsmOperand*> &);
205 bool cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
206 const SmallVectorImpl<MCParsedAsmOperand*> &);
207 bool cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
208 const SmallVectorImpl<MCParsedAsmOperand*> &);
209 bool cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
210 const SmallVectorImpl<MCParsedAsmOperand*> &);
212 bool validateInstruction(MCInst &Inst,
213 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
214 bool processInstruction(MCInst &Inst,
215 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
216 bool shouldOmitCCOutOperand(StringRef Mnemonic,
217 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
220 enum ARMMatchResultTy {
221 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
222 Match_RequiresNotITBlock,
227 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
228 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
229 MCAsmParserExtension::Initialize(_Parser);
231 // Initialize the set of available features.
232 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
234 // Not in an ITBlock to start with.
235 ITState.CurPosition = ~0U;
238 // Implementation of the MCTargetAsmParser interface:
239 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
240 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
241 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
242 bool ParseDirective(AsmToken DirectiveID);
244 unsigned checkTargetMatchPredicate(MCInst &Inst);
246 bool MatchAndEmitInstruction(SMLoc IDLoc,
247 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
250 } // end anonymous namespace
254 /// ARMOperand - Instances of this class represent a parsed ARM machine
256 class ARMOperand : public MCParsedAsmOperand {
277 k_VectorListAllLanes,
283 k_BitfieldDescriptor,
287 SMLoc StartLoc, EndLoc;
288 SmallVector<unsigned, 8> Registers;
292 ARMCC::CondCodes Val;
312 ARM_PROC::IFlags Val;
328 // A vector register list is a sequential list of 1 to 4 registers.
344 unsigned Val; // encoded 8-bit representation
347 /// Combined record for all forms of ARM address expressions.
350 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
352 const MCConstantExpr *OffsetImm; // Offset immediate value
353 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
354 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
355 unsigned ShiftImm; // shift for OffsetReg.
356 unsigned Alignment; // 0 = no alignment specified
357 // n = alignment in bytes (8, 16, or 32)
358 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
364 ARM_AM::ShiftOpc ShiftTy;
373 ARM_AM::ShiftOpc ShiftTy;
379 ARM_AM::ShiftOpc ShiftTy;
392 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
394 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
396 StartLoc = o.StartLoc;
413 case k_DPRRegisterList:
414 case k_SPRRegisterList:
415 Registers = o.Registers;
418 case k_VectorListAllLanes:
419 case k_VectorListIndexed:
420 VectorList = o.VectorList;
427 CoprocOption = o.CoprocOption;
435 case k_MemBarrierOpt:
441 case k_PostIndexRegister:
442 PostIdxReg = o.PostIdxReg;
450 case k_ShifterImmediate:
451 ShifterImm = o.ShifterImm;
453 case k_ShiftedRegister:
454 RegShiftedReg = o.RegShiftedReg;
456 case k_ShiftedImmediate:
457 RegShiftedImm = o.RegShiftedImm;
459 case k_RotateImmediate:
462 case k_BitfieldDescriptor:
463 Bitfield = o.Bitfield;
466 VectorIndex = o.VectorIndex;
471 /// getStartLoc - Get the location of the first token of this operand.
472 SMLoc getStartLoc() const { return StartLoc; }
473 /// getEndLoc - Get the location of the last token of this operand.
474 SMLoc getEndLoc() const { return EndLoc; }
476 ARMCC::CondCodes getCondCode() const {
477 assert(Kind == k_CondCode && "Invalid access!");
481 unsigned getCoproc() const {
482 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
486 StringRef getToken() const {
487 assert(Kind == k_Token && "Invalid access!");
488 return StringRef(Tok.Data, Tok.Length);
491 unsigned getReg() const {
492 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
496 const SmallVectorImpl<unsigned> &getRegList() const {
497 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
498 Kind == k_SPRRegisterList) && "Invalid access!");
502 const MCExpr *getImm() const {
503 assert(Kind == k_Immediate && "Invalid access!");
507 unsigned getFPImm() const {
508 assert(Kind == k_FPImmediate && "Invalid access!");
512 unsigned getVectorIndex() const {
513 assert(Kind == k_VectorIndex && "Invalid access!");
514 return VectorIndex.Val;
517 ARM_MB::MemBOpt getMemBarrierOpt() const {
518 assert(Kind == k_MemBarrierOpt && "Invalid access!");
522 ARM_PROC::IFlags getProcIFlags() const {
523 assert(Kind == k_ProcIFlags && "Invalid access!");
527 unsigned getMSRMask() const {
528 assert(Kind == k_MSRMask && "Invalid access!");
532 bool isCoprocNum() const { return Kind == k_CoprocNum; }
533 bool isCoprocReg() const { return Kind == k_CoprocReg; }
534 bool isCoprocOption() const { return Kind == k_CoprocOption; }
535 bool isCondCode() const { return Kind == k_CondCode; }
536 bool isCCOut() const { return Kind == k_CCOut; }
537 bool isITMask() const { return Kind == k_ITCondMask; }
538 bool isITCondCode() const { return Kind == k_CondCode; }
539 bool isImm() const { return Kind == k_Immediate; }
540 bool isFPImm() const { return Kind == k_FPImmediate; }
541 bool isImm8s4() const {
542 if (Kind != k_Immediate)
544 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
545 if (!CE) return false;
546 int64_t Value = CE->getValue();
547 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
549 bool isImm0_1020s4() const {
550 if (Kind != k_Immediate)
552 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
553 if (!CE) return false;
554 int64_t Value = CE->getValue();
555 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
557 bool isImm0_508s4() const {
558 if (Kind != k_Immediate)
560 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
561 if (!CE) return false;
562 int64_t Value = CE->getValue();
563 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
565 bool isImm0_255() const {
566 if (Kind != k_Immediate)
568 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
569 if (!CE) return false;
570 int64_t Value = CE->getValue();
571 return Value >= 0 && Value < 256;
573 bool isImm0_7() const {
574 if (Kind != k_Immediate)
576 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
577 if (!CE) return false;
578 int64_t Value = CE->getValue();
579 return Value >= 0 && Value < 8;
581 bool isImm0_15() const {
582 if (Kind != k_Immediate)
584 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
585 if (!CE) return false;
586 int64_t Value = CE->getValue();
587 return Value >= 0 && Value < 16;
589 bool isImm0_31() const {
590 if (Kind != k_Immediate)
592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
593 if (!CE) return false;
594 int64_t Value = CE->getValue();
595 return Value >= 0 && Value < 32;
597 bool isImm1_16() const {
598 if (Kind != k_Immediate)
600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
601 if (!CE) return false;
602 int64_t Value = CE->getValue();
603 return Value > 0 && Value < 17;
605 bool isImm1_32() const {
606 if (Kind != k_Immediate)
608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
609 if (!CE) return false;
610 int64_t Value = CE->getValue();
611 return Value > 0 && Value < 33;
613 bool isImm0_32() const {
614 if (Kind != k_Immediate)
616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
617 if (!CE) return false;
618 int64_t Value = CE->getValue();
619 return Value >= 0 && Value < 33;
621 bool isImm0_65535() const {
622 if (Kind != k_Immediate)
624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
625 if (!CE) return false;
626 int64_t Value = CE->getValue();
627 return Value >= 0 && Value < 65536;
629 bool isImm0_65535Expr() const {
630 if (Kind != k_Immediate)
632 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
633 // If it's not a constant expression, it'll generate a fixup and be
635 if (!CE) return true;
636 int64_t Value = CE->getValue();
637 return Value >= 0 && Value < 65536;
639 bool isImm24bit() const {
640 if (Kind != k_Immediate)
642 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
643 if (!CE) return false;
644 int64_t Value = CE->getValue();
645 return Value >= 0 && Value <= 0xffffff;
647 bool isImmThumbSR() const {
648 if (Kind != k_Immediate)
650 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
651 if (!CE) return false;
652 int64_t Value = CE->getValue();
653 return Value > 0 && Value < 33;
655 bool isPKHLSLImm() const {
656 if (Kind != k_Immediate)
658 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
659 if (!CE) return false;
660 int64_t Value = CE->getValue();
661 return Value >= 0 && Value < 32;
663 bool isPKHASRImm() const {
664 if (Kind != k_Immediate)
666 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
667 if (!CE) return false;
668 int64_t Value = CE->getValue();
669 return Value > 0 && Value <= 32;
671 bool isARMSOImm() const {
672 if (Kind != k_Immediate)
674 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
675 if (!CE) return false;
676 int64_t Value = CE->getValue();
677 return ARM_AM::getSOImmVal(Value) != -1;
679 bool isARMSOImmNot() const {
680 if (Kind != k_Immediate)
682 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683 if (!CE) return false;
684 int64_t Value = CE->getValue();
685 return ARM_AM::getSOImmVal(~Value) != -1;
687 bool isT2SOImm() const {
688 if (Kind != k_Immediate)
690 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
691 if (!CE) return false;
692 int64_t Value = CE->getValue();
693 return ARM_AM::getT2SOImmVal(Value) != -1;
695 bool isT2SOImmNot() const {
696 if (Kind != k_Immediate)
698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
699 if (!CE) return false;
700 int64_t Value = CE->getValue();
701 return ARM_AM::getT2SOImmVal(~Value) != -1;
703 bool isSetEndImm() const {
704 if (Kind != k_Immediate)
706 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
707 if (!CE) return false;
708 int64_t Value = CE->getValue();
709 return Value == 1 || Value == 0;
711 bool isReg() const { return Kind == k_Register; }
712 bool isRegList() const { return Kind == k_RegisterList; }
713 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
714 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
715 bool isToken() const { return Kind == k_Token; }
716 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
717 bool isMemory() const { return Kind == k_Memory; }
718 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
719 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
720 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
721 bool isRotImm() const { return Kind == k_RotateImmediate; }
722 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
723 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
724 bool isPostIdxReg() const {
725 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
727 bool isMemNoOffset(bool alignOK = false) const {
730 // No offset of any kind.
731 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
732 (alignOK || Memory.Alignment == 0);
734 bool isAlignedMemory() const {
735 return isMemNoOffset(true);
737 bool isAddrMode2() const {
738 if (!isMemory() || Memory.Alignment != 0) return false;
739 // Check for register offset.
740 if (Memory.OffsetRegNum) return true;
741 // Immediate offset in range [-4095, 4095].
742 if (!Memory.OffsetImm) return true;
743 int64_t Val = Memory.OffsetImm->getValue();
744 return Val > -4096 && Val < 4096;
746 bool isAM2OffsetImm() const {
747 if (Kind != k_Immediate)
749 // Immediate offset in range [-4095, 4095].
750 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
751 if (!CE) return false;
752 int64_t Val = CE->getValue();
753 return Val > -4096 && Val < 4096;
755 bool isAddrMode3() const {
756 if (!isMemory() || Memory.Alignment != 0) return false;
757 // No shifts are legal for AM3.
758 if (Memory.ShiftType != ARM_AM::no_shift) return false;
759 // Check for register offset.
760 if (Memory.OffsetRegNum) return true;
761 // Immediate offset in range [-255, 255].
762 if (!Memory.OffsetImm) return true;
763 int64_t Val = Memory.OffsetImm->getValue();
764 return Val > -256 && Val < 256;
766 bool isAM3Offset() const {
767 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
769 if (Kind == k_PostIndexRegister)
770 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
771 // Immediate offset in range [-255, 255].
772 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
773 if (!CE) return false;
774 int64_t Val = CE->getValue();
775 // Special case, #-0 is INT32_MIN.
776 return (Val > -256 && Val < 256) || Val == INT32_MIN;
778 bool isAddrMode5() const {
779 // If we have an immediate that's not a constant, treat it as a label
780 // reference needing a fixup. If it is a constant, it's something else
782 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
784 if (!isMemory() || Memory.Alignment != 0) return false;
785 // Check for register offset.
786 if (Memory.OffsetRegNum) return false;
787 // Immediate offset in range [-1020, 1020] and a multiple of 4.
788 if (!Memory.OffsetImm) return true;
789 int64_t Val = Memory.OffsetImm->getValue();
790 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
793 bool isMemTBB() const {
794 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
795 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
799 bool isMemTBH() const {
800 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
801 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
802 Memory.Alignment != 0 )
806 bool isMemRegOffset() const {
807 if (!isMemory() || !Memory.OffsetRegNum || Memory.Alignment != 0)
811 bool isT2MemRegOffset() const {
812 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
813 Memory.Alignment != 0)
815 // Only lsl #{0, 1, 2, 3} allowed.
816 if (Memory.ShiftType == ARM_AM::no_shift)
818 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
822 bool isMemThumbRR() const {
823 // Thumb reg+reg addressing is simple. Just two registers, a base and
824 // an offset. No shifts, negations or any other complicating factors.
825 if (!isMemory() || !Memory.OffsetRegNum || Memory.isNegative ||
826 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
828 return isARMLowRegister(Memory.BaseRegNum) &&
829 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
831 bool isMemThumbRIs4() const {
832 if (!isMemory() || Memory.OffsetRegNum != 0 ||
833 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
835 // Immediate offset, multiple of 4 in range [0, 124].
836 if (!Memory.OffsetImm) return true;
837 int64_t Val = Memory.OffsetImm->getValue();
838 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
840 bool isMemThumbRIs2() const {
841 if (!isMemory() || Memory.OffsetRegNum != 0 ||
842 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
844 // Immediate offset, multiple of 4 in range [0, 62].
845 if (!Memory.OffsetImm) return true;
846 int64_t Val = Memory.OffsetImm->getValue();
847 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
849 bool isMemThumbRIs1() const {
850 if (!isMemory() || Memory.OffsetRegNum != 0 ||
851 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
853 // Immediate offset in range [0, 31].
854 if (!Memory.OffsetImm) return true;
855 int64_t Val = Memory.OffsetImm->getValue();
856 return Val >= 0 && Val <= 31;
858 bool isMemThumbSPI() const {
859 if (!isMemory() || Memory.OffsetRegNum != 0 ||
860 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
862 // Immediate offset, multiple of 4 in range [0, 1020].
863 if (!Memory.OffsetImm) return true;
864 int64_t Val = Memory.OffsetImm->getValue();
865 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
867 bool isMemImm8s4Offset() const {
868 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
870 // Immediate offset a multiple of 4 in range [-1020, 1020].
871 if (!Memory.OffsetImm) return true;
872 int64_t Val = Memory.OffsetImm->getValue();
873 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
875 bool isMemImm0_1020s4Offset() const {
876 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
878 // Immediate offset a multiple of 4 in range [0, 1020].
879 if (!Memory.OffsetImm) return true;
880 int64_t Val = Memory.OffsetImm->getValue();
881 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
883 bool isMemImm8Offset() const {
884 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
886 // Immediate offset in range [-255, 255].
887 if (!Memory.OffsetImm) return true;
888 int64_t Val = Memory.OffsetImm->getValue();
889 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
891 bool isMemPosImm8Offset() const {
892 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
894 // Immediate offset in range [0, 255].
895 if (!Memory.OffsetImm) return true;
896 int64_t Val = Memory.OffsetImm->getValue();
897 return Val >= 0 && Val < 256;
899 bool isMemNegImm8Offset() const {
900 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
902 // Immediate offset in range [-255, -1].
903 if (!Memory.OffsetImm) return true;
904 int64_t Val = Memory.OffsetImm->getValue();
905 return Val > -256 && Val < 0;
907 bool isMemUImm12Offset() const {
908 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
910 // Immediate offset in range [0, 4095].
911 if (!Memory.OffsetImm) return true;
912 int64_t Val = Memory.OffsetImm->getValue();
913 return (Val >= 0 && Val < 4096);
915 bool isMemImm12Offset() const {
916 // If we have an immediate that's not a constant, treat it as a label
917 // reference needing a fixup. If it is a constant, it's something else
919 if (Kind == k_Immediate && !isa<MCConstantExpr>(getImm()))
922 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
924 // Immediate offset in range [-4095, 4095].
925 if (!Memory.OffsetImm) return true;
926 int64_t Val = Memory.OffsetImm->getValue();
927 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
929 bool isPostIdxImm8() const {
930 if (Kind != k_Immediate)
932 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933 if (!CE) return false;
934 int64_t Val = CE->getValue();
935 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
937 bool isPostIdxImm8s4() const {
938 if (Kind != k_Immediate)
940 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941 if (!CE) return false;
942 int64_t Val = CE->getValue();
943 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
947 bool isMSRMask() const { return Kind == k_MSRMask; }
948 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
951 bool isVecListOneD() const {
952 if (Kind != k_VectorList) return false;
953 return VectorList.Count == 1;
956 bool isVecListTwoD() const {
957 if (Kind != k_VectorList) return false;
958 return VectorList.Count == 2;
961 bool isVecListThreeD() const {
962 if (Kind != k_VectorList) return false;
963 return VectorList.Count == 3;
966 bool isVecListFourD() const {
967 if (Kind != k_VectorList) return false;
968 return VectorList.Count == 4;
971 bool isVecListTwoQ() const {
972 if (Kind != k_VectorList) return false;
973 //FIXME: We haven't taught the parser to handle by-two register lists
974 // yet, so don't pretend to know one.
975 return VectorList.Count == 2 && false;
978 bool isVecListOneDAllLanes() const {
979 if (Kind != k_VectorListAllLanes) return false;
980 return VectorList.Count == 1;
983 bool isVecListTwoDAllLanes() const {
984 if (Kind != k_VectorListAllLanes) return false;
985 return VectorList.Count == 2;
988 bool isVecListOneDByteIndexed() const {
989 if (Kind != k_VectorListIndexed) return false;
990 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
993 bool isVectorIndex8() const {
994 if (Kind != k_VectorIndex) return false;
995 return VectorIndex.Val < 8;
997 bool isVectorIndex16() const {
998 if (Kind != k_VectorIndex) return false;
999 return VectorIndex.Val < 4;
1001 bool isVectorIndex32() const {
1002 if (Kind != k_VectorIndex) return false;
1003 return VectorIndex.Val < 2;
1006 bool isNEONi8splat() const {
1007 if (Kind != k_Immediate)
1009 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1010 // Must be a constant.
1011 if (!CE) return false;
1012 int64_t Value = CE->getValue();
1013 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1015 return Value >= 0 && Value < 256;
1018 bool isNEONi16splat() const {
1019 if (Kind != k_Immediate)
1021 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1022 // Must be a constant.
1023 if (!CE) return false;
1024 int64_t Value = CE->getValue();
1025 // i16 value in the range [0,255] or [0x0100, 0xff00]
1026 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1029 bool isNEONi32splat() const {
1030 if (Kind != k_Immediate)
1032 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1033 // Must be a constant.
1034 if (!CE) return false;
1035 int64_t Value = CE->getValue();
1036 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1037 return (Value >= 0 && Value < 256) ||
1038 (Value >= 0x0100 && Value <= 0xff00) ||
1039 (Value >= 0x010000 && Value <= 0xff0000) ||
1040 (Value >= 0x01000000 && Value <= 0xff000000);
1043 bool isNEONi32vmov() const {
1044 if (Kind != k_Immediate)
1046 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1047 // Must be a constant.
1048 if (!CE) return false;
1049 int64_t Value = CE->getValue();
1050 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1051 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1052 return (Value >= 0 && Value < 256) ||
1053 (Value >= 0x0100 && Value <= 0xff00) ||
1054 (Value >= 0x010000 && Value <= 0xff0000) ||
1055 (Value >= 0x01000000 && Value <= 0xff000000) ||
1056 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1057 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1060 bool isNEONi64splat() const {
1061 if (Kind != k_Immediate)
1063 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1064 // Must be a constant.
1065 if (!CE) return false;
1066 uint64_t Value = CE->getValue();
1067 // i64 value with each byte being either 0 or 0xff.
1068 for (unsigned i = 0; i < 8; ++i)
1069 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1073 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1074 // Add as immediates when possible. Null MCExpr = 0.
1076 Inst.addOperand(MCOperand::CreateImm(0));
1077 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1078 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1080 Inst.addOperand(MCOperand::CreateExpr(Expr));
1083 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1084 assert(N == 2 && "Invalid number of operands!");
1085 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1086 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1087 Inst.addOperand(MCOperand::CreateReg(RegNum));
1090 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1091 assert(N == 1 && "Invalid number of operands!");
1092 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1095 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1096 assert(N == 1 && "Invalid number of operands!");
1097 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1100 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1101 assert(N == 1 && "Invalid number of operands!");
1102 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1105 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1106 assert(N == 1 && "Invalid number of operands!");
1107 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1110 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1111 assert(N == 1 && "Invalid number of operands!");
1112 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1115 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1116 assert(N == 1 && "Invalid number of operands!");
1117 Inst.addOperand(MCOperand::CreateReg(getReg()));
1120 void addRegOperands(MCInst &Inst, unsigned N) const {
1121 assert(N == 1 && "Invalid number of operands!");
1122 Inst.addOperand(MCOperand::CreateReg(getReg()));
1125 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1126 assert(N == 3 && "Invalid number of operands!");
1127 assert(isRegShiftedReg() &&
1128 "addRegShiftedRegOperands() on non RegShiftedReg!");
1129 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1130 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1131 Inst.addOperand(MCOperand::CreateImm(
1132 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1135 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1136 assert(N == 2 && "Invalid number of operands!");
1137 assert(isRegShiftedImm() &&
1138 "addRegShiftedImmOperands() on non RegShiftedImm!");
1139 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1140 Inst.addOperand(MCOperand::CreateImm(
1141 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
1144 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1145 assert(N == 1 && "Invalid number of operands!");
1146 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1150 void addRegListOperands(MCInst &Inst, unsigned N) const {
1151 assert(N == 1 && "Invalid number of operands!");
1152 const SmallVectorImpl<unsigned> &RegList = getRegList();
1153 for (SmallVectorImpl<unsigned>::const_iterator
1154 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1155 Inst.addOperand(MCOperand::CreateReg(*I));
1158 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1159 addRegListOperands(Inst, N);
1162 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1163 addRegListOperands(Inst, N);
1166 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1167 assert(N == 1 && "Invalid number of operands!");
1168 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1169 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1172 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1173 assert(N == 1 && "Invalid number of operands!");
1174 // Munge the lsb/width into a bitfield mask.
1175 unsigned lsb = Bitfield.LSB;
1176 unsigned width = Bitfield.Width;
1177 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1178 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1179 (32 - (lsb + width)));
1180 Inst.addOperand(MCOperand::CreateImm(Mask));
1183 void addImmOperands(MCInst &Inst, unsigned N) const {
1184 assert(N == 1 && "Invalid number of operands!");
1185 addExpr(Inst, getImm());
1188 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1189 assert(N == 1 && "Invalid number of operands!");
1190 Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1193 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1194 assert(N == 1 && "Invalid number of operands!");
1195 // FIXME: We really want to scale the value here, but the LDRD/STRD
1196 // instruction don't encode operands that way yet.
1197 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1198 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1201 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1202 assert(N == 1 && "Invalid number of operands!");
1203 // The immediate is scaled by four in the encoding and is stored
1204 // in the MCInst as such. Lop off the low two bits here.
1205 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1206 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1209 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1210 assert(N == 1 && "Invalid number of operands!");
1211 // The immediate is scaled by four in the encoding and is stored
1212 // in the MCInst as such. Lop off the low two bits here.
1213 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1214 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1217 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1218 assert(N == 1 && "Invalid number of operands!");
1219 // The constant encodes as the immediate-1, and we store in the instruction
1220 // the bits as encoded, so subtract off one here.
1221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1222 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1225 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1226 assert(N == 1 && "Invalid number of operands!");
1227 // The constant encodes as the immediate-1, and we store in the instruction
1228 // the bits as encoded, so subtract off one here.
1229 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1230 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1233 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1234 assert(N == 1 && "Invalid number of operands!");
1235 // The constant encodes as the immediate, except for 32, which encodes as
1237 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1238 unsigned Imm = CE->getValue();
1239 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1242 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1243 assert(N == 1 && "Invalid number of operands!");
1244 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1245 // the instruction as well.
1246 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1247 int Val = CE->getValue();
1248 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1251 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1252 assert(N == 1 && "Invalid number of operands!");
1253 // The operand is actually a t2_so_imm, but we have its bitwise
1254 // negation in the assembly source, so twiddle it here.
1255 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1256 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1259 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1260 assert(N == 1 && "Invalid number of operands!");
1261 // The operand is actually a so_imm, but we have its bitwise
1262 // negation in the assembly source, so twiddle it here.
1263 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1264 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1267 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1268 assert(N == 1 && "Invalid number of operands!");
1269 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1272 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1273 assert(N == 1 && "Invalid number of operands!");
1274 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1277 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1278 assert(N == 2 && "Invalid number of operands!");
1279 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1280 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1283 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1284 assert(N == 3 && "Invalid number of operands!");
1285 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1286 if (!Memory.OffsetRegNum) {
1287 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1288 // Special case for #-0
1289 if (Val == INT32_MIN) Val = 0;
1290 if (Val < 0) Val = -Val;
1291 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1293 // For register offset, we encode the shift type and negation flag
1295 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1296 Memory.ShiftImm, Memory.ShiftType);
1298 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1299 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1300 Inst.addOperand(MCOperand::CreateImm(Val));
1303 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1304 assert(N == 2 && "Invalid number of operands!");
1305 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1306 assert(CE && "non-constant AM2OffsetImm operand!");
1307 int32_t Val = CE->getValue();
1308 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1309 // Special case for #-0
1310 if (Val == INT32_MIN) Val = 0;
1311 if (Val < 0) Val = -Val;
1312 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1313 Inst.addOperand(MCOperand::CreateReg(0));
1314 Inst.addOperand(MCOperand::CreateImm(Val));
1317 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1318 assert(N == 3 && "Invalid number of operands!");
1319 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1320 if (!Memory.OffsetRegNum) {
1321 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1322 // Special case for #-0
1323 if (Val == INT32_MIN) Val = 0;
1324 if (Val < 0) Val = -Val;
1325 Val = ARM_AM::getAM3Opc(AddSub, Val);
1327 // For register offset, we encode the shift type and negation flag
1329 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1331 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1332 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1333 Inst.addOperand(MCOperand::CreateImm(Val));
1336 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1337 assert(N == 2 && "Invalid number of operands!");
1338 if (Kind == k_PostIndexRegister) {
1340 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1341 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1342 Inst.addOperand(MCOperand::CreateImm(Val));
1347 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1348 int32_t Val = CE->getValue();
1349 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1350 // Special case for #-0
1351 if (Val == INT32_MIN) Val = 0;
1352 if (Val < 0) Val = -Val;
1353 Val = ARM_AM::getAM3Opc(AddSub, Val);
1354 Inst.addOperand(MCOperand::CreateReg(0));
1355 Inst.addOperand(MCOperand::CreateImm(Val));
1358 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1359 assert(N == 2 && "Invalid number of operands!");
1360 // If we have an immediate that's not a constant, treat it as a label
1361 // reference needing a fixup. If it is a constant, it's something else
1362 // and we reject it.
1364 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1365 Inst.addOperand(MCOperand::CreateImm(0));
1369 // The lower two bits are always zero and as such are not encoded.
1370 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1371 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1372 // Special case for #-0
1373 if (Val == INT32_MIN) Val = 0;
1374 if (Val < 0) Val = -Val;
1375 Val = ARM_AM::getAM5Opc(AddSub, Val);
1376 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1377 Inst.addOperand(MCOperand::CreateImm(Val));
1380 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1381 assert(N == 2 && "Invalid number of operands!");
1382 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1383 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1384 Inst.addOperand(MCOperand::CreateImm(Val));
1387 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1388 assert(N == 2 && "Invalid number of operands!");
1389 // The lower two bits are always zero and as such are not encoded.
1390 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1391 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1392 Inst.addOperand(MCOperand::CreateImm(Val));
1395 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1396 assert(N == 2 && "Invalid number of operands!");
1397 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1398 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1399 Inst.addOperand(MCOperand::CreateImm(Val));
1402 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1403 addMemImm8OffsetOperands(Inst, N);
1406 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1407 addMemImm8OffsetOperands(Inst, N);
1410 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1411 assert(N == 2 && "Invalid number of operands!");
1412 // If this is an immediate, it's a label reference.
1413 if (Kind == k_Immediate) {
1414 addExpr(Inst, getImm());
1415 Inst.addOperand(MCOperand::CreateImm(0));
1419 // Otherwise, it's a normal memory reg+offset.
1420 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1421 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1422 Inst.addOperand(MCOperand::CreateImm(Val));
1425 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1426 assert(N == 2 && "Invalid number of operands!");
1427 // If this is an immediate, it's a label reference.
1428 if (Kind == k_Immediate) {
1429 addExpr(Inst, getImm());
1430 Inst.addOperand(MCOperand::CreateImm(0));
1434 // Otherwise, it's a normal memory reg+offset.
1435 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1436 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1437 Inst.addOperand(MCOperand::CreateImm(Val));
1440 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1441 assert(N == 2 && "Invalid number of operands!");
1442 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1443 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1446 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1447 assert(N == 2 && "Invalid number of operands!");
1448 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1449 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1452 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1453 assert(N == 3 && "Invalid number of operands!");
1455 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1456 Memory.ShiftImm, Memory.ShiftType);
1457 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1458 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1459 Inst.addOperand(MCOperand::CreateImm(Val));
1462 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1463 assert(N == 3 && "Invalid number of operands!");
1464 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1465 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1466 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1469 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1470 assert(N == 2 && "Invalid number of operands!");
1471 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1472 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1475 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1476 assert(N == 2 && "Invalid number of operands!");
1477 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1478 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1479 Inst.addOperand(MCOperand::CreateImm(Val));
1482 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1483 assert(N == 2 && "Invalid number of operands!");
1484 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1485 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1486 Inst.addOperand(MCOperand::CreateImm(Val));
1489 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1490 assert(N == 2 && "Invalid number of operands!");
1491 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1492 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1493 Inst.addOperand(MCOperand::CreateImm(Val));
1496 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1497 assert(N == 2 && "Invalid number of operands!");
1498 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1499 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1500 Inst.addOperand(MCOperand::CreateImm(Val));
1503 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1504 assert(N == 1 && "Invalid number of operands!");
1505 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1506 assert(CE && "non-constant post-idx-imm8 operand!");
1507 int Imm = CE->getValue();
1508 bool isAdd = Imm >= 0;
1509 if (Imm == INT32_MIN) Imm = 0;
1510 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1511 Inst.addOperand(MCOperand::CreateImm(Imm));
1514 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1515 assert(N == 1 && "Invalid number of operands!");
1516 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1517 assert(CE && "non-constant post-idx-imm8s4 operand!");
1518 int Imm = CE->getValue();
1519 bool isAdd = Imm >= 0;
1520 if (Imm == INT32_MIN) Imm = 0;
1521 // Immediate is scaled by 4.
1522 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1523 Inst.addOperand(MCOperand::CreateImm(Imm));
1526 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1527 assert(N == 2 && "Invalid number of operands!");
1528 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1529 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1532 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1533 assert(N == 2 && "Invalid number of operands!");
1534 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1535 // The sign, shift type, and shift amount are encoded in a single operand
1536 // using the AM2 encoding helpers.
1537 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1538 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1539 PostIdxReg.ShiftTy);
1540 Inst.addOperand(MCOperand::CreateImm(Imm));
1543 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1544 assert(N == 1 && "Invalid number of operands!");
1545 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1548 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1549 assert(N == 1 && "Invalid number of operands!");
1550 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1553 void addVecListOperands(MCInst &Inst, unsigned N) const {
1554 assert(N == 1 && "Invalid number of operands!");
1555 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1558 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1559 assert(N == 2 && "Invalid number of operands!");
1560 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1561 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1564 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1565 assert(N == 1 && "Invalid number of operands!");
1566 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1569 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1570 assert(N == 1 && "Invalid number of operands!");
1571 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1574 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1575 assert(N == 1 && "Invalid number of operands!");
1576 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1579 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1580 assert(N == 1 && "Invalid number of operands!");
1581 // The immediate encodes the type of constant as well as the value.
1582 // Mask in that this is an i8 splat.
1583 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1584 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1587 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
1588 assert(N == 1 && "Invalid number of operands!");
1589 // The immediate encodes the type of constant as well as the value.
1590 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1591 unsigned Value = CE->getValue();
1593 Value = (Value >> 8) | 0xa00;
1596 Inst.addOperand(MCOperand::CreateImm(Value));
1599 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
1600 assert(N == 1 && "Invalid number of operands!");
1601 // The immediate encodes the type of constant as well as the value.
1602 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1603 unsigned Value = CE->getValue();
1604 if (Value >= 256 && Value <= 0xff00)
1605 Value = (Value >> 8) | 0x200;
1606 else if (Value > 0xffff && Value <= 0xff0000)
1607 Value = (Value >> 16) | 0x400;
1608 else if (Value > 0xffffff)
1609 Value = (Value >> 24) | 0x600;
1610 Inst.addOperand(MCOperand::CreateImm(Value));
1613 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
1614 assert(N == 1 && "Invalid number of operands!");
1615 // The immediate encodes the type of constant as well as the value.
1616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1617 unsigned Value = CE->getValue();
1618 if (Value >= 256 && Value <= 0xffff)
1619 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
1620 else if (Value > 0xffff && Value <= 0xffffff)
1621 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
1622 else if (Value > 0xffffff)
1623 Value = (Value >> 24) | 0x600;
1624 Inst.addOperand(MCOperand::CreateImm(Value));
1627 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
1628 assert(N == 1 && "Invalid number of operands!");
1629 // The immediate encodes the type of constant as well as the value.
1630 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1631 uint64_t Value = CE->getValue();
1633 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
1634 Imm |= (Value & 1) << i;
1636 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
1639 virtual void print(raw_ostream &OS) const;
1641 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1642 ARMOperand *Op = new ARMOperand(k_ITCondMask);
1643 Op->ITMask.Mask = Mask;
1649 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1650 ARMOperand *Op = new ARMOperand(k_CondCode);
1657 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1658 ARMOperand *Op = new ARMOperand(k_CoprocNum);
1659 Op->Cop.Val = CopVal;
1665 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1666 ARMOperand *Op = new ARMOperand(k_CoprocReg);
1667 Op->Cop.Val = CopVal;
1673 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
1674 ARMOperand *Op = new ARMOperand(k_CoprocOption);
1681 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1682 ARMOperand *Op = new ARMOperand(k_CCOut);
1683 Op->Reg.RegNum = RegNum;
1689 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1690 ARMOperand *Op = new ARMOperand(k_Token);
1691 Op->Tok.Data = Str.data();
1692 Op->Tok.Length = Str.size();
1698 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1699 ARMOperand *Op = new ARMOperand(k_Register);
1700 Op->Reg.RegNum = RegNum;
1706 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1711 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
1712 Op->RegShiftedReg.ShiftTy = ShTy;
1713 Op->RegShiftedReg.SrcReg = SrcReg;
1714 Op->RegShiftedReg.ShiftReg = ShiftReg;
1715 Op->RegShiftedReg.ShiftImm = ShiftImm;
1721 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1725 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
1726 Op->RegShiftedImm.ShiftTy = ShTy;
1727 Op->RegShiftedImm.SrcReg = SrcReg;
1728 Op->RegShiftedImm.ShiftImm = ShiftImm;
1734 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1736 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
1737 Op->ShifterImm.isASR = isASR;
1738 Op->ShifterImm.Imm = Imm;
1744 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1745 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
1746 Op->RotImm.Imm = Imm;
1752 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1754 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
1755 Op->Bitfield.LSB = LSB;
1756 Op->Bitfield.Width = Width;
1763 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1764 SMLoc StartLoc, SMLoc EndLoc) {
1765 KindTy Kind = k_RegisterList;
1767 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1768 Kind = k_DPRRegisterList;
1769 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1770 contains(Regs.front().first))
1771 Kind = k_SPRRegisterList;
1773 ARMOperand *Op = new ARMOperand(Kind);
1774 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1775 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1776 Op->Registers.push_back(I->first);
1777 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1778 Op->StartLoc = StartLoc;
1779 Op->EndLoc = EndLoc;
1783 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
1785 ARMOperand *Op = new ARMOperand(k_VectorList);
1786 Op->VectorList.RegNum = RegNum;
1787 Op->VectorList.Count = Count;
1793 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
1795 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
1796 Op->VectorList.RegNum = RegNum;
1797 Op->VectorList.Count = Count;
1803 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
1804 unsigned Index, SMLoc S, SMLoc E) {
1805 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
1806 Op->VectorList.RegNum = RegNum;
1807 Op->VectorList.Count = Count;
1808 Op->VectorList.LaneIndex = Index;
1814 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
1816 ARMOperand *Op = new ARMOperand(k_VectorIndex);
1817 Op->VectorIndex.Val = Idx;
1823 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1824 ARMOperand *Op = new ARMOperand(k_Immediate);
1831 static ARMOperand *CreateFPImm(unsigned Val, SMLoc S, MCContext &Ctx) {
1832 ARMOperand *Op = new ARMOperand(k_FPImmediate);
1833 Op->FPImm.Val = Val;
1839 static ARMOperand *CreateMem(unsigned BaseRegNum,
1840 const MCConstantExpr *OffsetImm,
1841 unsigned OffsetRegNum,
1842 ARM_AM::ShiftOpc ShiftType,
1847 ARMOperand *Op = new ARMOperand(k_Memory);
1848 Op->Memory.BaseRegNum = BaseRegNum;
1849 Op->Memory.OffsetImm = OffsetImm;
1850 Op->Memory.OffsetRegNum = OffsetRegNum;
1851 Op->Memory.ShiftType = ShiftType;
1852 Op->Memory.ShiftImm = ShiftImm;
1853 Op->Memory.Alignment = Alignment;
1854 Op->Memory.isNegative = isNegative;
1860 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1861 ARM_AM::ShiftOpc ShiftTy,
1864 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
1865 Op->PostIdxReg.RegNum = RegNum;
1866 Op->PostIdxReg.isAdd = isAdd;
1867 Op->PostIdxReg.ShiftTy = ShiftTy;
1868 Op->PostIdxReg.ShiftImm = ShiftImm;
1874 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1875 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
1876 Op->MBOpt.Val = Opt;
1882 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1883 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
1884 Op->IFlags.Val = IFlags;
1890 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1891 ARMOperand *Op = new ARMOperand(k_MSRMask);
1892 Op->MMask.Val = MMask;
1899 } // end anonymous namespace.
1901 void ARMOperand::print(raw_ostream &OS) const {
1904 OS << "<fpimm " << getFPImm() << "(" << ARM_AM::getFPImmFloat(getFPImm())
1908 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1911 OS << "<ccout " << getReg() << ">";
1913 case k_ITCondMask: {
1914 static const char *MaskStr[] = {
1915 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
1916 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
1918 assert((ITMask.Mask & 0xf) == ITMask.Mask);
1919 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1923 OS << "<coprocessor number: " << getCoproc() << ">";
1926 OS << "<coprocessor register: " << getCoproc() << ">";
1928 case k_CoprocOption:
1929 OS << "<coprocessor option: " << CoprocOption.Val << ">";
1932 OS << "<mask: " << getMSRMask() << ">";
1935 getImm()->print(OS);
1937 case k_MemBarrierOpt:
1938 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1942 << " base:" << Memory.BaseRegNum;
1945 case k_PostIndexRegister:
1946 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1947 << PostIdxReg.RegNum;
1948 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1949 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1950 << PostIdxReg.ShiftImm;
1953 case k_ProcIFlags: {
1954 OS << "<ARM_PROC::";
1955 unsigned IFlags = getProcIFlags();
1956 for (int i=2; i >= 0; --i)
1957 if (IFlags & (1 << i))
1958 OS << ARM_PROC::IFlagsToString(1 << i);
1963 OS << "<register " << getReg() << ">";
1965 case k_ShifterImmediate:
1966 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1967 << " #" << ShifterImm.Imm << ">";
1969 case k_ShiftedRegister:
1970 OS << "<so_reg_reg "
1971 << RegShiftedReg.SrcReg << " "
1972 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
1973 << " " << RegShiftedReg.ShiftReg << ">";
1975 case k_ShiftedImmediate:
1976 OS << "<so_reg_imm "
1977 << RegShiftedImm.SrcReg << " "
1978 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
1979 << " #" << RegShiftedImm.ShiftImm << ">";
1981 case k_RotateImmediate:
1982 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1984 case k_BitfieldDescriptor:
1985 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1986 << ", width: " << Bitfield.Width << ">";
1988 case k_RegisterList:
1989 case k_DPRRegisterList:
1990 case k_SPRRegisterList: {
1991 OS << "<register_list ";
1993 const SmallVectorImpl<unsigned> &RegList = getRegList();
1994 for (SmallVectorImpl<unsigned>::const_iterator
1995 I = RegList.begin(), E = RegList.end(); I != E; ) {
1997 if (++I < E) OS << ", ";
2004 OS << "<vector_list " << VectorList.Count << " * "
2005 << VectorList.RegNum << ">";
2007 case k_VectorListAllLanes:
2008 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2009 << VectorList.RegNum << ">";
2011 case k_VectorListIndexed:
2012 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2013 << VectorList.Count << " * " << VectorList.RegNum << ">";
2016 OS << "'" << getToken() << "'";
2019 OS << "<vectorindex " << getVectorIndex() << ">";
2024 /// @name Auto-generated Match Functions
2027 static unsigned MatchRegisterName(StringRef Name);
2031 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2032 SMLoc &StartLoc, SMLoc &EndLoc) {
2033 RegNo = tryParseRegister();
2035 return (RegNo == (unsigned)-1);
2038 /// Try to parse a register name. The token must be an Identifier when called,
2039 /// and if it is a register name the token is eaten and the register number is
2040 /// returned. Otherwise return -1.
2042 int ARMAsmParser::tryParseRegister() {
2043 const AsmToken &Tok = Parser.getTok();
2044 if (Tok.isNot(AsmToken::Identifier)) return -1;
2046 // FIXME: Validate register for the current architecture; we have to do
2047 // validation later, so maybe there is no need for this here.
2048 std::string lowerCase = Tok.getString().lower();
2049 unsigned RegNum = MatchRegisterName(lowerCase);
2051 RegNum = StringSwitch<unsigned>(lowerCase)
2052 .Case("r13", ARM::SP)
2053 .Case("r14", ARM::LR)
2054 .Case("r15", ARM::PC)
2055 .Case("ip", ARM::R12)
2058 if (!RegNum) return -1;
2060 Parser.Lex(); // Eat identifier token.
2065 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2066 // If a recoverable error occurs, return 1. If an irrecoverable error
2067 // occurs, return -1. An irrecoverable error is one where tokens have been
2068 // consumed in the process of trying to parse the shifter (i.e., when it is
2069 // indeed a shifter operand, but malformed).
2070 int ARMAsmParser::tryParseShiftRegister(
2071 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2072 SMLoc S = Parser.getTok().getLoc();
2073 const AsmToken &Tok = Parser.getTok();
2074 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2076 std::string lowerCase = Tok.getString().lower();
2077 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2078 .Case("lsl", ARM_AM::lsl)
2079 .Case("lsr", ARM_AM::lsr)
2080 .Case("asr", ARM_AM::asr)
2081 .Case("ror", ARM_AM::ror)
2082 .Case("rrx", ARM_AM::rrx)
2083 .Default(ARM_AM::no_shift);
2085 if (ShiftTy == ARM_AM::no_shift)
2088 Parser.Lex(); // Eat the operator.
2090 // The source register for the shift has already been added to the
2091 // operand list, so we need to pop it off and combine it into the shifted
2092 // register operand instead.
2093 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2094 if (!PrevOp->isReg())
2095 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2096 int SrcReg = PrevOp->getReg();
2099 if (ShiftTy == ARM_AM::rrx) {
2100 // RRX Doesn't have an explicit shift amount. The encoder expects
2101 // the shift register to be the same as the source register. Seems odd,
2105 // Figure out if this is shifted by a constant or a register (for non-RRX).
2106 if (Parser.getTok().is(AsmToken::Hash)) {
2107 Parser.Lex(); // Eat hash.
2108 SMLoc ImmLoc = Parser.getTok().getLoc();
2109 const MCExpr *ShiftExpr = 0;
2110 if (getParser().ParseExpression(ShiftExpr)) {
2111 Error(ImmLoc, "invalid immediate shift value");
2114 // The expression must be evaluatable as an immediate.
2115 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2117 Error(ImmLoc, "invalid immediate shift value");
2120 // Range check the immediate.
2121 // lsl, ror: 0 <= imm <= 31
2122 // lsr, asr: 0 <= imm <= 32
2123 Imm = CE->getValue();
2125 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2126 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2127 Error(ImmLoc, "immediate shift value out of range");
2130 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2131 ShiftReg = tryParseRegister();
2132 SMLoc L = Parser.getTok().getLoc();
2133 if (ShiftReg == -1) {
2134 Error (L, "expected immediate or register in shift operand");
2138 Error (Parser.getTok().getLoc(),
2139 "expected immediate or register in shift operand");
2144 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2145 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2147 S, Parser.getTok().getLoc()));
2149 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2150 S, Parser.getTok().getLoc()));
2156 /// Try to parse a register name. The token must be an Identifier when called.
2157 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2158 /// if there is a "writeback". 'true' if it's not a register.
2160 /// TODO this is likely to change to allow different register types and or to
2161 /// parse for a specific register type.
2163 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2164 SMLoc S = Parser.getTok().getLoc();
2165 int RegNo = tryParseRegister();
2169 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
2171 const AsmToken &ExclaimTok = Parser.getTok();
2172 if (ExclaimTok.is(AsmToken::Exclaim)) {
2173 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2174 ExclaimTok.getLoc()));
2175 Parser.Lex(); // Eat exclaim token
2179 // Also check for an index operand. This is only legal for vector registers,
2180 // but that'll get caught OK in operand matching, so we don't need to
2181 // explicitly filter everything else out here.
2182 if (Parser.getTok().is(AsmToken::LBrac)) {
2183 SMLoc SIdx = Parser.getTok().getLoc();
2184 Parser.Lex(); // Eat left bracket token.
2186 const MCExpr *ImmVal;
2187 if (getParser().ParseExpression(ImmVal))
2188 return MatchOperand_ParseFail;
2189 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2191 TokError("immediate value expected for vector index");
2192 return MatchOperand_ParseFail;
2195 SMLoc E = Parser.getTok().getLoc();
2196 if (Parser.getTok().isNot(AsmToken::RBrac)) {
2197 Error(E, "']' expected");
2198 return MatchOperand_ParseFail;
2201 Parser.Lex(); // Eat right bracket token.
2203 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2211 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2212 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2214 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2215 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2217 switch (Name.size()) {
2220 if (Name[0] != CoprocOp)
2237 if (Name[0] != CoprocOp || Name[1] != '1')
2241 case '0': return 10;
2242 case '1': return 11;
2243 case '2': return 12;
2244 case '3': return 13;
2245 case '4': return 14;
2246 case '5': return 15;
2254 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2255 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2256 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2257 SMLoc S = Parser.getTok().getLoc();
2258 const AsmToken &Tok = Parser.getTok();
2259 if (!Tok.is(AsmToken::Identifier))
2260 return MatchOperand_NoMatch;
2261 unsigned CC = StringSwitch<unsigned>(Tok.getString())
2262 .Case("eq", ARMCC::EQ)
2263 .Case("ne", ARMCC::NE)
2264 .Case("hs", ARMCC::HS)
2265 .Case("cs", ARMCC::HS)
2266 .Case("lo", ARMCC::LO)
2267 .Case("cc", ARMCC::LO)
2268 .Case("mi", ARMCC::MI)
2269 .Case("pl", ARMCC::PL)
2270 .Case("vs", ARMCC::VS)
2271 .Case("vc", ARMCC::VC)
2272 .Case("hi", ARMCC::HI)
2273 .Case("ls", ARMCC::LS)
2274 .Case("ge", ARMCC::GE)
2275 .Case("lt", ARMCC::LT)
2276 .Case("gt", ARMCC::GT)
2277 .Case("le", ARMCC::LE)
2278 .Case("al", ARMCC::AL)
2281 return MatchOperand_NoMatch;
2282 Parser.Lex(); // Eat the token.
2284 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2286 return MatchOperand_Success;
2289 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2290 /// token must be an Identifier when called, and if it is a coprocessor
2291 /// number, the token is eaten and the operand is added to the operand list.
2292 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2293 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2294 SMLoc S = Parser.getTok().getLoc();
2295 const AsmToken &Tok = Parser.getTok();
2296 if (Tok.isNot(AsmToken::Identifier))
2297 return MatchOperand_NoMatch;
2299 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2301 return MatchOperand_NoMatch;
2303 Parser.Lex(); // Eat identifier token.
2304 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2305 return MatchOperand_Success;
2308 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2309 /// token must be an Identifier when called, and if it is a coprocessor
2310 /// number, the token is eaten and the operand is added to the operand list.
2311 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2312 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2313 SMLoc S = Parser.getTok().getLoc();
2314 const AsmToken &Tok = Parser.getTok();
2315 if (Tok.isNot(AsmToken::Identifier))
2316 return MatchOperand_NoMatch;
2318 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2320 return MatchOperand_NoMatch;
2322 Parser.Lex(); // Eat identifier token.
2323 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2324 return MatchOperand_Success;
2327 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2328 /// coproc_option : '{' imm0_255 '}'
2329 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2330 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2331 SMLoc S = Parser.getTok().getLoc();
2333 // If this isn't a '{', this isn't a coprocessor immediate operand.
2334 if (Parser.getTok().isNot(AsmToken::LCurly))
2335 return MatchOperand_NoMatch;
2336 Parser.Lex(); // Eat the '{'
2339 SMLoc Loc = Parser.getTok().getLoc();
2340 if (getParser().ParseExpression(Expr)) {
2341 Error(Loc, "illegal expression");
2342 return MatchOperand_ParseFail;
2344 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2345 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2346 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2347 return MatchOperand_ParseFail;
2349 int Val = CE->getValue();
2351 // Check for and consume the closing '}'
2352 if (Parser.getTok().isNot(AsmToken::RCurly))
2353 return MatchOperand_ParseFail;
2354 SMLoc E = Parser.getTok().getLoc();
2355 Parser.Lex(); // Eat the '}'
2357 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2358 return MatchOperand_Success;
2361 // For register list parsing, we need to map from raw GPR register numbering
2362 // to the enumeration values. The enumeration values aren't sorted by
2363 // register number due to our using "sp", "lr" and "pc" as canonical names.
2364 static unsigned getNextRegister(unsigned Reg) {
2365 // If this is a GPR, we need to do it manually, otherwise we can rely
2366 // on the sort ordering of the enumeration since the other reg-classes
2368 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2371 default: assert(0 && "Invalid GPR number!");
2372 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2373 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2374 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2375 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2376 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2377 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2378 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2379 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2383 // Return the low-subreg of a given Q register.
2384 static unsigned getDRegFromQReg(unsigned QReg) {
2386 default: llvm_unreachable("expected a Q register!");
2387 case ARM::Q0: return ARM::D0;
2388 case ARM::Q1: return ARM::D2;
2389 case ARM::Q2: return ARM::D4;
2390 case ARM::Q3: return ARM::D6;
2391 case ARM::Q4: return ARM::D8;
2392 case ARM::Q5: return ARM::D10;
2393 case ARM::Q6: return ARM::D12;
2394 case ARM::Q7: return ARM::D14;
2395 case ARM::Q8: return ARM::D16;
2396 case ARM::Q9: return ARM::D18;
2397 case ARM::Q10: return ARM::D20;
2398 case ARM::Q11: return ARM::D22;
2399 case ARM::Q12: return ARM::D24;
2400 case ARM::Q13: return ARM::D26;
2401 case ARM::Q14: return ARM::D28;
2402 case ARM::Q15: return ARM::D30;
2406 /// Parse a register list.
2408 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2409 assert(Parser.getTok().is(AsmToken::LCurly) &&
2410 "Token is not a Left Curly Brace");
2411 SMLoc S = Parser.getTok().getLoc();
2412 Parser.Lex(); // Eat '{' token.
2413 SMLoc RegLoc = Parser.getTok().getLoc();
2415 // Check the first register in the list to see what register class
2416 // this is a list of.
2417 int Reg = tryParseRegister();
2419 return Error(RegLoc, "register expected");
2421 // The reglist instructions have at most 16 registers, so reserve
2422 // space for that many.
2423 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2425 // Allow Q regs and just interpret them as the two D sub-registers.
2426 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2427 Reg = getDRegFromQReg(Reg);
2428 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2431 const MCRegisterClass *RC;
2432 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2433 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2434 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2435 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2436 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2437 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2439 return Error(RegLoc, "invalid register in register list");
2441 // Store the register.
2442 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2444 // This starts immediately after the first register token in the list,
2445 // so we can see either a comma or a minus (range separator) as a legal
2447 while (Parser.getTok().is(AsmToken::Comma) ||
2448 Parser.getTok().is(AsmToken::Minus)) {
2449 if (Parser.getTok().is(AsmToken::Minus)) {
2450 Parser.Lex(); // Eat the minus.
2451 SMLoc EndLoc = Parser.getTok().getLoc();
2452 int EndReg = tryParseRegister();
2454 return Error(EndLoc, "register expected");
2455 // Allow Q regs and just interpret them as the two D sub-registers.
2456 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2457 EndReg = getDRegFromQReg(EndReg) + 1;
2458 // If the register is the same as the start reg, there's nothing
2462 // The register must be in the same register class as the first.
2463 if (!RC->contains(EndReg))
2464 return Error(EndLoc, "invalid register in register list");
2465 // Ranges must go from low to high.
2466 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2467 return Error(EndLoc, "bad range in register list");
2469 // Add all the registers in the range to the register list.
2470 while (Reg != EndReg) {
2471 Reg = getNextRegister(Reg);
2472 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2476 Parser.Lex(); // Eat the comma.
2477 RegLoc = Parser.getTok().getLoc();
2479 Reg = tryParseRegister();
2481 return Error(RegLoc, "register expected");
2482 // Allow Q regs and just interpret them as the two D sub-registers.
2483 bool isQReg = false;
2484 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2485 Reg = getDRegFromQReg(Reg);
2488 // The register must be in the same register class as the first.
2489 if (!RC->contains(Reg))
2490 return Error(RegLoc, "invalid register in register list");
2491 // List must be monotonically increasing.
2492 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
2493 return Error(RegLoc, "register list not in ascending order");
2494 // VFP register lists must also be contiguous.
2495 // It's OK to use the enumeration values directly here rather, as the
2496 // VFP register classes have the enum sorted properly.
2497 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2499 return Error(RegLoc, "non-contiguous register range");
2500 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2502 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2505 SMLoc E = Parser.getTok().getLoc();
2506 if (Parser.getTok().isNot(AsmToken::RCurly))
2507 return Error(E, "'}' expected");
2508 Parser.Lex(); // Eat '}' token.
2510 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2514 // Helper function to parse the lane index for vector lists.
2515 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2516 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index) {
2517 Index = 0; // Always return a defined index value.
2518 if (Parser.getTok().is(AsmToken::LBrac)) {
2519 Parser.Lex(); // Eat the '['.
2520 if (Parser.getTok().is(AsmToken::RBrac)) {
2521 // "Dn[]" is the 'all lanes' syntax.
2522 LaneKind = AllLanes;
2523 Parser.Lex(); // Eat the ']'.
2524 return MatchOperand_Success;
2526 if (Parser.getTok().is(AsmToken::Integer)) {
2527 int64_t Val = Parser.getTok().getIntVal();
2528 // Make this range check context sensitive for .8, .16, .32.
2529 if (Val < 0 && Val > 7)
2530 Error(Parser.getTok().getLoc(), "lane index out of range");
2532 LaneKind = IndexedLane;
2533 Parser.Lex(); // Eat the token;
2534 if (Parser.getTok().isNot(AsmToken::RBrac))
2535 Error(Parser.getTok().getLoc(), "']' expected");
2536 Parser.Lex(); // Eat the ']'.
2537 return MatchOperand_Success;
2539 Error(Parser.getTok().getLoc(), "lane index must be empty or an integer");
2540 return MatchOperand_ParseFail;
2543 return MatchOperand_Success;
2546 // parse a vector register list
2547 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2548 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2549 VectorLaneTy LaneKind;
2551 SMLoc S = Parser.getTok().getLoc();
2552 // As an extension (to match gas), support a plain D register or Q register
2553 // (without encosing curly braces) as a single or double entry list,
2555 if (Parser.getTok().is(AsmToken::Identifier)) {
2556 int Reg = tryParseRegister();
2558 return MatchOperand_NoMatch;
2559 SMLoc E = Parser.getTok().getLoc();
2560 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
2561 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
2562 if (Res != MatchOperand_Success)
2566 assert(0 && "unexpected lane kind!");
2568 E = Parser.getTok().getLoc();
2569 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, S, E));
2572 E = Parser.getTok().getLoc();
2573 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, S, E));
2576 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
2580 return MatchOperand_Success;
2582 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2583 Reg = getDRegFromQReg(Reg);
2584 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex);
2585 if (Res != MatchOperand_Success)
2589 assert(0 && "unexpected lane kind!");
2591 E = Parser.getTok().getLoc();
2592 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, S, E));
2595 E = Parser.getTok().getLoc();
2596 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, S, E));
2599 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
2603 return MatchOperand_Success;
2605 Error(S, "vector register expected");
2606 return MatchOperand_ParseFail;
2609 if (Parser.getTok().isNot(AsmToken::LCurly))
2610 return MatchOperand_NoMatch;
2612 Parser.Lex(); // Eat '{' token.
2613 SMLoc RegLoc = Parser.getTok().getLoc();
2615 int Reg = tryParseRegister();
2617 Error(RegLoc, "register expected");
2618 return MatchOperand_ParseFail;
2621 unsigned FirstReg = Reg;
2622 // The list is of D registers, but we also allow Q regs and just interpret
2623 // them as the two D sub-registers.
2624 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2625 FirstReg = Reg = getDRegFromQReg(Reg);
2629 if (parseVectorLane(LaneKind, LaneIndex) != MatchOperand_Success)
2630 return MatchOperand_ParseFail;
2632 while (Parser.getTok().is(AsmToken::Comma) ||
2633 Parser.getTok().is(AsmToken::Minus)) {
2634 if (Parser.getTok().is(AsmToken::Minus)) {
2635 Parser.Lex(); // Eat the minus.
2636 SMLoc EndLoc = Parser.getTok().getLoc();
2637 int EndReg = tryParseRegister();
2639 Error(EndLoc, "register expected");
2640 return MatchOperand_ParseFail;
2642 // Allow Q regs and just interpret them as the two D sub-registers.
2643 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2644 EndReg = getDRegFromQReg(EndReg) + 1;
2645 // If the register is the same as the start reg, there's nothing
2649 // The register must be in the same register class as the first.
2650 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
2651 Error(EndLoc, "invalid register in register list");
2652 return MatchOperand_ParseFail;
2654 // Ranges must go from low to high.
2656 Error(EndLoc, "bad range in register list");
2657 return MatchOperand_ParseFail;
2659 // Parse the lane specifier if present.
2660 VectorLaneTy NextLaneKind;
2661 unsigned NextLaneIndex;
2662 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
2663 return MatchOperand_ParseFail;
2664 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
2665 Error(EndLoc, "mismatched lane index in register list");
2666 return MatchOperand_ParseFail;
2668 EndLoc = Parser.getTok().getLoc();
2670 // Add all the registers in the range to the register list.
2671 Count += EndReg - Reg;
2675 Parser.Lex(); // Eat the comma.
2676 RegLoc = Parser.getTok().getLoc();
2678 Reg = tryParseRegister();
2680 Error(RegLoc, "register expected");
2681 return MatchOperand_ParseFail;
2683 // vector register lists must be contiguous.
2684 // It's OK to use the enumeration values directly here rather, as the
2685 // VFP register classes have the enum sorted properly.
2687 // The list is of D registers, but we also allow Q regs and just interpret
2688 // them as the two D sub-registers.
2689 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2690 Reg = getDRegFromQReg(Reg);
2691 if (Reg != OldReg + 1) {
2692 Error(RegLoc, "non-contiguous register range");
2693 return MatchOperand_ParseFail;
2697 // Parse the lane specifier if present.
2698 VectorLaneTy NextLaneKind;
2699 unsigned NextLaneIndex;
2700 SMLoc EndLoc = Parser.getTok().getLoc();
2701 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
2702 return MatchOperand_ParseFail;
2703 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
2704 Error(EndLoc, "mismatched lane index in register list");
2705 return MatchOperand_ParseFail;
2709 // Normal D register. Just check that it's contiguous and keep going.
2710 if (Reg != OldReg + 1) {
2711 Error(RegLoc, "non-contiguous register range");
2712 return MatchOperand_ParseFail;
2715 // Parse the lane specifier if present.
2716 VectorLaneTy NextLaneKind;
2717 unsigned NextLaneIndex;
2718 SMLoc EndLoc = Parser.getTok().getLoc();
2719 if (parseVectorLane(NextLaneKind, NextLaneIndex) != MatchOperand_Success)
2720 return MatchOperand_ParseFail;
2721 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
2722 Error(EndLoc, "mismatched lane index in register list");
2723 return MatchOperand_ParseFail;
2727 SMLoc E = Parser.getTok().getLoc();
2728 if (Parser.getTok().isNot(AsmToken::RCurly)) {
2729 Error(E, "'}' expected");
2730 return MatchOperand_ParseFail;
2732 Parser.Lex(); // Eat '}' token.
2736 assert(0 && "unexpected lane kind in register list.");
2738 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count, S, E));
2741 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
2745 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
2749 return MatchOperand_Success;
2752 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
2753 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2754 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2755 SMLoc S = Parser.getTok().getLoc();
2756 const AsmToken &Tok = Parser.getTok();
2757 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2758 StringRef OptStr = Tok.getString();
2760 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
2761 .Case("sy", ARM_MB::SY)
2762 .Case("st", ARM_MB::ST)
2763 .Case("sh", ARM_MB::ISH)
2764 .Case("ish", ARM_MB::ISH)
2765 .Case("shst", ARM_MB::ISHST)
2766 .Case("ishst", ARM_MB::ISHST)
2767 .Case("nsh", ARM_MB::NSH)
2768 .Case("un", ARM_MB::NSH)
2769 .Case("nshst", ARM_MB::NSHST)
2770 .Case("unst", ARM_MB::NSHST)
2771 .Case("osh", ARM_MB::OSH)
2772 .Case("oshst", ARM_MB::OSHST)
2776 return MatchOperand_NoMatch;
2778 Parser.Lex(); // Eat identifier token.
2779 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2780 return MatchOperand_Success;
2783 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2784 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2785 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2786 SMLoc S = Parser.getTok().getLoc();
2787 const AsmToken &Tok = Parser.getTok();
2788 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2789 StringRef IFlagsStr = Tok.getString();
2791 // An iflags string of "none" is interpreted to mean that none of the AIF
2792 // bits are set. Not a terribly useful instruction, but a valid encoding.
2793 unsigned IFlags = 0;
2794 if (IFlagsStr != "none") {
2795 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2796 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2797 .Case("a", ARM_PROC::A)
2798 .Case("i", ARM_PROC::I)
2799 .Case("f", ARM_PROC::F)
2802 // If some specific iflag is already set, it means that some letter is
2803 // present more than once, this is not acceptable.
2804 if (Flag == ~0U || (IFlags & Flag))
2805 return MatchOperand_NoMatch;
2811 Parser.Lex(); // Eat identifier token.
2812 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2813 return MatchOperand_Success;
2816 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2817 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2818 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2819 SMLoc S = Parser.getTok().getLoc();
2820 const AsmToken &Tok = Parser.getTok();
2821 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2822 StringRef Mask = Tok.getString();
2825 // See ARMv6-M 10.1.1
2826 unsigned FlagsVal = StringSwitch<unsigned>(Mask)
2836 .Case("primask", 16)
2837 .Case("basepri", 17)
2838 .Case("basepri_max", 18)
2839 .Case("faultmask", 19)
2840 .Case("control", 20)
2843 if (FlagsVal == ~0U)
2844 return MatchOperand_NoMatch;
2846 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
2847 // basepri, basepri_max and faultmask only valid for V7m.
2848 return MatchOperand_NoMatch;
2850 Parser.Lex(); // Eat identifier token.
2851 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2852 return MatchOperand_Success;
2855 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2856 size_t Start = 0, Next = Mask.find('_');
2857 StringRef Flags = "";
2858 std::string SpecReg = Mask.slice(Start, Next).lower();
2859 if (Next != StringRef::npos)
2860 Flags = Mask.slice(Next+1, Mask.size());
2862 // FlagsVal contains the complete mask:
2864 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2865 unsigned FlagsVal = 0;
2867 if (SpecReg == "apsr") {
2868 FlagsVal = StringSwitch<unsigned>(Flags)
2869 .Case("nzcvq", 0x8) // same as CPSR_f
2870 .Case("g", 0x4) // same as CPSR_s
2871 .Case("nzcvqg", 0xc) // same as CPSR_fs
2874 if (FlagsVal == ~0U) {
2876 return MatchOperand_NoMatch;
2878 FlagsVal = 8; // No flag
2880 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2881 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2883 for (int i = 0, e = Flags.size(); i != e; ++i) {
2884 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2891 // If some specific flag is already set, it means that some letter is
2892 // present more than once, this is not acceptable.
2893 if (FlagsVal == ~0U || (FlagsVal & Flag))
2894 return MatchOperand_NoMatch;
2897 } else // No match for special register.
2898 return MatchOperand_NoMatch;
2900 // Special register without flags is NOT equivalent to "fc" flags.
2901 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
2902 // two lines would enable gas compatibility at the expense of breaking
2908 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2909 if (SpecReg == "spsr")
2912 Parser.Lex(); // Eat identifier token.
2913 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2914 return MatchOperand_Success;
2917 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2918 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2919 int Low, int High) {
2920 const AsmToken &Tok = Parser.getTok();
2921 if (Tok.isNot(AsmToken::Identifier)) {
2922 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2923 return MatchOperand_ParseFail;
2925 StringRef ShiftName = Tok.getString();
2926 std::string LowerOp = Op.lower();
2927 std::string UpperOp = Op.upper();
2928 if (ShiftName != LowerOp && ShiftName != UpperOp) {
2929 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2930 return MatchOperand_ParseFail;
2932 Parser.Lex(); // Eat shift type token.
2934 // There must be a '#' and a shift amount.
2935 if (Parser.getTok().isNot(AsmToken::Hash)) {
2936 Error(Parser.getTok().getLoc(), "'#' expected");
2937 return MatchOperand_ParseFail;
2939 Parser.Lex(); // Eat hash token.
2941 const MCExpr *ShiftAmount;
2942 SMLoc Loc = Parser.getTok().getLoc();
2943 if (getParser().ParseExpression(ShiftAmount)) {
2944 Error(Loc, "illegal expression");
2945 return MatchOperand_ParseFail;
2947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2949 Error(Loc, "constant expression expected");
2950 return MatchOperand_ParseFail;
2952 int Val = CE->getValue();
2953 if (Val < Low || Val > High) {
2954 Error(Loc, "immediate value out of range");
2955 return MatchOperand_ParseFail;
2958 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2960 return MatchOperand_Success;
2963 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2964 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2965 const AsmToken &Tok = Parser.getTok();
2966 SMLoc S = Tok.getLoc();
2967 if (Tok.isNot(AsmToken::Identifier)) {
2968 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2969 return MatchOperand_ParseFail;
2971 int Val = StringSwitch<int>(Tok.getString())
2975 Parser.Lex(); // Eat the token.
2978 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2979 return MatchOperand_ParseFail;
2981 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2983 S, Parser.getTok().getLoc()));
2984 return MatchOperand_Success;
2987 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2988 /// instructions. Legal values are:
2989 /// lsl #n 'n' in [0,31]
2990 /// asr #n 'n' in [1,32]
2991 /// n == 32 encoded as n == 0.
2992 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2993 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2994 const AsmToken &Tok = Parser.getTok();
2995 SMLoc S = Tok.getLoc();
2996 if (Tok.isNot(AsmToken::Identifier)) {
2997 Error(S, "shift operator 'asr' or 'lsl' expected");
2998 return MatchOperand_ParseFail;
3000 StringRef ShiftName = Tok.getString();
3002 if (ShiftName == "lsl" || ShiftName == "LSL")
3004 else if (ShiftName == "asr" || ShiftName == "ASR")
3007 Error(S, "shift operator 'asr' or 'lsl' expected");
3008 return MatchOperand_ParseFail;
3010 Parser.Lex(); // Eat the operator.
3012 // A '#' and a shift amount.
3013 if (Parser.getTok().isNot(AsmToken::Hash)) {
3014 Error(Parser.getTok().getLoc(), "'#' expected");
3015 return MatchOperand_ParseFail;
3017 Parser.Lex(); // Eat hash token.
3019 const MCExpr *ShiftAmount;
3020 SMLoc E = Parser.getTok().getLoc();
3021 if (getParser().ParseExpression(ShiftAmount)) {
3022 Error(E, "malformed shift expression");
3023 return MatchOperand_ParseFail;
3025 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3027 Error(E, "shift amount must be an immediate");
3028 return MatchOperand_ParseFail;
3031 int64_t Val = CE->getValue();
3033 // Shift amount must be in [1,32]
3034 if (Val < 1 || Val > 32) {
3035 Error(E, "'asr' shift amount must be in range [1,32]");
3036 return MatchOperand_ParseFail;
3038 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3039 if (isThumb() && Val == 32) {
3040 Error(E, "'asr #32' shift amount not allowed in Thumb mode");
3041 return MatchOperand_ParseFail;
3043 if (Val == 32) Val = 0;
3045 // Shift amount must be in [1,32]
3046 if (Val < 0 || Val > 31) {
3047 Error(E, "'lsr' shift amount must be in range [0,31]");
3048 return MatchOperand_ParseFail;
3052 E = Parser.getTok().getLoc();
3053 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
3055 return MatchOperand_Success;
3058 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3059 /// of instructions. Legal values are:
3060 /// ror #n 'n' in {0, 8, 16, 24}
3061 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3062 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3063 const AsmToken &Tok = Parser.getTok();
3064 SMLoc S = Tok.getLoc();
3065 if (Tok.isNot(AsmToken::Identifier))
3066 return MatchOperand_NoMatch;
3067 StringRef ShiftName = Tok.getString();
3068 if (ShiftName != "ror" && ShiftName != "ROR")
3069 return MatchOperand_NoMatch;
3070 Parser.Lex(); // Eat the operator.
3072 // A '#' and a rotate amount.
3073 if (Parser.getTok().isNot(AsmToken::Hash)) {
3074 Error(Parser.getTok().getLoc(), "'#' expected");
3075 return MatchOperand_ParseFail;
3077 Parser.Lex(); // Eat hash token.
3079 const MCExpr *ShiftAmount;
3080 SMLoc E = Parser.getTok().getLoc();
3081 if (getParser().ParseExpression(ShiftAmount)) {
3082 Error(E, "malformed rotate expression");
3083 return MatchOperand_ParseFail;
3085 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3087 Error(E, "rotate amount must be an immediate");
3088 return MatchOperand_ParseFail;
3091 int64_t Val = CE->getValue();
3092 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3093 // normally, zero is represented in asm by omitting the rotate operand
3095 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3096 Error(E, "'ror' rotate amount must be 8, 16, or 24");
3097 return MatchOperand_ParseFail;
3100 E = Parser.getTok().getLoc();
3101 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
3103 return MatchOperand_Success;
3106 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3107 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3108 SMLoc S = Parser.getTok().getLoc();
3109 // The bitfield descriptor is really two operands, the LSB and the width.
3110 if (Parser.getTok().isNot(AsmToken::Hash)) {
3111 Error(Parser.getTok().getLoc(), "'#' expected");
3112 return MatchOperand_ParseFail;
3114 Parser.Lex(); // Eat hash token.
3116 const MCExpr *LSBExpr;
3117 SMLoc E = Parser.getTok().getLoc();
3118 if (getParser().ParseExpression(LSBExpr)) {
3119 Error(E, "malformed immediate expression");
3120 return MatchOperand_ParseFail;
3122 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3124 Error(E, "'lsb' operand must be an immediate");
3125 return MatchOperand_ParseFail;
3128 int64_t LSB = CE->getValue();
3129 // The LSB must be in the range [0,31]
3130 if (LSB < 0 || LSB > 31) {
3131 Error(E, "'lsb' operand must be in the range [0,31]");
3132 return MatchOperand_ParseFail;
3134 E = Parser.getTok().getLoc();
3136 // Expect another immediate operand.
3137 if (Parser.getTok().isNot(AsmToken::Comma)) {
3138 Error(Parser.getTok().getLoc(), "too few operands");
3139 return MatchOperand_ParseFail;
3141 Parser.Lex(); // Eat hash token.
3142 if (Parser.getTok().isNot(AsmToken::Hash)) {
3143 Error(Parser.getTok().getLoc(), "'#' expected");
3144 return MatchOperand_ParseFail;
3146 Parser.Lex(); // Eat hash token.
3148 const MCExpr *WidthExpr;
3149 if (getParser().ParseExpression(WidthExpr)) {
3150 Error(E, "malformed immediate expression");
3151 return MatchOperand_ParseFail;
3153 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3155 Error(E, "'width' operand must be an immediate");
3156 return MatchOperand_ParseFail;
3159 int64_t Width = CE->getValue();
3160 // The LSB must be in the range [1,32-lsb]
3161 if (Width < 1 || Width > 32 - LSB) {
3162 Error(E, "'width' operand must be in the range [1,32-lsb]");
3163 return MatchOperand_ParseFail;
3165 E = Parser.getTok().getLoc();
3167 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
3169 return MatchOperand_Success;
3172 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3173 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3174 // Check for a post-index addressing register operand. Specifically:
3175 // postidx_reg := '+' register {, shift}
3176 // | '-' register {, shift}
3177 // | register {, shift}
3179 // This method must return MatchOperand_NoMatch without consuming any tokens
3180 // in the case where there is no match, as other alternatives take other
3182 AsmToken Tok = Parser.getTok();
3183 SMLoc S = Tok.getLoc();
3184 bool haveEaten = false;
3187 if (Tok.is(AsmToken::Plus)) {
3188 Parser.Lex(); // Eat the '+' token.
3190 } else if (Tok.is(AsmToken::Minus)) {
3191 Parser.Lex(); // Eat the '-' token.
3195 if (Parser.getTok().is(AsmToken::Identifier))
3196 Reg = tryParseRegister();
3199 return MatchOperand_NoMatch;
3200 Error(Parser.getTok().getLoc(), "register expected");
3201 return MatchOperand_ParseFail;
3203 SMLoc E = Parser.getTok().getLoc();
3205 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3206 unsigned ShiftImm = 0;
3207 if (Parser.getTok().is(AsmToken::Comma)) {
3208 Parser.Lex(); // Eat the ','.
3209 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3210 return MatchOperand_ParseFail;
3213 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3216 return MatchOperand_Success;
3219 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3220 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3221 // Check for a post-index addressing register operand. Specifically:
3222 // am3offset := '+' register
3229 // This method must return MatchOperand_NoMatch without consuming any tokens
3230 // in the case where there is no match, as other alternatives take other
3232 AsmToken Tok = Parser.getTok();
3233 SMLoc S = Tok.getLoc();
3235 // Do immediates first, as we always parse those if we have a '#'.
3236 if (Parser.getTok().is(AsmToken::Hash)) {
3237 Parser.Lex(); // Eat the '#'.
3238 // Explicitly look for a '-', as we need to encode negative zero
3240 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3241 const MCExpr *Offset;
3242 if (getParser().ParseExpression(Offset))
3243 return MatchOperand_ParseFail;
3244 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3246 Error(S, "constant expression expected");
3247 return MatchOperand_ParseFail;
3249 SMLoc E = Tok.getLoc();
3250 // Negative zero is encoded as the flag value INT32_MIN.
3251 int32_t Val = CE->getValue();
3252 if (isNegative && Val == 0)
3256 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3258 return MatchOperand_Success;
3262 bool haveEaten = false;
3265 if (Tok.is(AsmToken::Plus)) {
3266 Parser.Lex(); // Eat the '+' token.
3268 } else if (Tok.is(AsmToken::Minus)) {
3269 Parser.Lex(); // Eat the '-' token.
3273 if (Parser.getTok().is(AsmToken::Identifier))
3274 Reg = tryParseRegister();
3277 return MatchOperand_NoMatch;
3278 Error(Parser.getTok().getLoc(), "register expected");
3279 return MatchOperand_ParseFail;
3281 SMLoc E = Parser.getTok().getLoc();
3283 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3286 return MatchOperand_Success;
3289 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3290 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3291 /// when they refer multiple MIOperands inside a single one.
3293 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
3294 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3296 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3297 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3298 // Create a writeback register dummy placeholder.
3299 Inst.addOperand(MCOperand::CreateReg(0));
3301 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3303 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3307 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3308 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3309 /// when they refer multiple MIOperands inside a single one.
3311 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
3312 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3313 // Create a writeback register dummy placeholder.
3314 Inst.addOperand(MCOperand::CreateReg(0));
3316 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3317 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3319 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3321 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3325 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3326 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3327 /// when they refer multiple MIOperands inside a single one.
3329 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3330 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3331 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3333 // Create a writeback register dummy placeholder.
3334 Inst.addOperand(MCOperand::CreateImm(0));
3336 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3337 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3341 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3342 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3343 /// when they refer multiple MIOperands inside a single one.
3345 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
3346 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3347 // Create a writeback register dummy placeholder.
3348 Inst.addOperand(MCOperand::CreateImm(0));
3349 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3350 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3351 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3355 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3356 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3357 /// when they refer multiple MIOperands inside a single one.
3359 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3360 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3361 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3363 // Create a writeback register dummy placeholder.
3364 Inst.addOperand(MCOperand::CreateImm(0));
3366 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3367 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3371 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3372 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3373 /// when they refer multiple MIOperands inside a single one.
3375 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3376 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3377 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3379 // Create a writeback register dummy placeholder.
3380 Inst.addOperand(MCOperand::CreateImm(0));
3382 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3383 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3388 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3389 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3390 /// when they refer multiple MIOperands inside a single one.
3392 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
3393 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3394 // Create a writeback register dummy placeholder.
3395 Inst.addOperand(MCOperand::CreateImm(0));
3396 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3397 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3398 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3402 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3403 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3404 /// when they refer multiple MIOperands inside a single one.
3406 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
3407 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3408 // Create a writeback register dummy placeholder.
3409 Inst.addOperand(MCOperand::CreateImm(0));
3410 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3411 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3412 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3416 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3417 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3418 /// when they refer multiple MIOperands inside a single one.
3420 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3421 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3422 // Create a writeback register dummy placeholder.
3423 Inst.addOperand(MCOperand::CreateImm(0));
3424 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3425 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3426 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3430 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
3431 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3432 /// when they refer multiple MIOperands inside a single one.
3434 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3435 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3437 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3438 // Create a writeback register dummy placeholder.
3439 Inst.addOperand(MCOperand::CreateImm(0));
3441 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3443 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3445 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3449 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
3450 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3451 /// when they refer multiple MIOperands inside a single one.
3453 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3454 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3456 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3457 // Create a writeback register dummy placeholder.
3458 Inst.addOperand(MCOperand::CreateImm(0));
3460 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3462 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3464 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3468 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
3469 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3470 /// when they refer multiple MIOperands inside a single one.
3472 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
3473 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3474 // Create a writeback register dummy placeholder.
3475 Inst.addOperand(MCOperand::CreateImm(0));
3477 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3479 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3481 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
3483 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3487 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
3488 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3489 /// when they refer multiple MIOperands inside a single one.
3491 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
3492 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3493 // Create a writeback register dummy placeholder.
3494 Inst.addOperand(MCOperand::CreateImm(0));
3496 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3498 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
3500 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
3502 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3506 /// cvtLdrdPre - Convert parsed operands to MCInst.
3507 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3508 /// when they refer multiple MIOperands inside a single one.
3510 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
3511 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3513 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3514 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3515 // Create a writeback register dummy placeholder.
3516 Inst.addOperand(MCOperand::CreateImm(0));
3518 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3520 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3524 /// cvtStrdPre - Convert parsed operands to MCInst.
3525 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3526 /// when they refer multiple MIOperands inside a single one.
3528 cvtStrdPre(MCInst &Inst, unsigned Opcode,
3529 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3530 // Create a writeback register dummy placeholder.
3531 Inst.addOperand(MCOperand::CreateImm(0));
3533 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3534 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3536 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
3538 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3542 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
3543 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3544 /// when they refer multiple MIOperands inside a single one.
3546 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
3547 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3548 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3549 // Create a writeback register dummy placeholder.
3550 Inst.addOperand(MCOperand::CreateImm(0));
3551 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
3552 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3556 /// cvtThumbMultiple- Convert parsed operands to MCInst.
3557 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3558 /// when they refer multiple MIOperands inside a single one.
3560 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
3561 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3562 // The second source operand must be the same register as the destination
3564 if (Operands.size() == 6 &&
3565 (((ARMOperand*)Operands[3])->getReg() !=
3566 ((ARMOperand*)Operands[5])->getReg()) &&
3567 (((ARMOperand*)Operands[3])->getReg() !=
3568 ((ARMOperand*)Operands[4])->getReg())) {
3569 Error(Operands[3]->getStartLoc(),
3570 "destination register must match source register");
3573 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3574 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
3575 // If we have a three-operand form, make sure to set Rn to be the operand
3576 // that isn't the same as Rd.
3578 if (Operands.size() == 6 &&
3579 ((ARMOperand*)Operands[4])->getReg() ==
3580 ((ARMOperand*)Operands[3])->getReg())
3582 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
3583 Inst.addOperand(Inst.getOperand(0));
3584 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
3590 cvtVLDwbFixed(MCInst &Inst, unsigned Opcode,
3591 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3593 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3594 // Create a writeback register dummy placeholder.
3595 Inst.addOperand(MCOperand::CreateImm(0));
3597 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3599 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3604 cvtVLDwbRegister(MCInst &Inst, unsigned Opcode,
3605 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3607 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3608 // Create a writeback register dummy placeholder.
3609 Inst.addOperand(MCOperand::CreateImm(0));
3611 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3613 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3615 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3620 cvtVSTwbFixed(MCInst &Inst, unsigned Opcode,
3621 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3622 // Create a writeback register dummy placeholder.
3623 Inst.addOperand(MCOperand::CreateImm(0));
3625 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3627 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3629 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3634 cvtVSTwbRegister(MCInst &Inst, unsigned Opcode,
3635 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3636 // Create a writeback register dummy placeholder.
3637 Inst.addOperand(MCOperand::CreateImm(0));
3639 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
3641 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
3643 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
3645 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3649 /// Parse an ARM memory expression, return false if successful else return true
3650 /// or an error. The first token must be a '[' when called.
3652 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3654 assert(Parser.getTok().is(AsmToken::LBrac) &&
3655 "Token is not a Left Bracket");
3656 S = Parser.getTok().getLoc();
3657 Parser.Lex(); // Eat left bracket token.
3659 const AsmToken &BaseRegTok = Parser.getTok();
3660 int BaseRegNum = tryParseRegister();
3661 if (BaseRegNum == -1)
3662 return Error(BaseRegTok.getLoc(), "register expected");
3664 // The next token must either be a comma or a closing bracket.
3665 const AsmToken &Tok = Parser.getTok();
3666 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
3667 return Error(Tok.getLoc(), "malformed memory operand");
3669 if (Tok.is(AsmToken::RBrac)) {
3671 Parser.Lex(); // Eat right bracket token.
3673 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
3674 0, 0, false, S, E));
3676 // If there's a pre-indexing writeback marker, '!', just add it as a token
3677 // operand. It's rather odd, but syntactically valid.
3678 if (Parser.getTok().is(AsmToken::Exclaim)) {
3679 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3680 Parser.Lex(); // Eat the '!'.
3686 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
3687 Parser.Lex(); // Eat the comma.
3689 // If we have a ':', it's an alignment specifier.
3690 if (Parser.getTok().is(AsmToken::Colon)) {
3691 Parser.Lex(); // Eat the ':'.
3692 E = Parser.getTok().getLoc();
3695 if (getParser().ParseExpression(Expr))
3698 // The expression has to be a constant. Memory references with relocations
3699 // don't come through here, as they use the <label> forms of the relevant
3701 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3703 return Error (E, "constant expression expected");
3706 switch (CE->getValue()) {
3708 return Error(E, "alignment specifier must be 64, 128, or 256 bits");
3709 case 64: Align = 8; break;
3710 case 128: Align = 16; break;
3711 case 256: Align = 32; break;
3714 // Now we should have the closing ']'
3715 E = Parser.getTok().getLoc();
3716 if (Parser.getTok().isNot(AsmToken::RBrac))
3717 return Error(E, "']' expected");
3718 Parser.Lex(); // Eat right bracket token.
3720 // Don't worry about range checking the value here. That's handled by
3721 // the is*() predicates.
3722 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
3723 ARM_AM::no_shift, 0, Align,
3726 // If there's a pre-indexing writeback marker, '!', just add it as a token
3728 if (Parser.getTok().is(AsmToken::Exclaim)) {
3729 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3730 Parser.Lex(); // Eat the '!'.
3736 // If we have a '#', it's an immediate offset, else assume it's a register
3737 // offset. Be friendly and also accept a plain integer (without a leading
3738 // hash) for gas compatibility.
3739 if (Parser.getTok().is(AsmToken::Hash) ||
3740 Parser.getTok().is(AsmToken::Integer)) {
3741 if (Parser.getTok().is(AsmToken::Hash))
3742 Parser.Lex(); // Eat the '#'.
3743 E = Parser.getTok().getLoc();
3745 bool isNegative = getParser().getTok().is(AsmToken::Minus);
3746 const MCExpr *Offset;
3747 if (getParser().ParseExpression(Offset))
3750 // The expression has to be a constant. Memory references with relocations
3751 // don't come through here, as they use the <label> forms of the relevant
3753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3755 return Error (E, "constant expression expected");
3757 // If the constant was #-0, represent it as INT32_MIN.
3758 int32_t Val = CE->getValue();
3759 if (isNegative && Val == 0)
3760 CE = MCConstantExpr::Create(INT32_MIN, getContext());
3762 // Now we should have the closing ']'
3763 E = Parser.getTok().getLoc();
3764 if (Parser.getTok().isNot(AsmToken::RBrac))
3765 return Error(E, "']' expected");
3766 Parser.Lex(); // Eat right bracket token.
3768 // Don't worry about range checking the value here. That's handled by
3769 // the is*() predicates.
3770 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
3771 ARM_AM::no_shift, 0, 0,
3774 // If there's a pre-indexing writeback marker, '!', just add it as a token
3776 if (Parser.getTok().is(AsmToken::Exclaim)) {
3777 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3778 Parser.Lex(); // Eat the '!'.
3784 // The register offset is optionally preceded by a '+' or '-'
3785 bool isNegative = false;
3786 if (Parser.getTok().is(AsmToken::Minus)) {
3788 Parser.Lex(); // Eat the '-'.
3789 } else if (Parser.getTok().is(AsmToken::Plus)) {
3791 Parser.Lex(); // Eat the '+'.
3794 E = Parser.getTok().getLoc();
3795 int OffsetRegNum = tryParseRegister();
3796 if (OffsetRegNum == -1)
3797 return Error(E, "register expected");
3799 // If there's a shift operator, handle it.
3800 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
3801 unsigned ShiftImm = 0;
3802 if (Parser.getTok().is(AsmToken::Comma)) {
3803 Parser.Lex(); // Eat the ','.
3804 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
3808 // Now we should have the closing ']'
3809 E = Parser.getTok().getLoc();
3810 if (Parser.getTok().isNot(AsmToken::RBrac))
3811 return Error(E, "']' expected");
3812 Parser.Lex(); // Eat right bracket token.
3814 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
3815 ShiftType, ShiftImm, 0, isNegative,
3818 // If there's a pre-indexing writeback marker, '!', just add it as a token
3820 if (Parser.getTok().is(AsmToken::Exclaim)) {
3821 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
3822 Parser.Lex(); // Eat the '!'.
3828 /// parseMemRegOffsetShift - one of these two:
3829 /// ( lsl | lsr | asr | ror ) , # shift_amount
3831 /// return true if it parses a shift otherwise it returns false.
3832 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
3834 SMLoc Loc = Parser.getTok().getLoc();
3835 const AsmToken &Tok = Parser.getTok();
3836 if (Tok.isNot(AsmToken::Identifier))
3838 StringRef ShiftName = Tok.getString();
3839 if (ShiftName == "lsl" || ShiftName == "LSL")
3841 else if (ShiftName == "lsr" || ShiftName == "LSR")
3843 else if (ShiftName == "asr" || ShiftName == "ASR")
3845 else if (ShiftName == "ror" || ShiftName == "ROR")
3847 else if (ShiftName == "rrx" || ShiftName == "RRX")
3850 return Error(Loc, "illegal shift operator");
3851 Parser.Lex(); // Eat shift type token.
3853 // rrx stands alone.
3855 if (St != ARM_AM::rrx) {
3856 Loc = Parser.getTok().getLoc();
3857 // A '#' and a shift amount.
3858 const AsmToken &HashTok = Parser.getTok();
3859 if (HashTok.isNot(AsmToken::Hash))
3860 return Error(HashTok.getLoc(), "'#' expected");
3861 Parser.Lex(); // Eat hash token.
3864 if (getParser().ParseExpression(Expr))
3866 // Range check the immediate.
3867 // lsl, ror: 0 <= imm <= 31
3868 // lsr, asr: 0 <= imm <= 32
3869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3871 return Error(Loc, "shift amount must be an immediate");
3872 int64_t Imm = CE->getValue();
3874 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
3875 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
3876 return Error(Loc, "immediate shift value out of range");
3883 /// parseFPImm - A floating point immediate expression operand.
3884 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3885 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3886 SMLoc S = Parser.getTok().getLoc();
3888 if (Parser.getTok().isNot(AsmToken::Hash))
3889 return MatchOperand_NoMatch;
3891 // Disambiguate the VMOV forms that can accept an FP immediate.
3892 // vmov.f32 <sreg>, #imm
3893 // vmov.f64 <dreg>, #imm
3894 // vmov.f32 <dreg>, #imm @ vector f32x2
3895 // vmov.f32 <qreg>, #imm @ vector f32x4
3897 // There are also the NEON VMOV instructions which expect an
3898 // integer constant. Make sure we don't try to parse an FPImm
3900 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
3901 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
3902 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
3903 TyOp->getToken() != ".f64"))
3904 return MatchOperand_NoMatch;
3906 Parser.Lex(); // Eat the '#'.
3908 // Handle negation, as that still comes through as a separate token.
3909 bool isNegative = false;
3910 if (Parser.getTok().is(AsmToken::Minus)) {
3914 const AsmToken &Tok = Parser.getTok();
3915 if (Tok.is(AsmToken::Real)) {
3916 APFloat RealVal(APFloat::IEEEdouble, Tok.getString());
3917 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
3918 // If we had a '-' in front, toggle the sign bit.
3919 IntVal ^= (uint64_t)isNegative << 63;
3920 int Val = ARM_AM::getFP64Imm(APInt(64, IntVal));
3921 Parser.Lex(); // Eat the token.
3923 TokError("floating point value out of range");
3924 return MatchOperand_ParseFail;
3926 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3927 return MatchOperand_Success;
3929 if (Tok.is(AsmToken::Integer)) {
3930 int64_t Val = Tok.getIntVal();
3931 Parser.Lex(); // Eat the token.
3932 if (Val > 255 || Val < 0) {
3933 TokError("encoded floating point value out of range");
3934 return MatchOperand_ParseFail;
3936 Operands.push_back(ARMOperand::CreateFPImm(Val, S, getContext()));
3937 return MatchOperand_Success;
3940 TokError("invalid floating point immediate");
3941 return MatchOperand_ParseFail;
3943 /// Parse a arm instruction operand. For now this parses the operand regardless
3944 /// of the mnemonic.
3945 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3946 StringRef Mnemonic) {
3949 // Check if the current operand has a custom associated parser, if so, try to
3950 // custom parse the operand, or fallback to the general approach.
3951 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
3952 if (ResTy == MatchOperand_Success)
3954 // If there wasn't a custom match, try the generic matcher below. Otherwise,
3955 // there was a match, but an error occurred, in which case, just return that
3956 // the operand parsing failed.
3957 if (ResTy == MatchOperand_ParseFail)
3960 switch (getLexer().getKind()) {
3962 Error(Parser.getTok().getLoc(), "unexpected token in operand");
3964 case AsmToken::Identifier: {
3965 // If this is VMRS, check for the apsr_nzcv operand.
3966 if (!tryParseRegisterWithWriteBack(Operands))
3968 int Res = tryParseShiftRegister(Operands);
3969 if (Res == 0) // success
3971 else if (Res == -1) // irrecoverable error
3973 if (Mnemonic == "vmrs" && Parser.getTok().getString() == "apsr_nzcv") {
3974 S = Parser.getTok().getLoc();
3976 Operands.push_back(ARMOperand::CreateToken("apsr_nzcv", S));
3980 // Fall though for the Identifier case that is not a register or a
3983 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
3984 case AsmToken::Integer: // things like 1f and 2b as a branch targets
3985 case AsmToken::String: // quoted label names.
3986 case AsmToken::Dot: { // . as a branch target
3987 // This was not a register so parse other operands that start with an
3988 // identifier (like labels) as expressions and create them as immediates.
3989 const MCExpr *IdVal;
3990 S = Parser.getTok().getLoc();
3991 if (getParser().ParseExpression(IdVal))
3993 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3994 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3997 case AsmToken::LBrac:
3998 return parseMemory(Operands);
3999 case AsmToken::LCurly:
4000 return parseRegisterList(Operands);
4001 case AsmToken::Hash: {
4002 // #42 -> immediate.
4003 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
4004 S = Parser.getTok().getLoc();
4006 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4007 const MCExpr *ImmVal;
4008 if (getParser().ParseExpression(ImmVal))
4010 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4012 int32_t Val = CE->getValue();
4013 if (isNegative && Val == 0)
4014 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4016 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4017 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4020 case AsmToken::Colon: {
4021 // ":lower16:" and ":upper16:" expression prefixes
4022 // FIXME: Check it's an expression prefix,
4023 // e.g. (FOO - :lower16:BAR) isn't legal.
4024 ARMMCExpr::VariantKind RefKind;
4025 if (parsePrefix(RefKind))
4028 const MCExpr *SubExprVal;
4029 if (getParser().ParseExpression(SubExprVal))
4032 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4034 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4035 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4041 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4042 // :lower16: and :upper16:.
4043 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4044 RefKind = ARMMCExpr::VK_ARM_None;
4046 // :lower16: and :upper16: modifiers
4047 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4048 Parser.Lex(); // Eat ':'
4050 if (getLexer().isNot(AsmToken::Identifier)) {
4051 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4055 StringRef IDVal = Parser.getTok().getIdentifier();
4056 if (IDVal == "lower16") {
4057 RefKind = ARMMCExpr::VK_ARM_LO16;
4058 } else if (IDVal == "upper16") {
4059 RefKind = ARMMCExpr::VK_ARM_HI16;
4061 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4066 if (getLexer().isNot(AsmToken::Colon)) {
4067 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4070 Parser.Lex(); // Eat the last ':'
4074 /// \brief Given a mnemonic, split out possible predication code and carry
4075 /// setting letters to form a canonical mnemonic and flags.
4077 // FIXME: Would be nice to autogen this.
4078 // FIXME: This is a bit of a maze of special cases.
4079 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4080 unsigned &PredicationCode,
4082 unsigned &ProcessorIMod,
4083 StringRef &ITMask) {
4084 PredicationCode = ARMCC::AL;
4085 CarrySetting = false;
4088 // Ignore some mnemonics we know aren't predicated forms.
4090 // FIXME: Would be nice to autogen this.
4091 if ((Mnemonic == "movs" && isThumb()) ||
4092 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4093 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4094 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4095 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4096 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4097 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4098 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
4101 // First, split out any predication code. Ignore mnemonics we know aren't
4102 // predicated but do have a carry-set and so weren't caught above.
4103 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4104 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4105 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4106 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4107 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4108 .Case("eq", ARMCC::EQ)
4109 .Case("ne", ARMCC::NE)
4110 .Case("hs", ARMCC::HS)
4111 .Case("cs", ARMCC::HS)
4112 .Case("lo", ARMCC::LO)
4113 .Case("cc", ARMCC::LO)
4114 .Case("mi", ARMCC::MI)
4115 .Case("pl", ARMCC::PL)
4116 .Case("vs", ARMCC::VS)
4117 .Case("vc", ARMCC::VC)
4118 .Case("hi", ARMCC::HI)
4119 .Case("ls", ARMCC::LS)
4120 .Case("ge", ARMCC::GE)
4121 .Case("lt", ARMCC::LT)
4122 .Case("gt", ARMCC::GT)
4123 .Case("le", ARMCC::LE)
4124 .Case("al", ARMCC::AL)
4127 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4128 PredicationCode = CC;
4132 // Next, determine if we have a carry setting bit. We explicitly ignore all
4133 // the instructions we know end in 's'.
4134 if (Mnemonic.endswith("s") &&
4135 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4136 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4137 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4138 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4139 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
4140 (Mnemonic == "movs" && isThumb()))) {
4141 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4142 CarrySetting = true;
4145 // The "cps" instruction can have a interrupt mode operand which is glued into
4146 // the mnemonic. Check if this is the case, split it and parse the imod op
4147 if (Mnemonic.startswith("cps")) {
4148 // Split out any imod code.
4150 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4151 .Case("ie", ARM_PROC::IE)
4152 .Case("id", ARM_PROC::ID)
4155 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4156 ProcessorIMod = IMod;
4160 // The "it" instruction has the condition mask on the end of the mnemonic.
4161 if (Mnemonic.startswith("it")) {
4162 ITMask = Mnemonic.slice(2, Mnemonic.size());
4163 Mnemonic = Mnemonic.slice(0, 2);
4169 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4170 /// inclusion of carry set or predication code operands.
4172 // FIXME: It would be nice to autogen this.
4174 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4175 bool &CanAcceptPredicationCode) {
4176 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4177 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4178 Mnemonic == "add" || Mnemonic == "adc" ||
4179 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4180 Mnemonic == "orr" || Mnemonic == "mvn" ||
4181 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4182 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4183 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4184 Mnemonic == "mla" || Mnemonic == "smlal" ||
4185 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4186 CanAcceptCarrySet = true;
4188 CanAcceptCarrySet = false;
4190 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4191 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4192 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4193 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4194 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4195 (Mnemonic == "clrex" && !isThumb()) ||
4196 (Mnemonic == "nop" && isThumbOne()) ||
4197 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4198 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4199 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4200 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4202 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4203 CanAcceptPredicationCode = false;
4205 CanAcceptPredicationCode = true;
4208 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4209 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4210 CanAcceptPredicationCode = false;
4214 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4215 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4216 // FIXME: This is all horribly hacky. We really need a better way to deal
4217 // with optional operands like this in the matcher table.
4219 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4220 // another does not. Specifically, the MOVW instruction does not. So we
4221 // special case it here and remove the defaulted (non-setting) cc_out
4222 // operand if that's the instruction we're trying to match.
4224 // We do this as post-processing of the explicit operands rather than just
4225 // conditionally adding the cc_out in the first place because we need
4226 // to check the type of the parsed immediate operand.
4227 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4228 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4229 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4230 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4233 // Register-register 'add' for thumb does not have a cc_out operand
4234 // when there are only two register operands.
4235 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4236 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4237 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4238 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4240 // Register-register 'add' for thumb does not have a cc_out operand
4241 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4242 // have to check the immediate range here since Thumb2 has a variant
4243 // that can handle a different range and has a cc_out operand.
4244 if (((isThumb() && Mnemonic == "add") ||
4245 (isThumbTwo() && Mnemonic == "sub")) &&
4246 Operands.size() == 6 &&
4247 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4248 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4249 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4250 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4251 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
4252 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4254 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4255 // imm0_4095 variant. That's the least-preferred variant when
4256 // selecting via the generic "add" mnemonic, so to know that we
4257 // should remove the cc_out operand, we have to explicitly check that
4258 // it's not one of the other variants. Ugh.
4259 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4260 Operands.size() == 6 &&
4261 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4262 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4263 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4264 // Nest conditions rather than one big 'if' statement for readability.
4266 // If either register is a high reg, it's either one of the SP
4267 // variants (handled above) or a 32-bit encoding, so we just
4268 // check against T3.
4269 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4270 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4271 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4273 // If both registers are low, we're in an IT block, and the immediate is
4274 // in range, we should use encoding T1 instead, which has a cc_out.
4276 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4277 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4278 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4281 // Otherwise, we use encoding T4, which does not have a cc_out
4286 // The thumb2 multiply instruction doesn't have a CCOut register, so
4287 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4288 // use the 16-bit encoding or not.
4289 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4290 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4291 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4292 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4293 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4294 // If the registers aren't low regs, the destination reg isn't the
4295 // same as one of the source regs, or the cc_out operand is zero
4296 // outside of an IT block, we have to use the 32-bit encoding, so
4297 // remove the cc_out operand.
4298 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4299 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4300 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4302 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4303 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4304 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4305 static_cast<ARMOperand*>(Operands[4])->getReg())))
4308 // Also check the 'mul' syntax variant that doesn't specify an explicit
4309 // destination register.
4310 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4311 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4312 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4313 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4314 // If the registers aren't low regs or the cc_out operand is zero
4315 // outside of an IT block, we have to use the 32-bit encoding, so
4316 // remove the cc_out operand.
4317 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4318 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4324 // Register-register 'add/sub' for thumb does not have a cc_out operand
4325 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4326 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4327 // right, this will result in better diagnostics (which operand is off)
4329 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4330 (Operands.size() == 5 || Operands.size() == 6) &&
4331 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4332 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4333 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4339 static bool isDataTypeToken(StringRef Tok) {
4340 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4341 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4342 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4343 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4344 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4345 Tok == ".f" || Tok == ".d";
4348 // FIXME: This bit should probably be handled via an explicit match class
4349 // in the .td files that matches the suffix instead of having it be
4350 // a literal string token the way it is now.
4351 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4352 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4355 /// Parse an arm instruction mnemonic followed by its operands.
4356 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
4357 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4358 // Create the leading tokens for the mnemonic, split by '.' characters.
4359 size_t Start = 0, Next = Name.find('.');
4360 StringRef Mnemonic = Name.slice(Start, Next);
4362 // Split out the predication code and carry setting flag from the mnemonic.
4363 unsigned PredicationCode;
4364 unsigned ProcessorIMod;
4367 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4368 ProcessorIMod, ITMask);
4370 // In Thumb1, only the branch (B) instruction can be predicated.
4371 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
4372 Parser.EatToEndOfStatement();
4373 return Error(NameLoc, "conditional execution not supported in Thumb1");
4376 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
4378 // Handle the IT instruction ITMask. Convert it to a bitmask. This
4379 // is the mask as it will be for the IT encoding if the conditional
4380 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
4381 // where the conditional bit0 is zero, the instruction post-processing
4382 // will adjust the mask accordingly.
4383 if (Mnemonic == "it") {
4384 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
4385 if (ITMask.size() > 3) {
4386 Parser.EatToEndOfStatement();
4387 return Error(Loc, "too many conditions on IT instruction");
4390 for (unsigned i = ITMask.size(); i != 0; --i) {
4391 char pos = ITMask[i - 1];
4392 if (pos != 't' && pos != 'e') {
4393 Parser.EatToEndOfStatement();
4394 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
4397 if (ITMask[i - 1] == 't')
4400 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
4403 // FIXME: This is all a pretty gross hack. We should automatically handle
4404 // optional operands like this via tblgen.
4406 // Next, add the CCOut and ConditionCode operands, if needed.
4408 // For mnemonics which can ever incorporate a carry setting bit or predication
4409 // code, our matching model involves us always generating CCOut and
4410 // ConditionCode operands to match the mnemonic "as written" and then we let
4411 // the matcher deal with finding the right instruction or generating an
4412 // appropriate error.
4413 bool CanAcceptCarrySet, CanAcceptPredicationCode;
4414 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
4416 // If we had a carry-set on an instruction that can't do that, issue an
4418 if (!CanAcceptCarrySet && CarrySetting) {
4419 Parser.EatToEndOfStatement();
4420 return Error(NameLoc, "instruction '" + Mnemonic +
4421 "' can not set flags, but 's' suffix specified");
4423 // If we had a predication code on an instruction that can't do that, issue an
4425 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
4426 Parser.EatToEndOfStatement();
4427 return Error(NameLoc, "instruction '" + Mnemonic +
4428 "' is not predicable, but condition code specified");
4431 // Add the carry setting operand, if necessary.
4432 if (CanAcceptCarrySet) {
4433 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
4434 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
4438 // Add the predication code operand, if necessary.
4439 if (CanAcceptPredicationCode) {
4440 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
4442 Operands.push_back(ARMOperand::CreateCondCode(
4443 ARMCC::CondCodes(PredicationCode), Loc));
4446 // Add the processor imod operand, if necessary.
4447 if (ProcessorIMod) {
4448 Operands.push_back(ARMOperand::CreateImm(
4449 MCConstantExpr::Create(ProcessorIMod, getContext()),
4453 // Add the remaining tokens in the mnemonic.
4454 while (Next != StringRef::npos) {
4456 Next = Name.find('.', Start + 1);
4457 StringRef ExtraToken = Name.slice(Start, Next);
4459 // Some NEON instructions have an optional datatype suffix that is
4460 // completely ignored. Check for that.
4461 if (isDataTypeToken(ExtraToken) &&
4462 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
4465 if (ExtraToken != ".n") {
4466 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
4467 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
4471 // Read the remaining operands.
4472 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4473 // Read the first operand.
4474 if (parseOperand(Operands, Mnemonic)) {
4475 Parser.EatToEndOfStatement();
4479 while (getLexer().is(AsmToken::Comma)) {
4480 Parser.Lex(); // Eat the comma.
4482 // Parse and remember the operand.
4483 if (parseOperand(Operands, Mnemonic)) {
4484 Parser.EatToEndOfStatement();
4490 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4491 SMLoc Loc = getLexer().getLoc();
4492 Parser.EatToEndOfStatement();
4493 return Error(Loc, "unexpected token in argument list");
4496 Parser.Lex(); // Consume the EndOfStatement
4498 // Some instructions, mostly Thumb, have forms for the same mnemonic that
4499 // do and don't have a cc_out optional-def operand. With some spot-checks
4500 // of the operand list, we can figure out which variant we're trying to
4501 // parse and adjust accordingly before actually matching. We shouldn't ever
4502 // try to remove a cc_out operand that was explicitly set on the the
4503 // mnemonic, of course (CarrySetting == true). Reason number #317 the
4504 // table driven matcher doesn't fit well with the ARM instruction set.
4505 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
4506 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4507 Operands.erase(Operands.begin() + 1);
4511 // ARM mode 'blx' need special handling, as the register operand version
4512 // is predicable, but the label operand version is not. So, we can't rely
4513 // on the Mnemonic based checking to correctly figure out when to put
4514 // a k_CondCode operand in the list. If we're trying to match the label
4515 // version, remove the k_CondCode operand here.
4516 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
4517 static_cast<ARMOperand*>(Operands[2])->isImm()) {
4518 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
4519 Operands.erase(Operands.begin() + 1);
4523 // The vector-compare-to-zero instructions have a literal token "#0" at
4524 // the end that comes to here as an immediate operand. Convert it to a
4525 // token to play nicely with the matcher.
4526 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
4527 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
4528 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4529 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4530 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4531 if (CE && CE->getValue() == 0) {
4532 Operands.erase(Operands.begin() + 5);
4533 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4537 // VCMP{E} does the same thing, but with a different operand count.
4538 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
4539 static_cast<ARMOperand*>(Operands[4])->isImm()) {
4540 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
4541 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4542 if (CE && CE->getValue() == 0) {
4543 Operands.erase(Operands.begin() + 4);
4544 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4548 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
4549 // end. Convert it to a token here.
4550 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
4551 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4552 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
4553 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
4554 if (CE && CE->getValue() == 0) {
4555 Operands.erase(Operands.begin() + 5);
4556 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
4564 // Validate context-sensitive operand constraints.
4566 // return 'true' if register list contains non-low GPR registers,
4567 // 'false' otherwise. If Reg is in the register list or is HiReg, set
4568 // 'containsReg' to true.
4569 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
4570 unsigned HiReg, bool &containsReg) {
4571 containsReg = false;
4572 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4573 unsigned OpReg = Inst.getOperand(i).getReg();
4576 // Anything other than a low register isn't legal here.
4577 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
4583 // Check if the specified regisgter is in the register list of the inst,
4584 // starting at the indicated operand number.
4585 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
4586 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
4587 unsigned OpReg = Inst.getOperand(i).getReg();
4594 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
4595 // the ARMInsts array) instead. Getting that here requires awkward
4596 // API changes, though. Better way?
4598 extern const MCInstrDesc ARMInsts[];
4600 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
4601 return ARMInsts[Opcode];
4604 // FIXME: We would really like to be able to tablegen'erate this.
4606 validateInstruction(MCInst &Inst,
4607 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4608 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
4609 SMLoc Loc = Operands[0]->getStartLoc();
4610 // Check the IT block state first.
4611 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
4612 // being allowed in IT blocks, but not being predicable. It just always
4614 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
4616 if (ITState.FirstCond)
4617 ITState.FirstCond = false;
4619 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
4620 // The instruction must be predicable.
4621 if (!MCID.isPredicable())
4622 return Error(Loc, "instructions in IT block must be predicable");
4623 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
4624 unsigned ITCond = bit ? ITState.Cond :
4625 ARMCC::getOppositeCondition(ITState.Cond);
4626 if (Cond != ITCond) {
4627 // Find the condition code Operand to get its SMLoc information.
4629 for (unsigned i = 1; i < Operands.size(); ++i)
4630 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
4631 CondLoc = Operands[i]->getStartLoc();
4632 return Error(CondLoc, "incorrect condition in IT block; got '" +
4633 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
4634 "', but expected '" +
4635 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
4637 // Check for non-'al' condition codes outside of the IT block.
4638 } else if (isThumbTwo() && MCID.isPredicable() &&
4639 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
4640 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
4641 Inst.getOpcode() != ARM::t2B)
4642 return Error(Loc, "predicated instructions must be in IT block");
4644 switch (Inst.getOpcode()) {
4647 case ARM::LDRD_POST:
4649 // Rt2 must be Rt + 1.
4650 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4651 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4653 return Error(Operands[3]->getStartLoc(),
4654 "destination operands must be sequential");
4658 // Rt2 must be Rt + 1.
4659 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
4660 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4662 return Error(Operands[3]->getStartLoc(),
4663 "source operands must be sequential");
4667 case ARM::STRD_POST:
4669 // Rt2 must be Rt + 1.
4670 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
4671 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
4673 return Error(Operands[3]->getStartLoc(),
4674 "source operands must be sequential");
4679 // width must be in range [1, 32-lsb]
4680 unsigned lsb = Inst.getOperand(2).getImm();
4681 unsigned widthm1 = Inst.getOperand(3).getImm();
4682 if (widthm1 >= 32 - lsb)
4683 return Error(Operands[5]->getStartLoc(),
4684 "bitfield width must be in range [1,32-lsb]");
4688 // If we're parsing Thumb2, the .w variant is available and handles
4689 // most cases that are normally illegal for a Thumb1 LDM
4690 // instruction. We'll make the transformation in processInstruction()
4693 // Thumb LDM instructions are writeback iff the base register is not
4694 // in the register list.
4695 unsigned Rn = Inst.getOperand(0).getReg();
4696 bool hasWritebackToken =
4697 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
4698 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
4699 bool listContainsBase;
4700 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
4701 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
4702 "registers must be in range r0-r7");
4703 // If we should have writeback, then there should be a '!' token.
4704 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
4705 return Error(Operands[2]->getStartLoc(),
4706 "writeback operator '!' expected");
4707 // If we should not have writeback, there must not be a '!'. This is
4708 // true even for the 32-bit wide encodings.
4709 if (listContainsBase && hasWritebackToken)
4710 return Error(Operands[3]->getStartLoc(),
4711 "writeback operator '!' not allowed when base register "
4712 "in register list");
4716 case ARM::t2LDMIA_UPD: {
4717 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
4718 return Error(Operands[4]->getStartLoc(),
4719 "writeback operator '!' not allowed when base register "
4720 "in register list");
4723 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
4724 // so only issue a diagnostic for thumb1. The instructions will be
4725 // switched to the t2 encodings in processInstruction() if necessary.
4727 bool listContainsBase;
4728 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
4730 return Error(Operands[2]->getStartLoc(),
4731 "registers must be in range r0-r7 or pc");
4735 bool listContainsBase;
4736 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
4738 return Error(Operands[2]->getStartLoc(),
4739 "registers must be in range r0-r7 or lr");
4742 case ARM::tSTMIA_UPD: {
4743 bool listContainsBase;
4744 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
4745 return Error(Operands[4]->getStartLoc(),
4746 "registers must be in range r0-r7");
4754 static unsigned getRealVSTLNOpcode(unsigned Opc) {
4756 default: assert(0 && "unexpected opcode!");
4757 case ARM::VST1LNdWB_fixed_Asm_8: return ARM::VST1LNd8_UPD;
4758 case ARM::VST1LNdWB_fixed_Asm_P8: return ARM::VST1LNd8_UPD;
4759 case ARM::VST1LNdWB_fixed_Asm_I8: return ARM::VST1LNd8_UPD;
4760 case ARM::VST1LNdWB_fixed_Asm_S8: return ARM::VST1LNd8_UPD;
4761 case ARM::VST1LNdWB_fixed_Asm_U8: return ARM::VST1LNd8_UPD;
4762 case ARM::VST1LNdWB_fixed_Asm_16: return ARM::VST1LNd16_UPD;
4763 case ARM::VST1LNdWB_fixed_Asm_P16: return ARM::VST1LNd16_UPD;
4764 case ARM::VST1LNdWB_fixed_Asm_I16: return ARM::VST1LNd16_UPD;
4765 case ARM::VST1LNdWB_fixed_Asm_S16: return ARM::VST1LNd16_UPD;
4766 case ARM::VST1LNdWB_fixed_Asm_U16: return ARM::VST1LNd16_UPD;
4767 case ARM::VST1LNdWB_fixed_Asm_32: return ARM::VST1LNd32_UPD;
4768 case ARM::VST1LNdWB_fixed_Asm_F: return ARM::VST1LNd32_UPD;
4769 case ARM::VST1LNdWB_fixed_Asm_F32: return ARM::VST1LNd32_UPD;
4770 case ARM::VST1LNdWB_fixed_Asm_I32: return ARM::VST1LNd32_UPD;
4771 case ARM::VST1LNdWB_fixed_Asm_S32: return ARM::VST1LNd32_UPD;
4772 case ARM::VST1LNdWB_fixed_Asm_U32: return ARM::VST1LNd32_UPD;
4773 case ARM::VST1LNdWB_register_Asm_8: return ARM::VST1LNd8_UPD;
4774 case ARM::VST1LNdWB_register_Asm_P8: return ARM::VST1LNd8_UPD;
4775 case ARM::VST1LNdWB_register_Asm_I8: return ARM::VST1LNd8_UPD;
4776 case ARM::VST1LNdWB_register_Asm_S8: return ARM::VST1LNd8_UPD;
4777 case ARM::VST1LNdWB_register_Asm_U8: return ARM::VST1LNd8_UPD;
4778 case ARM::VST1LNdWB_register_Asm_16: return ARM::VST1LNd16_UPD;
4779 case ARM::VST1LNdWB_register_Asm_P16: return ARM::VST1LNd16_UPD;
4780 case ARM::VST1LNdWB_register_Asm_I16: return ARM::VST1LNd16_UPD;
4781 case ARM::VST1LNdWB_register_Asm_S16: return ARM::VST1LNd16_UPD;
4782 case ARM::VST1LNdWB_register_Asm_U16: return ARM::VST1LNd16_UPD;
4783 case ARM::VST1LNdWB_register_Asm_32: return ARM::VST1LNd32_UPD;
4784 case ARM::VST1LNdWB_register_Asm_F: return ARM::VST1LNd32_UPD;
4785 case ARM::VST1LNdWB_register_Asm_F32: return ARM::VST1LNd32_UPD;
4786 case ARM::VST1LNdWB_register_Asm_I32: return ARM::VST1LNd32_UPD;
4787 case ARM::VST1LNdWB_register_Asm_S32: return ARM::VST1LNd32_UPD;
4788 case ARM::VST1LNdWB_register_Asm_U32: return ARM::VST1LNd32_UPD;
4789 case ARM::VST1LNdAsm_8: return ARM::VST1LNd8;
4790 case ARM::VST1LNdAsm_P8: return ARM::VST1LNd8;
4791 case ARM::VST1LNdAsm_I8: return ARM::VST1LNd8;
4792 case ARM::VST1LNdAsm_S8: return ARM::VST1LNd8;
4793 case ARM::VST1LNdAsm_U8: return ARM::VST1LNd8;
4794 case ARM::VST1LNdAsm_16: return ARM::VST1LNd16;
4795 case ARM::VST1LNdAsm_P16: return ARM::VST1LNd16;
4796 case ARM::VST1LNdAsm_I16: return ARM::VST1LNd16;
4797 case ARM::VST1LNdAsm_S16: return ARM::VST1LNd16;
4798 case ARM::VST1LNdAsm_U16: return ARM::VST1LNd16;
4799 case ARM::VST1LNdAsm_32: return ARM::VST1LNd32;
4800 case ARM::VST1LNdAsm_F: return ARM::VST1LNd32;
4801 case ARM::VST1LNdAsm_F32: return ARM::VST1LNd32;
4802 case ARM::VST1LNdAsm_I32: return ARM::VST1LNd32;
4803 case ARM::VST1LNdAsm_S32: return ARM::VST1LNd32;
4804 case ARM::VST1LNdAsm_U32: return ARM::VST1LNd32;
4808 static unsigned getRealVLDLNOpcode(unsigned Opc) {
4810 default: assert(0 && "unexpected opcode!");
4811 case ARM::VLD1LNdWB_fixed_Asm_8: return ARM::VLD1LNd8_UPD;
4812 case ARM::VLD1LNdWB_fixed_Asm_P8: return ARM::VLD1LNd8_UPD;
4813 case ARM::VLD1LNdWB_fixed_Asm_I8: return ARM::VLD1LNd8_UPD;
4814 case ARM::VLD1LNdWB_fixed_Asm_S8: return ARM::VLD1LNd8_UPD;
4815 case ARM::VLD1LNdWB_fixed_Asm_U8: return ARM::VLD1LNd8_UPD;
4816 case ARM::VLD1LNdWB_fixed_Asm_16: return ARM::VLD1LNd16_UPD;
4817 case ARM::VLD1LNdWB_fixed_Asm_P16: return ARM::VLD1LNd16_UPD;
4818 case ARM::VLD1LNdWB_fixed_Asm_I16: return ARM::VLD1LNd16_UPD;
4819 case ARM::VLD1LNdWB_fixed_Asm_S16: return ARM::VLD1LNd16_UPD;
4820 case ARM::VLD1LNdWB_fixed_Asm_U16: return ARM::VLD1LNd16_UPD;
4821 case ARM::VLD1LNdWB_fixed_Asm_32: return ARM::VLD1LNd32_UPD;
4822 case ARM::VLD1LNdWB_fixed_Asm_F: return ARM::VLD1LNd32_UPD;
4823 case ARM::VLD1LNdWB_fixed_Asm_F32: return ARM::VLD1LNd32_UPD;
4824 case ARM::VLD1LNdWB_fixed_Asm_I32: return ARM::VLD1LNd32_UPD;
4825 case ARM::VLD1LNdWB_fixed_Asm_S32: return ARM::VLD1LNd32_UPD;
4826 case ARM::VLD1LNdWB_fixed_Asm_U32: return ARM::VLD1LNd32_UPD;
4827 case ARM::VLD1LNdWB_register_Asm_8: return ARM::VLD1LNd8_UPD;
4828 case ARM::VLD1LNdWB_register_Asm_P8: return ARM::VLD1LNd8_UPD;
4829 case ARM::VLD1LNdWB_register_Asm_I8: return ARM::VLD1LNd8_UPD;
4830 case ARM::VLD1LNdWB_register_Asm_S8: return ARM::VLD1LNd8_UPD;
4831 case ARM::VLD1LNdWB_register_Asm_U8: return ARM::VLD1LNd8_UPD;
4832 case ARM::VLD1LNdWB_register_Asm_16: return ARM::VLD1LNd16_UPD;
4833 case ARM::VLD1LNdWB_register_Asm_P16: return ARM::VLD1LNd16_UPD;
4834 case ARM::VLD1LNdWB_register_Asm_I16: return ARM::VLD1LNd16_UPD;
4835 case ARM::VLD1LNdWB_register_Asm_S16: return ARM::VLD1LNd16_UPD;
4836 case ARM::VLD1LNdWB_register_Asm_U16: return ARM::VLD1LNd16_UPD;
4837 case ARM::VLD1LNdWB_register_Asm_32: return ARM::VLD1LNd32_UPD;
4838 case ARM::VLD1LNdWB_register_Asm_F: return ARM::VLD1LNd32_UPD;
4839 case ARM::VLD1LNdWB_register_Asm_F32: return ARM::VLD1LNd32_UPD;
4840 case ARM::VLD1LNdWB_register_Asm_I32: return ARM::VLD1LNd32_UPD;
4841 case ARM::VLD1LNdWB_register_Asm_S32: return ARM::VLD1LNd32_UPD;
4842 case ARM::VLD1LNdWB_register_Asm_U32: return ARM::VLD1LNd32_UPD;
4843 case ARM::VLD1LNdAsm_8: return ARM::VLD1LNd8;
4844 case ARM::VLD1LNdAsm_P8: return ARM::VLD1LNd8;
4845 case ARM::VLD1LNdAsm_I8: return ARM::VLD1LNd8;
4846 case ARM::VLD1LNdAsm_S8: return ARM::VLD1LNd8;
4847 case ARM::VLD1LNdAsm_U8: return ARM::VLD1LNd8;
4848 case ARM::VLD1LNdAsm_16: return ARM::VLD1LNd16;
4849 case ARM::VLD1LNdAsm_P16: return ARM::VLD1LNd16;
4850 case ARM::VLD1LNdAsm_I16: return ARM::VLD1LNd16;
4851 case ARM::VLD1LNdAsm_S16: return ARM::VLD1LNd16;
4852 case ARM::VLD1LNdAsm_U16: return ARM::VLD1LNd16;
4853 case ARM::VLD1LNdAsm_32: return ARM::VLD1LNd32;
4854 case ARM::VLD1LNdAsm_F: return ARM::VLD1LNd32;
4855 case ARM::VLD1LNdAsm_F32: return ARM::VLD1LNd32;
4856 case ARM::VLD1LNdAsm_I32: return ARM::VLD1LNd32;
4857 case ARM::VLD1LNdAsm_S32: return ARM::VLD1LNd32;
4858 case ARM::VLD1LNdAsm_U32: return ARM::VLD1LNd32;
4863 processInstruction(MCInst &Inst,
4864 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4865 switch (Inst.getOpcode()) {
4866 // Handle NEON VST1 complex aliases.
4867 case ARM::VST1LNdWB_register_Asm_8:
4868 case ARM::VST1LNdWB_register_Asm_P8:
4869 case ARM::VST1LNdWB_register_Asm_I8:
4870 case ARM::VST1LNdWB_register_Asm_S8:
4871 case ARM::VST1LNdWB_register_Asm_U8:
4872 case ARM::VST1LNdWB_register_Asm_16:
4873 case ARM::VST1LNdWB_register_Asm_P16:
4874 case ARM::VST1LNdWB_register_Asm_I16:
4875 case ARM::VST1LNdWB_register_Asm_S16:
4876 case ARM::VST1LNdWB_register_Asm_U16:
4877 case ARM::VST1LNdWB_register_Asm_32:
4878 case ARM::VST1LNdWB_register_Asm_F:
4879 case ARM::VST1LNdWB_register_Asm_F32:
4880 case ARM::VST1LNdWB_register_Asm_I32:
4881 case ARM::VST1LNdWB_register_Asm_S32:
4882 case ARM::VST1LNdWB_register_Asm_U32: {
4884 // Shuffle the operands around so the lane index operand is in the
4886 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
4887 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
4888 TmpInst.addOperand(Inst.getOperand(2)); // Rn
4889 TmpInst.addOperand(Inst.getOperand(3)); // alignment
4890 TmpInst.addOperand(Inst.getOperand(4)); // Rm
4891 TmpInst.addOperand(Inst.getOperand(0)); // Vd
4892 TmpInst.addOperand(Inst.getOperand(1)); // lane
4893 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
4894 TmpInst.addOperand(Inst.getOperand(6));
4898 case ARM::VST1LNdWB_fixed_Asm_8:
4899 case ARM::VST1LNdWB_fixed_Asm_P8:
4900 case ARM::VST1LNdWB_fixed_Asm_I8:
4901 case ARM::VST1LNdWB_fixed_Asm_S8:
4902 case ARM::VST1LNdWB_fixed_Asm_U8:
4903 case ARM::VST1LNdWB_fixed_Asm_16:
4904 case ARM::VST1LNdWB_fixed_Asm_P16:
4905 case ARM::VST1LNdWB_fixed_Asm_I16:
4906 case ARM::VST1LNdWB_fixed_Asm_S16:
4907 case ARM::VST1LNdWB_fixed_Asm_U16:
4908 case ARM::VST1LNdWB_fixed_Asm_32:
4909 case ARM::VST1LNdWB_fixed_Asm_F:
4910 case ARM::VST1LNdWB_fixed_Asm_F32:
4911 case ARM::VST1LNdWB_fixed_Asm_I32:
4912 case ARM::VST1LNdWB_fixed_Asm_S32:
4913 case ARM::VST1LNdWB_fixed_Asm_U32: {
4915 // Shuffle the operands around so the lane index operand is in the
4917 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
4918 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
4919 TmpInst.addOperand(Inst.getOperand(2)); // Rn
4920 TmpInst.addOperand(Inst.getOperand(3)); // alignment
4921 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
4922 TmpInst.addOperand(Inst.getOperand(0)); // Vd
4923 TmpInst.addOperand(Inst.getOperand(1)); // lane
4924 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
4925 TmpInst.addOperand(Inst.getOperand(5));
4929 case ARM::VST1LNdAsm_8:
4930 case ARM::VST1LNdAsm_P8:
4931 case ARM::VST1LNdAsm_I8:
4932 case ARM::VST1LNdAsm_S8:
4933 case ARM::VST1LNdAsm_U8:
4934 case ARM::VST1LNdAsm_16:
4935 case ARM::VST1LNdAsm_P16:
4936 case ARM::VST1LNdAsm_I16:
4937 case ARM::VST1LNdAsm_S16:
4938 case ARM::VST1LNdAsm_U16:
4939 case ARM::VST1LNdAsm_32:
4940 case ARM::VST1LNdAsm_F:
4941 case ARM::VST1LNdAsm_F32:
4942 case ARM::VST1LNdAsm_I32:
4943 case ARM::VST1LNdAsm_S32:
4944 case ARM::VST1LNdAsm_U32: {
4946 // Shuffle the operands around so the lane index operand is in the
4948 TmpInst.setOpcode(getRealVSTLNOpcode(Inst.getOpcode()));
4949 TmpInst.addOperand(Inst.getOperand(2)); // Rn
4950 TmpInst.addOperand(Inst.getOperand(3)); // alignment
4951 TmpInst.addOperand(Inst.getOperand(0)); // Vd
4952 TmpInst.addOperand(Inst.getOperand(1)); // lane
4953 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
4954 TmpInst.addOperand(Inst.getOperand(5));
4958 // Handle NEON VLD1 complex aliases.
4959 case ARM::VLD1LNdWB_register_Asm_8:
4960 case ARM::VLD1LNdWB_register_Asm_P8:
4961 case ARM::VLD1LNdWB_register_Asm_I8:
4962 case ARM::VLD1LNdWB_register_Asm_S8:
4963 case ARM::VLD1LNdWB_register_Asm_U8:
4964 case ARM::VLD1LNdWB_register_Asm_16:
4965 case ARM::VLD1LNdWB_register_Asm_P16:
4966 case ARM::VLD1LNdWB_register_Asm_I16:
4967 case ARM::VLD1LNdWB_register_Asm_S16:
4968 case ARM::VLD1LNdWB_register_Asm_U16:
4969 case ARM::VLD1LNdWB_register_Asm_32:
4970 case ARM::VLD1LNdWB_register_Asm_F:
4971 case ARM::VLD1LNdWB_register_Asm_F32:
4972 case ARM::VLD1LNdWB_register_Asm_I32:
4973 case ARM::VLD1LNdWB_register_Asm_S32:
4974 case ARM::VLD1LNdWB_register_Asm_U32: {
4976 // Shuffle the operands around so the lane index operand is in the
4978 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
4979 TmpInst.addOperand(Inst.getOperand(0)); // Vd
4980 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
4981 TmpInst.addOperand(Inst.getOperand(2)); // Rn
4982 TmpInst.addOperand(Inst.getOperand(3)); // alignment
4983 TmpInst.addOperand(Inst.getOperand(4)); // Rm
4984 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
4985 TmpInst.addOperand(Inst.getOperand(1)); // lane
4986 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
4987 TmpInst.addOperand(Inst.getOperand(6));
4991 case ARM::VLD1LNdWB_fixed_Asm_8:
4992 case ARM::VLD1LNdWB_fixed_Asm_P8:
4993 case ARM::VLD1LNdWB_fixed_Asm_I8:
4994 case ARM::VLD1LNdWB_fixed_Asm_S8:
4995 case ARM::VLD1LNdWB_fixed_Asm_U8:
4996 case ARM::VLD1LNdWB_fixed_Asm_16:
4997 case ARM::VLD1LNdWB_fixed_Asm_P16:
4998 case ARM::VLD1LNdWB_fixed_Asm_I16:
4999 case ARM::VLD1LNdWB_fixed_Asm_S16:
5000 case ARM::VLD1LNdWB_fixed_Asm_U16:
5001 case ARM::VLD1LNdWB_fixed_Asm_32:
5002 case ARM::VLD1LNdWB_fixed_Asm_F:
5003 case ARM::VLD1LNdWB_fixed_Asm_F32:
5004 case ARM::VLD1LNdWB_fixed_Asm_I32:
5005 case ARM::VLD1LNdWB_fixed_Asm_S32:
5006 case ARM::VLD1LNdWB_fixed_Asm_U32: {
5008 // Shuffle the operands around so the lane index operand is in the
5010 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
5011 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5012 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5013 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5014 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5015 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5016 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5017 TmpInst.addOperand(Inst.getOperand(1)); // lane
5018 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5019 TmpInst.addOperand(Inst.getOperand(5));
5023 case ARM::VLD1LNdAsm_8:
5024 case ARM::VLD1LNdAsm_P8:
5025 case ARM::VLD1LNdAsm_I8:
5026 case ARM::VLD1LNdAsm_S8:
5027 case ARM::VLD1LNdAsm_U8:
5028 case ARM::VLD1LNdAsm_16:
5029 case ARM::VLD1LNdAsm_P16:
5030 case ARM::VLD1LNdAsm_I16:
5031 case ARM::VLD1LNdAsm_S16:
5032 case ARM::VLD1LNdAsm_U16:
5033 case ARM::VLD1LNdAsm_32:
5034 case ARM::VLD1LNdAsm_F:
5035 case ARM::VLD1LNdAsm_F32:
5036 case ARM::VLD1LNdAsm_I32:
5037 case ARM::VLD1LNdAsm_S32:
5038 case ARM::VLD1LNdAsm_U32: {
5040 // Shuffle the operands around so the lane index operand is in the
5042 TmpInst.setOpcode(getRealVLDLNOpcode(Inst.getOpcode()));
5043 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5044 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5045 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5046 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
5047 TmpInst.addOperand(Inst.getOperand(1)); // lane
5048 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5049 TmpInst.addOperand(Inst.getOperand(5));
5053 // Handle the MOV complex aliases.
5058 ARM_AM::ShiftOpc ShiftTy;
5059 switch(Inst.getOpcode()) {
5060 default: llvm_unreachable("unexpected opcode!");
5061 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
5062 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
5063 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
5064 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
5066 // A shift by zero is a plain MOVr, not a MOVsi.
5067 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
5069 TmpInst.setOpcode(ARM::MOVsr);
5070 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5071 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5072 TmpInst.addOperand(Inst.getOperand(2)); // Rm
5073 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5074 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5075 TmpInst.addOperand(Inst.getOperand(4));
5076 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
5084 ARM_AM::ShiftOpc ShiftTy;
5085 switch(Inst.getOpcode()) {
5086 default: llvm_unreachable("unexpected opcode!");
5087 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
5088 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
5089 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
5090 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
5092 // A shift by zero is a plain MOVr, not a MOVsi.
5093 unsigned Amt = Inst.getOperand(2).getImm();
5094 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
5095 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
5097 TmpInst.setOpcode(Opc);
5098 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5099 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5100 if (Opc == ARM::MOVsi)
5101 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5102 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
5103 TmpInst.addOperand(Inst.getOperand(4));
5104 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
5109 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
5111 TmpInst.setOpcode(ARM::MOVsi);
5112 TmpInst.addOperand(Inst.getOperand(0)); // Rd
5113 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5114 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
5115 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5116 TmpInst.addOperand(Inst.getOperand(3));
5117 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
5121 case ARM::t2LDMIA_UPD: {
5122 // If this is a load of a single register, then we should use
5123 // a post-indexed LDR instruction instead, per the ARM ARM.
5124 if (Inst.getNumOperands() != 5)
5127 TmpInst.setOpcode(ARM::t2LDR_POST);
5128 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5129 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5130 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5131 TmpInst.addOperand(MCOperand::CreateImm(4));
5132 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5133 TmpInst.addOperand(Inst.getOperand(3));
5137 case ARM::t2STMDB_UPD: {
5138 // If this is a store of a single register, then we should use
5139 // a pre-indexed STR instruction instead, per the ARM ARM.
5140 if (Inst.getNumOperands() != 5)
5143 TmpInst.setOpcode(ARM::t2STR_PRE);
5144 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5145 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5146 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5147 TmpInst.addOperand(MCOperand::CreateImm(-4));
5148 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5149 TmpInst.addOperand(Inst.getOperand(3));
5153 case ARM::LDMIA_UPD:
5154 // If this is a load of a single register via a 'pop', then we should use
5155 // a post-indexed LDR instruction instead, per the ARM ARM.
5156 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
5157 Inst.getNumOperands() == 5) {
5159 TmpInst.setOpcode(ARM::LDR_POST_IMM);
5160 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5161 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5162 TmpInst.addOperand(Inst.getOperand(1)); // Rn
5163 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
5164 TmpInst.addOperand(MCOperand::CreateImm(4));
5165 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5166 TmpInst.addOperand(Inst.getOperand(3));
5171 case ARM::STMDB_UPD:
5172 // If this is a store of a single register via a 'push', then we should use
5173 // a pre-indexed STR instruction instead, per the ARM ARM.
5174 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
5175 Inst.getNumOperands() == 5) {
5177 TmpInst.setOpcode(ARM::STR_PRE_IMM);
5178 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
5179 TmpInst.addOperand(Inst.getOperand(4)); // Rt
5180 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
5181 TmpInst.addOperand(MCOperand::CreateImm(-4));
5182 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
5183 TmpInst.addOperand(Inst.getOperand(3));
5188 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
5189 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
5190 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
5191 // to encoding T1 if <Rd> is omitted."
5192 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
5193 Inst.setOpcode(ARM::tADDi3);
5198 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
5199 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
5200 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
5201 // to encoding T1 if <Rd> is omitted."
5202 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
5203 Inst.setOpcode(ARM::tSUBi3);
5208 // A Thumb conditional branch outside of an IT block is a tBcc.
5209 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
5210 Inst.setOpcode(ARM::tBcc);
5215 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
5216 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
5217 Inst.setOpcode(ARM::t2Bcc);
5222 // If the conditional is AL or we're in an IT block, we really want t2B.
5223 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
5224 Inst.setOpcode(ARM::t2B);
5229 // If the conditional is AL, we really want tB.
5230 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
5231 Inst.setOpcode(ARM::tB);
5236 // If the register list contains any high registers, or if the writeback
5237 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
5238 // instead if we're in Thumb2. Otherwise, this should have generated
5239 // an error in validateInstruction().
5240 unsigned Rn = Inst.getOperand(0).getReg();
5241 bool hasWritebackToken =
5242 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5243 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5244 bool listContainsBase;
5245 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
5246 (!listContainsBase && !hasWritebackToken) ||
5247 (listContainsBase && hasWritebackToken)) {
5248 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
5249 assert (isThumbTwo());
5250 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
5251 // If we're switching to the updating version, we need to insert
5252 // the writeback tied operand.
5253 if (hasWritebackToken)
5254 Inst.insert(Inst.begin(),
5255 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
5260 case ARM::tSTMIA_UPD: {
5261 // If the register list contains any high registers, we need to use
5262 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
5263 // should have generated an error in validateInstruction().
5264 unsigned Rn = Inst.getOperand(0).getReg();
5265 bool listContainsBase;
5266 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
5267 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
5268 assert (isThumbTwo());
5269 Inst.setOpcode(ARM::t2STMIA_UPD);
5275 bool listContainsBase;
5276 // If the register list contains any high registers, we need to use
5277 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
5278 // should have generated an error in validateInstruction().
5279 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
5281 assert (isThumbTwo());
5282 Inst.setOpcode(ARM::t2LDMIA_UPD);
5283 // Add the base register and writeback operands.
5284 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
5285 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
5289 bool listContainsBase;
5290 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
5292 assert (isThumbTwo());
5293 Inst.setOpcode(ARM::t2STMDB_UPD);
5294 // Add the base register and writeback operands.
5295 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
5296 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
5300 // If we can use the 16-bit encoding and the user didn't explicitly
5301 // request the 32-bit variant, transform it here.
5302 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5303 Inst.getOperand(1).getImm() <= 255 &&
5304 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
5305 Inst.getOperand(4).getReg() == ARM::CPSR) ||
5306 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
5307 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
5308 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
5309 // The operands aren't in the same order for tMOVi8...
5311 TmpInst.setOpcode(ARM::tMOVi8);
5312 TmpInst.addOperand(Inst.getOperand(0));
5313 TmpInst.addOperand(Inst.getOperand(4));
5314 TmpInst.addOperand(Inst.getOperand(1));
5315 TmpInst.addOperand(Inst.getOperand(2));
5316 TmpInst.addOperand(Inst.getOperand(3));
5323 // If we can use the 16-bit encoding and the user didn't explicitly
5324 // request the 32-bit variant, transform it here.
5325 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5326 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5327 Inst.getOperand(2).getImm() == ARMCC::AL &&
5328 Inst.getOperand(4).getReg() == ARM::CPSR &&
5329 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
5330 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
5331 // The operands aren't the same for tMOV[S]r... (no cc_out)
5333 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
5334 TmpInst.addOperand(Inst.getOperand(0));
5335 TmpInst.addOperand(Inst.getOperand(1));
5336 TmpInst.addOperand(Inst.getOperand(2));
5337 TmpInst.addOperand(Inst.getOperand(3));
5347 // If we can use the 16-bit encoding and the user didn't explicitly
5348 // request the 32-bit variant, transform it here.
5349 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
5350 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5351 Inst.getOperand(2).getImm() == 0 &&
5352 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
5353 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
5355 switch (Inst.getOpcode()) {
5356 default: llvm_unreachable("Illegal opcode!");
5357 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
5358 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
5359 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
5360 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
5362 // The operands aren't the same for thumb1 (no rotate operand).
5364 TmpInst.setOpcode(NewOpc);
5365 TmpInst.addOperand(Inst.getOperand(0));
5366 TmpInst.addOperand(Inst.getOperand(1));
5367 TmpInst.addOperand(Inst.getOperand(3));
5368 TmpInst.addOperand(Inst.getOperand(4));
5375 // The mask bits for all but the first condition are represented as
5376 // the low bit of the condition code value implies 't'. We currently
5377 // always have 1 implies 't', so XOR toggle the bits if the low bit
5378 // of the condition code is zero. The encoding also expects the low
5379 // bit of the condition to be encoded as bit 4 of the mask operand,
5380 // so mask that in if needed
5381 MCOperand &MO = Inst.getOperand(1);
5382 unsigned Mask = MO.getImm();
5383 unsigned OrigMask = Mask;
5384 unsigned TZ = CountTrailingZeros_32(Mask);
5385 if ((Inst.getOperand(0).getImm() & 1) == 0) {
5386 assert(Mask && TZ <= 3 && "illegal IT mask value!");
5387 for (unsigned i = 3; i != TZ; --i)
5393 // Set up the IT block state according to the IT instruction we just
5395 assert(!inITBlock() && "nested IT blocks?!");
5396 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
5397 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
5398 ITState.CurPosition = 0;
5399 ITState.FirstCond = true;
5406 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
5407 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
5408 // suffix depending on whether they're in an IT block or not.
5409 unsigned Opc = Inst.getOpcode();
5410 const MCInstrDesc &MCID = getInstDesc(Opc);
5411 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
5412 assert(MCID.hasOptionalDef() &&
5413 "optionally flag setting instruction missing optional def operand");
5414 assert(MCID.NumOperands == Inst.getNumOperands() &&
5415 "operand count mismatch!");
5416 // Find the optional-def operand (cc_out).
5419 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
5422 // If we're parsing Thumb1, reject it completely.
5423 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
5424 return Match_MnemonicFail;
5425 // If we're parsing Thumb2, which form is legal depends on whether we're
5427 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
5429 return Match_RequiresITBlock;
5430 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
5432 return Match_RequiresNotITBlock;
5434 // Some high-register supporting Thumb1 encodings only allow both registers
5435 // to be from r0-r7 when in Thumb2.
5436 else if (Opc == ARM::tADDhirr && isThumbOne() &&
5437 isARMLowRegister(Inst.getOperand(1).getReg()) &&
5438 isARMLowRegister(Inst.getOperand(2).getReg()))
5439 return Match_RequiresThumb2;
5440 // Others only require ARMv6 or later.
5441 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
5442 isARMLowRegister(Inst.getOperand(0).getReg()) &&
5443 isARMLowRegister(Inst.getOperand(1).getReg()))
5444 return Match_RequiresV6;
5445 return Match_Success;
5449 MatchAndEmitInstruction(SMLoc IDLoc,
5450 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
5454 unsigned MatchResult;
5455 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
5456 switch (MatchResult) {
5459 // Context sensitive operand constraints aren't handled by the matcher,
5460 // so check them here.
5461 if (validateInstruction(Inst, Operands)) {
5462 // Still progress the IT block, otherwise one wrong condition causes
5463 // nasty cascading errors.
5464 forwardITPosition();
5468 // Some instructions need post-processing to, for example, tweak which
5469 // encoding is selected. Loop on it while changes happen so the
5470 // individual transformations can chain off each other. E.g.,
5471 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
5472 while (processInstruction(Inst, Operands))
5475 // Only move forward at the very end so that everything in validate
5476 // and process gets a consistent answer about whether we're in an IT
5478 forwardITPosition();
5480 Out.EmitInstruction(Inst);
5482 case Match_MissingFeature:
5483 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
5485 case Match_InvalidOperand: {
5486 SMLoc ErrorLoc = IDLoc;
5487 if (ErrorInfo != ~0U) {
5488 if (ErrorInfo >= Operands.size())
5489 return Error(IDLoc, "too few operands for instruction");
5491 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
5492 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
5495 return Error(ErrorLoc, "invalid operand for instruction");
5497 case Match_MnemonicFail:
5498 return Error(IDLoc, "invalid instruction");
5499 case Match_ConversionFail:
5500 // The converter function will have already emited a diagnostic.
5502 case Match_RequiresNotITBlock:
5503 return Error(IDLoc, "flag setting instruction only valid outside IT block");
5504 case Match_RequiresITBlock:
5505 return Error(IDLoc, "instruction only valid inside IT block");
5506 case Match_RequiresV6:
5507 return Error(IDLoc, "instruction variant requires ARMv6 or later");
5508 case Match_RequiresThumb2:
5509 return Error(IDLoc, "instruction variant requires Thumb2");
5512 llvm_unreachable("Implement any new match types added!");
5516 /// parseDirective parses the arm specific directives
5517 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
5518 StringRef IDVal = DirectiveID.getIdentifier();
5519 if (IDVal == ".word")
5520 return parseDirectiveWord(4, DirectiveID.getLoc());
5521 else if (IDVal == ".thumb")
5522 return parseDirectiveThumb(DirectiveID.getLoc());
5523 else if (IDVal == ".thumb_func")
5524 return parseDirectiveThumbFunc(DirectiveID.getLoc());
5525 else if (IDVal == ".code")
5526 return parseDirectiveCode(DirectiveID.getLoc());
5527 else if (IDVal == ".syntax")
5528 return parseDirectiveSyntax(DirectiveID.getLoc());
5532 /// parseDirectiveWord
5533 /// ::= .word [ expression (, expression)* ]
5534 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
5535 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5537 const MCExpr *Value;
5538 if (getParser().ParseExpression(Value))
5541 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
5543 if (getLexer().is(AsmToken::EndOfStatement))
5546 // FIXME: Improve diagnostic.
5547 if (getLexer().isNot(AsmToken::Comma))
5548 return Error(L, "unexpected token in directive");
5557 /// parseDirectiveThumb
5559 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
5560 if (getLexer().isNot(AsmToken::EndOfStatement))
5561 return Error(L, "unexpected token in directive");
5564 // TODO: set thumb mode
5565 // TODO: tell the MC streamer the mode
5566 // getParser().getStreamer().Emit???();
5570 /// parseDirectiveThumbFunc
5571 /// ::= .thumbfunc symbol_name
5572 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
5573 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
5574 bool isMachO = MAI.hasSubsectionsViaSymbols();
5577 // Darwin asm has function name after .thumb_func direction
5580 const AsmToken &Tok = Parser.getTok();
5581 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
5582 return Error(L, "unexpected token in .thumb_func directive");
5583 Name = Tok.getIdentifier();
5584 Parser.Lex(); // Consume the identifier token.
5587 if (getLexer().isNot(AsmToken::EndOfStatement))
5588 return Error(L, "unexpected token in directive");
5591 // FIXME: assuming function name will be the line following .thumb_func
5593 Name = Parser.getTok().getIdentifier();
5596 // Mark symbol as a thumb symbol.
5597 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
5598 getParser().getStreamer().EmitThumbFunc(Func);
5602 /// parseDirectiveSyntax
5603 /// ::= .syntax unified | divided
5604 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
5605 const AsmToken &Tok = Parser.getTok();
5606 if (Tok.isNot(AsmToken::Identifier))
5607 return Error(L, "unexpected token in .syntax directive");
5608 StringRef Mode = Tok.getString();
5609 if (Mode == "unified" || Mode == "UNIFIED")
5611 else if (Mode == "divided" || Mode == "DIVIDED")
5612 return Error(L, "'.syntax divided' arm asssembly not supported");
5614 return Error(L, "unrecognized syntax mode in .syntax directive");
5616 if (getLexer().isNot(AsmToken::EndOfStatement))
5617 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5620 // TODO tell the MC streamer the mode
5621 // getParser().getStreamer().Emit???();
5625 /// parseDirectiveCode
5626 /// ::= .code 16 | 32
5627 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
5628 const AsmToken &Tok = Parser.getTok();
5629 if (Tok.isNot(AsmToken::Integer))
5630 return Error(L, "unexpected token in .code directive");
5631 int64_t Val = Parser.getTok().getIntVal();
5637 return Error(L, "invalid operand to .code directive");
5639 if (getLexer().isNot(AsmToken::EndOfStatement))
5640 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
5646 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
5650 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
5656 extern "C" void LLVMInitializeARMAsmLexer();
5658 /// Force static initialization.
5659 extern "C" void LLVMInitializeARMAsmParser() {
5660 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
5661 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
5662 LLVMInitializeARMAsmLexer();
5665 #define GET_REGISTER_MATCHER
5666 #define GET_MATCHER_IMPLEMENTATION
5667 #include "ARMGenAsmMatcher.inc"