1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMMCExpr.h"
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARMSubtarget.h"
15 #include "llvm/MC/MCParser/MCAsmLexer.h"
16 #include "llvm/MC/MCParser/MCAsmParser.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Target/TargetAsmParser.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/OwningPtr.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringExtras.h"
31 #include "llvm/ADT/StringSwitch.h"
32 #include "llvm/ADT/Twine.h"
40 class ARMAsmParser : public TargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
45 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
50 int TryParseRegister();
51 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
52 bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
53 int TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
54 bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
55 bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
56 ARMII::AddrMode AddrMode);
57 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
58 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
59 const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
60 MCSymbolRefExpr::VariantKind Variant);
63 bool ParseMemoryOffsetReg(bool &Negative,
64 bool &OffsetRegShifted,
65 enum ARM_AM::ShiftOpc &ShiftType,
66 const MCExpr *&ShiftAmount,
67 const MCExpr *&Offset,
71 bool ParseShift(enum ARM_AM::ShiftOpc &St,
72 const MCExpr *&ShiftAmount, SMLoc &E);
73 bool ParseDirectiveWord(unsigned Size, SMLoc L);
74 bool ParseDirectiveThumb(SMLoc L);
75 bool ParseDirectiveThumbFunc(SMLoc L);
76 bool ParseDirectiveCode(SMLoc L);
77 bool ParseDirectiveSyntax(SMLoc L);
79 bool MatchAndEmitInstruction(SMLoc IDLoc,
80 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
82 void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
83 bool &CanAcceptPredicationCode);
85 bool isThumb() const {
86 // FIXME: Can tablegen auto-generate this?
87 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
89 bool isThumbOne() const {
90 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
93 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
94 setAvailableFeatures(FB);
97 /// @name Auto-generated Match Functions
100 #define GET_ASSEMBLER_HEADER
101 #include "ARMGenAsmMatcher.inc"
105 OperandMatchResultTy tryParseCoprocNumOperand(
106 SmallVectorImpl<MCParsedAsmOperand*>&);
107 OperandMatchResultTy tryParseCoprocRegOperand(
108 SmallVectorImpl<MCParsedAsmOperand*>&);
109 OperandMatchResultTy tryParseMemBarrierOptOperand(
110 SmallVectorImpl<MCParsedAsmOperand*>&);
111 OperandMatchResultTy tryParseProcIFlagsOperand(
112 SmallVectorImpl<MCParsedAsmOperand*>&);
113 OperandMatchResultTy tryParseMSRMaskOperand(
114 SmallVectorImpl<MCParsedAsmOperand*>&);
115 OperandMatchResultTy tryParseMemMode2Operand(
116 SmallVectorImpl<MCParsedAsmOperand*>&);
117 OperandMatchResultTy tryParseMemMode3Operand(
118 SmallVectorImpl<MCParsedAsmOperand*>&);
120 // Asm Match Converter Methods
121 bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
122 const SmallVectorImpl<MCParsedAsmOperand*> &);
123 bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
124 const SmallVectorImpl<MCParsedAsmOperand*> &);
125 bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
126 const SmallVectorImpl<MCParsedAsmOperand*> &);
127 bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
128 const SmallVectorImpl<MCParsedAsmOperand*> &);
131 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
132 : TargetAsmParser(), STI(_STI), Parser(_Parser) {
133 MCAsmParserExtension::Initialize(_Parser);
135 // Initialize the set of available features.
136 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
139 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
140 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
141 virtual bool ParseDirective(AsmToken DirectiveID);
143 } // end anonymous namespace
147 /// ARMOperand - Instances of this class represent a parsed ARM machine
149 class ARMOperand : public MCParsedAsmOperand {
169 SMLoc StartLoc, EndLoc;
170 SmallVector<unsigned, 8> Registers;
174 ARMCC::CondCodes Val;
186 ARM_PROC::IFlags Val;
206 /// Combined record for all forms of ARM address expressions.
208 ARMII::AddrMode AddrMode;
211 unsigned RegNum; ///< Offset register num, when OffsetIsReg.
212 const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
214 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
215 enum ARM_AM::ShiftOpc ShiftType; // used when OffsetRegShifted is true
216 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
217 unsigned Preindexed : 1;
218 unsigned Postindexed : 1;
219 unsigned OffsetIsReg : 1;
220 unsigned Negative : 1; // only used when OffsetIsReg is true
221 unsigned Writeback : 1;
225 ARM_AM::ShiftOpc ShiftTy;
229 ARM_AM::ShiftOpc ShiftTy;
236 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
238 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
240 StartLoc = o.StartLoc;
254 case DPRRegisterList:
255 case SPRRegisterList:
256 Registers = o.Registers;
280 case ShiftedRegister:
281 ShiftedReg = o.ShiftedReg;
286 /// getStartLoc - Get the location of the first token of this operand.
287 SMLoc getStartLoc() const { return StartLoc; }
288 /// getEndLoc - Get the location of the last token of this operand.
289 SMLoc getEndLoc() const { return EndLoc; }
291 ARMCC::CondCodes getCondCode() const {
292 assert(Kind == CondCode && "Invalid access!");
296 unsigned getCoproc() const {
297 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
301 StringRef getToken() const {
302 assert(Kind == Token && "Invalid access!");
303 return StringRef(Tok.Data, Tok.Length);
306 unsigned getReg() const {
307 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
311 const SmallVectorImpl<unsigned> &getRegList() const {
312 assert((Kind == RegisterList || Kind == DPRRegisterList ||
313 Kind == SPRRegisterList) && "Invalid access!");
317 const MCExpr *getImm() const {
318 assert(Kind == Immediate && "Invalid access!");
322 ARM_MB::MemBOpt getMemBarrierOpt() const {
323 assert(Kind == MemBarrierOpt && "Invalid access!");
327 ARM_PROC::IFlags getProcIFlags() const {
328 assert(Kind == ProcIFlags && "Invalid access!");
332 unsigned getMSRMask() const {
333 assert(Kind == MSRMask && "Invalid access!");
337 /// @name Memory Operand Accessors
339 ARMII::AddrMode getMemAddrMode() const {
342 unsigned getMemBaseRegNum() const {
343 return Mem.BaseRegNum;
345 unsigned getMemOffsetRegNum() const {
346 assert(Mem.OffsetIsReg && "Invalid access!");
347 return Mem.Offset.RegNum;
349 const MCExpr *getMemOffset() const {
350 assert(!Mem.OffsetIsReg && "Invalid access!");
351 return Mem.Offset.Value;
353 unsigned getMemOffsetRegShifted() const {
354 assert(Mem.OffsetIsReg && "Invalid access!");
355 return Mem.OffsetRegShifted;
357 const MCExpr *getMemShiftAmount() const {
358 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
359 return Mem.ShiftAmount;
361 enum ARM_AM::ShiftOpc getMemShiftType() const {
362 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
363 return Mem.ShiftType;
365 bool getMemPreindexed() const { return Mem.Preindexed; }
366 bool getMemPostindexed() const { return Mem.Postindexed; }
367 bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; }
368 bool getMemNegative() const { return Mem.Negative; }
369 bool getMemWriteback() const { return Mem.Writeback; }
373 bool isCoprocNum() const { return Kind == CoprocNum; }
374 bool isCoprocReg() const { return Kind == CoprocReg; }
375 bool isCondCode() const { return Kind == CondCode; }
376 bool isCCOut() const { return Kind == CCOut; }
377 bool isImm() const { return Kind == Immediate; }
378 bool isImm0_255() const {
379 if (Kind != Immediate)
381 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
382 if (!CE) return false;
383 int64_t Value = CE->getValue();
384 return Value >= 0 && Value < 256;
386 bool isImm0_7() const {
387 if (Kind != Immediate)
389 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
390 if (!CE) return false;
391 int64_t Value = CE->getValue();
392 return Value >= 0 && Value < 8;
394 bool isImm0_15() const {
395 if (Kind != Immediate)
397 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
398 if (!CE) return false;
399 int64_t Value = CE->getValue();
400 return Value >= 0 && Value < 16;
402 bool isImm0_65535() const {
403 if (Kind != Immediate)
405 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
406 if (!CE) return false;
407 int64_t Value = CE->getValue();
408 return Value >= 0 && Value < 65536;
410 bool isARMSOImm() const {
411 if (Kind != Immediate)
413 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
414 if (!CE) return false;
415 int64_t Value = CE->getValue();
416 return ARM_AM::getSOImmVal(Value) != -1;
418 bool isT2SOImm() const {
419 if (Kind != Immediate)
421 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
422 if (!CE) return false;
423 int64_t Value = CE->getValue();
424 return ARM_AM::getT2SOImmVal(Value) != -1;
426 bool isReg() const { return Kind == Register; }
427 bool isRegList() const { return Kind == RegisterList; }
428 bool isDPRRegList() const { return Kind == DPRRegisterList; }
429 bool isSPRRegList() const { return Kind == SPRRegisterList; }
430 bool isToken() const { return Kind == Token; }
431 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
432 bool isMemory() const { return Kind == Memory; }
433 bool isShifter() const { return Kind == Shifter; }
434 bool isShiftedReg() const { return Kind == ShiftedRegister; }
435 bool isMemMode2() const {
436 if (getMemAddrMode() != ARMII::AddrMode2)
439 if (getMemOffsetIsReg())
442 if (getMemNegative() &&
443 !(getMemPostindexed() || getMemPreindexed()))
446 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
447 if (!CE) return false;
448 int64_t Value = CE->getValue();
450 // The offset must be in the range 0-4095 (imm12).
451 if (Value > 4095 || Value < -4095)
456 bool isMemMode3() const {
457 if (getMemAddrMode() != ARMII::AddrMode3)
460 if (getMemOffsetIsReg()) {
461 if (getMemOffsetRegShifted())
462 return false; // No shift with offset reg allowed
466 if (getMemNegative() &&
467 !(getMemPostindexed() || getMemPreindexed()))
470 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
471 if (!CE) return false;
472 int64_t Value = CE->getValue();
474 // The offset must be in the range 0-255 (imm8).
475 if (Value > 255 || Value < -255)
480 bool isMemMode5() const {
481 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
485 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
486 if (!CE) return false;
488 // The offset must be a multiple of 4 in the range 0-1020.
489 int64_t Value = CE->getValue();
490 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
492 bool isMemMode7() const {
494 getMemPreindexed() ||
495 getMemPostindexed() ||
496 getMemOffsetIsReg() ||
501 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
502 if (!CE) return false;
509 bool isMemModeRegThumb() const {
510 if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback())
514 bool isMemModeImmThumb() const {
515 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback())
518 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
519 if (!CE) return false;
521 // The offset must be a multiple of 4 in the range 0-124.
522 uint64_t Value = CE->getValue();
523 return ((Value & 0x3) == 0 && Value <= 124);
525 bool isMSRMask() const { return Kind == MSRMask; }
526 bool isProcIFlags() const { return Kind == ProcIFlags; }
528 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
529 // Add as immediates when possible. Null MCExpr = 0.
531 Inst.addOperand(MCOperand::CreateImm(0));
532 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
533 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
535 Inst.addOperand(MCOperand::CreateExpr(Expr));
538 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
539 assert(N == 2 && "Invalid number of operands!");
540 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
541 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
542 Inst.addOperand(MCOperand::CreateReg(RegNum));
545 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
546 assert(N == 1 && "Invalid number of operands!");
547 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
550 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
551 assert(N == 1 && "Invalid number of operands!");
552 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
555 void addCCOutOperands(MCInst &Inst, unsigned N) const {
556 assert(N == 1 && "Invalid number of operands!");
557 Inst.addOperand(MCOperand::CreateReg(getReg()));
560 void addRegOperands(MCInst &Inst, unsigned N) const {
561 assert(N == 1 && "Invalid number of operands!");
562 Inst.addOperand(MCOperand::CreateReg(getReg()));
565 void addShiftedRegOperands(MCInst &Inst, unsigned N) const {
566 assert(N == 3 && "Invalid number of operands!");
567 assert(isShiftedReg() && "addShiftedRegOperands() on non ShiftedReg!");
568 assert((ShiftedReg.ShiftReg == 0 ||
569 ARM_AM::getSORegOffset(ShiftedReg.ShiftImm) == 0) &&
570 "Invalid shifted register operand!");
571 Inst.addOperand(MCOperand::CreateReg(ShiftedReg.SrcReg));
572 Inst.addOperand(MCOperand::CreateReg(ShiftedReg.ShiftReg));
573 Inst.addOperand(MCOperand::CreateImm(
574 ARM_AM::getSORegOpc(ShiftedReg.ShiftTy, ShiftedReg.ShiftImm)));
577 void addShifterOperands(MCInst &Inst, unsigned N) const {
578 assert(N == 1 && "Invalid number of operands!");
579 Inst.addOperand(MCOperand::CreateImm(
580 ARM_AM::getSORegOpc(Shift.ShiftTy, 0)));
583 void addRegListOperands(MCInst &Inst, unsigned N) const {
584 assert(N == 1 && "Invalid number of operands!");
585 const SmallVectorImpl<unsigned> &RegList = getRegList();
586 for (SmallVectorImpl<unsigned>::const_iterator
587 I = RegList.begin(), E = RegList.end(); I != E; ++I)
588 Inst.addOperand(MCOperand::CreateReg(*I));
591 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
592 addRegListOperands(Inst, N);
595 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
596 addRegListOperands(Inst, N);
599 void addImmOperands(MCInst &Inst, unsigned N) const {
600 assert(N == 1 && "Invalid number of operands!");
601 addExpr(Inst, getImm());
604 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
605 assert(N == 1 && "Invalid number of operands!");
606 addExpr(Inst, getImm());
609 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
610 assert(N == 1 && "Invalid number of operands!");
611 addExpr(Inst, getImm());
614 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
615 assert(N == 1 && "Invalid number of operands!");
616 addExpr(Inst, getImm());
619 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
620 assert(N == 1 && "Invalid number of operands!");
621 addExpr(Inst, getImm());
624 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
625 assert(N == 1 && "Invalid number of operands!");
626 addExpr(Inst, getImm());
629 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
630 assert(N == 1 && "Invalid number of operands!");
631 addExpr(Inst, getImm());
634 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
635 assert(N == 1 && "Invalid number of operands!");
636 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
639 void addMemMode7Operands(MCInst &Inst, unsigned N) const {
640 assert(N == 1 && isMemMode7() && "Invalid number of operands!");
641 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
643 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
645 assert((CE || CE->getValue() == 0) &&
646 "No offset operand support in mode 7");
649 void addMemMode2Operands(MCInst &Inst, unsigned N) const {
650 assert(isMemMode2() && "Invalid mode or number of operands!");
651 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
652 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
654 if (getMemOffsetIsReg()) {
655 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
657 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
658 ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
659 int64_t ShiftAmount = 0;
661 if (getMemOffsetRegShifted()) {
662 ShOpc = getMemShiftType();
663 const MCConstantExpr *CE =
664 dyn_cast<MCConstantExpr>(getMemShiftAmount());
665 ShiftAmount = CE->getValue();
668 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
673 // Create a operand placeholder to always yield the same number of operands.
674 Inst.addOperand(MCOperand::CreateReg(0));
676 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
678 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
679 assert(CE && "Non-constant mode 2 offset operand!");
680 int64_t Offset = CE->getValue();
683 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
684 Offset, ARM_AM::no_shift, IdxMode)));
686 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
687 -Offset, ARM_AM::no_shift, IdxMode)));
690 void addMemMode3Operands(MCInst &Inst, unsigned N) const {
691 assert(isMemMode3() && "Invalid mode or number of operands!");
692 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
693 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
695 if (getMemOffsetIsReg()) {
696 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
698 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
699 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(AMOpc, 0,
704 // Create a operand placeholder to always yield the same number of operands.
705 Inst.addOperand(MCOperand::CreateReg(0));
707 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
709 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
710 assert(CE && "Non-constant mode 3 offset operand!");
711 int64_t Offset = CE->getValue();
714 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::add,
717 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::sub,
721 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
722 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
724 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
725 assert(!getMemOffsetIsReg() && "Invalid mode 5 operand");
727 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
729 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
730 assert(CE && "Non-constant mode 5 offset operand!");
732 // The MCInst offset operand doesn't include the low two bits (like
733 // the instruction encoding).
734 int64_t Offset = CE->getValue() / 4;
736 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
739 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
743 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
744 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
745 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
746 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
749 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
750 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
751 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
752 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
753 assert(CE && "Non-constant mode offset operand!");
754 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
757 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
758 assert(N == 1 && "Invalid number of operands!");
759 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
762 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
763 assert(N == 1 && "Invalid number of operands!");
764 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
767 virtual void print(raw_ostream &OS) const;
769 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
770 ARMOperand *Op = new ARMOperand(CondCode);
777 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
778 ARMOperand *Op = new ARMOperand(CoprocNum);
779 Op->Cop.Val = CopVal;
785 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
786 ARMOperand *Op = new ARMOperand(CoprocReg);
787 Op->Cop.Val = CopVal;
793 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
794 ARMOperand *Op = new ARMOperand(CCOut);
795 Op->Reg.RegNum = RegNum;
801 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
802 ARMOperand *Op = new ARMOperand(Token);
803 Op->Tok.Data = Str.data();
804 Op->Tok.Length = Str.size();
810 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
811 ARMOperand *Op = new ARMOperand(Register);
812 Op->Reg.RegNum = RegNum;
818 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
823 ARMOperand *Op = new ARMOperand(ShiftedRegister);
824 Op->ShiftedReg.ShiftTy = ShTy;
825 Op->ShiftedReg.SrcReg = SrcReg;
826 Op->ShiftedReg.ShiftReg = ShiftReg;
827 Op->ShiftedReg.ShiftImm = ShiftImm;
833 static ARMOperand *CreateShifter(ARM_AM::ShiftOpc ShTy,
835 ARMOperand *Op = new ARMOperand(Shifter);
836 Op->Shift.ShiftTy = ShTy;
843 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
844 SMLoc StartLoc, SMLoc EndLoc) {
845 KindTy Kind = RegisterList;
847 if (ARM::DPRRegClass.contains(Regs.front().first))
848 Kind = DPRRegisterList;
849 else if (ARM::SPRRegClass.contains(Regs.front().first))
850 Kind = SPRRegisterList;
852 ARMOperand *Op = new ARMOperand(Kind);
853 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
854 I = Regs.begin(), E = Regs.end(); I != E; ++I)
855 Op->Registers.push_back(I->first);
856 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
857 Op->StartLoc = StartLoc;
862 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
863 ARMOperand *Op = new ARMOperand(Immediate);
870 static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
871 bool OffsetIsReg, const MCExpr *Offset,
872 int OffsetRegNum, bool OffsetRegShifted,
873 enum ARM_AM::ShiftOpc ShiftType,
874 const MCExpr *ShiftAmount, bool Preindexed,
875 bool Postindexed, bool Negative, bool Writeback,
877 assert((OffsetRegNum == -1 || OffsetIsReg) &&
878 "OffsetRegNum must imply OffsetIsReg!");
879 assert((!OffsetRegShifted || OffsetIsReg) &&
880 "OffsetRegShifted must imply OffsetIsReg!");
881 assert((Offset || OffsetIsReg) &&
882 "Offset must exists unless register offset is used!");
883 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
884 "Cannot have shift amount without shifted register offset!");
885 assert((!Offset || !OffsetIsReg) &&
886 "Cannot have expression offset and register offset!");
888 ARMOperand *Op = new ARMOperand(Memory);
889 Op->Mem.AddrMode = AddrMode;
890 Op->Mem.BaseRegNum = BaseRegNum;
891 Op->Mem.OffsetIsReg = OffsetIsReg;
893 Op->Mem.Offset.RegNum = OffsetRegNum;
895 Op->Mem.Offset.Value = Offset;
896 Op->Mem.OffsetRegShifted = OffsetRegShifted;
897 Op->Mem.ShiftType = ShiftType;
898 Op->Mem.ShiftAmount = ShiftAmount;
899 Op->Mem.Preindexed = Preindexed;
900 Op->Mem.Postindexed = Postindexed;
901 Op->Mem.Negative = Negative;
902 Op->Mem.Writeback = Writeback;
909 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
910 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
917 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
918 ARMOperand *Op = new ARMOperand(ProcIFlags);
919 Op->IFlags.Val = IFlags;
925 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
926 ARMOperand *Op = new ARMOperand(MSRMask);
927 Op->MMask.Val = MMask;
934 } // end anonymous namespace.
936 void ARMOperand::print(raw_ostream &OS) const {
939 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
942 OS << "<ccout " << getReg() << ">";
945 OS << "<coprocessor number: " << getCoproc() << ">";
948 OS << "<coprocessor register: " << getCoproc() << ">";
951 OS << "<mask: " << getMSRMask() << ">";
957 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
961 << "am:" << ARMII::AddrModeToString(getMemAddrMode())
962 << " base:" << getMemBaseRegNum();
963 if (getMemOffsetIsReg()) {
964 OS << " offset:<register " << getMemOffsetRegNum();
965 if (getMemOffsetRegShifted()) {
966 OS << " offset-shift-type:" << getMemShiftType();
967 OS << " offset-shift-amount:" << *getMemShiftAmount();
970 OS << " offset:" << *getMemOffset();
972 if (getMemOffsetIsReg())
973 OS << " (offset-is-reg)";
974 if (getMemPreindexed())
975 OS << " (pre-indexed)";
976 if (getMemPostindexed())
977 OS << " (post-indexed)";
978 if (getMemNegative())
980 if (getMemWriteback())
981 OS << " (writeback)";
986 unsigned IFlags = getProcIFlags();
987 for (int i=2; i >= 0; --i)
988 if (IFlags & (1 << i))
989 OS << ARM_PROC::IFlagsToString(1 << i);
994 OS << "<register " << getReg() << ">";
997 OS << "<shifter " << ARM_AM::getShiftOpcStr(Shift.ShiftTy) << ">";
999 case ShiftedRegister:
1001 << ShiftedReg.SrcReg
1002 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(ShiftedReg.ShiftImm))
1003 << ", " << ShiftedReg.ShiftReg << ", "
1004 << ARM_AM::getSORegOffset(ShiftedReg.ShiftImm)
1008 case DPRRegisterList:
1009 case SPRRegisterList: {
1010 OS << "<register_list ";
1012 const SmallVectorImpl<unsigned> &RegList = getRegList();
1013 for (SmallVectorImpl<unsigned>::const_iterator
1014 I = RegList.begin(), E = RegList.end(); I != E; ) {
1016 if (++I < E) OS << ", ";
1023 OS << "'" << getToken() << "'";
1028 /// @name Auto-generated Match Functions
1031 static unsigned MatchRegisterName(StringRef Name);
1035 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1036 SMLoc &StartLoc, SMLoc &EndLoc) {
1037 RegNo = TryParseRegister();
1039 return (RegNo == (unsigned)-1);
1042 /// Try to parse a register name. The token must be an Identifier when called,
1043 /// and if it is a register name the token is eaten and the register number is
1044 /// returned. Otherwise return -1.
1046 int ARMAsmParser::TryParseRegister() {
1047 const AsmToken &Tok = Parser.getTok();
1048 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1050 // FIXME: Validate register for the current architecture; we have to do
1051 // validation later, so maybe there is no need for this here.
1052 std::string upperCase = Tok.getString().str();
1053 std::string lowerCase = LowercaseString(upperCase);
1054 unsigned RegNum = MatchRegisterName(lowerCase);
1056 RegNum = StringSwitch<unsigned>(lowerCase)
1057 .Case("r13", ARM::SP)
1058 .Case("r14", ARM::LR)
1059 .Case("r15", ARM::PC)
1060 .Case("ip", ARM::R12)
1063 if (!RegNum) return -1;
1065 Parser.Lex(); // Eat identifier token.
1069 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1070 // If a recoverable error occurs, return 1. If an irrecoverable error
1071 // occurs, return -1. An irrecoverable error is one where tokens have been
1072 // consumed in the process of trying to parse the shifter (i.e., when it is
1073 // indeed a shifter operand, but malformed).
1074 int ARMAsmParser::TryParseShiftRegister(
1075 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1076 SMLoc S = Parser.getTok().getLoc();
1077 const AsmToken &Tok = Parser.getTok();
1078 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1080 std::string upperCase = Tok.getString().str();
1081 std::string lowerCase = LowercaseString(upperCase);
1082 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1083 .Case("lsl", ARM_AM::lsl)
1084 .Case("lsr", ARM_AM::lsr)
1085 .Case("asr", ARM_AM::asr)
1086 .Case("ror", ARM_AM::ror)
1087 .Case("rrx", ARM_AM::rrx)
1088 .Default(ARM_AM::no_shift);
1090 if (ShiftTy == ARM_AM::no_shift)
1093 Parser.Lex(); // Eat the operator.
1095 // The source register for the shift has already been added to the
1096 // operand list, so we need to pop it off and combine it into the shifted
1097 // register operand instead.
1098 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1099 if (!PrevOp->isReg())
1100 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1101 int SrcReg = PrevOp->getReg();
1104 if (ShiftTy == ARM_AM::rrx) {
1105 // RRX Doesn't have an explicit shift amount. The encoder expects
1106 // the shift register to be the same as the source register. Seems odd,
1110 // Figure out if this is shifted by a constant or a register (for non-RRX).
1111 if (Parser.getTok().is(AsmToken::Hash)) {
1112 Parser.Lex(); // Eat hash.
1113 SMLoc ImmLoc = Parser.getTok().getLoc();
1114 const MCExpr *ShiftExpr = 0;
1115 if (getParser().ParseExpression(ShiftExpr)) {
1116 Error(ImmLoc, "invalid immediate shift value");
1119 // The expression must be evaluatable as an immediate.
1120 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1122 Error(ImmLoc, "invalid immediate shift value");
1125 // Range check the immediate.
1126 // lsl, ror: 0 <= imm <= 31
1127 // lsr, asr: 0 <= imm <= 32
1128 Imm = CE->getValue();
1130 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1131 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1132 Error(ImmLoc, "immediate shift value out of range");
1135 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1136 ShiftReg = TryParseRegister();
1137 SMLoc L = Parser.getTok().getLoc();
1138 if (ShiftReg == -1) {
1139 Error (L, "expected immediate or register in shift operand");
1143 Error (Parser.getTok().getLoc(),
1144 "expected immediate or register in shift operand");
1149 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1151 S, Parser.getTok().getLoc()));
1157 /// Try to parse a register name. The token must be an Identifier when called.
1158 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1159 /// if there is a "writeback". 'true' if it's not a register.
1161 /// TODO this is likely to change to allow different register types and or to
1162 /// parse for a specific register type.
1164 TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1165 SMLoc S = Parser.getTok().getLoc();
1166 int RegNo = TryParseRegister();
1170 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1172 const AsmToken &ExclaimTok = Parser.getTok();
1173 if (ExclaimTok.is(AsmToken::Exclaim)) {
1174 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1175 ExclaimTok.getLoc()));
1176 Parser.Lex(); // Eat exclaim token
1182 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1183 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1185 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1186 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1188 switch (Name.size()) {
1191 if (Name[0] != CoprocOp)
1208 if (Name[0] != CoprocOp || Name[1] != '1')
1212 case '0': return 10;
1213 case '1': return 11;
1214 case '2': return 12;
1215 case '3': return 13;
1216 case '4': return 14;
1217 case '5': return 15;
1225 /// tryParseCoprocNumOperand - Try to parse an coprocessor number operand. The
1226 /// token must be an Identifier when called, and if it is a coprocessor
1227 /// number, the token is eaten and the operand is added to the operand list.
1228 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1229 tryParseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1230 SMLoc S = Parser.getTok().getLoc();
1231 const AsmToken &Tok = Parser.getTok();
1232 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1234 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1236 return MatchOperand_NoMatch;
1238 Parser.Lex(); // Eat identifier token.
1239 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1240 return MatchOperand_Success;
1243 /// tryParseCoprocRegOperand - Try to parse an coprocessor register operand. The
1244 /// token must be an Identifier when called, and if it is a coprocessor
1245 /// number, the token is eaten and the operand is added to the operand list.
1246 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1247 tryParseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1248 SMLoc S = Parser.getTok().getLoc();
1249 const AsmToken &Tok = Parser.getTok();
1250 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1252 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1254 return MatchOperand_NoMatch;
1256 Parser.Lex(); // Eat identifier token.
1257 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1258 return MatchOperand_Success;
1261 /// Parse a register list, return it if successful else return null. The first
1262 /// token must be a '{' when called.
1264 ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1265 assert(Parser.getTok().is(AsmToken::LCurly) &&
1266 "Token is not a Left Curly Brace");
1267 SMLoc S = Parser.getTok().getLoc();
1269 // Read the rest of the registers in the list.
1270 unsigned PrevRegNum = 0;
1271 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1274 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1275 Parser.Lex(); // Eat non-identifier token.
1277 const AsmToken &RegTok = Parser.getTok();
1278 SMLoc RegLoc = RegTok.getLoc();
1279 if (RegTok.isNot(AsmToken::Identifier)) {
1280 Error(RegLoc, "register expected");
1284 int RegNum = TryParseRegister();
1286 Error(RegLoc, "register expected");
1291 int Reg = PrevRegNum;
1294 Registers.push_back(std::make_pair(Reg, RegLoc));
1295 } while (Reg != RegNum);
1297 Registers.push_back(std::make_pair(RegNum, RegLoc));
1300 PrevRegNum = RegNum;
1301 } while (Parser.getTok().is(AsmToken::Comma) ||
1302 Parser.getTok().is(AsmToken::Minus));
1304 // Process the right curly brace of the list.
1305 const AsmToken &RCurlyTok = Parser.getTok();
1306 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1307 Error(RCurlyTok.getLoc(), "'}' expected");
1311 SMLoc E = RCurlyTok.getLoc();
1312 Parser.Lex(); // Eat right curly brace token.
1314 // Verify the register list.
1315 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1316 RI = Registers.begin(), RE = Registers.end();
1318 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1319 bool EmittedWarning = false;
1321 DenseMap<unsigned, bool> RegMap;
1322 RegMap[HighRegNum] = true;
1324 for (++RI; RI != RE; ++RI) {
1325 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1326 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1329 Error(RegInfo.second, "register duplicated in register list");
1333 if (!EmittedWarning && Reg < HighRegNum)
1334 Warning(RegInfo.second,
1335 "register not in ascending order in register list");
1338 HighRegNum = std::max(Reg, HighRegNum);
1341 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1345 /// tryParseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1346 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1347 tryParseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1348 SMLoc S = Parser.getTok().getLoc();
1349 const AsmToken &Tok = Parser.getTok();
1350 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1351 StringRef OptStr = Tok.getString();
1353 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1354 .Case("sy", ARM_MB::SY)
1355 .Case("st", ARM_MB::ST)
1356 .Case("sh", ARM_MB::ISH)
1357 .Case("ish", ARM_MB::ISH)
1358 .Case("shst", ARM_MB::ISHST)
1359 .Case("ishst", ARM_MB::ISHST)
1360 .Case("nsh", ARM_MB::NSH)
1361 .Case("un", ARM_MB::NSH)
1362 .Case("nshst", ARM_MB::NSHST)
1363 .Case("unst", ARM_MB::NSHST)
1364 .Case("osh", ARM_MB::OSH)
1365 .Case("oshst", ARM_MB::OSHST)
1369 return MatchOperand_NoMatch;
1371 Parser.Lex(); // Eat identifier token.
1372 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1373 return MatchOperand_Success;
1376 /// tryParseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1377 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1378 tryParseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1379 SMLoc S = Parser.getTok().getLoc();
1380 const AsmToken &Tok = Parser.getTok();
1381 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1382 StringRef IFlagsStr = Tok.getString();
1384 unsigned IFlags = 0;
1385 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1386 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1387 .Case("a", ARM_PROC::A)
1388 .Case("i", ARM_PROC::I)
1389 .Case("f", ARM_PROC::F)
1392 // If some specific iflag is already set, it means that some letter is
1393 // present more than once, this is not acceptable.
1394 if (Flag == ~0U || (IFlags & Flag))
1395 return MatchOperand_NoMatch;
1400 Parser.Lex(); // Eat identifier token.
1401 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1402 return MatchOperand_Success;
1405 /// tryParseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1406 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1407 tryParseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1408 SMLoc S = Parser.getTok().getLoc();
1409 const AsmToken &Tok = Parser.getTok();
1410 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1411 StringRef Mask = Tok.getString();
1413 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1414 size_t Start = 0, Next = Mask.find('_');
1415 StringRef Flags = "";
1416 StringRef SpecReg = Mask.slice(Start, Next);
1417 if (Next != StringRef::npos)
1418 Flags = Mask.slice(Next+1, Mask.size());
1420 // FlagsVal contains the complete mask:
1422 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1423 unsigned FlagsVal = 0;
1425 if (SpecReg == "apsr") {
1426 FlagsVal = StringSwitch<unsigned>(Flags)
1427 .Case("nzcvq", 0x8) // same as CPSR_c
1428 .Case("g", 0x4) // same as CPSR_s
1429 .Case("nzcvqg", 0xc) // same as CPSR_fs
1432 if (FlagsVal == ~0U) {
1434 return MatchOperand_NoMatch;
1436 FlagsVal = 0; // No flag
1438 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1439 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1441 for (int i = 0, e = Flags.size(); i != e; ++i) {
1442 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1449 // If some specific flag is already set, it means that some letter is
1450 // present more than once, this is not acceptable.
1451 if (FlagsVal == ~0U || (FlagsVal & Flag))
1452 return MatchOperand_NoMatch;
1455 } else // No match for special register.
1456 return MatchOperand_NoMatch;
1458 // Special register without flags are equivalent to "fc" flags.
1462 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1463 if (SpecReg == "spsr")
1466 Parser.Lex(); // Eat identifier token.
1467 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1468 return MatchOperand_Success;
1471 /// tryParseMemMode2Operand - Try to parse memory addressing mode 2 operand.
1472 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1473 tryParseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1474 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1476 if (ParseMemory(Operands, ARMII::AddrMode2))
1477 return MatchOperand_NoMatch;
1479 return MatchOperand_Success;
1482 /// tryParseMemMode3Operand - Try to parse memory addressing mode 3 operand.
1483 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1484 tryParseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1485 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1487 if (ParseMemory(Operands, ARMII::AddrMode3))
1488 return MatchOperand_NoMatch;
1490 return MatchOperand_Success;
1493 /// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1494 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1495 /// when they refer multiple MIOperands inside a single one.
1497 CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1498 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1499 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1501 // Create a writeback register dummy placeholder.
1502 Inst.addOperand(MCOperand::CreateImm(0));
1504 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1505 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1509 /// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1510 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1511 /// when they refer multiple MIOperands inside a single one.
1513 CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1514 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1515 // Create a writeback register dummy placeholder.
1516 Inst.addOperand(MCOperand::CreateImm(0));
1517 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1518 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1519 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1523 /// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1524 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1525 /// when they refer multiple MIOperands inside a single one.
1527 CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1528 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1529 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1531 // Create a writeback register dummy placeholder.
1532 Inst.addOperand(MCOperand::CreateImm(0));
1534 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1535 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1539 /// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1540 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1541 /// when they refer multiple MIOperands inside a single one.
1543 CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1544 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1545 // Create a writeback register dummy placeholder.
1546 Inst.addOperand(MCOperand::CreateImm(0));
1547 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1548 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1549 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1553 /// Parse an ARM memory expression, return false if successful else return true
1554 /// or an error. The first token must be a '[' when called.
1556 /// TODO Only preindexing and postindexing addressing are started, unindexed
1557 /// with option, etc are still to do.
1559 ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1560 ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
1562 assert(Parser.getTok().is(AsmToken::LBrac) &&
1563 "Token is not a Left Bracket");
1564 S = Parser.getTok().getLoc();
1565 Parser.Lex(); // Eat left bracket token.
1567 const AsmToken &BaseRegTok = Parser.getTok();
1568 if (BaseRegTok.isNot(AsmToken::Identifier)) {
1569 Error(BaseRegTok.getLoc(), "register expected");
1572 int BaseRegNum = TryParseRegister();
1573 if (BaseRegNum == -1) {
1574 Error(BaseRegTok.getLoc(), "register expected");
1578 // The next token must either be a comma or a closing bracket.
1579 const AsmToken &Tok = Parser.getTok();
1580 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
1583 bool Preindexed = false;
1584 bool Postindexed = false;
1585 bool OffsetIsReg = false;
1586 bool Negative = false;
1587 bool Writeback = false;
1588 ARMOperand *WBOp = 0;
1589 int OffsetRegNum = -1;
1590 bool OffsetRegShifted = false;
1591 enum ARM_AM::ShiftOpc ShiftType = ARM_AM::lsl;
1592 const MCExpr *ShiftAmount = 0;
1593 const MCExpr *Offset = 0;
1595 // First look for preindexed address forms, that is after the "[Rn" we now
1596 // have to see if the next token is a comma.
1597 if (Tok.is(AsmToken::Comma)) {
1599 Parser.Lex(); // Eat comma token.
1601 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
1602 Offset, OffsetIsReg, OffsetRegNum, E))
1604 const AsmToken &RBracTok = Parser.getTok();
1605 if (RBracTok.isNot(AsmToken::RBrac)) {
1606 Error(RBracTok.getLoc(), "']' expected");
1609 E = RBracTok.getLoc();
1610 Parser.Lex(); // Eat right bracket token.
1612 const AsmToken &ExclaimTok = Parser.getTok();
1613 if (ExclaimTok.is(AsmToken::Exclaim)) {
1614 // None of addrmode3 instruction uses "!"
1615 if (AddrMode == ARMII::AddrMode3)
1618 WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
1619 ExclaimTok.getLoc());
1621 Parser.Lex(); // Eat exclaim token
1622 } else { // In addressing mode 2, pre-indexed mode always end with "!"
1623 if (AddrMode == ARMII::AddrMode2)
1627 // The "[Rn" we have so far was not followed by a comma.
1629 // If there's anything other than the right brace, this is a post indexing
1632 Parser.Lex(); // Eat right bracket token.
1634 const AsmToken &NextTok = Parser.getTok();
1636 if (NextTok.isNot(AsmToken::EndOfStatement)) {
1640 if (NextTok.isNot(AsmToken::Comma)) {
1641 Error(NextTok.getLoc(), "',' expected");
1645 Parser.Lex(); // Eat comma token.
1647 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
1648 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
1654 // Force Offset to exist if used.
1657 Offset = MCConstantExpr::Create(0, getContext());
1659 if (AddrMode == ARMII::AddrMode3 && OffsetRegShifted) {
1660 Error(E, "shift amount not supported");
1665 Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
1666 Offset, OffsetRegNum, OffsetRegShifted,
1667 ShiftType, ShiftAmount, Preindexed,
1668 Postindexed, Negative, Writeback, S, E));
1670 Operands.push_back(WBOp);
1675 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
1676 /// we will parse the following (were +/- means that a plus or minus is
1681 /// we return false on success or an error otherwise.
1682 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
1683 bool &OffsetRegShifted,
1684 enum ARM_AM::ShiftOpc &ShiftType,
1685 const MCExpr *&ShiftAmount,
1686 const MCExpr *&Offset,
1691 OffsetRegShifted = false;
1692 OffsetIsReg = false;
1694 const AsmToken &NextTok = Parser.getTok();
1695 E = NextTok.getLoc();
1696 if (NextTok.is(AsmToken::Plus))
1697 Parser.Lex(); // Eat plus token.
1698 else if (NextTok.is(AsmToken::Minus)) {
1700 Parser.Lex(); // Eat minus token
1702 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
1703 const AsmToken &OffsetRegTok = Parser.getTok();
1704 if (OffsetRegTok.is(AsmToken::Identifier)) {
1705 SMLoc CurLoc = OffsetRegTok.getLoc();
1706 OffsetRegNum = TryParseRegister();
1707 if (OffsetRegNum != -1) {
1713 // If we parsed a register as the offset then there can be a shift after that.
1714 if (OffsetRegNum != -1) {
1715 // Look for a comma then a shift
1716 const AsmToken &Tok = Parser.getTok();
1717 if (Tok.is(AsmToken::Comma)) {
1718 Parser.Lex(); // Eat comma token.
1720 const AsmToken &Tok = Parser.getTok();
1721 if (ParseShift(ShiftType, ShiftAmount, E))
1722 return Error(Tok.getLoc(), "shift expected");
1723 OffsetRegShifted = true;
1726 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
1727 // Look for #offset following the "[Rn," or "[Rn],"
1728 const AsmToken &HashTok = Parser.getTok();
1729 if (HashTok.isNot(AsmToken::Hash))
1730 return Error(HashTok.getLoc(), "'#' expected");
1732 Parser.Lex(); // Eat hash token.
1734 if (getParser().ParseExpression(Offset))
1736 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1741 /// ParseShift as one of these two:
1742 /// ( lsl | lsr | asr | ror ) , # shift_amount
1744 /// and returns true if it parses a shift otherwise it returns false.
1745 bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St,
1746 const MCExpr *&ShiftAmount, SMLoc &E) {
1747 const AsmToken &Tok = Parser.getTok();
1748 if (Tok.isNot(AsmToken::Identifier))
1750 StringRef ShiftName = Tok.getString();
1751 if (ShiftName == "lsl" || ShiftName == "LSL")
1753 else if (ShiftName == "lsr" || ShiftName == "LSR")
1755 else if (ShiftName == "asr" || ShiftName == "ASR")
1757 else if (ShiftName == "ror" || ShiftName == "ROR")
1759 else if (ShiftName == "rrx" || ShiftName == "RRX")
1763 Parser.Lex(); // Eat shift type token.
1765 // Rrx stands alone.
1766 if (St == ARM_AM::rrx)
1769 // Otherwise, there must be a '#' and a shift amount.
1770 const AsmToken &HashTok = Parser.getTok();
1771 if (HashTok.isNot(AsmToken::Hash))
1772 return Error(HashTok.getLoc(), "'#' expected");
1773 Parser.Lex(); // Eat hash token.
1775 if (getParser().ParseExpression(ShiftAmount))
1781 /// Parse a arm instruction operand. For now this parses the operand regardless
1782 /// of the mnemonic.
1783 bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1784 StringRef Mnemonic) {
1787 // Check if the current operand has a custom associated parser, if so, try to
1788 // custom parse the operand, or fallback to the general approach.
1789 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1790 if (ResTy == MatchOperand_Success)
1792 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1793 // there was a match, but an error occurred, in which case, just return that
1794 // the operand parsing failed.
1795 if (ResTy == MatchOperand_ParseFail)
1798 switch (getLexer().getKind()) {
1800 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1802 case AsmToken::Identifier: {
1803 if (!TryParseRegisterWithWriteBack(Operands))
1805 int Res = TryParseShiftRegister(Operands);
1806 if (Res == 0) // success
1808 else if (Res == -1) // irrecoverable error
1811 // Fall though for the Identifier case that is not a register or a
1814 case AsmToken::Integer: // things like 1f and 2b as a branch targets
1815 case AsmToken::Dot: { // . as a branch target
1816 // This was not a register so parse other operands that start with an
1817 // identifier (like labels) as expressions and create them as immediates.
1818 const MCExpr *IdVal;
1819 S = Parser.getTok().getLoc();
1820 if (getParser().ParseExpression(IdVal))
1822 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1823 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
1826 case AsmToken::LBrac:
1827 return ParseMemory(Operands);
1828 case AsmToken::LCurly:
1829 return ParseRegisterList(Operands);
1830 case AsmToken::Hash:
1831 // #42 -> immediate.
1832 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
1833 S = Parser.getTok().getLoc();
1835 const MCExpr *ImmVal;
1836 if (getParser().ParseExpression(ImmVal))
1838 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1839 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
1841 case AsmToken::Colon: {
1842 // ":lower16:" and ":upper16:" expression prefixes
1843 // FIXME: Check it's an expression prefix,
1844 // e.g. (FOO - :lower16:BAR) isn't legal.
1845 ARMMCExpr::VariantKind RefKind;
1846 if (ParsePrefix(RefKind))
1849 const MCExpr *SubExprVal;
1850 if (getParser().ParseExpression(SubExprVal))
1853 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
1855 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1856 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
1862 // ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
1863 // :lower16: and :upper16:.
1864 bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
1865 RefKind = ARMMCExpr::VK_ARM_None;
1867 // :lower16: and :upper16: modifiers
1868 assert(getLexer().is(AsmToken::Colon) && "expected a :");
1869 Parser.Lex(); // Eat ':'
1871 if (getLexer().isNot(AsmToken::Identifier)) {
1872 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
1876 StringRef IDVal = Parser.getTok().getIdentifier();
1877 if (IDVal == "lower16") {
1878 RefKind = ARMMCExpr::VK_ARM_LO16;
1879 } else if (IDVal == "upper16") {
1880 RefKind = ARMMCExpr::VK_ARM_HI16;
1882 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
1887 if (getLexer().isNot(AsmToken::Colon)) {
1888 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
1891 Parser.Lex(); // Eat the last ':'
1896 ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
1897 MCSymbolRefExpr::VariantKind Variant) {
1898 // Recurse over the given expression, rebuilding it to apply the given variant
1899 // to the leftmost symbol.
1900 if (Variant == MCSymbolRefExpr::VK_None)
1903 switch (E->getKind()) {
1904 case MCExpr::Target:
1905 llvm_unreachable("Can't handle target expr yet");
1906 case MCExpr::Constant:
1907 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
1909 case MCExpr::SymbolRef: {
1910 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1912 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
1915 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
1919 llvm_unreachable("Can't handle unary expressions yet");
1921 case MCExpr::Binary: {
1922 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1923 const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant);
1924 const MCExpr *RHS = BE->getRHS();
1928 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
1932 assert(0 && "Invalid expression kind!");
1936 /// \brief Given a mnemonic, split out possible predication code and carry
1937 /// setting letters to form a canonical mnemonic and flags.
1939 // FIXME: Would be nice to autogen this.
1940 static StringRef SplitMnemonic(StringRef Mnemonic,
1941 unsigned &PredicationCode,
1943 unsigned &ProcessorIMod) {
1944 PredicationCode = ARMCC::AL;
1945 CarrySetting = false;
1948 // Ignore some mnemonics we know aren't predicated forms.
1950 // FIXME: Would be nice to autogen this.
1951 if (Mnemonic == "teq" || Mnemonic == "vceq" ||
1952 Mnemonic == "movs" ||
1953 Mnemonic == "svc" ||
1954 (Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
1955 Mnemonic == "vmls" || Mnemonic == "vnmls") ||
1956 Mnemonic == "vacge" || Mnemonic == "vcge" ||
1957 Mnemonic == "vclt" ||
1958 Mnemonic == "vacgt" || Mnemonic == "vcgt" ||
1959 Mnemonic == "vcle" ||
1960 (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" ||
1961 Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" ||
1962 Mnemonic == "vqdmlal"))
1965 // First, split out any predication code. Ignore mnemonics we know aren't
1966 // predicated but do have a carry-set and so weren't caught above.
1967 if (Mnemonic != "adcs" && Mnemonic != "bics") {
1968 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
1969 .Case("eq", ARMCC::EQ)
1970 .Case("ne", ARMCC::NE)
1971 .Case("hs", ARMCC::HS)
1972 .Case("cs", ARMCC::HS)
1973 .Case("lo", ARMCC::LO)
1974 .Case("cc", ARMCC::LO)
1975 .Case("mi", ARMCC::MI)
1976 .Case("pl", ARMCC::PL)
1977 .Case("vs", ARMCC::VS)
1978 .Case("vc", ARMCC::VC)
1979 .Case("hi", ARMCC::HI)
1980 .Case("ls", ARMCC::LS)
1981 .Case("ge", ARMCC::GE)
1982 .Case("lt", ARMCC::LT)
1983 .Case("gt", ARMCC::GT)
1984 .Case("le", ARMCC::LE)
1985 .Case("al", ARMCC::AL)
1988 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
1989 PredicationCode = CC;
1993 // Next, determine if we have a carry setting bit. We explicitly ignore all
1994 // the instructions we know end in 's'.
1995 if (Mnemonic.endswith("s") &&
1996 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
1997 Mnemonic == "movs" || Mnemonic == "mrs" || Mnemonic == "smmls" ||
1998 Mnemonic == "vabs" || Mnemonic == "vcls" || Mnemonic == "vmls" ||
1999 Mnemonic == "vmrs" || Mnemonic == "vnmls" || Mnemonic == "vqabs" ||
2000 Mnemonic == "vrecps" || Mnemonic == "vrsqrts")) {
2001 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2002 CarrySetting = true;
2005 // The "cps" instruction can have a interrupt mode operand which is glued into
2006 // the mnemonic. Check if this is the case, split it and parse the imod op
2007 if (Mnemonic.startswith("cps")) {
2008 // Split out any imod code.
2010 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2011 .Case("ie", ARM_PROC::IE)
2012 .Case("id", ARM_PROC::ID)
2015 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2016 ProcessorIMod = IMod;
2023 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
2024 /// inclusion of carry set or predication code operands.
2026 // FIXME: It would be nice to autogen this.
2028 GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2029 bool &CanAcceptPredicationCode) {
2030 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2031 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2032 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2033 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2034 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2035 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2036 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2037 Mnemonic == "eor" || Mnemonic == "smlal" ||
2038 (Mnemonic == "mov" && !isThumbOne())) {
2039 CanAcceptCarrySet = true;
2041 CanAcceptCarrySet = false;
2044 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2045 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2046 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2047 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2048 Mnemonic == "dsb" || Mnemonic == "movs" || Mnemonic == "isb" ||
2049 Mnemonic == "clrex" || Mnemonic.startswith("cps")) {
2050 CanAcceptPredicationCode = false;
2052 CanAcceptPredicationCode = true;
2056 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2057 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2058 CanAcceptPredicationCode = false;
2061 /// Parse an arm instruction mnemonic followed by its operands.
2062 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2063 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2064 // Create the leading tokens for the mnemonic, split by '.' characters.
2065 size_t Start = 0, Next = Name.find('.');
2066 StringRef Head = Name.slice(Start, Next);
2068 // Split out the predication code and carry setting flag from the mnemonic.
2069 unsigned PredicationCode;
2070 unsigned ProcessorIMod;
2072 Head = SplitMnemonic(Head, PredicationCode, CarrySetting,
2075 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
2077 // Next, add the CCOut and ConditionCode operands, if needed.
2079 // For mnemonics which can ever incorporate a carry setting bit or predication
2080 // code, our matching model involves us always generating CCOut and
2081 // ConditionCode operands to match the mnemonic "as written" and then we let
2082 // the matcher deal with finding the right instruction or generating an
2083 // appropriate error.
2084 bool CanAcceptCarrySet, CanAcceptPredicationCode;
2085 GetMnemonicAcceptInfo(Head, CanAcceptCarrySet, CanAcceptPredicationCode);
2087 // If we had a carry-set on an instruction that can't do that, issue an
2089 if (!CanAcceptCarrySet && CarrySetting) {
2090 Parser.EatToEndOfStatement();
2091 return Error(NameLoc, "instruction '" + Head +
2092 "' can not set flags, but 's' suffix specified");
2095 // Add the carry setting operand, if necessary.
2097 // FIXME: It would be awesome if we could somehow invent a location such that
2098 // match errors on this operand would print a nice diagnostic about how the
2099 // 's' character in the mnemonic resulted in a CCOut operand.
2100 if (CanAcceptCarrySet)
2101 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2104 // Add the predication code operand, if necessary.
2105 if (CanAcceptPredicationCode) {
2106 Operands.push_back(ARMOperand::CreateCondCode(
2107 ARMCC::CondCodes(PredicationCode), NameLoc));
2109 // This mnemonic can't ever accept a predication code, but the user wrote
2110 // one (or misspelled another mnemonic).
2112 // FIXME: Issue a nice error.
2115 // Add the processor imod operand, if necessary.
2116 if (ProcessorIMod) {
2117 Operands.push_back(ARMOperand::CreateImm(
2118 MCConstantExpr::Create(ProcessorIMod, getContext()),
2121 // This mnemonic can't ever accept a imod, but the user wrote
2122 // one (or misspelled another mnemonic).
2124 // FIXME: Issue a nice error.
2127 // Add the remaining tokens in the mnemonic.
2128 while (Next != StringRef::npos) {
2130 Next = Name.find('.', Start + 1);
2131 StringRef ExtraToken = Name.slice(Start, Next);
2133 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2136 // Read the remaining operands.
2137 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2138 // Read the first operand.
2139 if (ParseOperand(Operands, Head)) {
2140 Parser.EatToEndOfStatement();
2144 while (getLexer().is(AsmToken::Comma)) {
2145 Parser.Lex(); // Eat the comma.
2147 // Parse and remember the operand.
2148 if (ParseOperand(Operands, Head)) {
2149 Parser.EatToEndOfStatement();
2155 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2156 Parser.EatToEndOfStatement();
2157 return TokError("unexpected token in argument list");
2160 Parser.Lex(); // Consume the EndOfStatement
2165 MatchAndEmitInstruction(SMLoc IDLoc,
2166 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2170 MatchResultTy MatchResult;
2171 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
2172 switch (MatchResult) {
2174 Out.EmitInstruction(Inst);
2176 case Match_MissingFeature:
2177 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
2179 case Match_InvalidOperand: {
2180 SMLoc ErrorLoc = IDLoc;
2181 if (ErrorInfo != ~0U) {
2182 if (ErrorInfo >= Operands.size())
2183 return Error(IDLoc, "too few operands for instruction");
2185 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
2186 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
2189 return Error(ErrorLoc, "invalid operand for instruction");
2191 case Match_MnemonicFail:
2192 return Error(IDLoc, "unrecognized instruction mnemonic");
2193 case Match_ConversionFail:
2194 return Error(IDLoc, "unable to convert operands to instruction");
2197 llvm_unreachable("Implement any new match types added!");
2201 /// ParseDirective parses the arm specific directives
2202 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
2203 StringRef IDVal = DirectiveID.getIdentifier();
2204 if (IDVal == ".word")
2205 return ParseDirectiveWord(4, DirectiveID.getLoc());
2206 else if (IDVal == ".thumb")
2207 return ParseDirectiveThumb(DirectiveID.getLoc());
2208 else if (IDVal == ".thumb_func")
2209 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
2210 else if (IDVal == ".code")
2211 return ParseDirectiveCode(DirectiveID.getLoc());
2212 else if (IDVal == ".syntax")
2213 return ParseDirectiveSyntax(DirectiveID.getLoc());
2217 /// ParseDirectiveWord
2218 /// ::= .word [ expression (, expression)* ]
2219 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2220 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2222 const MCExpr *Value;
2223 if (getParser().ParseExpression(Value))
2226 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
2228 if (getLexer().is(AsmToken::EndOfStatement))
2231 // FIXME: Improve diagnostic.
2232 if (getLexer().isNot(AsmToken::Comma))
2233 return Error(L, "unexpected token in directive");
2242 /// ParseDirectiveThumb
2244 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
2245 if (getLexer().isNot(AsmToken::EndOfStatement))
2246 return Error(L, "unexpected token in directive");
2249 // TODO: set thumb mode
2250 // TODO: tell the MC streamer the mode
2251 // getParser().getStreamer().Emit???();
2255 /// ParseDirectiveThumbFunc
2256 /// ::= .thumbfunc symbol_name
2257 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
2258 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
2259 bool isMachO = MAI.hasSubsectionsViaSymbols();
2262 // Darwin asm has function name after .thumb_func direction
2265 const AsmToken &Tok = Parser.getTok();
2266 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
2267 return Error(L, "unexpected token in .thumb_func directive");
2268 Name = Tok.getString();
2269 Parser.Lex(); // Consume the identifier token.
2272 if (getLexer().isNot(AsmToken::EndOfStatement))
2273 return Error(L, "unexpected token in directive");
2276 // FIXME: assuming function name will be the line following .thumb_func
2278 Name = Parser.getTok().getString();
2281 // Mark symbol as a thumb symbol.
2282 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
2283 getParser().getStreamer().EmitThumbFunc(Func);
2287 /// ParseDirectiveSyntax
2288 /// ::= .syntax unified | divided
2289 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
2290 const AsmToken &Tok = Parser.getTok();
2291 if (Tok.isNot(AsmToken::Identifier))
2292 return Error(L, "unexpected token in .syntax directive");
2293 StringRef Mode = Tok.getString();
2294 if (Mode == "unified" || Mode == "UNIFIED")
2296 else if (Mode == "divided" || Mode == "DIVIDED")
2297 return Error(L, "'.syntax divided' arm asssembly not supported");
2299 return Error(L, "unrecognized syntax mode in .syntax directive");
2301 if (getLexer().isNot(AsmToken::EndOfStatement))
2302 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2305 // TODO tell the MC streamer the mode
2306 // getParser().getStreamer().Emit???();
2310 /// ParseDirectiveCode
2311 /// ::= .code 16 | 32
2312 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
2313 const AsmToken &Tok = Parser.getTok();
2314 if (Tok.isNot(AsmToken::Integer))
2315 return Error(L, "unexpected token in .code directive");
2316 int64_t Val = Parser.getTok().getIntVal();
2322 return Error(L, "invalid operand to .code directive");
2324 if (getLexer().isNot(AsmToken::EndOfStatement))
2325 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2331 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2335 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2341 extern "C" void LLVMInitializeARMAsmLexer();
2343 /// Force static initialization.
2344 extern "C" void LLVMInitializeARMAsmParser() {
2345 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
2346 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
2347 LLVMInitializeARMAsmLexer();
2350 #define GET_REGISTER_MATCHER
2351 #define GET_MATCHER_IMPLEMENTATION
2352 #include "ARMGenAsmMatcher.inc"