1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/MC/MCSubtargetInfo.h"
23 #include "llvm/MC/MCTargetAsmParser.h"
24 #include "llvm/Target/TargetRegistry.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/ADT/OwningPtr.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringExtras.h"
31 #include "llvm/ADT/StringSwitch.h"
32 #include "llvm/ADT/Twine.h"
40 class ARMAsmParser : public MCTargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
45 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
50 int tryParseRegister();
51 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
52 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
53 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
54 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
55 ARMII::AddrMode AddrMode);
56 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
57 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
58 const MCExpr *applyPrefixToExpr(const MCExpr *E,
59 MCSymbolRefExpr::VariantKind Variant);
62 bool parseMemoryOffsetReg(bool &Negative,
63 bool &OffsetRegShifted,
64 enum ARM_AM::ShiftOpc &ShiftType,
65 const MCExpr *&ShiftAmount,
66 const MCExpr *&Offset,
70 bool parseShift(enum ARM_AM::ShiftOpc &St,
71 const MCExpr *&ShiftAmount, SMLoc &E);
72 bool parseDirectiveWord(unsigned Size, SMLoc L);
73 bool parseDirectiveThumb(SMLoc L);
74 bool parseDirectiveThumbFunc(SMLoc L);
75 bool parseDirectiveCode(SMLoc L);
76 bool parseDirectiveSyntax(SMLoc L);
78 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
79 bool &CarrySetting, unsigned &ProcessorIMod);
80 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
81 bool &CanAcceptPredicationCode);
83 bool isThumb() const {
84 // FIXME: Can tablegen auto-generate this?
85 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
87 bool isThumbOne() const {
88 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
91 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
92 setAvailableFeatures(FB);
95 /// @name Auto-generated Match Functions
98 #define GET_ASSEMBLER_HEADER
99 #include "ARMGenAsmMatcher.inc"
103 OperandMatchResultTy parseCoprocNumOperand(
104 SmallVectorImpl<MCParsedAsmOperand*>&);
105 OperandMatchResultTy parseCoprocRegOperand(
106 SmallVectorImpl<MCParsedAsmOperand*>&);
107 OperandMatchResultTy parseMemBarrierOptOperand(
108 SmallVectorImpl<MCParsedAsmOperand*>&);
109 OperandMatchResultTy parseProcIFlagsOperand(
110 SmallVectorImpl<MCParsedAsmOperand*>&);
111 OperandMatchResultTy parseMSRMaskOperand(
112 SmallVectorImpl<MCParsedAsmOperand*>&);
113 OperandMatchResultTy parseMemMode2Operand(
114 SmallVectorImpl<MCParsedAsmOperand*>&);
115 OperandMatchResultTy parseMemMode3Operand(
116 SmallVectorImpl<MCParsedAsmOperand*>&);
117 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
118 StringRef Op, int Low, int High);
119 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
120 return parsePKHImm(O, "lsl", 0, 31);
122 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
123 return parsePKHImm(O, "asr", 1, 32);
125 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
126 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
127 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
128 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
130 // Asm Match Converter Methods
131 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
132 const SmallVectorImpl<MCParsedAsmOperand*> &);
133 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
134 const SmallVectorImpl<MCParsedAsmOperand*> &);
135 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
136 const SmallVectorImpl<MCParsedAsmOperand*> &);
137 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
138 const SmallVectorImpl<MCParsedAsmOperand*> &);
141 bool validateInstruction(MCInst &Inst,
142 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
145 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
146 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
147 MCAsmParserExtension::Initialize(_Parser);
149 // Initialize the set of available features.
150 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
153 // Implementation of the MCTargetAsmParser interface:
154 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
155 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
156 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
157 bool ParseDirective(AsmToken DirectiveID);
159 bool MatchAndEmitInstruction(SMLoc IDLoc,
160 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
163 } // end anonymous namespace
167 /// ARMOperand - Instances of this class represent a parsed ARM machine
169 class ARMOperand : public MCParsedAsmOperand {
192 SMLoc StartLoc, EndLoc;
193 SmallVector<unsigned, 8> Registers;
197 ARMCC::CondCodes Val;
209 ARM_PROC::IFlags Val;
229 /// Combined record for all forms of ARM address expressions.
231 ARMII::AddrMode AddrMode;
234 unsigned RegNum; ///< Offset register num, when OffsetIsReg.
235 const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
237 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
238 enum ARM_AM::ShiftOpc ShiftType; // used when OffsetRegShifted is true
239 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
240 unsigned Preindexed : 1;
241 unsigned Postindexed : 1;
242 unsigned OffsetIsReg : 1;
243 unsigned Negative : 1; // only used when OffsetIsReg is true
244 unsigned Writeback : 1;
252 ARM_AM::ShiftOpc ShiftTy;
258 ARM_AM::ShiftOpc ShiftTy;
271 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
273 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
275 StartLoc = o.StartLoc;
289 case DPRRegisterList:
290 case SPRRegisterList:
291 Registers = o.Registers;
312 case ShifterImmediate:
313 ShifterImm = o.ShifterImm;
315 case ShiftedRegister:
316 RegShiftedReg = o.RegShiftedReg;
318 case ShiftedImmediate:
319 RegShiftedImm = o.RegShiftedImm;
321 case RotateImmediate:
324 case BitfieldDescriptor:
325 Bitfield = o.Bitfield;
330 /// getStartLoc - Get the location of the first token of this operand.
331 SMLoc getStartLoc() const { return StartLoc; }
332 /// getEndLoc - Get the location of the last token of this operand.
333 SMLoc getEndLoc() const { return EndLoc; }
335 ARMCC::CondCodes getCondCode() const {
336 assert(Kind == CondCode && "Invalid access!");
340 unsigned getCoproc() const {
341 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
345 StringRef getToken() const {
346 assert(Kind == Token && "Invalid access!");
347 return StringRef(Tok.Data, Tok.Length);
350 unsigned getReg() const {
351 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
355 const SmallVectorImpl<unsigned> &getRegList() const {
356 assert((Kind == RegisterList || Kind == DPRRegisterList ||
357 Kind == SPRRegisterList) && "Invalid access!");
361 const MCExpr *getImm() const {
362 assert(Kind == Immediate && "Invalid access!");
366 ARM_MB::MemBOpt getMemBarrierOpt() const {
367 assert(Kind == MemBarrierOpt && "Invalid access!");
371 ARM_PROC::IFlags getProcIFlags() const {
372 assert(Kind == ProcIFlags && "Invalid access!");
376 unsigned getMSRMask() const {
377 assert(Kind == MSRMask && "Invalid access!");
381 /// @name Memory Operand Accessors
383 ARMII::AddrMode getMemAddrMode() const {
386 unsigned getMemBaseRegNum() const {
387 return Mem.BaseRegNum;
389 unsigned getMemOffsetRegNum() const {
390 assert(Mem.OffsetIsReg && "Invalid access!");
391 return Mem.Offset.RegNum;
393 const MCExpr *getMemOffset() const {
394 assert(!Mem.OffsetIsReg && "Invalid access!");
395 return Mem.Offset.Value;
397 unsigned getMemOffsetRegShifted() const {
398 assert(Mem.OffsetIsReg && "Invalid access!");
399 return Mem.OffsetRegShifted;
401 const MCExpr *getMemShiftAmount() const {
402 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
403 return Mem.ShiftAmount;
405 enum ARM_AM::ShiftOpc getMemShiftType() const {
406 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
407 return Mem.ShiftType;
409 bool getMemPreindexed() const { return Mem.Preindexed; }
410 bool getMemPostindexed() const { return Mem.Postindexed; }
411 bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; }
412 bool getMemNegative() const { return Mem.Negative; }
413 bool getMemWriteback() const { return Mem.Writeback; }
417 bool isCoprocNum() const { return Kind == CoprocNum; }
418 bool isCoprocReg() const { return Kind == CoprocReg; }
419 bool isCondCode() const { return Kind == CondCode; }
420 bool isCCOut() const { return Kind == CCOut; }
421 bool isImm() const { return Kind == Immediate; }
422 bool isImm0_255() const {
423 if (Kind != Immediate)
425 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
426 if (!CE) return false;
427 int64_t Value = CE->getValue();
428 return Value >= 0 && Value < 256;
430 bool isImm0_7() const {
431 if (Kind != Immediate)
433 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
434 if (!CE) return false;
435 int64_t Value = CE->getValue();
436 return Value >= 0 && Value < 8;
438 bool isImm0_15() const {
439 if (Kind != Immediate)
441 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
442 if (!CE) return false;
443 int64_t Value = CE->getValue();
444 return Value >= 0 && Value < 16;
446 bool isImm0_31() const {
447 if (Kind != Immediate)
449 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
450 if (!CE) return false;
451 int64_t Value = CE->getValue();
452 return Value >= 0 && Value < 32;
454 bool isImm1_16() const {
455 if (Kind != Immediate)
457 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
458 if (!CE) return false;
459 int64_t Value = CE->getValue();
460 return Value > 0 && Value < 17;
462 bool isImm1_32() const {
463 if (Kind != Immediate)
465 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
466 if (!CE) return false;
467 int64_t Value = CE->getValue();
468 return Value > 0 && Value < 33;
470 bool isImm0_65535() const {
471 if (Kind != Immediate)
473 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
474 if (!CE) return false;
475 int64_t Value = CE->getValue();
476 return Value >= 0 && Value < 65536;
478 bool isImm0_65535Expr() const {
479 if (Kind != Immediate)
481 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
482 // If it's not a constant expression, it'll generate a fixup and be
484 if (!CE) return true;
485 int64_t Value = CE->getValue();
486 return Value >= 0 && Value < 65536;
488 bool isImm24bit() const {
489 if (Kind != Immediate)
491 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
492 if (!CE) return false;
493 int64_t Value = CE->getValue();
494 return Value >= 0 && Value <= 0xffffff;
496 bool isPKHLSLImm() const {
497 if (Kind != Immediate)
499 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
500 if (!CE) return false;
501 int64_t Value = CE->getValue();
502 return Value >= 0 && Value < 32;
504 bool isPKHASRImm() const {
505 if (Kind != Immediate)
507 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
508 if (!CE) return false;
509 int64_t Value = CE->getValue();
510 return Value > 0 && Value <= 32;
512 bool isARMSOImm() const {
513 if (Kind != Immediate)
515 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
516 if (!CE) return false;
517 int64_t Value = CE->getValue();
518 return ARM_AM::getSOImmVal(Value) != -1;
520 bool isT2SOImm() const {
521 if (Kind != Immediate)
523 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
524 if (!CE) return false;
525 int64_t Value = CE->getValue();
526 return ARM_AM::getT2SOImmVal(Value) != -1;
528 bool isSetEndImm() const {
529 if (Kind != Immediate)
531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
532 if (!CE) return false;
533 int64_t Value = CE->getValue();
534 return Value == 1 || Value == 0;
536 bool isReg() const { return Kind == Register; }
537 bool isRegList() const { return Kind == RegisterList; }
538 bool isDPRRegList() const { return Kind == DPRRegisterList; }
539 bool isSPRRegList() const { return Kind == SPRRegisterList; }
540 bool isToken() const { return Kind == Token; }
541 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
542 bool isMemory() const { return Kind == Memory; }
543 bool isShifterImm() const { return Kind == ShifterImmediate; }
544 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
545 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
546 bool isRotImm() const { return Kind == RotateImmediate; }
547 bool isBitfield() const { return Kind == BitfieldDescriptor; }
548 bool isMemMode2() const {
549 if (getMemAddrMode() != ARMII::AddrMode2)
552 if (getMemOffsetIsReg())
555 if (getMemNegative() &&
556 !(getMemPostindexed() || getMemPreindexed()))
559 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
560 if (!CE) return false;
561 int64_t Value = CE->getValue();
563 // The offset must be in the range 0-4095 (imm12).
564 if (Value > 4095 || Value < -4095)
569 bool isMemMode3() const {
570 if (getMemAddrMode() != ARMII::AddrMode3)
573 if (getMemOffsetIsReg()) {
574 if (getMemOffsetRegShifted())
575 return false; // No shift with offset reg allowed
579 if (getMemNegative() &&
580 !(getMemPostindexed() || getMemPreindexed()))
583 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
584 if (!CE) return false;
585 int64_t Value = CE->getValue();
587 // The offset must be in the range 0-255 (imm8).
588 if (Value > 255 || Value < -255)
593 bool isMemMode5() const {
594 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
598 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
599 if (!CE) return false;
601 // The offset must be a multiple of 4 in the range 0-1020.
602 int64_t Value = CE->getValue();
603 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
605 bool isMemMode7() const {
607 getMemPreindexed() ||
608 getMemPostindexed() ||
609 getMemOffsetIsReg() ||
614 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
615 if (!CE) return false;
622 bool isMemModeRegThumb() const {
623 if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback())
627 bool isMemModeImmThumb() const {
628 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback())
631 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
632 if (!CE) return false;
634 // The offset must be a multiple of 4 in the range 0-124.
635 uint64_t Value = CE->getValue();
636 return ((Value & 0x3) == 0 && Value <= 124);
638 bool isMSRMask() const { return Kind == MSRMask; }
639 bool isProcIFlags() const { return Kind == ProcIFlags; }
641 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
642 // Add as immediates when possible. Null MCExpr = 0.
644 Inst.addOperand(MCOperand::CreateImm(0));
645 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
646 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
648 Inst.addOperand(MCOperand::CreateExpr(Expr));
651 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
652 assert(N == 2 && "Invalid number of operands!");
653 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
654 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
655 Inst.addOperand(MCOperand::CreateReg(RegNum));
658 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
659 assert(N == 1 && "Invalid number of operands!");
660 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
663 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
664 assert(N == 1 && "Invalid number of operands!");
665 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
668 void addCCOutOperands(MCInst &Inst, unsigned N) const {
669 assert(N == 1 && "Invalid number of operands!");
670 Inst.addOperand(MCOperand::CreateReg(getReg()));
673 void addRegOperands(MCInst &Inst, unsigned N) const {
674 assert(N == 1 && "Invalid number of operands!");
675 Inst.addOperand(MCOperand::CreateReg(getReg()));
678 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
679 assert(N == 3 && "Invalid number of operands!");
680 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
681 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
682 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
683 Inst.addOperand(MCOperand::CreateImm(
684 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
687 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
688 assert(N == 2 && "Invalid number of operands!");
689 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
690 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
691 Inst.addOperand(MCOperand::CreateImm(
692 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
696 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
697 assert(N == 1 && "Invalid number of operands!");
698 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
702 void addRegListOperands(MCInst &Inst, unsigned N) const {
703 assert(N == 1 && "Invalid number of operands!");
704 const SmallVectorImpl<unsigned> &RegList = getRegList();
705 for (SmallVectorImpl<unsigned>::const_iterator
706 I = RegList.begin(), E = RegList.end(); I != E; ++I)
707 Inst.addOperand(MCOperand::CreateReg(*I));
710 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
711 addRegListOperands(Inst, N);
714 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
715 addRegListOperands(Inst, N);
718 void addRotImmOperands(MCInst &Inst, unsigned N) const {
719 assert(N == 1 && "Invalid number of operands!");
720 // Encoded as val>>3. The printer handles display as 8, 16, 24.
721 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
724 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
725 assert(N == 1 && "Invalid number of operands!");
726 // Munge the lsb/width into a bitfield mask.
727 unsigned lsb = Bitfield.LSB;
728 unsigned width = Bitfield.Width;
729 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
730 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
731 (32 - (lsb + width)));
732 Inst.addOperand(MCOperand::CreateImm(Mask));
735 void addImmOperands(MCInst &Inst, unsigned N) const {
736 assert(N == 1 && "Invalid number of operands!");
737 addExpr(Inst, getImm());
740 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
741 assert(N == 1 && "Invalid number of operands!");
742 addExpr(Inst, getImm());
745 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
746 assert(N == 1 && "Invalid number of operands!");
747 addExpr(Inst, getImm());
750 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
751 assert(N == 1 && "Invalid number of operands!");
752 addExpr(Inst, getImm());
755 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
756 assert(N == 1 && "Invalid number of operands!");
757 addExpr(Inst, getImm());
760 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
761 assert(N == 1 && "Invalid number of operands!");
762 // The constant encodes as the immediate-1, and we store in the instruction
763 // the bits as encoded, so subtract off one here.
764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
768 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
769 assert(N == 1 && "Invalid number of operands!");
770 // The constant encodes as the immediate-1, and we store in the instruction
771 // the bits as encoded, so subtract off one here.
772 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
773 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
776 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
777 assert(N == 1 && "Invalid number of operands!");
778 addExpr(Inst, getImm());
781 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
782 assert(N == 1 && "Invalid number of operands!");
783 addExpr(Inst, getImm());
786 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
787 assert(N == 1 && "Invalid number of operands!");
788 addExpr(Inst, getImm());
791 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
792 assert(N == 1 && "Invalid number of operands!");
793 addExpr(Inst, getImm());
796 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
797 assert(N == 1 && "Invalid number of operands!");
798 // An ASR value of 32 encodes as 0, so that's how we want to add it to
799 // the instruction as well.
800 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
801 int Val = CE->getValue();
802 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
805 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
806 assert(N == 1 && "Invalid number of operands!");
807 addExpr(Inst, getImm());
810 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
811 assert(N == 1 && "Invalid number of operands!");
812 addExpr(Inst, getImm());
815 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
816 assert(N == 1 && "Invalid number of operands!");
817 addExpr(Inst, getImm());
820 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
821 assert(N == 1 && "Invalid number of operands!");
822 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
825 void addMemMode7Operands(MCInst &Inst, unsigned N) const {
826 assert(N == 1 && isMemMode7() && "Invalid number of operands!");
827 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
829 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
831 assert((CE || CE->getValue() == 0) &&
832 "No offset operand support in mode 7");
835 void addMemMode2Operands(MCInst &Inst, unsigned N) const {
836 assert(isMemMode2() && "Invalid mode or number of operands!");
837 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
838 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
840 if (getMemOffsetIsReg()) {
841 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
843 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
844 ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
845 int64_t ShiftAmount = 0;
847 if (getMemOffsetRegShifted()) {
848 ShOpc = getMemShiftType();
849 const MCConstantExpr *CE =
850 dyn_cast<MCConstantExpr>(getMemShiftAmount());
851 ShiftAmount = CE->getValue();
854 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
859 // Create a operand placeholder to always yield the same number of operands.
860 Inst.addOperand(MCOperand::CreateReg(0));
862 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
864 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
865 assert(CE && "Non-constant mode 2 offset operand!");
866 int64_t Offset = CE->getValue();
869 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
870 Offset, ARM_AM::no_shift, IdxMode)));
872 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
873 -Offset, ARM_AM::no_shift, IdxMode)));
876 void addMemMode3Operands(MCInst &Inst, unsigned N) const {
877 assert(isMemMode3() && "Invalid mode or number of operands!");
878 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
879 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
881 if (getMemOffsetIsReg()) {
882 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
884 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
885 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(AMOpc, 0,
890 // Create a operand placeholder to always yield the same number of operands.
891 Inst.addOperand(MCOperand::CreateReg(0));
893 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
895 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
896 assert(CE && "Non-constant mode 3 offset operand!");
897 int64_t Offset = CE->getValue();
900 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::add,
903 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::sub,
907 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
908 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
910 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
911 assert(!getMemOffsetIsReg() && "Invalid mode 5 operand");
913 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
916 assert(CE && "Non-constant mode 5 offset operand!");
918 // The MCInst offset operand doesn't include the low two bits (like
919 // the instruction encoding).
920 int64_t Offset = CE->getValue() / 4;
922 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
925 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
929 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
930 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
931 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
932 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
935 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
936 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
937 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
938 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
939 assert(CE && "Non-constant mode offset operand!");
940 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
943 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
944 assert(N == 1 && "Invalid number of operands!");
945 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
948 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
949 assert(N == 1 && "Invalid number of operands!");
950 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
953 virtual void print(raw_ostream &OS) const;
955 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
956 ARMOperand *Op = new ARMOperand(CondCode);
963 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
964 ARMOperand *Op = new ARMOperand(CoprocNum);
965 Op->Cop.Val = CopVal;
971 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
972 ARMOperand *Op = new ARMOperand(CoprocReg);
973 Op->Cop.Val = CopVal;
979 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
980 ARMOperand *Op = new ARMOperand(CCOut);
981 Op->Reg.RegNum = RegNum;
987 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
988 ARMOperand *Op = new ARMOperand(Token);
989 Op->Tok.Data = Str.data();
990 Op->Tok.Length = Str.size();
996 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
997 ARMOperand *Op = new ARMOperand(Register);
998 Op->Reg.RegNum = RegNum;
1004 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1009 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1010 Op->RegShiftedReg.ShiftTy = ShTy;
1011 Op->RegShiftedReg.SrcReg = SrcReg;
1012 Op->RegShiftedReg.ShiftReg = ShiftReg;
1013 Op->RegShiftedReg.ShiftImm = ShiftImm;
1019 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1023 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1024 Op->RegShiftedImm.ShiftTy = ShTy;
1025 Op->RegShiftedImm.SrcReg = SrcReg;
1026 Op->RegShiftedImm.ShiftImm = ShiftImm;
1032 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1034 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1035 Op->ShifterImm.isASR = isASR;
1036 Op->ShifterImm.Imm = Imm;
1042 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1043 ARMOperand *Op = new ARMOperand(RotateImmediate);
1044 Op->RotImm.Imm = Imm;
1050 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1052 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1053 Op->Bitfield.LSB = LSB;
1054 Op->Bitfield.Width = Width;
1061 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1062 SMLoc StartLoc, SMLoc EndLoc) {
1063 KindTy Kind = RegisterList;
1065 if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
1066 contains(Regs.front().first))
1067 Kind = DPRRegisterList;
1068 else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1069 contains(Regs.front().first))
1070 Kind = SPRRegisterList;
1072 ARMOperand *Op = new ARMOperand(Kind);
1073 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1074 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1075 Op->Registers.push_back(I->first);
1076 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1077 Op->StartLoc = StartLoc;
1078 Op->EndLoc = EndLoc;
1082 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1083 ARMOperand *Op = new ARMOperand(Immediate);
1090 static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
1091 bool OffsetIsReg, const MCExpr *Offset,
1092 int OffsetRegNum, bool OffsetRegShifted,
1093 enum ARM_AM::ShiftOpc ShiftType,
1094 const MCExpr *ShiftAmount, bool Preindexed,
1095 bool Postindexed, bool Negative, bool Writeback,
1097 assert((OffsetRegNum == -1 || OffsetIsReg) &&
1098 "OffsetRegNum must imply OffsetIsReg!");
1099 assert((!OffsetRegShifted || OffsetIsReg) &&
1100 "OffsetRegShifted must imply OffsetIsReg!");
1101 assert((Offset || OffsetIsReg) &&
1102 "Offset must exists unless register offset is used!");
1103 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
1104 "Cannot have shift amount without shifted register offset!");
1105 assert((!Offset || !OffsetIsReg) &&
1106 "Cannot have expression offset and register offset!");
1108 ARMOperand *Op = new ARMOperand(Memory);
1109 Op->Mem.AddrMode = AddrMode;
1110 Op->Mem.BaseRegNum = BaseRegNum;
1111 Op->Mem.OffsetIsReg = OffsetIsReg;
1113 Op->Mem.Offset.RegNum = OffsetRegNum;
1115 Op->Mem.Offset.Value = Offset;
1116 Op->Mem.OffsetRegShifted = OffsetRegShifted;
1117 Op->Mem.ShiftType = ShiftType;
1118 Op->Mem.ShiftAmount = ShiftAmount;
1119 Op->Mem.Preindexed = Preindexed;
1120 Op->Mem.Postindexed = Postindexed;
1121 Op->Mem.Negative = Negative;
1122 Op->Mem.Writeback = Writeback;
1129 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1130 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1131 Op->MBOpt.Val = Opt;
1137 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1138 ARMOperand *Op = new ARMOperand(ProcIFlags);
1139 Op->IFlags.Val = IFlags;
1145 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1146 ARMOperand *Op = new ARMOperand(MSRMask);
1147 Op->MMask.Val = MMask;
1154 } // end anonymous namespace.
1156 void ARMOperand::print(raw_ostream &OS) const {
1159 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1162 OS << "<ccout " << getReg() << ">";
1165 OS << "<coprocessor number: " << getCoproc() << ">";
1168 OS << "<coprocessor register: " << getCoproc() << ">";
1171 OS << "<mask: " << getMSRMask() << ">";
1174 getImm()->print(OS);
1177 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1181 << "am:" << ARMII::AddrModeToString(getMemAddrMode())
1182 << " base:" << getMemBaseRegNum();
1183 if (getMemOffsetIsReg()) {
1184 OS << " offset:<register " << getMemOffsetRegNum();
1185 if (getMemOffsetRegShifted()) {
1186 OS << " offset-shift-type:" << getMemShiftType();
1187 OS << " offset-shift-amount:" << *getMemShiftAmount();
1190 OS << " offset:" << *getMemOffset();
1192 if (getMemOffsetIsReg())
1193 OS << " (offset-is-reg)";
1194 if (getMemPreindexed())
1195 OS << " (pre-indexed)";
1196 if (getMemPostindexed())
1197 OS << " (post-indexed)";
1198 if (getMemNegative())
1199 OS << " (negative)";
1200 if (getMemWriteback())
1201 OS << " (writeback)";
1205 OS << "<ARM_PROC::";
1206 unsigned IFlags = getProcIFlags();
1207 for (int i=2; i >= 0; --i)
1208 if (IFlags & (1 << i))
1209 OS << ARM_PROC::IFlagsToString(1 << i);
1214 OS << "<register " << getReg() << ">";
1216 case ShifterImmediate:
1217 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1218 << " #" << ShifterImm.Imm << ">";
1220 case ShiftedRegister:
1221 OS << "<so_reg_reg "
1222 << RegShiftedReg.SrcReg
1223 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1224 << ", " << RegShiftedReg.ShiftReg << ", "
1225 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1228 case ShiftedImmediate:
1229 OS << "<so_reg_imm "
1230 << RegShiftedImm.SrcReg
1231 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1232 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1235 case RotateImmediate:
1236 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1238 case BitfieldDescriptor:
1239 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1240 << ", width: " << Bitfield.Width << ">";
1243 case DPRRegisterList:
1244 case SPRRegisterList: {
1245 OS << "<register_list ";
1247 const SmallVectorImpl<unsigned> &RegList = getRegList();
1248 for (SmallVectorImpl<unsigned>::const_iterator
1249 I = RegList.begin(), E = RegList.end(); I != E; ) {
1251 if (++I < E) OS << ", ";
1258 OS << "'" << getToken() << "'";
1263 /// @name Auto-generated Match Functions
1266 static unsigned MatchRegisterName(StringRef Name);
1270 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1271 SMLoc &StartLoc, SMLoc &EndLoc) {
1272 RegNo = tryParseRegister();
1274 return (RegNo == (unsigned)-1);
1277 /// Try to parse a register name. The token must be an Identifier when called,
1278 /// and if it is a register name the token is eaten and the register number is
1279 /// returned. Otherwise return -1.
1281 int ARMAsmParser::tryParseRegister() {
1282 const AsmToken &Tok = Parser.getTok();
1283 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1285 // FIXME: Validate register for the current architecture; we have to do
1286 // validation later, so maybe there is no need for this here.
1287 std::string upperCase = Tok.getString().str();
1288 std::string lowerCase = LowercaseString(upperCase);
1289 unsigned RegNum = MatchRegisterName(lowerCase);
1291 RegNum = StringSwitch<unsigned>(lowerCase)
1292 .Case("r13", ARM::SP)
1293 .Case("r14", ARM::LR)
1294 .Case("r15", ARM::PC)
1295 .Case("ip", ARM::R12)
1298 if (!RegNum) return -1;
1300 Parser.Lex(); // Eat identifier token.
1304 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1305 // If a recoverable error occurs, return 1. If an irrecoverable error
1306 // occurs, return -1. An irrecoverable error is one where tokens have been
1307 // consumed in the process of trying to parse the shifter (i.e., when it is
1308 // indeed a shifter operand, but malformed).
1309 int ARMAsmParser::tryParseShiftRegister(
1310 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1311 SMLoc S = Parser.getTok().getLoc();
1312 const AsmToken &Tok = Parser.getTok();
1313 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1315 std::string upperCase = Tok.getString().str();
1316 std::string lowerCase = LowercaseString(upperCase);
1317 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1318 .Case("lsl", ARM_AM::lsl)
1319 .Case("lsr", ARM_AM::lsr)
1320 .Case("asr", ARM_AM::asr)
1321 .Case("ror", ARM_AM::ror)
1322 .Case("rrx", ARM_AM::rrx)
1323 .Default(ARM_AM::no_shift);
1325 if (ShiftTy == ARM_AM::no_shift)
1328 Parser.Lex(); // Eat the operator.
1330 // The source register for the shift has already been added to the
1331 // operand list, so we need to pop it off and combine it into the shifted
1332 // register operand instead.
1333 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1334 if (!PrevOp->isReg())
1335 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1336 int SrcReg = PrevOp->getReg();
1339 if (ShiftTy == ARM_AM::rrx) {
1340 // RRX Doesn't have an explicit shift amount. The encoder expects
1341 // the shift register to be the same as the source register. Seems odd,
1345 // Figure out if this is shifted by a constant or a register (for non-RRX).
1346 if (Parser.getTok().is(AsmToken::Hash)) {
1347 Parser.Lex(); // Eat hash.
1348 SMLoc ImmLoc = Parser.getTok().getLoc();
1349 const MCExpr *ShiftExpr = 0;
1350 if (getParser().ParseExpression(ShiftExpr)) {
1351 Error(ImmLoc, "invalid immediate shift value");
1354 // The expression must be evaluatable as an immediate.
1355 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1357 Error(ImmLoc, "invalid immediate shift value");
1360 // Range check the immediate.
1361 // lsl, ror: 0 <= imm <= 31
1362 // lsr, asr: 0 <= imm <= 32
1363 Imm = CE->getValue();
1365 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1366 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1367 Error(ImmLoc, "immediate shift value out of range");
1370 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1371 ShiftReg = tryParseRegister();
1372 SMLoc L = Parser.getTok().getLoc();
1373 if (ShiftReg == -1) {
1374 Error (L, "expected immediate or register in shift operand");
1378 Error (Parser.getTok().getLoc(),
1379 "expected immediate or register in shift operand");
1384 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1385 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1387 S, Parser.getTok().getLoc()));
1389 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1390 S, Parser.getTok().getLoc()));
1396 /// Try to parse a register name. The token must be an Identifier when called.
1397 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1398 /// if there is a "writeback". 'true' if it's not a register.
1400 /// TODO this is likely to change to allow different register types and or to
1401 /// parse for a specific register type.
1403 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1404 SMLoc S = Parser.getTok().getLoc();
1405 int RegNo = tryParseRegister();
1409 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1411 const AsmToken &ExclaimTok = Parser.getTok();
1412 if (ExclaimTok.is(AsmToken::Exclaim)) {
1413 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1414 ExclaimTok.getLoc()));
1415 Parser.Lex(); // Eat exclaim token
1421 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1422 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1424 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1425 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1427 switch (Name.size()) {
1430 if (Name[0] != CoprocOp)
1447 if (Name[0] != CoprocOp || Name[1] != '1')
1451 case '0': return 10;
1452 case '1': return 11;
1453 case '2': return 12;
1454 case '3': return 13;
1455 case '4': return 14;
1456 case '5': return 15;
1464 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1465 /// token must be an Identifier when called, and if it is a coprocessor
1466 /// number, the token is eaten and the operand is added to the operand list.
1467 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1468 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1469 SMLoc S = Parser.getTok().getLoc();
1470 const AsmToken &Tok = Parser.getTok();
1471 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1473 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1475 return MatchOperand_NoMatch;
1477 Parser.Lex(); // Eat identifier token.
1478 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1479 return MatchOperand_Success;
1482 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1483 /// token must be an Identifier when called, and if it is a coprocessor
1484 /// number, the token is eaten and the operand is added to the operand list.
1485 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1486 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1487 SMLoc S = Parser.getTok().getLoc();
1488 const AsmToken &Tok = Parser.getTok();
1489 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1491 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1493 return MatchOperand_NoMatch;
1495 Parser.Lex(); // Eat identifier token.
1496 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1497 return MatchOperand_Success;
1500 /// Parse a register list, return it if successful else return null. The first
1501 /// token must be a '{' when called.
1503 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1504 assert(Parser.getTok().is(AsmToken::LCurly) &&
1505 "Token is not a Left Curly Brace");
1506 SMLoc S = Parser.getTok().getLoc();
1508 // Read the rest of the registers in the list.
1509 unsigned PrevRegNum = 0;
1510 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1513 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1514 Parser.Lex(); // Eat non-identifier token.
1516 const AsmToken &RegTok = Parser.getTok();
1517 SMLoc RegLoc = RegTok.getLoc();
1518 if (RegTok.isNot(AsmToken::Identifier)) {
1519 Error(RegLoc, "register expected");
1523 int RegNum = tryParseRegister();
1525 Error(RegLoc, "register expected");
1530 int Reg = PrevRegNum;
1533 Registers.push_back(std::make_pair(Reg, RegLoc));
1534 } while (Reg != RegNum);
1536 Registers.push_back(std::make_pair(RegNum, RegLoc));
1539 PrevRegNum = RegNum;
1540 } while (Parser.getTok().is(AsmToken::Comma) ||
1541 Parser.getTok().is(AsmToken::Minus));
1543 // Process the right curly brace of the list.
1544 const AsmToken &RCurlyTok = Parser.getTok();
1545 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1546 Error(RCurlyTok.getLoc(), "'}' expected");
1550 SMLoc E = RCurlyTok.getLoc();
1551 Parser.Lex(); // Eat right curly brace token.
1553 // Verify the register list.
1554 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1555 RI = Registers.begin(), RE = Registers.end();
1557 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1558 bool EmittedWarning = false;
1560 DenseMap<unsigned, bool> RegMap;
1561 RegMap[HighRegNum] = true;
1563 for (++RI; RI != RE; ++RI) {
1564 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1565 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1568 Error(RegInfo.second, "register duplicated in register list");
1572 if (!EmittedWarning && Reg < HighRegNum)
1573 Warning(RegInfo.second,
1574 "register not in ascending order in register list");
1577 HighRegNum = std::max(Reg, HighRegNum);
1580 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1584 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1585 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1586 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1587 SMLoc S = Parser.getTok().getLoc();
1588 const AsmToken &Tok = Parser.getTok();
1589 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1590 StringRef OptStr = Tok.getString();
1592 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1593 .Case("sy", ARM_MB::SY)
1594 .Case("st", ARM_MB::ST)
1595 .Case("sh", ARM_MB::ISH)
1596 .Case("ish", ARM_MB::ISH)
1597 .Case("shst", ARM_MB::ISHST)
1598 .Case("ishst", ARM_MB::ISHST)
1599 .Case("nsh", ARM_MB::NSH)
1600 .Case("un", ARM_MB::NSH)
1601 .Case("nshst", ARM_MB::NSHST)
1602 .Case("unst", ARM_MB::NSHST)
1603 .Case("osh", ARM_MB::OSH)
1604 .Case("oshst", ARM_MB::OSHST)
1608 return MatchOperand_NoMatch;
1610 Parser.Lex(); // Eat identifier token.
1611 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1612 return MatchOperand_Success;
1615 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1616 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1617 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1618 SMLoc S = Parser.getTok().getLoc();
1619 const AsmToken &Tok = Parser.getTok();
1620 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1621 StringRef IFlagsStr = Tok.getString();
1623 unsigned IFlags = 0;
1624 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1625 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1626 .Case("a", ARM_PROC::A)
1627 .Case("i", ARM_PROC::I)
1628 .Case("f", ARM_PROC::F)
1631 // If some specific iflag is already set, it means that some letter is
1632 // present more than once, this is not acceptable.
1633 if (Flag == ~0U || (IFlags & Flag))
1634 return MatchOperand_NoMatch;
1639 Parser.Lex(); // Eat identifier token.
1640 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1641 return MatchOperand_Success;
1644 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1645 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1646 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1647 SMLoc S = Parser.getTok().getLoc();
1648 const AsmToken &Tok = Parser.getTok();
1649 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1650 StringRef Mask = Tok.getString();
1652 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1653 size_t Start = 0, Next = Mask.find('_');
1654 StringRef Flags = "";
1655 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1656 if (Next != StringRef::npos)
1657 Flags = Mask.slice(Next+1, Mask.size());
1659 // FlagsVal contains the complete mask:
1661 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1662 unsigned FlagsVal = 0;
1664 if (SpecReg == "apsr") {
1665 FlagsVal = StringSwitch<unsigned>(Flags)
1666 .Case("nzcvq", 0x8) // same as CPSR_f
1667 .Case("g", 0x4) // same as CPSR_s
1668 .Case("nzcvqg", 0xc) // same as CPSR_fs
1671 if (FlagsVal == ~0U) {
1673 return MatchOperand_NoMatch;
1675 FlagsVal = 0; // No flag
1677 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1678 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1680 for (int i = 0, e = Flags.size(); i != e; ++i) {
1681 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1688 // If some specific flag is already set, it means that some letter is
1689 // present more than once, this is not acceptable.
1690 if (FlagsVal == ~0U || (FlagsVal & Flag))
1691 return MatchOperand_NoMatch;
1694 } else // No match for special register.
1695 return MatchOperand_NoMatch;
1697 // Special register without flags are equivalent to "fc" flags.
1701 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1702 if (SpecReg == "spsr")
1705 Parser.Lex(); // Eat identifier token.
1706 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1707 return MatchOperand_Success;
1710 /// parseMemMode2Operand - Try to parse memory addressing mode 2 operand.
1711 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1712 parseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1713 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1715 if (parseMemory(Operands, ARMII::AddrMode2))
1716 return MatchOperand_NoMatch;
1718 return MatchOperand_Success;
1721 /// parseMemMode3Operand - Try to parse memory addressing mode 3 operand.
1722 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1723 parseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1724 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1726 if (parseMemory(Operands, ARMII::AddrMode3))
1727 return MatchOperand_NoMatch;
1729 return MatchOperand_Success;
1732 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1733 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1734 int Low, int High) {
1735 const AsmToken &Tok = Parser.getTok();
1736 if (Tok.isNot(AsmToken::Identifier)) {
1737 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1738 return MatchOperand_ParseFail;
1740 StringRef ShiftName = Tok.getString();
1741 std::string LowerOp = LowercaseString(Op);
1742 std::string UpperOp = UppercaseString(Op);
1743 if (ShiftName != LowerOp && ShiftName != UpperOp) {
1744 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1745 return MatchOperand_ParseFail;
1747 Parser.Lex(); // Eat shift type token.
1749 // There must be a '#' and a shift amount.
1750 if (Parser.getTok().isNot(AsmToken::Hash)) {
1751 Error(Parser.getTok().getLoc(), "'#' expected");
1752 return MatchOperand_ParseFail;
1754 Parser.Lex(); // Eat hash token.
1756 const MCExpr *ShiftAmount;
1757 SMLoc Loc = Parser.getTok().getLoc();
1758 if (getParser().ParseExpression(ShiftAmount)) {
1759 Error(Loc, "illegal expression");
1760 return MatchOperand_ParseFail;
1762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1764 Error(Loc, "constant expression expected");
1765 return MatchOperand_ParseFail;
1767 int Val = CE->getValue();
1768 if (Val < Low || Val > High) {
1769 Error(Loc, "immediate value out of range");
1770 return MatchOperand_ParseFail;
1773 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1775 return MatchOperand_Success;
1778 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1779 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1780 const AsmToken &Tok = Parser.getTok();
1781 SMLoc S = Tok.getLoc();
1782 if (Tok.isNot(AsmToken::Identifier)) {
1783 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1784 return MatchOperand_ParseFail;
1786 int Val = StringSwitch<int>(Tok.getString())
1790 Parser.Lex(); // Eat the token.
1793 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1794 return MatchOperand_ParseFail;
1796 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1798 S, Parser.getTok().getLoc()));
1799 return MatchOperand_Success;
1802 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1803 /// instructions. Legal values are:
1804 /// lsl #n 'n' in [0,31]
1805 /// asr #n 'n' in [1,32]
1806 /// n == 32 encoded as n == 0.
1807 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1808 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1809 const AsmToken &Tok = Parser.getTok();
1810 SMLoc S = Tok.getLoc();
1811 if (Tok.isNot(AsmToken::Identifier)) {
1812 Error(S, "shift operator 'asr' or 'lsl' expected");
1813 return MatchOperand_ParseFail;
1815 StringRef ShiftName = Tok.getString();
1817 if (ShiftName == "lsl" || ShiftName == "LSL")
1819 else if (ShiftName == "asr" || ShiftName == "ASR")
1822 Error(S, "shift operator 'asr' or 'lsl' expected");
1823 return MatchOperand_ParseFail;
1825 Parser.Lex(); // Eat the operator.
1827 // A '#' and a shift amount.
1828 if (Parser.getTok().isNot(AsmToken::Hash)) {
1829 Error(Parser.getTok().getLoc(), "'#' expected");
1830 return MatchOperand_ParseFail;
1832 Parser.Lex(); // Eat hash token.
1834 const MCExpr *ShiftAmount;
1835 SMLoc E = Parser.getTok().getLoc();
1836 if (getParser().ParseExpression(ShiftAmount)) {
1837 Error(E, "malformed shift expression");
1838 return MatchOperand_ParseFail;
1840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1842 Error(E, "shift amount must be an immediate");
1843 return MatchOperand_ParseFail;
1846 int64_t Val = CE->getValue();
1848 // Shift amount must be in [1,32]
1849 if (Val < 1 || Val > 32) {
1850 Error(E, "'asr' shift amount must be in range [1,32]");
1851 return MatchOperand_ParseFail;
1853 // asr #32 encoded as asr #0.
1854 if (Val == 32) Val = 0;
1856 // Shift amount must be in [1,32]
1857 if (Val < 0 || Val > 31) {
1858 Error(E, "'lsr' shift amount must be in range [0,31]");
1859 return MatchOperand_ParseFail;
1863 E = Parser.getTok().getLoc();
1864 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1866 return MatchOperand_Success;
1869 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
1870 /// of instructions. Legal values are:
1871 /// ror #n 'n' in {0, 8, 16, 24}
1872 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1873 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1874 const AsmToken &Tok = Parser.getTok();
1875 SMLoc S = Tok.getLoc();
1876 if (Tok.isNot(AsmToken::Identifier)) {
1877 Error(S, "rotate operator 'ror' expected");
1878 return MatchOperand_ParseFail;
1880 StringRef ShiftName = Tok.getString();
1881 if (ShiftName != "ror" && ShiftName != "ROR") {
1882 Error(S, "rotate operator 'ror' expected");
1883 return MatchOperand_ParseFail;
1885 Parser.Lex(); // Eat the operator.
1887 // A '#' and a rotate amount.
1888 if (Parser.getTok().isNot(AsmToken::Hash)) {
1889 Error(Parser.getTok().getLoc(), "'#' expected");
1890 return MatchOperand_ParseFail;
1892 Parser.Lex(); // Eat hash token.
1894 const MCExpr *ShiftAmount;
1895 SMLoc E = Parser.getTok().getLoc();
1896 if (getParser().ParseExpression(ShiftAmount)) {
1897 Error(E, "malformed rotate expression");
1898 return MatchOperand_ParseFail;
1900 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1902 Error(E, "rotate amount must be an immediate");
1903 return MatchOperand_ParseFail;
1906 int64_t Val = CE->getValue();
1907 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
1908 // normally, zero is represented in asm by omitting the rotate operand
1910 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
1911 Error(E, "'ror' rotate amount must be 8, 16, or 24");
1912 return MatchOperand_ParseFail;
1915 E = Parser.getTok().getLoc();
1916 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
1918 return MatchOperand_Success;
1921 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1922 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1923 SMLoc S = Parser.getTok().getLoc();
1924 // The bitfield descriptor is really two operands, the LSB and the width.
1925 if (Parser.getTok().isNot(AsmToken::Hash)) {
1926 Error(Parser.getTok().getLoc(), "'#' expected");
1927 return MatchOperand_ParseFail;
1929 Parser.Lex(); // Eat hash token.
1931 const MCExpr *LSBExpr;
1932 SMLoc E = Parser.getTok().getLoc();
1933 if (getParser().ParseExpression(LSBExpr)) {
1934 Error(E, "malformed immediate expression");
1935 return MatchOperand_ParseFail;
1937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
1939 Error(E, "'lsb' operand must be an immediate");
1940 return MatchOperand_ParseFail;
1943 int64_t LSB = CE->getValue();
1944 // The LSB must be in the range [0,31]
1945 if (LSB < 0 || LSB > 31) {
1946 Error(E, "'lsb' operand must be in the range [0,31]");
1947 return MatchOperand_ParseFail;
1949 E = Parser.getTok().getLoc();
1951 // Expect another immediate operand.
1952 if (Parser.getTok().isNot(AsmToken::Comma)) {
1953 Error(Parser.getTok().getLoc(), "too few operands");
1954 return MatchOperand_ParseFail;
1956 Parser.Lex(); // Eat hash token.
1957 if (Parser.getTok().isNot(AsmToken::Hash)) {
1958 Error(Parser.getTok().getLoc(), "'#' expected");
1959 return MatchOperand_ParseFail;
1961 Parser.Lex(); // Eat hash token.
1963 const MCExpr *WidthExpr;
1964 if (getParser().ParseExpression(WidthExpr)) {
1965 Error(E, "malformed immediate expression");
1966 return MatchOperand_ParseFail;
1968 CE = dyn_cast<MCConstantExpr>(WidthExpr);
1970 Error(E, "'width' operand must be an immediate");
1971 return MatchOperand_ParseFail;
1974 int64_t Width = CE->getValue();
1975 // The LSB must be in the range [1,32-lsb]
1976 if (Width < 1 || Width > 32 - LSB) {
1977 Error(E, "'width' operand must be in the range [1,32-lsb]");
1978 return MatchOperand_ParseFail;
1980 E = Parser.getTok().getLoc();
1982 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
1984 return MatchOperand_Success;
1987 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1988 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1989 /// when they refer multiple MIOperands inside a single one.
1991 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1992 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1993 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1995 // Create a writeback register dummy placeholder.
1996 Inst.addOperand(MCOperand::CreateImm(0));
1998 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1999 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2003 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2004 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2005 /// when they refer multiple MIOperands inside a single one.
2007 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2008 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2009 // Create a writeback register dummy placeholder.
2010 Inst.addOperand(MCOperand::CreateImm(0));
2011 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2012 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
2013 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2017 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2018 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2019 /// when they refer multiple MIOperands inside a single one.
2021 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2022 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2023 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2025 // Create a writeback register dummy placeholder.
2026 Inst.addOperand(MCOperand::CreateImm(0));
2028 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
2029 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2033 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2034 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2035 /// when they refer multiple MIOperands inside a single one.
2037 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2038 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2039 // Create a writeback register dummy placeholder.
2040 Inst.addOperand(MCOperand::CreateImm(0));
2041 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2042 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
2043 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2047 /// Parse an ARM memory expression, return false if successful else return true
2048 /// or an error. The first token must be a '[' when called.
2050 /// TODO Only preindexing and postindexing addressing are started, unindexed
2051 /// with option, etc are still to do.
2053 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2054 ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
2056 assert(Parser.getTok().is(AsmToken::LBrac) &&
2057 "Token is not a Left Bracket");
2058 S = Parser.getTok().getLoc();
2059 Parser.Lex(); // Eat left bracket token.
2061 const AsmToken &BaseRegTok = Parser.getTok();
2062 if (BaseRegTok.isNot(AsmToken::Identifier)) {
2063 Error(BaseRegTok.getLoc(), "register expected");
2066 int BaseRegNum = tryParseRegister();
2067 if (BaseRegNum == -1) {
2068 Error(BaseRegTok.getLoc(), "register expected");
2072 // The next token must either be a comma or a closing bracket.
2073 const AsmToken &Tok = Parser.getTok();
2074 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2077 bool Preindexed = false;
2078 bool Postindexed = false;
2079 bool OffsetIsReg = false;
2080 bool Negative = false;
2081 bool Writeback = false;
2082 ARMOperand *WBOp = 0;
2083 int OffsetRegNum = -1;
2084 bool OffsetRegShifted = false;
2085 enum ARM_AM::ShiftOpc ShiftType = ARM_AM::lsl;
2086 const MCExpr *ShiftAmount = 0;
2087 const MCExpr *Offset = 0;
2089 // First look for preindexed address forms, that is after the "[Rn" we now
2090 // have to see if the next token is a comma.
2091 if (Tok.is(AsmToken::Comma)) {
2093 Parser.Lex(); // Eat comma token.
2095 if (parseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
2096 Offset, OffsetIsReg, OffsetRegNum, E))
2098 const AsmToken &RBracTok = Parser.getTok();
2099 if (RBracTok.isNot(AsmToken::RBrac)) {
2100 Error(RBracTok.getLoc(), "']' expected");
2103 E = RBracTok.getLoc();
2104 Parser.Lex(); // Eat right bracket token.
2106 const AsmToken &ExclaimTok = Parser.getTok();
2107 if (ExclaimTok.is(AsmToken::Exclaim)) {
2108 // None of addrmode3 instruction uses "!"
2109 if (AddrMode == ARMII::AddrMode3)
2112 WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
2113 ExclaimTok.getLoc());
2115 Parser.Lex(); // Eat exclaim token
2116 } else { // In addressing mode 2, pre-indexed mode always end with "!"
2117 if (AddrMode == ARMII::AddrMode2)
2121 // The "[Rn" we have so far was not followed by a comma.
2123 // If there's anything other than the right brace, this is a post indexing
2126 Parser.Lex(); // Eat right bracket token.
2128 const AsmToken &NextTok = Parser.getTok();
2130 if (NextTok.isNot(AsmToken::EndOfStatement)) {
2134 if (NextTok.isNot(AsmToken::Comma)) {
2135 Error(NextTok.getLoc(), "',' expected");
2139 Parser.Lex(); // Eat comma token.
2141 if (parseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
2142 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
2148 // Force Offset to exist if used.
2151 Offset = MCConstantExpr::Create(0, getContext());
2153 if (AddrMode == ARMII::AddrMode3 && OffsetRegShifted) {
2154 Error(E, "shift amount not supported");
2159 Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
2160 Offset, OffsetRegNum, OffsetRegShifted,
2161 ShiftType, ShiftAmount, Preindexed,
2162 Postindexed, Negative, Writeback, S, E));
2164 Operands.push_back(WBOp);
2169 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
2170 /// we will parse the following (were +/- means that a plus or minus is
2175 /// we return false on success or an error otherwise.
2176 bool ARMAsmParser::parseMemoryOffsetReg(bool &Negative,
2177 bool &OffsetRegShifted,
2178 enum ARM_AM::ShiftOpc &ShiftType,
2179 const MCExpr *&ShiftAmount,
2180 const MCExpr *&Offset,
2185 OffsetRegShifted = false;
2186 OffsetIsReg = false;
2188 const AsmToken &NextTok = Parser.getTok();
2189 E = NextTok.getLoc();
2190 if (NextTok.is(AsmToken::Plus))
2191 Parser.Lex(); // Eat plus token.
2192 else if (NextTok.is(AsmToken::Minus)) {
2194 Parser.Lex(); // Eat minus token
2196 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
2197 const AsmToken &OffsetRegTok = Parser.getTok();
2198 if (OffsetRegTok.is(AsmToken::Identifier)) {
2199 SMLoc CurLoc = OffsetRegTok.getLoc();
2200 OffsetRegNum = tryParseRegister();
2201 if (OffsetRegNum != -1) {
2207 // If we parsed a register as the offset then there can be a shift after that.
2208 if (OffsetRegNum != -1) {
2209 // Look for a comma then a shift
2210 const AsmToken &Tok = Parser.getTok();
2211 if (Tok.is(AsmToken::Comma)) {
2212 Parser.Lex(); // Eat comma token.
2214 const AsmToken &Tok = Parser.getTok();
2215 if (parseShift(ShiftType, ShiftAmount, E))
2216 return Error(Tok.getLoc(), "shift expected");
2217 OffsetRegShifted = true;
2220 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
2221 // Look for #offset following the "[Rn," or "[Rn],"
2222 const AsmToken &HashTok = Parser.getTok();
2223 if (HashTok.isNot(AsmToken::Hash))
2224 return Error(HashTok.getLoc(), "'#' expected");
2226 Parser.Lex(); // Eat hash token.
2228 if (getParser().ParseExpression(Offset))
2230 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2235 /// parseShift as one of these two:
2236 /// ( lsl | lsr | asr | ror ) , # shift_amount
2238 /// and returns true if it parses a shift otherwise it returns false.
2239 bool ARMAsmParser::parseShift(ARM_AM::ShiftOpc &St,
2240 const MCExpr *&ShiftAmount, SMLoc &E) {
2241 const AsmToken &Tok = Parser.getTok();
2242 if (Tok.isNot(AsmToken::Identifier))
2244 StringRef ShiftName = Tok.getString();
2245 if (ShiftName == "lsl" || ShiftName == "LSL")
2247 else if (ShiftName == "lsr" || ShiftName == "LSR")
2249 else if (ShiftName == "asr" || ShiftName == "ASR")
2251 else if (ShiftName == "ror" || ShiftName == "ROR")
2253 else if (ShiftName == "rrx" || ShiftName == "RRX")
2257 Parser.Lex(); // Eat shift type token.
2259 // Rrx stands alone.
2260 if (St == ARM_AM::rrx)
2263 // Otherwise, there must be a '#' and a shift amount.
2264 const AsmToken &HashTok = Parser.getTok();
2265 if (HashTok.isNot(AsmToken::Hash))
2266 return Error(HashTok.getLoc(), "'#' expected");
2267 Parser.Lex(); // Eat hash token.
2269 if (getParser().ParseExpression(ShiftAmount))
2275 /// Parse a arm instruction operand. For now this parses the operand regardless
2276 /// of the mnemonic.
2277 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2278 StringRef Mnemonic) {
2281 // Check if the current operand has a custom associated parser, if so, try to
2282 // custom parse the operand, or fallback to the general approach.
2283 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2284 if (ResTy == MatchOperand_Success)
2286 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2287 // there was a match, but an error occurred, in which case, just return that
2288 // the operand parsing failed.
2289 if (ResTy == MatchOperand_ParseFail)
2292 switch (getLexer().getKind()) {
2294 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2296 case AsmToken::Identifier: {
2297 if (!tryParseRegisterWithWriteBack(Operands))
2299 int Res = tryParseShiftRegister(Operands);
2300 if (Res == 0) // success
2302 else if (Res == -1) // irrecoverable error
2305 // Fall though for the Identifier case that is not a register or a
2308 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2309 case AsmToken::Dot: { // . as a branch target
2310 // This was not a register so parse other operands that start with an
2311 // identifier (like labels) as expressions and create them as immediates.
2312 const MCExpr *IdVal;
2313 S = Parser.getTok().getLoc();
2314 if (getParser().ParseExpression(IdVal))
2316 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2317 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2320 case AsmToken::LBrac:
2321 return parseMemory(Operands);
2322 case AsmToken::LCurly:
2323 return parseRegisterList(Operands);
2324 case AsmToken::Hash:
2325 // #42 -> immediate.
2326 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2327 S = Parser.getTok().getLoc();
2329 const MCExpr *ImmVal;
2330 if (getParser().ParseExpression(ImmVal))
2332 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2333 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2335 case AsmToken::Colon: {
2336 // ":lower16:" and ":upper16:" expression prefixes
2337 // FIXME: Check it's an expression prefix,
2338 // e.g. (FOO - :lower16:BAR) isn't legal.
2339 ARMMCExpr::VariantKind RefKind;
2340 if (parsePrefix(RefKind))
2343 const MCExpr *SubExprVal;
2344 if (getParser().ParseExpression(SubExprVal))
2347 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2349 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2350 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2356 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2357 // :lower16: and :upper16:.
2358 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
2359 RefKind = ARMMCExpr::VK_ARM_None;
2361 // :lower16: and :upper16: modifiers
2362 assert(getLexer().is(AsmToken::Colon) && "expected a :");
2363 Parser.Lex(); // Eat ':'
2365 if (getLexer().isNot(AsmToken::Identifier)) {
2366 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2370 StringRef IDVal = Parser.getTok().getIdentifier();
2371 if (IDVal == "lower16") {
2372 RefKind = ARMMCExpr::VK_ARM_LO16;
2373 } else if (IDVal == "upper16") {
2374 RefKind = ARMMCExpr::VK_ARM_HI16;
2376 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2381 if (getLexer().isNot(AsmToken::Colon)) {
2382 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2385 Parser.Lex(); // Eat the last ':'
2390 ARMAsmParser::applyPrefixToExpr(const MCExpr *E,
2391 MCSymbolRefExpr::VariantKind Variant) {
2392 // Recurse over the given expression, rebuilding it to apply the given variant
2393 // to the leftmost symbol.
2394 if (Variant == MCSymbolRefExpr::VK_None)
2397 switch (E->getKind()) {
2398 case MCExpr::Target:
2399 llvm_unreachable("Can't handle target expr yet");
2400 case MCExpr::Constant:
2401 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2403 case MCExpr::SymbolRef: {
2404 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2406 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2409 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2413 llvm_unreachable("Can't handle unary expressions yet");
2415 case MCExpr::Binary: {
2416 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2417 const MCExpr *LHS = applyPrefixToExpr(BE->getLHS(), Variant);
2418 const MCExpr *RHS = BE->getRHS();
2422 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2426 assert(0 && "Invalid expression kind!");
2430 /// \brief Given a mnemonic, split out possible predication code and carry
2431 /// setting letters to form a canonical mnemonic and flags.
2433 // FIXME: Would be nice to autogen this.
2434 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
2435 unsigned &PredicationCode,
2437 unsigned &ProcessorIMod) {
2438 PredicationCode = ARMCC::AL;
2439 CarrySetting = false;
2442 // Ignore some mnemonics we know aren't predicated forms.
2444 // FIXME: Would be nice to autogen this.
2445 if ((Mnemonic == "movs" && isThumb()) ||
2446 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
2447 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
2448 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
2449 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
2450 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
2451 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
2452 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2455 // First, split out any predication code. Ignore mnemonics we know aren't
2456 // predicated but do have a carry-set and so weren't caught above.
2457 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2458 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
2459 Mnemonic != "umlals" && Mnemonic != "umulls") {
2460 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2461 .Case("eq", ARMCC::EQ)
2462 .Case("ne", ARMCC::NE)
2463 .Case("hs", ARMCC::HS)
2464 .Case("cs", ARMCC::HS)
2465 .Case("lo", ARMCC::LO)
2466 .Case("cc", ARMCC::LO)
2467 .Case("mi", ARMCC::MI)
2468 .Case("pl", ARMCC::PL)
2469 .Case("vs", ARMCC::VS)
2470 .Case("vc", ARMCC::VC)
2471 .Case("hi", ARMCC::HI)
2472 .Case("ls", ARMCC::LS)
2473 .Case("ge", ARMCC::GE)
2474 .Case("lt", ARMCC::LT)
2475 .Case("gt", ARMCC::GT)
2476 .Case("le", ARMCC::LE)
2477 .Case("al", ARMCC::AL)
2480 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2481 PredicationCode = CC;
2485 // Next, determine if we have a carry setting bit. We explicitly ignore all
2486 // the instructions we know end in 's'.
2487 if (Mnemonic.endswith("s") &&
2488 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
2489 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2490 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2491 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2492 Mnemonic == "vrsqrts" || (Mnemonic == "movs" && isThumb()))) {
2493 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2494 CarrySetting = true;
2497 // The "cps" instruction can have a interrupt mode operand which is glued into
2498 // the mnemonic. Check if this is the case, split it and parse the imod op
2499 if (Mnemonic.startswith("cps")) {
2500 // Split out any imod code.
2502 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2503 .Case("ie", ARM_PROC::IE)
2504 .Case("id", ARM_PROC::ID)
2507 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2508 ProcessorIMod = IMod;
2515 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
2516 /// inclusion of carry set or predication code operands.
2518 // FIXME: It would be nice to autogen this.
2520 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2521 bool &CanAcceptPredicationCode) {
2522 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2523 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2524 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2525 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2526 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2527 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2528 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2529 Mnemonic == "eor" || Mnemonic == "smlal" ||
2530 (Mnemonic == "mov" && !isThumbOne())) {
2531 CanAcceptCarrySet = true;
2533 CanAcceptCarrySet = false;
2536 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2537 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2538 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2539 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2540 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2541 Mnemonic == "setend" ||
2542 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2543 CanAcceptPredicationCode = false;
2545 CanAcceptPredicationCode = true;
2549 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2550 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2551 CanAcceptPredicationCode = false;
2554 /// Parse an arm instruction mnemonic followed by its operands.
2555 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2556 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2557 // Create the leading tokens for the mnemonic, split by '.' characters.
2558 size_t Start = 0, Next = Name.find('.');
2559 StringRef Mnemonic = Name.slice(Start, Next);
2561 // Split out the predication code and carry setting flag from the mnemonic.
2562 unsigned PredicationCode;
2563 unsigned ProcessorIMod;
2565 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2568 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2570 // FIXME: This is all a pretty gross hack. We should automatically handle
2571 // optional operands like this via tblgen.
2573 // Next, add the CCOut and ConditionCode operands, if needed.
2575 // For mnemonics which can ever incorporate a carry setting bit or predication
2576 // code, our matching model involves us always generating CCOut and
2577 // ConditionCode operands to match the mnemonic "as written" and then we let
2578 // the matcher deal with finding the right instruction or generating an
2579 // appropriate error.
2580 bool CanAcceptCarrySet, CanAcceptPredicationCode;
2581 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2583 // If we had a carry-set on an instruction that can't do that, issue an
2585 if (!CanAcceptCarrySet && CarrySetting) {
2586 Parser.EatToEndOfStatement();
2587 return Error(NameLoc, "instruction '" + Mnemonic +
2588 "' can not set flags, but 's' suffix specified");
2590 // If we had a predication code on an instruction that can't do that, issue an
2592 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2593 Parser.EatToEndOfStatement();
2594 return Error(NameLoc, "instruction '" + Mnemonic +
2595 "' is not predicable, but condition code specified");
2598 // Add the carry setting operand, if necessary.
2600 // FIXME: It would be awesome if we could somehow invent a location such that
2601 // match errors on this operand would print a nice diagnostic about how the
2602 // 's' character in the mnemonic resulted in a CCOut operand.
2603 if (CanAcceptCarrySet)
2604 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2607 // Add the predication code operand, if necessary.
2608 if (CanAcceptPredicationCode) {
2609 Operands.push_back(ARMOperand::CreateCondCode(
2610 ARMCC::CondCodes(PredicationCode), NameLoc));
2613 // Add the processor imod operand, if necessary.
2614 if (ProcessorIMod) {
2615 Operands.push_back(ARMOperand::CreateImm(
2616 MCConstantExpr::Create(ProcessorIMod, getContext()),
2619 // This mnemonic can't ever accept a imod, but the user wrote
2620 // one (or misspelled another mnemonic).
2622 // FIXME: Issue a nice error.
2625 // Add the remaining tokens in the mnemonic.
2626 while (Next != StringRef::npos) {
2628 Next = Name.find('.', Start + 1);
2629 StringRef ExtraToken = Name.slice(Start, Next);
2631 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2634 // Read the remaining operands.
2635 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2636 // Read the first operand.
2637 if (parseOperand(Operands, Mnemonic)) {
2638 Parser.EatToEndOfStatement();
2642 while (getLexer().is(AsmToken::Comma)) {
2643 Parser.Lex(); // Eat the comma.
2645 // Parse and remember the operand.
2646 if (parseOperand(Operands, Mnemonic)) {
2647 Parser.EatToEndOfStatement();
2653 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2654 Parser.EatToEndOfStatement();
2655 return TokError("unexpected token in argument list");
2658 Parser.Lex(); // Consume the EndOfStatement
2661 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2662 // another does not. Specifically, the MOVW instruction does not. So we
2663 // special case it here and remove the defaulted (non-setting) cc_out
2664 // operand if that's the instruction we're trying to match.
2666 // We do this post-processing of the explicit operands rather than just
2667 // conditionally adding the cc_out in the first place because we need
2668 // to check the type of the parsed immediate operand.
2669 if (Mnemonic == "mov" && Operands.size() > 4 &&
2670 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2671 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2672 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) {
2673 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2674 Operands.erase(Operands.begin() + 1);
2681 // Validate context-sensitive operand constraints.
2682 // FIXME: We would really like to be able to tablegen'erate this.
2684 validateInstruction(MCInst &Inst,
2685 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2686 switch (Inst.getOpcode()) {
2688 // Rt2 must be Rt + 1.
2689 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
2690 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2692 return Error(Operands[3]->getStartLoc(),
2693 "destination operands must be sequential");
2697 // Rt2 must be Rt + 1.
2698 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
2699 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
2701 return Error(Operands[4]->getStartLoc(),
2702 "source operands must be sequential");
2707 // width must be in range [1, 32-lsb]
2708 unsigned lsb = Inst.getOperand(2).getImm();
2709 unsigned widthm1 = Inst.getOperand(3).getImm();
2710 if (widthm1 >= 32 - lsb)
2711 return Error(Operands[5]->getStartLoc(),
2712 "bitfield width must be in range [1,32-lsb]");
2720 MatchAndEmitInstruction(SMLoc IDLoc,
2721 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2725 MatchResultTy MatchResult;
2726 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
2727 switch (MatchResult) {
2729 // Context sensitive operand constraints aren't handled by the matcher,
2730 // so check them here.
2731 if (validateInstruction(Inst, Operands))
2734 Out.EmitInstruction(Inst);
2736 case Match_MissingFeature:
2737 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
2739 case Match_InvalidOperand: {
2740 SMLoc ErrorLoc = IDLoc;
2741 if (ErrorInfo != ~0U) {
2742 if (ErrorInfo >= Operands.size())
2743 return Error(IDLoc, "too few operands for instruction");
2745 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
2746 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
2749 return Error(ErrorLoc, "invalid operand for instruction");
2751 case Match_MnemonicFail:
2752 return Error(IDLoc, "unrecognized instruction mnemonic");
2753 case Match_ConversionFail:
2754 return Error(IDLoc, "unable to convert operands to instruction");
2757 llvm_unreachable("Implement any new match types added!");
2761 /// parseDirective parses the arm specific directives
2762 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
2763 StringRef IDVal = DirectiveID.getIdentifier();
2764 if (IDVal == ".word")
2765 return parseDirectiveWord(4, DirectiveID.getLoc());
2766 else if (IDVal == ".thumb")
2767 return parseDirectiveThumb(DirectiveID.getLoc());
2768 else if (IDVal == ".thumb_func")
2769 return parseDirectiveThumbFunc(DirectiveID.getLoc());
2770 else if (IDVal == ".code")
2771 return parseDirectiveCode(DirectiveID.getLoc());
2772 else if (IDVal == ".syntax")
2773 return parseDirectiveSyntax(DirectiveID.getLoc());
2777 /// parseDirectiveWord
2778 /// ::= .word [ expression (, expression)* ]
2779 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
2780 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2782 const MCExpr *Value;
2783 if (getParser().ParseExpression(Value))
2786 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
2788 if (getLexer().is(AsmToken::EndOfStatement))
2791 // FIXME: Improve diagnostic.
2792 if (getLexer().isNot(AsmToken::Comma))
2793 return Error(L, "unexpected token in directive");
2802 /// parseDirectiveThumb
2804 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
2805 if (getLexer().isNot(AsmToken::EndOfStatement))
2806 return Error(L, "unexpected token in directive");
2809 // TODO: set thumb mode
2810 // TODO: tell the MC streamer the mode
2811 // getParser().getStreamer().Emit???();
2815 /// parseDirectiveThumbFunc
2816 /// ::= .thumbfunc symbol_name
2817 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
2818 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
2819 bool isMachO = MAI.hasSubsectionsViaSymbols();
2822 // Darwin asm has function name after .thumb_func direction
2825 const AsmToken &Tok = Parser.getTok();
2826 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
2827 return Error(L, "unexpected token in .thumb_func directive");
2828 Name = Tok.getString();
2829 Parser.Lex(); // Consume the identifier token.
2832 if (getLexer().isNot(AsmToken::EndOfStatement))
2833 return Error(L, "unexpected token in directive");
2836 // FIXME: assuming function name will be the line following .thumb_func
2838 Name = Parser.getTok().getString();
2841 // Mark symbol as a thumb symbol.
2842 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
2843 getParser().getStreamer().EmitThumbFunc(Func);
2847 /// parseDirectiveSyntax
2848 /// ::= .syntax unified | divided
2849 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
2850 const AsmToken &Tok = Parser.getTok();
2851 if (Tok.isNot(AsmToken::Identifier))
2852 return Error(L, "unexpected token in .syntax directive");
2853 StringRef Mode = Tok.getString();
2854 if (Mode == "unified" || Mode == "UNIFIED")
2856 else if (Mode == "divided" || Mode == "DIVIDED")
2857 return Error(L, "'.syntax divided' arm asssembly not supported");
2859 return Error(L, "unrecognized syntax mode in .syntax directive");
2861 if (getLexer().isNot(AsmToken::EndOfStatement))
2862 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2865 // TODO tell the MC streamer the mode
2866 // getParser().getStreamer().Emit???();
2870 /// parseDirectiveCode
2871 /// ::= .code 16 | 32
2872 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
2873 const AsmToken &Tok = Parser.getTok();
2874 if (Tok.isNot(AsmToken::Integer))
2875 return Error(L, "unexpected token in .code directive");
2876 int64_t Val = Parser.getTok().getIntVal();
2882 return Error(L, "invalid operand to .code directive");
2884 if (getLexer().isNot(AsmToken::EndOfStatement))
2885 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2891 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2896 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2903 extern "C" void LLVMInitializeARMAsmLexer();
2905 /// Force static initialization.
2906 extern "C" void LLVMInitializeARMAsmParser() {
2907 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
2908 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
2909 LLVMInitializeARMAsmLexer();
2912 #define GET_REGISTER_MATCHER
2913 #define GET_MATCHER_IMPLEMENTATION
2914 #include "ARMGenAsmMatcher.inc"