1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/ADT/StringSwitch.h"
20 #include "llvm/ADT/Twine.h"
21 #include "llvm/MC/MCAsmInfo.h"
22 #include "llvm/MC/MCAssembler.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCDisassembler.h"
25 #include "llvm/MC/MCELF.h"
26 #include "llvm/MC/MCELFStreamer.h"
27 #include "llvm/MC/MCELFSymbolFlags.h"
28 #include "llvm/MC/MCExpr.h"
29 #include "llvm/MC/MCInst.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCObjectFileInfo.h"
33 #include "llvm/MC/MCParser/MCAsmLexer.h"
34 #include "llvm/MC/MCParser/MCAsmParser.h"
35 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/MC/MCSection.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/MC/MCSubtargetInfo.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/MC/MCTargetAsmParser.h"
42 #include "llvm/Support/ARMBuildAttributes.h"
43 #include "llvm/Support/ARMEHABI.h"
44 #include "llvm/Support/COFF.h"
45 #include "llvm/Support/Debug.h"
46 #include "llvm/Support/ELF.h"
47 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Support/SourceMgr.h"
49 #include "llvm/Support/TargetRegistry.h"
50 #include "llvm/Support/raw_ostream.h"
58 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
63 typedef SmallVector<SMLoc, 4> Locs;
68 Locs PersonalityIndexLocs;
73 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
75 bool hasFnStart() const { return !FnStartLocs.empty(); }
76 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
77 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
78 bool hasPersonality() const {
79 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
82 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
83 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
84 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
85 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
86 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
88 void saveFPReg(int Reg) { FPReg = Reg; }
89 int getFPReg() const { return FPReg; }
91 void emitFnStartLocNotes() const {
92 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
94 Parser.Note(*FI, ".fnstart was specified here");
96 void emitCantUnwindLocNotes() const {
97 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
98 UE = CantUnwindLocs.end(); UI != UE; ++UI)
99 Parser.Note(*UI, ".cantunwind was specified here");
101 void emitHandlerDataLocNotes() const {
102 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
103 HE = HandlerDataLocs.end(); HI != HE; ++HI)
104 Parser.Note(*HI, ".handlerdata was specified here");
106 void emitPersonalityLocNotes() const {
107 for (Locs::const_iterator PI = PersonalityLocs.begin(),
108 PE = PersonalityLocs.end(),
109 PII = PersonalityIndexLocs.begin(),
110 PIE = PersonalityIndexLocs.end();
111 PI != PE || PII != PIE;) {
112 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
113 Parser.Note(*PI++, ".personality was specified here");
114 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
115 Parser.Note(*PII++, ".personalityindex was specified here");
117 llvm_unreachable(".personality and .personalityindex cannot be "
118 "at the same location");
123 FnStartLocs = Locs();
124 CantUnwindLocs = Locs();
125 PersonalityLocs = Locs();
126 HandlerDataLocs = Locs();
127 PersonalityIndexLocs = Locs();
132 class ARMAsmParser : public MCTargetAsmParser {
133 MCSubtargetInfo &STI;
135 const MCInstrInfo &MII;
136 const MCRegisterInfo *MRI;
139 ARMTargetStreamer &getTargetStreamer() {
140 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
141 return static_cast<ARMTargetStreamer &>(TS);
144 // Map of register aliases registers via the .req directive.
145 StringMap<unsigned> RegisterReqs;
147 bool NextSymbolIsThumb;
150 ARMCC::CondCodes Cond; // Condition for IT block.
151 unsigned Mask:4; // Condition mask for instructions.
152 // Starting at first 1 (from lsb).
153 // '1' condition as indicated in IT.
154 // '0' inverse of condition (else).
155 // Count of instructions in IT block is
156 // 4 - trailingzeroes(mask)
158 bool FirstCond; // Explicit flag for when we're parsing the
159 // First instruction in the IT block. It's
160 // implied in the mask, so needs special
163 unsigned CurPosition; // Current position in parsing of IT
164 // block. In range [0,3]. Initialized
165 // according to count of instructions in block.
166 // ~0U if no active IT block.
168 bool inITBlock() { return ITState.CurPosition != ~0U;}
169 void forwardITPosition() {
170 if (!inITBlock()) return;
171 // Move to the next instruction in the IT block, if there is one. If not,
172 // mark the block as done.
173 unsigned TZ = countTrailingZeros(ITState.Mask);
174 if (++ITState.CurPosition == 5 - TZ)
175 ITState.CurPosition = ~0U; // Done with the IT block after this.
179 MCAsmParser &getParser() const { return Parser; }
180 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
182 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
183 return Parser.Note(L, Msg, Ranges);
185 bool Warning(SMLoc L, const Twine &Msg,
186 ArrayRef<SMRange> Ranges = None) {
187 return Parser.Warning(L, Msg, Ranges);
189 bool Error(SMLoc L, const Twine &Msg,
190 ArrayRef<SMRange> Ranges = None) {
191 return Parser.Error(L, Msg, Ranges);
194 int tryParseRegister();
195 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
196 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
199 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
200 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
201 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
202 unsigned &ShiftAmount);
203 bool parseLiteralValues(unsigned Size, SMLoc L);
204 bool parseDirectiveThumb(SMLoc L);
205 bool parseDirectiveARM(SMLoc L);
206 bool parseDirectiveThumbFunc(SMLoc L);
207 bool parseDirectiveCode(SMLoc L);
208 bool parseDirectiveSyntax(SMLoc L);
209 bool parseDirectiveReq(StringRef Name, SMLoc L);
210 bool parseDirectiveUnreq(SMLoc L);
211 bool parseDirectiveArch(SMLoc L);
212 bool parseDirectiveEabiAttr(SMLoc L);
213 bool parseDirectiveCPU(SMLoc L);
214 bool parseDirectiveFPU(SMLoc L);
215 bool parseDirectiveFnStart(SMLoc L);
216 bool parseDirectiveFnEnd(SMLoc L);
217 bool parseDirectiveCantUnwind(SMLoc L);
218 bool parseDirectivePersonality(SMLoc L);
219 bool parseDirectiveHandlerData(SMLoc L);
220 bool parseDirectiveSetFP(SMLoc L);
221 bool parseDirectivePad(SMLoc L);
222 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
223 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
224 bool parseDirectiveLtorg(SMLoc L);
225 bool parseDirectiveEven(SMLoc L);
226 bool parseDirectivePersonalityIndex(SMLoc L);
227 bool parseDirectiveUnwindRaw(SMLoc L);
228 bool parseDirectiveTLSDescSeq(SMLoc L);
229 bool parseDirectiveMovSP(SMLoc L);
230 bool parseDirectiveObjectArch(SMLoc L);
231 bool parseDirectiveArchExtension(SMLoc L);
232 bool parseDirectiveAlign(SMLoc L);
233 bool parseDirectiveThumbSet(SMLoc L);
235 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
236 bool &CarrySetting, unsigned &ProcessorIMod,
238 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
239 bool &CanAcceptCarrySet,
240 bool &CanAcceptPredicationCode);
242 bool isThumb() const {
243 // FIXME: Can tablegen auto-generate this?
244 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
246 bool isThumbOne() const {
247 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
249 bool isThumbTwo() const {
250 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
252 bool hasThumb() const {
253 return STI.getFeatureBits() & ARM::HasV4TOps;
255 bool hasV6Ops() const {
256 return STI.getFeatureBits() & ARM::HasV6Ops;
258 bool hasV6MOps() const {
259 return STI.getFeatureBits() & ARM::HasV6MOps;
261 bool hasV7Ops() const {
262 return STI.getFeatureBits() & ARM::HasV7Ops;
264 bool hasV8Ops() const {
265 return STI.getFeatureBits() & ARM::HasV8Ops;
267 bool hasARM() const {
268 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
272 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
273 setAvailableFeatures(FB);
275 bool isMClass() const {
276 return STI.getFeatureBits() & ARM::FeatureMClass;
279 /// @name Auto-generated Match Functions
282 #define GET_ASSEMBLER_HEADER
283 #include "ARMGenAsmMatcher.inc"
287 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
288 OperandMatchResultTy parseCoprocNumOperand(
289 SmallVectorImpl<MCParsedAsmOperand*>&);
290 OperandMatchResultTy parseCoprocRegOperand(
291 SmallVectorImpl<MCParsedAsmOperand*>&);
292 OperandMatchResultTy parseCoprocOptionOperand(
293 SmallVectorImpl<MCParsedAsmOperand*>&);
294 OperandMatchResultTy parseMemBarrierOptOperand(
295 SmallVectorImpl<MCParsedAsmOperand*>&);
296 OperandMatchResultTy parseInstSyncBarrierOptOperand(
297 SmallVectorImpl<MCParsedAsmOperand*>&);
298 OperandMatchResultTy parseProcIFlagsOperand(
299 SmallVectorImpl<MCParsedAsmOperand*>&);
300 OperandMatchResultTy parseMSRMaskOperand(
301 SmallVectorImpl<MCParsedAsmOperand*>&);
302 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
303 StringRef Op, int Low, int High);
304 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
305 return parsePKHImm(O, "lsl", 0, 31);
307 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
308 return parsePKHImm(O, "asr", 1, 32);
310 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
311 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
312 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
313 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
314 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
315 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
316 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
317 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
318 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
321 // Asm Match Converter Methods
322 void cvtThumbMultiply(MCInst &Inst,
323 const SmallVectorImpl<MCParsedAsmOperand*> &);
324 void cvtThumbBranches(MCInst &Inst,
325 const SmallVectorImpl<MCParsedAsmOperand*> &);
327 bool validateInstruction(MCInst &Inst,
328 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
329 bool processInstruction(MCInst &Inst,
330 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
331 bool shouldOmitCCOutOperand(StringRef Mnemonic,
332 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
333 bool shouldOmitPredicateOperand(StringRef Mnemonic,
334 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
336 enum ARMMatchResultTy {
337 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
338 Match_RequiresNotITBlock,
340 Match_RequiresThumb2,
341 #define GET_OPERAND_DIAGNOSTIC_TYPES
342 #include "ARMGenAsmMatcher.inc"
346 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
347 const MCInstrInfo &MII)
348 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
349 MCAsmParserExtension::Initialize(_Parser);
351 // Cache the MCRegisterInfo.
352 MRI = getContext().getRegisterInfo();
354 // Initialize the set of available features.
355 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
357 // Not in an ITBlock to start with.
358 ITState.CurPosition = ~0U;
360 NextSymbolIsThumb = false;
363 // Implementation of the MCTargetAsmParser interface:
364 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
366 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
368 SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
369 bool ParseDirective(AsmToken DirectiveID) override;
371 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
372 unsigned Kind) override;
373 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
375 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
376 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
377 MCStreamer &Out, unsigned &ErrorInfo,
378 bool MatchingInlineAsm) override;
379 void onLabelParsed(MCSymbol *Symbol) override;
381 } // end anonymous namespace
385 /// ARMOperand - Instances of this class represent a parsed ARM machine
387 class ARMOperand : public MCParsedAsmOperand {
397 k_InstSyncBarrierOpt,
408 k_VectorListAllLanes,
414 k_BitfieldDescriptor,
418 SMLoc StartLoc, EndLoc, AlignmentLoc;
419 SmallVector<unsigned, 8> Registers;
422 ARMCC::CondCodes Val;
429 struct CoprocOptionOp {
442 ARM_ISB::InstSyncBOpt Val;
446 ARM_PROC::IFlags Val;
462 // A vector register list is a sequential list of 1 to 4 registers.
463 struct VectorListOp {
470 struct VectorIndexOp {
478 /// Combined record for all forms of ARM address expressions.
481 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
483 const MCConstantExpr *OffsetImm; // Offset immediate value
484 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
485 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
486 unsigned ShiftImm; // shift for OffsetReg.
487 unsigned Alignment; // 0 = no alignment specified
488 // n = alignment in bytes (2, 4, 8, 16, or 32)
489 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
492 struct PostIdxRegOp {
495 ARM_AM::ShiftOpc ShiftTy;
499 struct ShifterImmOp {
504 struct RegShiftedRegOp {
505 ARM_AM::ShiftOpc ShiftTy;
511 struct RegShiftedImmOp {
512 ARM_AM::ShiftOpc ShiftTy;
529 struct CoprocOptionOp CoprocOption;
530 struct MBOptOp MBOpt;
531 struct ISBOptOp ISBOpt;
532 struct ITMaskOp ITMask;
533 struct IFlagsOp IFlags;
534 struct MMaskOp MMask;
537 struct VectorListOp VectorList;
538 struct VectorIndexOp VectorIndex;
540 struct MemoryOp Memory;
541 struct PostIdxRegOp PostIdxReg;
542 struct ShifterImmOp ShifterImm;
543 struct RegShiftedRegOp RegShiftedReg;
544 struct RegShiftedImmOp RegShiftedImm;
545 struct RotImmOp RotImm;
546 struct BitfieldOp Bitfield;
549 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
551 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
553 StartLoc = o.StartLoc;
570 case k_DPRRegisterList:
571 case k_SPRRegisterList:
572 Registers = o.Registers;
575 case k_VectorListAllLanes:
576 case k_VectorListIndexed:
577 VectorList = o.VectorList;
584 CoprocOption = o.CoprocOption;
589 case k_MemBarrierOpt:
592 case k_InstSyncBarrierOpt:
597 case k_PostIndexRegister:
598 PostIdxReg = o.PostIdxReg;
606 case k_ShifterImmediate:
607 ShifterImm = o.ShifterImm;
609 case k_ShiftedRegister:
610 RegShiftedReg = o.RegShiftedReg;
612 case k_ShiftedImmediate:
613 RegShiftedImm = o.RegShiftedImm;
615 case k_RotateImmediate:
618 case k_BitfieldDescriptor:
619 Bitfield = o.Bitfield;
622 VectorIndex = o.VectorIndex;
627 /// getStartLoc - Get the location of the first token of this operand.
628 SMLoc getStartLoc() const override { return StartLoc; }
629 /// getEndLoc - Get the location of the last token of this operand.
630 SMLoc getEndLoc() const override { return EndLoc; }
631 /// getLocRange - Get the range between the first and last token of this
633 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
635 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
636 SMLoc getAlignmentLoc() const {
637 assert(Kind == k_Memory && "Invalid access!");
641 ARMCC::CondCodes getCondCode() const {
642 assert(Kind == k_CondCode && "Invalid access!");
646 unsigned getCoproc() const {
647 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
651 StringRef getToken() const {
652 assert(Kind == k_Token && "Invalid access!");
653 return StringRef(Tok.Data, Tok.Length);
656 unsigned getReg() const override {
657 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
661 const SmallVectorImpl<unsigned> &getRegList() const {
662 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
663 Kind == k_SPRRegisterList) && "Invalid access!");
667 const MCExpr *getImm() const {
668 assert(isImm() && "Invalid access!");
672 unsigned getVectorIndex() const {
673 assert(Kind == k_VectorIndex && "Invalid access!");
674 return VectorIndex.Val;
677 ARM_MB::MemBOpt getMemBarrierOpt() const {
678 assert(Kind == k_MemBarrierOpt && "Invalid access!");
682 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
683 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
687 ARM_PROC::IFlags getProcIFlags() const {
688 assert(Kind == k_ProcIFlags && "Invalid access!");
692 unsigned getMSRMask() const {
693 assert(Kind == k_MSRMask && "Invalid access!");
697 bool isCoprocNum() const { return Kind == k_CoprocNum; }
698 bool isCoprocReg() const { return Kind == k_CoprocReg; }
699 bool isCoprocOption() const { return Kind == k_CoprocOption; }
700 bool isCondCode() const { return Kind == k_CondCode; }
701 bool isCCOut() const { return Kind == k_CCOut; }
702 bool isITMask() const { return Kind == k_ITCondMask; }
703 bool isITCondCode() const { return Kind == k_CondCode; }
704 bool isImm() const override { return Kind == k_Immediate; }
705 // checks whether this operand is an unsigned offset which fits is a field
706 // of specified width and scaled by a specific number of bits
707 template<unsigned width, unsigned scale>
708 bool isUnsignedOffset() const {
709 if (!isImm()) return false;
710 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
711 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
712 int64_t Val = CE->getValue();
713 int64_t Align = 1LL << scale;
714 int64_t Max = Align * ((1LL << width) - 1);
715 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
719 // checks whether this operand is an signed offset which fits is a field
720 // of specified width and scaled by a specific number of bits
721 template<unsigned width, unsigned scale>
722 bool isSignedOffset() const {
723 if (!isImm()) return false;
724 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
725 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
726 int64_t Val = CE->getValue();
727 int64_t Align = 1LL << scale;
728 int64_t Max = Align * ((1LL << (width-1)) - 1);
729 int64_t Min = -Align * (1LL << (width-1));
730 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
735 // checks whether this operand is a memory operand computed as an offset
736 // applied to PC. the offset may have 8 bits of magnitude and is represented
737 // with two bits of shift. textually it may be either [pc, #imm], #imm or
738 // relocable expression...
739 bool isThumbMemPC() const {
742 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
743 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
744 if (!CE) return false;
745 Val = CE->getValue();
748 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
749 if(Memory.BaseRegNum != ARM::PC) return false;
750 Val = Memory.OffsetImm->getValue();
753 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
755 bool isFPImm() const {
756 if (!isImm()) return false;
757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
758 if (!CE) return false;
759 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
762 bool isFBits16() const {
763 if (!isImm()) return false;
764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
765 if (!CE) return false;
766 int64_t Value = CE->getValue();
767 return Value >= 0 && Value <= 16;
769 bool isFBits32() const {
770 if (!isImm()) return false;
771 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
772 if (!CE) return false;
773 int64_t Value = CE->getValue();
774 return Value >= 1 && Value <= 32;
776 bool isImm8s4() const {
777 if (!isImm()) return false;
778 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
779 if (!CE) return false;
780 int64_t Value = CE->getValue();
781 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
783 bool isImm0_1020s4() const {
784 if (!isImm()) return false;
785 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
786 if (!CE) return false;
787 int64_t Value = CE->getValue();
788 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
790 bool isImm0_508s4() const {
791 if (!isImm()) return false;
792 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
793 if (!CE) return false;
794 int64_t Value = CE->getValue();
795 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
797 bool isImm0_508s4Neg() const {
798 if (!isImm()) return false;
799 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
800 if (!CE) return false;
801 int64_t Value = -CE->getValue();
802 // explicitly exclude zero. we want that to use the normal 0_508 version.
803 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
805 bool isImm0_239() const {
806 if (!isImm()) return false;
807 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
808 if (!CE) return false;
809 int64_t Value = CE->getValue();
810 return Value >= 0 && Value < 240;
812 bool isImm0_255() const {
813 if (!isImm()) return false;
814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
815 if (!CE) return false;
816 int64_t Value = CE->getValue();
817 return Value >= 0 && Value < 256;
819 bool isImm0_4095() const {
820 if (!isImm()) return false;
821 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
822 if (!CE) return false;
823 int64_t Value = CE->getValue();
824 return Value >= 0 && Value < 4096;
826 bool isImm0_4095Neg() const {
827 if (!isImm()) return false;
828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
829 if (!CE) return false;
830 int64_t Value = -CE->getValue();
831 return Value > 0 && Value < 4096;
833 bool isImm0_1() const {
834 if (!isImm()) return false;
835 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
836 if (!CE) return false;
837 int64_t Value = CE->getValue();
838 return Value >= 0 && Value < 2;
840 bool isImm0_3() const {
841 if (!isImm()) return false;
842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
843 if (!CE) return false;
844 int64_t Value = CE->getValue();
845 return Value >= 0 && Value < 4;
847 bool isImm0_7() const {
848 if (!isImm()) return false;
849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
850 if (!CE) return false;
851 int64_t Value = CE->getValue();
852 return Value >= 0 && Value < 8;
854 bool isImm0_15() const {
855 if (!isImm()) return false;
856 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
857 if (!CE) return false;
858 int64_t Value = CE->getValue();
859 return Value >= 0 && Value < 16;
861 bool isImm0_31() const {
862 if (!isImm()) return false;
863 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
864 if (!CE) return false;
865 int64_t Value = CE->getValue();
866 return Value >= 0 && Value < 32;
868 bool isImm0_63() const {
869 if (!isImm()) return false;
870 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
871 if (!CE) return false;
872 int64_t Value = CE->getValue();
873 return Value >= 0 && Value < 64;
875 bool isImm8() const {
876 if (!isImm()) return false;
877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
878 if (!CE) return false;
879 int64_t Value = CE->getValue();
882 bool isImm16() const {
883 if (!isImm()) return false;
884 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
885 if (!CE) return false;
886 int64_t Value = CE->getValue();
889 bool isImm32() const {
890 if (!isImm()) return false;
891 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
892 if (!CE) return false;
893 int64_t Value = CE->getValue();
896 bool isShrImm8() const {
897 if (!isImm()) return false;
898 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
899 if (!CE) return false;
900 int64_t Value = CE->getValue();
901 return Value > 0 && Value <= 8;
903 bool isShrImm16() const {
904 if (!isImm()) return false;
905 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
906 if (!CE) return false;
907 int64_t Value = CE->getValue();
908 return Value > 0 && Value <= 16;
910 bool isShrImm32() const {
911 if (!isImm()) return false;
912 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
913 if (!CE) return false;
914 int64_t Value = CE->getValue();
915 return Value > 0 && Value <= 32;
917 bool isShrImm64() const {
918 if (!isImm()) return false;
919 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
920 if (!CE) return false;
921 int64_t Value = CE->getValue();
922 return Value > 0 && Value <= 64;
924 bool isImm1_7() const {
925 if (!isImm()) return false;
926 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
927 if (!CE) return false;
928 int64_t Value = CE->getValue();
929 return Value > 0 && Value < 8;
931 bool isImm1_15() const {
932 if (!isImm()) return false;
933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934 if (!CE) return false;
935 int64_t Value = CE->getValue();
936 return Value > 0 && Value < 16;
938 bool isImm1_31() const {
939 if (!isImm()) return false;
940 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941 if (!CE) return false;
942 int64_t Value = CE->getValue();
943 return Value > 0 && Value < 32;
945 bool isImm1_16() const {
946 if (!isImm()) return false;
947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948 if (!CE) return false;
949 int64_t Value = CE->getValue();
950 return Value > 0 && Value < 17;
952 bool isImm1_32() const {
953 if (!isImm()) return false;
954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955 if (!CE) return false;
956 int64_t Value = CE->getValue();
957 return Value > 0 && Value < 33;
959 bool isImm0_32() const {
960 if (!isImm()) return false;
961 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
962 if (!CE) return false;
963 int64_t Value = CE->getValue();
964 return Value >= 0 && Value < 33;
966 bool isImm0_65535() const {
967 if (!isImm()) return false;
968 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
969 if (!CE) return false;
970 int64_t Value = CE->getValue();
971 return Value >= 0 && Value < 65536;
973 bool isImm256_65535Expr() const {
974 if (!isImm()) return false;
975 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
976 // If it's not a constant expression, it'll generate a fixup and be
978 if (!CE) return true;
979 int64_t Value = CE->getValue();
980 return Value >= 256 && Value < 65536;
982 bool isImm0_65535Expr() const {
983 if (!isImm()) return false;
984 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
985 // If it's not a constant expression, it'll generate a fixup and be
987 if (!CE) return true;
988 int64_t Value = CE->getValue();
989 return Value >= 0 && Value < 65536;
991 bool isImm24bit() const {
992 if (!isImm()) return false;
993 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
994 if (!CE) return false;
995 int64_t Value = CE->getValue();
996 return Value >= 0 && Value <= 0xffffff;
998 bool isImmThumbSR() const {
999 if (!isImm()) return false;
1000 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1001 if (!CE) return false;
1002 int64_t Value = CE->getValue();
1003 return Value > 0 && Value < 33;
1005 bool isPKHLSLImm() const {
1006 if (!isImm()) return false;
1007 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1008 if (!CE) return false;
1009 int64_t Value = CE->getValue();
1010 return Value >= 0 && Value < 32;
1012 bool isPKHASRImm() const {
1013 if (!isImm()) return false;
1014 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1015 if (!CE) return false;
1016 int64_t Value = CE->getValue();
1017 return Value > 0 && Value <= 32;
1019 bool isAdrLabel() const {
1020 // If we have an immediate that's not a constant, treat it as a label
1021 // reference needing a fixup. If it is a constant, but it can't fit
1022 // into shift immediate encoding, we reject it.
1023 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1024 else return (isARMSOImm() || isARMSOImmNeg());
1026 bool isARMSOImm() const {
1027 if (!isImm()) return false;
1028 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1029 if (!CE) return false;
1030 int64_t Value = CE->getValue();
1031 return ARM_AM::getSOImmVal(Value) != -1;
1033 bool isARMSOImmNot() const {
1034 if (!isImm()) return false;
1035 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1036 if (!CE) return false;
1037 int64_t Value = CE->getValue();
1038 return ARM_AM::getSOImmVal(~Value) != -1;
1040 bool isARMSOImmNeg() const {
1041 if (!isImm()) return false;
1042 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1043 if (!CE) return false;
1044 int64_t Value = CE->getValue();
1045 // Only use this when not representable as a plain so_imm.
1046 return ARM_AM::getSOImmVal(Value) == -1 &&
1047 ARM_AM::getSOImmVal(-Value) != -1;
1049 bool isT2SOImm() const {
1050 if (!isImm()) return false;
1051 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1052 if (!CE) return false;
1053 int64_t Value = CE->getValue();
1054 return ARM_AM::getT2SOImmVal(Value) != -1;
1056 bool isT2SOImmNot() const {
1057 if (!isImm()) return false;
1058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1059 if (!CE) return false;
1060 int64_t Value = CE->getValue();
1061 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1062 ARM_AM::getT2SOImmVal(~Value) != -1;
1064 bool isT2SOImmNeg() const {
1065 if (!isImm()) return false;
1066 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1067 if (!CE) return false;
1068 int64_t Value = CE->getValue();
1069 // Only use this when not representable as a plain so_imm.
1070 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1071 ARM_AM::getT2SOImmVal(-Value) != -1;
1073 bool isSetEndImm() const {
1074 if (!isImm()) return false;
1075 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1076 if (!CE) return false;
1077 int64_t Value = CE->getValue();
1078 return Value == 1 || Value == 0;
1080 bool isReg() const override { return Kind == k_Register; }
1081 bool isRegList() const { return Kind == k_RegisterList; }
1082 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1083 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1084 bool isToken() const override { return Kind == k_Token; }
1085 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1086 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1087 bool isMem() const override { return Kind == k_Memory; }
1088 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1089 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1090 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1091 bool isRotImm() const { return Kind == k_RotateImmediate; }
1092 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1093 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1094 bool isPostIdxReg() const {
1095 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1097 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1100 // No offset of any kind.
1101 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1102 (alignOK || Memory.Alignment == Alignment);
1104 bool isMemPCRelImm12() const {
1105 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1107 // Base register must be PC.
1108 if (Memory.BaseRegNum != ARM::PC)
1110 // Immediate offset in range [-4095, 4095].
1111 if (!Memory.OffsetImm) return true;
1112 int64_t Val = Memory.OffsetImm->getValue();
1113 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1115 bool isAlignedMemory() const {
1116 return isMemNoOffset(true);
1118 bool isAlignedMemoryNone() const {
1119 return isMemNoOffset(false, 0);
1121 bool isDupAlignedMemoryNone() const {
1122 return isMemNoOffset(false, 0);
1124 bool isAlignedMemory16() const {
1125 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1127 return isMemNoOffset(false, 0);
1129 bool isDupAlignedMemory16() const {
1130 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1132 return isMemNoOffset(false, 0);
1134 bool isAlignedMemory32() const {
1135 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1137 return isMemNoOffset(false, 0);
1139 bool isDupAlignedMemory32() const {
1140 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1142 return isMemNoOffset(false, 0);
1144 bool isAlignedMemory64() const {
1145 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1147 return isMemNoOffset(false, 0);
1149 bool isDupAlignedMemory64() const {
1150 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1152 return isMemNoOffset(false, 0);
1154 bool isAlignedMemory64or128() const {
1155 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1157 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1159 return isMemNoOffset(false, 0);
1161 bool isDupAlignedMemory64or128() const {
1162 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1164 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1166 return isMemNoOffset(false, 0);
1168 bool isAlignedMemory64or128or256() const {
1169 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1171 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1173 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1175 return isMemNoOffset(false, 0);
1177 bool isAddrMode2() const {
1178 if (!isMem() || Memory.Alignment != 0) return false;
1179 // Check for register offset.
1180 if (Memory.OffsetRegNum) return true;
1181 // Immediate offset in range [-4095, 4095].
1182 if (!Memory.OffsetImm) return true;
1183 int64_t Val = Memory.OffsetImm->getValue();
1184 return Val > -4096 && Val < 4096;
1186 bool isAM2OffsetImm() const {
1187 if (!isImm()) return false;
1188 // Immediate offset in range [-4095, 4095].
1189 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1190 if (!CE) return false;
1191 int64_t Val = CE->getValue();
1192 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1194 bool isAddrMode3() const {
1195 // If we have an immediate that's not a constant, treat it as a label
1196 // reference needing a fixup. If it is a constant, it's something else
1197 // and we reject it.
1198 if (isImm() && !isa<MCConstantExpr>(getImm()))
1200 if (!isMem() || Memory.Alignment != 0) return false;
1201 // No shifts are legal for AM3.
1202 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1203 // Check for register offset.
1204 if (Memory.OffsetRegNum) return true;
1205 // Immediate offset in range [-255, 255].
1206 if (!Memory.OffsetImm) return true;
1207 int64_t Val = Memory.OffsetImm->getValue();
1208 // The #-0 offset is encoded as INT32_MIN, and we have to check
1210 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1212 bool isAM3Offset() const {
1213 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1215 if (Kind == k_PostIndexRegister)
1216 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1217 // Immediate offset in range [-255, 255].
1218 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1219 if (!CE) return false;
1220 int64_t Val = CE->getValue();
1221 // Special case, #-0 is INT32_MIN.
1222 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1224 bool isAddrMode5() const {
1225 // If we have an immediate that's not a constant, treat it as a label
1226 // reference needing a fixup. If it is a constant, it's something else
1227 // and we reject it.
1228 if (isImm() && !isa<MCConstantExpr>(getImm()))
1230 if (!isMem() || Memory.Alignment != 0) return false;
1231 // Check for register offset.
1232 if (Memory.OffsetRegNum) return false;
1233 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1234 if (!Memory.OffsetImm) return true;
1235 int64_t Val = Memory.OffsetImm->getValue();
1236 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1239 bool isMemTBB() const {
1240 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1241 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1245 bool isMemTBH() const {
1246 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1247 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1248 Memory.Alignment != 0 )
1252 bool isMemRegOffset() const {
1253 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1257 bool isT2MemRegOffset() const {
1258 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1259 Memory.Alignment != 0)
1261 // Only lsl #{0, 1, 2, 3} allowed.
1262 if (Memory.ShiftType == ARM_AM::no_shift)
1264 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1268 bool isMemThumbRR() const {
1269 // Thumb reg+reg addressing is simple. Just two registers, a base and
1270 // an offset. No shifts, negations or any other complicating factors.
1271 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1272 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1274 return isARMLowRegister(Memory.BaseRegNum) &&
1275 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1277 bool isMemThumbRIs4() const {
1278 if (!isMem() || Memory.OffsetRegNum != 0 ||
1279 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1281 // Immediate offset, multiple of 4 in range [0, 124].
1282 if (!Memory.OffsetImm) return true;
1283 int64_t Val = Memory.OffsetImm->getValue();
1284 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1286 bool isMemThumbRIs2() const {
1287 if (!isMem() || Memory.OffsetRegNum != 0 ||
1288 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1290 // Immediate offset, multiple of 4 in range [0, 62].
1291 if (!Memory.OffsetImm) return true;
1292 int64_t Val = Memory.OffsetImm->getValue();
1293 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1295 bool isMemThumbRIs1() const {
1296 if (!isMem() || Memory.OffsetRegNum != 0 ||
1297 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1299 // Immediate offset in range [0, 31].
1300 if (!Memory.OffsetImm) return true;
1301 int64_t Val = Memory.OffsetImm->getValue();
1302 return Val >= 0 && Val <= 31;
1304 bool isMemThumbSPI() const {
1305 if (!isMem() || Memory.OffsetRegNum != 0 ||
1306 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1308 // Immediate offset, multiple of 4 in range [0, 1020].
1309 if (!Memory.OffsetImm) return true;
1310 int64_t Val = Memory.OffsetImm->getValue();
1311 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1313 bool isMemImm8s4Offset() const {
1314 // If we have an immediate that's not a constant, treat it as a label
1315 // reference needing a fixup. If it is a constant, it's something else
1316 // and we reject it.
1317 if (isImm() && !isa<MCConstantExpr>(getImm()))
1319 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1321 // Immediate offset a multiple of 4 in range [-1020, 1020].
1322 if (!Memory.OffsetImm) return true;
1323 int64_t Val = Memory.OffsetImm->getValue();
1324 // Special case, #-0 is INT32_MIN.
1325 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1327 bool isMemImm0_1020s4Offset() const {
1328 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1330 // Immediate offset a multiple of 4 in range [0, 1020].
1331 if (!Memory.OffsetImm) return true;
1332 int64_t Val = Memory.OffsetImm->getValue();
1333 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1335 bool isMemImm8Offset() const {
1336 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1338 // Base reg of PC isn't allowed for these encodings.
1339 if (Memory.BaseRegNum == ARM::PC) return false;
1340 // Immediate offset in range [-255, 255].
1341 if (!Memory.OffsetImm) return true;
1342 int64_t Val = Memory.OffsetImm->getValue();
1343 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1345 bool isMemPosImm8Offset() const {
1346 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1348 // Immediate offset in range [0, 255].
1349 if (!Memory.OffsetImm) return true;
1350 int64_t Val = Memory.OffsetImm->getValue();
1351 return Val >= 0 && Val < 256;
1353 bool isMemNegImm8Offset() const {
1354 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1356 // Base reg of PC isn't allowed for these encodings.
1357 if (Memory.BaseRegNum == ARM::PC) return false;
1358 // Immediate offset in range [-255, -1].
1359 if (!Memory.OffsetImm) return false;
1360 int64_t Val = Memory.OffsetImm->getValue();
1361 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1363 bool isMemUImm12Offset() const {
1364 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1366 // Immediate offset in range [0, 4095].
1367 if (!Memory.OffsetImm) return true;
1368 int64_t Val = Memory.OffsetImm->getValue();
1369 return (Val >= 0 && Val < 4096);
1371 bool isMemImm12Offset() const {
1372 // If we have an immediate that's not a constant, treat it as a label
1373 // reference needing a fixup. If it is a constant, it's something else
1374 // and we reject it.
1375 if (isImm() && !isa<MCConstantExpr>(getImm()))
1378 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1380 // Immediate offset in range [-4095, 4095].
1381 if (!Memory.OffsetImm) return true;
1382 int64_t Val = Memory.OffsetImm->getValue();
1383 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1385 bool isPostIdxImm8() const {
1386 if (!isImm()) return false;
1387 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1388 if (!CE) return false;
1389 int64_t Val = CE->getValue();
1390 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1392 bool isPostIdxImm8s4() const {
1393 if (!isImm()) return false;
1394 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1395 if (!CE) return false;
1396 int64_t Val = CE->getValue();
1397 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1401 bool isMSRMask() const { return Kind == k_MSRMask; }
1402 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1405 bool isSingleSpacedVectorList() const {
1406 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1408 bool isDoubleSpacedVectorList() const {
1409 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1411 bool isVecListOneD() const {
1412 if (!isSingleSpacedVectorList()) return false;
1413 return VectorList.Count == 1;
1416 bool isVecListDPair() const {
1417 if (!isSingleSpacedVectorList()) return false;
1418 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1419 .contains(VectorList.RegNum));
1422 bool isVecListThreeD() const {
1423 if (!isSingleSpacedVectorList()) return false;
1424 return VectorList.Count == 3;
1427 bool isVecListFourD() const {
1428 if (!isSingleSpacedVectorList()) return false;
1429 return VectorList.Count == 4;
1432 bool isVecListDPairSpaced() const {
1433 if (Kind != k_VectorList) return false;
1434 if (isSingleSpacedVectorList()) return false;
1435 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1436 .contains(VectorList.RegNum));
1439 bool isVecListThreeQ() const {
1440 if (!isDoubleSpacedVectorList()) return false;
1441 return VectorList.Count == 3;
1444 bool isVecListFourQ() const {
1445 if (!isDoubleSpacedVectorList()) return false;
1446 return VectorList.Count == 4;
1449 bool isSingleSpacedVectorAllLanes() const {
1450 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1452 bool isDoubleSpacedVectorAllLanes() const {
1453 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1455 bool isVecListOneDAllLanes() const {
1456 if (!isSingleSpacedVectorAllLanes()) return false;
1457 return VectorList.Count == 1;
1460 bool isVecListDPairAllLanes() const {
1461 if (!isSingleSpacedVectorAllLanes()) return false;
1462 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1463 .contains(VectorList.RegNum));
1466 bool isVecListDPairSpacedAllLanes() const {
1467 if (!isDoubleSpacedVectorAllLanes()) return false;
1468 return VectorList.Count == 2;
1471 bool isVecListThreeDAllLanes() const {
1472 if (!isSingleSpacedVectorAllLanes()) return false;
1473 return VectorList.Count == 3;
1476 bool isVecListThreeQAllLanes() const {
1477 if (!isDoubleSpacedVectorAllLanes()) return false;
1478 return VectorList.Count == 3;
1481 bool isVecListFourDAllLanes() const {
1482 if (!isSingleSpacedVectorAllLanes()) return false;
1483 return VectorList.Count == 4;
1486 bool isVecListFourQAllLanes() const {
1487 if (!isDoubleSpacedVectorAllLanes()) return false;
1488 return VectorList.Count == 4;
1491 bool isSingleSpacedVectorIndexed() const {
1492 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1494 bool isDoubleSpacedVectorIndexed() const {
1495 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1497 bool isVecListOneDByteIndexed() const {
1498 if (!isSingleSpacedVectorIndexed()) return false;
1499 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1502 bool isVecListOneDHWordIndexed() const {
1503 if (!isSingleSpacedVectorIndexed()) return false;
1504 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1507 bool isVecListOneDWordIndexed() const {
1508 if (!isSingleSpacedVectorIndexed()) return false;
1509 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1512 bool isVecListTwoDByteIndexed() const {
1513 if (!isSingleSpacedVectorIndexed()) return false;
1514 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1517 bool isVecListTwoDHWordIndexed() const {
1518 if (!isSingleSpacedVectorIndexed()) return false;
1519 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1522 bool isVecListTwoQWordIndexed() const {
1523 if (!isDoubleSpacedVectorIndexed()) return false;
1524 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1527 bool isVecListTwoQHWordIndexed() const {
1528 if (!isDoubleSpacedVectorIndexed()) return false;
1529 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1532 bool isVecListTwoDWordIndexed() const {
1533 if (!isSingleSpacedVectorIndexed()) return false;
1534 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1537 bool isVecListThreeDByteIndexed() const {
1538 if (!isSingleSpacedVectorIndexed()) return false;
1539 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1542 bool isVecListThreeDHWordIndexed() const {
1543 if (!isSingleSpacedVectorIndexed()) return false;
1544 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1547 bool isVecListThreeQWordIndexed() const {
1548 if (!isDoubleSpacedVectorIndexed()) return false;
1549 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1552 bool isVecListThreeQHWordIndexed() const {
1553 if (!isDoubleSpacedVectorIndexed()) return false;
1554 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1557 bool isVecListThreeDWordIndexed() const {
1558 if (!isSingleSpacedVectorIndexed()) return false;
1559 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1562 bool isVecListFourDByteIndexed() const {
1563 if (!isSingleSpacedVectorIndexed()) return false;
1564 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1567 bool isVecListFourDHWordIndexed() const {
1568 if (!isSingleSpacedVectorIndexed()) return false;
1569 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1572 bool isVecListFourQWordIndexed() const {
1573 if (!isDoubleSpacedVectorIndexed()) return false;
1574 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1577 bool isVecListFourQHWordIndexed() const {
1578 if (!isDoubleSpacedVectorIndexed()) return false;
1579 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1582 bool isVecListFourDWordIndexed() const {
1583 if (!isSingleSpacedVectorIndexed()) return false;
1584 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1587 bool isVectorIndex8() const {
1588 if (Kind != k_VectorIndex) return false;
1589 return VectorIndex.Val < 8;
1591 bool isVectorIndex16() const {
1592 if (Kind != k_VectorIndex) return false;
1593 return VectorIndex.Val < 4;
1595 bool isVectorIndex32() const {
1596 if (Kind != k_VectorIndex) return false;
1597 return VectorIndex.Val < 2;
1600 bool isNEONi8splat() const {
1601 if (!isImm()) return false;
1602 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1603 // Must be a constant.
1604 if (!CE) return false;
1605 int64_t Value = CE->getValue();
1606 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1608 return Value >= 0 && Value < 256;
1611 bool isNEONi16splat() const {
1612 if (!isImm()) return false;
1613 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1614 // Must be a constant.
1615 if (!CE) return false;
1616 int64_t Value = CE->getValue();
1617 // i16 value in the range [0,255] or [0x0100, 0xff00]
1618 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1621 bool isNEONi32splat() const {
1622 if (!isImm()) return false;
1623 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1624 // Must be a constant.
1625 if (!CE) return false;
1626 int64_t Value = CE->getValue();
1627 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1628 return (Value >= 0 && Value < 256) ||
1629 (Value >= 0x0100 && Value <= 0xff00) ||
1630 (Value >= 0x010000 && Value <= 0xff0000) ||
1631 (Value >= 0x01000000 && Value <= 0xff000000);
1634 bool isNEONi32vmov() const {
1635 if (!isImm()) return false;
1636 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1637 // Must be a constant.
1638 if (!CE) return false;
1639 int64_t Value = CE->getValue();
1640 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1641 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1642 return (Value >= 0 && Value < 256) ||
1643 (Value >= 0x0100 && Value <= 0xff00) ||
1644 (Value >= 0x010000 && Value <= 0xff0000) ||
1645 (Value >= 0x01000000 && Value <= 0xff000000) ||
1646 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1647 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1649 bool isNEONi32vmovNeg() const {
1650 if (!isImm()) return false;
1651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1652 // Must be a constant.
1653 if (!CE) return false;
1654 int64_t Value = ~CE->getValue();
1655 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1656 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1657 return (Value >= 0 && Value < 256) ||
1658 (Value >= 0x0100 && Value <= 0xff00) ||
1659 (Value >= 0x010000 && Value <= 0xff0000) ||
1660 (Value >= 0x01000000 && Value <= 0xff000000) ||
1661 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1662 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1665 bool isNEONi64splat() const {
1666 if (!isImm()) return false;
1667 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1668 // Must be a constant.
1669 if (!CE) return false;
1670 uint64_t Value = CE->getValue();
1671 // i64 value with each byte being either 0 or 0xff.
1672 for (unsigned i = 0; i < 8; ++i)
1673 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1677 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1678 // Add as immediates when possible. Null MCExpr = 0.
1680 Inst.addOperand(MCOperand::CreateImm(0));
1681 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1682 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1684 Inst.addOperand(MCOperand::CreateExpr(Expr));
1687 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1688 assert(N == 2 && "Invalid number of operands!");
1689 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1690 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1691 Inst.addOperand(MCOperand::CreateReg(RegNum));
1694 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1695 assert(N == 1 && "Invalid number of operands!");
1696 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1699 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1700 assert(N == 1 && "Invalid number of operands!");
1701 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1704 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1705 assert(N == 1 && "Invalid number of operands!");
1706 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1709 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1710 assert(N == 1 && "Invalid number of operands!");
1711 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1714 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1715 assert(N == 1 && "Invalid number of operands!");
1716 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1719 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1720 assert(N == 1 && "Invalid number of operands!");
1721 Inst.addOperand(MCOperand::CreateReg(getReg()));
1724 void addRegOperands(MCInst &Inst, unsigned N) const {
1725 assert(N == 1 && "Invalid number of operands!");
1726 Inst.addOperand(MCOperand::CreateReg(getReg()));
1729 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1730 assert(N == 3 && "Invalid number of operands!");
1731 assert(isRegShiftedReg() &&
1732 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1733 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1734 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1735 Inst.addOperand(MCOperand::CreateImm(
1736 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1739 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1740 assert(N == 2 && "Invalid number of operands!");
1741 assert(isRegShiftedImm() &&
1742 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1743 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1744 // Shift of #32 is encoded as 0 where permitted
1745 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1746 Inst.addOperand(MCOperand::CreateImm(
1747 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1750 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1751 assert(N == 1 && "Invalid number of operands!");
1752 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1756 void addRegListOperands(MCInst &Inst, unsigned N) const {
1757 assert(N == 1 && "Invalid number of operands!");
1758 const SmallVectorImpl<unsigned> &RegList = getRegList();
1759 for (SmallVectorImpl<unsigned>::const_iterator
1760 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1761 Inst.addOperand(MCOperand::CreateReg(*I));
1764 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1765 addRegListOperands(Inst, N);
1768 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1769 addRegListOperands(Inst, N);
1772 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1773 assert(N == 1 && "Invalid number of operands!");
1774 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1775 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1778 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1779 assert(N == 1 && "Invalid number of operands!");
1780 // Munge the lsb/width into a bitfield mask.
1781 unsigned lsb = Bitfield.LSB;
1782 unsigned width = Bitfield.Width;
1783 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1784 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1785 (32 - (lsb + width)));
1786 Inst.addOperand(MCOperand::CreateImm(Mask));
1789 void addImmOperands(MCInst &Inst, unsigned N) const {
1790 assert(N == 1 && "Invalid number of operands!");
1791 addExpr(Inst, getImm());
1794 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1795 assert(N == 1 && "Invalid number of operands!");
1796 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1797 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1800 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1801 assert(N == 1 && "Invalid number of operands!");
1802 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1803 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1806 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1807 assert(N == 1 && "Invalid number of operands!");
1808 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1809 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1810 Inst.addOperand(MCOperand::CreateImm(Val));
1813 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1814 assert(N == 1 && "Invalid number of operands!");
1815 // FIXME: We really want to scale the value here, but the LDRD/STRD
1816 // instruction don't encode operands that way yet.
1817 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1818 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1821 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1822 assert(N == 1 && "Invalid number of operands!");
1823 // The immediate is scaled by four in the encoding and is stored
1824 // in the MCInst as such. Lop off the low two bits here.
1825 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1826 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1829 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1830 assert(N == 1 && "Invalid number of operands!");
1831 // The immediate is scaled by four in the encoding and is stored
1832 // in the MCInst as such. Lop off the low two bits here.
1833 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1834 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1837 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1838 assert(N == 1 && "Invalid number of operands!");
1839 // The immediate is scaled by four in the encoding and is stored
1840 // in the MCInst as such. Lop off the low two bits here.
1841 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1842 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1845 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1846 assert(N == 1 && "Invalid number of operands!");
1847 // The constant encodes as the immediate-1, and we store in the instruction
1848 // the bits as encoded, so subtract off one here.
1849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1850 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1853 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1854 assert(N == 1 && "Invalid number of operands!");
1855 // The constant encodes as the immediate-1, and we store in the instruction
1856 // the bits as encoded, so subtract off one here.
1857 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1858 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1861 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1862 assert(N == 1 && "Invalid number of operands!");
1863 // The constant encodes as the immediate, except for 32, which encodes as
1865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1866 unsigned Imm = CE->getValue();
1867 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1870 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1871 assert(N == 1 && "Invalid number of operands!");
1872 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1873 // the instruction as well.
1874 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1875 int Val = CE->getValue();
1876 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1879 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1880 assert(N == 1 && "Invalid number of operands!");
1881 // The operand is actually a t2_so_imm, but we have its bitwise
1882 // negation in the assembly source, so twiddle it here.
1883 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1884 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1887 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1888 assert(N == 1 && "Invalid number of operands!");
1889 // The operand is actually a t2_so_imm, but we have its
1890 // negation in the assembly source, so twiddle it here.
1891 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1892 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1895 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1896 assert(N == 1 && "Invalid number of operands!");
1897 // The operand is actually an imm0_4095, but we have its
1898 // negation in the assembly source, so twiddle it here.
1899 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1900 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1903 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1904 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1905 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1909 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1910 assert(SR && "Unknown value type!");
1911 Inst.addOperand(MCOperand::CreateExpr(SR));
1914 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1915 assert(N == 1 && "Invalid number of operands!");
1917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1919 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1923 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1924 assert(SR && "Unknown value type!");
1925 Inst.addOperand(MCOperand::CreateExpr(SR));
1929 assert(isMem() && "Unknown value type!");
1930 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1931 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1934 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1935 assert(N == 1 && "Invalid number of operands!");
1936 // The operand is actually a so_imm, but we have its bitwise
1937 // negation in the assembly source, so twiddle it here.
1938 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1939 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1942 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1943 assert(N == 1 && "Invalid number of operands!");
1944 // The operand is actually a so_imm, but we have its
1945 // negation in the assembly source, so twiddle it here.
1946 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1947 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1950 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1951 assert(N == 1 && "Invalid number of operands!");
1952 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1955 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1956 assert(N == 1 && "Invalid number of operands!");
1957 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1960 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1961 assert(N == 1 && "Invalid number of operands!");
1962 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1965 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1966 assert(N == 1 && "Invalid number of operands!");
1967 int32_t Imm = Memory.OffsetImm->getValue();
1968 Inst.addOperand(MCOperand::CreateImm(Imm));
1971 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1972 assert(N == 1 && "Invalid number of operands!");
1973 assert(isImm() && "Not an immediate!");
1975 // If we have an immediate that's not a constant, treat it as a label
1976 // reference needing a fixup.
1977 if (!isa<MCConstantExpr>(getImm())) {
1978 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1982 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1983 int Val = CE->getValue();
1984 Inst.addOperand(MCOperand::CreateImm(Val));
1987 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1988 assert(N == 2 && "Invalid number of operands!");
1989 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1990 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1993 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
1994 addAlignedMemoryOperands(Inst, N);
1997 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
1998 addAlignedMemoryOperands(Inst, N);
2001 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2002 addAlignedMemoryOperands(Inst, N);
2005 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2006 addAlignedMemoryOperands(Inst, N);
2009 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2010 addAlignedMemoryOperands(Inst, N);
2013 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2014 addAlignedMemoryOperands(Inst, N);
2017 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2018 addAlignedMemoryOperands(Inst, N);
2021 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2022 addAlignedMemoryOperands(Inst, N);
2025 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2026 addAlignedMemoryOperands(Inst, N);
2029 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2030 addAlignedMemoryOperands(Inst, N);
2033 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2034 addAlignedMemoryOperands(Inst, N);
2037 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2038 assert(N == 3 && "Invalid number of operands!");
2039 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2040 if (!Memory.OffsetRegNum) {
2041 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2042 // Special case for #-0
2043 if (Val == INT32_MIN) Val = 0;
2044 if (Val < 0) Val = -Val;
2045 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2047 // For register offset, we encode the shift type and negation flag
2049 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2050 Memory.ShiftImm, Memory.ShiftType);
2052 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2053 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2054 Inst.addOperand(MCOperand::CreateImm(Val));
2057 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2058 assert(N == 2 && "Invalid number of operands!");
2059 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2060 assert(CE && "non-constant AM2OffsetImm operand!");
2061 int32_t Val = CE->getValue();
2062 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2063 // Special case for #-0
2064 if (Val == INT32_MIN) Val = 0;
2065 if (Val < 0) Val = -Val;
2066 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2067 Inst.addOperand(MCOperand::CreateReg(0));
2068 Inst.addOperand(MCOperand::CreateImm(Val));
2071 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2072 assert(N == 3 && "Invalid number of operands!");
2073 // If we have an immediate that's not a constant, treat it as a label
2074 // reference needing a fixup. If it is a constant, it's something else
2075 // and we reject it.
2077 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2078 Inst.addOperand(MCOperand::CreateReg(0));
2079 Inst.addOperand(MCOperand::CreateImm(0));
2083 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2084 if (!Memory.OffsetRegNum) {
2085 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2086 // Special case for #-0
2087 if (Val == INT32_MIN) Val = 0;
2088 if (Val < 0) Val = -Val;
2089 Val = ARM_AM::getAM3Opc(AddSub, Val);
2091 // For register offset, we encode the shift type and negation flag
2093 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2095 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2096 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2097 Inst.addOperand(MCOperand::CreateImm(Val));
2100 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2101 assert(N == 2 && "Invalid number of operands!");
2102 if (Kind == k_PostIndexRegister) {
2104 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2105 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2106 Inst.addOperand(MCOperand::CreateImm(Val));
2111 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2112 int32_t Val = CE->getValue();
2113 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2114 // Special case for #-0
2115 if (Val == INT32_MIN) Val = 0;
2116 if (Val < 0) Val = -Val;
2117 Val = ARM_AM::getAM3Opc(AddSub, Val);
2118 Inst.addOperand(MCOperand::CreateReg(0));
2119 Inst.addOperand(MCOperand::CreateImm(Val));
2122 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2123 assert(N == 2 && "Invalid number of operands!");
2124 // If we have an immediate that's not a constant, treat it as a label
2125 // reference needing a fixup. If it is a constant, it's something else
2126 // and we reject it.
2128 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2129 Inst.addOperand(MCOperand::CreateImm(0));
2133 // The lower two bits are always zero and as such are not encoded.
2134 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2135 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2136 // Special case for #-0
2137 if (Val == INT32_MIN) Val = 0;
2138 if (Val < 0) Val = -Val;
2139 Val = ARM_AM::getAM5Opc(AddSub, Val);
2140 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2141 Inst.addOperand(MCOperand::CreateImm(Val));
2144 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2145 assert(N == 2 && "Invalid number of operands!");
2146 // If we have an immediate that's not a constant, treat it as a label
2147 // reference needing a fixup. If it is a constant, it's something else
2148 // and we reject it.
2150 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2151 Inst.addOperand(MCOperand::CreateImm(0));
2155 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2156 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2157 Inst.addOperand(MCOperand::CreateImm(Val));
2160 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2161 assert(N == 2 && "Invalid number of operands!");
2162 // The lower two bits are always zero and as such are not encoded.
2163 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2164 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2165 Inst.addOperand(MCOperand::CreateImm(Val));
2168 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2169 assert(N == 2 && "Invalid number of operands!");
2170 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2171 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2172 Inst.addOperand(MCOperand::CreateImm(Val));
2175 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2176 addMemImm8OffsetOperands(Inst, N);
2179 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2180 addMemImm8OffsetOperands(Inst, N);
2183 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2184 assert(N == 2 && "Invalid number of operands!");
2185 // If this is an immediate, it's a label reference.
2187 addExpr(Inst, getImm());
2188 Inst.addOperand(MCOperand::CreateImm(0));
2192 // Otherwise, it's a normal memory reg+offset.
2193 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2194 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2195 Inst.addOperand(MCOperand::CreateImm(Val));
2198 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2199 assert(N == 2 && "Invalid number of operands!");
2200 // If this is an immediate, it's a label reference.
2202 addExpr(Inst, getImm());
2203 Inst.addOperand(MCOperand::CreateImm(0));
2207 // Otherwise, it's a normal memory reg+offset.
2208 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2209 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2210 Inst.addOperand(MCOperand::CreateImm(Val));
2213 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2214 assert(N == 2 && "Invalid number of operands!");
2215 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2216 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2219 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2220 assert(N == 2 && "Invalid number of operands!");
2221 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2222 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2225 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2226 assert(N == 3 && "Invalid number of operands!");
2228 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2229 Memory.ShiftImm, Memory.ShiftType);
2230 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2231 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2232 Inst.addOperand(MCOperand::CreateImm(Val));
2235 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2236 assert(N == 3 && "Invalid number of operands!");
2237 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2238 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2239 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2242 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2243 assert(N == 2 && "Invalid number of operands!");
2244 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2245 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2248 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2249 assert(N == 2 && "Invalid number of operands!");
2250 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2251 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2252 Inst.addOperand(MCOperand::CreateImm(Val));
2255 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2256 assert(N == 2 && "Invalid number of operands!");
2257 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2258 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2259 Inst.addOperand(MCOperand::CreateImm(Val));
2262 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2263 assert(N == 2 && "Invalid number of operands!");
2264 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2265 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2266 Inst.addOperand(MCOperand::CreateImm(Val));
2269 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2270 assert(N == 2 && "Invalid number of operands!");
2271 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2272 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2273 Inst.addOperand(MCOperand::CreateImm(Val));
2276 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2277 assert(N == 1 && "Invalid number of operands!");
2278 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2279 assert(CE && "non-constant post-idx-imm8 operand!");
2280 int Imm = CE->getValue();
2281 bool isAdd = Imm >= 0;
2282 if (Imm == INT32_MIN) Imm = 0;
2283 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2284 Inst.addOperand(MCOperand::CreateImm(Imm));
2287 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2288 assert(N == 1 && "Invalid number of operands!");
2289 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2290 assert(CE && "non-constant post-idx-imm8s4 operand!");
2291 int Imm = CE->getValue();
2292 bool isAdd = Imm >= 0;
2293 if (Imm == INT32_MIN) Imm = 0;
2294 // Immediate is scaled by 4.
2295 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2296 Inst.addOperand(MCOperand::CreateImm(Imm));
2299 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2300 assert(N == 2 && "Invalid number of operands!");
2301 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2302 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2305 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2306 assert(N == 2 && "Invalid number of operands!");
2307 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2308 // The sign, shift type, and shift amount are encoded in a single operand
2309 // using the AM2 encoding helpers.
2310 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2311 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2312 PostIdxReg.ShiftTy);
2313 Inst.addOperand(MCOperand::CreateImm(Imm));
2316 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2317 assert(N == 1 && "Invalid number of operands!");
2318 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2321 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2322 assert(N == 1 && "Invalid number of operands!");
2323 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2326 void addVecListOperands(MCInst &Inst, unsigned N) const {
2327 assert(N == 1 && "Invalid number of operands!");
2328 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2331 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2332 assert(N == 2 && "Invalid number of operands!");
2333 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2334 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2337 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2338 assert(N == 1 && "Invalid number of operands!");
2339 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2342 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2343 assert(N == 1 && "Invalid number of operands!");
2344 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2347 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2348 assert(N == 1 && "Invalid number of operands!");
2349 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2352 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2353 assert(N == 1 && "Invalid number of operands!");
2354 // The immediate encodes the type of constant as well as the value.
2355 // Mask in that this is an i8 splat.
2356 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2357 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2360 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2361 assert(N == 1 && "Invalid number of operands!");
2362 // The immediate encodes the type of constant as well as the value.
2363 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2364 unsigned Value = CE->getValue();
2366 Value = (Value >> 8) | 0xa00;
2369 Inst.addOperand(MCOperand::CreateImm(Value));
2372 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2373 assert(N == 1 && "Invalid number of operands!");
2374 // The immediate encodes the type of constant as well as the value.
2375 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2376 unsigned Value = CE->getValue();
2377 if (Value >= 256 && Value <= 0xff00)
2378 Value = (Value >> 8) | 0x200;
2379 else if (Value > 0xffff && Value <= 0xff0000)
2380 Value = (Value >> 16) | 0x400;
2381 else if (Value > 0xffffff)
2382 Value = (Value >> 24) | 0x600;
2383 Inst.addOperand(MCOperand::CreateImm(Value));
2386 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2387 assert(N == 1 && "Invalid number of operands!");
2388 // The immediate encodes the type of constant as well as the value.
2389 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2390 unsigned Value = CE->getValue();
2391 if (Value >= 256 && Value <= 0xffff)
2392 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2393 else if (Value > 0xffff && Value <= 0xffffff)
2394 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2395 else if (Value > 0xffffff)
2396 Value = (Value >> 24) | 0x600;
2397 Inst.addOperand(MCOperand::CreateImm(Value));
2400 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2401 assert(N == 1 && "Invalid number of operands!");
2402 // The immediate encodes the type of constant as well as the value.
2403 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2404 unsigned Value = ~CE->getValue();
2405 if (Value >= 256 && Value <= 0xffff)
2406 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2407 else if (Value > 0xffff && Value <= 0xffffff)
2408 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2409 else if (Value > 0xffffff)
2410 Value = (Value >> 24) | 0x600;
2411 Inst.addOperand(MCOperand::CreateImm(Value));
2414 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2415 assert(N == 1 && "Invalid number of operands!");
2416 // The immediate encodes the type of constant as well as the value.
2417 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2418 uint64_t Value = CE->getValue();
2420 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2421 Imm |= (Value & 1) << i;
2423 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2426 void print(raw_ostream &OS) const override;
2428 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2429 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2430 Op->ITMask.Mask = Mask;
2436 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2437 ARMOperand *Op = new ARMOperand(k_CondCode);
2444 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2445 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2446 Op->Cop.Val = CopVal;
2452 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2453 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2454 Op->Cop.Val = CopVal;
2460 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2461 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2468 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2469 ARMOperand *Op = new ARMOperand(k_CCOut);
2470 Op->Reg.RegNum = RegNum;
2476 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2477 ARMOperand *Op = new ARMOperand(k_Token);
2478 Op->Tok.Data = Str.data();
2479 Op->Tok.Length = Str.size();
2485 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2486 ARMOperand *Op = new ARMOperand(k_Register);
2487 Op->Reg.RegNum = RegNum;
2493 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2498 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2499 Op->RegShiftedReg.ShiftTy = ShTy;
2500 Op->RegShiftedReg.SrcReg = SrcReg;
2501 Op->RegShiftedReg.ShiftReg = ShiftReg;
2502 Op->RegShiftedReg.ShiftImm = ShiftImm;
2508 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2512 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2513 Op->RegShiftedImm.ShiftTy = ShTy;
2514 Op->RegShiftedImm.SrcReg = SrcReg;
2515 Op->RegShiftedImm.ShiftImm = ShiftImm;
2521 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2523 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2524 Op->ShifterImm.isASR = isASR;
2525 Op->ShifterImm.Imm = Imm;
2531 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2532 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2533 Op->RotImm.Imm = Imm;
2539 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2541 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2542 Op->Bitfield.LSB = LSB;
2543 Op->Bitfield.Width = Width;
2550 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2551 SMLoc StartLoc, SMLoc EndLoc) {
2552 assert (Regs.size() > 0 && "RegList contains no registers?");
2553 KindTy Kind = k_RegisterList;
2555 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2556 Kind = k_DPRRegisterList;
2557 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2558 contains(Regs.front().second))
2559 Kind = k_SPRRegisterList;
2561 // Sort based on the register encoding values.
2562 array_pod_sort(Regs.begin(), Regs.end());
2564 ARMOperand *Op = new ARMOperand(Kind);
2565 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2566 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2567 Op->Registers.push_back(I->second);
2568 Op->StartLoc = StartLoc;
2569 Op->EndLoc = EndLoc;
2573 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2574 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2575 ARMOperand *Op = new ARMOperand(k_VectorList);
2576 Op->VectorList.RegNum = RegNum;
2577 Op->VectorList.Count = Count;
2578 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2584 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2585 bool isDoubleSpaced,
2587 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2588 Op->VectorList.RegNum = RegNum;
2589 Op->VectorList.Count = Count;
2590 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2596 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2598 bool isDoubleSpaced,
2600 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2601 Op->VectorList.RegNum = RegNum;
2602 Op->VectorList.Count = Count;
2603 Op->VectorList.LaneIndex = Index;
2604 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2610 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2612 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2613 Op->VectorIndex.Val = Idx;
2619 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2620 ARMOperand *Op = new ARMOperand(k_Immediate);
2627 static ARMOperand *CreateMem(unsigned BaseRegNum,
2628 const MCConstantExpr *OffsetImm,
2629 unsigned OffsetRegNum,
2630 ARM_AM::ShiftOpc ShiftType,
2635 SMLoc AlignmentLoc = SMLoc()) {
2636 ARMOperand *Op = new ARMOperand(k_Memory);
2637 Op->Memory.BaseRegNum = BaseRegNum;
2638 Op->Memory.OffsetImm = OffsetImm;
2639 Op->Memory.OffsetRegNum = OffsetRegNum;
2640 Op->Memory.ShiftType = ShiftType;
2641 Op->Memory.ShiftImm = ShiftImm;
2642 Op->Memory.Alignment = Alignment;
2643 Op->Memory.isNegative = isNegative;
2646 Op->AlignmentLoc = AlignmentLoc;
2650 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2651 ARM_AM::ShiftOpc ShiftTy,
2654 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2655 Op->PostIdxReg.RegNum = RegNum;
2656 Op->PostIdxReg.isAdd = isAdd;
2657 Op->PostIdxReg.ShiftTy = ShiftTy;
2658 Op->PostIdxReg.ShiftImm = ShiftImm;
2664 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2665 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2666 Op->MBOpt.Val = Opt;
2672 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2674 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2675 Op->ISBOpt.Val = Opt;
2681 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2682 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2683 Op->IFlags.Val = IFlags;
2689 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2690 ARMOperand *Op = new ARMOperand(k_MSRMask);
2691 Op->MMask.Val = MMask;
2698 } // end anonymous namespace.
2700 void ARMOperand::print(raw_ostream &OS) const {
2703 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2706 OS << "<ccout " << getReg() << ">";
2708 case k_ITCondMask: {
2709 static const char *const MaskStr[] = {
2710 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2711 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2713 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2714 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2718 OS << "<coprocessor number: " << getCoproc() << ">";
2721 OS << "<coprocessor register: " << getCoproc() << ">";
2723 case k_CoprocOption:
2724 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2727 OS << "<mask: " << getMSRMask() << ">";
2730 getImm()->print(OS);
2732 case k_MemBarrierOpt:
2733 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2735 case k_InstSyncBarrierOpt:
2736 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2740 << " base:" << Memory.BaseRegNum;
2743 case k_PostIndexRegister:
2744 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2745 << PostIdxReg.RegNum;
2746 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2747 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2748 << PostIdxReg.ShiftImm;
2751 case k_ProcIFlags: {
2752 OS << "<ARM_PROC::";
2753 unsigned IFlags = getProcIFlags();
2754 for (int i=2; i >= 0; --i)
2755 if (IFlags & (1 << i))
2756 OS << ARM_PROC::IFlagsToString(1 << i);
2761 OS << "<register " << getReg() << ">";
2763 case k_ShifterImmediate:
2764 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2765 << " #" << ShifterImm.Imm << ">";
2767 case k_ShiftedRegister:
2768 OS << "<so_reg_reg "
2769 << RegShiftedReg.SrcReg << " "
2770 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2771 << " " << RegShiftedReg.ShiftReg << ">";
2773 case k_ShiftedImmediate:
2774 OS << "<so_reg_imm "
2775 << RegShiftedImm.SrcReg << " "
2776 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2777 << " #" << RegShiftedImm.ShiftImm << ">";
2779 case k_RotateImmediate:
2780 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2782 case k_BitfieldDescriptor:
2783 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2784 << ", width: " << Bitfield.Width << ">";
2786 case k_RegisterList:
2787 case k_DPRRegisterList:
2788 case k_SPRRegisterList: {
2789 OS << "<register_list ";
2791 const SmallVectorImpl<unsigned> &RegList = getRegList();
2792 for (SmallVectorImpl<unsigned>::const_iterator
2793 I = RegList.begin(), E = RegList.end(); I != E; ) {
2795 if (++I < E) OS << ", ";
2802 OS << "<vector_list " << VectorList.Count << " * "
2803 << VectorList.RegNum << ">";
2805 case k_VectorListAllLanes:
2806 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2807 << VectorList.RegNum << ">";
2809 case k_VectorListIndexed:
2810 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2811 << VectorList.Count << " * " << VectorList.RegNum << ">";
2814 OS << "'" << getToken() << "'";
2817 OS << "<vectorindex " << getVectorIndex() << ">";
2822 /// @name Auto-generated Match Functions
2825 static unsigned MatchRegisterName(StringRef Name);
2829 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2830 SMLoc &StartLoc, SMLoc &EndLoc) {
2831 StartLoc = Parser.getTok().getLoc();
2832 EndLoc = Parser.getTok().getEndLoc();
2833 RegNo = tryParseRegister();
2835 return (RegNo == (unsigned)-1);
2838 /// Try to parse a register name. The token must be an Identifier when called,
2839 /// and if it is a register name the token is eaten and the register number is
2840 /// returned. Otherwise return -1.
2842 int ARMAsmParser::tryParseRegister() {
2843 const AsmToken &Tok = Parser.getTok();
2844 if (Tok.isNot(AsmToken::Identifier)) return -1;
2846 std::string lowerCase = Tok.getString().lower();
2847 unsigned RegNum = MatchRegisterName(lowerCase);
2849 RegNum = StringSwitch<unsigned>(lowerCase)
2850 .Case("r13", ARM::SP)
2851 .Case("r14", ARM::LR)
2852 .Case("r15", ARM::PC)
2853 .Case("ip", ARM::R12)
2854 // Additional register name aliases for 'gas' compatibility.
2855 .Case("a1", ARM::R0)
2856 .Case("a2", ARM::R1)
2857 .Case("a3", ARM::R2)
2858 .Case("a4", ARM::R3)
2859 .Case("v1", ARM::R4)
2860 .Case("v2", ARM::R5)
2861 .Case("v3", ARM::R6)
2862 .Case("v4", ARM::R7)
2863 .Case("v5", ARM::R8)
2864 .Case("v6", ARM::R9)
2865 .Case("v7", ARM::R10)
2866 .Case("v8", ARM::R11)
2867 .Case("sb", ARM::R9)
2868 .Case("sl", ARM::R10)
2869 .Case("fp", ARM::R11)
2873 // Check for aliases registered via .req. Canonicalize to lower case.
2874 // That's more consistent since register names are case insensitive, and
2875 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2876 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2877 // If no match, return failure.
2878 if (Entry == RegisterReqs.end())
2880 Parser.Lex(); // Eat identifier token.
2881 return Entry->getValue();
2884 Parser.Lex(); // Eat identifier token.
2889 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2890 // If a recoverable error occurs, return 1. If an irrecoverable error
2891 // occurs, return -1. An irrecoverable error is one where tokens have been
2892 // consumed in the process of trying to parse the shifter (i.e., when it is
2893 // indeed a shifter operand, but malformed).
2894 int ARMAsmParser::tryParseShiftRegister(
2895 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2896 SMLoc S = Parser.getTok().getLoc();
2897 const AsmToken &Tok = Parser.getTok();
2898 if (Tok.isNot(AsmToken::Identifier))
2901 std::string lowerCase = Tok.getString().lower();
2902 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2903 .Case("asl", ARM_AM::lsl)
2904 .Case("lsl", ARM_AM::lsl)
2905 .Case("lsr", ARM_AM::lsr)
2906 .Case("asr", ARM_AM::asr)
2907 .Case("ror", ARM_AM::ror)
2908 .Case("rrx", ARM_AM::rrx)
2909 .Default(ARM_AM::no_shift);
2911 if (ShiftTy == ARM_AM::no_shift)
2914 Parser.Lex(); // Eat the operator.
2916 // The source register for the shift has already been added to the
2917 // operand list, so we need to pop it off and combine it into the shifted
2918 // register operand instead.
2919 std::unique_ptr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2920 if (!PrevOp->isReg())
2921 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2922 int SrcReg = PrevOp->getReg();
2927 if (ShiftTy == ARM_AM::rrx) {
2928 // RRX Doesn't have an explicit shift amount. The encoder expects
2929 // the shift register to be the same as the source register. Seems odd,
2933 // Figure out if this is shifted by a constant or a register (for non-RRX).
2934 if (Parser.getTok().is(AsmToken::Hash) ||
2935 Parser.getTok().is(AsmToken::Dollar)) {
2936 Parser.Lex(); // Eat hash.
2937 SMLoc ImmLoc = Parser.getTok().getLoc();
2938 const MCExpr *ShiftExpr = 0;
2939 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2940 Error(ImmLoc, "invalid immediate shift value");
2943 // The expression must be evaluatable as an immediate.
2944 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2946 Error(ImmLoc, "invalid immediate shift value");
2949 // Range check the immediate.
2950 // lsl, ror: 0 <= imm <= 31
2951 // lsr, asr: 0 <= imm <= 32
2952 Imm = CE->getValue();
2954 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2955 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2956 Error(ImmLoc, "immediate shift value out of range");
2959 // shift by zero is a nop. Always send it through as lsl.
2960 // ('as' compatibility)
2962 ShiftTy = ARM_AM::lsl;
2963 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2964 SMLoc L = Parser.getTok().getLoc();
2965 EndLoc = Parser.getTok().getEndLoc();
2966 ShiftReg = tryParseRegister();
2967 if (ShiftReg == -1) {
2968 Error (L, "expected immediate or register in shift operand");
2972 Error (Parser.getTok().getLoc(),
2973 "expected immediate or register in shift operand");
2978 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2979 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2983 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2990 /// Try to parse a register name. The token must be an Identifier when called.
2991 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2992 /// if there is a "writeback". 'true' if it's not a register.
2994 /// TODO this is likely to change to allow different register types and or to
2995 /// parse for a specific register type.
2997 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2998 const AsmToken &RegTok = Parser.getTok();
2999 int RegNo = tryParseRegister();
3003 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3004 RegTok.getEndLoc()));
3006 const AsmToken &ExclaimTok = Parser.getTok();
3007 if (ExclaimTok.is(AsmToken::Exclaim)) {
3008 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3009 ExclaimTok.getLoc()));
3010 Parser.Lex(); // Eat exclaim token
3014 // Also check for an index operand. This is only legal for vector registers,
3015 // but that'll get caught OK in operand matching, so we don't need to
3016 // explicitly filter everything else out here.
3017 if (Parser.getTok().is(AsmToken::LBrac)) {
3018 SMLoc SIdx = Parser.getTok().getLoc();
3019 Parser.Lex(); // Eat left bracket token.
3021 const MCExpr *ImmVal;
3022 if (getParser().parseExpression(ImmVal))
3024 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3026 return TokError("immediate value expected for vector index");
3028 if (Parser.getTok().isNot(AsmToken::RBrac))
3029 return Error(Parser.getTok().getLoc(), "']' expected");
3031 SMLoc E = Parser.getTok().getEndLoc();
3032 Parser.Lex(); // Eat right bracket token.
3034 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3042 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3043 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
3045 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3046 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3048 switch (Name.size()) {
3051 if (Name[0] != CoprocOp)
3067 if (Name[0] != CoprocOp || Name[1] != '1')
3071 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
3072 case '0': return CoprocOp == 'p'? -1: 10;
3073 case '1': return CoprocOp == 'p'? -1: 11;
3074 case '2': return 12;
3075 case '3': return 13;
3076 case '4': return 14;
3077 case '5': return 15;
3082 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3083 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3084 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3085 SMLoc S = Parser.getTok().getLoc();
3086 const AsmToken &Tok = Parser.getTok();
3087 if (!Tok.is(AsmToken::Identifier))
3088 return MatchOperand_NoMatch;
3089 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3090 .Case("eq", ARMCC::EQ)
3091 .Case("ne", ARMCC::NE)
3092 .Case("hs", ARMCC::HS)
3093 .Case("cs", ARMCC::HS)
3094 .Case("lo", ARMCC::LO)
3095 .Case("cc", ARMCC::LO)
3096 .Case("mi", ARMCC::MI)
3097 .Case("pl", ARMCC::PL)
3098 .Case("vs", ARMCC::VS)
3099 .Case("vc", ARMCC::VC)
3100 .Case("hi", ARMCC::HI)
3101 .Case("ls", ARMCC::LS)
3102 .Case("ge", ARMCC::GE)
3103 .Case("lt", ARMCC::LT)
3104 .Case("gt", ARMCC::GT)
3105 .Case("le", ARMCC::LE)
3106 .Case("al", ARMCC::AL)
3109 return MatchOperand_NoMatch;
3110 Parser.Lex(); // Eat the token.
3112 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3114 return MatchOperand_Success;
3117 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3118 /// token must be an Identifier when called, and if it is a coprocessor
3119 /// number, the token is eaten and the operand is added to the operand list.
3120 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3121 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3122 SMLoc S = Parser.getTok().getLoc();
3123 const AsmToken &Tok = Parser.getTok();
3124 if (Tok.isNot(AsmToken::Identifier))
3125 return MatchOperand_NoMatch;
3127 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3129 return MatchOperand_NoMatch;
3131 Parser.Lex(); // Eat identifier token.
3132 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3133 return MatchOperand_Success;
3136 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3137 /// token must be an Identifier when called, and if it is a coprocessor
3138 /// number, the token is eaten and the operand is added to the operand list.
3139 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3140 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3141 SMLoc S = Parser.getTok().getLoc();
3142 const AsmToken &Tok = Parser.getTok();
3143 if (Tok.isNot(AsmToken::Identifier))
3144 return MatchOperand_NoMatch;
3146 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3148 return MatchOperand_NoMatch;
3150 Parser.Lex(); // Eat identifier token.
3151 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3152 return MatchOperand_Success;
3155 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3156 /// coproc_option : '{' imm0_255 '}'
3157 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3158 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3159 SMLoc S = Parser.getTok().getLoc();
3161 // If this isn't a '{', this isn't a coprocessor immediate operand.
3162 if (Parser.getTok().isNot(AsmToken::LCurly))
3163 return MatchOperand_NoMatch;
3164 Parser.Lex(); // Eat the '{'
3167 SMLoc Loc = Parser.getTok().getLoc();
3168 if (getParser().parseExpression(Expr)) {
3169 Error(Loc, "illegal expression");
3170 return MatchOperand_ParseFail;
3172 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3173 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3174 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3175 return MatchOperand_ParseFail;
3177 int Val = CE->getValue();
3179 // Check for and consume the closing '}'
3180 if (Parser.getTok().isNot(AsmToken::RCurly))
3181 return MatchOperand_ParseFail;
3182 SMLoc E = Parser.getTok().getEndLoc();
3183 Parser.Lex(); // Eat the '}'
3185 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3186 return MatchOperand_Success;
3189 // For register list parsing, we need to map from raw GPR register numbering
3190 // to the enumeration values. The enumeration values aren't sorted by
3191 // register number due to our using "sp", "lr" and "pc" as canonical names.
3192 static unsigned getNextRegister(unsigned Reg) {
3193 // If this is a GPR, we need to do it manually, otherwise we can rely
3194 // on the sort ordering of the enumeration since the other reg-classes
3196 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3199 default: llvm_unreachable("Invalid GPR number!");
3200 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3201 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3202 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3203 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3204 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3205 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3206 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3207 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3211 // Return the low-subreg of a given Q register.
3212 static unsigned getDRegFromQReg(unsigned QReg) {
3214 default: llvm_unreachable("expected a Q register!");
3215 case ARM::Q0: return ARM::D0;
3216 case ARM::Q1: return ARM::D2;
3217 case ARM::Q2: return ARM::D4;
3218 case ARM::Q3: return ARM::D6;
3219 case ARM::Q4: return ARM::D8;
3220 case ARM::Q5: return ARM::D10;
3221 case ARM::Q6: return ARM::D12;
3222 case ARM::Q7: return ARM::D14;
3223 case ARM::Q8: return ARM::D16;
3224 case ARM::Q9: return ARM::D18;
3225 case ARM::Q10: return ARM::D20;
3226 case ARM::Q11: return ARM::D22;
3227 case ARM::Q12: return ARM::D24;
3228 case ARM::Q13: return ARM::D26;
3229 case ARM::Q14: return ARM::D28;
3230 case ARM::Q15: return ARM::D30;
3234 /// Parse a register list.
3236 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3237 assert(Parser.getTok().is(AsmToken::LCurly) &&
3238 "Token is not a Left Curly Brace");
3239 SMLoc S = Parser.getTok().getLoc();
3240 Parser.Lex(); // Eat '{' token.
3241 SMLoc RegLoc = Parser.getTok().getLoc();
3243 // Check the first register in the list to see what register class
3244 // this is a list of.
3245 int Reg = tryParseRegister();
3247 return Error(RegLoc, "register expected");
3249 // The reglist instructions have at most 16 registers, so reserve
3250 // space for that many.
3252 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3254 // Allow Q regs and just interpret them as the two D sub-registers.
3255 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3256 Reg = getDRegFromQReg(Reg);
3257 EReg = MRI->getEncodingValue(Reg);
3258 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3261 const MCRegisterClass *RC;
3262 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3263 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3264 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3265 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3266 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3267 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3269 return Error(RegLoc, "invalid register in register list");
3271 // Store the register.
3272 EReg = MRI->getEncodingValue(Reg);
3273 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3275 // This starts immediately after the first register token in the list,
3276 // so we can see either a comma or a minus (range separator) as a legal
3278 while (Parser.getTok().is(AsmToken::Comma) ||
3279 Parser.getTok().is(AsmToken::Minus)) {
3280 if (Parser.getTok().is(AsmToken::Minus)) {
3281 Parser.Lex(); // Eat the minus.
3282 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3283 int EndReg = tryParseRegister();
3285 return Error(AfterMinusLoc, "register expected");
3286 // Allow Q regs and just interpret them as the two D sub-registers.
3287 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3288 EndReg = getDRegFromQReg(EndReg) + 1;
3289 // If the register is the same as the start reg, there's nothing
3293 // The register must be in the same register class as the first.
3294 if (!RC->contains(EndReg))
3295 return Error(AfterMinusLoc, "invalid register in register list");
3296 // Ranges must go from low to high.
3297 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3298 return Error(AfterMinusLoc, "bad range in register list");
3300 // Add all the registers in the range to the register list.
3301 while (Reg != EndReg) {
3302 Reg = getNextRegister(Reg);
3303 EReg = MRI->getEncodingValue(Reg);
3304 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3308 Parser.Lex(); // Eat the comma.
3309 RegLoc = Parser.getTok().getLoc();
3311 const AsmToken RegTok = Parser.getTok();
3312 Reg = tryParseRegister();
3314 return Error(RegLoc, "register expected");
3315 // Allow Q regs and just interpret them as the two D sub-registers.
3316 bool isQReg = false;
3317 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3318 Reg = getDRegFromQReg(Reg);
3321 // The register must be in the same register class as the first.
3322 if (!RC->contains(Reg))
3323 return Error(RegLoc, "invalid register in register list");
3324 // List must be monotonically increasing.
3325 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3326 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3327 Warning(RegLoc, "register list not in ascending order");
3329 return Error(RegLoc, "register list not in ascending order");
3331 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3332 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3333 ") in register list");
3336 // VFP register lists must also be contiguous.
3337 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3339 return Error(RegLoc, "non-contiguous register range");
3340 EReg = MRI->getEncodingValue(Reg);
3341 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3343 EReg = MRI->getEncodingValue(++Reg);
3344 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3348 if (Parser.getTok().isNot(AsmToken::RCurly))
3349 return Error(Parser.getTok().getLoc(), "'}' expected");
3350 SMLoc E = Parser.getTok().getEndLoc();
3351 Parser.Lex(); // Eat '}' token.
3353 // Push the register list operand.
3354 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3356 // The ARM system instruction variants for LDM/STM have a '^' token here.
3357 if (Parser.getTok().is(AsmToken::Caret)) {
3358 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3359 Parser.Lex(); // Eat '^' token.
3365 // Helper function to parse the lane index for vector lists.
3366 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3367 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3368 Index = 0; // Always return a defined index value.
3369 if (Parser.getTok().is(AsmToken::LBrac)) {
3370 Parser.Lex(); // Eat the '['.
3371 if (Parser.getTok().is(AsmToken::RBrac)) {
3372 // "Dn[]" is the 'all lanes' syntax.
3373 LaneKind = AllLanes;
3374 EndLoc = Parser.getTok().getEndLoc();
3375 Parser.Lex(); // Eat the ']'.
3376 return MatchOperand_Success;
3379 // There's an optional '#' token here. Normally there wouldn't be, but
3380 // inline assemble puts one in, and it's friendly to accept that.
3381 if (Parser.getTok().is(AsmToken::Hash))
3382 Parser.Lex(); // Eat '#' or '$'.
3384 const MCExpr *LaneIndex;
3385 SMLoc Loc = Parser.getTok().getLoc();
3386 if (getParser().parseExpression(LaneIndex)) {
3387 Error(Loc, "illegal expression");
3388 return MatchOperand_ParseFail;
3390 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3392 Error(Loc, "lane index must be empty or an integer");
3393 return MatchOperand_ParseFail;
3395 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3396 Error(Parser.getTok().getLoc(), "']' expected");
3397 return MatchOperand_ParseFail;
3399 EndLoc = Parser.getTok().getEndLoc();
3400 Parser.Lex(); // Eat the ']'.
3401 int64_t Val = CE->getValue();
3403 // FIXME: Make this range check context sensitive for .8, .16, .32.
3404 if (Val < 0 || Val > 7) {
3405 Error(Parser.getTok().getLoc(), "lane index out of range");
3406 return MatchOperand_ParseFail;
3409 LaneKind = IndexedLane;
3410 return MatchOperand_Success;
3413 return MatchOperand_Success;
3416 // parse a vector register list
3417 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3418 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3419 VectorLaneTy LaneKind;
3421 SMLoc S = Parser.getTok().getLoc();
3422 // As an extension (to match gas), support a plain D register or Q register
3423 // (without encosing curly braces) as a single or double entry list,
3425 if (Parser.getTok().is(AsmToken::Identifier)) {
3426 SMLoc E = Parser.getTok().getEndLoc();
3427 int Reg = tryParseRegister();
3429 return MatchOperand_NoMatch;
3430 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3431 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3432 if (Res != MatchOperand_Success)
3436 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3439 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3443 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3448 return MatchOperand_Success;
3450 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3451 Reg = getDRegFromQReg(Reg);
3452 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3453 if (Res != MatchOperand_Success)
3457 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3458 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3459 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3462 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3463 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3464 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3468 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3473 return MatchOperand_Success;
3475 Error(S, "vector register expected");
3476 return MatchOperand_ParseFail;
3479 if (Parser.getTok().isNot(AsmToken::LCurly))
3480 return MatchOperand_NoMatch;
3482 Parser.Lex(); // Eat '{' token.
3483 SMLoc RegLoc = Parser.getTok().getLoc();
3485 int Reg = tryParseRegister();
3487 Error(RegLoc, "register expected");
3488 return MatchOperand_ParseFail;
3492 unsigned FirstReg = Reg;
3493 // The list is of D registers, but we also allow Q regs and just interpret
3494 // them as the two D sub-registers.
3495 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3496 FirstReg = Reg = getDRegFromQReg(Reg);
3497 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3498 // it's ambiguous with four-register single spaced.
3504 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3505 return MatchOperand_ParseFail;
3507 while (Parser.getTok().is(AsmToken::Comma) ||
3508 Parser.getTok().is(AsmToken::Minus)) {
3509 if (Parser.getTok().is(AsmToken::Minus)) {
3511 Spacing = 1; // Register range implies a single spaced list.
3512 else if (Spacing == 2) {
3513 Error(Parser.getTok().getLoc(),
3514 "sequential registers in double spaced list");
3515 return MatchOperand_ParseFail;
3517 Parser.Lex(); // Eat the minus.
3518 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3519 int EndReg = tryParseRegister();
3521 Error(AfterMinusLoc, "register expected");
3522 return MatchOperand_ParseFail;
3524 // Allow Q regs and just interpret them as the two D sub-registers.
3525 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3526 EndReg = getDRegFromQReg(EndReg) + 1;
3527 // If the register is the same as the start reg, there's nothing
3531 // The register must be in the same register class as the first.
3532 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3533 Error(AfterMinusLoc, "invalid register in register list");
3534 return MatchOperand_ParseFail;
3536 // Ranges must go from low to high.
3538 Error(AfterMinusLoc, "bad range in register list");
3539 return MatchOperand_ParseFail;
3541 // Parse the lane specifier if present.
3542 VectorLaneTy NextLaneKind;
3543 unsigned NextLaneIndex;
3544 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3545 MatchOperand_Success)
3546 return MatchOperand_ParseFail;
3547 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3548 Error(AfterMinusLoc, "mismatched lane index in register list");
3549 return MatchOperand_ParseFail;
3552 // Add all the registers in the range to the register list.
3553 Count += EndReg - Reg;
3557 Parser.Lex(); // Eat the comma.
3558 RegLoc = Parser.getTok().getLoc();
3560 Reg = tryParseRegister();
3562 Error(RegLoc, "register expected");
3563 return MatchOperand_ParseFail;
3565 // vector register lists must be contiguous.
3566 // It's OK to use the enumeration values directly here rather, as the
3567 // VFP register classes have the enum sorted properly.
3569 // The list is of D registers, but we also allow Q regs and just interpret
3570 // them as the two D sub-registers.
3571 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3573 Spacing = 1; // Register range implies a single spaced list.
3574 else if (Spacing == 2) {
3576 "invalid register in double-spaced list (must be 'D' register')");
3577 return MatchOperand_ParseFail;
3579 Reg = getDRegFromQReg(Reg);
3580 if (Reg != OldReg + 1) {
3581 Error(RegLoc, "non-contiguous register range");
3582 return MatchOperand_ParseFail;
3586 // Parse the lane specifier if present.
3587 VectorLaneTy NextLaneKind;
3588 unsigned NextLaneIndex;
3589 SMLoc LaneLoc = Parser.getTok().getLoc();
3590 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3591 MatchOperand_Success)
3592 return MatchOperand_ParseFail;
3593 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3594 Error(LaneLoc, "mismatched lane index in register list");
3595 return MatchOperand_ParseFail;
3599 // Normal D register.
3600 // Figure out the register spacing (single or double) of the list if
3601 // we don't know it already.
3603 Spacing = 1 + (Reg == OldReg + 2);
3605 // Just check that it's contiguous and keep going.
3606 if (Reg != OldReg + Spacing) {
3607 Error(RegLoc, "non-contiguous register range");
3608 return MatchOperand_ParseFail;
3611 // Parse the lane specifier if present.
3612 VectorLaneTy NextLaneKind;
3613 unsigned NextLaneIndex;
3614 SMLoc EndLoc = Parser.getTok().getLoc();
3615 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3616 return MatchOperand_ParseFail;
3617 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3618 Error(EndLoc, "mismatched lane index in register list");
3619 return MatchOperand_ParseFail;
3623 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3624 Error(Parser.getTok().getLoc(), "'}' expected");
3625 return MatchOperand_ParseFail;
3627 E = Parser.getTok().getEndLoc();
3628 Parser.Lex(); // Eat '}' token.
3632 // Two-register operands have been converted to the
3633 // composite register classes.
3635 const MCRegisterClass *RC = (Spacing == 1) ?
3636 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3637 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3638 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3641 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3642 (Spacing == 2), S, E));
3645 // Two-register operands have been converted to the
3646 // composite register classes.
3648 const MCRegisterClass *RC = (Spacing == 1) ?
3649 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3650 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3651 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3653 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3658 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3664 return MatchOperand_Success;
3667 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3668 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3669 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3670 SMLoc S = Parser.getTok().getLoc();
3671 const AsmToken &Tok = Parser.getTok();
3674 if (Tok.is(AsmToken::Identifier)) {
3675 StringRef OptStr = Tok.getString();
3677 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3678 .Case("sy", ARM_MB::SY)
3679 .Case("st", ARM_MB::ST)
3680 .Case("ld", ARM_MB::LD)
3681 .Case("sh", ARM_MB::ISH)
3682 .Case("ish", ARM_MB::ISH)
3683 .Case("shst", ARM_MB::ISHST)
3684 .Case("ishst", ARM_MB::ISHST)
3685 .Case("ishld", ARM_MB::ISHLD)
3686 .Case("nsh", ARM_MB::NSH)
3687 .Case("un", ARM_MB::NSH)
3688 .Case("nshst", ARM_MB::NSHST)
3689 .Case("nshld", ARM_MB::NSHLD)
3690 .Case("unst", ARM_MB::NSHST)
3691 .Case("osh", ARM_MB::OSH)
3692 .Case("oshst", ARM_MB::OSHST)
3693 .Case("oshld", ARM_MB::OSHLD)
3696 // ishld, oshld, nshld and ld are only available from ARMv8.
3697 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3698 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3702 return MatchOperand_NoMatch;
3704 Parser.Lex(); // Eat identifier token.
3705 } else if (Tok.is(AsmToken::Hash) ||
3706 Tok.is(AsmToken::Dollar) ||
3707 Tok.is(AsmToken::Integer)) {
3708 if (Parser.getTok().isNot(AsmToken::Integer))
3709 Parser.Lex(); // Eat '#' or '$'.
3710 SMLoc Loc = Parser.getTok().getLoc();
3712 const MCExpr *MemBarrierID;
3713 if (getParser().parseExpression(MemBarrierID)) {
3714 Error(Loc, "illegal expression");
3715 return MatchOperand_ParseFail;
3718 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3720 Error(Loc, "constant expression expected");
3721 return MatchOperand_ParseFail;
3724 int Val = CE->getValue();
3726 Error(Loc, "immediate value out of range");
3727 return MatchOperand_ParseFail;
3730 Opt = ARM_MB::RESERVED_0 + Val;
3732 return MatchOperand_ParseFail;
3734 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3735 return MatchOperand_Success;
3738 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3739 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3740 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3741 SMLoc S = Parser.getTok().getLoc();
3742 const AsmToken &Tok = Parser.getTok();
3745 if (Tok.is(AsmToken::Identifier)) {
3746 StringRef OptStr = Tok.getString();
3748 if (OptStr.equals_lower("sy"))
3751 return MatchOperand_NoMatch;
3753 Parser.Lex(); // Eat identifier token.
3754 } else if (Tok.is(AsmToken::Hash) ||
3755 Tok.is(AsmToken::Dollar) ||
3756 Tok.is(AsmToken::Integer)) {
3757 if (Parser.getTok().isNot(AsmToken::Integer))
3758 Parser.Lex(); // Eat '#' or '$'.
3759 SMLoc Loc = Parser.getTok().getLoc();
3761 const MCExpr *ISBarrierID;
3762 if (getParser().parseExpression(ISBarrierID)) {
3763 Error(Loc, "illegal expression");
3764 return MatchOperand_ParseFail;
3767 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3769 Error(Loc, "constant expression expected");
3770 return MatchOperand_ParseFail;
3773 int Val = CE->getValue();
3775 Error(Loc, "immediate value out of range");
3776 return MatchOperand_ParseFail;
3779 Opt = ARM_ISB::RESERVED_0 + Val;
3781 return MatchOperand_ParseFail;
3783 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3784 (ARM_ISB::InstSyncBOpt)Opt, S));
3785 return MatchOperand_Success;
3789 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3790 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3791 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3792 SMLoc S = Parser.getTok().getLoc();
3793 const AsmToken &Tok = Parser.getTok();
3794 if (!Tok.is(AsmToken::Identifier))
3795 return MatchOperand_NoMatch;
3796 StringRef IFlagsStr = Tok.getString();
3798 // An iflags string of "none" is interpreted to mean that none of the AIF
3799 // bits are set. Not a terribly useful instruction, but a valid encoding.
3800 unsigned IFlags = 0;
3801 if (IFlagsStr != "none") {
3802 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3803 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3804 .Case("a", ARM_PROC::A)
3805 .Case("i", ARM_PROC::I)
3806 .Case("f", ARM_PROC::F)
3809 // If some specific iflag is already set, it means that some letter is
3810 // present more than once, this is not acceptable.
3811 if (Flag == ~0U || (IFlags & Flag))
3812 return MatchOperand_NoMatch;
3818 Parser.Lex(); // Eat identifier token.
3819 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3820 return MatchOperand_Success;
3823 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3824 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3825 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3826 SMLoc S = Parser.getTok().getLoc();
3827 const AsmToken &Tok = Parser.getTok();
3828 if (!Tok.is(AsmToken::Identifier))
3829 return MatchOperand_NoMatch;
3830 StringRef Mask = Tok.getString();
3833 // See ARMv6-M 10.1.1
3834 std::string Name = Mask.lower();
3835 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3836 // Note: in the documentation:
3837 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3838 // for MSR APSR_nzcvq.
3839 // but we do make it an alias here. This is so to get the "mask encoding"
3840 // bits correct on MSR APSR writes.
3842 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3843 // should really only be allowed when writing a special register. Note
3844 // they get dropped in the MRS instruction reading a special register as
3845 // the SYSm field is only 8 bits.
3847 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3848 // includes the DSP extension but that is not checked.
3849 .Case("apsr", 0x800)
3850 .Case("apsr_nzcvq", 0x800)
3851 .Case("apsr_g", 0x400)
3852 .Case("apsr_nzcvqg", 0xc00)
3853 .Case("iapsr", 0x801)
3854 .Case("iapsr_nzcvq", 0x801)
3855 .Case("iapsr_g", 0x401)
3856 .Case("iapsr_nzcvqg", 0xc01)
3857 .Case("eapsr", 0x802)
3858 .Case("eapsr_nzcvq", 0x802)
3859 .Case("eapsr_g", 0x402)
3860 .Case("eapsr_nzcvqg", 0xc02)
3861 .Case("xpsr", 0x803)
3862 .Case("xpsr_nzcvq", 0x803)
3863 .Case("xpsr_g", 0x403)
3864 .Case("xpsr_nzcvqg", 0xc03)
3865 .Case("ipsr", 0x805)
3866 .Case("epsr", 0x806)
3867 .Case("iepsr", 0x807)
3870 .Case("primask", 0x810)
3871 .Case("basepri", 0x811)
3872 .Case("basepri_max", 0x812)
3873 .Case("faultmask", 0x813)
3874 .Case("control", 0x814)
3877 if (FlagsVal == ~0U)
3878 return MatchOperand_NoMatch;
3880 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3881 // basepri, basepri_max and faultmask only valid for V7m.
3882 return MatchOperand_NoMatch;
3884 Parser.Lex(); // Eat identifier token.
3885 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3886 return MatchOperand_Success;
3889 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3890 size_t Start = 0, Next = Mask.find('_');
3891 StringRef Flags = "";
3892 std::string SpecReg = Mask.slice(Start, Next).lower();
3893 if (Next != StringRef::npos)
3894 Flags = Mask.slice(Next+1, Mask.size());
3896 // FlagsVal contains the complete mask:
3898 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3899 unsigned FlagsVal = 0;
3901 if (SpecReg == "apsr") {
3902 FlagsVal = StringSwitch<unsigned>(Flags)
3903 .Case("nzcvq", 0x8) // same as CPSR_f
3904 .Case("g", 0x4) // same as CPSR_s
3905 .Case("nzcvqg", 0xc) // same as CPSR_fs
3908 if (FlagsVal == ~0U) {
3910 return MatchOperand_NoMatch;
3912 FlagsVal = 8; // No flag
3914 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3915 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3916 if (Flags == "all" || Flags == "")
3918 for (int i = 0, e = Flags.size(); i != e; ++i) {
3919 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3926 // If some specific flag is already set, it means that some letter is
3927 // present more than once, this is not acceptable.
3928 if (FlagsVal == ~0U || (FlagsVal & Flag))
3929 return MatchOperand_NoMatch;
3932 } else // No match for special register.
3933 return MatchOperand_NoMatch;
3935 // Special register without flags is NOT equivalent to "fc" flags.
3936 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3937 // two lines would enable gas compatibility at the expense of breaking
3943 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3944 if (SpecReg == "spsr")
3947 Parser.Lex(); // Eat identifier token.
3948 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3949 return MatchOperand_Success;
3952 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3953 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3954 int Low, int High) {
3955 const AsmToken &Tok = Parser.getTok();
3956 if (Tok.isNot(AsmToken::Identifier)) {
3957 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3958 return MatchOperand_ParseFail;
3960 StringRef ShiftName = Tok.getString();
3961 std::string LowerOp = Op.lower();
3962 std::string UpperOp = Op.upper();
3963 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3964 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3965 return MatchOperand_ParseFail;
3967 Parser.Lex(); // Eat shift type token.
3969 // There must be a '#' and a shift amount.
3970 if (Parser.getTok().isNot(AsmToken::Hash) &&
3971 Parser.getTok().isNot(AsmToken::Dollar)) {
3972 Error(Parser.getTok().getLoc(), "'#' expected");
3973 return MatchOperand_ParseFail;
3975 Parser.Lex(); // Eat hash token.
3977 const MCExpr *ShiftAmount;
3978 SMLoc Loc = Parser.getTok().getLoc();
3980 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3981 Error(Loc, "illegal expression");
3982 return MatchOperand_ParseFail;
3984 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3986 Error(Loc, "constant expression expected");
3987 return MatchOperand_ParseFail;
3989 int Val = CE->getValue();
3990 if (Val < Low || Val > High) {
3991 Error(Loc, "immediate value out of range");
3992 return MatchOperand_ParseFail;
3995 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3997 return MatchOperand_Success;
4000 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4001 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4002 const AsmToken &Tok = Parser.getTok();
4003 SMLoc S = Tok.getLoc();
4004 if (Tok.isNot(AsmToken::Identifier)) {
4005 Error(S, "'be' or 'le' operand expected");
4006 return MatchOperand_ParseFail;
4008 int Val = StringSwitch<int>(Tok.getString().lower())
4012 Parser.Lex(); // Eat the token.
4015 Error(S, "'be' or 'le' operand expected");
4016 return MatchOperand_ParseFail;
4018 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4020 S, Tok.getEndLoc()));
4021 return MatchOperand_Success;
4024 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4025 /// instructions. Legal values are:
4026 /// lsl #n 'n' in [0,31]
4027 /// asr #n 'n' in [1,32]
4028 /// n == 32 encoded as n == 0.
4029 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4030 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4031 const AsmToken &Tok = Parser.getTok();
4032 SMLoc S = Tok.getLoc();
4033 if (Tok.isNot(AsmToken::Identifier)) {
4034 Error(S, "shift operator 'asr' or 'lsl' expected");
4035 return MatchOperand_ParseFail;
4037 StringRef ShiftName = Tok.getString();
4039 if (ShiftName == "lsl" || ShiftName == "LSL")
4041 else if (ShiftName == "asr" || ShiftName == "ASR")
4044 Error(S, "shift operator 'asr' or 'lsl' expected");
4045 return MatchOperand_ParseFail;
4047 Parser.Lex(); // Eat the operator.
4049 // A '#' and a shift amount.
4050 if (Parser.getTok().isNot(AsmToken::Hash) &&
4051 Parser.getTok().isNot(AsmToken::Dollar)) {
4052 Error(Parser.getTok().getLoc(), "'#' expected");
4053 return MatchOperand_ParseFail;
4055 Parser.Lex(); // Eat hash token.
4056 SMLoc ExLoc = Parser.getTok().getLoc();
4058 const MCExpr *ShiftAmount;
4060 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4061 Error(ExLoc, "malformed shift expression");
4062 return MatchOperand_ParseFail;
4064 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4066 Error(ExLoc, "shift amount must be an immediate");
4067 return MatchOperand_ParseFail;
4070 int64_t Val = CE->getValue();
4072 // Shift amount must be in [1,32]
4073 if (Val < 1 || Val > 32) {
4074 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4075 return MatchOperand_ParseFail;
4077 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4078 if (isThumb() && Val == 32) {
4079 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4080 return MatchOperand_ParseFail;
4082 if (Val == 32) Val = 0;
4084 // Shift amount must be in [1,32]
4085 if (Val < 0 || Val > 31) {
4086 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4087 return MatchOperand_ParseFail;
4091 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4093 return MatchOperand_Success;
4096 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4097 /// of instructions. Legal values are:
4098 /// ror #n 'n' in {0, 8, 16, 24}
4099 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4100 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4101 const AsmToken &Tok = Parser.getTok();
4102 SMLoc S = Tok.getLoc();
4103 if (Tok.isNot(AsmToken::Identifier))
4104 return MatchOperand_NoMatch;
4105 StringRef ShiftName = Tok.getString();
4106 if (ShiftName != "ror" && ShiftName != "ROR")
4107 return MatchOperand_NoMatch;
4108 Parser.Lex(); // Eat the operator.
4110 // A '#' and a rotate amount.
4111 if (Parser.getTok().isNot(AsmToken::Hash) &&
4112 Parser.getTok().isNot(AsmToken::Dollar)) {
4113 Error(Parser.getTok().getLoc(), "'#' expected");
4114 return MatchOperand_ParseFail;
4116 Parser.Lex(); // Eat hash token.
4117 SMLoc ExLoc = Parser.getTok().getLoc();
4119 const MCExpr *ShiftAmount;
4121 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4122 Error(ExLoc, "malformed rotate expression");
4123 return MatchOperand_ParseFail;
4125 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4127 Error(ExLoc, "rotate amount must be an immediate");
4128 return MatchOperand_ParseFail;
4131 int64_t Val = CE->getValue();
4132 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4133 // normally, zero is represented in asm by omitting the rotate operand
4135 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4136 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4137 return MatchOperand_ParseFail;
4140 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4142 return MatchOperand_Success;
4145 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4146 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4147 SMLoc S = Parser.getTok().getLoc();
4148 // The bitfield descriptor is really two operands, the LSB and the width.
4149 if (Parser.getTok().isNot(AsmToken::Hash) &&
4150 Parser.getTok().isNot(AsmToken::Dollar)) {
4151 Error(Parser.getTok().getLoc(), "'#' expected");
4152 return MatchOperand_ParseFail;
4154 Parser.Lex(); // Eat hash token.
4156 const MCExpr *LSBExpr;
4157 SMLoc E = Parser.getTok().getLoc();
4158 if (getParser().parseExpression(LSBExpr)) {
4159 Error(E, "malformed immediate expression");
4160 return MatchOperand_ParseFail;
4162 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4164 Error(E, "'lsb' operand must be an immediate");
4165 return MatchOperand_ParseFail;
4168 int64_t LSB = CE->getValue();
4169 // The LSB must be in the range [0,31]
4170 if (LSB < 0 || LSB > 31) {
4171 Error(E, "'lsb' operand must be in the range [0,31]");
4172 return MatchOperand_ParseFail;
4174 E = Parser.getTok().getLoc();
4176 // Expect another immediate operand.
4177 if (Parser.getTok().isNot(AsmToken::Comma)) {
4178 Error(Parser.getTok().getLoc(), "too few operands");
4179 return MatchOperand_ParseFail;
4181 Parser.Lex(); // Eat hash token.
4182 if (Parser.getTok().isNot(AsmToken::Hash) &&
4183 Parser.getTok().isNot(AsmToken::Dollar)) {
4184 Error(Parser.getTok().getLoc(), "'#' expected");
4185 return MatchOperand_ParseFail;
4187 Parser.Lex(); // Eat hash token.
4189 const MCExpr *WidthExpr;
4191 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4192 Error(E, "malformed immediate expression");
4193 return MatchOperand_ParseFail;
4195 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4197 Error(E, "'width' operand must be an immediate");
4198 return MatchOperand_ParseFail;
4201 int64_t Width = CE->getValue();
4202 // The LSB must be in the range [1,32-lsb]
4203 if (Width < 1 || Width > 32 - LSB) {
4204 Error(E, "'width' operand must be in the range [1,32-lsb]");
4205 return MatchOperand_ParseFail;
4208 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4210 return MatchOperand_Success;
4213 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4214 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4215 // Check for a post-index addressing register operand. Specifically:
4216 // postidx_reg := '+' register {, shift}
4217 // | '-' register {, shift}
4218 // | register {, shift}
4220 // This method must return MatchOperand_NoMatch without consuming any tokens
4221 // in the case where there is no match, as other alternatives take other
4223 AsmToken Tok = Parser.getTok();
4224 SMLoc S = Tok.getLoc();
4225 bool haveEaten = false;
4227 if (Tok.is(AsmToken::Plus)) {
4228 Parser.Lex(); // Eat the '+' token.
4230 } else if (Tok.is(AsmToken::Minus)) {
4231 Parser.Lex(); // Eat the '-' token.
4236 SMLoc E = Parser.getTok().getEndLoc();
4237 int Reg = tryParseRegister();
4240 return MatchOperand_NoMatch;
4241 Error(Parser.getTok().getLoc(), "register expected");
4242 return MatchOperand_ParseFail;
4245 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4246 unsigned ShiftImm = 0;
4247 if (Parser.getTok().is(AsmToken::Comma)) {
4248 Parser.Lex(); // Eat the ','.
4249 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4250 return MatchOperand_ParseFail;
4252 // FIXME: Only approximates end...may include intervening whitespace.
4253 E = Parser.getTok().getLoc();
4256 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4259 return MatchOperand_Success;
4262 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4263 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4264 // Check for a post-index addressing register operand. Specifically:
4265 // am3offset := '+' register
4272 // This method must return MatchOperand_NoMatch without consuming any tokens
4273 // in the case where there is no match, as other alternatives take other
4275 AsmToken Tok = Parser.getTok();
4276 SMLoc S = Tok.getLoc();
4278 // Do immediates first, as we always parse those if we have a '#'.
4279 if (Parser.getTok().is(AsmToken::Hash) ||
4280 Parser.getTok().is(AsmToken::Dollar)) {
4281 Parser.Lex(); // Eat '#' or '$'.
4282 // Explicitly look for a '-', as we need to encode negative zero
4284 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4285 const MCExpr *Offset;
4287 if (getParser().parseExpression(Offset, E))
4288 return MatchOperand_ParseFail;
4289 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4291 Error(S, "constant expression expected");
4292 return MatchOperand_ParseFail;
4294 // Negative zero is encoded as the flag value INT32_MIN.
4295 int32_t Val = CE->getValue();
4296 if (isNegative && Val == 0)
4300 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4302 return MatchOperand_Success;
4306 bool haveEaten = false;
4308 if (Tok.is(AsmToken::Plus)) {
4309 Parser.Lex(); // Eat the '+' token.
4311 } else if (Tok.is(AsmToken::Minus)) {
4312 Parser.Lex(); // Eat the '-' token.
4317 Tok = Parser.getTok();
4318 int Reg = tryParseRegister();
4321 return MatchOperand_NoMatch;
4322 Error(Tok.getLoc(), "register expected");
4323 return MatchOperand_ParseFail;
4326 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4327 0, S, Tok.getEndLoc()));
4329 return MatchOperand_Success;
4332 /// Convert parsed operands to MCInst. Needed here because this instruction
4333 /// only has two register operands, but multiplication is commutative so
4334 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4336 cvtThumbMultiply(MCInst &Inst,
4337 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4338 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4339 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4340 // If we have a three-operand form, make sure to set Rn to be the operand
4341 // that isn't the same as Rd.
4343 if (Operands.size() == 6 &&
4344 ((ARMOperand*)Operands[4])->getReg() ==
4345 ((ARMOperand*)Operands[3])->getReg())
4347 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4348 Inst.addOperand(Inst.getOperand(0));
4349 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4353 cvtThumbBranches(MCInst &Inst,
4354 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4355 int CondOp = -1, ImmOp = -1;
4356 switch(Inst.getOpcode()) {
4358 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4361 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4363 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4365 // first decide whether or not the branch should be conditional
4366 // by looking at it's location relative to an IT block
4368 // inside an IT block we cannot have any conditional branches. any
4369 // such instructions needs to be converted to unconditional form
4370 switch(Inst.getOpcode()) {
4371 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4372 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4375 // outside IT blocks we can only have unconditional branches with AL
4376 // condition code or conditional branches with non-AL condition code
4377 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4378 switch(Inst.getOpcode()) {
4381 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4385 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4390 // now decide on encoding size based on branch target range
4391 switch(Inst.getOpcode()) {
4392 // classify tB as either t2B or t1B based on range of immediate operand
4394 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4395 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4396 Inst.setOpcode(ARM::t2B);
4399 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4401 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4402 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4403 Inst.setOpcode(ARM::t2Bcc);
4407 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4408 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4411 /// Parse an ARM memory expression, return false if successful else return true
4412 /// or an error. The first token must be a '[' when called.
4414 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4416 assert(Parser.getTok().is(AsmToken::LBrac) &&
4417 "Token is not a Left Bracket");
4418 S = Parser.getTok().getLoc();
4419 Parser.Lex(); // Eat left bracket token.
4421 const AsmToken &BaseRegTok = Parser.getTok();
4422 int BaseRegNum = tryParseRegister();
4423 if (BaseRegNum == -1)
4424 return Error(BaseRegTok.getLoc(), "register expected");
4426 // The next token must either be a comma, a colon or a closing bracket.
4427 const AsmToken &Tok = Parser.getTok();
4428 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4429 !Tok.is(AsmToken::RBrac))
4430 return Error(Tok.getLoc(), "malformed memory operand");
4432 if (Tok.is(AsmToken::RBrac)) {
4433 E = Tok.getEndLoc();
4434 Parser.Lex(); // Eat right bracket token.
4436 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4437 0, 0, false, S, E));
4439 // If there's a pre-indexing writeback marker, '!', just add it as a token
4440 // operand. It's rather odd, but syntactically valid.
4441 if (Parser.getTok().is(AsmToken::Exclaim)) {
4442 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4443 Parser.Lex(); // Eat the '!'.
4449 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4450 "Lost colon or comma in memory operand?!");
4451 if (Tok.is(AsmToken::Comma)) {
4452 Parser.Lex(); // Eat the comma.
4455 // If we have a ':', it's an alignment specifier.
4456 if (Parser.getTok().is(AsmToken::Colon)) {
4457 Parser.Lex(); // Eat the ':'.
4458 E = Parser.getTok().getLoc();
4459 SMLoc AlignmentLoc = Tok.getLoc();
4462 if (getParser().parseExpression(Expr))
4465 // The expression has to be a constant. Memory references with relocations
4466 // don't come through here, as they use the <label> forms of the relevant
4468 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4470 return Error (E, "constant expression expected");
4473 switch (CE->getValue()) {
4476 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4477 case 16: Align = 2; break;
4478 case 32: Align = 4; break;
4479 case 64: Align = 8; break;
4480 case 128: Align = 16; break;
4481 case 256: Align = 32; break;
4484 // Now we should have the closing ']'
4485 if (Parser.getTok().isNot(AsmToken::RBrac))
4486 return Error(Parser.getTok().getLoc(), "']' expected");
4487 E = Parser.getTok().getEndLoc();
4488 Parser.Lex(); // Eat right bracket token.
4490 // Don't worry about range checking the value here. That's handled by
4491 // the is*() predicates.
4492 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4493 ARM_AM::no_shift, 0, Align,
4494 false, S, E, AlignmentLoc));
4496 // If there's a pre-indexing writeback marker, '!', just add it as a token
4498 if (Parser.getTok().is(AsmToken::Exclaim)) {
4499 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4500 Parser.Lex(); // Eat the '!'.
4506 // If we have a '#', it's an immediate offset, else assume it's a register
4507 // offset. Be friendly and also accept a plain integer (without a leading
4508 // hash) for gas compatibility.
4509 if (Parser.getTok().is(AsmToken::Hash) ||
4510 Parser.getTok().is(AsmToken::Dollar) ||
4511 Parser.getTok().is(AsmToken::Integer)) {
4512 if (Parser.getTok().isNot(AsmToken::Integer))
4513 Parser.Lex(); // Eat '#' or '$'.
4514 E = Parser.getTok().getLoc();
4516 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4517 const MCExpr *Offset;
4518 if (getParser().parseExpression(Offset))
4521 // The expression has to be a constant. Memory references with relocations
4522 // don't come through here, as they use the <label> forms of the relevant
4524 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4526 return Error (E, "constant expression expected");
4528 // If the constant was #-0, represent it as INT32_MIN.
4529 int32_t Val = CE->getValue();
4530 if (isNegative && Val == 0)
4531 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4533 // Now we should have the closing ']'
4534 if (Parser.getTok().isNot(AsmToken::RBrac))
4535 return Error(Parser.getTok().getLoc(), "']' expected");
4536 E = Parser.getTok().getEndLoc();
4537 Parser.Lex(); // Eat right bracket token.
4539 // Don't worry about range checking the value here. That's handled by
4540 // the is*() predicates.
4541 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4542 ARM_AM::no_shift, 0, 0,
4545 // If there's a pre-indexing writeback marker, '!', just add it as a token
4547 if (Parser.getTok().is(AsmToken::Exclaim)) {
4548 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4549 Parser.Lex(); // Eat the '!'.
4555 // The register offset is optionally preceded by a '+' or '-'
4556 bool isNegative = false;
4557 if (Parser.getTok().is(AsmToken::Minus)) {
4559 Parser.Lex(); // Eat the '-'.
4560 } else if (Parser.getTok().is(AsmToken::Plus)) {
4562 Parser.Lex(); // Eat the '+'.
4565 E = Parser.getTok().getLoc();
4566 int OffsetRegNum = tryParseRegister();
4567 if (OffsetRegNum == -1)
4568 return Error(E, "register expected");
4570 // If there's a shift operator, handle it.
4571 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4572 unsigned ShiftImm = 0;
4573 if (Parser.getTok().is(AsmToken::Comma)) {
4574 Parser.Lex(); // Eat the ','.
4575 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4579 // Now we should have the closing ']'
4580 if (Parser.getTok().isNot(AsmToken::RBrac))
4581 return Error(Parser.getTok().getLoc(), "']' expected");
4582 E = Parser.getTok().getEndLoc();
4583 Parser.Lex(); // Eat right bracket token.
4585 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4586 ShiftType, ShiftImm, 0, isNegative,
4589 // If there's a pre-indexing writeback marker, '!', just add it as a token
4591 if (Parser.getTok().is(AsmToken::Exclaim)) {
4592 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4593 Parser.Lex(); // Eat the '!'.
4599 /// parseMemRegOffsetShift - one of these two:
4600 /// ( lsl | lsr | asr | ror ) , # shift_amount
4602 /// return true if it parses a shift otherwise it returns false.
4603 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4605 SMLoc Loc = Parser.getTok().getLoc();
4606 const AsmToken &Tok = Parser.getTok();
4607 if (Tok.isNot(AsmToken::Identifier))
4609 StringRef ShiftName = Tok.getString();
4610 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4611 ShiftName == "asl" || ShiftName == "ASL")
4613 else if (ShiftName == "lsr" || ShiftName == "LSR")
4615 else if (ShiftName == "asr" || ShiftName == "ASR")
4617 else if (ShiftName == "ror" || ShiftName == "ROR")
4619 else if (ShiftName == "rrx" || ShiftName == "RRX")
4622 return Error(Loc, "illegal shift operator");
4623 Parser.Lex(); // Eat shift type token.
4625 // rrx stands alone.
4627 if (St != ARM_AM::rrx) {
4628 Loc = Parser.getTok().getLoc();
4629 // A '#' and a shift amount.
4630 const AsmToken &HashTok = Parser.getTok();
4631 if (HashTok.isNot(AsmToken::Hash) &&
4632 HashTok.isNot(AsmToken::Dollar))
4633 return Error(HashTok.getLoc(), "'#' expected");
4634 Parser.Lex(); // Eat hash token.
4637 if (getParser().parseExpression(Expr))
4639 // Range check the immediate.
4640 // lsl, ror: 0 <= imm <= 31
4641 // lsr, asr: 0 <= imm <= 32
4642 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4644 return Error(Loc, "shift amount must be an immediate");
4645 int64_t Imm = CE->getValue();
4647 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4648 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4649 return Error(Loc, "immediate shift value out of range");
4650 // If <ShiftTy> #0, turn it into a no_shift.
4653 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4662 /// parseFPImm - A floating point immediate expression operand.
4663 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4664 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4665 // Anything that can accept a floating point constant as an operand
4666 // needs to go through here, as the regular parseExpression is
4669 // This routine still creates a generic Immediate operand, containing
4670 // a bitcast of the 64-bit floating point value. The various operands
4671 // that accept floats can check whether the value is valid for them
4672 // via the standard is*() predicates.
4674 SMLoc S = Parser.getTok().getLoc();
4676 if (Parser.getTok().isNot(AsmToken::Hash) &&
4677 Parser.getTok().isNot(AsmToken::Dollar))
4678 return MatchOperand_NoMatch;
4680 // Disambiguate the VMOV forms that can accept an FP immediate.
4681 // vmov.f32 <sreg>, #imm
4682 // vmov.f64 <dreg>, #imm
4683 // vmov.f32 <dreg>, #imm @ vector f32x2
4684 // vmov.f32 <qreg>, #imm @ vector f32x4
4686 // There are also the NEON VMOV instructions which expect an
4687 // integer constant. Make sure we don't try to parse an FPImm
4689 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4690 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4691 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" ||
4692 TyOp->getToken() == ".f64");
4693 ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]);
4694 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" ||
4695 Mnemonic->getToken() == "fconsts");
4696 if (!(isVmovf || isFconst))
4697 return MatchOperand_NoMatch;
4699 Parser.Lex(); // Eat '#' or '$'.
4701 // Handle negation, as that still comes through as a separate token.
4702 bool isNegative = false;
4703 if (Parser.getTok().is(AsmToken::Minus)) {
4707 const AsmToken &Tok = Parser.getTok();
4708 SMLoc Loc = Tok.getLoc();
4709 if (Tok.is(AsmToken::Real) && isVmovf) {
4710 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4711 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4712 // If we had a '-' in front, toggle the sign bit.
4713 IntVal ^= (uint64_t)isNegative << 31;
4714 Parser.Lex(); // Eat the token.
4715 Operands.push_back(ARMOperand::CreateImm(
4716 MCConstantExpr::Create(IntVal, getContext()),
4717 S, Parser.getTok().getLoc()));
4718 return MatchOperand_Success;
4720 // Also handle plain integers. Instructions which allow floating point
4721 // immediates also allow a raw encoded 8-bit value.
4722 if (Tok.is(AsmToken::Integer) && isFconst) {
4723 int64_t Val = Tok.getIntVal();
4724 Parser.Lex(); // Eat the token.
4725 if (Val > 255 || Val < 0) {
4726 Error(Loc, "encoded floating point value out of range");
4727 return MatchOperand_ParseFail;
4729 float RealVal = ARM_AM::getFPImmFloat(Val);
4730 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4732 Operands.push_back(ARMOperand::CreateImm(
4733 MCConstantExpr::Create(Val, getContext()), S,
4734 Parser.getTok().getLoc()));
4735 return MatchOperand_Success;
4738 Error(Loc, "invalid floating point immediate");
4739 return MatchOperand_ParseFail;
4742 /// Parse a arm instruction operand. For now this parses the operand regardless
4743 /// of the mnemonic.
4744 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4745 StringRef Mnemonic) {
4748 // Check if the current operand has a custom associated parser, if so, try to
4749 // custom parse the operand, or fallback to the general approach.
4750 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4751 if (ResTy == MatchOperand_Success)
4753 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4754 // there was a match, but an error occurred, in which case, just return that
4755 // the operand parsing failed.
4756 if (ResTy == MatchOperand_ParseFail)
4759 switch (getLexer().getKind()) {
4761 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4763 case AsmToken::Identifier: {
4764 // If we've seen a branch mnemonic, the next operand must be a label. This
4765 // is true even if the label is a register name. So "br r1" means branch to
4767 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4769 if (!tryParseRegisterWithWriteBack(Operands))
4771 int Res = tryParseShiftRegister(Operands);
4772 if (Res == 0) // success
4774 else if (Res == -1) // irrecoverable error
4776 // If this is VMRS, check for the apsr_nzcv operand.
4777 if (Mnemonic == "vmrs" &&
4778 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4779 S = Parser.getTok().getLoc();
4781 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4786 // Fall though for the Identifier case that is not a register or a
4789 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4790 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4791 case AsmToken::String: // quoted label names.
4792 case AsmToken::Dot: { // . as a branch target
4793 // This was not a register so parse other operands that start with an
4794 // identifier (like labels) as expressions and create them as immediates.
4795 const MCExpr *IdVal;
4796 S = Parser.getTok().getLoc();
4797 if (getParser().parseExpression(IdVal))
4799 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4800 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4803 case AsmToken::LBrac:
4804 return parseMemory(Operands);
4805 case AsmToken::LCurly:
4806 return parseRegisterList(Operands);
4807 case AsmToken::Dollar:
4808 case AsmToken::Hash: {
4809 // #42 -> immediate.
4810 S = Parser.getTok().getLoc();
4813 if (Parser.getTok().isNot(AsmToken::Colon)) {
4814 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4815 const MCExpr *ImmVal;
4816 if (getParser().parseExpression(ImmVal))
4818 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4820 int32_t Val = CE->getValue();
4821 if (isNegative && Val == 0)
4822 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4824 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4825 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4827 // There can be a trailing '!' on operands that we want as a separate
4828 // '!' Token operand. Handle that here. For example, the compatibility
4829 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4830 if (Parser.getTok().is(AsmToken::Exclaim)) {
4831 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4832 Parser.getTok().getLoc()));
4833 Parser.Lex(); // Eat exclaim token
4837 // w/ a ':' after the '#', it's just like a plain ':'.
4840 case AsmToken::Colon: {
4841 // ":lower16:" and ":upper16:" expression prefixes
4842 // FIXME: Check it's an expression prefix,
4843 // e.g. (FOO - :lower16:BAR) isn't legal.
4844 ARMMCExpr::VariantKind RefKind;
4845 if (parsePrefix(RefKind))
4848 const MCExpr *SubExprVal;
4849 if (getParser().parseExpression(SubExprVal))
4852 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4854 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4855 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4858 case AsmToken::Equal: {
4859 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4860 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4862 Parser.Lex(); // Eat '='
4863 const MCExpr *SubExprVal;
4864 if (getParser().parseExpression(SubExprVal))
4866 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4868 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
4869 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4875 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4876 // :lower16: and :upper16:.
4877 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4878 RefKind = ARMMCExpr::VK_ARM_None;
4880 // consume an optional '#' (GNU compatibility)
4881 if (getLexer().is(AsmToken::Hash))
4884 // :lower16: and :upper16: modifiers
4885 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4886 Parser.Lex(); // Eat ':'
4888 if (getLexer().isNot(AsmToken::Identifier)) {
4889 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4893 StringRef IDVal = Parser.getTok().getIdentifier();
4894 if (IDVal == "lower16") {
4895 RefKind = ARMMCExpr::VK_ARM_LO16;
4896 } else if (IDVal == "upper16") {
4897 RefKind = ARMMCExpr::VK_ARM_HI16;
4899 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4904 if (getLexer().isNot(AsmToken::Colon)) {
4905 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4908 Parser.Lex(); // Eat the last ':'
4912 /// \brief Given a mnemonic, split out possible predication code and carry
4913 /// setting letters to form a canonical mnemonic and flags.
4915 // FIXME: Would be nice to autogen this.
4916 // FIXME: This is a bit of a maze of special cases.
4917 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4918 unsigned &PredicationCode,
4920 unsigned &ProcessorIMod,
4921 StringRef &ITMask) {
4922 PredicationCode = ARMCC::AL;
4923 CarrySetting = false;
4926 // Ignore some mnemonics we know aren't predicated forms.
4928 // FIXME: Would be nice to autogen this.
4929 if ((Mnemonic == "movs" && isThumb()) ||
4930 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4931 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4932 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4933 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4934 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4935 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4936 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4937 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4938 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4939 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4940 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4941 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4944 // First, split out any predication code. Ignore mnemonics we know aren't
4945 // predicated but do have a carry-set and so weren't caught above.
4946 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4947 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4948 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4949 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4950 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4951 .Case("eq", ARMCC::EQ)
4952 .Case("ne", ARMCC::NE)
4953 .Case("hs", ARMCC::HS)
4954 .Case("cs", ARMCC::HS)
4955 .Case("lo", ARMCC::LO)
4956 .Case("cc", ARMCC::LO)
4957 .Case("mi", ARMCC::MI)
4958 .Case("pl", ARMCC::PL)
4959 .Case("vs", ARMCC::VS)
4960 .Case("vc", ARMCC::VC)
4961 .Case("hi", ARMCC::HI)
4962 .Case("ls", ARMCC::LS)
4963 .Case("ge", ARMCC::GE)
4964 .Case("lt", ARMCC::LT)
4965 .Case("gt", ARMCC::GT)
4966 .Case("le", ARMCC::LE)
4967 .Case("al", ARMCC::AL)
4970 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4971 PredicationCode = CC;
4975 // Next, determine if we have a carry setting bit. We explicitly ignore all
4976 // the instructions we know end in 's'.
4977 if (Mnemonic.endswith("s") &&
4978 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4979 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4980 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4981 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4982 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4983 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4984 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4985 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4986 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
4987 (Mnemonic == "movs" && isThumb()))) {
4988 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4989 CarrySetting = true;
4992 // The "cps" instruction can have a interrupt mode operand which is glued into
4993 // the mnemonic. Check if this is the case, split it and parse the imod op
4994 if (Mnemonic.startswith("cps")) {
4995 // Split out any imod code.
4997 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4998 .Case("ie", ARM_PROC::IE)
4999 .Case("id", ARM_PROC::ID)
5002 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5003 ProcessorIMod = IMod;
5007 // The "it" instruction has the condition mask on the end of the mnemonic.
5008 if (Mnemonic.startswith("it")) {
5009 ITMask = Mnemonic.slice(2, Mnemonic.size());
5010 Mnemonic = Mnemonic.slice(0, 2);
5016 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5017 /// inclusion of carry set or predication code operands.
5019 // FIXME: It would be nice to autogen this.
5021 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5022 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
5023 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5024 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5025 Mnemonic == "add" || Mnemonic == "adc" ||
5026 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
5027 Mnemonic == "orr" || Mnemonic == "mvn" ||
5028 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
5029 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5030 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5031 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5032 Mnemonic == "mla" || Mnemonic == "smlal" ||
5033 Mnemonic == "umlal" || Mnemonic == "umull"))) {
5034 CanAcceptCarrySet = true;
5036 CanAcceptCarrySet = false;
5038 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5039 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5040 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
5041 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
5042 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5043 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5044 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5045 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
5046 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5047 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5048 // These mnemonics are never predicable
5049 CanAcceptPredicationCode = false;
5050 } else if (!isThumb()) {
5051 // Some instructions are only predicable in Thumb mode
5052 CanAcceptPredicationCode
5053 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5054 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5055 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5056 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5057 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5058 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5059 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5060 } else if (isThumbOne()) {
5062 CanAcceptPredicationCode = Mnemonic != "movs";
5064 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5066 CanAcceptPredicationCode = true;
5069 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5070 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5071 // FIXME: This is all horribly hacky. We really need a better way to deal
5072 // with optional operands like this in the matcher table.
5074 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5075 // another does not. Specifically, the MOVW instruction does not. So we
5076 // special case it here and remove the defaulted (non-setting) cc_out
5077 // operand if that's the instruction we're trying to match.
5079 // We do this as post-processing of the explicit operands rather than just
5080 // conditionally adding the cc_out in the first place because we need
5081 // to check the type of the parsed immediate operand.
5082 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5083 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
5084 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
5085 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5088 // Register-register 'add' for thumb does not have a cc_out operand
5089 // when there are only two register operands.
5090 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5091 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5092 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5093 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5095 // Register-register 'add' for thumb does not have a cc_out operand
5096 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5097 // have to check the immediate range here since Thumb2 has a variant
5098 // that can handle a different range and has a cc_out operand.
5099 if (((isThumb() && Mnemonic == "add") ||
5100 (isThumbTwo() && Mnemonic == "sub")) &&
5101 Operands.size() == 6 &&
5102 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5103 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5104 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
5105 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5106 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
5107 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
5109 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5110 // imm0_4095 variant. That's the least-preferred variant when
5111 // selecting via the generic "add" mnemonic, so to know that we
5112 // should remove the cc_out operand, we have to explicitly check that
5113 // it's not one of the other variants. Ugh.
5114 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5115 Operands.size() == 6 &&
5116 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5117 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5118 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5119 // Nest conditions rather than one big 'if' statement for readability.
5121 // If both registers are low, we're in an IT block, and the immediate is
5122 // in range, we should use encoding T1 instead, which has a cc_out.
5124 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5125 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5126 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5128 // Check against T3. If the second register is the PC, this is an
5129 // alternate form of ADR, which uses encoding T4, so check for that too.
5130 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5131 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5134 // Otherwise, we use encoding T4, which does not have a cc_out
5139 // The thumb2 multiply instruction doesn't have a CCOut register, so
5140 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5141 // use the 16-bit encoding or not.
5142 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5143 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5144 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5145 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5146 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5147 // If the registers aren't low regs, the destination reg isn't the
5148 // same as one of the source regs, or the cc_out operand is zero
5149 // outside of an IT block, we have to use the 32-bit encoding, so
5150 // remove the cc_out operand.
5151 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5152 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5153 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5155 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5156 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5157 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5158 static_cast<ARMOperand*>(Operands[4])->getReg())))
5161 // Also check the 'mul' syntax variant that doesn't specify an explicit
5162 // destination register.
5163 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5164 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5165 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5166 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5167 // If the registers aren't low regs or the cc_out operand is zero
5168 // outside of an IT block, we have to use the 32-bit encoding, so
5169 // remove the cc_out operand.
5170 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5171 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5177 // Register-register 'add/sub' for thumb does not have a cc_out operand
5178 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5179 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5180 // right, this will result in better diagnostics (which operand is off)
5182 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5183 (Operands.size() == 5 || Operands.size() == 6) &&
5184 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5185 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5186 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5187 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5188 (Operands.size() == 6 &&
5189 static_cast<ARMOperand*>(Operands[5])->isImm())))
5195 bool ARMAsmParser::shouldOmitPredicateOperand(
5196 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5197 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5198 unsigned RegIdx = 3;
5199 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5200 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5201 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5202 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5205 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5206 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5207 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5208 ARMMCRegisterClasses[ARM::QPRRegClassID]
5209 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5215 static bool isDataTypeToken(StringRef Tok) {
5216 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5217 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5218 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5219 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5220 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5221 Tok == ".f" || Tok == ".d";
5224 // FIXME: This bit should probably be handled via an explicit match class
5225 // in the .td files that matches the suffix instead of having it be
5226 // a literal string token the way it is now.
5227 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5228 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5230 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5231 unsigned VariantID);
5233 static bool RequiresVFPRegListValidation(StringRef Inst,
5234 bool &AcceptSinglePrecisionOnly,
5235 bool &AcceptDoublePrecisionOnly) {
5236 if (Inst.size() < 7)
5239 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5240 StringRef AddressingMode = Inst.substr(4, 2);
5241 if (AddressingMode == "ia" || AddressingMode == "db" ||
5242 AddressingMode == "ea" || AddressingMode == "fd") {
5243 AcceptSinglePrecisionOnly = Inst[6] == 's';
5244 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5252 /// Parse an arm instruction mnemonic followed by its operands.
5253 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5255 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5256 // FIXME: Can this be done via tablegen in some fashion?
5257 bool RequireVFPRegisterListCheck;
5258 bool AcceptSinglePrecisionOnly;
5259 bool AcceptDoublePrecisionOnly;
5260 RequireVFPRegisterListCheck =
5261 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5262 AcceptDoublePrecisionOnly);
5264 // Apply mnemonic aliases before doing anything else, as the destination
5265 // mnemonic may include suffices and we want to handle them normally.
5266 // The generic tblgen'erated code does this later, at the start of
5267 // MatchInstructionImpl(), but that's too late for aliases that include
5268 // any sort of suffix.
5269 unsigned AvailableFeatures = getAvailableFeatures();
5270 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5271 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5273 // First check for the ARM-specific .req directive.
5274 if (Parser.getTok().is(AsmToken::Identifier) &&
5275 Parser.getTok().getIdentifier() == ".req") {
5276 parseDirectiveReq(Name, NameLoc);
5277 // We always return 'error' for this, as we're done with this
5278 // statement and don't need to match the 'instruction."
5282 // Create the leading tokens for the mnemonic, split by '.' characters.
5283 size_t Start = 0, Next = Name.find('.');
5284 StringRef Mnemonic = Name.slice(Start, Next);
5286 // Split out the predication code and carry setting flag from the mnemonic.
5287 unsigned PredicationCode;
5288 unsigned ProcessorIMod;
5291 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5292 ProcessorIMod, ITMask);
5294 // In Thumb1, only the branch (B) instruction can be predicated.
5295 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5296 Parser.eatToEndOfStatement();
5297 return Error(NameLoc, "conditional execution not supported in Thumb1");
5300 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5302 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5303 // is the mask as it will be for the IT encoding if the conditional
5304 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5305 // where the conditional bit0 is zero, the instruction post-processing
5306 // will adjust the mask accordingly.
5307 if (Mnemonic == "it") {
5308 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5309 if (ITMask.size() > 3) {
5310 Parser.eatToEndOfStatement();
5311 return Error(Loc, "too many conditions on IT instruction");
5314 for (unsigned i = ITMask.size(); i != 0; --i) {
5315 char pos = ITMask[i - 1];
5316 if (pos != 't' && pos != 'e') {
5317 Parser.eatToEndOfStatement();
5318 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5321 if (ITMask[i - 1] == 't')
5324 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5327 // FIXME: This is all a pretty gross hack. We should automatically handle
5328 // optional operands like this via tblgen.
5330 // Next, add the CCOut and ConditionCode operands, if needed.
5332 // For mnemonics which can ever incorporate a carry setting bit or predication
5333 // code, our matching model involves us always generating CCOut and
5334 // ConditionCode operands to match the mnemonic "as written" and then we let
5335 // the matcher deal with finding the right instruction or generating an
5336 // appropriate error.
5337 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5338 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5340 // If we had a carry-set on an instruction that can't do that, issue an
5342 if (!CanAcceptCarrySet && CarrySetting) {
5343 Parser.eatToEndOfStatement();
5344 return Error(NameLoc, "instruction '" + Mnemonic +
5345 "' can not set flags, but 's' suffix specified");
5347 // If we had a predication code on an instruction that can't do that, issue an
5349 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5350 Parser.eatToEndOfStatement();
5351 return Error(NameLoc, "instruction '" + Mnemonic +
5352 "' is not predicable, but condition code specified");
5355 // Add the carry setting operand, if necessary.
5356 if (CanAcceptCarrySet) {
5357 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5358 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5362 // Add the predication code operand, if necessary.
5363 if (CanAcceptPredicationCode) {
5364 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5366 Operands.push_back(ARMOperand::CreateCondCode(
5367 ARMCC::CondCodes(PredicationCode), Loc));
5370 // Add the processor imod operand, if necessary.
5371 if (ProcessorIMod) {
5372 Operands.push_back(ARMOperand::CreateImm(
5373 MCConstantExpr::Create(ProcessorIMod, getContext()),
5377 // Add the remaining tokens in the mnemonic.
5378 while (Next != StringRef::npos) {
5380 Next = Name.find('.', Start + 1);
5381 StringRef ExtraToken = Name.slice(Start, Next);
5383 // Some NEON instructions have an optional datatype suffix that is
5384 // completely ignored. Check for that.
5385 if (isDataTypeToken(ExtraToken) &&
5386 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5389 // For for ARM mode generate an error if the .n qualifier is used.
5390 if (ExtraToken == ".n" && !isThumb()) {
5391 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5392 Parser.eatToEndOfStatement();
5393 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5397 // The .n qualifier is always discarded as that is what the tables
5398 // and matcher expect. In ARM mode the .w qualifier has no effect,
5399 // so discard it to avoid errors that can be caused by the matcher.
5400 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5401 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5402 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5406 // Read the remaining operands.
5407 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5408 // Read the first operand.
5409 if (parseOperand(Operands, Mnemonic)) {
5410 Parser.eatToEndOfStatement();
5414 while (getLexer().is(AsmToken::Comma)) {
5415 Parser.Lex(); // Eat the comma.
5417 // Parse and remember the operand.
5418 if (parseOperand(Operands, Mnemonic)) {
5419 Parser.eatToEndOfStatement();
5425 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5426 SMLoc Loc = getLexer().getLoc();
5427 Parser.eatToEndOfStatement();
5428 return Error(Loc, "unexpected token in argument list");
5431 Parser.Lex(); // Consume the EndOfStatement
5433 if (RequireVFPRegisterListCheck) {
5434 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5435 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5436 return Error(Op->getStartLoc(),
5437 "VFP/Neon single precision register expected");
5438 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5439 return Error(Op->getStartLoc(),
5440 "VFP/Neon double precision register expected");
5443 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5444 // do and don't have a cc_out optional-def operand. With some spot-checks
5445 // of the operand list, we can figure out which variant we're trying to
5446 // parse and adjust accordingly before actually matching. We shouldn't ever
5447 // try to remove a cc_out operand that was explicitly set on the the
5448 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5449 // table driven matcher doesn't fit well with the ARM instruction set.
5450 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5451 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5452 Operands.erase(Operands.begin() + 1);
5456 // Some instructions have the same mnemonic, but don't always
5457 // have a predicate. Distinguish them here and delete the
5458 // predicate if needed.
5459 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5460 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5461 Operands.erase(Operands.begin() + 1);
5465 // ARM mode 'blx' need special handling, as the register operand version
5466 // is predicable, but the label operand version is not. So, we can't rely
5467 // on the Mnemonic based checking to correctly figure out when to put
5468 // a k_CondCode operand in the list. If we're trying to match the label
5469 // version, remove the k_CondCode operand here.
5470 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5471 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5472 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5473 Operands.erase(Operands.begin() + 1);
5477 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5478 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5479 // a single GPRPair reg operand is used in the .td file to replace the two
5480 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5481 // expressed as a GPRPair, so we have to manually merge them.
5482 // FIXME: We would really like to be able to tablegen'erate this.
5483 if (!isThumb() && Operands.size() > 4 &&
5484 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5485 Mnemonic == "stlexd")) {
5486 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5487 unsigned Idx = isLoad ? 2 : 3;
5488 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5489 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5491 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5492 // Adjust only if Op1 and Op2 are GPRs.
5493 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5494 MRC.contains(Op2->getReg())) {
5495 unsigned Reg1 = Op1->getReg();
5496 unsigned Reg2 = Op2->getReg();
5497 unsigned Rt = MRI->getEncodingValue(Reg1);
5498 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5500 // Rt2 must be Rt + 1 and Rt must be even.
5501 if (Rt + 1 != Rt2 || (Rt & 1)) {
5502 Error(Op2->getStartLoc(), isLoad ?
5503 "destination operands must be sequential" :
5504 "source operands must be sequential");
5507 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5508 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5509 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5510 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5511 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5517 // GNU Assembler extension (compatibility)
5518 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5519 ARMOperand *Op2 = static_cast<ARMOperand *>(Operands[2]);
5520 ARMOperand *Op3 = static_cast<ARMOperand *>(Operands[3]);
5522 assert(Op2->isReg() && "expected register argument");
5524 unsigned SuperReg = MRI->getMatchingSuperReg(
5525 Op2->getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5527 assert(SuperReg && "expected register pair");
5529 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5531 Operands.insert(Operands.begin() + 3,
5532 ARMOperand::CreateReg(PairedReg,
5538 // FIXME: As said above, this is all a pretty gross hack. This instruction
5539 // does not fit with other "subs" and tblgen.
5540 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5541 // so the Mnemonic is the original name "subs" and delete the predicate
5542 // operand so it will match the table entry.
5543 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5544 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5545 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5546 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5547 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5548 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5549 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5550 Operands.erase(Operands.begin());
5552 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5554 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5555 Operands.erase(Operands.begin() + 1);
5561 // Validate context-sensitive operand constraints.
5563 // return 'true' if register list contains non-low GPR registers,
5564 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5565 // 'containsReg' to true.
5566 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5567 unsigned HiReg, bool &containsReg) {
5568 containsReg = false;
5569 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5570 unsigned OpReg = Inst.getOperand(i).getReg();
5573 // Anything other than a low register isn't legal here.
5574 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5580 // Check if the specified regisgter is in the register list of the inst,
5581 // starting at the indicated operand number.
5582 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5583 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5584 unsigned OpReg = Inst.getOperand(i).getReg();
5591 // Return true if instruction has the interesting property of being
5592 // allowed in IT blocks, but not being predicable.
5593 static bool instIsBreakpoint(const MCInst &Inst) {
5594 return Inst.getOpcode() == ARM::tBKPT ||
5595 Inst.getOpcode() == ARM::BKPT ||
5596 Inst.getOpcode() == ARM::tHLT ||
5597 Inst.getOpcode() == ARM::HLT;
5601 // FIXME: We would really like to be able to tablegen'erate this.
5603 validateInstruction(MCInst &Inst,
5604 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5605 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5606 SMLoc Loc = Operands[0]->getStartLoc();
5608 // Check the IT block state first.
5609 // NOTE: BKPT and HLT instructions have the interesting property of being
5610 // allowed in IT blocks, but not being predicable. They just always execute.
5611 if (inITBlock() && !instIsBreakpoint(Inst)) {
5613 if (ITState.FirstCond)
5614 ITState.FirstCond = false;
5616 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5617 // The instruction must be predicable.
5618 if (!MCID.isPredicable())
5619 return Error(Loc, "instructions in IT block must be predicable");
5620 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5621 unsigned ITCond = Bit ? ITState.Cond :
5622 ARMCC::getOppositeCondition(ITState.Cond);
5623 if (Cond != ITCond) {
5624 // Find the condition code Operand to get its SMLoc information.
5626 for (unsigned I = 1; I < Operands.size(); ++I)
5627 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5628 CondLoc = Operands[I]->getStartLoc();
5629 return Error(CondLoc, "incorrect condition in IT block; got '" +
5630 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5631 "', but expected '" +
5632 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5634 // Check for non-'al' condition codes outside of the IT block.
5635 } else if (isThumbTwo() && MCID.isPredicable() &&
5636 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5637 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5638 Inst.getOpcode() != ARM::t2Bcc)
5639 return Error(Loc, "predicated instructions must be in IT block");
5641 const unsigned Opcode = Inst.getOpcode();
5645 case ARM::LDRD_POST: {
5646 const unsigned RtReg = Inst.getOperand(0).getReg();
5649 if (RtReg == ARM::LR)
5650 return Error(Operands[3]->getStartLoc(),
5653 const unsigned Rt = MRI->getEncodingValue(RtReg);
5654 // Rt must be even-numbered.
5656 return Error(Operands[3]->getStartLoc(),
5657 "Rt must be even-numbered");
5659 // Rt2 must be Rt + 1.
5660 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5662 return Error(Operands[3]->getStartLoc(),
5663 "destination operands must be sequential");
5665 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5666 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5667 // For addressing modes with writeback, the base register needs to be
5668 // different from the destination registers.
5669 if (Rn == Rt || Rn == Rt2)
5670 return Error(Operands[3]->getStartLoc(),
5671 "base register needs to be different from destination "
5678 case ARM::t2LDRD_PRE:
5679 case ARM::t2LDRD_POST: {
5680 // Rt2 must be different from Rt.
5681 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5682 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5684 return Error(Operands[3]->getStartLoc(),
5685 "destination operands can't be identical");
5689 // Rt2 must be Rt + 1.
5690 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5691 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5693 return Error(Operands[3]->getStartLoc(),
5694 "source operands must be sequential");
5698 case ARM::STRD_POST: {
5699 // Rt2 must be Rt + 1.
5700 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5701 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5703 return Error(Operands[3]->getStartLoc(),
5704 "source operands must be sequential");
5709 // Width must be in range [1, 32-lsb].
5710 unsigned LSB = Inst.getOperand(2).getImm();
5711 unsigned Widthm1 = Inst.getOperand(3).getImm();
5712 if (Widthm1 >= 32 - LSB)
5713 return Error(Operands[5]->getStartLoc(),
5714 "bitfield width must be in range [1,32-lsb]");
5717 // Notionally handles ARM::tLDMIA_UPD too.
5719 // If we're parsing Thumb2, the .w variant is available and handles
5720 // most cases that are normally illegal for a Thumb1 LDM instruction.
5721 // We'll make the transformation in processInstruction() if necessary.
5723 // Thumb LDM instructions are writeback iff the base register is not
5724 // in the register list.
5725 unsigned Rn = Inst.getOperand(0).getReg();
5726 bool HasWritebackToken =
5727 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5728 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5729 bool ListContainsBase;
5730 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5731 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5732 "registers must be in range r0-r7");
5733 // If we should have writeback, then there should be a '!' token.
5734 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5735 return Error(Operands[2]->getStartLoc(),
5736 "writeback operator '!' expected");
5737 // If we should not have writeback, there must not be a '!'. This is
5738 // true even for the 32-bit wide encodings.
5739 if (ListContainsBase && HasWritebackToken)
5740 return Error(Operands[3]->getStartLoc(),
5741 "writeback operator '!' not allowed when base register "
5742 "in register list");
5746 case ARM::LDMIA_UPD:
5747 case ARM::LDMDB_UPD:
5748 case ARM::LDMIB_UPD:
5749 case ARM::LDMDA_UPD:
5750 // ARM variants loading and updating the same register are only officially
5751 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5755 case ARM::t2LDMIA_UPD:
5756 case ARM::t2LDMDB_UPD:
5757 case ARM::t2STMIA_UPD:
5758 case ARM::t2STMDB_UPD: {
5759 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5760 return Error(Operands.back()->getStartLoc(),
5761 "writeback register not allowed in register list");
5764 case ARM::sysLDMIA_UPD:
5765 case ARM::sysLDMDA_UPD:
5766 case ARM::sysLDMDB_UPD:
5767 case ARM::sysLDMIB_UPD:
5768 if (!listContainsReg(Inst, 3, ARM::PC))
5769 return Error(Operands[4]->getStartLoc(),
5770 "writeback register only allowed on system LDM "
5771 "if PC in register-list");
5773 case ARM::sysSTMIA_UPD:
5774 case ARM::sysSTMDA_UPD:
5775 case ARM::sysSTMDB_UPD:
5776 case ARM::sysSTMIB_UPD:
5777 return Error(Operands[2]->getStartLoc(),
5778 "system STM cannot have writeback register");
5780 // The second source operand must be the same register as the destination
5783 // In this case, we must directly check the parsed operands because the
5784 // cvtThumbMultiply() function is written in such a way that it guarantees
5785 // this first statement is always true for the new Inst. Essentially, the
5786 // destination is unconditionally copied into the second source operand
5787 // without checking to see if it matches what we actually parsed.
5788 if (Operands.size() == 6 &&
5789 (((ARMOperand*)Operands[3])->getReg() !=
5790 ((ARMOperand*)Operands[5])->getReg()) &&
5791 (((ARMOperand*)Operands[3])->getReg() !=
5792 ((ARMOperand*)Operands[4])->getReg())) {
5793 return Error(Operands[3]->getStartLoc(),
5794 "destination register must match source register");
5798 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5799 // so only issue a diagnostic for thumb1. The instructions will be
5800 // switched to the t2 encodings in processInstruction() if necessary.
5802 bool ListContainsBase;
5803 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5805 return Error(Operands[2]->getStartLoc(),
5806 "registers must be in range r0-r7 or pc");
5810 bool ListContainsBase;
5811 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5813 return Error(Operands[2]->getStartLoc(),
5814 "registers must be in range r0-r7 or lr");
5817 case ARM::tSTMIA_UPD: {
5818 bool ListContainsBase, InvalidLowList;
5819 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5820 0, ListContainsBase);
5821 if (InvalidLowList && !isThumbTwo())
5822 return Error(Operands[4]->getStartLoc(),
5823 "registers must be in range r0-r7");
5825 // This would be converted to a 32-bit stm, but that's not valid if the
5826 // writeback register is in the list.
5827 if (InvalidLowList && ListContainsBase)
5828 return Error(Operands[4]->getStartLoc(),
5829 "writeback operator '!' not allowed when base register "
5830 "in register list");
5833 case ARM::tADDrSP: {
5834 // If the non-SP source operand and the destination operand are not the
5835 // same, we need thumb2 (for the wide encoding), or we have an error.
5836 if (!isThumbTwo() &&
5837 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5838 return Error(Operands[4]->getStartLoc(),
5839 "source register must be the same as destination");
5843 // Final range checking for Thumb unconditional branch instructions.
5845 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5846 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5849 int op = (Operands[2]->isImm()) ? 2 : 3;
5850 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5851 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5854 // Final range checking for Thumb conditional branch instructions.
5856 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5857 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5860 int Op = (Operands[2]->isImm()) ? 2 : 3;
5861 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5862 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5867 case ARM::t2MOVTi16:
5869 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
5870 // especially when we turn it into a movw and the expression <symbol> does
5871 // not have a :lower16: or :upper16 as part of the expression. We don't
5872 // want the behavior of silently truncating, which can be unexpected and
5873 // lead to bugs that are difficult to find since this is an easy mistake
5875 int i = (Operands[3]->isImm()) ? 3 : 4;
5876 ARMOperand *Op = static_cast<ARMOperand*>(Operands[i]);
5877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5879 const MCExpr *E = dyn_cast<MCExpr>(Op->getImm());
5881 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
5882 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
5883 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16)) {
5884 return Error(Op->getStartLoc(),
5885 "immediate expression for mov requires :lower16: or :upper16");
5894 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5896 default: llvm_unreachable("unexpected opcode!");
5898 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5899 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5900 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5901 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5902 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5903 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5904 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5905 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5906 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5909 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5910 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5911 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5912 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5913 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5915 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5916 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5917 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5918 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5919 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5921 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5922 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5923 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5924 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5925 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5928 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5929 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5930 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5931 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5932 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5933 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5934 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5935 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5936 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5937 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5938 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5939 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5940 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5941 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5942 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5945 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5946 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5947 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5948 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5949 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5950 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5951 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5952 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5953 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5954 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5955 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5956 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5957 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5958 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5959 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5960 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5961 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5962 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5965 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5966 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5967 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5968 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5969 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5970 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5971 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5972 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5973 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5974 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5975 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5976 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5977 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5978 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5979 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5982 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5983 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5984 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5985 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5986 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5987 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5988 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5989 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5990 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5991 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5992 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5993 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5994 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5995 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5996 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5997 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5998 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5999 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6003 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6005 default: llvm_unreachable("unexpected opcode!");
6007 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6008 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6009 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6010 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6011 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6012 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6013 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6014 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6015 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6018 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6019 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6020 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6021 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6022 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6023 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6024 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6025 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6026 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6027 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6028 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6029 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6030 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6031 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6032 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6035 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6036 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6037 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6038 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6039 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6040 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6041 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6042 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6043 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6044 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6045 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6046 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6047 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6048 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6049 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6050 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6051 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6052 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6055 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6056 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6057 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6058 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6059 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6060 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6061 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6062 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6063 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6064 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6065 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6066 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6067 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6068 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6069 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6072 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6073 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6074 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6075 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6076 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6077 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6078 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6079 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6080 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6081 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6082 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6083 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6084 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6085 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6086 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6087 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6088 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6089 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6092 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6093 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6094 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6095 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6096 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6097 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6098 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6099 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6100 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6101 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6102 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6103 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6104 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6105 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6106 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6109 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6110 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6111 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6112 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6113 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6114 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6115 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6116 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6117 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6118 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6119 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6120 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6121 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6122 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6123 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6124 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6125 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6126 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6129 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6130 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6131 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6132 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6133 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6134 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6135 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6136 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6137 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6138 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6139 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6140 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6141 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6142 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6143 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6144 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6145 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6146 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6151 processInstruction(MCInst &Inst,
6152 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6153 switch (Inst.getOpcode()) {
6154 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6155 case ARM::LDRT_POST:
6156 case ARM::LDRBT_POST: {
6157 const unsigned Opcode =
6158 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6159 : ARM::LDRBT_POST_IMM;
6161 TmpInst.setOpcode(Opcode);
6162 TmpInst.addOperand(Inst.getOperand(0));
6163 TmpInst.addOperand(Inst.getOperand(1));
6164 TmpInst.addOperand(Inst.getOperand(1));
6165 TmpInst.addOperand(MCOperand::CreateReg(0));
6166 TmpInst.addOperand(MCOperand::CreateImm(0));
6167 TmpInst.addOperand(Inst.getOperand(2));
6168 TmpInst.addOperand(Inst.getOperand(3));
6172 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6173 case ARM::STRT_POST:
6174 case ARM::STRBT_POST: {
6175 const unsigned Opcode =
6176 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6177 : ARM::STRBT_POST_IMM;
6179 TmpInst.setOpcode(Opcode);
6180 TmpInst.addOperand(Inst.getOperand(1));
6181 TmpInst.addOperand(Inst.getOperand(0));
6182 TmpInst.addOperand(Inst.getOperand(1));
6183 TmpInst.addOperand(MCOperand::CreateReg(0));
6184 TmpInst.addOperand(MCOperand::CreateImm(0));
6185 TmpInst.addOperand(Inst.getOperand(2));
6186 TmpInst.addOperand(Inst.getOperand(3));
6190 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6192 if (Inst.getOperand(1).getReg() != ARM::PC ||
6193 Inst.getOperand(5).getReg() != 0)
6196 TmpInst.setOpcode(ARM::ADR);
6197 TmpInst.addOperand(Inst.getOperand(0));
6198 TmpInst.addOperand(Inst.getOperand(2));
6199 TmpInst.addOperand(Inst.getOperand(3));
6200 TmpInst.addOperand(Inst.getOperand(4));
6204 // Aliases for alternate PC+imm syntax of LDR instructions.
6205 case ARM::t2LDRpcrel:
6206 // Select the narrow version if the immediate will fit.
6207 if (Inst.getOperand(1).getImm() > 0 &&
6208 Inst.getOperand(1).getImm() <= 0xff &&
6209 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
6210 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
6211 Inst.setOpcode(ARM::tLDRpci);
6213 Inst.setOpcode(ARM::t2LDRpci);
6215 case ARM::t2LDRBpcrel:
6216 Inst.setOpcode(ARM::t2LDRBpci);
6218 case ARM::t2LDRHpcrel:
6219 Inst.setOpcode(ARM::t2LDRHpci);
6221 case ARM::t2LDRSBpcrel:
6222 Inst.setOpcode(ARM::t2LDRSBpci);
6224 case ARM::t2LDRSHpcrel:
6225 Inst.setOpcode(ARM::t2LDRSHpci);
6227 // Handle NEON VST complex aliases.
6228 case ARM::VST1LNdWB_register_Asm_8:
6229 case ARM::VST1LNdWB_register_Asm_16:
6230 case ARM::VST1LNdWB_register_Asm_32: {
6232 // Shuffle the operands around so the lane index operand is in the
6235 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6236 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6237 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6238 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6239 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6240 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6241 TmpInst.addOperand(Inst.getOperand(1)); // lane
6242 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6243 TmpInst.addOperand(Inst.getOperand(6));
6248 case ARM::VST2LNdWB_register_Asm_8:
6249 case ARM::VST2LNdWB_register_Asm_16:
6250 case ARM::VST2LNdWB_register_Asm_32:
6251 case ARM::VST2LNqWB_register_Asm_16:
6252 case ARM::VST2LNqWB_register_Asm_32: {
6254 // Shuffle the operands around so the lane index operand is in the
6257 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6258 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6259 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6260 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6261 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6262 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6263 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6265 TmpInst.addOperand(Inst.getOperand(1)); // lane
6266 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6267 TmpInst.addOperand(Inst.getOperand(6));
6272 case ARM::VST3LNdWB_register_Asm_8:
6273 case ARM::VST3LNdWB_register_Asm_16:
6274 case ARM::VST3LNdWB_register_Asm_32:
6275 case ARM::VST3LNqWB_register_Asm_16:
6276 case ARM::VST3LNqWB_register_Asm_32: {
6278 // Shuffle the operands around so the lane index operand is in the
6281 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6282 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6283 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6284 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6285 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6286 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6287 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6289 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6291 TmpInst.addOperand(Inst.getOperand(1)); // lane
6292 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6293 TmpInst.addOperand(Inst.getOperand(6));
6298 case ARM::VST4LNdWB_register_Asm_8:
6299 case ARM::VST4LNdWB_register_Asm_16:
6300 case ARM::VST4LNdWB_register_Asm_32:
6301 case ARM::VST4LNqWB_register_Asm_16:
6302 case ARM::VST4LNqWB_register_Asm_32: {
6304 // Shuffle the operands around so the lane index operand is in the
6307 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6308 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6309 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6310 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6311 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6312 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6313 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6315 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6317 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6319 TmpInst.addOperand(Inst.getOperand(1)); // lane
6320 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6321 TmpInst.addOperand(Inst.getOperand(6));
6326 case ARM::VST1LNdWB_fixed_Asm_8:
6327 case ARM::VST1LNdWB_fixed_Asm_16:
6328 case ARM::VST1LNdWB_fixed_Asm_32: {
6330 // Shuffle the operands around so the lane index operand is in the
6333 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6334 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6335 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6336 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6337 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6338 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6339 TmpInst.addOperand(Inst.getOperand(1)); // lane
6340 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6341 TmpInst.addOperand(Inst.getOperand(5));
6346 case ARM::VST2LNdWB_fixed_Asm_8:
6347 case ARM::VST2LNdWB_fixed_Asm_16:
6348 case ARM::VST2LNdWB_fixed_Asm_32:
6349 case ARM::VST2LNqWB_fixed_Asm_16:
6350 case ARM::VST2LNqWB_fixed_Asm_32: {
6352 // Shuffle the operands around so the lane index operand is in the
6355 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6356 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6357 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6358 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6359 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6360 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6361 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6363 TmpInst.addOperand(Inst.getOperand(1)); // lane
6364 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6365 TmpInst.addOperand(Inst.getOperand(5));
6370 case ARM::VST3LNdWB_fixed_Asm_8:
6371 case ARM::VST3LNdWB_fixed_Asm_16:
6372 case ARM::VST3LNdWB_fixed_Asm_32:
6373 case ARM::VST3LNqWB_fixed_Asm_16:
6374 case ARM::VST3LNqWB_fixed_Asm_32: {
6376 // Shuffle the operands around so the lane index operand is in the
6379 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6380 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6381 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6382 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6383 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6384 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6385 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6387 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6389 TmpInst.addOperand(Inst.getOperand(1)); // lane
6390 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6391 TmpInst.addOperand(Inst.getOperand(5));
6396 case ARM::VST4LNdWB_fixed_Asm_8:
6397 case ARM::VST4LNdWB_fixed_Asm_16:
6398 case ARM::VST4LNdWB_fixed_Asm_32:
6399 case ARM::VST4LNqWB_fixed_Asm_16:
6400 case ARM::VST4LNqWB_fixed_Asm_32: {
6402 // Shuffle the operands around so the lane index operand is in the
6405 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6406 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6407 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6408 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6409 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6410 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6411 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6413 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6415 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6417 TmpInst.addOperand(Inst.getOperand(1)); // lane
6418 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6419 TmpInst.addOperand(Inst.getOperand(5));
6424 case ARM::VST1LNdAsm_8:
6425 case ARM::VST1LNdAsm_16:
6426 case ARM::VST1LNdAsm_32: {
6428 // Shuffle the operands around so the lane index operand is in the
6431 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6432 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6433 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6434 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6435 TmpInst.addOperand(Inst.getOperand(1)); // lane
6436 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6437 TmpInst.addOperand(Inst.getOperand(5));
6442 case ARM::VST2LNdAsm_8:
6443 case ARM::VST2LNdAsm_16:
6444 case ARM::VST2LNdAsm_32:
6445 case ARM::VST2LNqAsm_16:
6446 case ARM::VST2LNqAsm_32: {
6448 // Shuffle the operands around so the lane index operand is in the
6451 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6452 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6453 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6454 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6455 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6457 TmpInst.addOperand(Inst.getOperand(1)); // lane
6458 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6459 TmpInst.addOperand(Inst.getOperand(5));
6464 case ARM::VST3LNdAsm_8:
6465 case ARM::VST3LNdAsm_16:
6466 case ARM::VST3LNdAsm_32:
6467 case ARM::VST3LNqAsm_16:
6468 case ARM::VST3LNqAsm_32: {
6470 // Shuffle the operands around so the lane index operand is in the
6473 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6474 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6475 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6476 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6477 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6479 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6481 TmpInst.addOperand(Inst.getOperand(1)); // lane
6482 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6483 TmpInst.addOperand(Inst.getOperand(5));
6488 case ARM::VST4LNdAsm_8:
6489 case ARM::VST4LNdAsm_16:
6490 case ARM::VST4LNdAsm_32:
6491 case ARM::VST4LNqAsm_16:
6492 case ARM::VST4LNqAsm_32: {
6494 // Shuffle the operands around so the lane index operand is in the
6497 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6498 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6499 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6500 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6501 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6503 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6505 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6507 TmpInst.addOperand(Inst.getOperand(1)); // lane
6508 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6509 TmpInst.addOperand(Inst.getOperand(5));
6514 // Handle NEON VLD complex aliases.
6515 case ARM::VLD1LNdWB_register_Asm_8:
6516 case ARM::VLD1LNdWB_register_Asm_16:
6517 case ARM::VLD1LNdWB_register_Asm_32: {
6519 // Shuffle the operands around so the lane index operand is in the
6522 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6523 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6524 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6525 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6526 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6527 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6528 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6529 TmpInst.addOperand(Inst.getOperand(1)); // lane
6530 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6531 TmpInst.addOperand(Inst.getOperand(6));
6536 case ARM::VLD2LNdWB_register_Asm_8:
6537 case ARM::VLD2LNdWB_register_Asm_16:
6538 case ARM::VLD2LNdWB_register_Asm_32:
6539 case ARM::VLD2LNqWB_register_Asm_16:
6540 case ARM::VLD2LNqWB_register_Asm_32: {
6542 // Shuffle the operands around so the lane index operand is in the
6545 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6546 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6547 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6549 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6550 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6551 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6552 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6553 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6554 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6556 TmpInst.addOperand(Inst.getOperand(1)); // lane
6557 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6558 TmpInst.addOperand(Inst.getOperand(6));
6563 case ARM::VLD3LNdWB_register_Asm_8:
6564 case ARM::VLD3LNdWB_register_Asm_16:
6565 case ARM::VLD3LNdWB_register_Asm_32:
6566 case ARM::VLD3LNqWB_register_Asm_16:
6567 case ARM::VLD3LNqWB_register_Asm_32: {
6569 // Shuffle the operands around so the lane index operand is in the
6572 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6573 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6574 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6576 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6578 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6579 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6580 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6581 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6582 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6583 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6585 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6587 TmpInst.addOperand(Inst.getOperand(1)); // lane
6588 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6589 TmpInst.addOperand(Inst.getOperand(6));
6594 case ARM::VLD4LNdWB_register_Asm_8:
6595 case ARM::VLD4LNdWB_register_Asm_16:
6596 case ARM::VLD4LNdWB_register_Asm_32:
6597 case ARM::VLD4LNqWB_register_Asm_16:
6598 case ARM::VLD4LNqWB_register_Asm_32: {
6600 // Shuffle the operands around so the lane index operand is in the
6603 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6604 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6605 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6607 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6609 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6611 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6612 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6613 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6614 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6615 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6616 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6618 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6620 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6622 TmpInst.addOperand(Inst.getOperand(1)); // lane
6623 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6624 TmpInst.addOperand(Inst.getOperand(6));
6629 case ARM::VLD1LNdWB_fixed_Asm_8:
6630 case ARM::VLD1LNdWB_fixed_Asm_16:
6631 case ARM::VLD1LNdWB_fixed_Asm_32: {
6633 // Shuffle the operands around so the lane index operand is in the
6636 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6637 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6638 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6639 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6640 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6641 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6642 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6643 TmpInst.addOperand(Inst.getOperand(1)); // lane
6644 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6645 TmpInst.addOperand(Inst.getOperand(5));
6650 case ARM::VLD2LNdWB_fixed_Asm_8:
6651 case ARM::VLD2LNdWB_fixed_Asm_16:
6652 case ARM::VLD2LNdWB_fixed_Asm_32:
6653 case ARM::VLD2LNqWB_fixed_Asm_16:
6654 case ARM::VLD2LNqWB_fixed_Asm_32: {
6656 // Shuffle the operands around so the lane index operand is in the
6659 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6660 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6661 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6663 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6664 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6665 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6666 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6667 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6668 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6670 TmpInst.addOperand(Inst.getOperand(1)); // lane
6671 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6672 TmpInst.addOperand(Inst.getOperand(5));
6677 case ARM::VLD3LNdWB_fixed_Asm_8:
6678 case ARM::VLD3LNdWB_fixed_Asm_16:
6679 case ARM::VLD3LNdWB_fixed_Asm_32:
6680 case ARM::VLD3LNqWB_fixed_Asm_16:
6681 case ARM::VLD3LNqWB_fixed_Asm_32: {
6683 // Shuffle the operands around so the lane index operand is in the
6686 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6687 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6688 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6690 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6692 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6693 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6694 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6695 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6696 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6697 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6699 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6701 TmpInst.addOperand(Inst.getOperand(1)); // lane
6702 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6703 TmpInst.addOperand(Inst.getOperand(5));
6708 case ARM::VLD4LNdWB_fixed_Asm_8:
6709 case ARM::VLD4LNdWB_fixed_Asm_16:
6710 case ARM::VLD4LNdWB_fixed_Asm_32:
6711 case ARM::VLD4LNqWB_fixed_Asm_16:
6712 case ARM::VLD4LNqWB_fixed_Asm_32: {
6714 // Shuffle the operands around so the lane index operand is in the
6717 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6718 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6719 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6721 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6723 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6725 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6726 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6727 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6728 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6729 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6730 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6732 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6734 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6736 TmpInst.addOperand(Inst.getOperand(1)); // lane
6737 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6738 TmpInst.addOperand(Inst.getOperand(5));
6743 case ARM::VLD1LNdAsm_8:
6744 case ARM::VLD1LNdAsm_16:
6745 case ARM::VLD1LNdAsm_32: {
6747 // Shuffle the operands around so the lane index operand is in the
6750 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6751 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6752 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6753 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6754 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6755 TmpInst.addOperand(Inst.getOperand(1)); // lane
6756 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6757 TmpInst.addOperand(Inst.getOperand(5));
6762 case ARM::VLD2LNdAsm_8:
6763 case ARM::VLD2LNdAsm_16:
6764 case ARM::VLD2LNdAsm_32:
6765 case ARM::VLD2LNqAsm_16:
6766 case ARM::VLD2LNqAsm_32: {
6768 // Shuffle the operands around so the lane index operand is in the
6771 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6772 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6773 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6775 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6776 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6777 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6778 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6780 TmpInst.addOperand(Inst.getOperand(1)); // lane
6781 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6782 TmpInst.addOperand(Inst.getOperand(5));
6787 case ARM::VLD3LNdAsm_8:
6788 case ARM::VLD3LNdAsm_16:
6789 case ARM::VLD3LNdAsm_32:
6790 case ARM::VLD3LNqAsm_16:
6791 case ARM::VLD3LNqAsm_32: {
6793 // Shuffle the operands around so the lane index operand is in the
6796 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6797 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6798 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6800 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6802 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6803 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6804 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6805 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6807 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6809 TmpInst.addOperand(Inst.getOperand(1)); // lane
6810 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6811 TmpInst.addOperand(Inst.getOperand(5));
6816 case ARM::VLD4LNdAsm_8:
6817 case ARM::VLD4LNdAsm_16:
6818 case ARM::VLD4LNdAsm_32:
6819 case ARM::VLD4LNqAsm_16:
6820 case ARM::VLD4LNqAsm_32: {
6822 // Shuffle the operands around so the lane index operand is in the
6825 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6826 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6827 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6829 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6831 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6833 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6834 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6835 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6836 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6838 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6840 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6842 TmpInst.addOperand(Inst.getOperand(1)); // lane
6843 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6844 TmpInst.addOperand(Inst.getOperand(5));
6849 // VLD3DUP single 3-element structure to all lanes instructions.
6850 case ARM::VLD3DUPdAsm_8:
6851 case ARM::VLD3DUPdAsm_16:
6852 case ARM::VLD3DUPdAsm_32:
6853 case ARM::VLD3DUPqAsm_8:
6854 case ARM::VLD3DUPqAsm_16:
6855 case ARM::VLD3DUPqAsm_32: {
6858 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6859 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6860 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6862 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6864 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6865 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6866 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6867 TmpInst.addOperand(Inst.getOperand(4));
6872 case ARM::VLD3DUPdWB_fixed_Asm_8:
6873 case ARM::VLD3DUPdWB_fixed_Asm_16:
6874 case ARM::VLD3DUPdWB_fixed_Asm_32:
6875 case ARM::VLD3DUPqWB_fixed_Asm_8:
6876 case ARM::VLD3DUPqWB_fixed_Asm_16:
6877 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6880 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6881 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6882 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6884 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6886 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6887 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6888 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6889 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6890 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6891 TmpInst.addOperand(Inst.getOperand(4));
6896 case ARM::VLD3DUPdWB_register_Asm_8:
6897 case ARM::VLD3DUPdWB_register_Asm_16:
6898 case ARM::VLD3DUPdWB_register_Asm_32:
6899 case ARM::VLD3DUPqWB_register_Asm_8:
6900 case ARM::VLD3DUPqWB_register_Asm_16:
6901 case ARM::VLD3DUPqWB_register_Asm_32: {
6904 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6905 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6906 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6908 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6910 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6911 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6912 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6913 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6914 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6915 TmpInst.addOperand(Inst.getOperand(5));
6920 // VLD3 multiple 3-element structure instructions.
6921 case ARM::VLD3dAsm_8:
6922 case ARM::VLD3dAsm_16:
6923 case ARM::VLD3dAsm_32:
6924 case ARM::VLD3qAsm_8:
6925 case ARM::VLD3qAsm_16:
6926 case ARM::VLD3qAsm_32: {
6929 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6930 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6931 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6933 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6935 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6936 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6937 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6938 TmpInst.addOperand(Inst.getOperand(4));
6943 case ARM::VLD3dWB_fixed_Asm_8:
6944 case ARM::VLD3dWB_fixed_Asm_16:
6945 case ARM::VLD3dWB_fixed_Asm_32:
6946 case ARM::VLD3qWB_fixed_Asm_8:
6947 case ARM::VLD3qWB_fixed_Asm_16:
6948 case ARM::VLD3qWB_fixed_Asm_32: {
6951 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6952 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6953 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6955 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6957 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6958 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6959 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6960 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6961 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6962 TmpInst.addOperand(Inst.getOperand(4));
6967 case ARM::VLD3dWB_register_Asm_8:
6968 case ARM::VLD3dWB_register_Asm_16:
6969 case ARM::VLD3dWB_register_Asm_32:
6970 case ARM::VLD3qWB_register_Asm_8:
6971 case ARM::VLD3qWB_register_Asm_16:
6972 case ARM::VLD3qWB_register_Asm_32: {
6975 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6976 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6977 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6979 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6981 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6982 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6983 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6984 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6985 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6986 TmpInst.addOperand(Inst.getOperand(5));
6991 // VLD4DUP single 3-element structure to all lanes instructions.
6992 case ARM::VLD4DUPdAsm_8:
6993 case ARM::VLD4DUPdAsm_16:
6994 case ARM::VLD4DUPdAsm_32:
6995 case ARM::VLD4DUPqAsm_8:
6996 case ARM::VLD4DUPqAsm_16:
6997 case ARM::VLD4DUPqAsm_32: {
7000 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7001 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7002 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7004 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7006 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7008 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7009 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7010 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7011 TmpInst.addOperand(Inst.getOperand(4));
7016 case ARM::VLD4DUPdWB_fixed_Asm_8:
7017 case ARM::VLD4DUPdWB_fixed_Asm_16:
7018 case ARM::VLD4DUPdWB_fixed_Asm_32:
7019 case ARM::VLD4DUPqWB_fixed_Asm_8:
7020 case ARM::VLD4DUPqWB_fixed_Asm_16:
7021 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7024 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7025 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7026 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7028 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7030 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7032 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7033 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7034 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7035 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7036 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7037 TmpInst.addOperand(Inst.getOperand(4));
7042 case ARM::VLD4DUPdWB_register_Asm_8:
7043 case ARM::VLD4DUPdWB_register_Asm_16:
7044 case ARM::VLD4DUPdWB_register_Asm_32:
7045 case ARM::VLD4DUPqWB_register_Asm_8:
7046 case ARM::VLD4DUPqWB_register_Asm_16:
7047 case ARM::VLD4DUPqWB_register_Asm_32: {
7050 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7051 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7052 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7054 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7056 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7058 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7059 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7060 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7061 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7062 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7063 TmpInst.addOperand(Inst.getOperand(5));
7068 // VLD4 multiple 4-element structure instructions.
7069 case ARM::VLD4dAsm_8:
7070 case ARM::VLD4dAsm_16:
7071 case ARM::VLD4dAsm_32:
7072 case ARM::VLD4qAsm_8:
7073 case ARM::VLD4qAsm_16:
7074 case ARM::VLD4qAsm_32: {
7077 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7078 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7079 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7081 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7083 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7085 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7086 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7087 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7088 TmpInst.addOperand(Inst.getOperand(4));
7093 case ARM::VLD4dWB_fixed_Asm_8:
7094 case ARM::VLD4dWB_fixed_Asm_16:
7095 case ARM::VLD4dWB_fixed_Asm_32:
7096 case ARM::VLD4qWB_fixed_Asm_8:
7097 case ARM::VLD4qWB_fixed_Asm_16:
7098 case ARM::VLD4qWB_fixed_Asm_32: {
7101 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7102 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7103 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7105 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7107 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7109 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7110 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7111 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7112 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7113 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7114 TmpInst.addOperand(Inst.getOperand(4));
7119 case ARM::VLD4dWB_register_Asm_8:
7120 case ARM::VLD4dWB_register_Asm_16:
7121 case ARM::VLD4dWB_register_Asm_32:
7122 case ARM::VLD4qWB_register_Asm_8:
7123 case ARM::VLD4qWB_register_Asm_16:
7124 case ARM::VLD4qWB_register_Asm_32: {
7127 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7128 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7129 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7131 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7133 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7135 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7136 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7137 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7138 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7139 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7140 TmpInst.addOperand(Inst.getOperand(5));
7145 // VST3 multiple 3-element structure instructions.
7146 case ARM::VST3dAsm_8:
7147 case ARM::VST3dAsm_16:
7148 case ARM::VST3dAsm_32:
7149 case ARM::VST3qAsm_8:
7150 case ARM::VST3qAsm_16:
7151 case ARM::VST3qAsm_32: {
7154 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7155 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7156 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7157 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7158 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7160 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7162 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7163 TmpInst.addOperand(Inst.getOperand(4));
7168 case ARM::VST3dWB_fixed_Asm_8:
7169 case ARM::VST3dWB_fixed_Asm_16:
7170 case ARM::VST3dWB_fixed_Asm_32:
7171 case ARM::VST3qWB_fixed_Asm_8:
7172 case ARM::VST3qWB_fixed_Asm_16:
7173 case ARM::VST3qWB_fixed_Asm_32: {
7176 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7177 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7178 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7179 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7180 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7181 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7182 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7184 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7186 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7187 TmpInst.addOperand(Inst.getOperand(4));
7192 case ARM::VST3dWB_register_Asm_8:
7193 case ARM::VST3dWB_register_Asm_16:
7194 case ARM::VST3dWB_register_Asm_32:
7195 case ARM::VST3qWB_register_Asm_8:
7196 case ARM::VST3qWB_register_Asm_16:
7197 case ARM::VST3qWB_register_Asm_32: {
7200 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7201 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7202 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7203 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7204 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7205 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7206 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7208 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7210 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7211 TmpInst.addOperand(Inst.getOperand(5));
7216 // VST4 multiple 3-element structure instructions.
7217 case ARM::VST4dAsm_8:
7218 case ARM::VST4dAsm_16:
7219 case ARM::VST4dAsm_32:
7220 case ARM::VST4qAsm_8:
7221 case ARM::VST4qAsm_16:
7222 case ARM::VST4qAsm_32: {
7225 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7226 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7227 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7228 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7229 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7231 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7233 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7235 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7236 TmpInst.addOperand(Inst.getOperand(4));
7241 case ARM::VST4dWB_fixed_Asm_8:
7242 case ARM::VST4dWB_fixed_Asm_16:
7243 case ARM::VST4dWB_fixed_Asm_32:
7244 case ARM::VST4qWB_fixed_Asm_8:
7245 case ARM::VST4qWB_fixed_Asm_16:
7246 case ARM::VST4qWB_fixed_Asm_32: {
7249 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7250 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7251 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7252 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7253 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7254 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7255 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7257 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7259 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7261 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7262 TmpInst.addOperand(Inst.getOperand(4));
7267 case ARM::VST4dWB_register_Asm_8:
7268 case ARM::VST4dWB_register_Asm_16:
7269 case ARM::VST4dWB_register_Asm_32:
7270 case ARM::VST4qWB_register_Asm_8:
7271 case ARM::VST4qWB_register_Asm_16:
7272 case ARM::VST4qWB_register_Asm_32: {
7275 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7276 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7277 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7278 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7279 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7280 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7281 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7283 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7285 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7287 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7288 TmpInst.addOperand(Inst.getOperand(5));
7293 // Handle encoding choice for the shift-immediate instructions.
7296 case ARM::t2ASRri: {
7297 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7298 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7299 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7300 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7301 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7303 switch (Inst.getOpcode()) {
7304 default: llvm_unreachable("unexpected opcode");
7305 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7306 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7307 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7309 // The Thumb1 operands aren't in the same order. Awesome, eh?
7311 TmpInst.setOpcode(NewOpc);
7312 TmpInst.addOperand(Inst.getOperand(0));
7313 TmpInst.addOperand(Inst.getOperand(5));
7314 TmpInst.addOperand(Inst.getOperand(1));
7315 TmpInst.addOperand(Inst.getOperand(2));
7316 TmpInst.addOperand(Inst.getOperand(3));
7317 TmpInst.addOperand(Inst.getOperand(4));
7324 // Handle the Thumb2 mode MOV complex aliases.
7326 case ARM::t2MOVSsr: {
7327 // Which instruction to expand to depends on the CCOut operand and
7328 // whether we're in an IT block if the register operands are low
7330 bool isNarrow = false;
7331 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7332 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7333 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7334 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7335 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7339 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7340 default: llvm_unreachable("unexpected opcode!");
7341 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7342 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7343 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7344 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7346 TmpInst.setOpcode(newOpc);
7347 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7349 TmpInst.addOperand(MCOperand::CreateReg(
7350 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7351 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7352 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7353 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7354 TmpInst.addOperand(Inst.getOperand(5));
7356 TmpInst.addOperand(MCOperand::CreateReg(
7357 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7362 case ARM::t2MOVSsi: {
7363 // Which instruction to expand to depends on the CCOut operand and
7364 // whether we're in an IT block if the register operands are low
7366 bool isNarrow = false;
7367 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7368 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7369 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7373 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7374 default: llvm_unreachable("unexpected opcode!");
7375 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7376 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7377 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7378 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7379 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7381 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7382 if (Amount == 32) Amount = 0;
7383 TmpInst.setOpcode(newOpc);
7384 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7386 TmpInst.addOperand(MCOperand::CreateReg(
7387 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7388 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7389 if (newOpc != ARM::t2RRX)
7390 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7391 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7392 TmpInst.addOperand(Inst.getOperand(4));
7394 TmpInst.addOperand(MCOperand::CreateReg(
7395 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7399 // Handle the ARM mode MOV complex aliases.
7404 ARM_AM::ShiftOpc ShiftTy;
7405 switch(Inst.getOpcode()) {
7406 default: llvm_unreachable("unexpected opcode!");
7407 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7408 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7409 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7410 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7412 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7414 TmpInst.setOpcode(ARM::MOVsr);
7415 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7416 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7417 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7418 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7419 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7420 TmpInst.addOperand(Inst.getOperand(4));
7421 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7429 ARM_AM::ShiftOpc ShiftTy;
7430 switch(Inst.getOpcode()) {
7431 default: llvm_unreachable("unexpected opcode!");
7432 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7433 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7434 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7435 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7437 // A shift by zero is a plain MOVr, not a MOVsi.
7438 unsigned Amt = Inst.getOperand(2).getImm();
7439 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7440 // A shift by 32 should be encoded as 0 when permitted
7441 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7443 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7445 TmpInst.setOpcode(Opc);
7446 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7447 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7448 if (Opc == ARM::MOVsi)
7449 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7450 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7451 TmpInst.addOperand(Inst.getOperand(4));
7452 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7457 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7459 TmpInst.setOpcode(ARM::MOVsi);
7460 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7461 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7462 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7463 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7464 TmpInst.addOperand(Inst.getOperand(3));
7465 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7469 case ARM::t2LDMIA_UPD: {
7470 // If this is a load of a single register, then we should use
7471 // a post-indexed LDR instruction instead, per the ARM ARM.
7472 if (Inst.getNumOperands() != 5)
7475 TmpInst.setOpcode(ARM::t2LDR_POST);
7476 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7477 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7478 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7479 TmpInst.addOperand(MCOperand::CreateImm(4));
7480 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7481 TmpInst.addOperand(Inst.getOperand(3));
7485 case ARM::t2STMDB_UPD: {
7486 // If this is a store of a single register, then we should use
7487 // a pre-indexed STR instruction instead, per the ARM ARM.
7488 if (Inst.getNumOperands() != 5)
7491 TmpInst.setOpcode(ARM::t2STR_PRE);
7492 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7493 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7494 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7495 TmpInst.addOperand(MCOperand::CreateImm(-4));
7496 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7497 TmpInst.addOperand(Inst.getOperand(3));
7501 case ARM::LDMIA_UPD:
7502 // If this is a load of a single register via a 'pop', then we should use
7503 // a post-indexed LDR instruction instead, per the ARM ARM.
7504 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7505 Inst.getNumOperands() == 5) {
7507 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7508 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7509 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7510 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7511 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7512 TmpInst.addOperand(MCOperand::CreateImm(4));
7513 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7514 TmpInst.addOperand(Inst.getOperand(3));
7519 case ARM::STMDB_UPD:
7520 // If this is a store of a single register via a 'push', then we should use
7521 // a pre-indexed STR instruction instead, per the ARM ARM.
7522 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7523 Inst.getNumOperands() == 5) {
7525 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7526 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7527 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7528 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7529 TmpInst.addOperand(MCOperand::CreateImm(-4));
7530 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7531 TmpInst.addOperand(Inst.getOperand(3));
7535 case ARM::t2ADDri12:
7536 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7537 // mnemonic was used (not "addw"), encoding T3 is preferred.
7538 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7539 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7541 Inst.setOpcode(ARM::t2ADDri);
7542 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7544 case ARM::t2SUBri12:
7545 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7546 // mnemonic was used (not "subw"), encoding T3 is preferred.
7547 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7548 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7550 Inst.setOpcode(ARM::t2SUBri);
7551 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7554 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7555 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7556 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7557 // to encoding T1 if <Rd> is omitted."
7558 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7559 Inst.setOpcode(ARM::tADDi3);
7564 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7565 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7566 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7567 // to encoding T1 if <Rd> is omitted."
7568 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7569 Inst.setOpcode(ARM::tSUBi3);
7574 case ARM::t2SUBri: {
7575 // If the destination and first source operand are the same, and
7576 // the flags are compatible with the current IT status, use encoding T2
7577 // instead of T3. For compatibility with the system 'as'. Make sure the
7578 // wide encoding wasn't explicit.
7579 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7580 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7581 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7582 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7583 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7584 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7585 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7588 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7589 ARM::tADDi8 : ARM::tSUBi8);
7590 TmpInst.addOperand(Inst.getOperand(0));
7591 TmpInst.addOperand(Inst.getOperand(5));
7592 TmpInst.addOperand(Inst.getOperand(0));
7593 TmpInst.addOperand(Inst.getOperand(2));
7594 TmpInst.addOperand(Inst.getOperand(3));
7595 TmpInst.addOperand(Inst.getOperand(4));
7599 case ARM::t2ADDrr: {
7600 // If the destination and first source operand are the same, and
7601 // there's no setting of the flags, use encoding T2 instead of T3.
7602 // Note that this is only for ADD, not SUB. This mirrors the system
7603 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7604 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7605 Inst.getOperand(5).getReg() != 0 ||
7606 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7607 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7610 TmpInst.setOpcode(ARM::tADDhirr);
7611 TmpInst.addOperand(Inst.getOperand(0));
7612 TmpInst.addOperand(Inst.getOperand(0));
7613 TmpInst.addOperand(Inst.getOperand(2));
7614 TmpInst.addOperand(Inst.getOperand(3));
7615 TmpInst.addOperand(Inst.getOperand(4));
7619 case ARM::tADDrSP: {
7620 // If the non-SP source operand and the destination operand are not the
7621 // same, we need to use the 32-bit encoding if it's available.
7622 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7623 Inst.setOpcode(ARM::t2ADDrr);
7624 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7630 // A Thumb conditional branch outside of an IT block is a tBcc.
7631 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7632 Inst.setOpcode(ARM::tBcc);
7637 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7638 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7639 Inst.setOpcode(ARM::t2Bcc);
7644 // If the conditional is AL or we're in an IT block, we really want t2B.
7645 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7646 Inst.setOpcode(ARM::t2B);
7651 // If the conditional is AL, we really want tB.
7652 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7653 Inst.setOpcode(ARM::tB);
7658 // If the register list contains any high registers, or if the writeback
7659 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7660 // instead if we're in Thumb2. Otherwise, this should have generated
7661 // an error in validateInstruction().
7662 unsigned Rn = Inst.getOperand(0).getReg();
7663 bool hasWritebackToken =
7664 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7665 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7666 bool listContainsBase;
7667 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7668 (!listContainsBase && !hasWritebackToken) ||
7669 (listContainsBase && hasWritebackToken)) {
7670 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7671 assert (isThumbTwo());
7672 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7673 // If we're switching to the updating version, we need to insert
7674 // the writeback tied operand.
7675 if (hasWritebackToken)
7676 Inst.insert(Inst.begin(),
7677 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7682 case ARM::tSTMIA_UPD: {
7683 // If the register list contains any high registers, we need to use
7684 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7685 // should have generated an error in validateInstruction().
7686 unsigned Rn = Inst.getOperand(0).getReg();
7687 bool listContainsBase;
7688 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7689 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7690 assert (isThumbTwo());
7691 Inst.setOpcode(ARM::t2STMIA_UPD);
7697 bool listContainsBase;
7698 // If the register list contains any high registers, we need to use
7699 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7700 // should have generated an error in validateInstruction().
7701 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7703 assert (isThumbTwo());
7704 Inst.setOpcode(ARM::t2LDMIA_UPD);
7705 // Add the base register and writeback operands.
7706 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7707 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7711 bool listContainsBase;
7712 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7714 assert (isThumbTwo());
7715 Inst.setOpcode(ARM::t2STMDB_UPD);
7716 // Add the base register and writeback operands.
7717 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7718 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7722 // If we can use the 16-bit encoding and the user didn't explicitly
7723 // request the 32-bit variant, transform it here.
7724 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7725 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7726 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7727 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7728 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7729 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7730 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7731 // The operands aren't in the same order for tMOVi8...
7733 TmpInst.setOpcode(ARM::tMOVi8);
7734 TmpInst.addOperand(Inst.getOperand(0));
7735 TmpInst.addOperand(Inst.getOperand(4));
7736 TmpInst.addOperand(Inst.getOperand(1));
7737 TmpInst.addOperand(Inst.getOperand(2));
7738 TmpInst.addOperand(Inst.getOperand(3));
7745 // If we can use the 16-bit encoding and the user didn't explicitly
7746 // request the 32-bit variant, transform it here.
7747 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7748 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7749 Inst.getOperand(2).getImm() == ARMCC::AL &&
7750 Inst.getOperand(4).getReg() == ARM::CPSR &&
7751 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7752 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7753 // The operands aren't the same for tMOV[S]r... (no cc_out)
7755 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7756 TmpInst.addOperand(Inst.getOperand(0));
7757 TmpInst.addOperand(Inst.getOperand(1));
7758 TmpInst.addOperand(Inst.getOperand(2));
7759 TmpInst.addOperand(Inst.getOperand(3));
7769 // If we can use the 16-bit encoding and the user didn't explicitly
7770 // request the 32-bit variant, transform it here.
7771 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7772 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7773 Inst.getOperand(2).getImm() == 0 &&
7774 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7775 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7777 switch (Inst.getOpcode()) {
7778 default: llvm_unreachable("Illegal opcode!");
7779 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7780 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7781 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7782 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7784 // The operands aren't the same for thumb1 (no rotate operand).
7786 TmpInst.setOpcode(NewOpc);
7787 TmpInst.addOperand(Inst.getOperand(0));
7788 TmpInst.addOperand(Inst.getOperand(1));
7789 TmpInst.addOperand(Inst.getOperand(3));
7790 TmpInst.addOperand(Inst.getOperand(4));
7797 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7798 // rrx shifts and asr/lsr of #32 is encoded as 0
7799 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7801 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7802 // Shifting by zero is accepted as a vanilla 'MOVr'
7804 TmpInst.setOpcode(ARM::MOVr);
7805 TmpInst.addOperand(Inst.getOperand(0));
7806 TmpInst.addOperand(Inst.getOperand(1));
7807 TmpInst.addOperand(Inst.getOperand(3));
7808 TmpInst.addOperand(Inst.getOperand(4));
7809 TmpInst.addOperand(Inst.getOperand(5));
7822 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7823 if (SOpc == ARM_AM::rrx) return false;
7824 switch (Inst.getOpcode()) {
7825 default: llvm_unreachable("unexpected opcode!");
7826 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7827 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7828 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7829 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7830 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7831 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7833 // If the shift is by zero, use the non-shifted instruction definition.
7834 // The exception is for right shifts, where 0 == 32
7835 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7836 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7838 TmpInst.setOpcode(newOpc);
7839 TmpInst.addOperand(Inst.getOperand(0));
7840 TmpInst.addOperand(Inst.getOperand(1));
7841 TmpInst.addOperand(Inst.getOperand(2));
7842 TmpInst.addOperand(Inst.getOperand(4));
7843 TmpInst.addOperand(Inst.getOperand(5));
7844 TmpInst.addOperand(Inst.getOperand(6));
7852 // The mask bits for all but the first condition are represented as
7853 // the low bit of the condition code value implies 't'. We currently
7854 // always have 1 implies 't', so XOR toggle the bits if the low bit
7855 // of the condition code is zero.
7856 MCOperand &MO = Inst.getOperand(1);
7857 unsigned Mask = MO.getImm();
7858 unsigned OrigMask = Mask;
7859 unsigned TZ = countTrailingZeros(Mask);
7860 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7861 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7862 Mask ^= (0xE << TZ) & 0xF;
7866 // Set up the IT block state according to the IT instruction we just
7868 assert(!inITBlock() && "nested IT blocks?!");
7869 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7870 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7871 ITState.CurPosition = 0;
7872 ITState.FirstCond = true;
7882 // Assemblers should use the narrow encodings of these instructions when permissible.
7883 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7884 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7885 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7886 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7887 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7888 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7889 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7891 switch (Inst.getOpcode()) {
7892 default: llvm_unreachable("unexpected opcode");
7893 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7894 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7895 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7896 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7897 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7898 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7901 TmpInst.setOpcode(NewOpc);
7902 TmpInst.addOperand(Inst.getOperand(0));
7903 TmpInst.addOperand(Inst.getOperand(5));
7904 TmpInst.addOperand(Inst.getOperand(1));
7905 TmpInst.addOperand(Inst.getOperand(2));
7906 TmpInst.addOperand(Inst.getOperand(3));
7907 TmpInst.addOperand(Inst.getOperand(4));
7918 // Assemblers should use the narrow encodings of these instructions when permissible.
7919 // These instructions are special in that they are commutable, so shorter encodings
7920 // are available more often.
7921 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7922 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7923 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7924 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7925 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7926 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7927 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7928 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7930 switch (Inst.getOpcode()) {
7931 default: llvm_unreachable("unexpected opcode");
7932 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7933 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7934 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7935 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7938 TmpInst.setOpcode(NewOpc);
7939 TmpInst.addOperand(Inst.getOperand(0));
7940 TmpInst.addOperand(Inst.getOperand(5));
7941 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7942 TmpInst.addOperand(Inst.getOperand(1));
7943 TmpInst.addOperand(Inst.getOperand(2));
7945 TmpInst.addOperand(Inst.getOperand(2));
7946 TmpInst.addOperand(Inst.getOperand(1));
7948 TmpInst.addOperand(Inst.getOperand(3));
7949 TmpInst.addOperand(Inst.getOperand(4));
7959 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7960 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7961 // suffix depending on whether they're in an IT block or not.
7962 unsigned Opc = Inst.getOpcode();
7963 const MCInstrDesc &MCID = MII.get(Opc);
7964 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7965 assert(MCID.hasOptionalDef() &&
7966 "optionally flag setting instruction missing optional def operand");
7967 assert(MCID.NumOperands == Inst.getNumOperands() &&
7968 "operand count mismatch!");
7969 // Find the optional-def operand (cc_out).
7972 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7975 // If we're parsing Thumb1, reject it completely.
7976 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7977 return Match_MnemonicFail;
7978 // If we're parsing Thumb2, which form is legal depends on whether we're
7980 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7982 return Match_RequiresITBlock;
7983 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7985 return Match_RequiresNotITBlock;
7987 // Some high-register supporting Thumb1 encodings only allow both registers
7988 // to be from r0-r7 when in Thumb2.
7989 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7990 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7991 isARMLowRegister(Inst.getOperand(2).getReg()))
7992 return Match_RequiresThumb2;
7993 // Others only require ARMv6 or later.
7994 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7995 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7996 isARMLowRegister(Inst.getOperand(1).getReg()))
7997 return Match_RequiresV6;
7998 return Match_Success;
8002 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8003 return true; // In an assembly source, no need to second-guess
8007 static const char *getSubtargetFeatureName(unsigned Val);
8009 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8010 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
8011 MCStreamer &Out, unsigned &ErrorInfo,
8012 bool MatchingInlineAsm) {
8014 unsigned MatchResult;
8016 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8018 switch (MatchResult) {
8021 // Context sensitive operand constraints aren't handled by the matcher,
8022 // so check them here.
8023 if (validateInstruction(Inst, Operands)) {
8024 // Still progress the IT block, otherwise one wrong condition causes
8025 // nasty cascading errors.
8026 forwardITPosition();
8030 { // processInstruction() updates inITBlock state, we need to save it away
8031 bool wasInITBlock = inITBlock();
8033 // Some instructions need post-processing to, for example, tweak which
8034 // encoding is selected. Loop on it while changes happen so the
8035 // individual transformations can chain off each other. E.g.,
8036 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8037 while (processInstruction(Inst, Operands))
8040 // Only after the instruction is fully processed, we can validate it
8041 if (wasInITBlock && hasV8Ops() && isThumb() &&
8042 !isV8EligibleForIT(&Inst)) {
8043 Warning(IDLoc, "deprecated instruction in IT block");
8047 // Only move forward at the very end so that everything in validate
8048 // and process gets a consistent answer about whether we're in an IT
8050 forwardITPosition();
8052 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8053 // doesn't actually encode.
8054 if (Inst.getOpcode() == ARM::ITasm)
8058 Out.EmitInstruction(Inst, STI);
8060 case Match_MissingFeature: {
8061 assert(ErrorInfo && "Unknown missing feature!");
8062 // Special case the error message for the very common case where only
8063 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8064 std::string Msg = "instruction requires:";
8066 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8067 if (ErrorInfo & Mask) {
8069 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8073 return Error(IDLoc, Msg);
8075 case Match_InvalidOperand: {
8076 SMLoc ErrorLoc = IDLoc;
8077 if (ErrorInfo != ~0U) {
8078 if (ErrorInfo >= Operands.size())
8079 return Error(IDLoc, "too few operands for instruction");
8081 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8082 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8085 return Error(ErrorLoc, "invalid operand for instruction");
8087 case Match_MnemonicFail:
8088 return Error(IDLoc, "invalid instruction",
8089 ((ARMOperand*)Operands[0])->getLocRange());
8090 case Match_RequiresNotITBlock:
8091 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8092 case Match_RequiresITBlock:
8093 return Error(IDLoc, "instruction only valid inside IT block");
8094 case Match_RequiresV6:
8095 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8096 case Match_RequiresThumb2:
8097 return Error(IDLoc, "instruction variant requires Thumb2");
8098 case Match_ImmRange0_15: {
8099 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8100 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8101 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8103 case Match_ImmRange0_239: {
8104 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
8105 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8106 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8108 case Match_AlignedMemoryRequiresNone:
8109 case Match_DupAlignedMemoryRequiresNone:
8110 case Match_AlignedMemoryRequires16:
8111 case Match_DupAlignedMemoryRequires16:
8112 case Match_AlignedMemoryRequires32:
8113 case Match_DupAlignedMemoryRequires32:
8114 case Match_AlignedMemoryRequires64:
8115 case Match_DupAlignedMemoryRequires64:
8116 case Match_AlignedMemoryRequires64or128:
8117 case Match_DupAlignedMemoryRequires64or128:
8118 case Match_AlignedMemoryRequires64or128or256:
8120 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getAlignmentLoc();
8121 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8122 switch (MatchResult) {
8124 llvm_unreachable("Missing Match_Aligned type");
8125 case Match_AlignedMemoryRequiresNone:
8126 case Match_DupAlignedMemoryRequiresNone:
8127 return Error(ErrorLoc, "alignment must be omitted");
8128 case Match_AlignedMemoryRequires16:
8129 case Match_DupAlignedMemoryRequires16:
8130 return Error(ErrorLoc, "alignment must be 16 or omitted");
8131 case Match_AlignedMemoryRequires32:
8132 case Match_DupAlignedMemoryRequires32:
8133 return Error(ErrorLoc, "alignment must be 32 or omitted");
8134 case Match_AlignedMemoryRequires64:
8135 case Match_DupAlignedMemoryRequires64:
8136 return Error(ErrorLoc, "alignment must be 64 or omitted");
8137 case Match_AlignedMemoryRequires64or128:
8138 case Match_DupAlignedMemoryRequires64or128:
8139 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8140 case Match_AlignedMemoryRequires64or128or256:
8141 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8146 llvm_unreachable("Implement any new match types added!");
8149 /// parseDirective parses the arm specific directives
8150 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8151 const MCObjectFileInfo::Environment Format =
8152 getContext().getObjectFileInfo()->getObjectFileType();
8153 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8155 StringRef IDVal = DirectiveID.getIdentifier();
8156 if (IDVal == ".word")
8157 return parseLiteralValues(4, DirectiveID.getLoc());
8158 else if (IDVal == ".short" || IDVal == ".hword")
8159 return parseLiteralValues(2, DirectiveID.getLoc());
8160 else if (IDVal == ".thumb")
8161 return parseDirectiveThumb(DirectiveID.getLoc());
8162 else if (IDVal == ".arm")
8163 return parseDirectiveARM(DirectiveID.getLoc());
8164 else if (IDVal == ".thumb_func")
8165 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8166 else if (IDVal == ".code")
8167 return parseDirectiveCode(DirectiveID.getLoc());
8168 else if (IDVal == ".syntax")
8169 return parseDirectiveSyntax(DirectiveID.getLoc());
8170 else if (IDVal == ".unreq")
8171 return parseDirectiveUnreq(DirectiveID.getLoc());
8172 else if (IDVal == ".fnend")
8173 return parseDirectiveFnEnd(DirectiveID.getLoc());
8174 else if (IDVal == ".cantunwind")
8175 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8176 else if (IDVal == ".personality")
8177 return parseDirectivePersonality(DirectiveID.getLoc());
8178 else if (IDVal == ".handlerdata")
8179 return parseDirectiveHandlerData(DirectiveID.getLoc());
8180 else if (IDVal == ".setfp")
8181 return parseDirectiveSetFP(DirectiveID.getLoc());
8182 else if (IDVal == ".pad")
8183 return parseDirectivePad(DirectiveID.getLoc());
8184 else if (IDVal == ".save")
8185 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8186 else if (IDVal == ".vsave")
8187 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8188 else if (IDVal == ".ltorg" || IDVal == ".pool")
8189 return parseDirectiveLtorg(DirectiveID.getLoc());
8190 else if (IDVal == ".even")
8191 return parseDirectiveEven(DirectiveID.getLoc());
8192 else if (IDVal == ".personalityindex")
8193 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8194 else if (IDVal == ".unwind_raw")
8195 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8196 else if (IDVal == ".movsp")
8197 return parseDirectiveMovSP(DirectiveID.getLoc());
8198 else if (IDVal == ".arch_extension")
8199 return parseDirectiveArchExtension(DirectiveID.getLoc());
8200 else if (IDVal == ".align")
8201 return parseDirectiveAlign(DirectiveID.getLoc());
8202 else if (IDVal == ".thumb_set")
8203 return parseDirectiveThumbSet(DirectiveID.getLoc());
8206 if (IDVal == ".arch")
8207 return parseDirectiveArch(DirectiveID.getLoc());
8208 else if (IDVal == ".cpu")
8209 return parseDirectiveCPU(DirectiveID.getLoc());
8210 else if (IDVal == ".eabi_attribute")
8211 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8212 else if (IDVal == ".fpu")
8213 return parseDirectiveFPU(DirectiveID.getLoc());
8214 else if (IDVal == ".fnstart")
8215 return parseDirectiveFnStart(DirectiveID.getLoc());
8216 else if (IDVal == ".inst")
8217 return parseDirectiveInst(DirectiveID.getLoc());
8218 else if (IDVal == ".inst.n")
8219 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8220 else if (IDVal == ".inst.w")
8221 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8222 else if (IDVal == ".object_arch")
8223 return parseDirectiveObjectArch(DirectiveID.getLoc());
8224 else if (IDVal == ".tlsdescseq")
8225 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8231 /// parseLiteralValues
8232 /// ::= .hword expression [, expression]*
8233 /// ::= .short expression [, expression]*
8234 /// ::= .word expression [, expression]*
8235 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8236 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8238 const MCExpr *Value;
8239 if (getParser().parseExpression(Value)) {
8240 Parser.eatToEndOfStatement();
8244 getParser().getStreamer().EmitValue(Value, Size);
8246 if (getLexer().is(AsmToken::EndOfStatement))
8249 // FIXME: Improve diagnostic.
8250 if (getLexer().isNot(AsmToken::Comma)) {
8251 Error(L, "unexpected token in directive");
8262 /// parseDirectiveThumb
8264 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8265 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8266 Error(L, "unexpected token in directive");
8272 Error(L, "target does not support Thumb mode");
8279 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8283 /// parseDirectiveARM
8285 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8286 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8287 Error(L, "unexpected token in directive");
8293 Error(L, "target does not support ARM mode");
8300 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8304 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8305 if (NextSymbolIsThumb) {
8306 getParser().getStreamer().EmitThumbFunc(Symbol);
8307 NextSymbolIsThumb = false;
8314 const MCObjectFileInfo::Environment Format =
8315 getContext().getObjectFileInfo()->getObjectFileType();
8317 case MCObjectFileInfo::IsCOFF: {
8318 const MCSymbolData &SD =
8319 getParser().getStreamer().getOrCreateSymbolData(Symbol);
8320 char Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
8321 if (SD.getFlags() & (Type << COFF::SF_TypeShift))
8322 getParser().getStreamer().EmitThumbFunc(Symbol);
8325 case MCObjectFileInfo::IsELF: {
8326 const MCSymbolData &SD =
8327 getParser().getStreamer().getOrCreateSymbolData(Symbol);
8328 if (MCELF::GetType(SD) & (ELF::STT_FUNC << ELF_STT_Shift))
8329 getParser().getStreamer().EmitThumbFunc(Symbol);
8332 case MCObjectFileInfo::IsMachO:
8337 /// parseDirectiveThumbFunc
8338 /// ::= .thumbfunc symbol_name
8339 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8340 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8341 bool isMachO = MAI->hasSubsectionsViaSymbols();
8343 // Darwin asm has (optionally) function name after .thumb_func direction
8346 const AsmToken &Tok = Parser.getTok();
8347 if (Tok.isNot(AsmToken::EndOfStatement)) {
8348 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8349 Error(L, "unexpected token in .thumb_func directive");
8354 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8355 getParser().getStreamer().EmitThumbFunc(Func);
8356 Parser.Lex(); // Consume the identifier token.
8361 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8362 Error(L, "unexpected token in directive");
8366 NextSymbolIsThumb = true;
8370 /// parseDirectiveSyntax
8371 /// ::= .syntax unified | divided
8372 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8373 const AsmToken &Tok = Parser.getTok();
8374 if (Tok.isNot(AsmToken::Identifier)) {
8375 Error(L, "unexpected token in .syntax directive");
8379 StringRef Mode = Tok.getString();
8380 if (Mode == "unified" || Mode == "UNIFIED") {
8382 } else if (Mode == "divided" || Mode == "DIVIDED") {
8383 Error(L, "'.syntax divided' arm asssembly not supported");
8386 Error(L, "unrecognized syntax mode in .syntax directive");
8390 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8391 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8396 // TODO tell the MC streamer the mode
8397 // getParser().getStreamer().Emit???();
8401 /// parseDirectiveCode
8402 /// ::= .code 16 | 32
8403 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8404 const AsmToken &Tok = Parser.getTok();
8405 if (Tok.isNot(AsmToken::Integer)) {
8406 Error(L, "unexpected token in .code directive");
8409 int64_t Val = Parser.getTok().getIntVal();
8410 if (Val != 16 && Val != 32) {
8411 Error(L, "invalid operand to .code directive");
8416 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8417 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8424 Error(L, "target does not support Thumb mode");
8430 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8433 Error(L, "target does not support ARM mode");
8439 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8445 /// parseDirectiveReq
8446 /// ::= name .req registername
8447 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8448 Parser.Lex(); // Eat the '.req' token.
8450 SMLoc SRegLoc, ERegLoc;
8451 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8452 Parser.eatToEndOfStatement();
8453 Error(SRegLoc, "register name expected");
8457 // Shouldn't be anything else.
8458 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8459 Parser.eatToEndOfStatement();
8460 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8464 Parser.Lex(); // Consume the EndOfStatement
8466 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8467 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8474 /// parseDirectiveUneq
8475 /// ::= .unreq registername
8476 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8477 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8478 Parser.eatToEndOfStatement();
8479 Error(L, "unexpected input in .unreq directive.");
8482 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8483 Parser.Lex(); // Eat the identifier.
8487 /// parseDirectiveArch
8489 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8490 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8492 unsigned ID = StringSwitch<unsigned>(Arch)
8493 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8494 .Case(NAME, ARM::ID)
8495 #define ARM_ARCH_ALIAS(NAME, ID) \
8496 .Case(NAME, ARM::ID)
8497 #include "MCTargetDesc/ARMArchName.def"
8498 .Default(ARM::INVALID_ARCH);
8500 if (ID == ARM::INVALID_ARCH) {
8501 Error(L, "Unknown arch name");
8505 getTargetStreamer().emitArch(ID);
8509 /// parseDirectiveEabiAttr
8510 /// ::= .eabi_attribute int, int [, "str"]
8511 /// ::= .eabi_attribute Tag_name, int [, "str"]
8512 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8515 TagLoc = Parser.getTok().getLoc();
8516 if (Parser.getTok().is(AsmToken::Identifier)) {
8517 StringRef Name = Parser.getTok().getIdentifier();
8518 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8520 Error(TagLoc, "attribute name not recognised: " + Name);
8521 Parser.eatToEndOfStatement();
8526 const MCExpr *AttrExpr;
8528 TagLoc = Parser.getTok().getLoc();
8529 if (Parser.parseExpression(AttrExpr)) {
8530 Parser.eatToEndOfStatement();
8534 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8536 Error(TagLoc, "expected numeric constant");
8537 Parser.eatToEndOfStatement();
8541 Tag = CE->getValue();
8544 if (Parser.getTok().isNot(AsmToken::Comma)) {
8545 Error(Parser.getTok().getLoc(), "comma expected");
8546 Parser.eatToEndOfStatement();
8549 Parser.Lex(); // skip comma
8551 StringRef StringValue = "";
8552 bool IsStringValue = false;
8554 int64_t IntegerValue = 0;
8555 bool IsIntegerValue = false;
8557 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8558 IsStringValue = true;
8559 else if (Tag == ARMBuildAttrs::compatibility) {
8560 IsStringValue = true;
8561 IsIntegerValue = true;
8562 } else if (Tag < 32 || Tag % 2 == 0)
8563 IsIntegerValue = true;
8564 else if (Tag % 2 == 1)
8565 IsStringValue = true;
8567 llvm_unreachable("invalid tag type");
8569 if (IsIntegerValue) {
8570 const MCExpr *ValueExpr;
8571 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8572 if (Parser.parseExpression(ValueExpr)) {
8573 Parser.eatToEndOfStatement();
8577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8579 Error(ValueExprLoc, "expected numeric constant");
8580 Parser.eatToEndOfStatement();
8584 IntegerValue = CE->getValue();
8587 if (Tag == ARMBuildAttrs::compatibility) {
8588 if (Parser.getTok().isNot(AsmToken::Comma))
8589 IsStringValue = false;
8594 if (IsStringValue) {
8595 if (Parser.getTok().isNot(AsmToken::String)) {
8596 Error(Parser.getTok().getLoc(), "bad string constant");
8597 Parser.eatToEndOfStatement();
8601 StringValue = Parser.getTok().getStringContents();
8605 if (IsIntegerValue && IsStringValue) {
8606 assert(Tag == ARMBuildAttrs::compatibility);
8607 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8608 } else if (IsIntegerValue)
8609 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8610 else if (IsStringValue)
8611 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8615 /// parseDirectiveCPU
8617 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8618 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8619 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8623 /// parseDirectiveFPU
8625 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8626 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8628 unsigned ID = StringSwitch<unsigned>(FPU)
8629 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8630 #include "ARMFPUName.def"
8631 .Default(ARM::INVALID_FPU);
8633 if (ID == ARM::INVALID_FPU) {
8634 Error(L, "Unknown FPU name");
8638 getTargetStreamer().emitFPU(ID);
8642 /// parseDirectiveFnStart
8644 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8645 if (UC.hasFnStart()) {
8646 Error(L, ".fnstart starts before the end of previous one");
8647 UC.emitFnStartLocNotes();
8651 // Reset the unwind directives parser state
8654 getTargetStreamer().emitFnStart();
8656 UC.recordFnStart(L);
8660 /// parseDirectiveFnEnd
8662 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8663 // Check the ordering of unwind directives
8664 if (!UC.hasFnStart()) {
8665 Error(L, ".fnstart must precede .fnend directive");
8669 // Reset the unwind directives parser state
8670 getTargetStreamer().emitFnEnd();
8676 /// parseDirectiveCantUnwind
8678 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8679 UC.recordCantUnwind(L);
8681 // Check the ordering of unwind directives
8682 if (!UC.hasFnStart()) {
8683 Error(L, ".fnstart must precede .cantunwind directive");
8686 if (UC.hasHandlerData()) {
8687 Error(L, ".cantunwind can't be used with .handlerdata directive");
8688 UC.emitHandlerDataLocNotes();
8691 if (UC.hasPersonality()) {
8692 Error(L, ".cantunwind can't be used with .personality directive");
8693 UC.emitPersonalityLocNotes();
8697 getTargetStreamer().emitCantUnwind();
8701 /// parseDirectivePersonality
8702 /// ::= .personality name
8703 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8704 bool HasExistingPersonality = UC.hasPersonality();
8706 UC.recordPersonality(L);
8708 // Check the ordering of unwind directives
8709 if (!UC.hasFnStart()) {
8710 Error(L, ".fnstart must precede .personality directive");
8713 if (UC.cantUnwind()) {
8714 Error(L, ".personality can't be used with .cantunwind directive");
8715 UC.emitCantUnwindLocNotes();
8718 if (UC.hasHandlerData()) {
8719 Error(L, ".personality must precede .handlerdata directive");
8720 UC.emitHandlerDataLocNotes();
8723 if (HasExistingPersonality) {
8724 Parser.eatToEndOfStatement();
8725 Error(L, "multiple personality directives");
8726 UC.emitPersonalityLocNotes();
8730 // Parse the name of the personality routine
8731 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8732 Parser.eatToEndOfStatement();
8733 Error(L, "unexpected input in .personality directive.");
8736 StringRef Name(Parser.getTok().getIdentifier());
8739 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8740 getTargetStreamer().emitPersonality(PR);
8744 /// parseDirectiveHandlerData
8745 /// ::= .handlerdata
8746 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8747 UC.recordHandlerData(L);
8749 // Check the ordering of unwind directives
8750 if (!UC.hasFnStart()) {
8751 Error(L, ".fnstart must precede .personality directive");
8754 if (UC.cantUnwind()) {
8755 Error(L, ".handlerdata can't be used with .cantunwind directive");
8756 UC.emitCantUnwindLocNotes();
8760 getTargetStreamer().emitHandlerData();
8764 /// parseDirectiveSetFP
8765 /// ::= .setfp fpreg, spreg [, offset]
8766 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8767 // Check the ordering of unwind directives
8768 if (!UC.hasFnStart()) {
8769 Error(L, ".fnstart must precede .setfp directive");
8772 if (UC.hasHandlerData()) {
8773 Error(L, ".setfp must precede .handlerdata directive");
8778 SMLoc FPRegLoc = Parser.getTok().getLoc();
8779 int FPReg = tryParseRegister();
8781 Error(FPRegLoc, "frame pointer register expected");
8786 if (Parser.getTok().isNot(AsmToken::Comma)) {
8787 Error(Parser.getTok().getLoc(), "comma expected");
8790 Parser.Lex(); // skip comma
8793 SMLoc SPRegLoc = Parser.getTok().getLoc();
8794 int SPReg = tryParseRegister();
8796 Error(SPRegLoc, "stack pointer register expected");
8800 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8801 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8805 // Update the frame pointer register
8806 UC.saveFPReg(FPReg);
8810 if (Parser.getTok().is(AsmToken::Comma)) {
8811 Parser.Lex(); // skip comma
8813 if (Parser.getTok().isNot(AsmToken::Hash) &&
8814 Parser.getTok().isNot(AsmToken::Dollar)) {
8815 Error(Parser.getTok().getLoc(), "'#' expected");
8818 Parser.Lex(); // skip hash token.
8820 const MCExpr *OffsetExpr;
8821 SMLoc ExLoc = Parser.getTok().getLoc();
8823 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8824 Error(ExLoc, "malformed setfp offset");
8827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8829 Error(ExLoc, "setfp offset must be an immediate");
8833 Offset = CE->getValue();
8836 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8837 static_cast<unsigned>(SPReg), Offset);
8843 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8844 // Check the ordering of unwind directives
8845 if (!UC.hasFnStart()) {
8846 Error(L, ".fnstart must precede .pad directive");
8849 if (UC.hasHandlerData()) {
8850 Error(L, ".pad must precede .handlerdata directive");
8855 if (Parser.getTok().isNot(AsmToken::Hash) &&
8856 Parser.getTok().isNot(AsmToken::Dollar)) {
8857 Error(Parser.getTok().getLoc(), "'#' expected");
8860 Parser.Lex(); // skip hash token.
8862 const MCExpr *OffsetExpr;
8863 SMLoc ExLoc = Parser.getTok().getLoc();
8865 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8866 Error(ExLoc, "malformed pad offset");
8869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8871 Error(ExLoc, "pad offset must be an immediate");
8875 getTargetStreamer().emitPad(CE->getValue());
8879 /// parseDirectiveRegSave
8880 /// ::= .save { registers }
8881 /// ::= .vsave { registers }
8882 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8883 // Check the ordering of unwind directives
8884 if (!UC.hasFnStart()) {
8885 Error(L, ".fnstart must precede .save or .vsave directives");
8888 if (UC.hasHandlerData()) {
8889 Error(L, ".save or .vsave must precede .handlerdata directive");
8893 // RAII object to make sure parsed operands are deleted.
8894 struct CleanupObject {
8895 SmallVector<MCParsedAsmOperand *, 1> Operands;
8897 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8902 // Parse the register list
8903 if (parseRegisterList(CO.Operands))
8905 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8906 if (!IsVector && !Op->isRegList()) {
8907 Error(L, ".save expects GPR registers");
8910 if (IsVector && !Op->isDPRRegList()) {
8911 Error(L, ".vsave expects DPR registers");
8915 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8919 /// parseDirectiveInst
8920 /// ::= .inst opcode [, ...]
8921 /// ::= .inst.n opcode [, ...]
8922 /// ::= .inst.w opcode [, ...]
8923 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8935 Parser.eatToEndOfStatement();
8936 Error(Loc, "cannot determine Thumb instruction size, "
8937 "use inst.n/inst.w instead");
8942 Parser.eatToEndOfStatement();
8943 Error(Loc, "width suffixes are invalid in ARM mode");
8949 if (getLexer().is(AsmToken::EndOfStatement)) {
8950 Parser.eatToEndOfStatement();
8951 Error(Loc, "expected expression following directive");
8958 if (getParser().parseExpression(Expr)) {
8959 Error(Loc, "expected expression");
8963 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8965 Error(Loc, "expected constant expression");
8971 if (Value->getValue() > 0xffff) {
8972 Error(Loc, "inst.n operand is too big, use inst.w instead");
8977 if (Value->getValue() > 0xffffffff) {
8979 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8984 llvm_unreachable("only supported widths are 2 and 4");
8987 getTargetStreamer().emitInst(Value->getValue(), Suffix);
8989 if (getLexer().is(AsmToken::EndOfStatement))
8992 if (getLexer().isNot(AsmToken::Comma)) {
8993 Error(Loc, "unexpected token in directive");
9004 /// parseDirectiveLtorg
9005 /// ::= .ltorg | .pool
9006 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9007 getTargetStreamer().emitCurrentConstantPool();
9011 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9012 const MCSection *Section = getStreamer().getCurrentSection().first;
9014 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9015 TokError("unexpected token in directive");
9020 getStreamer().InitSections();
9021 Section = getStreamer().getCurrentSection().first;
9024 assert(Section && "must have section to emit alignment");
9025 if (Section->UseCodeAlign())
9026 getStreamer().EmitCodeAlignment(2);
9028 getStreamer().EmitValueToAlignment(2);
9033 /// parseDirectivePersonalityIndex
9034 /// ::= .personalityindex index
9035 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9036 bool HasExistingPersonality = UC.hasPersonality();
9038 UC.recordPersonalityIndex(L);
9040 if (!UC.hasFnStart()) {
9041 Parser.eatToEndOfStatement();
9042 Error(L, ".fnstart must precede .personalityindex directive");
9045 if (UC.cantUnwind()) {
9046 Parser.eatToEndOfStatement();
9047 Error(L, ".personalityindex cannot be used with .cantunwind");
9048 UC.emitCantUnwindLocNotes();
9051 if (UC.hasHandlerData()) {
9052 Parser.eatToEndOfStatement();
9053 Error(L, ".personalityindex must precede .handlerdata directive");
9054 UC.emitHandlerDataLocNotes();
9057 if (HasExistingPersonality) {
9058 Parser.eatToEndOfStatement();
9059 Error(L, "multiple personality directives");
9060 UC.emitPersonalityLocNotes();
9064 const MCExpr *IndexExpression;
9065 SMLoc IndexLoc = Parser.getTok().getLoc();
9066 if (Parser.parseExpression(IndexExpression)) {
9067 Parser.eatToEndOfStatement();
9071 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9073 Parser.eatToEndOfStatement();
9074 Error(IndexLoc, "index must be a constant number");
9077 if (CE->getValue() < 0 ||
9078 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9079 Parser.eatToEndOfStatement();
9080 Error(IndexLoc, "personality routine index should be in range [0-3]");
9084 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9088 /// parseDirectiveUnwindRaw
9089 /// ::= .unwind_raw offset, opcode [, opcode...]
9090 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9091 if (!UC.hasFnStart()) {
9092 Parser.eatToEndOfStatement();
9093 Error(L, ".fnstart must precede .unwind_raw directives");
9097 int64_t StackOffset;
9099 const MCExpr *OffsetExpr;
9100 SMLoc OffsetLoc = getLexer().getLoc();
9101 if (getLexer().is(AsmToken::EndOfStatement) ||
9102 getParser().parseExpression(OffsetExpr)) {
9103 Error(OffsetLoc, "expected expression");
9104 Parser.eatToEndOfStatement();
9108 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9110 Error(OffsetLoc, "offset must be a constant");
9111 Parser.eatToEndOfStatement();
9115 StackOffset = CE->getValue();
9117 if (getLexer().isNot(AsmToken::Comma)) {
9118 Error(getLexer().getLoc(), "expected comma");
9119 Parser.eatToEndOfStatement();
9124 SmallVector<uint8_t, 16> Opcodes;
9128 SMLoc OpcodeLoc = getLexer().getLoc();
9129 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9130 Error(OpcodeLoc, "expected opcode expression");
9131 Parser.eatToEndOfStatement();
9135 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9137 Error(OpcodeLoc, "opcode value must be a constant");
9138 Parser.eatToEndOfStatement();
9142 const int64_t Opcode = OC->getValue();
9143 if (Opcode & ~0xff) {
9144 Error(OpcodeLoc, "invalid opcode");
9145 Parser.eatToEndOfStatement();
9149 Opcodes.push_back(uint8_t(Opcode));
9151 if (getLexer().is(AsmToken::EndOfStatement))
9154 if (getLexer().isNot(AsmToken::Comma)) {
9155 Error(getLexer().getLoc(), "unexpected token in directive");
9156 Parser.eatToEndOfStatement();
9163 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9169 /// parseDirectiveTLSDescSeq
9170 /// ::= .tlsdescseq tls-variable
9171 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9172 if (getLexer().isNot(AsmToken::Identifier)) {
9173 TokError("expected variable after '.tlsdescseq' directive");
9174 Parser.eatToEndOfStatement();
9178 const MCSymbolRefExpr *SRE =
9179 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9180 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9183 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9184 Error(Parser.getTok().getLoc(), "unexpected token");
9185 Parser.eatToEndOfStatement();
9189 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9193 /// parseDirectiveMovSP
9194 /// ::= .movsp reg [, #offset]
9195 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9196 if (!UC.hasFnStart()) {
9197 Parser.eatToEndOfStatement();
9198 Error(L, ".fnstart must precede .movsp directives");
9201 if (UC.getFPReg() != ARM::SP) {
9202 Parser.eatToEndOfStatement();
9203 Error(L, "unexpected .movsp directive");
9207 SMLoc SPRegLoc = Parser.getTok().getLoc();
9208 int SPReg = tryParseRegister();
9210 Parser.eatToEndOfStatement();
9211 Error(SPRegLoc, "register expected");
9215 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9216 Parser.eatToEndOfStatement();
9217 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9222 if (Parser.getTok().is(AsmToken::Comma)) {
9225 if (Parser.getTok().isNot(AsmToken::Hash)) {
9226 Error(Parser.getTok().getLoc(), "expected #constant");
9227 Parser.eatToEndOfStatement();
9232 const MCExpr *OffsetExpr;
9233 SMLoc OffsetLoc = Parser.getTok().getLoc();
9234 if (Parser.parseExpression(OffsetExpr)) {
9235 Parser.eatToEndOfStatement();
9236 Error(OffsetLoc, "malformed offset expression");
9240 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9242 Parser.eatToEndOfStatement();
9243 Error(OffsetLoc, "offset must be an immediate constant");
9247 Offset = CE->getValue();
9250 getTargetStreamer().emitMovSP(SPReg, Offset);
9251 UC.saveFPReg(SPReg);
9256 /// parseDirectiveObjectArch
9257 /// ::= .object_arch name
9258 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9259 if (getLexer().isNot(AsmToken::Identifier)) {
9260 Error(getLexer().getLoc(), "unexpected token");
9261 Parser.eatToEndOfStatement();
9265 StringRef Arch = Parser.getTok().getString();
9266 SMLoc ArchLoc = Parser.getTok().getLoc();
9269 unsigned ID = StringSwitch<unsigned>(Arch)
9270 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9271 .Case(NAME, ARM::ID)
9272 #define ARM_ARCH_ALIAS(NAME, ID) \
9273 .Case(NAME, ARM::ID)
9274 #include "MCTargetDesc/ARMArchName.def"
9275 #undef ARM_ARCH_NAME
9276 #undef ARM_ARCH_ALIAS
9277 .Default(ARM::INVALID_ARCH);
9279 if (ID == ARM::INVALID_ARCH) {
9280 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9281 Parser.eatToEndOfStatement();
9285 getTargetStreamer().emitObjectArch(ID);
9287 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9288 Error(getLexer().getLoc(), "unexpected token");
9289 Parser.eatToEndOfStatement();
9295 /// parseDirectiveAlign
9297 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9298 // NOTE: if this is not the end of the statement, fall back to the target
9299 // agnostic handling for this directive which will correctly handle this.
9300 if (getLexer().isNot(AsmToken::EndOfStatement))
9303 // '.align' is target specifically handled to mean 2**2 byte alignment.
9304 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9305 getStreamer().EmitCodeAlignment(4, 0);
9307 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9312 /// parseDirectiveThumbSet
9313 /// ::= .thumb_set name, value
9314 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9316 if (Parser.parseIdentifier(Name)) {
9317 TokError("expected identifier after '.thumb_set'");
9318 Parser.eatToEndOfStatement();
9322 if (getLexer().isNot(AsmToken::Comma)) {
9323 TokError("expected comma after name '" + Name + "'");
9324 Parser.eatToEndOfStatement();
9329 const MCExpr *Value;
9330 if (Parser.parseExpression(Value)) {
9331 TokError("missing expression");
9332 Parser.eatToEndOfStatement();
9336 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9337 TokError("unexpected token");
9338 Parser.eatToEndOfStatement();
9343 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9344 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Value)) {
9345 MCSymbol *Sym = getContext().LookupSymbol(SRE->getSymbol().getName());
9346 if (!Sym->isDefined()) {
9347 getStreamer().EmitSymbolAttribute(Sym, MCSA_Global);
9348 getStreamer().EmitAssignment(Alias, Value);
9352 const MCObjectFileInfo::Environment Format =
9353 getContext().getObjectFileInfo()->getObjectFileType();
9355 case MCObjectFileInfo::IsCOFF: {
9356 char Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
9357 getStreamer().EmitCOFFSymbolType(Type);
9358 // .set values are always local in COFF
9359 getStreamer().EmitSymbolAttribute(Alias, MCSA_Local);
9362 case MCObjectFileInfo::IsELF:
9363 getStreamer().EmitSymbolAttribute(Alias, MCSA_ELF_TypeFunction);
9365 case MCObjectFileInfo::IsMachO:
9370 // FIXME: set the function as being a thumb function via the assembler
9371 getStreamer().EmitThumbFunc(Alias);
9372 getStreamer().EmitAssignment(Alias, Value);
9377 /// Force static initialization.
9378 extern "C" void LLVMInitializeARMAsmParser() {
9379 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9380 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9381 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9382 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9385 #define GET_REGISTER_MATCHER
9386 #define GET_SUBTARGET_FEATURE_NAME
9387 #define GET_MATCHER_IMPLEMENTATION
9388 #include "ARMGenAsmMatcher.inc"
9390 static const struct ExtMapEntry {
9391 const char *Extension;
9392 const unsigned ArchCheck;
9393 const uint64_t Features;
9395 { "crc", Feature_HasV8, ARM::FeatureCRC },
9396 { "crypto", Feature_HasV8,
9397 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9398 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9399 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9400 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9401 // FIXME: iWMMXT not supported
9402 { "iwmmxt", Feature_None, 0 },
9403 // FIXME: iWMMXT2 not supported
9404 { "iwmmxt2", Feature_None, 0 },
9405 // FIXME: Maverick not supported
9406 { "maverick", Feature_None, 0 },
9407 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9408 // FIXME: ARMv6-m OS Extensions feature not checked
9409 { "os", Feature_None, 0 },
9410 // FIXME: Also available in ARMv6-K
9411 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9412 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9413 // FIXME: Only available in A-class, isel not predicated
9414 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9415 // FIXME: xscale not supported
9416 { "xscale", Feature_None, 0 },
9419 /// parseDirectiveArchExtension
9420 /// ::= .arch_extension [no]feature
9421 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9422 if (getLexer().isNot(AsmToken::Identifier)) {
9423 Error(getLexer().getLoc(), "unexpected token");
9424 Parser.eatToEndOfStatement();
9428 StringRef Extension = Parser.getTok().getString();
9429 SMLoc ExtLoc = Parser.getTok().getLoc();
9432 bool EnableFeature = true;
9433 if (Extension.startswith_lower("no")) {
9434 EnableFeature = false;
9435 Extension = Extension.substr(2);
9438 for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) {
9439 if (Extensions[EI].Extension != Extension)
9442 unsigned FB = getAvailableFeatures();
9443 if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) {
9444 Error(ExtLoc, "architectural extension '" + Extension + "' is not "
9445 "allowed for the current base architecture");
9449 if (!Extensions[EI].Features)
9450 report_fatal_error("unsupported architectural extension: " + Extension);
9453 FB |= ComputeAvailableFeatures(Extensions[EI].Features);
9455 FB &= ~ComputeAvailableFeatures(Extensions[EI].Features);
9457 setAvailableFeatures(FB);
9461 Error(ExtLoc, "unknown architectural extension: " + Extension);
9462 Parser.eatToEndOfStatement();
9466 // Define this matcher function after the auto-generated include so we
9467 // have the match class enum definitions.
9468 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
9470 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
9471 // If the kind is a token for a literal immediate, check if our asm
9472 // operand matches. This is for InstAliases which have a fixed-value
9473 // immediate in the syntax.
9478 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()))
9479 if (CE->getValue() == 0)
9480 return Match_Success;
9484 const MCExpr *SOExpr = Op->getImm();
9486 if (!SOExpr->EvaluateAsAbsolute(Value))
9487 return Match_Success;
9488 assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
9489 "expression value must be representiable in 32 bits");
9494 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg()))
9495 return Match_Success;
9498 return Match_InvalidOperand;