1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCTargetAsmParser.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/OwningPtr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCParser/MCAsmLexer.h"
28 #include "llvm/MC/MCParser/MCAsmParser.h"
29 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/Support/ELF.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/SourceMgr.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
45 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
47 class ARMAsmParser : public MCTargetAsmParser {
50 const MCRegisterInfo *MRI;
52 // Unwind directives state
58 void resetUnwindDirectiveParserState() {
60 CantUnwindLoc = SMLoc();
61 PersonalityLoc = SMLoc();
62 HandlerDataLoc = SMLoc();
66 // Map of register aliases registers via the .req directive.
67 StringMap<unsigned> RegisterReqs;
70 ARMCC::CondCodes Cond; // Condition for IT block.
71 unsigned Mask:4; // Condition mask for instructions.
72 // Starting at first 1 (from lsb).
73 // '1' condition as indicated in IT.
74 // '0' inverse of condition (else).
75 // Count of instructions in IT block is
76 // 4 - trailingzeroes(mask)
78 bool FirstCond; // Explicit flag for when we're parsing the
79 // First instruction in the IT block. It's
80 // implied in the mask, so needs special
83 unsigned CurPosition; // Current position in parsing of IT
84 // block. In range [0,3]. Initialized
85 // according to count of instructions in block.
86 // ~0U if no active IT block.
88 bool inITBlock() { return ITState.CurPosition != ~0U;}
89 void forwardITPosition() {
90 if (!inITBlock()) return;
91 // Move to the next instruction in the IT block, if there is one. If not,
92 // mark the block as done.
93 unsigned TZ = countTrailingZeros(ITState.Mask);
94 if (++ITState.CurPosition == 5 - TZ)
95 ITState.CurPosition = ~0U; // Done with the IT block after this.
99 MCAsmParser &getParser() const { return Parser; }
100 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
102 bool Warning(SMLoc L, const Twine &Msg,
103 ArrayRef<SMRange> Ranges = None) {
104 return Parser.Warning(L, Msg, Ranges);
106 bool Error(SMLoc L, const Twine &Msg,
107 ArrayRef<SMRange> Ranges = None) {
108 return Parser.Error(L, Msg, Ranges);
111 int tryParseRegister();
112 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
113 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
114 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
115 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
116 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
117 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
118 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
119 unsigned &ShiftAmount);
120 bool parseDirectiveWord(unsigned Size, SMLoc L);
121 bool parseDirectiveThumb(SMLoc L);
122 bool parseDirectiveARM(SMLoc L);
123 bool parseDirectiveThumbFunc(SMLoc L);
124 bool parseDirectiveCode(SMLoc L);
125 bool parseDirectiveSyntax(SMLoc L);
126 bool parseDirectiveReq(StringRef Name, SMLoc L);
127 bool parseDirectiveUnreq(SMLoc L);
128 bool parseDirectiveArch(SMLoc L);
129 bool parseDirectiveEabiAttr(SMLoc L);
130 bool parseDirectiveFnStart(SMLoc L);
131 bool parseDirectiveFnEnd(SMLoc L);
132 bool parseDirectiveCantUnwind(SMLoc L);
133 bool parseDirectivePersonality(SMLoc L);
134 bool parseDirectiveHandlerData(SMLoc L);
135 bool parseDirectiveSetFP(SMLoc L);
136 bool parseDirectivePad(SMLoc L);
137 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
139 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
140 bool &CarrySetting, unsigned &ProcessorIMod,
142 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
143 bool &CanAcceptPredicationCode);
145 bool isThumb() const {
146 // FIXME: Can tablegen auto-generate this?
147 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
149 bool isThumbOne() const {
150 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
152 bool isThumbTwo() const {
153 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
155 bool hasThumb() const {
156 return STI.getFeatureBits() & ARM::HasV4TOps;
158 bool hasV6Ops() const {
159 return STI.getFeatureBits() & ARM::HasV6Ops;
161 bool hasV7Ops() const {
162 return STI.getFeatureBits() & ARM::HasV7Ops;
164 bool hasV8Ops() const {
165 return STI.getFeatureBits() & ARM::HasV8Ops;
167 bool hasARM() const {
168 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
172 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
173 setAvailableFeatures(FB);
175 bool isMClass() const {
176 return STI.getFeatureBits() & ARM::FeatureMClass;
179 /// @name Auto-generated Match Functions
182 #define GET_ASSEMBLER_HEADER
183 #include "ARMGenAsmMatcher.inc"
187 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
188 OperandMatchResultTy parseCoprocNumOperand(
189 SmallVectorImpl<MCParsedAsmOperand*>&);
190 OperandMatchResultTy parseCoprocRegOperand(
191 SmallVectorImpl<MCParsedAsmOperand*>&);
192 OperandMatchResultTy parseCoprocOptionOperand(
193 SmallVectorImpl<MCParsedAsmOperand*>&);
194 OperandMatchResultTy parseMemBarrierOptOperand(
195 SmallVectorImpl<MCParsedAsmOperand*>&);
196 OperandMatchResultTy parseInstSyncBarrierOptOperand(
197 SmallVectorImpl<MCParsedAsmOperand*>&);
198 OperandMatchResultTy parseProcIFlagsOperand(
199 SmallVectorImpl<MCParsedAsmOperand*>&);
200 OperandMatchResultTy parseMSRMaskOperand(
201 SmallVectorImpl<MCParsedAsmOperand*>&);
202 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
203 StringRef Op, int Low, int High);
204 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
205 return parsePKHImm(O, "lsl", 0, 31);
207 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
208 return parsePKHImm(O, "asr", 1, 32);
210 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
211 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
212 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
213 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
214 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
215 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
216 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
217 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
218 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
221 // Asm Match Converter Methods
222 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
223 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
224 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
225 const SmallVectorImpl<MCParsedAsmOperand*> &);
226 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
227 const SmallVectorImpl<MCParsedAsmOperand*> &);
228 void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
229 const SmallVectorImpl<MCParsedAsmOperand*> &);
230 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
231 const SmallVectorImpl<MCParsedAsmOperand*> &);
232 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
233 const SmallVectorImpl<MCParsedAsmOperand*> &);
234 void cvtStWriteBackRegAddrMode2(MCInst &Inst,
235 const SmallVectorImpl<MCParsedAsmOperand*> &);
236 void cvtStWriteBackRegAddrMode3(MCInst &Inst,
237 const SmallVectorImpl<MCParsedAsmOperand*> &);
238 void cvtLdExtTWriteBackImm(MCInst &Inst,
239 const SmallVectorImpl<MCParsedAsmOperand*> &);
240 void cvtLdExtTWriteBackReg(MCInst &Inst,
241 const SmallVectorImpl<MCParsedAsmOperand*> &);
242 void cvtStExtTWriteBackImm(MCInst &Inst,
243 const SmallVectorImpl<MCParsedAsmOperand*> &);
244 void cvtStExtTWriteBackReg(MCInst &Inst,
245 const SmallVectorImpl<MCParsedAsmOperand*> &);
246 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
247 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
248 void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
249 const SmallVectorImpl<MCParsedAsmOperand*> &);
250 void cvtThumbMultiply(MCInst &Inst,
251 const SmallVectorImpl<MCParsedAsmOperand*> &);
252 void cvtVLDwbFixed(MCInst &Inst,
253 const SmallVectorImpl<MCParsedAsmOperand*> &);
254 void cvtVLDwbRegister(MCInst &Inst,
255 const SmallVectorImpl<MCParsedAsmOperand*> &);
256 void cvtVSTwbFixed(MCInst &Inst,
257 const SmallVectorImpl<MCParsedAsmOperand*> &);
258 void cvtVSTwbRegister(MCInst &Inst,
259 const SmallVectorImpl<MCParsedAsmOperand*> &);
260 bool validateInstruction(MCInst &Inst,
261 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
262 bool processInstruction(MCInst &Inst,
263 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
264 bool shouldOmitCCOutOperand(StringRef Mnemonic,
265 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
268 enum ARMMatchResultTy {
269 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
270 Match_RequiresNotITBlock,
272 Match_RequiresThumb2,
273 #define GET_OPERAND_DIAGNOSTIC_TYPES
274 #include "ARMGenAsmMatcher.inc"
278 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
279 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) {
280 MCAsmParserExtension::Initialize(_Parser);
282 // Cache the MCRegisterInfo.
283 MRI = getContext().getRegisterInfo();
285 // Initialize the set of available features.
286 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
288 // Not in an ITBlock to start with.
289 ITState.CurPosition = ~0U;
291 // Set ELF header flags.
292 // FIXME: This should eventually end up somewhere else where more
293 // intelligent flag decisions can be made. For now we are just maintaining
294 // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
295 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
296 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
299 // Implementation of the MCTargetAsmParser interface:
300 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
301 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
303 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
304 bool ParseDirective(AsmToken DirectiveID);
306 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
307 unsigned checkTargetMatchPredicate(MCInst &Inst);
309 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
310 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
311 MCStreamer &Out, unsigned &ErrorInfo,
312 bool MatchingInlineAsm);
314 } // end anonymous namespace
318 /// ARMOperand - Instances of this class represent a parsed ARM machine
320 class ARMOperand : public MCParsedAsmOperand {
330 k_InstSyncBarrierOpt,
341 k_VectorListAllLanes,
347 k_BitfieldDescriptor,
351 SMLoc StartLoc, EndLoc;
352 SmallVector<unsigned, 8> Registers;
355 ARMCC::CondCodes Val;
362 struct CoprocOptionOp {
375 ARM_ISB::InstSyncBOpt Val;
379 ARM_PROC::IFlags Val;
395 // A vector register list is a sequential list of 1 to 4 registers.
396 struct VectorListOp {
403 struct VectorIndexOp {
411 /// Combined record for all forms of ARM address expressions.
414 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
416 const MCConstantExpr *OffsetImm; // Offset immediate value
417 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
418 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
419 unsigned ShiftImm; // shift for OffsetReg.
420 unsigned Alignment; // 0 = no alignment specified
421 // n = alignment in bytes (2, 4, 8, 16, or 32)
422 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
425 struct PostIdxRegOp {
428 ARM_AM::ShiftOpc ShiftTy;
432 struct ShifterImmOp {
437 struct RegShiftedRegOp {
438 ARM_AM::ShiftOpc ShiftTy;
444 struct RegShiftedImmOp {
445 ARM_AM::ShiftOpc ShiftTy;
462 struct CoprocOptionOp CoprocOption;
463 struct MBOptOp MBOpt;
464 struct ISBOptOp ISBOpt;
465 struct ITMaskOp ITMask;
466 struct IFlagsOp IFlags;
467 struct MMaskOp MMask;
470 struct VectorListOp VectorList;
471 struct VectorIndexOp VectorIndex;
473 struct MemoryOp Memory;
474 struct PostIdxRegOp PostIdxReg;
475 struct ShifterImmOp ShifterImm;
476 struct RegShiftedRegOp RegShiftedReg;
477 struct RegShiftedImmOp RegShiftedImm;
478 struct RotImmOp RotImm;
479 struct BitfieldOp Bitfield;
482 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
484 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
486 StartLoc = o.StartLoc;
503 case k_DPRRegisterList:
504 case k_SPRRegisterList:
505 Registers = o.Registers;
508 case k_VectorListAllLanes:
509 case k_VectorListIndexed:
510 VectorList = o.VectorList;
517 CoprocOption = o.CoprocOption;
522 case k_MemBarrierOpt:
525 case k_InstSyncBarrierOpt:
530 case k_PostIndexRegister:
531 PostIdxReg = o.PostIdxReg;
539 case k_ShifterImmediate:
540 ShifterImm = o.ShifterImm;
542 case k_ShiftedRegister:
543 RegShiftedReg = o.RegShiftedReg;
545 case k_ShiftedImmediate:
546 RegShiftedImm = o.RegShiftedImm;
548 case k_RotateImmediate:
551 case k_BitfieldDescriptor:
552 Bitfield = o.Bitfield;
555 VectorIndex = o.VectorIndex;
560 /// getStartLoc - Get the location of the first token of this operand.
561 SMLoc getStartLoc() const { return StartLoc; }
562 /// getEndLoc - Get the location of the last token of this operand.
563 SMLoc getEndLoc() const { return EndLoc; }
564 /// getLocRange - Get the range between the first and last token of this
566 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
568 ARMCC::CondCodes getCondCode() const {
569 assert(Kind == k_CondCode && "Invalid access!");
573 unsigned getCoproc() const {
574 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
578 StringRef getToken() const {
579 assert(Kind == k_Token && "Invalid access!");
580 return StringRef(Tok.Data, Tok.Length);
583 unsigned getReg() const {
584 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
588 const SmallVectorImpl<unsigned> &getRegList() const {
589 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
590 Kind == k_SPRRegisterList) && "Invalid access!");
594 const MCExpr *getImm() const {
595 assert(isImm() && "Invalid access!");
599 unsigned getVectorIndex() const {
600 assert(Kind == k_VectorIndex && "Invalid access!");
601 return VectorIndex.Val;
604 ARM_MB::MemBOpt getMemBarrierOpt() const {
605 assert(Kind == k_MemBarrierOpt && "Invalid access!");
609 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
610 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
614 ARM_PROC::IFlags getProcIFlags() const {
615 assert(Kind == k_ProcIFlags && "Invalid access!");
619 unsigned getMSRMask() const {
620 assert(Kind == k_MSRMask && "Invalid access!");
624 bool isCoprocNum() const { return Kind == k_CoprocNum; }
625 bool isCoprocReg() const { return Kind == k_CoprocReg; }
626 bool isCoprocOption() const { return Kind == k_CoprocOption; }
627 bool isCondCode() const { return Kind == k_CondCode; }
628 bool isCCOut() const { return Kind == k_CCOut; }
629 bool isITMask() const { return Kind == k_ITCondMask; }
630 bool isITCondCode() const { return Kind == k_CondCode; }
631 bool isImm() const { return Kind == k_Immediate; }
632 // checks whether this operand is an unsigned offset which fits is a field
633 // of specified width and scaled by a specific number of bits
634 template<unsigned width, unsigned scale>
635 bool isUnsignedOffset() const {
636 if (!isImm()) return false;
637 if (dyn_cast<MCSymbolRefExpr>(Imm.Val)) return true;
638 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
639 int64_t Val = CE->getValue();
640 int64_t Align = 1LL << scale;
641 int64_t Max = Align * ((1LL << width) - 1);
642 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
646 bool isFPImm() const {
647 if (!isImm()) return false;
648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
649 if (!CE) return false;
650 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
653 bool isFBits16() const {
654 if (!isImm()) return false;
655 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
656 if (!CE) return false;
657 int64_t Value = CE->getValue();
658 return Value >= 0 && Value <= 16;
660 bool isFBits32() const {
661 if (!isImm()) return false;
662 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
663 if (!CE) return false;
664 int64_t Value = CE->getValue();
665 return Value >= 1 && Value <= 32;
667 bool isImm8s4() const {
668 if (!isImm()) return false;
669 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
670 if (!CE) return false;
671 int64_t Value = CE->getValue();
672 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
674 bool isImm0_4() const {
675 if (!isImm()) return false;
676 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
677 if (!CE) return false;
678 int64_t Value = CE->getValue();
679 return Value >= 0 && Value < 5;
681 bool isImm0_1020s4() const {
682 if (!isImm()) return false;
683 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
684 if (!CE) return false;
685 int64_t Value = CE->getValue();
686 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
688 bool isImm0_508s4() const {
689 if (!isImm()) return false;
690 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
691 if (!CE) return false;
692 int64_t Value = CE->getValue();
693 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
695 bool isImm0_508s4Neg() const {
696 if (!isImm()) return false;
697 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
698 if (!CE) return false;
699 int64_t Value = -CE->getValue();
700 // explicitly exclude zero. we want that to use the normal 0_508 version.
701 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
703 bool isImm0_255() const {
704 if (!isImm()) return false;
705 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
706 if (!CE) return false;
707 int64_t Value = CE->getValue();
708 return Value >= 0 && Value < 256;
710 bool isImm0_4095() const {
711 if (!isImm()) return false;
712 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
713 if (!CE) return false;
714 int64_t Value = CE->getValue();
715 return Value >= 0 && Value < 4096;
717 bool isImm0_4095Neg() const {
718 if (!isImm()) return false;
719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
720 if (!CE) return false;
721 int64_t Value = -CE->getValue();
722 return Value > 0 && Value < 4096;
724 bool isImm0_1() const {
725 if (!isImm()) return false;
726 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
727 if (!CE) return false;
728 int64_t Value = CE->getValue();
729 return Value >= 0 && Value < 2;
731 bool isImm0_3() const {
732 if (!isImm()) return false;
733 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
734 if (!CE) return false;
735 int64_t Value = CE->getValue();
736 return Value >= 0 && Value < 4;
738 bool isImm0_7() const {
739 if (!isImm()) return false;
740 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
741 if (!CE) return false;
742 int64_t Value = CE->getValue();
743 return Value >= 0 && Value < 8;
745 bool isImm0_15() const {
746 if (!isImm()) return false;
747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
748 if (!CE) return false;
749 int64_t Value = CE->getValue();
750 return Value >= 0 && Value < 16;
752 bool isImm0_31() const {
753 if (!isImm()) return false;
754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755 if (!CE) return false;
756 int64_t Value = CE->getValue();
757 return Value >= 0 && Value < 32;
759 bool isImm0_63() const {
760 if (!isImm()) return false;
761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762 if (!CE) return false;
763 int64_t Value = CE->getValue();
764 return Value >= 0 && Value < 64;
766 bool isImm8() const {
767 if (!isImm()) return false;
768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
769 if (!CE) return false;
770 int64_t Value = CE->getValue();
773 bool isImm16() const {
774 if (!isImm()) return false;
775 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
776 if (!CE) return false;
777 int64_t Value = CE->getValue();
780 bool isImm32() const {
781 if (!isImm()) return false;
782 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
783 if (!CE) return false;
784 int64_t Value = CE->getValue();
787 bool isShrImm8() const {
788 if (!isImm()) return false;
789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790 if (!CE) return false;
791 int64_t Value = CE->getValue();
792 return Value > 0 && Value <= 8;
794 bool isShrImm16() const {
795 if (!isImm()) return false;
796 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
797 if (!CE) return false;
798 int64_t Value = CE->getValue();
799 return Value > 0 && Value <= 16;
801 bool isShrImm32() const {
802 if (!isImm()) return false;
803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804 if (!CE) return false;
805 int64_t Value = CE->getValue();
806 return Value > 0 && Value <= 32;
808 bool isShrImm64() const {
809 if (!isImm()) return false;
810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
811 if (!CE) return false;
812 int64_t Value = CE->getValue();
813 return Value > 0 && Value <= 64;
815 bool isImm1_7() const {
816 if (!isImm()) return false;
817 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818 if (!CE) return false;
819 int64_t Value = CE->getValue();
820 return Value > 0 && Value < 8;
822 bool isImm1_15() const {
823 if (!isImm()) return false;
824 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825 if (!CE) return false;
826 int64_t Value = CE->getValue();
827 return Value > 0 && Value < 16;
829 bool isImm1_31() const {
830 if (!isImm()) return false;
831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832 if (!CE) return false;
833 int64_t Value = CE->getValue();
834 return Value > 0 && Value < 32;
836 bool isImm1_16() const {
837 if (!isImm()) return false;
838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839 if (!CE) return false;
840 int64_t Value = CE->getValue();
841 return Value > 0 && Value < 17;
843 bool isImm1_32() const {
844 if (!isImm()) return false;
845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846 if (!CE) return false;
847 int64_t Value = CE->getValue();
848 return Value > 0 && Value < 33;
850 bool isImm0_32() const {
851 if (!isImm()) return false;
852 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853 if (!CE) return false;
854 int64_t Value = CE->getValue();
855 return Value >= 0 && Value < 33;
857 bool isImm0_65535() const {
858 if (!isImm()) return false;
859 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
860 if (!CE) return false;
861 int64_t Value = CE->getValue();
862 return Value >= 0 && Value < 65536;
864 bool isImm0_65535Expr() const {
865 if (!isImm()) return false;
866 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
867 // If it's not a constant expression, it'll generate a fixup and be
869 if (!CE) return true;
870 int64_t Value = CE->getValue();
871 return Value >= 0 && Value < 65536;
873 bool isImm24bit() const {
874 if (!isImm()) return false;
875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
876 if (!CE) return false;
877 int64_t Value = CE->getValue();
878 return Value >= 0 && Value <= 0xffffff;
880 bool isImmThumbSR() const {
881 if (!isImm()) return false;
882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
883 if (!CE) return false;
884 int64_t Value = CE->getValue();
885 return Value > 0 && Value < 33;
887 bool isPKHLSLImm() const {
888 if (!isImm()) return false;
889 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
890 if (!CE) return false;
891 int64_t Value = CE->getValue();
892 return Value >= 0 && Value < 32;
894 bool isPKHASRImm() const {
895 if (!isImm()) return false;
896 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
897 if (!CE) return false;
898 int64_t Value = CE->getValue();
899 return Value > 0 && Value <= 32;
901 bool isAdrLabel() const {
902 // If we have an immediate that's not a constant, treat it as a label
903 // reference needing a fixup. If it is a constant, but it can't fit
904 // into shift immediate encoding, we reject it.
905 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
906 else return (isARMSOImm() || isARMSOImmNeg());
908 bool isARMSOImm() const {
909 if (!isImm()) return false;
910 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
911 if (!CE) return false;
912 int64_t Value = CE->getValue();
913 return ARM_AM::getSOImmVal(Value) != -1;
915 bool isARMSOImmNot() const {
916 if (!isImm()) return false;
917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
918 if (!CE) return false;
919 int64_t Value = CE->getValue();
920 return ARM_AM::getSOImmVal(~Value) != -1;
922 bool isARMSOImmNeg() const {
923 if (!isImm()) return false;
924 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
925 if (!CE) return false;
926 int64_t Value = CE->getValue();
927 // Only use this when not representable as a plain so_imm.
928 return ARM_AM::getSOImmVal(Value) == -1 &&
929 ARM_AM::getSOImmVal(-Value) != -1;
931 bool isT2SOImm() const {
932 if (!isImm()) return false;
933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
934 if (!CE) return false;
935 int64_t Value = CE->getValue();
936 return ARM_AM::getT2SOImmVal(Value) != -1;
938 bool isT2SOImmNot() const {
939 if (!isImm()) return false;
940 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941 if (!CE) return false;
942 int64_t Value = CE->getValue();
943 return ARM_AM::getT2SOImmVal(~Value) != -1;
945 bool isT2SOImmNeg() const {
946 if (!isImm()) return false;
947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948 if (!CE) return false;
949 int64_t Value = CE->getValue();
950 // Only use this when not representable as a plain so_imm.
951 return ARM_AM::getT2SOImmVal(Value) == -1 &&
952 ARM_AM::getT2SOImmVal(-Value) != -1;
954 bool isSetEndImm() const {
955 if (!isImm()) return false;
956 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
957 if (!CE) return false;
958 int64_t Value = CE->getValue();
959 return Value == 1 || Value == 0;
961 bool isReg() const { return Kind == k_Register; }
962 bool isRegList() const { return Kind == k_RegisterList; }
963 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
964 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
965 bool isToken() const { return Kind == k_Token; }
966 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
967 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
968 bool isMem() const { return Kind == k_Memory; }
969 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
970 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
971 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
972 bool isRotImm() const { return Kind == k_RotateImmediate; }
973 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
974 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
975 bool isPostIdxReg() const {
976 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
978 bool isMemNoOffset(bool alignOK = false) const {
981 // No offset of any kind.
982 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
983 (alignOK || Memory.Alignment == 0);
985 bool isMemPCRelImm12() const {
986 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
988 // Base register must be PC.
989 if (Memory.BaseRegNum != ARM::PC)
991 // Immediate offset in range [-4095, 4095].
992 if (!Memory.OffsetImm) return true;
993 int64_t Val = Memory.OffsetImm->getValue();
994 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
996 bool isAlignedMemory() const {
997 return isMemNoOffset(true);
999 bool isAddrMode2() const {
1000 if (!isMem() || Memory.Alignment != 0) return false;
1001 // Check for register offset.
1002 if (Memory.OffsetRegNum) return true;
1003 // Immediate offset in range [-4095, 4095].
1004 if (!Memory.OffsetImm) return true;
1005 int64_t Val = Memory.OffsetImm->getValue();
1006 return Val > -4096 && Val < 4096;
1008 bool isAM2OffsetImm() const {
1009 if (!isImm()) return false;
1010 // Immediate offset in range [-4095, 4095].
1011 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1012 if (!CE) return false;
1013 int64_t Val = CE->getValue();
1014 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1016 bool isAddrMode3() const {
1017 // If we have an immediate that's not a constant, treat it as a label
1018 // reference needing a fixup. If it is a constant, it's something else
1019 // and we reject it.
1020 if (isImm() && !isa<MCConstantExpr>(getImm()))
1022 if (!isMem() || Memory.Alignment != 0) return false;
1023 // No shifts are legal for AM3.
1024 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1025 // Check for register offset.
1026 if (Memory.OffsetRegNum) return true;
1027 // Immediate offset in range [-255, 255].
1028 if (!Memory.OffsetImm) return true;
1029 int64_t Val = Memory.OffsetImm->getValue();
1030 // The #-0 offset is encoded as INT32_MIN, and we have to check
1032 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1034 bool isAM3Offset() const {
1035 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1037 if (Kind == k_PostIndexRegister)
1038 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1039 // Immediate offset in range [-255, 255].
1040 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041 if (!CE) return false;
1042 int64_t Val = CE->getValue();
1043 // Special case, #-0 is INT32_MIN.
1044 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1046 bool isAddrMode5() const {
1047 // If we have an immediate that's not a constant, treat it as a label
1048 // reference needing a fixup. If it is a constant, it's something else
1049 // and we reject it.
1050 if (isImm() && !isa<MCConstantExpr>(getImm()))
1052 if (!isMem() || Memory.Alignment != 0) return false;
1053 // Check for register offset.
1054 if (Memory.OffsetRegNum) return false;
1055 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1056 if (!Memory.OffsetImm) return true;
1057 int64_t Val = Memory.OffsetImm->getValue();
1058 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1061 bool isMemTBB() const {
1062 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1063 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1067 bool isMemTBH() const {
1068 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1069 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1070 Memory.Alignment != 0 )
1074 bool isMemRegOffset() const {
1075 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1079 bool isT2MemRegOffset() const {
1080 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1081 Memory.Alignment != 0)
1083 // Only lsl #{0, 1, 2, 3} allowed.
1084 if (Memory.ShiftType == ARM_AM::no_shift)
1086 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1090 bool isMemThumbRR() const {
1091 // Thumb reg+reg addressing is simple. Just two registers, a base and
1092 // an offset. No shifts, negations or any other complicating factors.
1093 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1094 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1096 return isARMLowRegister(Memory.BaseRegNum) &&
1097 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1099 bool isMemThumbRIs4() const {
1100 if (!isMem() || Memory.OffsetRegNum != 0 ||
1101 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1103 // Immediate offset, multiple of 4 in range [0, 124].
1104 if (!Memory.OffsetImm) return true;
1105 int64_t Val = Memory.OffsetImm->getValue();
1106 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1108 bool isMemThumbRIs2() const {
1109 if (!isMem() || Memory.OffsetRegNum != 0 ||
1110 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1112 // Immediate offset, multiple of 4 in range [0, 62].
1113 if (!Memory.OffsetImm) return true;
1114 int64_t Val = Memory.OffsetImm->getValue();
1115 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1117 bool isMemThumbRIs1() const {
1118 if (!isMem() || Memory.OffsetRegNum != 0 ||
1119 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1121 // Immediate offset in range [0, 31].
1122 if (!Memory.OffsetImm) return true;
1123 int64_t Val = Memory.OffsetImm->getValue();
1124 return Val >= 0 && Val <= 31;
1126 bool isMemThumbSPI() const {
1127 if (!isMem() || Memory.OffsetRegNum != 0 ||
1128 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1130 // Immediate offset, multiple of 4 in range [0, 1020].
1131 if (!Memory.OffsetImm) return true;
1132 int64_t Val = Memory.OffsetImm->getValue();
1133 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1135 bool isMemImm8s4Offset() const {
1136 // If we have an immediate that's not a constant, treat it as a label
1137 // reference needing a fixup. If it is a constant, it's something else
1138 // and we reject it.
1139 if (isImm() && !isa<MCConstantExpr>(getImm()))
1141 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1143 // Immediate offset a multiple of 4 in range [-1020, 1020].
1144 if (!Memory.OffsetImm) return true;
1145 int64_t Val = Memory.OffsetImm->getValue();
1146 // Special case, #-0 is INT32_MIN.
1147 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1149 bool isMemImm0_1020s4Offset() const {
1150 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1152 // Immediate offset a multiple of 4 in range [0, 1020].
1153 if (!Memory.OffsetImm) return true;
1154 int64_t Val = Memory.OffsetImm->getValue();
1155 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1157 bool isMemImm8Offset() const {
1158 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1160 // Base reg of PC isn't allowed for these encodings.
1161 if (Memory.BaseRegNum == ARM::PC) return false;
1162 // Immediate offset in range [-255, 255].
1163 if (!Memory.OffsetImm) return true;
1164 int64_t Val = Memory.OffsetImm->getValue();
1165 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1167 bool isMemPosImm8Offset() const {
1168 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1170 // Immediate offset in range [0, 255].
1171 if (!Memory.OffsetImm) return true;
1172 int64_t Val = Memory.OffsetImm->getValue();
1173 return Val >= 0 && Val < 256;
1175 bool isMemNegImm8Offset() const {
1176 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1178 // Base reg of PC isn't allowed for these encodings.
1179 if (Memory.BaseRegNum == ARM::PC) return false;
1180 // Immediate offset in range [-255, -1].
1181 if (!Memory.OffsetImm) return false;
1182 int64_t Val = Memory.OffsetImm->getValue();
1183 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1185 bool isMemUImm12Offset() const {
1186 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1188 // Immediate offset in range [0, 4095].
1189 if (!Memory.OffsetImm) return true;
1190 int64_t Val = Memory.OffsetImm->getValue();
1191 return (Val >= 0 && Val < 4096);
1193 bool isMemImm12Offset() const {
1194 // If we have an immediate that's not a constant, treat it as a label
1195 // reference needing a fixup. If it is a constant, it's something else
1196 // and we reject it.
1197 if (isImm() && !isa<MCConstantExpr>(getImm()))
1200 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1202 // Immediate offset in range [-4095, 4095].
1203 if (!Memory.OffsetImm) return true;
1204 int64_t Val = Memory.OffsetImm->getValue();
1205 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1207 bool isPostIdxImm8() const {
1208 if (!isImm()) return false;
1209 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1210 if (!CE) return false;
1211 int64_t Val = CE->getValue();
1212 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1214 bool isPostIdxImm8s4() const {
1215 if (!isImm()) return false;
1216 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1217 if (!CE) return false;
1218 int64_t Val = CE->getValue();
1219 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1223 bool isMSRMask() const { return Kind == k_MSRMask; }
1224 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1227 bool isSingleSpacedVectorList() const {
1228 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1230 bool isDoubleSpacedVectorList() const {
1231 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1233 bool isVecListOneD() const {
1234 if (!isSingleSpacedVectorList()) return false;
1235 return VectorList.Count == 1;
1238 bool isVecListDPair() const {
1239 if (!isSingleSpacedVectorList()) return false;
1240 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1241 .contains(VectorList.RegNum));
1244 bool isVecListThreeD() const {
1245 if (!isSingleSpacedVectorList()) return false;
1246 return VectorList.Count == 3;
1249 bool isVecListFourD() const {
1250 if (!isSingleSpacedVectorList()) return false;
1251 return VectorList.Count == 4;
1254 bool isVecListDPairSpaced() const {
1255 if (isSingleSpacedVectorList()) return false;
1256 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1257 .contains(VectorList.RegNum));
1260 bool isVecListThreeQ() const {
1261 if (!isDoubleSpacedVectorList()) return false;
1262 return VectorList.Count == 3;
1265 bool isVecListFourQ() const {
1266 if (!isDoubleSpacedVectorList()) return false;
1267 return VectorList.Count == 4;
1270 bool isSingleSpacedVectorAllLanes() const {
1271 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1273 bool isDoubleSpacedVectorAllLanes() const {
1274 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1276 bool isVecListOneDAllLanes() const {
1277 if (!isSingleSpacedVectorAllLanes()) return false;
1278 return VectorList.Count == 1;
1281 bool isVecListDPairAllLanes() const {
1282 if (!isSingleSpacedVectorAllLanes()) return false;
1283 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1284 .contains(VectorList.RegNum));
1287 bool isVecListDPairSpacedAllLanes() const {
1288 if (!isDoubleSpacedVectorAllLanes()) return false;
1289 return VectorList.Count == 2;
1292 bool isVecListThreeDAllLanes() const {
1293 if (!isSingleSpacedVectorAllLanes()) return false;
1294 return VectorList.Count == 3;
1297 bool isVecListThreeQAllLanes() const {
1298 if (!isDoubleSpacedVectorAllLanes()) return false;
1299 return VectorList.Count == 3;
1302 bool isVecListFourDAllLanes() const {
1303 if (!isSingleSpacedVectorAllLanes()) return false;
1304 return VectorList.Count == 4;
1307 bool isVecListFourQAllLanes() const {
1308 if (!isDoubleSpacedVectorAllLanes()) return false;
1309 return VectorList.Count == 4;
1312 bool isSingleSpacedVectorIndexed() const {
1313 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1315 bool isDoubleSpacedVectorIndexed() const {
1316 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1318 bool isVecListOneDByteIndexed() const {
1319 if (!isSingleSpacedVectorIndexed()) return false;
1320 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1323 bool isVecListOneDHWordIndexed() const {
1324 if (!isSingleSpacedVectorIndexed()) return false;
1325 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1328 bool isVecListOneDWordIndexed() const {
1329 if (!isSingleSpacedVectorIndexed()) return false;
1330 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1333 bool isVecListTwoDByteIndexed() const {
1334 if (!isSingleSpacedVectorIndexed()) return false;
1335 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1338 bool isVecListTwoDHWordIndexed() const {
1339 if (!isSingleSpacedVectorIndexed()) return false;
1340 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1343 bool isVecListTwoQWordIndexed() const {
1344 if (!isDoubleSpacedVectorIndexed()) return false;
1345 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1348 bool isVecListTwoQHWordIndexed() const {
1349 if (!isDoubleSpacedVectorIndexed()) return false;
1350 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1353 bool isVecListTwoDWordIndexed() const {
1354 if (!isSingleSpacedVectorIndexed()) return false;
1355 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1358 bool isVecListThreeDByteIndexed() const {
1359 if (!isSingleSpacedVectorIndexed()) return false;
1360 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1363 bool isVecListThreeDHWordIndexed() const {
1364 if (!isSingleSpacedVectorIndexed()) return false;
1365 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1368 bool isVecListThreeQWordIndexed() const {
1369 if (!isDoubleSpacedVectorIndexed()) return false;
1370 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1373 bool isVecListThreeQHWordIndexed() const {
1374 if (!isDoubleSpacedVectorIndexed()) return false;
1375 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1378 bool isVecListThreeDWordIndexed() const {
1379 if (!isSingleSpacedVectorIndexed()) return false;
1380 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1383 bool isVecListFourDByteIndexed() const {
1384 if (!isSingleSpacedVectorIndexed()) return false;
1385 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1388 bool isVecListFourDHWordIndexed() const {
1389 if (!isSingleSpacedVectorIndexed()) return false;
1390 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1393 bool isVecListFourQWordIndexed() const {
1394 if (!isDoubleSpacedVectorIndexed()) return false;
1395 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1398 bool isVecListFourQHWordIndexed() const {
1399 if (!isDoubleSpacedVectorIndexed()) return false;
1400 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1403 bool isVecListFourDWordIndexed() const {
1404 if (!isSingleSpacedVectorIndexed()) return false;
1405 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1408 bool isVectorIndex8() const {
1409 if (Kind != k_VectorIndex) return false;
1410 return VectorIndex.Val < 8;
1412 bool isVectorIndex16() const {
1413 if (Kind != k_VectorIndex) return false;
1414 return VectorIndex.Val < 4;
1416 bool isVectorIndex32() const {
1417 if (Kind != k_VectorIndex) return false;
1418 return VectorIndex.Val < 2;
1421 bool isNEONi8splat() const {
1422 if (!isImm()) return false;
1423 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1424 // Must be a constant.
1425 if (!CE) return false;
1426 int64_t Value = CE->getValue();
1427 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1429 return Value >= 0 && Value < 256;
1432 bool isNEONi16splat() const {
1433 if (!isImm()) return false;
1434 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1435 // Must be a constant.
1436 if (!CE) return false;
1437 int64_t Value = CE->getValue();
1438 // i16 value in the range [0,255] or [0x0100, 0xff00]
1439 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1442 bool isNEONi32splat() const {
1443 if (!isImm()) return false;
1444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1445 // Must be a constant.
1446 if (!CE) return false;
1447 int64_t Value = CE->getValue();
1448 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1449 return (Value >= 0 && Value < 256) ||
1450 (Value >= 0x0100 && Value <= 0xff00) ||
1451 (Value >= 0x010000 && Value <= 0xff0000) ||
1452 (Value >= 0x01000000 && Value <= 0xff000000);
1455 bool isNEONi32vmov() const {
1456 if (!isImm()) return false;
1457 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1458 // Must be a constant.
1459 if (!CE) return false;
1460 int64_t Value = CE->getValue();
1461 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1462 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1463 return (Value >= 0 && Value < 256) ||
1464 (Value >= 0x0100 && Value <= 0xff00) ||
1465 (Value >= 0x010000 && Value <= 0xff0000) ||
1466 (Value >= 0x01000000 && Value <= 0xff000000) ||
1467 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1468 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1470 bool isNEONi32vmovNeg() const {
1471 if (!isImm()) return false;
1472 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1473 // Must be a constant.
1474 if (!CE) return false;
1475 int64_t Value = ~CE->getValue();
1476 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1477 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1478 return (Value >= 0 && Value < 256) ||
1479 (Value >= 0x0100 && Value <= 0xff00) ||
1480 (Value >= 0x010000 && Value <= 0xff0000) ||
1481 (Value >= 0x01000000 && Value <= 0xff000000) ||
1482 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1483 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1486 bool isNEONi64splat() const {
1487 if (!isImm()) return false;
1488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1489 // Must be a constant.
1490 if (!CE) return false;
1491 uint64_t Value = CE->getValue();
1492 // i64 value with each byte being either 0 or 0xff.
1493 for (unsigned i = 0; i < 8; ++i)
1494 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1498 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1499 // Add as immediates when possible. Null MCExpr = 0.
1501 Inst.addOperand(MCOperand::CreateImm(0));
1502 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1503 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1505 Inst.addOperand(MCOperand::CreateExpr(Expr));
1508 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1509 assert(N == 2 && "Invalid number of operands!");
1510 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1511 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1512 Inst.addOperand(MCOperand::CreateReg(RegNum));
1515 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1516 assert(N == 1 && "Invalid number of operands!");
1517 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1520 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1521 assert(N == 1 && "Invalid number of operands!");
1522 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1525 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1526 assert(N == 1 && "Invalid number of operands!");
1527 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1530 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1531 assert(N == 1 && "Invalid number of operands!");
1532 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1535 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1536 assert(N == 1 && "Invalid number of operands!");
1537 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1540 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1541 assert(N == 1 && "Invalid number of operands!");
1542 Inst.addOperand(MCOperand::CreateReg(getReg()));
1545 void addRegOperands(MCInst &Inst, unsigned N) const {
1546 assert(N == 1 && "Invalid number of operands!");
1547 Inst.addOperand(MCOperand::CreateReg(getReg()));
1550 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1551 assert(N == 3 && "Invalid number of operands!");
1552 assert(isRegShiftedReg() &&
1553 "addRegShiftedRegOperands() on non RegShiftedReg!");
1554 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1555 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1556 Inst.addOperand(MCOperand::CreateImm(
1557 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1560 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1561 assert(N == 2 && "Invalid number of operands!");
1562 assert(isRegShiftedImm() &&
1563 "addRegShiftedImmOperands() on non RegShiftedImm!");
1564 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1565 // Shift of #32 is encoded as 0 where permitted
1566 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1567 Inst.addOperand(MCOperand::CreateImm(
1568 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1571 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1572 assert(N == 1 && "Invalid number of operands!");
1573 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1577 void addRegListOperands(MCInst &Inst, unsigned N) const {
1578 assert(N == 1 && "Invalid number of operands!");
1579 const SmallVectorImpl<unsigned> &RegList = getRegList();
1580 for (SmallVectorImpl<unsigned>::const_iterator
1581 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1582 Inst.addOperand(MCOperand::CreateReg(*I));
1585 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1586 addRegListOperands(Inst, N);
1589 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1590 addRegListOperands(Inst, N);
1593 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1594 assert(N == 1 && "Invalid number of operands!");
1595 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1596 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1599 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1600 assert(N == 1 && "Invalid number of operands!");
1601 // Munge the lsb/width into a bitfield mask.
1602 unsigned lsb = Bitfield.LSB;
1603 unsigned width = Bitfield.Width;
1604 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1605 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1606 (32 - (lsb + width)));
1607 Inst.addOperand(MCOperand::CreateImm(Mask));
1610 void addImmOperands(MCInst &Inst, unsigned N) const {
1611 assert(N == 1 && "Invalid number of operands!");
1612 addExpr(Inst, getImm());
1615 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1616 assert(N == 1 && "Invalid number of operands!");
1617 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1618 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1621 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1622 assert(N == 1 && "Invalid number of operands!");
1623 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1624 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1627 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1628 assert(N == 1 && "Invalid number of operands!");
1629 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1630 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1631 Inst.addOperand(MCOperand::CreateImm(Val));
1634 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1635 assert(N == 1 && "Invalid number of operands!");
1636 // FIXME: We really want to scale the value here, but the LDRD/STRD
1637 // instruction don't encode operands that way yet.
1638 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1639 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1642 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1643 assert(N == 1 && "Invalid number of operands!");
1644 // The immediate is scaled by four in the encoding and is stored
1645 // in the MCInst as such. Lop off the low two bits here.
1646 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1647 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1650 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1651 assert(N == 1 && "Invalid number of operands!");
1652 // The immediate is scaled by four in the encoding and is stored
1653 // in the MCInst as such. Lop off the low two bits here.
1654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1655 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1658 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1659 assert(N == 1 && "Invalid number of operands!");
1660 // The immediate is scaled by four in the encoding and is stored
1661 // in the MCInst as such. Lop off the low two bits here.
1662 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1663 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1666 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1667 assert(N == 1 && "Invalid number of operands!");
1668 // The constant encodes as the immediate-1, and we store in the instruction
1669 // the bits as encoded, so subtract off one here.
1670 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1671 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1674 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1675 assert(N == 1 && "Invalid number of operands!");
1676 // The constant encodes as the immediate-1, and we store in the instruction
1677 // the bits as encoded, so subtract off one here.
1678 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1679 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1682 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1683 assert(N == 1 && "Invalid number of operands!");
1684 // The constant encodes as the immediate, except for 32, which encodes as
1686 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1687 unsigned Imm = CE->getValue();
1688 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1691 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1692 assert(N == 1 && "Invalid number of operands!");
1693 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1694 // the instruction as well.
1695 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1696 int Val = CE->getValue();
1697 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1700 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1701 assert(N == 1 && "Invalid number of operands!");
1702 // The operand is actually a t2_so_imm, but we have its bitwise
1703 // negation in the assembly source, so twiddle it here.
1704 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1705 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1708 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1709 assert(N == 1 && "Invalid number of operands!");
1710 // The operand is actually a t2_so_imm, but we have its
1711 // negation in the assembly source, so twiddle it here.
1712 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1713 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1716 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1717 assert(N == 1 && "Invalid number of operands!");
1718 // The operand is actually an imm0_4095, but we have its
1719 // negation in the assembly source, so twiddle it here.
1720 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1721 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1724 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1725 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1726 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1730 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1731 assert(SR && "Unknown value type!");
1732 Inst.addOperand(MCOperand::CreateExpr(SR));
1735 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1736 assert(N == 1 && "Invalid number of operands!");
1737 // The operand is actually a so_imm, but we have its bitwise
1738 // negation in the assembly source, so twiddle it here.
1739 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1740 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1743 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1744 assert(N == 1 && "Invalid number of operands!");
1745 // The operand is actually a so_imm, but we have its
1746 // negation in the assembly source, so twiddle it here.
1747 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1748 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1751 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1752 assert(N == 1 && "Invalid number of operands!");
1753 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1756 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1757 assert(N == 1 && "Invalid number of operands!");
1758 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1761 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1762 assert(N == 1 && "Invalid number of operands!");
1763 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1766 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1767 assert(N == 1 && "Invalid number of operands!");
1768 int32_t Imm = Memory.OffsetImm->getValue();
1769 // FIXME: Handle #-0
1770 if (Imm == INT32_MIN) Imm = 0;
1771 Inst.addOperand(MCOperand::CreateImm(Imm));
1774 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1775 assert(N == 1 && "Invalid number of operands!");
1776 assert(isImm() && "Not an immediate!");
1778 // If we have an immediate that's not a constant, treat it as a label
1779 // reference needing a fixup.
1780 if (!isa<MCConstantExpr>(getImm())) {
1781 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1785 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1786 int Val = CE->getValue();
1787 Inst.addOperand(MCOperand::CreateImm(Val));
1790 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1791 assert(N == 2 && "Invalid number of operands!");
1792 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1793 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1796 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1797 assert(N == 3 && "Invalid number of operands!");
1798 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1799 if (!Memory.OffsetRegNum) {
1800 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1801 // Special case for #-0
1802 if (Val == INT32_MIN) Val = 0;
1803 if (Val < 0) Val = -Val;
1804 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1806 // For register offset, we encode the shift type and negation flag
1808 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1809 Memory.ShiftImm, Memory.ShiftType);
1811 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1812 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1813 Inst.addOperand(MCOperand::CreateImm(Val));
1816 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1817 assert(N == 2 && "Invalid number of operands!");
1818 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1819 assert(CE && "non-constant AM2OffsetImm operand!");
1820 int32_t Val = CE->getValue();
1821 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1822 // Special case for #-0
1823 if (Val == INT32_MIN) Val = 0;
1824 if (Val < 0) Val = -Val;
1825 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1826 Inst.addOperand(MCOperand::CreateReg(0));
1827 Inst.addOperand(MCOperand::CreateImm(Val));
1830 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1831 assert(N == 3 && "Invalid number of operands!");
1832 // If we have an immediate that's not a constant, treat it as a label
1833 // reference needing a fixup. If it is a constant, it's something else
1834 // and we reject it.
1836 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1837 Inst.addOperand(MCOperand::CreateReg(0));
1838 Inst.addOperand(MCOperand::CreateImm(0));
1842 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1843 if (!Memory.OffsetRegNum) {
1844 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1845 // Special case for #-0
1846 if (Val == INT32_MIN) Val = 0;
1847 if (Val < 0) Val = -Val;
1848 Val = ARM_AM::getAM3Opc(AddSub, Val);
1850 // For register offset, we encode the shift type and negation flag
1852 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1854 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1855 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1856 Inst.addOperand(MCOperand::CreateImm(Val));
1859 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1860 assert(N == 2 && "Invalid number of operands!");
1861 if (Kind == k_PostIndexRegister) {
1863 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1864 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1865 Inst.addOperand(MCOperand::CreateImm(Val));
1870 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1871 int32_t Val = CE->getValue();
1872 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1873 // Special case for #-0
1874 if (Val == INT32_MIN) Val = 0;
1875 if (Val < 0) Val = -Val;
1876 Val = ARM_AM::getAM3Opc(AddSub, Val);
1877 Inst.addOperand(MCOperand::CreateReg(0));
1878 Inst.addOperand(MCOperand::CreateImm(Val));
1881 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1882 assert(N == 2 && "Invalid number of operands!");
1883 // If we have an immediate that's not a constant, treat it as a label
1884 // reference needing a fixup. If it is a constant, it's something else
1885 // and we reject it.
1887 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1888 Inst.addOperand(MCOperand::CreateImm(0));
1892 // The lower two bits are always zero and as such are not encoded.
1893 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1894 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1895 // Special case for #-0
1896 if (Val == INT32_MIN) Val = 0;
1897 if (Val < 0) Val = -Val;
1898 Val = ARM_AM::getAM5Opc(AddSub, Val);
1899 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1900 Inst.addOperand(MCOperand::CreateImm(Val));
1903 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1904 assert(N == 2 && "Invalid number of operands!");
1905 // If we have an immediate that's not a constant, treat it as a label
1906 // reference needing a fixup. If it is a constant, it's something else
1907 // and we reject it.
1909 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1910 Inst.addOperand(MCOperand::CreateImm(0));
1914 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1915 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1916 Inst.addOperand(MCOperand::CreateImm(Val));
1919 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1920 assert(N == 2 && "Invalid number of operands!");
1921 // The lower two bits are always zero and as such are not encoded.
1922 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1923 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1924 Inst.addOperand(MCOperand::CreateImm(Val));
1927 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1928 assert(N == 2 && "Invalid number of operands!");
1929 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1930 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1931 Inst.addOperand(MCOperand::CreateImm(Val));
1934 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1935 addMemImm8OffsetOperands(Inst, N);
1938 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1939 addMemImm8OffsetOperands(Inst, N);
1942 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1943 assert(N == 2 && "Invalid number of operands!");
1944 // If this is an immediate, it's a label reference.
1946 addExpr(Inst, getImm());
1947 Inst.addOperand(MCOperand::CreateImm(0));
1951 // Otherwise, it's a normal memory reg+offset.
1952 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1953 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1954 Inst.addOperand(MCOperand::CreateImm(Val));
1957 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1958 assert(N == 2 && "Invalid number of operands!");
1959 // If this is an immediate, it's a label reference.
1961 addExpr(Inst, getImm());
1962 Inst.addOperand(MCOperand::CreateImm(0));
1966 // Otherwise, it's a normal memory reg+offset.
1967 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1968 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1969 Inst.addOperand(MCOperand::CreateImm(Val));
1972 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1973 assert(N == 2 && "Invalid number of operands!");
1974 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1975 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1978 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1979 assert(N == 2 && "Invalid number of operands!");
1980 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1981 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1984 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1985 assert(N == 3 && "Invalid number of operands!");
1987 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1988 Memory.ShiftImm, Memory.ShiftType);
1989 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1990 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1991 Inst.addOperand(MCOperand::CreateImm(Val));
1994 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1995 assert(N == 3 && "Invalid number of operands!");
1996 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1997 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1998 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2001 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2002 assert(N == 2 && "Invalid number of operands!");
2003 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2004 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2007 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2008 assert(N == 2 && "Invalid number of operands!");
2009 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2010 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2011 Inst.addOperand(MCOperand::CreateImm(Val));
2014 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2015 assert(N == 2 && "Invalid number of operands!");
2016 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2017 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2018 Inst.addOperand(MCOperand::CreateImm(Val));
2021 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2022 assert(N == 2 && "Invalid number of operands!");
2023 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2024 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2025 Inst.addOperand(MCOperand::CreateImm(Val));
2028 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2029 assert(N == 2 && "Invalid number of operands!");
2030 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2031 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2032 Inst.addOperand(MCOperand::CreateImm(Val));
2035 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2036 assert(N == 1 && "Invalid number of operands!");
2037 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2038 assert(CE && "non-constant post-idx-imm8 operand!");
2039 int Imm = CE->getValue();
2040 bool isAdd = Imm >= 0;
2041 if (Imm == INT32_MIN) Imm = 0;
2042 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2043 Inst.addOperand(MCOperand::CreateImm(Imm));
2046 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2047 assert(N == 1 && "Invalid number of operands!");
2048 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2049 assert(CE && "non-constant post-idx-imm8s4 operand!");
2050 int Imm = CE->getValue();
2051 bool isAdd = Imm >= 0;
2052 if (Imm == INT32_MIN) Imm = 0;
2053 // Immediate is scaled by 4.
2054 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2055 Inst.addOperand(MCOperand::CreateImm(Imm));
2058 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2059 assert(N == 2 && "Invalid number of operands!");
2060 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2061 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2064 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2065 assert(N == 2 && "Invalid number of operands!");
2066 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2067 // The sign, shift type, and shift amount are encoded in a single operand
2068 // using the AM2 encoding helpers.
2069 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2070 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2071 PostIdxReg.ShiftTy);
2072 Inst.addOperand(MCOperand::CreateImm(Imm));
2075 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2076 assert(N == 1 && "Invalid number of operands!");
2077 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2080 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2081 assert(N == 1 && "Invalid number of operands!");
2082 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2085 void addVecListOperands(MCInst &Inst, unsigned N) const {
2086 assert(N == 1 && "Invalid number of operands!");
2087 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2090 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2091 assert(N == 2 && "Invalid number of operands!");
2092 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2093 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2096 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2097 assert(N == 1 && "Invalid number of operands!");
2098 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2101 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2102 assert(N == 1 && "Invalid number of operands!");
2103 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2106 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2107 assert(N == 1 && "Invalid number of operands!");
2108 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2111 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2112 assert(N == 1 && "Invalid number of operands!");
2113 // The immediate encodes the type of constant as well as the value.
2114 // Mask in that this is an i8 splat.
2115 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2116 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2119 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2120 assert(N == 1 && "Invalid number of operands!");
2121 // The immediate encodes the type of constant as well as the value.
2122 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2123 unsigned Value = CE->getValue();
2125 Value = (Value >> 8) | 0xa00;
2128 Inst.addOperand(MCOperand::CreateImm(Value));
2131 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2132 assert(N == 1 && "Invalid number of operands!");
2133 // The immediate encodes the type of constant as well as the value.
2134 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2135 unsigned Value = CE->getValue();
2136 if (Value >= 256 && Value <= 0xff00)
2137 Value = (Value >> 8) | 0x200;
2138 else if (Value > 0xffff && Value <= 0xff0000)
2139 Value = (Value >> 16) | 0x400;
2140 else if (Value > 0xffffff)
2141 Value = (Value >> 24) | 0x600;
2142 Inst.addOperand(MCOperand::CreateImm(Value));
2145 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2146 assert(N == 1 && "Invalid number of operands!");
2147 // The immediate encodes the type of constant as well as the value.
2148 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2149 unsigned Value = CE->getValue();
2150 if (Value >= 256 && Value <= 0xffff)
2151 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2152 else if (Value > 0xffff && Value <= 0xffffff)
2153 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2154 else if (Value > 0xffffff)
2155 Value = (Value >> 24) | 0x600;
2156 Inst.addOperand(MCOperand::CreateImm(Value));
2159 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2160 assert(N == 1 && "Invalid number of operands!");
2161 // The immediate encodes the type of constant as well as the value.
2162 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2163 unsigned Value = ~CE->getValue();
2164 if (Value >= 256 && Value <= 0xffff)
2165 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2166 else if (Value > 0xffff && Value <= 0xffffff)
2167 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2168 else if (Value > 0xffffff)
2169 Value = (Value >> 24) | 0x600;
2170 Inst.addOperand(MCOperand::CreateImm(Value));
2173 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2174 assert(N == 1 && "Invalid number of operands!");
2175 // The immediate encodes the type of constant as well as the value.
2176 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2177 uint64_t Value = CE->getValue();
2179 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2180 Imm |= (Value & 1) << i;
2182 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2185 virtual void print(raw_ostream &OS) const;
2187 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2188 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2189 Op->ITMask.Mask = Mask;
2195 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2196 ARMOperand *Op = new ARMOperand(k_CondCode);
2203 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2204 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2205 Op->Cop.Val = CopVal;
2211 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2212 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2213 Op->Cop.Val = CopVal;
2219 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2220 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2227 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2228 ARMOperand *Op = new ARMOperand(k_CCOut);
2229 Op->Reg.RegNum = RegNum;
2235 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2236 ARMOperand *Op = new ARMOperand(k_Token);
2237 Op->Tok.Data = Str.data();
2238 Op->Tok.Length = Str.size();
2244 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2245 ARMOperand *Op = new ARMOperand(k_Register);
2246 Op->Reg.RegNum = RegNum;
2252 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2257 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2258 Op->RegShiftedReg.ShiftTy = ShTy;
2259 Op->RegShiftedReg.SrcReg = SrcReg;
2260 Op->RegShiftedReg.ShiftReg = ShiftReg;
2261 Op->RegShiftedReg.ShiftImm = ShiftImm;
2267 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2271 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2272 Op->RegShiftedImm.ShiftTy = ShTy;
2273 Op->RegShiftedImm.SrcReg = SrcReg;
2274 Op->RegShiftedImm.ShiftImm = ShiftImm;
2280 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2282 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2283 Op->ShifterImm.isASR = isASR;
2284 Op->ShifterImm.Imm = Imm;
2290 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2291 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2292 Op->RotImm.Imm = Imm;
2298 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2300 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2301 Op->Bitfield.LSB = LSB;
2302 Op->Bitfield.Width = Width;
2309 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2310 SMLoc StartLoc, SMLoc EndLoc) {
2311 assert (Regs.size() > 0 && "RegList contains no registers?");
2312 KindTy Kind = k_RegisterList;
2314 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2315 Kind = k_DPRRegisterList;
2316 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2317 contains(Regs.front().second))
2318 Kind = k_SPRRegisterList;
2320 // Sort based on the register encoding values.
2321 array_pod_sort(Regs.begin(), Regs.end());
2323 ARMOperand *Op = new ARMOperand(Kind);
2324 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2325 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2326 Op->Registers.push_back(I->second);
2327 Op->StartLoc = StartLoc;
2328 Op->EndLoc = EndLoc;
2332 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2333 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2334 ARMOperand *Op = new ARMOperand(k_VectorList);
2335 Op->VectorList.RegNum = RegNum;
2336 Op->VectorList.Count = Count;
2337 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2343 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2344 bool isDoubleSpaced,
2346 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2347 Op->VectorList.RegNum = RegNum;
2348 Op->VectorList.Count = Count;
2349 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2355 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2357 bool isDoubleSpaced,
2359 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2360 Op->VectorList.RegNum = RegNum;
2361 Op->VectorList.Count = Count;
2362 Op->VectorList.LaneIndex = Index;
2363 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2369 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2371 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2372 Op->VectorIndex.Val = Idx;
2378 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2379 ARMOperand *Op = new ARMOperand(k_Immediate);
2386 static ARMOperand *CreateMem(unsigned BaseRegNum,
2387 const MCConstantExpr *OffsetImm,
2388 unsigned OffsetRegNum,
2389 ARM_AM::ShiftOpc ShiftType,
2394 ARMOperand *Op = new ARMOperand(k_Memory);
2395 Op->Memory.BaseRegNum = BaseRegNum;
2396 Op->Memory.OffsetImm = OffsetImm;
2397 Op->Memory.OffsetRegNum = OffsetRegNum;
2398 Op->Memory.ShiftType = ShiftType;
2399 Op->Memory.ShiftImm = ShiftImm;
2400 Op->Memory.Alignment = Alignment;
2401 Op->Memory.isNegative = isNegative;
2407 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2408 ARM_AM::ShiftOpc ShiftTy,
2411 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2412 Op->PostIdxReg.RegNum = RegNum;
2413 Op->PostIdxReg.isAdd = isAdd;
2414 Op->PostIdxReg.ShiftTy = ShiftTy;
2415 Op->PostIdxReg.ShiftImm = ShiftImm;
2421 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2422 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2423 Op->MBOpt.Val = Opt;
2429 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2431 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2432 Op->ISBOpt.Val = Opt;
2438 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2439 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2440 Op->IFlags.Val = IFlags;
2446 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2447 ARMOperand *Op = new ARMOperand(k_MSRMask);
2448 Op->MMask.Val = MMask;
2455 } // end anonymous namespace.
2457 void ARMOperand::print(raw_ostream &OS) const {
2460 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2463 OS << "<ccout " << getReg() << ">";
2465 case k_ITCondMask: {
2466 static const char *const MaskStr[] = {
2467 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2468 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2470 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2471 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2475 OS << "<coprocessor number: " << getCoproc() << ">";
2478 OS << "<coprocessor register: " << getCoproc() << ">";
2480 case k_CoprocOption:
2481 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2484 OS << "<mask: " << getMSRMask() << ">";
2487 getImm()->print(OS);
2489 case k_MemBarrierOpt:
2490 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2492 case k_InstSyncBarrierOpt:
2493 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2497 << " base:" << Memory.BaseRegNum;
2500 case k_PostIndexRegister:
2501 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2502 << PostIdxReg.RegNum;
2503 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2504 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2505 << PostIdxReg.ShiftImm;
2508 case k_ProcIFlags: {
2509 OS << "<ARM_PROC::";
2510 unsigned IFlags = getProcIFlags();
2511 for (int i=2; i >= 0; --i)
2512 if (IFlags & (1 << i))
2513 OS << ARM_PROC::IFlagsToString(1 << i);
2518 OS << "<register " << getReg() << ">";
2520 case k_ShifterImmediate:
2521 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2522 << " #" << ShifterImm.Imm << ">";
2524 case k_ShiftedRegister:
2525 OS << "<so_reg_reg "
2526 << RegShiftedReg.SrcReg << " "
2527 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2528 << " " << RegShiftedReg.ShiftReg << ">";
2530 case k_ShiftedImmediate:
2531 OS << "<so_reg_imm "
2532 << RegShiftedImm.SrcReg << " "
2533 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2534 << " #" << RegShiftedImm.ShiftImm << ">";
2536 case k_RotateImmediate:
2537 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2539 case k_BitfieldDescriptor:
2540 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2541 << ", width: " << Bitfield.Width << ">";
2543 case k_RegisterList:
2544 case k_DPRRegisterList:
2545 case k_SPRRegisterList: {
2546 OS << "<register_list ";
2548 const SmallVectorImpl<unsigned> &RegList = getRegList();
2549 for (SmallVectorImpl<unsigned>::const_iterator
2550 I = RegList.begin(), E = RegList.end(); I != E; ) {
2552 if (++I < E) OS << ", ";
2559 OS << "<vector_list " << VectorList.Count << " * "
2560 << VectorList.RegNum << ">";
2562 case k_VectorListAllLanes:
2563 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2564 << VectorList.RegNum << ">";
2566 case k_VectorListIndexed:
2567 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2568 << VectorList.Count << " * " << VectorList.RegNum << ">";
2571 OS << "'" << getToken() << "'";
2574 OS << "<vectorindex " << getVectorIndex() << ">";
2579 /// @name Auto-generated Match Functions
2582 static unsigned MatchRegisterName(StringRef Name);
2586 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2587 SMLoc &StartLoc, SMLoc &EndLoc) {
2588 StartLoc = Parser.getTok().getLoc();
2589 EndLoc = Parser.getTok().getEndLoc();
2590 RegNo = tryParseRegister();
2592 return (RegNo == (unsigned)-1);
2595 /// Try to parse a register name. The token must be an Identifier when called,
2596 /// and if it is a register name the token is eaten and the register number is
2597 /// returned. Otherwise return -1.
2599 int ARMAsmParser::tryParseRegister() {
2600 const AsmToken &Tok = Parser.getTok();
2601 if (Tok.isNot(AsmToken::Identifier)) return -1;
2603 std::string lowerCase = Tok.getString().lower();
2604 unsigned RegNum = MatchRegisterName(lowerCase);
2606 RegNum = StringSwitch<unsigned>(lowerCase)
2607 .Case("r13", ARM::SP)
2608 .Case("r14", ARM::LR)
2609 .Case("r15", ARM::PC)
2610 .Case("ip", ARM::R12)
2611 // Additional register name aliases for 'gas' compatibility.
2612 .Case("a1", ARM::R0)
2613 .Case("a2", ARM::R1)
2614 .Case("a3", ARM::R2)
2615 .Case("a4", ARM::R3)
2616 .Case("v1", ARM::R4)
2617 .Case("v2", ARM::R5)
2618 .Case("v3", ARM::R6)
2619 .Case("v4", ARM::R7)
2620 .Case("v5", ARM::R8)
2621 .Case("v6", ARM::R9)
2622 .Case("v7", ARM::R10)
2623 .Case("v8", ARM::R11)
2624 .Case("sb", ARM::R9)
2625 .Case("sl", ARM::R10)
2626 .Case("fp", ARM::R11)
2630 // Check for aliases registered via .req. Canonicalize to lower case.
2631 // That's more consistent since register names are case insensitive, and
2632 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2633 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2634 // If no match, return failure.
2635 if (Entry == RegisterReqs.end())
2637 Parser.Lex(); // Eat identifier token.
2638 return Entry->getValue();
2641 Parser.Lex(); // Eat identifier token.
2646 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2647 // If a recoverable error occurs, return 1. If an irrecoverable error
2648 // occurs, return -1. An irrecoverable error is one where tokens have been
2649 // consumed in the process of trying to parse the shifter (i.e., when it is
2650 // indeed a shifter operand, but malformed).
2651 int ARMAsmParser::tryParseShiftRegister(
2652 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2653 SMLoc S = Parser.getTok().getLoc();
2654 const AsmToken &Tok = Parser.getTok();
2655 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2657 std::string lowerCase = Tok.getString().lower();
2658 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2659 .Case("asl", ARM_AM::lsl)
2660 .Case("lsl", ARM_AM::lsl)
2661 .Case("lsr", ARM_AM::lsr)
2662 .Case("asr", ARM_AM::asr)
2663 .Case("ror", ARM_AM::ror)
2664 .Case("rrx", ARM_AM::rrx)
2665 .Default(ARM_AM::no_shift);
2667 if (ShiftTy == ARM_AM::no_shift)
2670 Parser.Lex(); // Eat the operator.
2672 // The source register for the shift has already been added to the
2673 // operand list, so we need to pop it off and combine it into the shifted
2674 // register operand instead.
2675 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2676 if (!PrevOp->isReg())
2677 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2678 int SrcReg = PrevOp->getReg();
2683 if (ShiftTy == ARM_AM::rrx) {
2684 // RRX Doesn't have an explicit shift amount. The encoder expects
2685 // the shift register to be the same as the source register. Seems odd,
2689 // Figure out if this is shifted by a constant or a register (for non-RRX).
2690 if (Parser.getTok().is(AsmToken::Hash) ||
2691 Parser.getTok().is(AsmToken::Dollar)) {
2692 Parser.Lex(); // Eat hash.
2693 SMLoc ImmLoc = Parser.getTok().getLoc();
2694 const MCExpr *ShiftExpr = 0;
2695 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2696 Error(ImmLoc, "invalid immediate shift value");
2699 // The expression must be evaluatable as an immediate.
2700 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2702 Error(ImmLoc, "invalid immediate shift value");
2705 // Range check the immediate.
2706 // lsl, ror: 0 <= imm <= 31
2707 // lsr, asr: 0 <= imm <= 32
2708 Imm = CE->getValue();
2710 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2711 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2712 Error(ImmLoc, "immediate shift value out of range");
2715 // shift by zero is a nop. Always send it through as lsl.
2716 // ('as' compatibility)
2718 ShiftTy = ARM_AM::lsl;
2719 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2720 SMLoc L = Parser.getTok().getLoc();
2721 EndLoc = Parser.getTok().getEndLoc();
2722 ShiftReg = tryParseRegister();
2723 if (ShiftReg == -1) {
2724 Error (L, "expected immediate or register in shift operand");
2728 Error (Parser.getTok().getLoc(),
2729 "expected immediate or register in shift operand");
2734 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2735 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2739 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2746 /// Try to parse a register name. The token must be an Identifier when called.
2747 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2748 /// if there is a "writeback". 'true' if it's not a register.
2750 /// TODO this is likely to change to allow different register types and or to
2751 /// parse for a specific register type.
2753 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2754 const AsmToken &RegTok = Parser.getTok();
2755 int RegNo = tryParseRegister();
2759 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2760 RegTok.getEndLoc()));
2762 const AsmToken &ExclaimTok = Parser.getTok();
2763 if (ExclaimTok.is(AsmToken::Exclaim)) {
2764 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2765 ExclaimTok.getLoc()));
2766 Parser.Lex(); // Eat exclaim token
2770 // Also check for an index operand. This is only legal for vector registers,
2771 // but that'll get caught OK in operand matching, so we don't need to
2772 // explicitly filter everything else out here.
2773 if (Parser.getTok().is(AsmToken::LBrac)) {
2774 SMLoc SIdx = Parser.getTok().getLoc();
2775 Parser.Lex(); // Eat left bracket token.
2777 const MCExpr *ImmVal;
2778 if (getParser().parseExpression(ImmVal))
2780 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2782 return TokError("immediate value expected for vector index");
2784 if (Parser.getTok().isNot(AsmToken::RBrac))
2785 return Error(Parser.getTok().getLoc(), "']' expected");
2787 SMLoc E = Parser.getTok().getEndLoc();
2788 Parser.Lex(); // Eat right bracket token.
2790 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2798 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2799 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2801 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2802 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2804 switch (Name.size()) {
2807 if (Name[0] != CoprocOp)
2823 if (Name[0] != CoprocOp || Name[1] != '1')
2827 case '0': return 10;
2828 case '1': return 11;
2829 case '2': return 12;
2830 case '3': return 13;
2831 case '4': return 14;
2832 case '5': return 15;
2837 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2838 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2839 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2840 SMLoc S = Parser.getTok().getLoc();
2841 const AsmToken &Tok = Parser.getTok();
2842 if (!Tok.is(AsmToken::Identifier))
2843 return MatchOperand_NoMatch;
2844 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2845 .Case("eq", ARMCC::EQ)
2846 .Case("ne", ARMCC::NE)
2847 .Case("hs", ARMCC::HS)
2848 .Case("cs", ARMCC::HS)
2849 .Case("lo", ARMCC::LO)
2850 .Case("cc", ARMCC::LO)
2851 .Case("mi", ARMCC::MI)
2852 .Case("pl", ARMCC::PL)
2853 .Case("vs", ARMCC::VS)
2854 .Case("vc", ARMCC::VC)
2855 .Case("hi", ARMCC::HI)
2856 .Case("ls", ARMCC::LS)
2857 .Case("ge", ARMCC::GE)
2858 .Case("lt", ARMCC::LT)
2859 .Case("gt", ARMCC::GT)
2860 .Case("le", ARMCC::LE)
2861 .Case("al", ARMCC::AL)
2864 return MatchOperand_NoMatch;
2865 Parser.Lex(); // Eat the token.
2867 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2869 return MatchOperand_Success;
2872 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2873 /// token must be an Identifier when called, and if it is a coprocessor
2874 /// number, the token is eaten and the operand is added to the operand list.
2875 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2876 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2877 SMLoc S = Parser.getTok().getLoc();
2878 const AsmToken &Tok = Parser.getTok();
2879 if (Tok.isNot(AsmToken::Identifier))
2880 return MatchOperand_NoMatch;
2882 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2884 return MatchOperand_NoMatch;
2886 Parser.Lex(); // Eat identifier token.
2887 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2888 return MatchOperand_Success;
2891 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2892 /// token must be an Identifier when called, and if it is a coprocessor
2893 /// number, the token is eaten and the operand is added to the operand list.
2894 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2895 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2896 SMLoc S = Parser.getTok().getLoc();
2897 const AsmToken &Tok = Parser.getTok();
2898 if (Tok.isNot(AsmToken::Identifier))
2899 return MatchOperand_NoMatch;
2901 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2903 return MatchOperand_NoMatch;
2905 Parser.Lex(); // Eat identifier token.
2906 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2907 return MatchOperand_Success;
2910 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2911 /// coproc_option : '{' imm0_255 '}'
2912 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2913 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2914 SMLoc S = Parser.getTok().getLoc();
2916 // If this isn't a '{', this isn't a coprocessor immediate operand.
2917 if (Parser.getTok().isNot(AsmToken::LCurly))
2918 return MatchOperand_NoMatch;
2919 Parser.Lex(); // Eat the '{'
2922 SMLoc Loc = Parser.getTok().getLoc();
2923 if (getParser().parseExpression(Expr)) {
2924 Error(Loc, "illegal expression");
2925 return MatchOperand_ParseFail;
2927 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2928 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2929 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2930 return MatchOperand_ParseFail;
2932 int Val = CE->getValue();
2934 // Check for and consume the closing '}'
2935 if (Parser.getTok().isNot(AsmToken::RCurly))
2936 return MatchOperand_ParseFail;
2937 SMLoc E = Parser.getTok().getEndLoc();
2938 Parser.Lex(); // Eat the '}'
2940 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2941 return MatchOperand_Success;
2944 // For register list parsing, we need to map from raw GPR register numbering
2945 // to the enumeration values. The enumeration values aren't sorted by
2946 // register number due to our using "sp", "lr" and "pc" as canonical names.
2947 static unsigned getNextRegister(unsigned Reg) {
2948 // If this is a GPR, we need to do it manually, otherwise we can rely
2949 // on the sort ordering of the enumeration since the other reg-classes
2951 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2954 default: llvm_unreachable("Invalid GPR number!");
2955 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2956 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2957 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2958 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2959 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2960 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2961 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2962 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2966 // Return the low-subreg of a given Q register.
2967 static unsigned getDRegFromQReg(unsigned QReg) {
2969 default: llvm_unreachable("expected a Q register!");
2970 case ARM::Q0: return ARM::D0;
2971 case ARM::Q1: return ARM::D2;
2972 case ARM::Q2: return ARM::D4;
2973 case ARM::Q3: return ARM::D6;
2974 case ARM::Q4: return ARM::D8;
2975 case ARM::Q5: return ARM::D10;
2976 case ARM::Q6: return ARM::D12;
2977 case ARM::Q7: return ARM::D14;
2978 case ARM::Q8: return ARM::D16;
2979 case ARM::Q9: return ARM::D18;
2980 case ARM::Q10: return ARM::D20;
2981 case ARM::Q11: return ARM::D22;
2982 case ARM::Q12: return ARM::D24;
2983 case ARM::Q13: return ARM::D26;
2984 case ARM::Q14: return ARM::D28;
2985 case ARM::Q15: return ARM::D30;
2989 /// Parse a register list.
2991 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2992 assert(Parser.getTok().is(AsmToken::LCurly) &&
2993 "Token is not a Left Curly Brace");
2994 SMLoc S = Parser.getTok().getLoc();
2995 Parser.Lex(); // Eat '{' token.
2996 SMLoc RegLoc = Parser.getTok().getLoc();
2998 // Check the first register in the list to see what register class
2999 // this is a list of.
3000 int Reg = tryParseRegister();
3002 return Error(RegLoc, "register expected");
3004 // The reglist instructions have at most 16 registers, so reserve
3005 // space for that many.
3007 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3009 // Allow Q regs and just interpret them as the two D sub-registers.
3010 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3011 Reg = getDRegFromQReg(Reg);
3012 EReg = MRI->getEncodingValue(Reg);
3013 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3016 const MCRegisterClass *RC;
3017 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3018 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3019 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3020 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3021 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3022 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3024 return Error(RegLoc, "invalid register in register list");
3026 // Store the register.
3027 EReg = MRI->getEncodingValue(Reg);
3028 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3030 // This starts immediately after the first register token in the list,
3031 // so we can see either a comma or a minus (range separator) as a legal
3033 while (Parser.getTok().is(AsmToken::Comma) ||
3034 Parser.getTok().is(AsmToken::Minus)) {
3035 if (Parser.getTok().is(AsmToken::Minus)) {
3036 Parser.Lex(); // Eat the minus.
3037 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3038 int EndReg = tryParseRegister();
3040 return Error(AfterMinusLoc, "register expected");
3041 // Allow Q regs and just interpret them as the two D sub-registers.
3042 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3043 EndReg = getDRegFromQReg(EndReg) + 1;
3044 // If the register is the same as the start reg, there's nothing
3048 // The register must be in the same register class as the first.
3049 if (!RC->contains(EndReg))
3050 return Error(AfterMinusLoc, "invalid register in register list");
3051 // Ranges must go from low to high.
3052 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3053 return Error(AfterMinusLoc, "bad range in register list");
3055 // Add all the registers in the range to the register list.
3056 while (Reg != EndReg) {
3057 Reg = getNextRegister(Reg);
3058 EReg = MRI->getEncodingValue(Reg);
3059 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3063 Parser.Lex(); // Eat the comma.
3064 RegLoc = Parser.getTok().getLoc();
3066 const AsmToken RegTok = Parser.getTok();
3067 Reg = tryParseRegister();
3069 return Error(RegLoc, "register expected");
3070 // Allow Q regs and just interpret them as the two D sub-registers.
3071 bool isQReg = false;
3072 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3073 Reg = getDRegFromQReg(Reg);
3076 // The register must be in the same register class as the first.
3077 if (!RC->contains(Reg))
3078 return Error(RegLoc, "invalid register in register list");
3079 // List must be monotonically increasing.
3080 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3081 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3082 Warning(RegLoc, "register list not in ascending order");
3084 return Error(RegLoc, "register list not in ascending order");
3086 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3087 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3088 ") in register list");
3091 // VFP register lists must also be contiguous.
3092 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3094 return Error(RegLoc, "non-contiguous register range");
3095 EReg = MRI->getEncodingValue(Reg);
3096 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3098 EReg = MRI->getEncodingValue(++Reg);
3099 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3103 if (Parser.getTok().isNot(AsmToken::RCurly))
3104 return Error(Parser.getTok().getLoc(), "'}' expected");
3105 SMLoc E = Parser.getTok().getEndLoc();
3106 Parser.Lex(); // Eat '}' token.
3108 // Push the register list operand.
3109 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3111 // The ARM system instruction variants for LDM/STM have a '^' token here.
3112 if (Parser.getTok().is(AsmToken::Caret)) {
3113 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3114 Parser.Lex(); // Eat '^' token.
3120 // Helper function to parse the lane index for vector lists.
3121 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3122 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3123 Index = 0; // Always return a defined index value.
3124 if (Parser.getTok().is(AsmToken::LBrac)) {
3125 Parser.Lex(); // Eat the '['.
3126 if (Parser.getTok().is(AsmToken::RBrac)) {
3127 // "Dn[]" is the 'all lanes' syntax.
3128 LaneKind = AllLanes;
3129 EndLoc = Parser.getTok().getEndLoc();
3130 Parser.Lex(); // Eat the ']'.
3131 return MatchOperand_Success;
3134 // There's an optional '#' token here. Normally there wouldn't be, but
3135 // inline assemble puts one in, and it's friendly to accept that.
3136 if (Parser.getTok().is(AsmToken::Hash))
3137 Parser.Lex(); // Eat '#' or '$'.
3139 const MCExpr *LaneIndex;
3140 SMLoc Loc = Parser.getTok().getLoc();
3141 if (getParser().parseExpression(LaneIndex)) {
3142 Error(Loc, "illegal expression");
3143 return MatchOperand_ParseFail;
3145 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3147 Error(Loc, "lane index must be empty or an integer");
3148 return MatchOperand_ParseFail;
3150 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3151 Error(Parser.getTok().getLoc(), "']' expected");
3152 return MatchOperand_ParseFail;
3154 EndLoc = Parser.getTok().getEndLoc();
3155 Parser.Lex(); // Eat the ']'.
3156 int64_t Val = CE->getValue();
3158 // FIXME: Make this range check context sensitive for .8, .16, .32.
3159 if (Val < 0 || Val > 7) {
3160 Error(Parser.getTok().getLoc(), "lane index out of range");
3161 return MatchOperand_ParseFail;
3164 LaneKind = IndexedLane;
3165 return MatchOperand_Success;
3168 return MatchOperand_Success;
3171 // parse a vector register list
3172 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3173 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3174 VectorLaneTy LaneKind;
3176 SMLoc S = Parser.getTok().getLoc();
3177 // As an extension (to match gas), support a plain D register or Q register
3178 // (without encosing curly braces) as a single or double entry list,
3180 if (Parser.getTok().is(AsmToken::Identifier)) {
3181 SMLoc E = Parser.getTok().getEndLoc();
3182 int Reg = tryParseRegister();
3184 return MatchOperand_NoMatch;
3185 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3186 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3187 if (Res != MatchOperand_Success)
3191 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3194 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3198 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3203 return MatchOperand_Success;
3205 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3206 Reg = getDRegFromQReg(Reg);
3207 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3208 if (Res != MatchOperand_Success)
3212 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3213 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3214 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3217 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3218 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3219 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3223 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3228 return MatchOperand_Success;
3230 Error(S, "vector register expected");
3231 return MatchOperand_ParseFail;
3234 if (Parser.getTok().isNot(AsmToken::LCurly))
3235 return MatchOperand_NoMatch;
3237 Parser.Lex(); // Eat '{' token.
3238 SMLoc RegLoc = Parser.getTok().getLoc();
3240 int Reg = tryParseRegister();
3242 Error(RegLoc, "register expected");
3243 return MatchOperand_ParseFail;
3247 unsigned FirstReg = Reg;
3248 // The list is of D registers, but we also allow Q regs and just interpret
3249 // them as the two D sub-registers.
3250 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3251 FirstReg = Reg = getDRegFromQReg(Reg);
3252 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3253 // it's ambiguous with four-register single spaced.
3259 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3260 return MatchOperand_ParseFail;
3262 while (Parser.getTok().is(AsmToken::Comma) ||
3263 Parser.getTok().is(AsmToken::Minus)) {
3264 if (Parser.getTok().is(AsmToken::Minus)) {
3266 Spacing = 1; // Register range implies a single spaced list.
3267 else if (Spacing == 2) {
3268 Error(Parser.getTok().getLoc(),
3269 "sequential registers in double spaced list");
3270 return MatchOperand_ParseFail;
3272 Parser.Lex(); // Eat the minus.
3273 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3274 int EndReg = tryParseRegister();
3276 Error(AfterMinusLoc, "register expected");
3277 return MatchOperand_ParseFail;
3279 // Allow Q regs and just interpret them as the two D sub-registers.
3280 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3281 EndReg = getDRegFromQReg(EndReg) + 1;
3282 // If the register is the same as the start reg, there's nothing
3286 // The register must be in the same register class as the first.
3287 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3288 Error(AfterMinusLoc, "invalid register in register list");
3289 return MatchOperand_ParseFail;
3291 // Ranges must go from low to high.
3293 Error(AfterMinusLoc, "bad range in register list");
3294 return MatchOperand_ParseFail;
3296 // Parse the lane specifier if present.
3297 VectorLaneTy NextLaneKind;
3298 unsigned NextLaneIndex;
3299 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3300 MatchOperand_Success)
3301 return MatchOperand_ParseFail;
3302 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3303 Error(AfterMinusLoc, "mismatched lane index in register list");
3304 return MatchOperand_ParseFail;
3307 // Add all the registers in the range to the register list.
3308 Count += EndReg - Reg;
3312 Parser.Lex(); // Eat the comma.
3313 RegLoc = Parser.getTok().getLoc();
3315 Reg = tryParseRegister();
3317 Error(RegLoc, "register expected");
3318 return MatchOperand_ParseFail;
3320 // vector register lists must be contiguous.
3321 // It's OK to use the enumeration values directly here rather, as the
3322 // VFP register classes have the enum sorted properly.
3324 // The list is of D registers, but we also allow Q regs and just interpret
3325 // them as the two D sub-registers.
3326 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3328 Spacing = 1; // Register range implies a single spaced list.
3329 else if (Spacing == 2) {
3331 "invalid register in double-spaced list (must be 'D' register')");
3332 return MatchOperand_ParseFail;
3334 Reg = getDRegFromQReg(Reg);
3335 if (Reg != OldReg + 1) {
3336 Error(RegLoc, "non-contiguous register range");
3337 return MatchOperand_ParseFail;
3341 // Parse the lane specifier if present.
3342 VectorLaneTy NextLaneKind;
3343 unsigned NextLaneIndex;
3344 SMLoc LaneLoc = Parser.getTok().getLoc();
3345 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3346 MatchOperand_Success)
3347 return MatchOperand_ParseFail;
3348 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3349 Error(LaneLoc, "mismatched lane index in register list");
3350 return MatchOperand_ParseFail;
3354 // Normal D register.
3355 // Figure out the register spacing (single or double) of the list if
3356 // we don't know it already.
3358 Spacing = 1 + (Reg == OldReg + 2);
3360 // Just check that it's contiguous and keep going.
3361 if (Reg != OldReg + Spacing) {
3362 Error(RegLoc, "non-contiguous register range");
3363 return MatchOperand_ParseFail;
3366 // Parse the lane specifier if present.
3367 VectorLaneTy NextLaneKind;
3368 unsigned NextLaneIndex;
3369 SMLoc EndLoc = Parser.getTok().getLoc();
3370 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3371 return MatchOperand_ParseFail;
3372 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3373 Error(EndLoc, "mismatched lane index in register list");
3374 return MatchOperand_ParseFail;
3378 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3379 Error(Parser.getTok().getLoc(), "'}' expected");
3380 return MatchOperand_ParseFail;
3382 E = Parser.getTok().getEndLoc();
3383 Parser.Lex(); // Eat '}' token.
3387 // Two-register operands have been converted to the
3388 // composite register classes.
3390 const MCRegisterClass *RC = (Spacing == 1) ?
3391 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3392 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3393 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3396 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3397 (Spacing == 2), S, E));
3400 // Two-register operands have been converted to the
3401 // composite register classes.
3403 const MCRegisterClass *RC = (Spacing == 1) ?
3404 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3405 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3406 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3408 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3413 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3419 return MatchOperand_Success;
3422 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3423 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3424 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3425 SMLoc S = Parser.getTok().getLoc();
3426 const AsmToken &Tok = Parser.getTok();
3429 if (Tok.is(AsmToken::Identifier)) {
3430 StringRef OptStr = Tok.getString();
3432 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3433 .Case("sy", ARM_MB::SY)
3434 .Case("st", ARM_MB::ST)
3435 .Case("sh", ARM_MB::ISH)
3436 .Case("ish", ARM_MB::ISH)
3437 .Case("shst", ARM_MB::ISHST)
3438 .Case("ishst", ARM_MB::ISHST)
3439 .Case("nsh", ARM_MB::NSH)
3440 .Case("un", ARM_MB::NSH)
3441 .Case("nshst", ARM_MB::NSHST)
3442 .Case("unst", ARM_MB::NSHST)
3443 .Case("osh", ARM_MB::OSH)
3444 .Case("oshst", ARM_MB::OSHST)
3448 return MatchOperand_NoMatch;
3450 Parser.Lex(); // Eat identifier token.
3451 } else if (Tok.is(AsmToken::Hash) ||
3452 Tok.is(AsmToken::Dollar) ||
3453 Tok.is(AsmToken::Integer)) {
3454 if (Parser.getTok().isNot(AsmToken::Integer))
3455 Parser.Lex(); // Eat '#' or '$'.
3456 SMLoc Loc = Parser.getTok().getLoc();
3458 const MCExpr *MemBarrierID;
3459 if (getParser().parseExpression(MemBarrierID)) {
3460 Error(Loc, "illegal expression");
3461 return MatchOperand_ParseFail;
3464 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3466 Error(Loc, "constant expression expected");
3467 return MatchOperand_ParseFail;
3470 int Val = CE->getValue();
3472 Error(Loc, "immediate value out of range");
3473 return MatchOperand_ParseFail;
3476 Opt = ARM_MB::RESERVED_0 + Val;
3478 return MatchOperand_ParseFail;
3480 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3481 return MatchOperand_Success;
3484 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3485 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3486 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3487 SMLoc S = Parser.getTok().getLoc();
3488 const AsmToken &Tok = Parser.getTok();
3491 if (Tok.is(AsmToken::Identifier)) {
3492 StringRef OptStr = Tok.getString();
3494 if (OptStr.lower() == "sy")
3497 return MatchOperand_NoMatch;
3499 Parser.Lex(); // Eat identifier token.
3500 } else if (Tok.is(AsmToken::Hash) ||
3501 Tok.is(AsmToken::Dollar) ||
3502 Tok.is(AsmToken::Integer)) {
3503 if (Parser.getTok().isNot(AsmToken::Integer))
3504 Parser.Lex(); // Eat '#' or '$'.
3505 SMLoc Loc = Parser.getTok().getLoc();
3507 const MCExpr *ISBarrierID;
3508 if (getParser().parseExpression(ISBarrierID)) {
3509 Error(Loc, "illegal expression");
3510 return MatchOperand_ParseFail;
3513 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3515 Error(Loc, "constant expression expected");
3516 return MatchOperand_ParseFail;
3519 int Val = CE->getValue();
3521 Error(Loc, "immediate value out of range");
3522 return MatchOperand_ParseFail;
3525 Opt = ARM_ISB::RESERVED_0 + Val;
3527 return MatchOperand_ParseFail;
3529 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3530 (ARM_ISB::InstSyncBOpt)Opt, S));
3531 return MatchOperand_Success;
3535 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3536 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3537 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3538 SMLoc S = Parser.getTok().getLoc();
3539 const AsmToken &Tok = Parser.getTok();
3540 if (!Tok.is(AsmToken::Identifier))
3541 return MatchOperand_NoMatch;
3542 StringRef IFlagsStr = Tok.getString();
3544 // An iflags string of "none" is interpreted to mean that none of the AIF
3545 // bits are set. Not a terribly useful instruction, but a valid encoding.
3546 unsigned IFlags = 0;
3547 if (IFlagsStr != "none") {
3548 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3549 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3550 .Case("a", ARM_PROC::A)
3551 .Case("i", ARM_PROC::I)
3552 .Case("f", ARM_PROC::F)
3555 // If some specific iflag is already set, it means that some letter is
3556 // present more than once, this is not acceptable.
3557 if (Flag == ~0U || (IFlags & Flag))
3558 return MatchOperand_NoMatch;
3564 Parser.Lex(); // Eat identifier token.
3565 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3566 return MatchOperand_Success;
3569 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3570 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3571 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3572 SMLoc S = Parser.getTok().getLoc();
3573 const AsmToken &Tok = Parser.getTok();
3574 if (!Tok.is(AsmToken::Identifier))
3575 return MatchOperand_NoMatch;
3576 StringRef Mask = Tok.getString();
3579 // See ARMv6-M 10.1.1
3580 std::string Name = Mask.lower();
3581 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3582 // Note: in the documentation:
3583 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3584 // for MSR APSR_nzcvq.
3585 // but we do make it an alias here. This is so to get the "mask encoding"
3586 // bits correct on MSR APSR writes.
3588 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3589 // should really only be allowed when writing a special register. Note
3590 // they get dropped in the MRS instruction reading a special register as
3591 // the SYSm field is only 8 bits.
3593 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3594 // includes the DSP extension but that is not checked.
3595 .Case("apsr", 0x800)
3596 .Case("apsr_nzcvq", 0x800)
3597 .Case("apsr_g", 0x400)
3598 .Case("apsr_nzcvqg", 0xc00)
3599 .Case("iapsr", 0x801)
3600 .Case("iapsr_nzcvq", 0x801)
3601 .Case("iapsr_g", 0x401)
3602 .Case("iapsr_nzcvqg", 0xc01)
3603 .Case("eapsr", 0x802)
3604 .Case("eapsr_nzcvq", 0x802)
3605 .Case("eapsr_g", 0x402)
3606 .Case("eapsr_nzcvqg", 0xc02)
3607 .Case("xpsr", 0x803)
3608 .Case("xpsr_nzcvq", 0x803)
3609 .Case("xpsr_g", 0x403)
3610 .Case("xpsr_nzcvqg", 0xc03)
3611 .Case("ipsr", 0x805)
3612 .Case("epsr", 0x806)
3613 .Case("iepsr", 0x807)
3616 .Case("primask", 0x810)
3617 .Case("basepri", 0x811)
3618 .Case("basepri_max", 0x812)
3619 .Case("faultmask", 0x813)
3620 .Case("control", 0x814)
3623 if (FlagsVal == ~0U)
3624 return MatchOperand_NoMatch;
3626 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3627 // basepri, basepri_max and faultmask only valid for V7m.
3628 return MatchOperand_NoMatch;
3630 Parser.Lex(); // Eat identifier token.
3631 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3632 return MatchOperand_Success;
3635 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3636 size_t Start = 0, Next = Mask.find('_');
3637 StringRef Flags = "";
3638 std::string SpecReg = Mask.slice(Start, Next).lower();
3639 if (Next != StringRef::npos)
3640 Flags = Mask.slice(Next+1, Mask.size());
3642 // FlagsVal contains the complete mask:
3644 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3645 unsigned FlagsVal = 0;
3647 if (SpecReg == "apsr") {
3648 FlagsVal = StringSwitch<unsigned>(Flags)
3649 .Case("nzcvq", 0x8) // same as CPSR_f
3650 .Case("g", 0x4) // same as CPSR_s
3651 .Case("nzcvqg", 0xc) // same as CPSR_fs
3654 if (FlagsVal == ~0U) {
3656 return MatchOperand_NoMatch;
3658 FlagsVal = 8; // No flag
3660 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3661 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3662 if (Flags == "all" || Flags == "")
3664 for (int i = 0, e = Flags.size(); i != e; ++i) {
3665 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3672 // If some specific flag is already set, it means that some letter is
3673 // present more than once, this is not acceptable.
3674 if (FlagsVal == ~0U || (FlagsVal & Flag))
3675 return MatchOperand_NoMatch;
3678 } else // No match for special register.
3679 return MatchOperand_NoMatch;
3681 // Special register without flags is NOT equivalent to "fc" flags.
3682 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3683 // two lines would enable gas compatibility at the expense of breaking
3689 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3690 if (SpecReg == "spsr")
3693 Parser.Lex(); // Eat identifier token.
3694 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3695 return MatchOperand_Success;
3698 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3699 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3700 int Low, int High) {
3701 const AsmToken &Tok = Parser.getTok();
3702 if (Tok.isNot(AsmToken::Identifier)) {
3703 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3704 return MatchOperand_ParseFail;
3706 StringRef ShiftName = Tok.getString();
3707 std::string LowerOp = Op.lower();
3708 std::string UpperOp = Op.upper();
3709 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3710 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3711 return MatchOperand_ParseFail;
3713 Parser.Lex(); // Eat shift type token.
3715 // There must be a '#' and a shift amount.
3716 if (Parser.getTok().isNot(AsmToken::Hash) &&
3717 Parser.getTok().isNot(AsmToken::Dollar)) {
3718 Error(Parser.getTok().getLoc(), "'#' expected");
3719 return MatchOperand_ParseFail;
3721 Parser.Lex(); // Eat hash token.
3723 const MCExpr *ShiftAmount;
3724 SMLoc Loc = Parser.getTok().getLoc();
3726 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3727 Error(Loc, "illegal expression");
3728 return MatchOperand_ParseFail;
3730 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3732 Error(Loc, "constant expression expected");
3733 return MatchOperand_ParseFail;
3735 int Val = CE->getValue();
3736 if (Val < Low || Val > High) {
3737 Error(Loc, "immediate value out of range");
3738 return MatchOperand_ParseFail;
3741 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3743 return MatchOperand_Success;
3746 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3747 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3748 const AsmToken &Tok = Parser.getTok();
3749 SMLoc S = Tok.getLoc();
3750 if (Tok.isNot(AsmToken::Identifier)) {
3751 Error(S, "'be' or 'le' operand expected");
3752 return MatchOperand_ParseFail;
3754 int Val = StringSwitch<int>(Tok.getString().lower())
3758 Parser.Lex(); // Eat the token.
3761 Error(S, "'be' or 'le' operand expected");
3762 return MatchOperand_ParseFail;
3764 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3766 S, Tok.getEndLoc()));
3767 return MatchOperand_Success;
3770 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3771 /// instructions. Legal values are:
3772 /// lsl #n 'n' in [0,31]
3773 /// asr #n 'n' in [1,32]
3774 /// n == 32 encoded as n == 0.
3775 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3776 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3777 const AsmToken &Tok = Parser.getTok();
3778 SMLoc S = Tok.getLoc();
3779 if (Tok.isNot(AsmToken::Identifier)) {
3780 Error(S, "shift operator 'asr' or 'lsl' expected");
3781 return MatchOperand_ParseFail;
3783 StringRef ShiftName = Tok.getString();
3785 if (ShiftName == "lsl" || ShiftName == "LSL")
3787 else if (ShiftName == "asr" || ShiftName == "ASR")
3790 Error(S, "shift operator 'asr' or 'lsl' expected");
3791 return MatchOperand_ParseFail;
3793 Parser.Lex(); // Eat the operator.
3795 // A '#' and a shift amount.
3796 if (Parser.getTok().isNot(AsmToken::Hash) &&
3797 Parser.getTok().isNot(AsmToken::Dollar)) {
3798 Error(Parser.getTok().getLoc(), "'#' expected");
3799 return MatchOperand_ParseFail;
3801 Parser.Lex(); // Eat hash token.
3802 SMLoc ExLoc = Parser.getTok().getLoc();
3804 const MCExpr *ShiftAmount;
3806 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3807 Error(ExLoc, "malformed shift expression");
3808 return MatchOperand_ParseFail;
3810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3812 Error(ExLoc, "shift amount must be an immediate");
3813 return MatchOperand_ParseFail;
3816 int64_t Val = CE->getValue();
3818 // Shift amount must be in [1,32]
3819 if (Val < 1 || Val > 32) {
3820 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3821 return MatchOperand_ParseFail;
3823 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3824 if (isThumb() && Val == 32) {
3825 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3826 return MatchOperand_ParseFail;
3828 if (Val == 32) Val = 0;
3830 // Shift amount must be in [1,32]
3831 if (Val < 0 || Val > 31) {
3832 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3833 return MatchOperand_ParseFail;
3837 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3839 return MatchOperand_Success;
3842 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3843 /// of instructions. Legal values are:
3844 /// ror #n 'n' in {0, 8, 16, 24}
3845 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3846 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3847 const AsmToken &Tok = Parser.getTok();
3848 SMLoc S = Tok.getLoc();
3849 if (Tok.isNot(AsmToken::Identifier))
3850 return MatchOperand_NoMatch;
3851 StringRef ShiftName = Tok.getString();
3852 if (ShiftName != "ror" && ShiftName != "ROR")
3853 return MatchOperand_NoMatch;
3854 Parser.Lex(); // Eat the operator.
3856 // A '#' and a rotate amount.
3857 if (Parser.getTok().isNot(AsmToken::Hash) &&
3858 Parser.getTok().isNot(AsmToken::Dollar)) {
3859 Error(Parser.getTok().getLoc(), "'#' expected");
3860 return MatchOperand_ParseFail;
3862 Parser.Lex(); // Eat hash token.
3863 SMLoc ExLoc = Parser.getTok().getLoc();
3865 const MCExpr *ShiftAmount;
3867 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3868 Error(ExLoc, "malformed rotate expression");
3869 return MatchOperand_ParseFail;
3871 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3873 Error(ExLoc, "rotate amount must be an immediate");
3874 return MatchOperand_ParseFail;
3877 int64_t Val = CE->getValue();
3878 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3879 // normally, zero is represented in asm by omitting the rotate operand
3881 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3882 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3883 return MatchOperand_ParseFail;
3886 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3888 return MatchOperand_Success;
3891 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3892 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3893 SMLoc S = Parser.getTok().getLoc();
3894 // The bitfield descriptor is really two operands, the LSB and the width.
3895 if (Parser.getTok().isNot(AsmToken::Hash) &&
3896 Parser.getTok().isNot(AsmToken::Dollar)) {
3897 Error(Parser.getTok().getLoc(), "'#' expected");
3898 return MatchOperand_ParseFail;
3900 Parser.Lex(); // Eat hash token.
3902 const MCExpr *LSBExpr;
3903 SMLoc E = Parser.getTok().getLoc();
3904 if (getParser().parseExpression(LSBExpr)) {
3905 Error(E, "malformed immediate expression");
3906 return MatchOperand_ParseFail;
3908 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3910 Error(E, "'lsb' operand must be an immediate");
3911 return MatchOperand_ParseFail;
3914 int64_t LSB = CE->getValue();
3915 // The LSB must be in the range [0,31]
3916 if (LSB < 0 || LSB > 31) {
3917 Error(E, "'lsb' operand must be in the range [0,31]");
3918 return MatchOperand_ParseFail;
3920 E = Parser.getTok().getLoc();
3922 // Expect another immediate operand.
3923 if (Parser.getTok().isNot(AsmToken::Comma)) {
3924 Error(Parser.getTok().getLoc(), "too few operands");
3925 return MatchOperand_ParseFail;
3927 Parser.Lex(); // Eat hash token.
3928 if (Parser.getTok().isNot(AsmToken::Hash) &&
3929 Parser.getTok().isNot(AsmToken::Dollar)) {
3930 Error(Parser.getTok().getLoc(), "'#' expected");
3931 return MatchOperand_ParseFail;
3933 Parser.Lex(); // Eat hash token.
3935 const MCExpr *WidthExpr;
3937 if (getParser().parseExpression(WidthExpr, EndLoc)) {
3938 Error(E, "malformed immediate expression");
3939 return MatchOperand_ParseFail;
3941 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3943 Error(E, "'width' operand must be an immediate");
3944 return MatchOperand_ParseFail;
3947 int64_t Width = CE->getValue();
3948 // The LSB must be in the range [1,32-lsb]
3949 if (Width < 1 || Width > 32 - LSB) {
3950 Error(E, "'width' operand must be in the range [1,32-lsb]");
3951 return MatchOperand_ParseFail;
3954 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3956 return MatchOperand_Success;
3959 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3960 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3961 // Check for a post-index addressing register operand. Specifically:
3962 // postidx_reg := '+' register {, shift}
3963 // | '-' register {, shift}
3964 // | register {, shift}
3966 // This method must return MatchOperand_NoMatch without consuming any tokens
3967 // in the case where there is no match, as other alternatives take other
3969 AsmToken Tok = Parser.getTok();
3970 SMLoc S = Tok.getLoc();
3971 bool haveEaten = false;
3973 if (Tok.is(AsmToken::Plus)) {
3974 Parser.Lex(); // Eat the '+' token.
3976 } else if (Tok.is(AsmToken::Minus)) {
3977 Parser.Lex(); // Eat the '-' token.
3982 SMLoc E = Parser.getTok().getEndLoc();
3983 int Reg = tryParseRegister();
3986 return MatchOperand_NoMatch;
3987 Error(Parser.getTok().getLoc(), "register expected");
3988 return MatchOperand_ParseFail;
3991 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3992 unsigned ShiftImm = 0;
3993 if (Parser.getTok().is(AsmToken::Comma)) {
3994 Parser.Lex(); // Eat the ','.
3995 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3996 return MatchOperand_ParseFail;
3998 // FIXME: Only approximates end...may include intervening whitespace.
3999 E = Parser.getTok().getLoc();
4002 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4005 return MatchOperand_Success;
4008 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4009 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4010 // Check for a post-index addressing register operand. Specifically:
4011 // am3offset := '+' register
4018 // This method must return MatchOperand_NoMatch without consuming any tokens
4019 // in the case where there is no match, as other alternatives take other
4021 AsmToken Tok = Parser.getTok();
4022 SMLoc S = Tok.getLoc();
4024 // Do immediates first, as we always parse those if we have a '#'.
4025 if (Parser.getTok().is(AsmToken::Hash) ||
4026 Parser.getTok().is(AsmToken::Dollar)) {
4027 Parser.Lex(); // Eat '#' or '$'.
4028 // Explicitly look for a '-', as we need to encode negative zero
4030 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4031 const MCExpr *Offset;
4033 if (getParser().parseExpression(Offset, E))
4034 return MatchOperand_ParseFail;
4035 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4037 Error(S, "constant expression expected");
4038 return MatchOperand_ParseFail;
4040 // Negative zero is encoded as the flag value INT32_MIN.
4041 int32_t Val = CE->getValue();
4042 if (isNegative && Val == 0)
4046 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4048 return MatchOperand_Success;
4052 bool haveEaten = false;
4054 if (Tok.is(AsmToken::Plus)) {
4055 Parser.Lex(); // Eat the '+' token.
4057 } else if (Tok.is(AsmToken::Minus)) {
4058 Parser.Lex(); // Eat the '-' token.
4063 Tok = Parser.getTok();
4064 int Reg = tryParseRegister();
4067 return MatchOperand_NoMatch;
4068 Error(Tok.getLoc(), "register expected");
4069 return MatchOperand_ParseFail;
4072 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4073 0, S, Tok.getEndLoc()));
4075 return MatchOperand_Success;
4078 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
4079 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4080 /// when they refer multiple MIOperands inside a single one.
4082 cvtT2LdrdPre(MCInst &Inst,
4083 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4085 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4086 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4087 // Create a writeback register dummy placeholder.
4088 Inst.addOperand(MCOperand::CreateReg(0));
4090 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
4092 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4095 /// cvtT2StrdPre - Convert parsed operands to MCInst.
4096 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4097 /// when they refer multiple MIOperands inside a single one.
4099 cvtT2StrdPre(MCInst &Inst,
4100 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4101 // Create a writeback register dummy placeholder.
4102 Inst.addOperand(MCOperand::CreateReg(0));
4104 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4105 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4107 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
4109 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4112 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
4113 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4114 /// when they refer multiple MIOperands inside a single one.
4116 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
4117 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4118 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4120 // Create a writeback register dummy placeholder.
4121 Inst.addOperand(MCOperand::CreateImm(0));
4123 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
4124 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4127 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
4128 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4129 /// when they refer multiple MIOperands inside a single one.
4131 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
4132 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4133 // Create a writeback register dummy placeholder.
4134 Inst.addOperand(MCOperand::CreateImm(0));
4135 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4136 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
4137 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4140 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4141 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4142 /// when they refer multiple MIOperands inside a single one.
4144 cvtLdWriteBackRegAddrMode2(MCInst &Inst,
4145 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4146 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4148 // Create a writeback register dummy placeholder.
4149 Inst.addOperand(MCOperand::CreateImm(0));
4151 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4152 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4155 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4156 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4157 /// when they refer multiple MIOperands inside a single one.
4159 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
4160 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4161 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4163 // Create a writeback register dummy placeholder.
4164 Inst.addOperand(MCOperand::CreateImm(0));
4166 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4167 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4171 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
4172 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4173 /// when they refer multiple MIOperands inside a single one.
4175 cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
4176 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4177 // Create a writeback register dummy placeholder.
4178 Inst.addOperand(MCOperand::CreateImm(0));
4179 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4180 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
4181 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4184 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
4185 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4186 /// when they refer multiple MIOperands inside a single one.
4188 cvtStWriteBackRegAddrMode2(MCInst &Inst,
4189 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4190 // Create a writeback register dummy placeholder.
4191 Inst.addOperand(MCOperand::CreateImm(0));
4192 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4193 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4194 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4197 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4198 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4199 /// when they refer multiple MIOperands inside a single one.
4201 cvtStWriteBackRegAddrMode3(MCInst &Inst,
4202 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4203 // Create a writeback register dummy placeholder.
4204 Inst.addOperand(MCOperand::CreateImm(0));
4205 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4206 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4207 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4210 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4211 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4212 /// when they refer multiple MIOperands inside a single one.
4214 cvtLdExtTWriteBackImm(MCInst &Inst,
4215 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4217 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4218 // Create a writeback register dummy placeholder.
4219 Inst.addOperand(MCOperand::CreateImm(0));
4221 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4223 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4225 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4228 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4229 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4230 /// when they refer multiple MIOperands inside a single one.
4232 cvtLdExtTWriteBackReg(MCInst &Inst,
4233 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4235 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4236 // Create a writeback register dummy placeholder.
4237 Inst.addOperand(MCOperand::CreateImm(0));
4239 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4241 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4243 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4246 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4247 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4248 /// when they refer multiple MIOperands inside a single one.
4250 cvtStExtTWriteBackImm(MCInst &Inst,
4251 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4252 // Create a writeback register dummy placeholder.
4253 Inst.addOperand(MCOperand::CreateImm(0));
4255 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4257 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4259 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4261 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4264 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4265 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4266 /// when they refer multiple MIOperands inside a single one.
4268 cvtStExtTWriteBackReg(MCInst &Inst,
4269 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4270 // Create a writeback register dummy placeholder.
4271 Inst.addOperand(MCOperand::CreateImm(0));
4273 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4275 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4277 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4279 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4282 /// cvtLdrdPre - Convert parsed operands to MCInst.
4283 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4284 /// when they refer multiple MIOperands inside a single one.
4286 cvtLdrdPre(MCInst &Inst,
4287 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4289 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4290 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4291 // Create a writeback register dummy placeholder.
4292 Inst.addOperand(MCOperand::CreateImm(0));
4294 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4296 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4299 /// cvtStrdPre - Convert parsed operands to MCInst.
4300 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4301 /// when they refer multiple MIOperands inside a single one.
4303 cvtStrdPre(MCInst &Inst,
4304 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4305 // Create a writeback register dummy placeholder.
4306 Inst.addOperand(MCOperand::CreateImm(0));
4308 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4309 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4311 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4313 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4316 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4317 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4318 /// when they refer multiple MIOperands inside a single one.
4320 cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4321 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4322 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4323 // Create a writeback register dummy placeholder.
4324 Inst.addOperand(MCOperand::CreateImm(0));
4325 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4326 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4329 /// cvtThumbMultiply - Convert parsed operands to MCInst.
4330 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4331 /// when they refer multiple MIOperands inside a single one.
4333 cvtThumbMultiply(MCInst &Inst,
4334 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4335 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4336 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4337 // If we have a three-operand form, make sure to set Rn to be the operand
4338 // that isn't the same as Rd.
4340 if (Operands.size() == 6 &&
4341 ((ARMOperand*)Operands[4])->getReg() ==
4342 ((ARMOperand*)Operands[3])->getReg())
4344 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4345 Inst.addOperand(Inst.getOperand(0));
4346 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4350 cvtVLDwbFixed(MCInst &Inst,
4351 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4353 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4354 // Create a writeback register dummy placeholder.
4355 Inst.addOperand(MCOperand::CreateImm(0));
4357 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4359 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4363 cvtVLDwbRegister(MCInst &Inst,
4364 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4366 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4367 // Create a writeback register dummy placeholder.
4368 Inst.addOperand(MCOperand::CreateImm(0));
4370 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4372 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4374 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4378 cvtVSTwbFixed(MCInst &Inst,
4379 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4380 // Create a writeback register dummy placeholder.
4381 Inst.addOperand(MCOperand::CreateImm(0));
4383 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4385 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4387 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4391 cvtVSTwbRegister(MCInst &Inst,
4392 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4393 // Create a writeback register dummy placeholder.
4394 Inst.addOperand(MCOperand::CreateImm(0));
4396 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4398 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4400 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4402 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4405 /// Parse an ARM memory expression, return false if successful else return true
4406 /// or an error. The first token must be a '[' when called.
4408 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4410 assert(Parser.getTok().is(AsmToken::LBrac) &&
4411 "Token is not a Left Bracket");
4412 S = Parser.getTok().getLoc();
4413 Parser.Lex(); // Eat left bracket token.
4415 const AsmToken &BaseRegTok = Parser.getTok();
4416 int BaseRegNum = tryParseRegister();
4417 if (BaseRegNum == -1)
4418 return Error(BaseRegTok.getLoc(), "register expected");
4420 // The next token must either be a comma, a colon or a closing bracket.
4421 const AsmToken &Tok = Parser.getTok();
4422 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4423 !Tok.is(AsmToken::RBrac))
4424 return Error(Tok.getLoc(), "malformed memory operand");
4426 if (Tok.is(AsmToken::RBrac)) {
4427 E = Tok.getEndLoc();
4428 Parser.Lex(); // Eat right bracket token.
4430 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4431 0, 0, false, S, E));
4433 // If there's a pre-indexing writeback marker, '!', just add it as a token
4434 // operand. It's rather odd, but syntactically valid.
4435 if (Parser.getTok().is(AsmToken::Exclaim)) {
4436 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4437 Parser.Lex(); // Eat the '!'.
4443 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4444 "Lost colon or comma in memory operand?!");
4445 if (Tok.is(AsmToken::Comma)) {
4446 Parser.Lex(); // Eat the comma.
4449 // If we have a ':', it's an alignment specifier.
4450 if (Parser.getTok().is(AsmToken::Colon)) {
4451 Parser.Lex(); // Eat the ':'.
4452 E = Parser.getTok().getLoc();
4455 if (getParser().parseExpression(Expr))
4458 // The expression has to be a constant. Memory references with relocations
4459 // don't come through here, as they use the <label> forms of the relevant
4461 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4463 return Error (E, "constant expression expected");
4466 switch (CE->getValue()) {
4469 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4470 case 16: Align = 2; break;
4471 case 32: Align = 4; break;
4472 case 64: Align = 8; break;
4473 case 128: Align = 16; break;
4474 case 256: Align = 32; break;
4477 // Now we should have the closing ']'
4478 if (Parser.getTok().isNot(AsmToken::RBrac))
4479 return Error(Parser.getTok().getLoc(), "']' expected");
4480 E = Parser.getTok().getEndLoc();
4481 Parser.Lex(); // Eat right bracket token.
4483 // Don't worry about range checking the value here. That's handled by
4484 // the is*() predicates.
4485 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4486 ARM_AM::no_shift, 0, Align,
4489 // If there's a pre-indexing writeback marker, '!', just add it as a token
4491 if (Parser.getTok().is(AsmToken::Exclaim)) {
4492 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4493 Parser.Lex(); // Eat the '!'.
4499 // If we have a '#', it's an immediate offset, else assume it's a register
4500 // offset. Be friendly and also accept a plain integer (without a leading
4501 // hash) for gas compatibility.
4502 if (Parser.getTok().is(AsmToken::Hash) ||
4503 Parser.getTok().is(AsmToken::Dollar) ||
4504 Parser.getTok().is(AsmToken::Integer)) {
4505 if (Parser.getTok().isNot(AsmToken::Integer))
4506 Parser.Lex(); // Eat '#' or '$'.
4507 E = Parser.getTok().getLoc();
4509 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4510 const MCExpr *Offset;
4511 if (getParser().parseExpression(Offset))
4514 // The expression has to be a constant. Memory references with relocations
4515 // don't come through here, as they use the <label> forms of the relevant
4517 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4519 return Error (E, "constant expression expected");
4521 // If the constant was #-0, represent it as INT32_MIN.
4522 int32_t Val = CE->getValue();
4523 if (isNegative && Val == 0)
4524 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4526 // Now we should have the closing ']'
4527 if (Parser.getTok().isNot(AsmToken::RBrac))
4528 return Error(Parser.getTok().getLoc(), "']' expected");
4529 E = Parser.getTok().getEndLoc();
4530 Parser.Lex(); // Eat right bracket token.
4532 // Don't worry about range checking the value here. That's handled by
4533 // the is*() predicates.
4534 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4535 ARM_AM::no_shift, 0, 0,
4538 // If there's a pre-indexing writeback marker, '!', just add it as a token
4540 if (Parser.getTok().is(AsmToken::Exclaim)) {
4541 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4542 Parser.Lex(); // Eat the '!'.
4548 // The register offset is optionally preceded by a '+' or '-'
4549 bool isNegative = false;
4550 if (Parser.getTok().is(AsmToken::Minus)) {
4552 Parser.Lex(); // Eat the '-'.
4553 } else if (Parser.getTok().is(AsmToken::Plus)) {
4555 Parser.Lex(); // Eat the '+'.
4558 E = Parser.getTok().getLoc();
4559 int OffsetRegNum = tryParseRegister();
4560 if (OffsetRegNum == -1)
4561 return Error(E, "register expected");
4563 // If there's a shift operator, handle it.
4564 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4565 unsigned ShiftImm = 0;
4566 if (Parser.getTok().is(AsmToken::Comma)) {
4567 Parser.Lex(); // Eat the ','.
4568 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4572 // Now we should have the closing ']'
4573 if (Parser.getTok().isNot(AsmToken::RBrac))
4574 return Error(Parser.getTok().getLoc(), "']' expected");
4575 E = Parser.getTok().getEndLoc();
4576 Parser.Lex(); // Eat right bracket token.
4578 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4579 ShiftType, ShiftImm, 0, isNegative,
4582 // If there's a pre-indexing writeback marker, '!', just add it as a token
4584 if (Parser.getTok().is(AsmToken::Exclaim)) {
4585 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4586 Parser.Lex(); // Eat the '!'.
4592 /// parseMemRegOffsetShift - one of these two:
4593 /// ( lsl | lsr | asr | ror ) , # shift_amount
4595 /// return true if it parses a shift otherwise it returns false.
4596 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4598 SMLoc Loc = Parser.getTok().getLoc();
4599 const AsmToken &Tok = Parser.getTok();
4600 if (Tok.isNot(AsmToken::Identifier))
4602 StringRef ShiftName = Tok.getString();
4603 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4604 ShiftName == "asl" || ShiftName == "ASL")
4606 else if (ShiftName == "lsr" || ShiftName == "LSR")
4608 else if (ShiftName == "asr" || ShiftName == "ASR")
4610 else if (ShiftName == "ror" || ShiftName == "ROR")
4612 else if (ShiftName == "rrx" || ShiftName == "RRX")
4615 return Error(Loc, "illegal shift operator");
4616 Parser.Lex(); // Eat shift type token.
4618 // rrx stands alone.
4620 if (St != ARM_AM::rrx) {
4621 Loc = Parser.getTok().getLoc();
4622 // A '#' and a shift amount.
4623 const AsmToken &HashTok = Parser.getTok();
4624 if (HashTok.isNot(AsmToken::Hash) &&
4625 HashTok.isNot(AsmToken::Dollar))
4626 return Error(HashTok.getLoc(), "'#' expected");
4627 Parser.Lex(); // Eat hash token.
4630 if (getParser().parseExpression(Expr))
4632 // Range check the immediate.
4633 // lsl, ror: 0 <= imm <= 31
4634 // lsr, asr: 0 <= imm <= 32
4635 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4637 return Error(Loc, "shift amount must be an immediate");
4638 int64_t Imm = CE->getValue();
4640 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4641 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4642 return Error(Loc, "immediate shift value out of range");
4643 // If <ShiftTy> #0, turn it into a no_shift.
4646 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4655 /// parseFPImm - A floating point immediate expression operand.
4656 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4657 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4658 // Anything that can accept a floating point constant as an operand
4659 // needs to go through here, as the regular parseExpression is
4662 // This routine still creates a generic Immediate operand, containing
4663 // a bitcast of the 64-bit floating point value. The various operands
4664 // that accept floats can check whether the value is valid for them
4665 // via the standard is*() predicates.
4667 SMLoc S = Parser.getTok().getLoc();
4669 if (Parser.getTok().isNot(AsmToken::Hash) &&
4670 Parser.getTok().isNot(AsmToken::Dollar))
4671 return MatchOperand_NoMatch;
4673 // Disambiguate the VMOV forms that can accept an FP immediate.
4674 // vmov.f32 <sreg>, #imm
4675 // vmov.f64 <dreg>, #imm
4676 // vmov.f32 <dreg>, #imm @ vector f32x2
4677 // vmov.f32 <qreg>, #imm @ vector f32x4
4679 // There are also the NEON VMOV instructions which expect an
4680 // integer constant. Make sure we don't try to parse an FPImm
4682 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4683 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4684 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4685 TyOp->getToken() != ".f64"))
4686 return MatchOperand_NoMatch;
4688 Parser.Lex(); // Eat '#' or '$'.
4690 // Handle negation, as that still comes through as a separate token.
4691 bool isNegative = false;
4692 if (Parser.getTok().is(AsmToken::Minus)) {
4696 const AsmToken &Tok = Parser.getTok();
4697 SMLoc Loc = Tok.getLoc();
4698 if (Tok.is(AsmToken::Real)) {
4699 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4700 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4701 // If we had a '-' in front, toggle the sign bit.
4702 IntVal ^= (uint64_t)isNegative << 31;
4703 Parser.Lex(); // Eat the token.
4704 Operands.push_back(ARMOperand::CreateImm(
4705 MCConstantExpr::Create(IntVal, getContext()),
4706 S, Parser.getTok().getLoc()));
4707 return MatchOperand_Success;
4709 // Also handle plain integers. Instructions which allow floating point
4710 // immediates also allow a raw encoded 8-bit value.
4711 if (Tok.is(AsmToken::Integer)) {
4712 int64_t Val = Tok.getIntVal();
4713 Parser.Lex(); // Eat the token.
4714 if (Val > 255 || Val < 0) {
4715 Error(Loc, "encoded floating point value out of range");
4716 return MatchOperand_ParseFail;
4718 double RealVal = ARM_AM::getFPImmFloat(Val);
4719 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4720 Operands.push_back(ARMOperand::CreateImm(
4721 MCConstantExpr::Create(Val, getContext()), S,
4722 Parser.getTok().getLoc()));
4723 return MatchOperand_Success;
4726 Error(Loc, "invalid floating point immediate");
4727 return MatchOperand_ParseFail;
4730 /// Parse a arm instruction operand. For now this parses the operand regardless
4731 /// of the mnemonic.
4732 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4733 StringRef Mnemonic) {
4736 // Check if the current operand has a custom associated parser, if so, try to
4737 // custom parse the operand, or fallback to the general approach.
4738 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4739 if (ResTy == MatchOperand_Success)
4741 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4742 // there was a match, but an error occurred, in which case, just return that
4743 // the operand parsing failed.
4744 if (ResTy == MatchOperand_ParseFail)
4747 switch (getLexer().getKind()) {
4749 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4751 case AsmToken::Identifier: {
4752 // If we've seen a branch mnemonic, the next operand must be a label. This
4753 // is true even if the label is a register name. So "br r1" means branch to
4755 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4757 if (!tryParseRegisterWithWriteBack(Operands))
4759 int Res = tryParseShiftRegister(Operands);
4760 if (Res == 0) // success
4762 else if (Res == -1) // irrecoverable error
4764 // If this is VMRS, check for the apsr_nzcv operand.
4765 if (Mnemonic == "vmrs" &&
4766 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4767 S = Parser.getTok().getLoc();
4769 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4774 // Fall though for the Identifier case that is not a register or a
4777 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4778 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4779 case AsmToken::String: // quoted label names.
4780 case AsmToken::Dot: { // . as a branch target
4781 // This was not a register so parse other operands that start with an
4782 // identifier (like labels) as expressions and create them as immediates.
4783 const MCExpr *IdVal;
4784 S = Parser.getTok().getLoc();
4785 if (getParser().parseExpression(IdVal))
4787 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4788 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4791 case AsmToken::LBrac:
4792 return parseMemory(Operands);
4793 case AsmToken::LCurly:
4794 return parseRegisterList(Operands);
4795 case AsmToken::Dollar:
4796 case AsmToken::Hash: {
4797 // #42 -> immediate.
4798 S = Parser.getTok().getLoc();
4801 if (Parser.getTok().isNot(AsmToken::Colon)) {
4802 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4803 const MCExpr *ImmVal;
4804 if (getParser().parseExpression(ImmVal))
4806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4808 int32_t Val = CE->getValue();
4809 if (isNegative && Val == 0)
4810 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4812 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4813 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4815 // There can be a trailing '!' on operands that we want as a separate
4816 // '!' Token operand. Handle that here. For example, the compatibilty
4817 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4818 if (Parser.getTok().is(AsmToken::Exclaim)) {
4819 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4820 Parser.getTok().getLoc()));
4821 Parser.Lex(); // Eat exclaim token
4825 // w/ a ':' after the '#', it's just like a plain ':'.
4828 case AsmToken::Colon: {
4829 // ":lower16:" and ":upper16:" expression prefixes
4830 // FIXME: Check it's an expression prefix,
4831 // e.g. (FOO - :lower16:BAR) isn't legal.
4832 ARMMCExpr::VariantKind RefKind;
4833 if (parsePrefix(RefKind))
4836 const MCExpr *SubExprVal;
4837 if (getParser().parseExpression(SubExprVal))
4840 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4842 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4843 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4849 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4850 // :lower16: and :upper16:.
4851 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4852 RefKind = ARMMCExpr::VK_ARM_None;
4854 // :lower16: and :upper16: modifiers
4855 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4856 Parser.Lex(); // Eat ':'
4858 if (getLexer().isNot(AsmToken::Identifier)) {
4859 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4863 StringRef IDVal = Parser.getTok().getIdentifier();
4864 if (IDVal == "lower16") {
4865 RefKind = ARMMCExpr::VK_ARM_LO16;
4866 } else if (IDVal == "upper16") {
4867 RefKind = ARMMCExpr::VK_ARM_HI16;
4869 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4874 if (getLexer().isNot(AsmToken::Colon)) {
4875 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4878 Parser.Lex(); // Eat the last ':'
4882 /// \brief Given a mnemonic, split out possible predication code and carry
4883 /// setting letters to form a canonical mnemonic and flags.
4885 // FIXME: Would be nice to autogen this.
4886 // FIXME: This is a bit of a maze of special cases.
4887 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4888 unsigned &PredicationCode,
4890 unsigned &ProcessorIMod,
4891 StringRef &ITMask) {
4892 PredicationCode = ARMCC::AL;
4893 CarrySetting = false;
4896 // Ignore some mnemonics we know aren't predicated forms.
4898 // FIXME: Would be nice to autogen this.
4899 if ((Mnemonic == "movs" && isThumb()) ||
4900 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4901 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4902 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4903 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4904 Mnemonic == "vaclt" || Mnemonic == "vacle" ||
4905 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4906 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4907 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4908 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4909 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4910 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4911 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4914 // First, split out any predication code. Ignore mnemonics we know aren't
4915 // predicated but do have a carry-set and so weren't caught above.
4916 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4917 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4918 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4919 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4920 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4921 .Case("eq", ARMCC::EQ)
4922 .Case("ne", ARMCC::NE)
4923 .Case("hs", ARMCC::HS)
4924 .Case("cs", ARMCC::HS)
4925 .Case("lo", ARMCC::LO)
4926 .Case("cc", ARMCC::LO)
4927 .Case("mi", ARMCC::MI)
4928 .Case("pl", ARMCC::PL)
4929 .Case("vs", ARMCC::VS)
4930 .Case("vc", ARMCC::VC)
4931 .Case("hi", ARMCC::HI)
4932 .Case("ls", ARMCC::LS)
4933 .Case("ge", ARMCC::GE)
4934 .Case("lt", ARMCC::LT)
4935 .Case("gt", ARMCC::GT)
4936 .Case("le", ARMCC::LE)
4937 .Case("al", ARMCC::AL)
4940 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4941 PredicationCode = CC;
4945 // Next, determine if we have a carry setting bit. We explicitly ignore all
4946 // the instructions we know end in 's'.
4947 if (Mnemonic.endswith("s") &&
4948 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4949 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4950 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4951 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4952 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4953 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4954 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4955 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4956 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4957 (Mnemonic == "movs" && isThumb()))) {
4958 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4959 CarrySetting = true;
4962 // The "cps" instruction can have a interrupt mode operand which is glued into
4963 // the mnemonic. Check if this is the case, split it and parse the imod op
4964 if (Mnemonic.startswith("cps")) {
4965 // Split out any imod code.
4967 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4968 .Case("ie", ARM_PROC::IE)
4969 .Case("id", ARM_PROC::ID)
4972 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4973 ProcessorIMod = IMod;
4977 // The "it" instruction has the condition mask on the end of the mnemonic.
4978 if (Mnemonic.startswith("it")) {
4979 ITMask = Mnemonic.slice(2, Mnemonic.size());
4980 Mnemonic = Mnemonic.slice(0, 2);
4986 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4987 /// inclusion of carry set or predication code operands.
4989 // FIXME: It would be nice to autogen this.
4991 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4992 bool &CanAcceptPredicationCode) {
4993 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4994 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4995 Mnemonic == "add" || Mnemonic == "adc" ||
4996 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4997 Mnemonic == "orr" || Mnemonic == "mvn" ||
4998 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4999 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
5000 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5001 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
5002 Mnemonic == "mla" || Mnemonic == "smlal" ||
5003 Mnemonic == "umlal" || Mnemonic == "umull"))) {
5004 CanAcceptCarrySet = true;
5006 CanAcceptCarrySet = false;
5008 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5009 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5010 Mnemonic == "trap" || Mnemonic == "setend" ||
5011 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
5012 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
5013 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
5014 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
5015 Mnemonic == "vrintm") {
5016 // These mnemonics are never predicable
5017 CanAcceptPredicationCode = false;
5018 } else if (!isThumb()) {
5019 // Some instructions are only predicable in Thumb mode
5020 CanAcceptPredicationCode
5021 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5022 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5023 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5024 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5025 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5026 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5027 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
5028 } else if (isThumbOne()) {
5029 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5031 CanAcceptPredicationCode = true;
5034 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5035 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5036 // FIXME: This is all horribly hacky. We really need a better way to deal
5037 // with optional operands like this in the matcher table.
5039 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5040 // another does not. Specifically, the MOVW instruction does not. So we
5041 // special case it here and remove the defaulted (non-setting) cc_out
5042 // operand if that's the instruction we're trying to match.
5044 // We do this as post-processing of the explicit operands rather than just
5045 // conditionally adding the cc_out in the first place because we need
5046 // to check the type of the parsed immediate operand.
5047 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5048 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
5049 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
5050 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5053 // Register-register 'add' for thumb does not have a cc_out operand
5054 // when there are only two register operands.
5055 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5056 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5057 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5058 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
5060 // Register-register 'add' for thumb does not have a cc_out operand
5061 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5062 // have to check the immediate range here since Thumb2 has a variant
5063 // that can handle a different range and has a cc_out operand.
5064 if (((isThumb() && Mnemonic == "add") ||
5065 (isThumbTwo() && Mnemonic == "sub")) &&
5066 Operands.size() == 6 &&
5067 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5068 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5069 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
5070 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5071 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
5072 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
5074 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5075 // imm0_4095 variant. That's the least-preferred variant when
5076 // selecting via the generic "add" mnemonic, so to know that we
5077 // should remove the cc_out operand, we have to explicitly check that
5078 // it's not one of the other variants. Ugh.
5079 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5080 Operands.size() == 6 &&
5081 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5082 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5083 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5084 // Nest conditions rather than one big 'if' statement for readability.
5086 // If both registers are low, we're in an IT block, and the immediate is
5087 // in range, we should use encoding T1 instead, which has a cc_out.
5089 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5090 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5091 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5093 // Check against T3. If the second register is the PC, this is an
5094 // alternate form of ADR, which uses encoding T4, so check for that too.
5095 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5096 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5099 // Otherwise, we use encoding T4, which does not have a cc_out
5104 // The thumb2 multiply instruction doesn't have a CCOut register, so
5105 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5106 // use the 16-bit encoding or not.
5107 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5108 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5109 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5110 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5111 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5112 // If the registers aren't low regs, the destination reg isn't the
5113 // same as one of the source regs, or the cc_out operand is zero
5114 // outside of an IT block, we have to use the 32-bit encoding, so
5115 // remove the cc_out operand.
5116 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5117 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5118 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5120 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5121 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5122 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5123 static_cast<ARMOperand*>(Operands[4])->getReg())))
5126 // Also check the 'mul' syntax variant that doesn't specify an explicit
5127 // destination register.
5128 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5129 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5130 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5131 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5132 // If the registers aren't low regs or the cc_out operand is zero
5133 // outside of an IT block, we have to use the 32-bit encoding, so
5134 // remove the cc_out operand.
5135 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5136 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5142 // Register-register 'add/sub' for thumb does not have a cc_out operand
5143 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5144 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5145 // right, this will result in better diagnostics (which operand is off)
5147 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5148 (Operands.size() == 5 || Operands.size() == 6) &&
5149 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5150 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5151 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5152 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5153 (Operands.size() == 6 &&
5154 static_cast<ARMOperand*>(Operands[5])->isImm())))
5160 static bool isDataTypeToken(StringRef Tok) {
5161 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5162 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5163 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5164 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5165 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5166 Tok == ".f" || Tok == ".d";
5169 // FIXME: This bit should probably be handled via an explicit match class
5170 // in the .td files that matches the suffix instead of having it be
5171 // a literal string token the way it is now.
5172 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5173 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5175 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5176 unsigned VariantID);
5177 /// Parse an arm instruction mnemonic followed by its operands.
5178 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5180 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5181 // Apply mnemonic aliases before doing anything else, as the destination
5182 // mnemnonic may include suffices and we want to handle them normally.
5183 // The generic tblgen'erated code does this later, at the start of
5184 // MatchInstructionImpl(), but that's too late for aliases that include
5185 // any sort of suffix.
5186 unsigned AvailableFeatures = getAvailableFeatures();
5187 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5188 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5190 // First check for the ARM-specific .req directive.
5191 if (Parser.getTok().is(AsmToken::Identifier) &&
5192 Parser.getTok().getIdentifier() == ".req") {
5193 parseDirectiveReq(Name, NameLoc);
5194 // We always return 'error' for this, as we're done with this
5195 // statement and don't need to match the 'instruction."
5199 // Create the leading tokens for the mnemonic, split by '.' characters.
5200 size_t Start = 0, Next = Name.find('.');
5201 StringRef Mnemonic = Name.slice(Start, Next);
5203 // Split out the predication code and carry setting flag from the mnemonic.
5204 unsigned PredicationCode;
5205 unsigned ProcessorIMod;
5208 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5209 ProcessorIMod, ITMask);
5211 // In Thumb1, only the branch (B) instruction can be predicated.
5212 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5213 Parser.eatToEndOfStatement();
5214 return Error(NameLoc, "conditional execution not supported in Thumb1");
5217 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5219 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5220 // is the mask as it will be for the IT encoding if the conditional
5221 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5222 // where the conditional bit0 is zero, the instruction post-processing
5223 // will adjust the mask accordingly.
5224 if (Mnemonic == "it") {
5225 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5226 if (ITMask.size() > 3) {
5227 Parser.eatToEndOfStatement();
5228 return Error(Loc, "too many conditions on IT instruction");
5231 for (unsigned i = ITMask.size(); i != 0; --i) {
5232 char pos = ITMask[i - 1];
5233 if (pos != 't' && pos != 'e') {
5234 Parser.eatToEndOfStatement();
5235 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5238 if (ITMask[i - 1] == 't')
5241 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5244 // FIXME: This is all a pretty gross hack. We should automatically handle
5245 // optional operands like this via tblgen.
5247 // Next, add the CCOut and ConditionCode operands, if needed.
5249 // For mnemonics which can ever incorporate a carry setting bit or predication
5250 // code, our matching model involves us always generating CCOut and
5251 // ConditionCode operands to match the mnemonic "as written" and then we let
5252 // the matcher deal with finding the right instruction or generating an
5253 // appropriate error.
5254 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5255 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5257 // If we had a carry-set on an instruction that can't do that, issue an
5259 if (!CanAcceptCarrySet && CarrySetting) {
5260 Parser.eatToEndOfStatement();
5261 return Error(NameLoc, "instruction '" + Mnemonic +
5262 "' can not set flags, but 's' suffix specified");
5264 // If we had a predication code on an instruction that can't do that, issue an
5266 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5267 Parser.eatToEndOfStatement();
5268 return Error(NameLoc, "instruction '" + Mnemonic +
5269 "' is not predicable, but condition code specified");
5272 // Add the carry setting operand, if necessary.
5273 if (CanAcceptCarrySet) {
5274 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5275 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5279 // Add the predication code operand, if necessary.
5280 if (CanAcceptPredicationCode) {
5281 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5283 Operands.push_back(ARMOperand::CreateCondCode(
5284 ARMCC::CondCodes(PredicationCode), Loc));
5287 // Add the processor imod operand, if necessary.
5288 if (ProcessorIMod) {
5289 Operands.push_back(ARMOperand::CreateImm(
5290 MCConstantExpr::Create(ProcessorIMod, getContext()),
5294 // Add the remaining tokens in the mnemonic.
5295 while (Next != StringRef::npos) {
5297 Next = Name.find('.', Start + 1);
5298 StringRef ExtraToken = Name.slice(Start, Next);
5300 // Some NEON instructions have an optional datatype suffix that is
5301 // completely ignored. Check for that.
5302 if (isDataTypeToken(ExtraToken) &&
5303 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5306 // For for ARM mode generate an error if the .n qualifier is used.
5307 if (ExtraToken == ".n" && !isThumb()) {
5308 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5309 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5313 // The .n qualifier is always discarded as that is what the tables
5314 // and matcher expect. In ARM mode the .w qualifier has no effect,
5315 // so discard it to avoid errors that can be caused by the matcher.
5316 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5317 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5318 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5322 // Read the remaining operands.
5323 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5324 // Read the first operand.
5325 if (parseOperand(Operands, Mnemonic)) {
5326 Parser.eatToEndOfStatement();
5330 while (getLexer().is(AsmToken::Comma)) {
5331 Parser.Lex(); // Eat the comma.
5333 // Parse and remember the operand.
5334 if (parseOperand(Operands, Mnemonic)) {
5335 Parser.eatToEndOfStatement();
5341 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5342 SMLoc Loc = getLexer().getLoc();
5343 Parser.eatToEndOfStatement();
5344 return Error(Loc, "unexpected token in argument list");
5347 Parser.Lex(); // Consume the EndOfStatement
5349 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5350 // do and don't have a cc_out optional-def operand. With some spot-checks
5351 // of the operand list, we can figure out which variant we're trying to
5352 // parse and adjust accordingly before actually matching. We shouldn't ever
5353 // try to remove a cc_out operand that was explicitly set on the the
5354 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5355 // table driven matcher doesn't fit well with the ARM instruction set.
5356 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5357 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5358 Operands.erase(Operands.begin() + 1);
5362 // ARM mode 'blx' need special handling, as the register operand version
5363 // is predicable, but the label operand version is not. So, we can't rely
5364 // on the Mnemonic based checking to correctly figure out when to put
5365 // a k_CondCode operand in the list. If we're trying to match the label
5366 // version, remove the k_CondCode operand here.
5367 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5368 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5369 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5370 Operands.erase(Operands.begin() + 1);
5374 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5375 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5376 // a single GPRPair reg operand is used in the .td file to replace the two
5377 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5378 // expressed as a GPRPair, so we have to manually merge them.
5379 // FIXME: We would really like to be able to tablegen'erate this.
5380 if (!isThumb() && Operands.size() > 4 &&
5381 (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5382 bool isLoad = (Mnemonic == "ldrexd");
5383 unsigned Idx = isLoad ? 2 : 3;
5384 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5385 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5387 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5388 // Adjust only if Op1 and Op2 are GPRs.
5389 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5390 MRC.contains(Op2->getReg())) {
5391 unsigned Reg1 = Op1->getReg();
5392 unsigned Reg2 = Op2->getReg();
5393 unsigned Rt = MRI->getEncodingValue(Reg1);
5394 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5396 // Rt2 must be Rt + 1 and Rt must be even.
5397 if (Rt + 1 != Rt2 || (Rt & 1)) {
5398 Error(Op2->getStartLoc(), isLoad ?
5399 "destination operands must be sequential" :
5400 "source operands must be sequential");
5403 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5404 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5405 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5406 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5407 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5416 // Validate context-sensitive operand constraints.
5418 // return 'true' if register list contains non-low GPR registers,
5419 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5420 // 'containsReg' to true.
5421 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5422 unsigned HiReg, bool &containsReg) {
5423 containsReg = false;
5424 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5425 unsigned OpReg = Inst.getOperand(i).getReg();
5428 // Anything other than a low register isn't legal here.
5429 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5435 // Check if the specified regisgter is in the register list of the inst,
5436 // starting at the indicated operand number.
5437 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5438 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5439 unsigned OpReg = Inst.getOperand(i).getReg();
5446 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5447 // the ARMInsts array) instead. Getting that here requires awkward
5448 // API changes, though. Better way?
5450 extern const MCInstrDesc ARMInsts[];
5452 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5453 return ARMInsts[Opcode];
5456 // FIXME: We would really like to be able to tablegen'erate this.
5458 validateInstruction(MCInst &Inst,
5459 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5460 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5461 SMLoc Loc = Operands[0]->getStartLoc();
5462 // Check the IT block state first.
5463 // NOTE: BKPT instruction has the interesting property of being
5464 // allowed in IT blocks, but not being predicable. It just always
5466 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5467 Inst.getOpcode() != ARM::BKPT) {
5469 if (ITState.FirstCond)
5470 ITState.FirstCond = false;
5472 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5473 // The instruction must be predicable.
5474 if (!MCID.isPredicable())
5475 return Error(Loc, "instructions in IT block must be predicable");
5476 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5477 unsigned ITCond = bit ? ITState.Cond :
5478 ARMCC::getOppositeCondition(ITState.Cond);
5479 if (Cond != ITCond) {
5480 // Find the condition code Operand to get its SMLoc information.
5482 for (unsigned i = 1; i < Operands.size(); ++i)
5483 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5484 CondLoc = Operands[i]->getStartLoc();
5485 return Error(CondLoc, "incorrect condition in IT block; got '" +
5486 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5487 "', but expected '" +
5488 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5490 // Check for non-'al' condition codes outside of the IT block.
5491 } else if (isThumbTwo() && MCID.isPredicable() &&
5492 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5493 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5494 Inst.getOpcode() != ARM::t2B)
5495 return Error(Loc, "predicated instructions must be in IT block");
5497 switch (Inst.getOpcode()) {
5500 case ARM::LDRD_POST: {
5501 // Rt2 must be Rt + 1.
5502 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5503 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5505 return Error(Operands[3]->getStartLoc(),
5506 "destination operands must be sequential");
5510 // Rt2 must be Rt + 1.
5511 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5512 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5514 return Error(Operands[3]->getStartLoc(),
5515 "source operands must be sequential");
5519 case ARM::STRD_POST: {
5520 // Rt2 must be Rt + 1.
5521 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5522 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5524 return Error(Operands[3]->getStartLoc(),
5525 "source operands must be sequential");
5530 // width must be in range [1, 32-lsb]
5531 unsigned lsb = Inst.getOperand(2).getImm();
5532 unsigned widthm1 = Inst.getOperand(3).getImm();
5533 if (widthm1 >= 32 - lsb)
5534 return Error(Operands[5]->getStartLoc(),
5535 "bitfield width must be in range [1,32-lsb]");
5539 // If we're parsing Thumb2, the .w variant is available and handles
5540 // most cases that are normally illegal for a Thumb1 LDM
5541 // instruction. We'll make the transformation in processInstruction()
5544 // Thumb LDM instructions are writeback iff the base register is not
5545 // in the register list.
5546 unsigned Rn = Inst.getOperand(0).getReg();
5547 bool hasWritebackToken =
5548 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5549 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5550 bool listContainsBase;
5551 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5552 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5553 "registers must be in range r0-r7");
5554 // If we should have writeback, then there should be a '!' token.
5555 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5556 return Error(Operands[2]->getStartLoc(),
5557 "writeback operator '!' expected");
5558 // If we should not have writeback, there must not be a '!'. This is
5559 // true even for the 32-bit wide encodings.
5560 if (listContainsBase && hasWritebackToken)
5561 return Error(Operands[3]->getStartLoc(),
5562 "writeback operator '!' not allowed when base register "
5563 "in register list");
5567 case ARM::t2LDMIA_UPD: {
5568 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5569 return Error(Operands[4]->getStartLoc(),
5570 "writeback operator '!' not allowed when base register "
5571 "in register list");
5575 // The second source operand must be the same register as the destination
5578 // In this case, we must directly check the parsed operands because the
5579 // cvtThumbMultiply() function is written in such a way that it guarantees
5580 // this first statement is always true for the new Inst. Essentially, the
5581 // destination is unconditionally copied into the second source operand
5582 // without checking to see if it matches what we actually parsed.
5583 if (Operands.size() == 6 &&
5584 (((ARMOperand*)Operands[3])->getReg() !=
5585 ((ARMOperand*)Operands[5])->getReg()) &&
5586 (((ARMOperand*)Operands[3])->getReg() !=
5587 ((ARMOperand*)Operands[4])->getReg())) {
5588 return Error(Operands[3]->getStartLoc(),
5589 "destination register must match source register");
5593 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5594 // so only issue a diagnostic for thumb1. The instructions will be
5595 // switched to the t2 encodings in processInstruction() if necessary.
5597 bool listContainsBase;
5598 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5600 return Error(Operands[2]->getStartLoc(),
5601 "registers must be in range r0-r7 or pc");
5605 bool listContainsBase;
5606 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5608 return Error(Operands[2]->getStartLoc(),
5609 "registers must be in range r0-r7 or lr");
5612 case ARM::tSTMIA_UPD: {
5613 bool listContainsBase;
5614 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5615 return Error(Operands[4]->getStartLoc(),
5616 "registers must be in range r0-r7");
5619 case ARM::tADDrSP: {
5620 // If the non-SP source operand and the destination operand are not the
5621 // same, we need thumb2 (for the wide encoding), or we have an error.
5622 if (!isThumbTwo() &&
5623 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5624 return Error(Operands[4]->getStartLoc(),
5625 "source register must be the same as destination");
5634 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5636 default: llvm_unreachable("unexpected opcode!");
5638 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5639 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5640 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5641 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5642 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5643 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5644 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5645 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5646 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5649 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5650 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5651 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5652 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5653 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5655 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5656 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5657 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5658 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5659 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5661 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5662 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5663 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5664 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5665 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5668 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5669 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5670 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5671 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5672 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5673 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5674 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5675 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5676 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5677 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5678 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5679 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5680 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5681 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5682 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5685 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5686 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5687 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5688 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5689 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5690 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5691 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5692 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5693 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5694 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5695 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5696 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5697 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5698 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5699 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5700 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5701 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5702 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5705 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5706 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5707 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5708 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5709 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5710 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5711 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5712 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5713 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5714 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5715 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5716 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5717 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5718 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5719 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5722 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5723 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5724 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5725 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5726 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5727 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5728 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5729 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5730 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5731 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5732 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5733 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5734 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5735 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5736 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5737 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5738 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5739 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5743 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5745 default: llvm_unreachable("unexpected opcode!");
5747 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5748 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5749 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5750 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5751 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5752 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5753 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5754 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5755 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5758 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5759 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5760 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5761 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5762 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5763 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5764 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5765 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5766 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5767 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5768 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5769 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5770 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5771 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5772 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5775 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5776 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5777 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5778 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5779 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5780 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5781 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5782 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5783 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5784 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5785 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5786 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5787 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5788 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5789 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5790 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5791 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5792 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5795 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5796 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5797 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5798 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5799 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5800 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5801 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5802 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5803 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5804 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5805 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5806 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5807 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5808 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5809 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5812 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5813 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5814 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5815 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5816 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5817 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5818 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5819 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5820 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5821 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5822 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5823 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5824 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5825 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5826 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5827 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5828 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5829 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5832 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5833 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5834 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5835 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5836 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5837 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5838 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5839 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5840 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5841 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5842 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5843 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5844 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5845 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5846 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5849 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5850 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5851 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5852 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5853 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5854 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5855 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5856 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5857 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5858 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5859 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5860 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5861 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5862 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5863 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5864 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5865 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5866 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5869 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5870 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5871 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5872 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5873 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5874 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5875 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5876 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5877 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5878 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5879 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5880 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5881 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5882 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5883 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5884 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5885 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5886 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5891 processInstruction(MCInst &Inst,
5892 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5893 switch (Inst.getOpcode()) {
5894 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5896 if (Inst.getOperand(1).getReg() != ARM::PC ||
5897 Inst.getOperand(5).getReg() != 0)
5900 TmpInst.setOpcode(ARM::ADR);
5901 TmpInst.addOperand(Inst.getOperand(0));
5902 TmpInst.addOperand(Inst.getOperand(2));
5903 TmpInst.addOperand(Inst.getOperand(3));
5904 TmpInst.addOperand(Inst.getOperand(4));
5908 // Aliases for alternate PC+imm syntax of LDR instructions.
5909 case ARM::t2LDRpcrel:
5910 // Select the narrow version if the immediate will fit.
5911 if (Inst.getOperand(1).getImm() > 0 &&
5912 Inst.getOperand(1).getImm() <= 0xff &&
5913 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5914 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5915 Inst.setOpcode(ARM::tLDRpci);
5917 Inst.setOpcode(ARM::t2LDRpci);
5919 case ARM::t2LDRBpcrel:
5920 Inst.setOpcode(ARM::t2LDRBpci);
5922 case ARM::t2LDRHpcrel:
5923 Inst.setOpcode(ARM::t2LDRHpci);
5925 case ARM::t2LDRSBpcrel:
5926 Inst.setOpcode(ARM::t2LDRSBpci);
5928 case ARM::t2LDRSHpcrel:
5929 Inst.setOpcode(ARM::t2LDRSHpci);
5931 // Handle NEON VST complex aliases.
5932 case ARM::VST1LNdWB_register_Asm_8:
5933 case ARM::VST1LNdWB_register_Asm_16:
5934 case ARM::VST1LNdWB_register_Asm_32: {
5936 // Shuffle the operands around so the lane index operand is in the
5939 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5940 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5941 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5942 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5943 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5944 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5945 TmpInst.addOperand(Inst.getOperand(1)); // lane
5946 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5947 TmpInst.addOperand(Inst.getOperand(6));
5952 case ARM::VST2LNdWB_register_Asm_8:
5953 case ARM::VST2LNdWB_register_Asm_16:
5954 case ARM::VST2LNdWB_register_Asm_32:
5955 case ARM::VST2LNqWB_register_Asm_16:
5956 case ARM::VST2LNqWB_register_Asm_32: {
5958 // Shuffle the operands around so the lane index operand is in the
5961 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5962 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5963 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5964 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5965 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5966 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5967 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5969 TmpInst.addOperand(Inst.getOperand(1)); // lane
5970 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5971 TmpInst.addOperand(Inst.getOperand(6));
5976 case ARM::VST3LNdWB_register_Asm_8:
5977 case ARM::VST3LNdWB_register_Asm_16:
5978 case ARM::VST3LNdWB_register_Asm_32:
5979 case ARM::VST3LNqWB_register_Asm_16:
5980 case ARM::VST3LNqWB_register_Asm_32: {
5982 // Shuffle the operands around so the lane index operand is in the
5985 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5986 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5987 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5988 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5989 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5990 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5991 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5993 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5995 TmpInst.addOperand(Inst.getOperand(1)); // lane
5996 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5997 TmpInst.addOperand(Inst.getOperand(6));
6002 case ARM::VST4LNdWB_register_Asm_8:
6003 case ARM::VST4LNdWB_register_Asm_16:
6004 case ARM::VST4LNdWB_register_Asm_32:
6005 case ARM::VST4LNqWB_register_Asm_16:
6006 case ARM::VST4LNqWB_register_Asm_32: {
6008 // Shuffle the operands around so the lane index operand is in the
6011 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6012 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6013 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6014 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6015 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6016 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6017 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6019 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6021 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6023 TmpInst.addOperand(Inst.getOperand(1)); // lane
6024 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6025 TmpInst.addOperand(Inst.getOperand(6));
6030 case ARM::VST1LNdWB_fixed_Asm_8:
6031 case ARM::VST1LNdWB_fixed_Asm_16:
6032 case ARM::VST1LNdWB_fixed_Asm_32: {
6034 // Shuffle the operands around so the lane index operand is in the
6037 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6038 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6039 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6040 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6041 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6042 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6043 TmpInst.addOperand(Inst.getOperand(1)); // lane
6044 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6045 TmpInst.addOperand(Inst.getOperand(5));
6050 case ARM::VST2LNdWB_fixed_Asm_8:
6051 case ARM::VST2LNdWB_fixed_Asm_16:
6052 case ARM::VST2LNdWB_fixed_Asm_32:
6053 case ARM::VST2LNqWB_fixed_Asm_16:
6054 case ARM::VST2LNqWB_fixed_Asm_32: {
6056 // Shuffle the operands around so the lane index operand is in the
6059 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6060 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6061 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6062 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6063 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6064 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6065 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6067 TmpInst.addOperand(Inst.getOperand(1)); // lane
6068 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6069 TmpInst.addOperand(Inst.getOperand(5));
6074 case ARM::VST3LNdWB_fixed_Asm_8:
6075 case ARM::VST3LNdWB_fixed_Asm_16:
6076 case ARM::VST3LNdWB_fixed_Asm_32:
6077 case ARM::VST3LNqWB_fixed_Asm_16:
6078 case ARM::VST3LNqWB_fixed_Asm_32: {
6080 // Shuffle the operands around so the lane index operand is in the
6083 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6084 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6085 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6086 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6087 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6088 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6089 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6091 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6093 TmpInst.addOperand(Inst.getOperand(1)); // lane
6094 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6095 TmpInst.addOperand(Inst.getOperand(5));
6100 case ARM::VST4LNdWB_fixed_Asm_8:
6101 case ARM::VST4LNdWB_fixed_Asm_16:
6102 case ARM::VST4LNdWB_fixed_Asm_32:
6103 case ARM::VST4LNqWB_fixed_Asm_16:
6104 case ARM::VST4LNqWB_fixed_Asm_32: {
6106 // Shuffle the operands around so the lane index operand is in the
6109 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6110 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6111 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6112 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6113 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6114 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6115 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6117 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6119 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6121 TmpInst.addOperand(Inst.getOperand(1)); // lane
6122 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6123 TmpInst.addOperand(Inst.getOperand(5));
6128 case ARM::VST1LNdAsm_8:
6129 case ARM::VST1LNdAsm_16:
6130 case ARM::VST1LNdAsm_32: {
6132 // Shuffle the operands around so the lane index operand is in the
6135 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6136 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6137 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6138 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6139 TmpInst.addOperand(Inst.getOperand(1)); // lane
6140 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6141 TmpInst.addOperand(Inst.getOperand(5));
6146 case ARM::VST2LNdAsm_8:
6147 case ARM::VST2LNdAsm_16:
6148 case ARM::VST2LNdAsm_32:
6149 case ARM::VST2LNqAsm_16:
6150 case ARM::VST2LNqAsm_32: {
6152 // Shuffle the operands around so the lane index operand is in the
6155 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6156 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6157 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6158 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6159 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6161 TmpInst.addOperand(Inst.getOperand(1)); // lane
6162 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6163 TmpInst.addOperand(Inst.getOperand(5));
6168 case ARM::VST3LNdAsm_8:
6169 case ARM::VST3LNdAsm_16:
6170 case ARM::VST3LNdAsm_32:
6171 case ARM::VST3LNqAsm_16:
6172 case ARM::VST3LNqAsm_32: {
6174 // Shuffle the operands around so the lane index operand is in the
6177 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6178 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6179 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6180 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6181 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6183 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6185 TmpInst.addOperand(Inst.getOperand(1)); // lane
6186 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6187 TmpInst.addOperand(Inst.getOperand(5));
6192 case ARM::VST4LNdAsm_8:
6193 case ARM::VST4LNdAsm_16:
6194 case ARM::VST4LNdAsm_32:
6195 case ARM::VST4LNqAsm_16:
6196 case ARM::VST4LNqAsm_32: {
6198 // Shuffle the operands around so the lane index operand is in the
6201 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6202 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6203 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6204 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6205 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6207 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6209 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6211 TmpInst.addOperand(Inst.getOperand(1)); // lane
6212 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6213 TmpInst.addOperand(Inst.getOperand(5));
6218 // Handle NEON VLD complex aliases.
6219 case ARM::VLD1LNdWB_register_Asm_8:
6220 case ARM::VLD1LNdWB_register_Asm_16:
6221 case ARM::VLD1LNdWB_register_Asm_32: {
6223 // Shuffle the operands around so the lane index operand is in the
6226 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6227 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6228 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6229 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6230 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6231 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6232 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6233 TmpInst.addOperand(Inst.getOperand(1)); // lane
6234 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6235 TmpInst.addOperand(Inst.getOperand(6));
6240 case ARM::VLD2LNdWB_register_Asm_8:
6241 case ARM::VLD2LNdWB_register_Asm_16:
6242 case ARM::VLD2LNdWB_register_Asm_32:
6243 case ARM::VLD2LNqWB_register_Asm_16:
6244 case ARM::VLD2LNqWB_register_Asm_32: {
6246 // Shuffle the operands around so the lane index operand is in the
6249 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6250 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6251 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6253 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6254 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6255 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6256 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6257 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6258 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6260 TmpInst.addOperand(Inst.getOperand(1)); // lane
6261 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6262 TmpInst.addOperand(Inst.getOperand(6));
6267 case ARM::VLD3LNdWB_register_Asm_8:
6268 case ARM::VLD3LNdWB_register_Asm_16:
6269 case ARM::VLD3LNdWB_register_Asm_32:
6270 case ARM::VLD3LNqWB_register_Asm_16:
6271 case ARM::VLD3LNqWB_register_Asm_32: {
6273 // Shuffle the operands around so the lane index operand is in the
6276 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6277 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6278 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6280 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6282 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6283 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6284 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6285 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6286 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6287 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6289 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6291 TmpInst.addOperand(Inst.getOperand(1)); // lane
6292 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6293 TmpInst.addOperand(Inst.getOperand(6));
6298 case ARM::VLD4LNdWB_register_Asm_8:
6299 case ARM::VLD4LNdWB_register_Asm_16:
6300 case ARM::VLD4LNdWB_register_Asm_32:
6301 case ARM::VLD4LNqWB_register_Asm_16:
6302 case ARM::VLD4LNqWB_register_Asm_32: {
6304 // Shuffle the operands around so the lane index operand is in the
6307 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6308 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6309 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6311 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6313 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6315 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6316 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6317 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6318 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6319 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6320 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6322 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6324 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6326 TmpInst.addOperand(Inst.getOperand(1)); // lane
6327 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6328 TmpInst.addOperand(Inst.getOperand(6));
6333 case ARM::VLD1LNdWB_fixed_Asm_8:
6334 case ARM::VLD1LNdWB_fixed_Asm_16:
6335 case ARM::VLD1LNdWB_fixed_Asm_32: {
6337 // Shuffle the operands around so the lane index operand is in the
6340 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6341 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6342 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6343 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6344 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6345 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6346 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6347 TmpInst.addOperand(Inst.getOperand(1)); // lane
6348 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6349 TmpInst.addOperand(Inst.getOperand(5));
6354 case ARM::VLD2LNdWB_fixed_Asm_8:
6355 case ARM::VLD2LNdWB_fixed_Asm_16:
6356 case ARM::VLD2LNdWB_fixed_Asm_32:
6357 case ARM::VLD2LNqWB_fixed_Asm_16:
6358 case ARM::VLD2LNqWB_fixed_Asm_32: {
6360 // Shuffle the operands around so the lane index operand is in the
6363 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6364 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6367 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6368 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6369 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6370 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6371 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6372 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6374 TmpInst.addOperand(Inst.getOperand(1)); // lane
6375 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6376 TmpInst.addOperand(Inst.getOperand(5));
6381 case ARM::VLD3LNdWB_fixed_Asm_8:
6382 case ARM::VLD3LNdWB_fixed_Asm_16:
6383 case ARM::VLD3LNdWB_fixed_Asm_32:
6384 case ARM::VLD3LNqWB_fixed_Asm_16:
6385 case ARM::VLD3LNqWB_fixed_Asm_32: {
6387 // Shuffle the operands around so the lane index operand is in the
6390 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6391 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6392 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6394 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6396 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6397 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6398 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6399 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6400 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6401 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6403 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6405 TmpInst.addOperand(Inst.getOperand(1)); // lane
6406 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6407 TmpInst.addOperand(Inst.getOperand(5));
6412 case ARM::VLD4LNdWB_fixed_Asm_8:
6413 case ARM::VLD4LNdWB_fixed_Asm_16:
6414 case ARM::VLD4LNdWB_fixed_Asm_32:
6415 case ARM::VLD4LNqWB_fixed_Asm_16:
6416 case ARM::VLD4LNqWB_fixed_Asm_32: {
6418 // Shuffle the operands around so the lane index operand is in the
6421 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6422 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6423 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6425 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6427 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6429 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6430 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6431 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6432 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6433 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6434 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6436 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6438 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6440 TmpInst.addOperand(Inst.getOperand(1)); // lane
6441 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6442 TmpInst.addOperand(Inst.getOperand(5));
6447 case ARM::VLD1LNdAsm_8:
6448 case ARM::VLD1LNdAsm_16:
6449 case ARM::VLD1LNdAsm_32: {
6451 // Shuffle the operands around so the lane index operand is in the
6454 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6455 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6456 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6457 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6458 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6459 TmpInst.addOperand(Inst.getOperand(1)); // lane
6460 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6461 TmpInst.addOperand(Inst.getOperand(5));
6466 case ARM::VLD2LNdAsm_8:
6467 case ARM::VLD2LNdAsm_16:
6468 case ARM::VLD2LNdAsm_32:
6469 case ARM::VLD2LNqAsm_16:
6470 case ARM::VLD2LNqAsm_32: {
6472 // Shuffle the operands around so the lane index operand is in the
6475 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6476 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6477 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6479 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6480 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6481 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6482 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6484 TmpInst.addOperand(Inst.getOperand(1)); // lane
6485 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6486 TmpInst.addOperand(Inst.getOperand(5));
6491 case ARM::VLD3LNdAsm_8:
6492 case ARM::VLD3LNdAsm_16:
6493 case ARM::VLD3LNdAsm_32:
6494 case ARM::VLD3LNqAsm_16:
6495 case ARM::VLD3LNqAsm_32: {
6497 // Shuffle the operands around so the lane index operand is in the
6500 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6501 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6502 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6504 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6506 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6507 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6508 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6509 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6511 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6513 TmpInst.addOperand(Inst.getOperand(1)); // lane
6514 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6515 TmpInst.addOperand(Inst.getOperand(5));
6520 case ARM::VLD4LNdAsm_8:
6521 case ARM::VLD4LNdAsm_16:
6522 case ARM::VLD4LNdAsm_32:
6523 case ARM::VLD4LNqAsm_16:
6524 case ARM::VLD4LNqAsm_32: {
6526 // Shuffle the operands around so the lane index operand is in the
6529 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6530 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6531 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6533 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6535 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6537 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6538 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6539 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6540 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6542 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6544 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6546 TmpInst.addOperand(Inst.getOperand(1)); // lane
6547 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6548 TmpInst.addOperand(Inst.getOperand(5));
6553 // VLD3DUP single 3-element structure to all lanes instructions.
6554 case ARM::VLD3DUPdAsm_8:
6555 case ARM::VLD3DUPdAsm_16:
6556 case ARM::VLD3DUPdAsm_32:
6557 case ARM::VLD3DUPqAsm_8:
6558 case ARM::VLD3DUPqAsm_16:
6559 case ARM::VLD3DUPqAsm_32: {
6562 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6563 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6564 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6566 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6568 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6569 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6570 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6571 TmpInst.addOperand(Inst.getOperand(4));
6576 case ARM::VLD3DUPdWB_fixed_Asm_8:
6577 case ARM::VLD3DUPdWB_fixed_Asm_16:
6578 case ARM::VLD3DUPdWB_fixed_Asm_32:
6579 case ARM::VLD3DUPqWB_fixed_Asm_8:
6580 case ARM::VLD3DUPqWB_fixed_Asm_16:
6581 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6584 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6585 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6586 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6588 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6590 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6591 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6592 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6593 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6594 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6595 TmpInst.addOperand(Inst.getOperand(4));
6600 case ARM::VLD3DUPdWB_register_Asm_8:
6601 case ARM::VLD3DUPdWB_register_Asm_16:
6602 case ARM::VLD3DUPdWB_register_Asm_32:
6603 case ARM::VLD3DUPqWB_register_Asm_8:
6604 case ARM::VLD3DUPqWB_register_Asm_16:
6605 case ARM::VLD3DUPqWB_register_Asm_32: {
6608 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6609 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6610 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6612 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6614 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6615 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6616 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6617 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6618 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6619 TmpInst.addOperand(Inst.getOperand(5));
6624 // VLD3 multiple 3-element structure instructions.
6625 case ARM::VLD3dAsm_8:
6626 case ARM::VLD3dAsm_16:
6627 case ARM::VLD3dAsm_32:
6628 case ARM::VLD3qAsm_8:
6629 case ARM::VLD3qAsm_16:
6630 case ARM::VLD3qAsm_32: {
6633 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6634 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6635 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6637 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6639 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6640 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6641 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6642 TmpInst.addOperand(Inst.getOperand(4));
6647 case ARM::VLD3dWB_fixed_Asm_8:
6648 case ARM::VLD3dWB_fixed_Asm_16:
6649 case ARM::VLD3dWB_fixed_Asm_32:
6650 case ARM::VLD3qWB_fixed_Asm_8:
6651 case ARM::VLD3qWB_fixed_Asm_16:
6652 case ARM::VLD3qWB_fixed_Asm_32: {
6655 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6656 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6657 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6659 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6661 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6662 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6663 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6664 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6665 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6666 TmpInst.addOperand(Inst.getOperand(4));
6671 case ARM::VLD3dWB_register_Asm_8:
6672 case ARM::VLD3dWB_register_Asm_16:
6673 case ARM::VLD3dWB_register_Asm_32:
6674 case ARM::VLD3qWB_register_Asm_8:
6675 case ARM::VLD3qWB_register_Asm_16:
6676 case ARM::VLD3qWB_register_Asm_32: {
6679 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6680 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6681 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6683 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6685 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6686 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6687 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6688 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6689 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6690 TmpInst.addOperand(Inst.getOperand(5));
6695 // VLD4DUP single 3-element structure to all lanes instructions.
6696 case ARM::VLD4DUPdAsm_8:
6697 case ARM::VLD4DUPdAsm_16:
6698 case ARM::VLD4DUPdAsm_32:
6699 case ARM::VLD4DUPqAsm_8:
6700 case ARM::VLD4DUPqAsm_16:
6701 case ARM::VLD4DUPqAsm_32: {
6704 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6705 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6706 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6708 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6710 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6712 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6713 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6714 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6715 TmpInst.addOperand(Inst.getOperand(4));
6720 case ARM::VLD4DUPdWB_fixed_Asm_8:
6721 case ARM::VLD4DUPdWB_fixed_Asm_16:
6722 case ARM::VLD4DUPdWB_fixed_Asm_32:
6723 case ARM::VLD4DUPqWB_fixed_Asm_8:
6724 case ARM::VLD4DUPqWB_fixed_Asm_16:
6725 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6728 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6729 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6730 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6732 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6734 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6736 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6737 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6738 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6739 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6740 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6741 TmpInst.addOperand(Inst.getOperand(4));
6746 case ARM::VLD4DUPdWB_register_Asm_8:
6747 case ARM::VLD4DUPdWB_register_Asm_16:
6748 case ARM::VLD4DUPdWB_register_Asm_32:
6749 case ARM::VLD4DUPqWB_register_Asm_8:
6750 case ARM::VLD4DUPqWB_register_Asm_16:
6751 case ARM::VLD4DUPqWB_register_Asm_32: {
6754 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6755 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6756 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6758 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6760 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6762 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6763 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6764 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6765 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6766 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6767 TmpInst.addOperand(Inst.getOperand(5));
6772 // VLD4 multiple 4-element structure instructions.
6773 case ARM::VLD4dAsm_8:
6774 case ARM::VLD4dAsm_16:
6775 case ARM::VLD4dAsm_32:
6776 case ARM::VLD4qAsm_8:
6777 case ARM::VLD4qAsm_16:
6778 case ARM::VLD4qAsm_32: {
6781 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6782 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6783 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6785 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6787 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6789 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6790 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6791 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6792 TmpInst.addOperand(Inst.getOperand(4));
6797 case ARM::VLD4dWB_fixed_Asm_8:
6798 case ARM::VLD4dWB_fixed_Asm_16:
6799 case ARM::VLD4dWB_fixed_Asm_32:
6800 case ARM::VLD4qWB_fixed_Asm_8:
6801 case ARM::VLD4qWB_fixed_Asm_16:
6802 case ARM::VLD4qWB_fixed_Asm_32: {
6805 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6806 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6807 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6809 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6811 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6813 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6814 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6815 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6816 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6817 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6818 TmpInst.addOperand(Inst.getOperand(4));
6823 case ARM::VLD4dWB_register_Asm_8:
6824 case ARM::VLD4dWB_register_Asm_16:
6825 case ARM::VLD4dWB_register_Asm_32:
6826 case ARM::VLD4qWB_register_Asm_8:
6827 case ARM::VLD4qWB_register_Asm_16:
6828 case ARM::VLD4qWB_register_Asm_32: {
6831 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6832 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6833 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6835 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6837 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6839 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6840 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6841 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6842 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6843 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6844 TmpInst.addOperand(Inst.getOperand(5));
6849 // VST3 multiple 3-element structure instructions.
6850 case ARM::VST3dAsm_8:
6851 case ARM::VST3dAsm_16:
6852 case ARM::VST3dAsm_32:
6853 case ARM::VST3qAsm_8:
6854 case ARM::VST3qAsm_16:
6855 case ARM::VST3qAsm_32: {
6858 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6859 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6860 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6861 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6862 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6864 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6866 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6867 TmpInst.addOperand(Inst.getOperand(4));
6872 case ARM::VST3dWB_fixed_Asm_8:
6873 case ARM::VST3dWB_fixed_Asm_16:
6874 case ARM::VST3dWB_fixed_Asm_32:
6875 case ARM::VST3qWB_fixed_Asm_8:
6876 case ARM::VST3qWB_fixed_Asm_16:
6877 case ARM::VST3qWB_fixed_Asm_32: {
6880 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6881 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6882 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6883 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6884 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6885 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6886 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6888 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6890 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6891 TmpInst.addOperand(Inst.getOperand(4));
6896 case ARM::VST3dWB_register_Asm_8:
6897 case ARM::VST3dWB_register_Asm_16:
6898 case ARM::VST3dWB_register_Asm_32:
6899 case ARM::VST3qWB_register_Asm_8:
6900 case ARM::VST3qWB_register_Asm_16:
6901 case ARM::VST3qWB_register_Asm_32: {
6904 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6905 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6906 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6907 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6908 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6909 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6910 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6912 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6914 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6915 TmpInst.addOperand(Inst.getOperand(5));
6920 // VST4 multiple 3-element structure instructions.
6921 case ARM::VST4dAsm_8:
6922 case ARM::VST4dAsm_16:
6923 case ARM::VST4dAsm_32:
6924 case ARM::VST4qAsm_8:
6925 case ARM::VST4qAsm_16:
6926 case ARM::VST4qAsm_32: {
6929 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6930 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6931 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6932 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6933 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6935 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6937 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6939 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6940 TmpInst.addOperand(Inst.getOperand(4));
6945 case ARM::VST4dWB_fixed_Asm_8:
6946 case ARM::VST4dWB_fixed_Asm_16:
6947 case ARM::VST4dWB_fixed_Asm_32:
6948 case ARM::VST4qWB_fixed_Asm_8:
6949 case ARM::VST4qWB_fixed_Asm_16:
6950 case ARM::VST4qWB_fixed_Asm_32: {
6953 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6954 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6955 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6956 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6957 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6958 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6959 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6961 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6963 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6965 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6966 TmpInst.addOperand(Inst.getOperand(4));
6971 case ARM::VST4dWB_register_Asm_8:
6972 case ARM::VST4dWB_register_Asm_16:
6973 case ARM::VST4dWB_register_Asm_32:
6974 case ARM::VST4qWB_register_Asm_8:
6975 case ARM::VST4qWB_register_Asm_16:
6976 case ARM::VST4qWB_register_Asm_32: {
6979 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6980 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6981 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6982 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6983 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6984 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6985 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6987 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6989 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6991 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6992 TmpInst.addOperand(Inst.getOperand(5));
6997 // Handle encoding choice for the shift-immediate instructions.
7000 case ARM::t2ASRri: {
7001 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7002 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7003 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7004 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7005 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7007 switch (Inst.getOpcode()) {
7008 default: llvm_unreachable("unexpected opcode");
7009 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7010 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7011 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7013 // The Thumb1 operands aren't in the same order. Awesome, eh?
7015 TmpInst.setOpcode(NewOpc);
7016 TmpInst.addOperand(Inst.getOperand(0));
7017 TmpInst.addOperand(Inst.getOperand(5));
7018 TmpInst.addOperand(Inst.getOperand(1));
7019 TmpInst.addOperand(Inst.getOperand(2));
7020 TmpInst.addOperand(Inst.getOperand(3));
7021 TmpInst.addOperand(Inst.getOperand(4));
7028 // Handle the Thumb2 mode MOV complex aliases.
7030 case ARM::t2MOVSsr: {
7031 // Which instruction to expand to depends on the CCOut operand and
7032 // whether we're in an IT block if the register operands are low
7034 bool isNarrow = false;
7035 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7036 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7037 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7038 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7039 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7043 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7044 default: llvm_unreachable("unexpected opcode!");
7045 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7046 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7047 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7048 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7050 TmpInst.setOpcode(newOpc);
7051 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7053 TmpInst.addOperand(MCOperand::CreateReg(
7054 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7055 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7056 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7057 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7058 TmpInst.addOperand(Inst.getOperand(5));
7060 TmpInst.addOperand(MCOperand::CreateReg(
7061 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7066 case ARM::t2MOVSsi: {
7067 // Which instruction to expand to depends on the CCOut operand and
7068 // whether we're in an IT block if the register operands are low
7070 bool isNarrow = false;
7071 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7072 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7073 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7077 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7078 default: llvm_unreachable("unexpected opcode!");
7079 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7080 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7081 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7082 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7083 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7085 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7086 if (Amount == 32) Amount = 0;
7087 TmpInst.setOpcode(newOpc);
7088 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7090 TmpInst.addOperand(MCOperand::CreateReg(
7091 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7092 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7093 if (newOpc != ARM::t2RRX)
7094 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7095 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7096 TmpInst.addOperand(Inst.getOperand(4));
7098 TmpInst.addOperand(MCOperand::CreateReg(
7099 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7103 // Handle the ARM mode MOV complex aliases.
7108 ARM_AM::ShiftOpc ShiftTy;
7109 switch(Inst.getOpcode()) {
7110 default: llvm_unreachable("unexpected opcode!");
7111 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7112 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7113 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7114 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7116 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7118 TmpInst.setOpcode(ARM::MOVsr);
7119 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7120 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7121 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7122 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7123 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7124 TmpInst.addOperand(Inst.getOperand(4));
7125 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7133 ARM_AM::ShiftOpc ShiftTy;
7134 switch(Inst.getOpcode()) {
7135 default: llvm_unreachable("unexpected opcode!");
7136 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7137 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7138 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7139 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7141 // A shift by zero is a plain MOVr, not a MOVsi.
7142 unsigned Amt = Inst.getOperand(2).getImm();
7143 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7144 // A shift by 32 should be encoded as 0 when permitted
7145 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7147 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7149 TmpInst.setOpcode(Opc);
7150 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7151 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7152 if (Opc == ARM::MOVsi)
7153 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7154 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7155 TmpInst.addOperand(Inst.getOperand(4));
7156 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7161 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7163 TmpInst.setOpcode(ARM::MOVsi);
7164 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7165 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7166 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7167 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7168 TmpInst.addOperand(Inst.getOperand(3));
7169 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7173 case ARM::t2LDMIA_UPD: {
7174 // If this is a load of a single register, then we should use
7175 // a post-indexed LDR instruction instead, per the ARM ARM.
7176 if (Inst.getNumOperands() != 5)
7179 TmpInst.setOpcode(ARM::t2LDR_POST);
7180 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7181 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7182 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7183 TmpInst.addOperand(MCOperand::CreateImm(4));
7184 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7185 TmpInst.addOperand(Inst.getOperand(3));
7189 case ARM::t2STMDB_UPD: {
7190 // If this is a store of a single register, then we should use
7191 // a pre-indexed STR instruction instead, per the ARM ARM.
7192 if (Inst.getNumOperands() != 5)
7195 TmpInst.setOpcode(ARM::t2STR_PRE);
7196 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7197 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7198 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7199 TmpInst.addOperand(MCOperand::CreateImm(-4));
7200 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7201 TmpInst.addOperand(Inst.getOperand(3));
7205 case ARM::LDMIA_UPD:
7206 // If this is a load of a single register via a 'pop', then we should use
7207 // a post-indexed LDR instruction instead, per the ARM ARM.
7208 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7209 Inst.getNumOperands() == 5) {
7211 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7212 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7213 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7214 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7215 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7216 TmpInst.addOperand(MCOperand::CreateImm(4));
7217 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7218 TmpInst.addOperand(Inst.getOperand(3));
7223 case ARM::STMDB_UPD:
7224 // If this is a store of a single register via a 'push', then we should use
7225 // a pre-indexed STR instruction instead, per the ARM ARM.
7226 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7227 Inst.getNumOperands() == 5) {
7229 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7230 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7231 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7232 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7233 TmpInst.addOperand(MCOperand::CreateImm(-4));
7234 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7235 TmpInst.addOperand(Inst.getOperand(3));
7239 case ARM::t2ADDri12:
7240 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7241 // mnemonic was used (not "addw"), encoding T3 is preferred.
7242 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7243 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7245 Inst.setOpcode(ARM::t2ADDri);
7246 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7248 case ARM::t2SUBri12:
7249 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7250 // mnemonic was used (not "subw"), encoding T3 is preferred.
7251 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7252 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7254 Inst.setOpcode(ARM::t2SUBri);
7255 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7258 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7259 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7260 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7261 // to encoding T1 if <Rd> is omitted."
7262 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7263 Inst.setOpcode(ARM::tADDi3);
7268 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7269 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7270 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7271 // to encoding T1 if <Rd> is omitted."
7272 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7273 Inst.setOpcode(ARM::tSUBi3);
7278 case ARM::t2SUBri: {
7279 // If the destination and first source operand are the same, and
7280 // the flags are compatible with the current IT status, use encoding T2
7281 // instead of T3. For compatibility with the system 'as'. Make sure the
7282 // wide encoding wasn't explicit.
7283 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7284 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7285 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7286 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7287 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7288 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7289 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7292 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7293 ARM::tADDi8 : ARM::tSUBi8);
7294 TmpInst.addOperand(Inst.getOperand(0));
7295 TmpInst.addOperand(Inst.getOperand(5));
7296 TmpInst.addOperand(Inst.getOperand(0));
7297 TmpInst.addOperand(Inst.getOperand(2));
7298 TmpInst.addOperand(Inst.getOperand(3));
7299 TmpInst.addOperand(Inst.getOperand(4));
7303 case ARM::t2ADDrr: {
7304 // If the destination and first source operand are the same, and
7305 // there's no setting of the flags, use encoding T2 instead of T3.
7306 // Note that this is only for ADD, not SUB. This mirrors the system
7307 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7308 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7309 Inst.getOperand(5).getReg() != 0 ||
7310 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7311 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7314 TmpInst.setOpcode(ARM::tADDhirr);
7315 TmpInst.addOperand(Inst.getOperand(0));
7316 TmpInst.addOperand(Inst.getOperand(0));
7317 TmpInst.addOperand(Inst.getOperand(2));
7318 TmpInst.addOperand(Inst.getOperand(3));
7319 TmpInst.addOperand(Inst.getOperand(4));
7323 case ARM::tADDrSP: {
7324 // If the non-SP source operand and the destination operand are not the
7325 // same, we need to use the 32-bit encoding if it's available.
7326 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7327 Inst.setOpcode(ARM::t2ADDrr);
7328 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7334 // A Thumb conditional branch outside of an IT block is a tBcc.
7335 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7336 Inst.setOpcode(ARM::tBcc);
7341 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7342 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7343 Inst.setOpcode(ARM::t2Bcc);
7348 // If the conditional is AL or we're in an IT block, we really want t2B.
7349 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7350 Inst.setOpcode(ARM::t2B);
7355 // If the conditional is AL, we really want tB.
7356 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7357 Inst.setOpcode(ARM::tB);
7362 // If the register list contains any high registers, or if the writeback
7363 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7364 // instead if we're in Thumb2. Otherwise, this should have generated
7365 // an error in validateInstruction().
7366 unsigned Rn = Inst.getOperand(0).getReg();
7367 bool hasWritebackToken =
7368 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7369 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7370 bool listContainsBase;
7371 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7372 (!listContainsBase && !hasWritebackToken) ||
7373 (listContainsBase && hasWritebackToken)) {
7374 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7375 assert (isThumbTwo());
7376 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7377 // If we're switching to the updating version, we need to insert
7378 // the writeback tied operand.
7379 if (hasWritebackToken)
7380 Inst.insert(Inst.begin(),
7381 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7386 case ARM::tSTMIA_UPD: {
7387 // If the register list contains any high registers, we need to use
7388 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7389 // should have generated an error in validateInstruction().
7390 unsigned Rn = Inst.getOperand(0).getReg();
7391 bool listContainsBase;
7392 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7393 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7394 assert (isThumbTwo());
7395 Inst.setOpcode(ARM::t2STMIA_UPD);
7401 bool listContainsBase;
7402 // If the register list contains any high registers, we need to use
7403 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7404 // should have generated an error in validateInstruction().
7405 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7407 assert (isThumbTwo());
7408 Inst.setOpcode(ARM::t2LDMIA_UPD);
7409 // Add the base register and writeback operands.
7410 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7411 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7415 bool listContainsBase;
7416 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7418 assert (isThumbTwo());
7419 Inst.setOpcode(ARM::t2STMDB_UPD);
7420 // Add the base register and writeback operands.
7421 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7422 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7426 // If we can use the 16-bit encoding and the user didn't explicitly
7427 // request the 32-bit variant, transform it here.
7428 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7429 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7430 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7431 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7432 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7433 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7434 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7435 // The operands aren't in the same order for tMOVi8...
7437 TmpInst.setOpcode(ARM::tMOVi8);
7438 TmpInst.addOperand(Inst.getOperand(0));
7439 TmpInst.addOperand(Inst.getOperand(4));
7440 TmpInst.addOperand(Inst.getOperand(1));
7441 TmpInst.addOperand(Inst.getOperand(2));
7442 TmpInst.addOperand(Inst.getOperand(3));
7449 // If we can use the 16-bit encoding and the user didn't explicitly
7450 // request the 32-bit variant, transform it here.
7451 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7452 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7453 Inst.getOperand(2).getImm() == ARMCC::AL &&
7454 Inst.getOperand(4).getReg() == ARM::CPSR &&
7455 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7456 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7457 // The operands aren't the same for tMOV[S]r... (no cc_out)
7459 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7460 TmpInst.addOperand(Inst.getOperand(0));
7461 TmpInst.addOperand(Inst.getOperand(1));
7462 TmpInst.addOperand(Inst.getOperand(2));
7463 TmpInst.addOperand(Inst.getOperand(3));
7473 // If we can use the 16-bit encoding and the user didn't explicitly
7474 // request the 32-bit variant, transform it here.
7475 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7476 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7477 Inst.getOperand(2).getImm() == 0 &&
7478 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7479 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7481 switch (Inst.getOpcode()) {
7482 default: llvm_unreachable("Illegal opcode!");
7483 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7484 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7485 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7486 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7488 // The operands aren't the same for thumb1 (no rotate operand).
7490 TmpInst.setOpcode(NewOpc);
7491 TmpInst.addOperand(Inst.getOperand(0));
7492 TmpInst.addOperand(Inst.getOperand(1));
7493 TmpInst.addOperand(Inst.getOperand(3));
7494 TmpInst.addOperand(Inst.getOperand(4));
7501 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7502 // rrx shifts and asr/lsr of #32 is encoded as 0
7503 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7505 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7506 // Shifting by zero is accepted as a vanilla 'MOVr'
7508 TmpInst.setOpcode(ARM::MOVr);
7509 TmpInst.addOperand(Inst.getOperand(0));
7510 TmpInst.addOperand(Inst.getOperand(1));
7511 TmpInst.addOperand(Inst.getOperand(3));
7512 TmpInst.addOperand(Inst.getOperand(4));
7513 TmpInst.addOperand(Inst.getOperand(5));
7526 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7527 if (SOpc == ARM_AM::rrx) return false;
7528 switch (Inst.getOpcode()) {
7529 default: llvm_unreachable("unexpected opcode!");
7530 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7531 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7532 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7533 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7534 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7535 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7537 // If the shift is by zero, use the non-shifted instruction definition.
7538 // The exception is for right shifts, where 0 == 32
7539 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7540 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7542 TmpInst.setOpcode(newOpc);
7543 TmpInst.addOperand(Inst.getOperand(0));
7544 TmpInst.addOperand(Inst.getOperand(1));
7545 TmpInst.addOperand(Inst.getOperand(2));
7546 TmpInst.addOperand(Inst.getOperand(4));
7547 TmpInst.addOperand(Inst.getOperand(5));
7548 TmpInst.addOperand(Inst.getOperand(6));
7556 // The mask bits for all but the first condition are represented as
7557 // the low bit of the condition code value implies 't'. We currently
7558 // always have 1 implies 't', so XOR toggle the bits if the low bit
7559 // of the condition code is zero.
7560 MCOperand &MO = Inst.getOperand(1);
7561 unsigned Mask = MO.getImm();
7562 unsigned OrigMask = Mask;
7563 unsigned TZ = countTrailingZeros(Mask);
7564 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7565 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7566 Mask ^= (0xE << TZ) & 0xF;
7570 // Set up the IT block state according to the IT instruction we just
7572 assert(!inITBlock() && "nested IT blocks?!");
7573 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7574 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7575 ITState.CurPosition = 0;
7576 ITState.FirstCond = true;
7586 // Assemblers should use the narrow encodings of these instructions when permissible.
7587 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7588 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7589 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7590 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7591 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7592 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7593 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7595 switch (Inst.getOpcode()) {
7596 default: llvm_unreachable("unexpected opcode");
7597 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7598 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7599 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7600 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7601 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7602 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7605 TmpInst.setOpcode(NewOpc);
7606 TmpInst.addOperand(Inst.getOperand(0));
7607 TmpInst.addOperand(Inst.getOperand(5));
7608 TmpInst.addOperand(Inst.getOperand(1));
7609 TmpInst.addOperand(Inst.getOperand(2));
7610 TmpInst.addOperand(Inst.getOperand(3));
7611 TmpInst.addOperand(Inst.getOperand(4));
7622 // Assemblers should use the narrow encodings of these instructions when permissible.
7623 // These instructions are special in that they are commutable, so shorter encodings
7624 // are available more often.
7625 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7626 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7627 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7628 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7629 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7630 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7631 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7632 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7634 switch (Inst.getOpcode()) {
7635 default: llvm_unreachable("unexpected opcode");
7636 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7637 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7638 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7639 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7642 TmpInst.setOpcode(NewOpc);
7643 TmpInst.addOperand(Inst.getOperand(0));
7644 TmpInst.addOperand(Inst.getOperand(5));
7645 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7646 TmpInst.addOperand(Inst.getOperand(1));
7647 TmpInst.addOperand(Inst.getOperand(2));
7649 TmpInst.addOperand(Inst.getOperand(2));
7650 TmpInst.addOperand(Inst.getOperand(1));
7652 TmpInst.addOperand(Inst.getOperand(3));
7653 TmpInst.addOperand(Inst.getOperand(4));
7663 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7664 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7665 // suffix depending on whether they're in an IT block or not.
7666 unsigned Opc = Inst.getOpcode();
7667 const MCInstrDesc &MCID = getInstDesc(Opc);
7668 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7669 assert(MCID.hasOptionalDef() &&
7670 "optionally flag setting instruction missing optional def operand");
7671 assert(MCID.NumOperands == Inst.getNumOperands() &&
7672 "operand count mismatch!");
7673 // Find the optional-def operand (cc_out).
7676 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7679 // If we're parsing Thumb1, reject it completely.
7680 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7681 return Match_MnemonicFail;
7682 // If we're parsing Thumb2, which form is legal depends on whether we're
7684 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7686 return Match_RequiresITBlock;
7687 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7689 return Match_RequiresNotITBlock;
7691 // Some high-register supporting Thumb1 encodings only allow both registers
7692 // to be from r0-r7 when in Thumb2.
7693 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7694 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7695 isARMLowRegister(Inst.getOperand(2).getReg()))
7696 return Match_RequiresThumb2;
7697 // Others only require ARMv6 or later.
7698 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7699 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7700 isARMLowRegister(Inst.getOperand(1).getReg()))
7701 return Match_RequiresV6;
7702 return Match_Success;
7705 static const char *getSubtargetFeatureName(unsigned Val);
7707 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7708 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7709 MCStreamer &Out, unsigned &ErrorInfo,
7710 bool MatchingInlineAsm) {
7712 unsigned MatchResult;
7714 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7716 switch (MatchResult) {
7719 // Context sensitive operand constraints aren't handled by the matcher,
7720 // so check them here.
7721 if (validateInstruction(Inst, Operands)) {
7722 // Still progress the IT block, otherwise one wrong condition causes
7723 // nasty cascading errors.
7724 forwardITPosition();
7728 // Some instructions need post-processing to, for example, tweak which
7729 // encoding is selected. Loop on it while changes happen so the
7730 // individual transformations can chain off each other. E.g.,
7731 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7732 while (processInstruction(Inst, Operands))
7735 // Only move forward at the very end so that everything in validate
7736 // and process gets a consistent answer about whether we're in an IT
7738 forwardITPosition();
7740 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7741 // doesn't actually encode.
7742 if (Inst.getOpcode() == ARM::ITasm)
7746 Out.EmitInstruction(Inst);
7748 case Match_MissingFeature: {
7749 assert(ErrorInfo && "Unknown missing feature!");
7750 // Special case the error message for the very common case where only
7751 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7752 std::string Msg = "instruction requires:";
7754 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7755 if (ErrorInfo & Mask) {
7757 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7761 return Error(IDLoc, Msg);
7763 case Match_InvalidOperand: {
7764 SMLoc ErrorLoc = IDLoc;
7765 if (ErrorInfo != ~0U) {
7766 if (ErrorInfo >= Operands.size())
7767 return Error(IDLoc, "too few operands for instruction");
7769 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7770 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7773 return Error(ErrorLoc, "invalid operand for instruction");
7775 case Match_MnemonicFail:
7776 return Error(IDLoc, "invalid instruction",
7777 ((ARMOperand*)Operands[0])->getLocRange());
7778 case Match_RequiresNotITBlock:
7779 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7780 case Match_RequiresITBlock:
7781 return Error(IDLoc, "instruction only valid inside IT block");
7782 case Match_RequiresV6:
7783 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7784 case Match_RequiresThumb2:
7785 return Error(IDLoc, "instruction variant requires Thumb2");
7786 case Match_ImmRange0_4: {
7787 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7788 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7789 return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7791 case Match_ImmRange0_15: {
7792 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7793 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7794 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7798 llvm_unreachable("Implement any new match types added!");
7801 /// parseDirective parses the arm specific directives
7802 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7803 StringRef IDVal = DirectiveID.getIdentifier();
7804 if (IDVal == ".word")
7805 return parseDirectiveWord(4, DirectiveID.getLoc());
7806 else if (IDVal == ".thumb")
7807 return parseDirectiveThumb(DirectiveID.getLoc());
7808 else if (IDVal == ".arm")
7809 return parseDirectiveARM(DirectiveID.getLoc());
7810 else if (IDVal == ".thumb_func")
7811 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7812 else if (IDVal == ".code")
7813 return parseDirectiveCode(DirectiveID.getLoc());
7814 else if (IDVal == ".syntax")
7815 return parseDirectiveSyntax(DirectiveID.getLoc());
7816 else if (IDVal == ".unreq")
7817 return parseDirectiveUnreq(DirectiveID.getLoc());
7818 else if (IDVal == ".arch")
7819 return parseDirectiveArch(DirectiveID.getLoc());
7820 else if (IDVal == ".eabi_attribute")
7821 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7822 else if (IDVal == ".fnstart")
7823 return parseDirectiveFnStart(DirectiveID.getLoc());
7824 else if (IDVal == ".fnend")
7825 return parseDirectiveFnEnd(DirectiveID.getLoc());
7826 else if (IDVal == ".cantunwind")
7827 return parseDirectiveCantUnwind(DirectiveID.getLoc());
7828 else if (IDVal == ".personality")
7829 return parseDirectivePersonality(DirectiveID.getLoc());
7830 else if (IDVal == ".handlerdata")
7831 return parseDirectiveHandlerData(DirectiveID.getLoc());
7832 else if (IDVal == ".setfp")
7833 return parseDirectiveSetFP(DirectiveID.getLoc());
7834 else if (IDVal == ".pad")
7835 return parseDirectivePad(DirectiveID.getLoc());
7836 else if (IDVal == ".save")
7837 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7838 else if (IDVal == ".vsave")
7839 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7843 /// parseDirectiveWord
7844 /// ::= .word [ expression (, expression)* ]
7845 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7846 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7848 const MCExpr *Value;
7849 if (getParser().parseExpression(Value))
7852 getParser().getStreamer().EmitValue(Value, Size);
7854 if (getLexer().is(AsmToken::EndOfStatement))
7857 // FIXME: Improve diagnostic.
7858 if (getLexer().isNot(AsmToken::Comma))
7859 return Error(L, "unexpected token in directive");
7868 /// parseDirectiveThumb
7870 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7871 if (getLexer().isNot(AsmToken::EndOfStatement))
7872 return Error(L, "unexpected token in directive");
7876 return Error(L, "target does not support Thumb mode");
7880 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7884 /// parseDirectiveARM
7886 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7887 if (getLexer().isNot(AsmToken::EndOfStatement))
7888 return Error(L, "unexpected token in directive");
7892 return Error(L, "target does not support ARM mode");
7896 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7900 /// parseDirectiveThumbFunc
7901 /// ::= .thumbfunc symbol_name
7902 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7903 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7904 bool isMachO = MAI->hasSubsectionsViaSymbols();
7906 bool needFuncName = true;
7908 // Darwin asm has (optionally) function name after .thumb_func direction
7911 const AsmToken &Tok = Parser.getTok();
7912 if (Tok.isNot(AsmToken::EndOfStatement)) {
7913 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7914 return Error(L, "unexpected token in .thumb_func directive");
7915 Name = Tok.getIdentifier();
7916 Parser.Lex(); // Consume the identifier token.
7917 needFuncName = false;
7921 if (getLexer().isNot(AsmToken::EndOfStatement))
7922 return Error(L, "unexpected token in directive");
7924 // Eat the end of statement and any blank lines that follow.
7925 while (getLexer().is(AsmToken::EndOfStatement))
7928 // FIXME: assuming function name will be the line following .thumb_func
7929 // We really should be checking the next symbol definition even if there's
7930 // stuff in between.
7932 Name = Parser.getTok().getIdentifier();
7935 // Mark symbol as a thumb symbol.
7936 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7937 getParser().getStreamer().EmitThumbFunc(Func);
7941 /// parseDirectiveSyntax
7942 /// ::= .syntax unified | divided
7943 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7944 const AsmToken &Tok = Parser.getTok();
7945 if (Tok.isNot(AsmToken::Identifier))
7946 return Error(L, "unexpected token in .syntax directive");
7947 StringRef Mode = Tok.getString();
7948 if (Mode == "unified" || Mode == "UNIFIED")
7950 else if (Mode == "divided" || Mode == "DIVIDED")
7951 return Error(L, "'.syntax divided' arm asssembly not supported");
7953 return Error(L, "unrecognized syntax mode in .syntax directive");
7955 if (getLexer().isNot(AsmToken::EndOfStatement))
7956 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7959 // TODO tell the MC streamer the mode
7960 // getParser().getStreamer().Emit???();
7964 /// parseDirectiveCode
7965 /// ::= .code 16 | 32
7966 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7967 const AsmToken &Tok = Parser.getTok();
7968 if (Tok.isNot(AsmToken::Integer))
7969 return Error(L, "unexpected token in .code directive");
7970 int64_t Val = Parser.getTok().getIntVal();
7976 return Error(L, "invalid operand to .code directive");
7978 if (getLexer().isNot(AsmToken::EndOfStatement))
7979 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7984 return Error(L, "target does not support Thumb mode");
7988 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7991 return Error(L, "target does not support ARM mode");
7995 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8001 /// parseDirectiveReq
8002 /// ::= name .req registername
8003 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8004 Parser.Lex(); // Eat the '.req' token.
8006 SMLoc SRegLoc, ERegLoc;
8007 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8008 Parser.eatToEndOfStatement();
8009 return Error(SRegLoc, "register name expected");
8012 // Shouldn't be anything else.
8013 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8014 Parser.eatToEndOfStatement();
8015 return Error(Parser.getTok().getLoc(),
8016 "unexpected input in .req directive.");
8019 Parser.Lex(); // Consume the EndOfStatement
8021 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
8022 return Error(SRegLoc, "redefinition of '" + Name +
8023 "' does not match original.");
8028 /// parseDirectiveUneq
8029 /// ::= .unreq registername
8030 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8031 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8032 Parser.eatToEndOfStatement();
8033 return Error(L, "unexpected input in .unreq directive.");
8035 RegisterReqs.erase(Parser.getTok().getIdentifier());
8036 Parser.Lex(); // Eat the identifier.
8040 /// parseDirectiveArch
8042 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8046 /// parseDirectiveEabiAttr
8047 /// ::= .eabi_attribute int, int
8048 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8052 /// parseDirectiveFnStart
8054 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8055 if (FnStartLoc.isValid()) {
8056 Error(L, ".fnstart starts before the end of previous one");
8057 Error(FnStartLoc, "previous .fnstart starts here");
8062 getParser().getStreamer().EmitFnStart();
8066 /// parseDirectiveFnEnd
8068 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8069 // Check the ordering of unwind directives
8070 if (!FnStartLoc.isValid())
8071 return Error(L, ".fnstart must precede .fnend directive");
8073 // Reset the unwind directives parser state
8074 resetUnwindDirectiveParserState();
8076 getParser().getStreamer().EmitFnEnd();
8080 /// parseDirectiveCantUnwind
8082 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8083 // Check the ordering of unwind directives
8085 if (!FnStartLoc.isValid())
8086 return Error(L, ".fnstart must precede .cantunwind directive");
8087 if (HandlerDataLoc.isValid()) {
8088 Error(L, ".cantunwind can't be used with .handlerdata directive");
8089 Error(HandlerDataLoc, ".handlerdata was specified here");
8092 if (PersonalityLoc.isValid()) {
8093 Error(L, ".cantunwind can't be used with .personality directive");
8094 Error(PersonalityLoc, ".personality was specified here");
8098 getParser().getStreamer().EmitCantUnwind();
8102 /// parseDirectivePersonality
8103 /// ::= .personality name
8104 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8105 // Check the ordering of unwind directives
8107 if (!FnStartLoc.isValid())
8108 return Error(L, ".fnstart must precede .personality directive");
8109 if (CantUnwindLoc.isValid()) {
8110 Error(L, ".personality can't be used with .cantunwind directive");
8111 Error(CantUnwindLoc, ".cantunwind was specified here");
8114 if (HandlerDataLoc.isValid()) {
8115 Error(L, ".personality must precede .handlerdata directive");
8116 Error(HandlerDataLoc, ".handlerdata was specified here");
8120 // Parse the name of the personality routine
8121 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8122 Parser.eatToEndOfStatement();
8123 return Error(L, "unexpected input in .personality directive.");
8125 StringRef Name(Parser.getTok().getIdentifier());
8128 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8129 getParser().getStreamer().EmitPersonality(PR);
8133 /// parseDirectiveHandlerData
8134 /// ::= .handlerdata
8135 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8136 // Check the ordering of unwind directives
8138 if (!FnStartLoc.isValid())
8139 return Error(L, ".fnstart must precede .personality directive");
8140 if (CantUnwindLoc.isValid()) {
8141 Error(L, ".handlerdata can't be used with .cantunwind directive");
8142 Error(CantUnwindLoc, ".cantunwind was specified here");
8146 getParser().getStreamer().EmitHandlerData();
8150 /// parseDirectiveSetFP
8151 /// ::= .setfp fpreg, spreg [, offset]
8152 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8153 // Check the ordering of unwind directives
8154 if (!FnStartLoc.isValid())
8155 return Error(L, ".fnstart must precede .setfp directive");
8156 if (HandlerDataLoc.isValid())
8157 return Error(L, ".setfp must precede .handlerdata directive");
8160 SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8161 int NewFPReg = tryParseRegister();
8163 return Error(NewFPRegLoc, "frame pointer register expected");
8166 if (!Parser.getTok().is(AsmToken::Comma))
8167 return Error(Parser.getTok().getLoc(), "comma expected");
8168 Parser.Lex(); // skip comma
8171 SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8172 int NewSPReg = tryParseRegister();
8174 return Error(NewSPRegLoc, "stack pointer register expected");
8176 if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8177 return Error(NewSPRegLoc,
8178 "register should be either $sp or the latest fp register");
8180 // Update the frame pointer register
8185 if (Parser.getTok().is(AsmToken::Comma)) {
8186 Parser.Lex(); // skip comma
8188 if (Parser.getTok().isNot(AsmToken::Hash) &&
8189 Parser.getTok().isNot(AsmToken::Dollar)) {
8190 return Error(Parser.getTok().getLoc(), "'#' expected");
8192 Parser.Lex(); // skip hash token.
8194 const MCExpr *OffsetExpr;
8195 SMLoc ExLoc = Parser.getTok().getLoc();
8197 if (getParser().parseExpression(OffsetExpr, EndLoc))
8198 return Error(ExLoc, "malformed setfp offset");
8199 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8201 return Error(ExLoc, "setfp offset must be an immediate");
8203 Offset = CE->getValue();
8206 getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
8207 static_cast<unsigned>(NewSPReg),
8214 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8215 // Check the ordering of unwind directives
8216 if (!FnStartLoc.isValid())
8217 return Error(L, ".fnstart must precede .pad directive");
8218 if (HandlerDataLoc.isValid())
8219 return Error(L, ".pad must precede .handlerdata directive");
8222 if (Parser.getTok().isNot(AsmToken::Hash) &&
8223 Parser.getTok().isNot(AsmToken::Dollar)) {
8224 return Error(Parser.getTok().getLoc(), "'#' expected");
8226 Parser.Lex(); // skip hash token.
8228 const MCExpr *OffsetExpr;
8229 SMLoc ExLoc = Parser.getTok().getLoc();
8231 if (getParser().parseExpression(OffsetExpr, EndLoc))
8232 return Error(ExLoc, "malformed pad offset");
8233 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8235 return Error(ExLoc, "pad offset must be an immediate");
8237 getParser().getStreamer().EmitPad(CE->getValue());
8241 /// parseDirectiveRegSave
8242 /// ::= .save { registers }
8243 /// ::= .vsave { registers }
8244 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8245 // Check the ordering of unwind directives
8246 if (!FnStartLoc.isValid())
8247 return Error(L, ".fnstart must precede .save or .vsave directives");
8248 if (HandlerDataLoc.isValid())
8249 return Error(L, ".save or .vsave must precede .handlerdata directive");
8251 // Parse the register list
8252 SmallVector<MCParsedAsmOperand*, 1> Operands;
8253 if (parseRegisterList(Operands))
8255 ARMOperand *Op = (ARMOperand*)Operands[0];
8256 if (!IsVector && !Op->isRegList())
8257 return Error(L, ".save expects GPR registers");
8258 if (IsVector && !Op->isDPRRegList())
8259 return Error(L, ".vsave expects DPR registers");
8261 getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
8265 /// Force static initialization.
8266 extern "C" void LLVMInitializeARMAsmParser() {
8267 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8268 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8271 #define GET_REGISTER_MATCHER
8272 #define GET_SUBTARGET_FEATURE_NAME
8273 #define GET_MATCHER_IMPLEMENTATION
8274 #include "ARMGenAsmMatcher.inc"
8276 // Define this matcher function after the auto-generated include so we
8277 // have the match class enum definitions.
8278 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8280 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8281 // If the kind is a token for a literal immediate, check if our asm
8282 // operand matches. This is for InstAliases which have a fixed-value
8283 // immediate in the syntax.
8284 if (Kind == MCK__35_0 && Op->isImm()) {
8285 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8287 return Match_InvalidOperand;
8288 if (CE->getValue() == 0)
8289 return Match_Success;
8291 return Match_InvalidOperand;