1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMBaseRegisterInfo.h"
12 #include "ARMSubtarget.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "MCTargetDesc/ARMMCExpr.h"
15 #include "llvm/MC/MCParser/MCAsmLexer.h"
16 #include "llvm/MC/MCParser/MCAsmParser.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCAsmInfo.h"
19 #include "llvm/MC/MCContext.h"
20 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/MC/MCExpr.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/TargetAsmParser.h"
25 #include "llvm/Target/TargetRegistry.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/raw_ostream.h"
28 #include "llvm/ADT/OwningPtr.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringExtras.h"
31 #include "llvm/ADT/StringSwitch.h"
32 #include "llvm/ADT/Twine.h"
40 class ARMAsmParser : public TargetAsmParser {
44 MCAsmParser &getParser() const { return Parser; }
45 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
47 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
50 int TryParseRegister();
51 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
52 bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
53 int TryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
54 bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
55 bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &,
56 ARMII::AddrMode AddrMode);
57 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
58 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
59 const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
60 MCSymbolRefExpr::VariantKind Variant);
63 bool ParseMemoryOffsetReg(bool &Negative,
64 bool &OffsetRegShifted,
65 enum ARM_AM::ShiftOpc &ShiftType,
66 const MCExpr *&ShiftAmount,
67 const MCExpr *&Offset,
71 bool ParseShift(enum ARM_AM::ShiftOpc &St,
72 const MCExpr *&ShiftAmount, SMLoc &E);
73 bool ParseDirectiveWord(unsigned Size, SMLoc L);
74 bool ParseDirectiveThumb(SMLoc L);
75 bool ParseDirectiveThumbFunc(SMLoc L);
76 bool ParseDirectiveCode(SMLoc L);
77 bool ParseDirectiveSyntax(SMLoc L);
79 bool MatchAndEmitInstruction(SMLoc IDLoc,
80 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
82 StringRef SplitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
83 bool &CarrySetting, unsigned &ProcessorIMod);
84 void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
85 bool &CanAcceptPredicationCode);
87 bool isThumb() const {
88 // FIXME: Can tablegen auto-generate this?
89 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
91 bool isThumbOne() const {
92 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
95 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
96 setAvailableFeatures(FB);
99 /// @name Auto-generated Match Functions
102 #define GET_ASSEMBLER_HEADER
103 #include "ARMGenAsmMatcher.inc"
107 OperandMatchResultTy parseCoprocNumOperand(
108 SmallVectorImpl<MCParsedAsmOperand*>&);
109 OperandMatchResultTy parseCoprocRegOperand(
110 SmallVectorImpl<MCParsedAsmOperand*>&);
111 OperandMatchResultTy parseMemBarrierOptOperand(
112 SmallVectorImpl<MCParsedAsmOperand*>&);
113 OperandMatchResultTy parseProcIFlagsOperand(
114 SmallVectorImpl<MCParsedAsmOperand*>&);
115 OperandMatchResultTy parseMSRMaskOperand(
116 SmallVectorImpl<MCParsedAsmOperand*>&);
117 OperandMatchResultTy parseMemMode2Operand(
118 SmallVectorImpl<MCParsedAsmOperand*>&);
119 OperandMatchResultTy parseMemMode3Operand(
120 SmallVectorImpl<MCParsedAsmOperand*>&);
121 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
122 StringRef Op, int Low, int High);
123 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
124 return parsePKHImm(O, "lsl", 0, 31);
126 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
127 return parsePKHImm(O, "asr", 1, 32);
129 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
130 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
132 // Asm Match Converter Methods
133 bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
134 const SmallVectorImpl<MCParsedAsmOperand*> &);
135 bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
136 const SmallVectorImpl<MCParsedAsmOperand*> &);
137 bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
138 const SmallVectorImpl<MCParsedAsmOperand*> &);
139 bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
140 const SmallVectorImpl<MCParsedAsmOperand*> &);
143 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
144 : TargetAsmParser(), STI(_STI), Parser(_Parser) {
145 MCAsmParserExtension::Initialize(_Parser);
147 // Initialize the set of available features.
148 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
151 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
152 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
153 virtual bool ParseDirective(AsmToken DirectiveID);
155 } // end anonymous namespace
158 // FIXME: TableGen this?
159 extern MCRegisterClass ARMMCRegisterClasses[]; // In ARMGenRegisterInfo.inc.
164 /// ARMOperand - Instances of this class represent a parsed ARM machine
166 class ARMOperand : public MCParsedAsmOperand {
187 SMLoc StartLoc, EndLoc;
188 SmallVector<unsigned, 8> Registers;
192 ARMCC::CondCodes Val;
204 ARM_PROC::IFlags Val;
224 /// Combined record for all forms of ARM address expressions.
226 ARMII::AddrMode AddrMode;
229 unsigned RegNum; ///< Offset register num, when OffsetIsReg.
230 const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
232 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
233 enum ARM_AM::ShiftOpc ShiftType; // used when OffsetRegShifted is true
234 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
235 unsigned Preindexed : 1;
236 unsigned Postindexed : 1;
237 unsigned OffsetIsReg : 1;
238 unsigned Negative : 1; // only used when OffsetIsReg is true
239 unsigned Writeback : 1;
247 ARM_AM::ShiftOpc ShiftTy;
253 ARM_AM::ShiftOpc ShiftTy;
259 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
261 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
263 StartLoc = o.StartLoc;
277 case DPRRegisterList:
278 case SPRRegisterList:
279 Registers = o.Registers;
300 case ShifterImmediate:
301 ShifterImm = o.ShifterImm;
303 case ShiftedRegister:
304 RegShiftedReg = o.RegShiftedReg;
306 case ShiftedImmediate:
307 RegShiftedImm = o.RegShiftedImm;
312 /// getStartLoc - Get the location of the first token of this operand.
313 SMLoc getStartLoc() const { return StartLoc; }
314 /// getEndLoc - Get the location of the last token of this operand.
315 SMLoc getEndLoc() const { return EndLoc; }
317 ARMCC::CondCodes getCondCode() const {
318 assert(Kind == CondCode && "Invalid access!");
322 unsigned getCoproc() const {
323 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
327 StringRef getToken() const {
328 assert(Kind == Token && "Invalid access!");
329 return StringRef(Tok.Data, Tok.Length);
332 unsigned getReg() const {
333 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
337 const SmallVectorImpl<unsigned> &getRegList() const {
338 assert((Kind == RegisterList || Kind == DPRRegisterList ||
339 Kind == SPRRegisterList) && "Invalid access!");
343 const MCExpr *getImm() const {
344 assert(Kind == Immediate && "Invalid access!");
348 ARM_MB::MemBOpt getMemBarrierOpt() const {
349 assert(Kind == MemBarrierOpt && "Invalid access!");
353 ARM_PROC::IFlags getProcIFlags() const {
354 assert(Kind == ProcIFlags && "Invalid access!");
358 unsigned getMSRMask() const {
359 assert(Kind == MSRMask && "Invalid access!");
363 /// @name Memory Operand Accessors
365 ARMII::AddrMode getMemAddrMode() const {
368 unsigned getMemBaseRegNum() const {
369 return Mem.BaseRegNum;
371 unsigned getMemOffsetRegNum() const {
372 assert(Mem.OffsetIsReg && "Invalid access!");
373 return Mem.Offset.RegNum;
375 const MCExpr *getMemOffset() const {
376 assert(!Mem.OffsetIsReg && "Invalid access!");
377 return Mem.Offset.Value;
379 unsigned getMemOffsetRegShifted() const {
380 assert(Mem.OffsetIsReg && "Invalid access!");
381 return Mem.OffsetRegShifted;
383 const MCExpr *getMemShiftAmount() const {
384 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
385 return Mem.ShiftAmount;
387 enum ARM_AM::ShiftOpc getMemShiftType() const {
388 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
389 return Mem.ShiftType;
391 bool getMemPreindexed() const { return Mem.Preindexed; }
392 bool getMemPostindexed() const { return Mem.Postindexed; }
393 bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; }
394 bool getMemNegative() const { return Mem.Negative; }
395 bool getMemWriteback() const { return Mem.Writeback; }
399 bool isCoprocNum() const { return Kind == CoprocNum; }
400 bool isCoprocReg() const { return Kind == CoprocReg; }
401 bool isCondCode() const { return Kind == CondCode; }
402 bool isCCOut() const { return Kind == CCOut; }
403 bool isImm() const { return Kind == Immediate; }
404 bool isImm0_255() const {
405 if (Kind != Immediate)
407 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
408 if (!CE) return false;
409 int64_t Value = CE->getValue();
410 return Value >= 0 && Value < 256;
412 bool isImm0_7() const {
413 if (Kind != Immediate)
415 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
416 if (!CE) return false;
417 int64_t Value = CE->getValue();
418 return Value >= 0 && Value < 8;
420 bool isImm0_15() const {
421 if (Kind != Immediate)
423 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
424 if (!CE) return false;
425 int64_t Value = CE->getValue();
426 return Value >= 0 && Value < 16;
428 bool isImm0_31() const {
429 if (Kind != Immediate)
431 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
432 if (!CE) return false;
433 int64_t Value = CE->getValue();
434 return Value >= 0 && Value < 32;
436 bool isImm1_16() const {
437 if (Kind != Immediate)
439 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
440 if (!CE) return false;
441 int64_t Value = CE->getValue();
442 return Value > 0 && Value < 17;
444 bool isImm1_32() const {
445 if (Kind != Immediate)
447 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
448 if (!CE) return false;
449 int64_t Value = CE->getValue();
450 return Value > 0 && Value < 33;
452 bool isImm0_65535() const {
453 if (Kind != Immediate)
455 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
456 if (!CE) return false;
457 int64_t Value = CE->getValue();
458 return Value >= 0 && Value < 65536;
460 bool isImm0_65535Expr() const {
461 if (Kind != Immediate)
463 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
464 // If it's not a constant expression, it'll generate a fixup and be
466 if (!CE) return true;
467 int64_t Value = CE->getValue();
468 return Value >= 0 && Value < 65536;
470 bool isPKHLSLImm() const {
471 if (Kind != Immediate)
473 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
474 if (!CE) return false;
475 int64_t Value = CE->getValue();
476 return Value >= 0 && Value < 32;
478 bool isPKHASRImm() const {
479 if (Kind != Immediate)
481 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
482 if (!CE) return false;
483 int64_t Value = CE->getValue();
484 return Value > 0 && Value <= 32;
486 bool isARMSOImm() const {
487 if (Kind != Immediate)
489 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
490 if (!CE) return false;
491 int64_t Value = CE->getValue();
492 return ARM_AM::getSOImmVal(Value) != -1;
494 bool isT2SOImm() const {
495 if (Kind != Immediate)
497 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
498 if (!CE) return false;
499 int64_t Value = CE->getValue();
500 return ARM_AM::getT2SOImmVal(Value) != -1;
502 bool isSetEndImm() const {
503 if (Kind != Immediate)
505 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
506 if (!CE) return false;
507 int64_t Value = CE->getValue();
508 return Value == 1 || Value == 0;
510 bool isReg() const { return Kind == Register; }
511 bool isRegList() const { return Kind == RegisterList; }
512 bool isDPRRegList() const { return Kind == DPRRegisterList; }
513 bool isSPRRegList() const { return Kind == SPRRegisterList; }
514 bool isToken() const { return Kind == Token; }
515 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
516 bool isMemory() const { return Kind == Memory; }
517 bool isShifterImm() const { return Kind == ShifterImmediate; }
518 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
519 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
520 bool isMemMode2() const {
521 if (getMemAddrMode() != ARMII::AddrMode2)
524 if (getMemOffsetIsReg())
527 if (getMemNegative() &&
528 !(getMemPostindexed() || getMemPreindexed()))
531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
532 if (!CE) return false;
533 int64_t Value = CE->getValue();
535 // The offset must be in the range 0-4095 (imm12).
536 if (Value > 4095 || Value < -4095)
541 bool isMemMode3() const {
542 if (getMemAddrMode() != ARMII::AddrMode3)
545 if (getMemOffsetIsReg()) {
546 if (getMemOffsetRegShifted())
547 return false; // No shift with offset reg allowed
551 if (getMemNegative() &&
552 !(getMemPostindexed() || getMemPreindexed()))
555 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
556 if (!CE) return false;
557 int64_t Value = CE->getValue();
559 // The offset must be in the range 0-255 (imm8).
560 if (Value > 255 || Value < -255)
565 bool isMemMode5() const {
566 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
570 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
571 if (!CE) return false;
573 // The offset must be a multiple of 4 in the range 0-1020.
574 int64_t Value = CE->getValue();
575 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
577 bool isMemMode7() const {
579 getMemPreindexed() ||
580 getMemPostindexed() ||
581 getMemOffsetIsReg() ||
586 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
587 if (!CE) return false;
594 bool isMemModeRegThumb() const {
595 if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback())
599 bool isMemModeImmThumb() const {
600 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback())
603 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
604 if (!CE) return false;
606 // The offset must be a multiple of 4 in the range 0-124.
607 uint64_t Value = CE->getValue();
608 return ((Value & 0x3) == 0 && Value <= 124);
610 bool isMSRMask() const { return Kind == MSRMask; }
611 bool isProcIFlags() const { return Kind == ProcIFlags; }
613 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
614 // Add as immediates when possible. Null MCExpr = 0.
616 Inst.addOperand(MCOperand::CreateImm(0));
617 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
618 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
620 Inst.addOperand(MCOperand::CreateExpr(Expr));
623 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
624 assert(N == 2 && "Invalid number of operands!");
625 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
626 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
627 Inst.addOperand(MCOperand::CreateReg(RegNum));
630 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
631 assert(N == 1 && "Invalid number of operands!");
632 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
635 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
636 assert(N == 1 && "Invalid number of operands!");
637 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
640 void addCCOutOperands(MCInst &Inst, unsigned N) const {
641 assert(N == 1 && "Invalid number of operands!");
642 Inst.addOperand(MCOperand::CreateReg(getReg()));
645 void addRegOperands(MCInst &Inst, unsigned N) const {
646 assert(N == 1 && "Invalid number of operands!");
647 Inst.addOperand(MCOperand::CreateReg(getReg()));
650 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
651 assert(N == 3 && "Invalid number of operands!");
652 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
653 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
654 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
655 Inst.addOperand(MCOperand::CreateImm(
656 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
659 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
660 assert(N == 2 && "Invalid number of operands!");
661 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
662 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
663 Inst.addOperand(MCOperand::CreateImm(
664 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
668 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
669 assert(N == 1 && "Invalid number of operands!");
670 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
674 void addRegListOperands(MCInst &Inst, unsigned N) const {
675 assert(N == 1 && "Invalid number of operands!");
676 const SmallVectorImpl<unsigned> &RegList = getRegList();
677 for (SmallVectorImpl<unsigned>::const_iterator
678 I = RegList.begin(), E = RegList.end(); I != E; ++I)
679 Inst.addOperand(MCOperand::CreateReg(*I));
682 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
683 addRegListOperands(Inst, N);
686 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
687 addRegListOperands(Inst, N);
690 void addImmOperands(MCInst &Inst, unsigned N) const {
691 assert(N == 1 && "Invalid number of operands!");
692 addExpr(Inst, getImm());
695 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
696 assert(N == 1 && "Invalid number of operands!");
697 addExpr(Inst, getImm());
700 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
701 assert(N == 1 && "Invalid number of operands!");
702 addExpr(Inst, getImm());
705 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
706 assert(N == 1 && "Invalid number of operands!");
707 addExpr(Inst, getImm());
710 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
711 assert(N == 1 && "Invalid number of operands!");
712 addExpr(Inst, getImm());
715 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
716 assert(N == 1 && "Invalid number of operands!");
717 // The constant encodes as the immediate-1, and we store in the instruction
718 // the bits as encoded, so subtract off one here.
719 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
720 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
723 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
724 assert(N == 1 && "Invalid number of operands!");
725 // The constant encodes as the immediate-1, and we store in the instruction
726 // the bits as encoded, so subtract off one here.
727 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
728 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
731 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
732 assert(N == 1 && "Invalid number of operands!");
733 addExpr(Inst, getImm());
736 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
737 assert(N == 1 && "Invalid number of operands!");
738 addExpr(Inst, getImm());
741 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
742 assert(N == 1 && "Invalid number of operands!");
743 addExpr(Inst, getImm());
746 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
747 assert(N == 1 && "Invalid number of operands!");
748 // An ASR value of 32 encodes as 0, so that's how we want to add it to
749 // the instruction as well.
750 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
751 int Val = CE->getValue();
752 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
755 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
756 assert(N == 1 && "Invalid number of operands!");
757 addExpr(Inst, getImm());
760 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
761 assert(N == 1 && "Invalid number of operands!");
762 addExpr(Inst, getImm());
765 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
766 assert(N == 1 && "Invalid number of operands!");
767 addExpr(Inst, getImm());
770 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
771 assert(N == 1 && "Invalid number of operands!");
772 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
775 void addMemMode7Operands(MCInst &Inst, unsigned N) const {
776 assert(N == 1 && isMemMode7() && "Invalid number of operands!");
777 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
779 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
781 assert((CE || CE->getValue() == 0) &&
782 "No offset operand support in mode 7");
785 void addMemMode2Operands(MCInst &Inst, unsigned N) const {
786 assert(isMemMode2() && "Invalid mode or number of operands!");
787 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
788 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
790 if (getMemOffsetIsReg()) {
791 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
793 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
794 ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
795 int64_t ShiftAmount = 0;
797 if (getMemOffsetRegShifted()) {
798 ShOpc = getMemShiftType();
799 const MCConstantExpr *CE =
800 dyn_cast<MCConstantExpr>(getMemShiftAmount());
801 ShiftAmount = CE->getValue();
804 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
809 // Create a operand placeholder to always yield the same number of operands.
810 Inst.addOperand(MCOperand::CreateReg(0));
812 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
815 assert(CE && "Non-constant mode 2 offset operand!");
816 int64_t Offset = CE->getValue();
819 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
820 Offset, ARM_AM::no_shift, IdxMode)));
822 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
823 -Offset, ARM_AM::no_shift, IdxMode)));
826 void addMemMode3Operands(MCInst &Inst, unsigned N) const {
827 assert(isMemMode3() && "Invalid mode or number of operands!");
828 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
829 unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
831 if (getMemOffsetIsReg()) {
832 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
834 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
835 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(AMOpc, 0,
840 // Create a operand placeholder to always yield the same number of operands.
841 Inst.addOperand(MCOperand::CreateReg(0));
843 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
846 assert(CE && "Non-constant mode 3 offset operand!");
847 int64_t Offset = CE->getValue();
850 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::add,
853 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::sub,
857 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
858 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
860 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
861 assert(!getMemOffsetIsReg() && "Invalid mode 5 operand");
863 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
866 assert(CE && "Non-constant mode 5 offset operand!");
868 // The MCInst offset operand doesn't include the low two bits (like
869 // the instruction encoding).
870 int64_t Offset = CE->getValue() / 4;
872 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
875 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
879 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
880 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
881 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
882 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
885 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
886 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
887 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
888 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
889 assert(CE && "Non-constant mode offset operand!");
890 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
893 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
894 assert(N == 1 && "Invalid number of operands!");
895 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
898 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
899 assert(N == 1 && "Invalid number of operands!");
900 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
903 virtual void print(raw_ostream &OS) const;
905 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
906 ARMOperand *Op = new ARMOperand(CondCode);
913 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
914 ARMOperand *Op = new ARMOperand(CoprocNum);
915 Op->Cop.Val = CopVal;
921 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
922 ARMOperand *Op = new ARMOperand(CoprocReg);
923 Op->Cop.Val = CopVal;
929 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
930 ARMOperand *Op = new ARMOperand(CCOut);
931 Op->Reg.RegNum = RegNum;
937 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
938 ARMOperand *Op = new ARMOperand(Token);
939 Op->Tok.Data = Str.data();
940 Op->Tok.Length = Str.size();
946 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
947 ARMOperand *Op = new ARMOperand(Register);
948 Op->Reg.RegNum = RegNum;
954 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
959 ARMOperand *Op = new ARMOperand(ShiftedRegister);
960 Op->RegShiftedReg.ShiftTy = ShTy;
961 Op->RegShiftedReg.SrcReg = SrcReg;
962 Op->RegShiftedReg.ShiftReg = ShiftReg;
963 Op->RegShiftedReg.ShiftImm = ShiftImm;
969 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
973 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
974 Op->RegShiftedImm.ShiftTy = ShTy;
975 Op->RegShiftedImm.SrcReg = SrcReg;
976 Op->RegShiftedImm.ShiftImm = ShiftImm;
982 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
984 ARMOperand *Op = new ARMOperand(ShifterImmediate);
985 Op->ShifterImm.isASR = isASR;
986 Op->ShifterImm.Imm = Imm;
993 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
994 SMLoc StartLoc, SMLoc EndLoc) {
995 KindTy Kind = RegisterList;
997 if (llvm::ARMMCRegisterClasses[ARM::DPRRegClassID].
998 contains(Regs.front().first))
999 Kind = DPRRegisterList;
1000 else if (llvm::ARMMCRegisterClasses[ARM::SPRRegClassID].
1001 contains(Regs.front().first))
1002 Kind = SPRRegisterList;
1004 ARMOperand *Op = new ARMOperand(Kind);
1005 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1006 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1007 Op->Registers.push_back(I->first);
1008 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1009 Op->StartLoc = StartLoc;
1010 Op->EndLoc = EndLoc;
1014 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1015 ARMOperand *Op = new ARMOperand(Immediate);
1022 static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
1023 bool OffsetIsReg, const MCExpr *Offset,
1024 int OffsetRegNum, bool OffsetRegShifted,
1025 enum ARM_AM::ShiftOpc ShiftType,
1026 const MCExpr *ShiftAmount, bool Preindexed,
1027 bool Postindexed, bool Negative, bool Writeback,
1029 assert((OffsetRegNum == -1 || OffsetIsReg) &&
1030 "OffsetRegNum must imply OffsetIsReg!");
1031 assert((!OffsetRegShifted || OffsetIsReg) &&
1032 "OffsetRegShifted must imply OffsetIsReg!");
1033 assert((Offset || OffsetIsReg) &&
1034 "Offset must exists unless register offset is used!");
1035 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
1036 "Cannot have shift amount without shifted register offset!");
1037 assert((!Offset || !OffsetIsReg) &&
1038 "Cannot have expression offset and register offset!");
1040 ARMOperand *Op = new ARMOperand(Memory);
1041 Op->Mem.AddrMode = AddrMode;
1042 Op->Mem.BaseRegNum = BaseRegNum;
1043 Op->Mem.OffsetIsReg = OffsetIsReg;
1045 Op->Mem.Offset.RegNum = OffsetRegNum;
1047 Op->Mem.Offset.Value = Offset;
1048 Op->Mem.OffsetRegShifted = OffsetRegShifted;
1049 Op->Mem.ShiftType = ShiftType;
1050 Op->Mem.ShiftAmount = ShiftAmount;
1051 Op->Mem.Preindexed = Preindexed;
1052 Op->Mem.Postindexed = Postindexed;
1053 Op->Mem.Negative = Negative;
1054 Op->Mem.Writeback = Writeback;
1061 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1062 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1063 Op->MBOpt.Val = Opt;
1069 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1070 ARMOperand *Op = new ARMOperand(ProcIFlags);
1071 Op->IFlags.Val = IFlags;
1077 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1078 ARMOperand *Op = new ARMOperand(MSRMask);
1079 Op->MMask.Val = MMask;
1086 } // end anonymous namespace.
1088 void ARMOperand::print(raw_ostream &OS) const {
1091 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1094 OS << "<ccout " << getReg() << ">";
1097 OS << "<coprocessor number: " << getCoproc() << ">";
1100 OS << "<coprocessor register: " << getCoproc() << ">";
1103 OS << "<mask: " << getMSRMask() << ">";
1106 getImm()->print(OS);
1109 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1113 << "am:" << ARMII::AddrModeToString(getMemAddrMode())
1114 << " base:" << getMemBaseRegNum();
1115 if (getMemOffsetIsReg()) {
1116 OS << " offset:<register " << getMemOffsetRegNum();
1117 if (getMemOffsetRegShifted()) {
1118 OS << " offset-shift-type:" << getMemShiftType();
1119 OS << " offset-shift-amount:" << *getMemShiftAmount();
1122 OS << " offset:" << *getMemOffset();
1124 if (getMemOffsetIsReg())
1125 OS << " (offset-is-reg)";
1126 if (getMemPreindexed())
1127 OS << " (pre-indexed)";
1128 if (getMemPostindexed())
1129 OS << " (post-indexed)";
1130 if (getMemNegative())
1131 OS << " (negative)";
1132 if (getMemWriteback())
1133 OS << " (writeback)";
1137 OS << "<ARM_PROC::";
1138 unsigned IFlags = getProcIFlags();
1139 for (int i=2; i >= 0; --i)
1140 if (IFlags & (1 << i))
1141 OS << ARM_PROC::IFlagsToString(1 << i);
1146 OS << "<register " << getReg() << ">";
1148 case ShifterImmediate:
1149 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1150 << " #" << ShifterImm.Imm << ">";
1152 case ShiftedRegister:
1153 OS << "<so_reg_reg "
1154 << RegShiftedReg.SrcReg
1155 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1156 << ", " << RegShiftedReg.ShiftReg << ", "
1157 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1160 case ShiftedImmediate:
1161 OS << "<so_reg_imm "
1162 << RegShiftedImm.SrcReg
1163 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1164 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1168 case DPRRegisterList:
1169 case SPRRegisterList: {
1170 OS << "<register_list ";
1172 const SmallVectorImpl<unsigned> &RegList = getRegList();
1173 for (SmallVectorImpl<unsigned>::const_iterator
1174 I = RegList.begin(), E = RegList.end(); I != E; ) {
1176 if (++I < E) OS << ", ";
1183 OS << "'" << getToken() << "'";
1188 /// @name Auto-generated Match Functions
1191 static unsigned MatchRegisterName(StringRef Name);
1195 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1196 SMLoc &StartLoc, SMLoc &EndLoc) {
1197 RegNo = TryParseRegister();
1199 return (RegNo == (unsigned)-1);
1202 /// Try to parse a register name. The token must be an Identifier when called,
1203 /// and if it is a register name the token is eaten and the register number is
1204 /// returned. Otherwise return -1.
1206 int ARMAsmParser::TryParseRegister() {
1207 const AsmToken &Tok = Parser.getTok();
1208 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1210 // FIXME: Validate register for the current architecture; we have to do
1211 // validation later, so maybe there is no need for this here.
1212 std::string upperCase = Tok.getString().str();
1213 std::string lowerCase = LowercaseString(upperCase);
1214 unsigned RegNum = MatchRegisterName(lowerCase);
1216 RegNum = StringSwitch<unsigned>(lowerCase)
1217 .Case("r13", ARM::SP)
1218 .Case("r14", ARM::LR)
1219 .Case("r15", ARM::PC)
1220 .Case("ip", ARM::R12)
1223 if (!RegNum) return -1;
1225 Parser.Lex(); // Eat identifier token.
1229 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1230 // If a recoverable error occurs, return 1. If an irrecoverable error
1231 // occurs, return -1. An irrecoverable error is one where tokens have been
1232 // consumed in the process of trying to parse the shifter (i.e., when it is
1233 // indeed a shifter operand, but malformed).
1234 int ARMAsmParser::TryParseShiftRegister(
1235 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1236 SMLoc S = Parser.getTok().getLoc();
1237 const AsmToken &Tok = Parser.getTok();
1238 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1240 std::string upperCase = Tok.getString().str();
1241 std::string lowerCase = LowercaseString(upperCase);
1242 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1243 .Case("lsl", ARM_AM::lsl)
1244 .Case("lsr", ARM_AM::lsr)
1245 .Case("asr", ARM_AM::asr)
1246 .Case("ror", ARM_AM::ror)
1247 .Case("rrx", ARM_AM::rrx)
1248 .Default(ARM_AM::no_shift);
1250 if (ShiftTy == ARM_AM::no_shift)
1253 Parser.Lex(); // Eat the operator.
1255 // The source register for the shift has already been added to the
1256 // operand list, so we need to pop it off and combine it into the shifted
1257 // register operand instead.
1258 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1259 if (!PrevOp->isReg())
1260 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1261 int SrcReg = PrevOp->getReg();
1264 if (ShiftTy == ARM_AM::rrx) {
1265 // RRX Doesn't have an explicit shift amount. The encoder expects
1266 // the shift register to be the same as the source register. Seems odd,
1270 // Figure out if this is shifted by a constant or a register (for non-RRX).
1271 if (Parser.getTok().is(AsmToken::Hash)) {
1272 Parser.Lex(); // Eat hash.
1273 SMLoc ImmLoc = Parser.getTok().getLoc();
1274 const MCExpr *ShiftExpr = 0;
1275 if (getParser().ParseExpression(ShiftExpr)) {
1276 Error(ImmLoc, "invalid immediate shift value");
1279 // The expression must be evaluatable as an immediate.
1280 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1282 Error(ImmLoc, "invalid immediate shift value");
1285 // Range check the immediate.
1286 // lsl, ror: 0 <= imm <= 31
1287 // lsr, asr: 0 <= imm <= 32
1288 Imm = CE->getValue();
1290 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1291 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1292 Error(ImmLoc, "immediate shift value out of range");
1295 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1296 ShiftReg = TryParseRegister();
1297 SMLoc L = Parser.getTok().getLoc();
1298 if (ShiftReg == -1) {
1299 Error (L, "expected immediate or register in shift operand");
1303 Error (Parser.getTok().getLoc(),
1304 "expected immediate or register in shift operand");
1309 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1310 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1312 S, Parser.getTok().getLoc()));
1314 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1315 S, Parser.getTok().getLoc()));
1321 /// Try to parse a register name. The token must be an Identifier when called.
1322 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1323 /// if there is a "writeback". 'true' if it's not a register.
1325 /// TODO this is likely to change to allow different register types and or to
1326 /// parse for a specific register type.
1328 TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1329 SMLoc S = Parser.getTok().getLoc();
1330 int RegNo = TryParseRegister();
1334 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1336 const AsmToken &ExclaimTok = Parser.getTok();
1337 if (ExclaimTok.is(AsmToken::Exclaim)) {
1338 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1339 ExclaimTok.getLoc()));
1340 Parser.Lex(); // Eat exclaim token
1346 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1347 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1349 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1350 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1352 switch (Name.size()) {
1355 if (Name[0] != CoprocOp)
1372 if (Name[0] != CoprocOp || Name[1] != '1')
1376 case '0': return 10;
1377 case '1': return 11;
1378 case '2': return 12;
1379 case '3': return 13;
1380 case '4': return 14;
1381 case '5': return 15;
1389 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1390 /// token must be an Identifier when called, and if it is a coprocessor
1391 /// number, the token is eaten and the operand is added to the operand list.
1392 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1393 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1394 SMLoc S = Parser.getTok().getLoc();
1395 const AsmToken &Tok = Parser.getTok();
1396 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1398 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1400 return MatchOperand_NoMatch;
1402 Parser.Lex(); // Eat identifier token.
1403 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1404 return MatchOperand_Success;
1407 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1408 /// token must be an Identifier when called, and if it is a coprocessor
1409 /// number, the token is eaten and the operand is added to the operand list.
1410 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1411 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1412 SMLoc S = Parser.getTok().getLoc();
1413 const AsmToken &Tok = Parser.getTok();
1414 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1416 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1418 return MatchOperand_NoMatch;
1420 Parser.Lex(); // Eat identifier token.
1421 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1422 return MatchOperand_Success;
1425 /// Parse a register list, return it if successful else return null. The first
1426 /// token must be a '{' when called.
1428 ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1429 assert(Parser.getTok().is(AsmToken::LCurly) &&
1430 "Token is not a Left Curly Brace");
1431 SMLoc S = Parser.getTok().getLoc();
1433 // Read the rest of the registers in the list.
1434 unsigned PrevRegNum = 0;
1435 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
1438 bool IsRange = Parser.getTok().is(AsmToken::Minus);
1439 Parser.Lex(); // Eat non-identifier token.
1441 const AsmToken &RegTok = Parser.getTok();
1442 SMLoc RegLoc = RegTok.getLoc();
1443 if (RegTok.isNot(AsmToken::Identifier)) {
1444 Error(RegLoc, "register expected");
1448 int RegNum = TryParseRegister();
1450 Error(RegLoc, "register expected");
1455 int Reg = PrevRegNum;
1458 Registers.push_back(std::make_pair(Reg, RegLoc));
1459 } while (Reg != RegNum);
1461 Registers.push_back(std::make_pair(RegNum, RegLoc));
1464 PrevRegNum = RegNum;
1465 } while (Parser.getTok().is(AsmToken::Comma) ||
1466 Parser.getTok().is(AsmToken::Minus));
1468 // Process the right curly brace of the list.
1469 const AsmToken &RCurlyTok = Parser.getTok();
1470 if (RCurlyTok.isNot(AsmToken::RCurly)) {
1471 Error(RCurlyTok.getLoc(), "'}' expected");
1475 SMLoc E = RCurlyTok.getLoc();
1476 Parser.Lex(); // Eat right curly brace token.
1478 // Verify the register list.
1479 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1480 RI = Registers.begin(), RE = Registers.end();
1482 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
1483 bool EmittedWarning = false;
1485 DenseMap<unsigned, bool> RegMap;
1486 RegMap[HighRegNum] = true;
1488 for (++RI; RI != RE; ++RI) {
1489 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
1490 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
1493 Error(RegInfo.second, "register duplicated in register list");
1497 if (!EmittedWarning && Reg < HighRegNum)
1498 Warning(RegInfo.second,
1499 "register not in ascending order in register list");
1502 HighRegNum = std::max(Reg, HighRegNum);
1505 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1509 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1510 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1511 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1512 SMLoc S = Parser.getTok().getLoc();
1513 const AsmToken &Tok = Parser.getTok();
1514 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1515 StringRef OptStr = Tok.getString();
1517 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1518 .Case("sy", ARM_MB::SY)
1519 .Case("st", ARM_MB::ST)
1520 .Case("sh", ARM_MB::ISH)
1521 .Case("ish", ARM_MB::ISH)
1522 .Case("shst", ARM_MB::ISHST)
1523 .Case("ishst", ARM_MB::ISHST)
1524 .Case("nsh", ARM_MB::NSH)
1525 .Case("un", ARM_MB::NSH)
1526 .Case("nshst", ARM_MB::NSHST)
1527 .Case("unst", ARM_MB::NSHST)
1528 .Case("osh", ARM_MB::OSH)
1529 .Case("oshst", ARM_MB::OSHST)
1533 return MatchOperand_NoMatch;
1535 Parser.Lex(); // Eat identifier token.
1536 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
1537 return MatchOperand_Success;
1540 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
1541 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1542 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1543 SMLoc S = Parser.getTok().getLoc();
1544 const AsmToken &Tok = Parser.getTok();
1545 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1546 StringRef IFlagsStr = Tok.getString();
1548 unsigned IFlags = 0;
1549 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
1550 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
1551 .Case("a", ARM_PROC::A)
1552 .Case("i", ARM_PROC::I)
1553 .Case("f", ARM_PROC::F)
1556 // If some specific iflag is already set, it means that some letter is
1557 // present more than once, this is not acceptable.
1558 if (Flag == ~0U || (IFlags & Flag))
1559 return MatchOperand_NoMatch;
1564 Parser.Lex(); // Eat identifier token.
1565 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
1566 return MatchOperand_Success;
1569 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
1570 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1571 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1572 SMLoc S = Parser.getTok().getLoc();
1573 const AsmToken &Tok = Parser.getTok();
1574 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1575 StringRef Mask = Tok.getString();
1577 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
1578 size_t Start = 0, Next = Mask.find('_');
1579 StringRef Flags = "";
1580 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
1581 if (Next != StringRef::npos)
1582 Flags = Mask.slice(Next+1, Mask.size());
1584 // FlagsVal contains the complete mask:
1586 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1587 unsigned FlagsVal = 0;
1589 if (SpecReg == "apsr") {
1590 FlagsVal = StringSwitch<unsigned>(Flags)
1591 .Case("nzcvq", 0x8) // same as CPSR_f
1592 .Case("g", 0x4) // same as CPSR_s
1593 .Case("nzcvqg", 0xc) // same as CPSR_fs
1596 if (FlagsVal == ~0U) {
1598 return MatchOperand_NoMatch;
1600 FlagsVal = 0; // No flag
1602 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
1603 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
1605 for (int i = 0, e = Flags.size(); i != e; ++i) {
1606 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
1613 // If some specific flag is already set, it means that some letter is
1614 // present more than once, this is not acceptable.
1615 if (FlagsVal == ~0U || (FlagsVal & Flag))
1616 return MatchOperand_NoMatch;
1619 } else // No match for special register.
1620 return MatchOperand_NoMatch;
1622 // Special register without flags are equivalent to "fc" flags.
1626 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
1627 if (SpecReg == "spsr")
1630 Parser.Lex(); // Eat identifier token.
1631 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
1632 return MatchOperand_Success;
1635 /// parseMemMode2Operand - Try to parse memory addressing mode 2 operand.
1636 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1637 parseMemMode2Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1638 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1640 if (ParseMemory(Operands, ARMII::AddrMode2))
1641 return MatchOperand_NoMatch;
1643 return MatchOperand_Success;
1646 /// parseMemMode3Operand - Try to parse memory addressing mode 3 operand.
1647 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1648 parseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1649 assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
1651 if (ParseMemory(Operands, ARMII::AddrMode3))
1652 return MatchOperand_NoMatch;
1654 return MatchOperand_Success;
1657 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1658 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
1659 int Low, int High) {
1660 const AsmToken &Tok = Parser.getTok();
1661 if (Tok.isNot(AsmToken::Identifier)) {
1662 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1663 return MatchOperand_ParseFail;
1665 StringRef ShiftName = Tok.getString();
1666 std::string LowerOp = LowercaseString(Op);
1667 std::string UpperOp = UppercaseString(Op);
1668 if (ShiftName != LowerOp && ShiftName != UpperOp) {
1669 Error(Parser.getTok().getLoc(), Op + " operand expected.");
1670 return MatchOperand_ParseFail;
1672 Parser.Lex(); // Eat shift type token.
1674 // There must be a '#' and a shift amount.
1675 if (Parser.getTok().isNot(AsmToken::Hash)) {
1676 Error(Parser.getTok().getLoc(), "'#' expected");
1677 return MatchOperand_ParseFail;
1679 Parser.Lex(); // Eat hash token.
1681 const MCExpr *ShiftAmount;
1682 SMLoc Loc = Parser.getTok().getLoc();
1683 if (getParser().ParseExpression(ShiftAmount)) {
1684 Error(Loc, "illegal expression");
1685 return MatchOperand_ParseFail;
1687 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1689 Error(Loc, "constant expression expected");
1690 return MatchOperand_ParseFail;
1692 int Val = CE->getValue();
1693 if (Val < Low || Val > High) {
1694 Error(Loc, "immediate value out of range");
1695 return MatchOperand_ParseFail;
1698 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
1700 return MatchOperand_Success;
1703 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1704 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1705 const AsmToken &Tok = Parser.getTok();
1706 SMLoc S = Tok.getLoc();
1707 if (Tok.isNot(AsmToken::Identifier)) {
1708 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1709 return MatchOperand_ParseFail;
1711 int Val = StringSwitch<int>(Tok.getString())
1715 Parser.Lex(); // Eat the token.
1718 Error(Tok.getLoc(), "'be' or 'le' operand expected");
1719 return MatchOperand_ParseFail;
1721 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
1723 S, Parser.getTok().getLoc()));
1724 return MatchOperand_Success;
1727 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
1728 /// instructions. Legal values are:
1729 /// lsl #n 'n' in [0,31]
1730 /// asr #n 'n' in [1,32]
1731 /// n == 32 encoded as n == 0.
1732 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1733 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1734 const AsmToken &Tok = Parser.getTok();
1735 SMLoc S = Tok.getLoc();
1736 if (Tok.isNot(AsmToken::Identifier)) {
1737 Error(S, "shift operator 'asr' or 'lsl' expected");
1738 return MatchOperand_ParseFail;
1740 StringRef ShiftName = Tok.getString();
1742 if (ShiftName == "lsl" || ShiftName == "LSL")
1744 else if (ShiftName == "asr" || ShiftName == "ASR")
1747 Error(S, "shift operator 'asr' or 'lsl' expected");
1748 return MatchOperand_ParseFail;
1750 Parser.Lex(); // Eat the operator.
1752 // A '#' and a shift amount.
1753 if (Parser.getTok().isNot(AsmToken::Hash)) {
1754 Error(Parser.getTok().getLoc(), "'#' expected");
1755 return MatchOperand_ParseFail;
1757 Parser.Lex(); // Eat hash token.
1759 const MCExpr *ShiftAmount;
1760 SMLoc E = Parser.getTok().getLoc();
1761 if (getParser().ParseExpression(ShiftAmount)) {
1762 Error(E, "malformed shift expression");
1763 return MatchOperand_ParseFail;
1765 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
1767 Error(E, "shift amount must be an immediate");
1768 return MatchOperand_ParseFail;
1771 int64_t Val = CE->getValue();
1773 // Shift amount must be in [1,32]
1774 if (Val < 1 || Val > 32) {
1775 Error(E, "'asr' shift amount must be in range [1,32]");
1776 return MatchOperand_ParseFail;
1778 // asr #32 encoded as asr #0.
1779 if (Val == 32) Val = 0;
1781 // Shift amount must be in [1,32]
1782 if (Val < 0 || Val > 31) {
1783 Error(E, "'lsr' shift amount must be in range [0,31]");
1784 return MatchOperand_ParseFail;
1788 E = Parser.getTok().getLoc();
1789 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
1791 return MatchOperand_Success;
1794 /// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1795 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1796 /// when they refer multiple MIOperands inside a single one.
1798 CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1799 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1800 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1802 // Create a writeback register dummy placeholder.
1803 Inst.addOperand(MCOperand::CreateImm(0));
1805 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1806 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1810 /// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1811 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1812 /// when they refer multiple MIOperands inside a single one.
1814 CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1815 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1816 // Create a writeback register dummy placeholder.
1817 Inst.addOperand(MCOperand::CreateImm(0));
1818 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1819 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1820 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1824 /// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1825 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1826 /// when they refer multiple MIOperands inside a single one.
1828 CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1829 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1830 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1832 // Create a writeback register dummy placeholder.
1833 Inst.addOperand(MCOperand::CreateImm(0));
1835 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1836 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1840 /// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
1841 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1842 /// when they refer multiple MIOperands inside a single one.
1844 CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
1845 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1846 // Create a writeback register dummy placeholder.
1847 Inst.addOperand(MCOperand::CreateImm(0));
1848 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1849 ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
1850 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1854 /// Parse an ARM memory expression, return false if successful else return true
1855 /// or an error. The first token must be a '[' when called.
1857 /// TODO Only preindexing and postindexing addressing are started, unindexed
1858 /// with option, etc are still to do.
1860 ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1861 ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
1863 assert(Parser.getTok().is(AsmToken::LBrac) &&
1864 "Token is not a Left Bracket");
1865 S = Parser.getTok().getLoc();
1866 Parser.Lex(); // Eat left bracket token.
1868 const AsmToken &BaseRegTok = Parser.getTok();
1869 if (BaseRegTok.isNot(AsmToken::Identifier)) {
1870 Error(BaseRegTok.getLoc(), "register expected");
1873 int BaseRegNum = TryParseRegister();
1874 if (BaseRegNum == -1) {
1875 Error(BaseRegTok.getLoc(), "register expected");
1879 // The next token must either be a comma or a closing bracket.
1880 const AsmToken &Tok = Parser.getTok();
1881 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
1884 bool Preindexed = false;
1885 bool Postindexed = false;
1886 bool OffsetIsReg = false;
1887 bool Negative = false;
1888 bool Writeback = false;
1889 ARMOperand *WBOp = 0;
1890 int OffsetRegNum = -1;
1891 bool OffsetRegShifted = false;
1892 enum ARM_AM::ShiftOpc ShiftType = ARM_AM::lsl;
1893 const MCExpr *ShiftAmount = 0;
1894 const MCExpr *Offset = 0;
1896 // First look for preindexed address forms, that is after the "[Rn" we now
1897 // have to see if the next token is a comma.
1898 if (Tok.is(AsmToken::Comma)) {
1900 Parser.Lex(); // Eat comma token.
1902 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
1903 Offset, OffsetIsReg, OffsetRegNum, E))
1905 const AsmToken &RBracTok = Parser.getTok();
1906 if (RBracTok.isNot(AsmToken::RBrac)) {
1907 Error(RBracTok.getLoc(), "']' expected");
1910 E = RBracTok.getLoc();
1911 Parser.Lex(); // Eat right bracket token.
1913 const AsmToken &ExclaimTok = Parser.getTok();
1914 if (ExclaimTok.is(AsmToken::Exclaim)) {
1915 // None of addrmode3 instruction uses "!"
1916 if (AddrMode == ARMII::AddrMode3)
1919 WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
1920 ExclaimTok.getLoc());
1922 Parser.Lex(); // Eat exclaim token
1923 } else { // In addressing mode 2, pre-indexed mode always end with "!"
1924 if (AddrMode == ARMII::AddrMode2)
1928 // The "[Rn" we have so far was not followed by a comma.
1930 // If there's anything other than the right brace, this is a post indexing
1933 Parser.Lex(); // Eat right bracket token.
1935 const AsmToken &NextTok = Parser.getTok();
1937 if (NextTok.isNot(AsmToken::EndOfStatement)) {
1941 if (NextTok.isNot(AsmToken::Comma)) {
1942 Error(NextTok.getLoc(), "',' expected");
1946 Parser.Lex(); // Eat comma token.
1948 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
1949 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
1955 // Force Offset to exist if used.
1958 Offset = MCConstantExpr::Create(0, getContext());
1960 if (AddrMode == ARMII::AddrMode3 && OffsetRegShifted) {
1961 Error(E, "shift amount not supported");
1966 Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
1967 Offset, OffsetRegNum, OffsetRegShifted,
1968 ShiftType, ShiftAmount, Preindexed,
1969 Postindexed, Negative, Writeback, S, E));
1971 Operands.push_back(WBOp);
1976 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
1977 /// we will parse the following (were +/- means that a plus or minus is
1982 /// we return false on success or an error otherwise.
1983 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
1984 bool &OffsetRegShifted,
1985 enum ARM_AM::ShiftOpc &ShiftType,
1986 const MCExpr *&ShiftAmount,
1987 const MCExpr *&Offset,
1992 OffsetRegShifted = false;
1993 OffsetIsReg = false;
1995 const AsmToken &NextTok = Parser.getTok();
1996 E = NextTok.getLoc();
1997 if (NextTok.is(AsmToken::Plus))
1998 Parser.Lex(); // Eat plus token.
1999 else if (NextTok.is(AsmToken::Minus)) {
2001 Parser.Lex(); // Eat minus token
2003 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
2004 const AsmToken &OffsetRegTok = Parser.getTok();
2005 if (OffsetRegTok.is(AsmToken::Identifier)) {
2006 SMLoc CurLoc = OffsetRegTok.getLoc();
2007 OffsetRegNum = TryParseRegister();
2008 if (OffsetRegNum != -1) {
2014 // If we parsed a register as the offset then there can be a shift after that.
2015 if (OffsetRegNum != -1) {
2016 // Look for a comma then a shift
2017 const AsmToken &Tok = Parser.getTok();
2018 if (Tok.is(AsmToken::Comma)) {
2019 Parser.Lex(); // Eat comma token.
2021 const AsmToken &Tok = Parser.getTok();
2022 if (ParseShift(ShiftType, ShiftAmount, E))
2023 return Error(Tok.getLoc(), "shift expected");
2024 OffsetRegShifted = true;
2027 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
2028 // Look for #offset following the "[Rn," or "[Rn],"
2029 const AsmToken &HashTok = Parser.getTok();
2030 if (HashTok.isNot(AsmToken::Hash))
2031 return Error(HashTok.getLoc(), "'#' expected");
2033 Parser.Lex(); // Eat hash token.
2035 if (getParser().ParseExpression(Offset))
2037 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2042 /// ParseShift as one of these two:
2043 /// ( lsl | lsr | asr | ror ) , # shift_amount
2045 /// and returns true if it parses a shift otherwise it returns false.
2046 bool ARMAsmParser::ParseShift(ARM_AM::ShiftOpc &St,
2047 const MCExpr *&ShiftAmount, SMLoc &E) {
2048 const AsmToken &Tok = Parser.getTok();
2049 if (Tok.isNot(AsmToken::Identifier))
2051 StringRef ShiftName = Tok.getString();
2052 if (ShiftName == "lsl" || ShiftName == "LSL")
2054 else if (ShiftName == "lsr" || ShiftName == "LSR")
2056 else if (ShiftName == "asr" || ShiftName == "ASR")
2058 else if (ShiftName == "ror" || ShiftName == "ROR")
2060 else if (ShiftName == "rrx" || ShiftName == "RRX")
2064 Parser.Lex(); // Eat shift type token.
2066 // Rrx stands alone.
2067 if (St == ARM_AM::rrx)
2070 // Otherwise, there must be a '#' and a shift amount.
2071 const AsmToken &HashTok = Parser.getTok();
2072 if (HashTok.isNot(AsmToken::Hash))
2073 return Error(HashTok.getLoc(), "'#' expected");
2074 Parser.Lex(); // Eat hash token.
2076 if (getParser().ParseExpression(ShiftAmount))
2082 /// Parse a arm instruction operand. For now this parses the operand regardless
2083 /// of the mnemonic.
2084 bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2085 StringRef Mnemonic) {
2088 // Check if the current operand has a custom associated parser, if so, try to
2089 // custom parse the operand, or fallback to the general approach.
2090 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2091 if (ResTy == MatchOperand_Success)
2093 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2094 // there was a match, but an error occurred, in which case, just return that
2095 // the operand parsing failed.
2096 if (ResTy == MatchOperand_ParseFail)
2099 switch (getLexer().getKind()) {
2101 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2103 case AsmToken::Identifier: {
2104 if (!TryParseRegisterWithWriteBack(Operands))
2106 int Res = TryParseShiftRegister(Operands);
2107 if (Res == 0) // success
2109 else if (Res == -1) // irrecoverable error
2112 // Fall though for the Identifier case that is not a register or a
2115 case AsmToken::Integer: // things like 1f and 2b as a branch targets
2116 case AsmToken::Dot: { // . as a branch target
2117 // This was not a register so parse other operands that start with an
2118 // identifier (like labels) as expressions and create them as immediates.
2119 const MCExpr *IdVal;
2120 S = Parser.getTok().getLoc();
2121 if (getParser().ParseExpression(IdVal))
2123 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2124 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
2127 case AsmToken::LBrac:
2128 return ParseMemory(Operands);
2129 case AsmToken::LCurly:
2130 return ParseRegisterList(Operands);
2131 case AsmToken::Hash:
2132 // #42 -> immediate.
2133 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
2134 S = Parser.getTok().getLoc();
2136 const MCExpr *ImmVal;
2137 if (getParser().ParseExpression(ImmVal))
2139 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2140 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
2142 case AsmToken::Colon: {
2143 // ":lower16:" and ":upper16:" expression prefixes
2144 // FIXME: Check it's an expression prefix,
2145 // e.g. (FOO - :lower16:BAR) isn't legal.
2146 ARMMCExpr::VariantKind RefKind;
2147 if (ParsePrefix(RefKind))
2150 const MCExpr *SubExprVal;
2151 if (getParser().ParseExpression(SubExprVal))
2154 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
2156 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
2157 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
2163 // ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
2164 // :lower16: and :upper16:.
2165 bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
2166 RefKind = ARMMCExpr::VK_ARM_None;
2168 // :lower16: and :upper16: modifiers
2169 assert(getLexer().is(AsmToken::Colon) && "expected a :");
2170 Parser.Lex(); // Eat ':'
2172 if (getLexer().isNot(AsmToken::Identifier)) {
2173 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
2177 StringRef IDVal = Parser.getTok().getIdentifier();
2178 if (IDVal == "lower16") {
2179 RefKind = ARMMCExpr::VK_ARM_LO16;
2180 } else if (IDVal == "upper16") {
2181 RefKind = ARMMCExpr::VK_ARM_HI16;
2183 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
2188 if (getLexer().isNot(AsmToken::Colon)) {
2189 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
2192 Parser.Lex(); // Eat the last ':'
2197 ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
2198 MCSymbolRefExpr::VariantKind Variant) {
2199 // Recurse over the given expression, rebuilding it to apply the given variant
2200 // to the leftmost symbol.
2201 if (Variant == MCSymbolRefExpr::VK_None)
2204 switch (E->getKind()) {
2205 case MCExpr::Target:
2206 llvm_unreachable("Can't handle target expr yet");
2207 case MCExpr::Constant:
2208 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
2210 case MCExpr::SymbolRef: {
2211 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
2213 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
2216 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
2220 llvm_unreachable("Can't handle unary expressions yet");
2222 case MCExpr::Binary: {
2223 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
2224 const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant);
2225 const MCExpr *RHS = BE->getRHS();
2229 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
2233 assert(0 && "Invalid expression kind!");
2237 /// \brief Given a mnemonic, split out possible predication code and carry
2238 /// setting letters to form a canonical mnemonic and flags.
2240 // FIXME: Would be nice to autogen this.
2241 StringRef ARMAsmParser::SplitMnemonic(StringRef Mnemonic,
2242 unsigned &PredicationCode,
2244 unsigned &ProcessorIMod) {
2245 PredicationCode = ARMCC::AL;
2246 CarrySetting = false;
2249 // Ignore some mnemonics we know aren't predicated forms.
2251 // FIXME: Would be nice to autogen this.
2252 if ((Mnemonic == "movs" && isThumb()) ||
2253 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
2254 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
2255 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
2256 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
2257 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
2258 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
2259 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
2262 // First, split out any predication code. Ignore mnemonics we know aren't
2263 // predicated but do have a carry-set and so weren't caught above.
2264 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
2265 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls") {
2266 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
2267 .Case("eq", ARMCC::EQ)
2268 .Case("ne", ARMCC::NE)
2269 .Case("hs", ARMCC::HS)
2270 .Case("cs", ARMCC::HS)
2271 .Case("lo", ARMCC::LO)
2272 .Case("cc", ARMCC::LO)
2273 .Case("mi", ARMCC::MI)
2274 .Case("pl", ARMCC::PL)
2275 .Case("vs", ARMCC::VS)
2276 .Case("vc", ARMCC::VC)
2277 .Case("hi", ARMCC::HI)
2278 .Case("ls", ARMCC::LS)
2279 .Case("ge", ARMCC::GE)
2280 .Case("lt", ARMCC::LT)
2281 .Case("gt", ARMCC::GT)
2282 .Case("le", ARMCC::LE)
2283 .Case("al", ARMCC::AL)
2286 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
2287 PredicationCode = CC;
2291 // Next, determine if we have a carry setting bit. We explicitly ignore all
2292 // the instructions we know end in 's'.
2293 if (Mnemonic.endswith("s") &&
2294 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
2295 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
2296 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
2297 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
2298 Mnemonic == "vrsqrts" || (Mnemonic == "movs" && isThumb()))) {
2299 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
2300 CarrySetting = true;
2303 // The "cps" instruction can have a interrupt mode operand which is glued into
2304 // the mnemonic. Check if this is the case, split it and parse the imod op
2305 if (Mnemonic.startswith("cps")) {
2306 // Split out any imod code.
2308 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
2309 .Case("ie", ARM_PROC::IE)
2310 .Case("id", ARM_PROC::ID)
2313 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
2314 ProcessorIMod = IMod;
2321 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
2322 /// inclusion of carry set or predication code operands.
2324 // FIXME: It would be nice to autogen this.
2326 GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
2327 bool &CanAcceptPredicationCode) {
2328 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
2329 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
2330 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
2331 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
2332 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
2333 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
2334 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
2335 Mnemonic == "eor" || Mnemonic == "smlal" ||
2336 (Mnemonic == "mov" && !isThumbOne())) {
2337 CanAcceptCarrySet = true;
2339 CanAcceptCarrySet = false;
2342 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
2343 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
2344 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
2345 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
2346 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "clrex" ||
2347 Mnemonic == "setend" ||
2348 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumb())) {
2349 CanAcceptPredicationCode = false;
2351 CanAcceptPredicationCode = true;
2355 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
2356 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
2357 CanAcceptPredicationCode = false;
2360 /// Parse an arm instruction mnemonic followed by its operands.
2361 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
2362 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2363 // Create the leading tokens for the mnemonic, split by '.' characters.
2364 size_t Start = 0, Next = Name.find('.');
2365 StringRef Mnemonic = Name.slice(Start, Next);
2367 // Split out the predication code and carry setting flag from the mnemonic.
2368 unsigned PredicationCode;
2369 unsigned ProcessorIMod;
2371 Mnemonic = SplitMnemonic(Mnemonic, PredicationCode, CarrySetting,
2374 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
2376 // FIXME: This is all a pretty gross hack. We should automatically handle
2377 // optional operands like this via tblgen.
2379 // Next, add the CCOut and ConditionCode operands, if needed.
2381 // For mnemonics which can ever incorporate a carry setting bit or predication
2382 // code, our matching model involves us always generating CCOut and
2383 // ConditionCode operands to match the mnemonic "as written" and then we let
2384 // the matcher deal with finding the right instruction or generating an
2385 // appropriate error.
2386 bool CanAcceptCarrySet, CanAcceptPredicationCode;
2387 GetMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
2389 // If we had a carry-set on an instruction that can't do that, issue an
2391 if (!CanAcceptCarrySet && CarrySetting) {
2392 Parser.EatToEndOfStatement();
2393 return Error(NameLoc, "instruction '" + Mnemonic +
2394 "' can not set flags, but 's' suffix specified");
2396 // If we had a predication code on an instruction that can't do that, issue an
2398 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
2399 Parser.EatToEndOfStatement();
2400 return Error(NameLoc, "instruction '" + Mnemonic +
2401 "' is not predicable, but condition code specified");
2404 // Add the carry setting operand, if necessary.
2406 // FIXME: It would be awesome if we could somehow invent a location such that
2407 // match errors on this operand would print a nice diagnostic about how the
2408 // 's' character in the mnemonic resulted in a CCOut operand.
2409 if (CanAcceptCarrySet)
2410 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
2413 // Add the predication code operand, if necessary.
2414 if (CanAcceptPredicationCode) {
2415 Operands.push_back(ARMOperand::CreateCondCode(
2416 ARMCC::CondCodes(PredicationCode), NameLoc));
2419 // Add the processor imod operand, if necessary.
2420 if (ProcessorIMod) {
2421 Operands.push_back(ARMOperand::CreateImm(
2422 MCConstantExpr::Create(ProcessorIMod, getContext()),
2425 // This mnemonic can't ever accept a imod, but the user wrote
2426 // one (or misspelled another mnemonic).
2428 // FIXME: Issue a nice error.
2431 // Add the remaining tokens in the mnemonic.
2432 while (Next != StringRef::npos) {
2434 Next = Name.find('.', Start + 1);
2435 StringRef ExtraToken = Name.slice(Start, Next);
2437 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
2440 // Read the remaining operands.
2441 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2442 // Read the first operand.
2443 if (ParseOperand(Operands, Mnemonic)) {
2444 Parser.EatToEndOfStatement();
2448 while (getLexer().is(AsmToken::Comma)) {
2449 Parser.Lex(); // Eat the comma.
2451 // Parse and remember the operand.
2452 if (ParseOperand(Operands, Mnemonic)) {
2453 Parser.EatToEndOfStatement();
2459 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2460 Parser.EatToEndOfStatement();
2461 return TokError("unexpected token in argument list");
2464 Parser.Lex(); // Consume the EndOfStatement
2467 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
2468 // another does not. Specifically, the MOVW instruction does not. So we
2469 // special case it here and remove the defaulted (non-setting) cc_out
2470 // operand if that's the instruction we're trying to match.
2472 // We do this post-processing of the explicit operands rather than just
2473 // conditionally adding the cc_out in the first place because we need
2474 // to check the type of the parsed immediate operand.
2475 if (Mnemonic == "mov" && Operands.size() > 4 &&
2476 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
2477 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
2478 static_cast<ARMOperand*>(Operands[1])->getReg() == 0) {
2479 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
2480 Operands.erase(Operands.begin() + 1);
2488 MatchAndEmitInstruction(SMLoc IDLoc,
2489 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2493 MatchResultTy MatchResult;
2494 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
2495 switch (MatchResult) {
2497 Out.EmitInstruction(Inst);
2499 case Match_MissingFeature:
2500 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
2502 case Match_InvalidOperand: {
2503 SMLoc ErrorLoc = IDLoc;
2504 if (ErrorInfo != ~0U) {
2505 if (ErrorInfo >= Operands.size())
2506 return Error(IDLoc, "too few operands for instruction");
2508 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
2509 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
2512 return Error(ErrorLoc, "invalid operand for instruction");
2514 case Match_MnemonicFail:
2515 return Error(IDLoc, "unrecognized instruction mnemonic");
2516 case Match_ConversionFail:
2517 return Error(IDLoc, "unable to convert operands to instruction");
2520 llvm_unreachable("Implement any new match types added!");
2524 /// ParseDirective parses the arm specific directives
2525 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
2526 StringRef IDVal = DirectiveID.getIdentifier();
2527 if (IDVal == ".word")
2528 return ParseDirectiveWord(4, DirectiveID.getLoc());
2529 else if (IDVal == ".thumb")
2530 return ParseDirectiveThumb(DirectiveID.getLoc());
2531 else if (IDVal == ".thumb_func")
2532 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
2533 else if (IDVal == ".code")
2534 return ParseDirectiveCode(DirectiveID.getLoc());
2535 else if (IDVal == ".syntax")
2536 return ParseDirectiveSyntax(DirectiveID.getLoc());
2540 /// ParseDirectiveWord
2541 /// ::= .word [ expression (, expression)* ]
2542 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
2543 if (getLexer().isNot(AsmToken::EndOfStatement)) {
2545 const MCExpr *Value;
2546 if (getParser().ParseExpression(Value))
2549 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
2551 if (getLexer().is(AsmToken::EndOfStatement))
2554 // FIXME: Improve diagnostic.
2555 if (getLexer().isNot(AsmToken::Comma))
2556 return Error(L, "unexpected token in directive");
2565 /// ParseDirectiveThumb
2567 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
2568 if (getLexer().isNot(AsmToken::EndOfStatement))
2569 return Error(L, "unexpected token in directive");
2572 // TODO: set thumb mode
2573 // TODO: tell the MC streamer the mode
2574 // getParser().getStreamer().Emit???();
2578 /// ParseDirectiveThumbFunc
2579 /// ::= .thumbfunc symbol_name
2580 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
2581 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
2582 bool isMachO = MAI.hasSubsectionsViaSymbols();
2585 // Darwin asm has function name after .thumb_func direction
2588 const AsmToken &Tok = Parser.getTok();
2589 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
2590 return Error(L, "unexpected token in .thumb_func directive");
2591 Name = Tok.getString();
2592 Parser.Lex(); // Consume the identifier token.
2595 if (getLexer().isNot(AsmToken::EndOfStatement))
2596 return Error(L, "unexpected token in directive");
2599 // FIXME: assuming function name will be the line following .thumb_func
2601 Name = Parser.getTok().getString();
2604 // Mark symbol as a thumb symbol.
2605 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
2606 getParser().getStreamer().EmitThumbFunc(Func);
2610 /// ParseDirectiveSyntax
2611 /// ::= .syntax unified | divided
2612 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
2613 const AsmToken &Tok = Parser.getTok();
2614 if (Tok.isNot(AsmToken::Identifier))
2615 return Error(L, "unexpected token in .syntax directive");
2616 StringRef Mode = Tok.getString();
2617 if (Mode == "unified" || Mode == "UNIFIED")
2619 else if (Mode == "divided" || Mode == "DIVIDED")
2620 return Error(L, "'.syntax divided' arm asssembly not supported");
2622 return Error(L, "unrecognized syntax mode in .syntax directive");
2624 if (getLexer().isNot(AsmToken::EndOfStatement))
2625 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2628 // TODO tell the MC streamer the mode
2629 // getParser().getStreamer().Emit???();
2633 /// ParseDirectiveCode
2634 /// ::= .code 16 | 32
2635 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
2636 const AsmToken &Tok = Parser.getTok();
2637 if (Tok.isNot(AsmToken::Integer))
2638 return Error(L, "unexpected token in .code directive");
2639 int64_t Val = Parser.getTok().getIntVal();
2645 return Error(L, "invalid operand to .code directive");
2647 if (getLexer().isNot(AsmToken::EndOfStatement))
2648 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
2654 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
2658 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
2664 extern "C" void LLVMInitializeARMAsmLexer();
2666 /// Force static initialization.
2667 extern "C" void LLVMInitializeARMAsmParser() {
2668 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
2669 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
2670 LLVMInitializeARMAsmLexer();
2673 #define GET_REGISTER_MATCHER
2674 #define GET_MATCHER_IMPLEMENTATION
2675 #include "ARMGenAsmMatcher.inc"