1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMAddressingModes.h"
12 #include "ARMMCExpr.h"
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARMSubtarget.h"
15 #include "llvm/MC/MCParser/MCAsmLexer.h"
16 #include "llvm/MC/MCParser/MCAsmParser.h"
17 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCStreamer.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCInst.h"
22 #include "llvm/Target/TargetRegistry.h"
23 #include "llvm/Target/TargetAsmParser.h"
24 #include "llvm/Support/SourceMgr.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/StringExtras.h"
28 #include "llvm/ADT/StringSwitch.h"
29 #include "llvm/ADT/Twine.h"
32 /// Shift types used for register controlled shifts in ARM memory addressing.
45 class ARMAsmParser : public TargetAsmParser {
49 MCAsmParser &getParser() const { return Parser; }
50 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
52 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
53 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
55 int TryParseRegister();
56 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
57 bool TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
58 bool ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
59 bool ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
60 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
61 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
62 const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
63 MCSymbolRefExpr::VariantKind Variant);
66 bool ParseMemoryOffsetReg(bool &Negative,
67 bool &OffsetRegShifted,
68 enum ShiftType &ShiftType,
69 const MCExpr *&ShiftAmount,
70 const MCExpr *&Offset,
74 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
75 bool ParseDirectiveWord(unsigned Size, SMLoc L);
76 bool ParseDirectiveThumb(SMLoc L);
77 bool ParseDirectiveThumbFunc(SMLoc L);
78 bool ParseDirectiveCode(SMLoc L);
79 bool ParseDirectiveSyntax(SMLoc L);
81 bool MatchAndEmitInstruction(SMLoc IDLoc,
82 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
84 void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
85 bool &CanAcceptPredicationCode);
87 /// @name Auto-generated Match Functions
90 #define GET_ASSEMBLER_HEADER
91 #include "ARMGenAsmMatcher.inc"
95 OperandMatchResultTy tryParseCoprocNumOperand(
96 SmallVectorImpl<MCParsedAsmOperand*>&);
97 OperandMatchResultTy tryParseCoprocRegOperand(
98 SmallVectorImpl<MCParsedAsmOperand*>&);
99 OperandMatchResultTy tryParseMemBarrierOptOperand(
100 SmallVectorImpl<MCParsedAsmOperand*> &);
101 OperandMatchResultTy tryParseProcIFlagsOperand(
102 SmallVectorImpl<MCParsedAsmOperand*> &);
105 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
106 : TargetAsmParser(T), Parser(_Parser), TM(_TM) {
107 // Initialize the set of available features.
108 setAvailableFeatures(ComputeAvailableFeatures(
109 &TM.getSubtarget<ARMSubtarget>()));
112 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
113 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
114 virtual bool ParseDirective(AsmToken DirectiveID);
116 } // end anonymous namespace
120 /// ARMOperand - Instances of this class represent a parsed ARM machine
122 class ARMOperand : public MCParsedAsmOperand {
139 SMLoc StartLoc, EndLoc;
140 SmallVector<unsigned, 8> Registers;
144 ARMCC::CondCodes Val;
156 ARM_PROC::IFlags Val;
172 /// Combined record for all forms of ARM address expressions.
176 unsigned RegNum; ///< Offset register num, when OffsetIsReg.
177 const MCExpr *Value; ///< Offset value, when !OffsetIsReg.
179 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
180 enum ShiftType ShiftType; // used when OffsetRegShifted is true
181 unsigned OffsetRegShifted : 1; // only used when OffsetIsReg is true
182 unsigned Preindexed : 1;
183 unsigned Postindexed : 1;
184 unsigned OffsetIsReg : 1;
185 unsigned Negative : 1; // only used when OffsetIsReg is true
186 unsigned Writeback : 1;
190 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
192 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
194 StartLoc = o.StartLoc;
208 case DPRRegisterList:
209 case SPRRegisterList:
210 Registers = o.Registers;
230 /// getStartLoc - Get the location of the first token of this operand.
231 SMLoc getStartLoc() const { return StartLoc; }
232 /// getEndLoc - Get the location of the last token of this operand.
233 SMLoc getEndLoc() const { return EndLoc; }
235 ARMCC::CondCodes getCondCode() const {
236 assert(Kind == CondCode && "Invalid access!");
240 unsigned getCoproc() const {
241 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
245 StringRef getToken() const {
246 assert(Kind == Token && "Invalid access!");
247 return StringRef(Tok.Data, Tok.Length);
250 unsigned getReg() const {
251 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
255 const SmallVectorImpl<unsigned> &getRegList() const {
256 assert((Kind == RegisterList || Kind == DPRRegisterList ||
257 Kind == SPRRegisterList) && "Invalid access!");
261 const MCExpr *getImm() const {
262 assert(Kind == Immediate && "Invalid access!");
266 ARM_MB::MemBOpt getMemBarrierOpt() const {
267 assert(Kind == MemBarrierOpt && "Invalid access!");
271 ARM_PROC::IFlags getProcIFlags() const {
272 assert(Kind == ProcIFlags && "Invalid access!");
276 /// @name Memory Operand Accessors
279 unsigned getMemBaseRegNum() const {
280 return Mem.BaseRegNum;
282 unsigned getMemOffsetRegNum() const {
283 assert(Mem.OffsetIsReg && "Invalid access!");
284 return Mem.Offset.RegNum;
286 const MCExpr *getMemOffset() const {
287 assert(!Mem.OffsetIsReg && "Invalid access!");
288 return Mem.Offset.Value;
290 unsigned getMemOffsetRegShifted() const {
291 assert(Mem.OffsetIsReg && "Invalid access!");
292 return Mem.OffsetRegShifted;
294 const MCExpr *getMemShiftAmount() const {
295 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
296 return Mem.ShiftAmount;
298 enum ShiftType getMemShiftType() const {
299 assert(Mem.OffsetIsReg && Mem.OffsetRegShifted && "Invalid access!");
300 return Mem.ShiftType;
302 bool getMemPreindexed() const { return Mem.Preindexed; }
303 bool getMemPostindexed() const { return Mem.Postindexed; }
304 bool getMemOffsetIsReg() const { return Mem.OffsetIsReg; }
305 bool getMemNegative() const { return Mem.Negative; }
306 bool getMemWriteback() const { return Mem.Writeback; }
310 bool isCoprocNum() const { return Kind == CoprocNum; }
311 bool isCoprocReg() const { return Kind == CoprocReg; }
312 bool isCondCode() const { return Kind == CondCode; }
313 bool isCCOut() const { return Kind == CCOut; }
314 bool isImm() const { return Kind == Immediate; }
315 bool isReg() const { return Kind == Register; }
316 bool isRegList() const { return Kind == RegisterList; }
317 bool isDPRRegList() const { return Kind == DPRRegisterList; }
318 bool isSPRRegList() const { return Kind == SPRRegisterList; }
319 bool isToken() const { return Kind == Token; }
320 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
321 bool isMemory() const { return Kind == Memory; }
322 bool isMemMode5() const {
323 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
327 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
328 if (!CE) return false;
330 // The offset must be a multiple of 4 in the range 0-1020.
331 int64_t Value = CE->getValue();
332 return ((Value & 0x3) == 0 && Value <= 1020 && Value >= -1020);
334 bool isMemModeRegThumb() const {
335 if (!isMemory() || !getMemOffsetIsReg() || getMemWriteback())
339 bool isMemModeImmThumb() const {
340 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback())
343 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
344 if (!CE) return false;
346 // The offset must be a multiple of 4 in the range 0-124.
347 uint64_t Value = CE->getValue();
348 return ((Value & 0x3) == 0 && Value <= 124);
350 bool isProcIFlags() const { return Kind == ProcIFlags; }
352 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
353 // Add as immediates when possible. Null MCExpr = 0.
355 Inst.addOperand(MCOperand::CreateImm(0));
356 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
357 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
359 Inst.addOperand(MCOperand::CreateExpr(Expr));
362 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
363 assert(N == 2 && "Invalid number of operands!");
364 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
365 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
366 Inst.addOperand(MCOperand::CreateReg(RegNum));
369 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
370 assert(N == 1 && "Invalid number of operands!");
371 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
374 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
375 assert(N == 1 && "Invalid number of operands!");
376 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
379 void addCCOutOperands(MCInst &Inst, unsigned N) const {
380 assert(N == 1 && "Invalid number of operands!");
381 Inst.addOperand(MCOperand::CreateReg(getReg()));
384 void addRegOperands(MCInst &Inst, unsigned N) const {
385 assert(N == 1 && "Invalid number of operands!");
386 Inst.addOperand(MCOperand::CreateReg(getReg()));
389 void addRegListOperands(MCInst &Inst, unsigned N) const {
390 assert(N == 1 && "Invalid number of operands!");
391 const SmallVectorImpl<unsigned> &RegList = getRegList();
392 for (SmallVectorImpl<unsigned>::const_iterator
393 I = RegList.begin(), E = RegList.end(); I != E; ++I)
394 Inst.addOperand(MCOperand::CreateReg(*I));
397 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
398 addRegListOperands(Inst, N);
401 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
402 addRegListOperands(Inst, N);
405 void addImmOperands(MCInst &Inst, unsigned N) const {
406 assert(N == 1 && "Invalid number of operands!");
407 addExpr(Inst, getImm());
410 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
411 assert(N == 1 && "Invalid number of operands!");
412 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
415 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
416 assert(N == 2 && isMemMode5() && "Invalid number of operands!");
418 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
419 assert(!getMemOffsetIsReg() && "Invalid mode 5 operand");
421 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
423 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
424 assert(CE && "Non-constant mode 5 offset operand!");
426 // The MCInst offset operand doesn't include the low two bits (like
427 // the instruction encoding).
428 int64_t Offset = CE->getValue() / 4;
430 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add,
433 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub,
437 void addMemModeRegThumbOperands(MCInst &Inst, unsigned N) const {
438 assert(N == 2 && isMemModeRegThumb() && "Invalid number of operands!");
439 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
440 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
443 void addMemModeImmThumbOperands(MCInst &Inst, unsigned N) const {
444 assert(N == 2 && isMemModeImmThumb() && "Invalid number of operands!");
445 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
446 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
447 assert(CE && "Non-constant mode offset operand!");
448 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
451 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
452 assert(N == 1 && "Invalid number of operands!");
453 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
456 virtual void dump(raw_ostream &OS) const;
458 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
459 ARMOperand *Op = new ARMOperand(CondCode);
466 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
467 ARMOperand *Op = new ARMOperand(CoprocNum);
468 Op->Cop.Val = CopVal;
474 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
475 ARMOperand *Op = new ARMOperand(CoprocReg);
476 Op->Cop.Val = CopVal;
482 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
483 ARMOperand *Op = new ARMOperand(CCOut);
484 Op->Reg.RegNum = RegNum;
490 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
491 ARMOperand *Op = new ARMOperand(Token);
492 Op->Tok.Data = Str.data();
493 Op->Tok.Length = Str.size();
499 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
500 ARMOperand *Op = new ARMOperand(Register);
501 Op->Reg.RegNum = RegNum;
508 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
509 SMLoc StartLoc, SMLoc EndLoc) {
510 KindTy Kind = RegisterList;
512 if (ARM::DPRRegClass.contains(Regs.front().first))
513 Kind = DPRRegisterList;
514 else if (ARM::SPRRegClass.contains(Regs.front().first))
515 Kind = SPRRegisterList;
517 ARMOperand *Op = new ARMOperand(Kind);
518 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
519 I = Regs.begin(), E = Regs.end(); I != E; ++I)
520 Op->Registers.push_back(I->first);
521 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
522 Op->StartLoc = StartLoc;
527 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
528 ARMOperand *Op = new ARMOperand(Immediate);
535 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
536 const MCExpr *Offset, int OffsetRegNum,
537 bool OffsetRegShifted, enum ShiftType ShiftType,
538 const MCExpr *ShiftAmount, bool Preindexed,
539 bool Postindexed, bool Negative, bool Writeback,
541 assert((OffsetRegNum == -1 || OffsetIsReg) &&
542 "OffsetRegNum must imply OffsetIsReg!");
543 assert((!OffsetRegShifted || OffsetIsReg) &&
544 "OffsetRegShifted must imply OffsetIsReg!");
545 assert((Offset || OffsetIsReg) &&
546 "Offset must exists unless register offset is used!");
547 assert((!ShiftAmount || (OffsetIsReg && OffsetRegShifted)) &&
548 "Cannot have shift amount without shifted register offset!");
549 assert((!Offset || !OffsetIsReg) &&
550 "Cannot have expression offset and register offset!");
552 ARMOperand *Op = new ARMOperand(Memory);
553 Op->Mem.BaseRegNum = BaseRegNum;
554 Op->Mem.OffsetIsReg = OffsetIsReg;
556 Op->Mem.Offset.RegNum = OffsetRegNum;
558 Op->Mem.Offset.Value = Offset;
559 Op->Mem.OffsetRegShifted = OffsetRegShifted;
560 Op->Mem.ShiftType = ShiftType;
561 Op->Mem.ShiftAmount = ShiftAmount;
562 Op->Mem.Preindexed = Preindexed;
563 Op->Mem.Postindexed = Postindexed;
564 Op->Mem.Negative = Negative;
565 Op->Mem.Writeback = Writeback;
572 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
573 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
580 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
581 ARMOperand *Op = new ARMOperand(ProcIFlags);
582 Op->IFlags.Val = IFlags;
589 } // end anonymous namespace.
591 void ARMOperand::dump(raw_ostream &OS) const {
594 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
597 OS << "<ccout " << getReg() << ">";
600 OS << "<coprocessor number: " << getCoproc() << ">";
603 OS << "<coprocessor register: " << getCoproc() << ">";
609 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
613 << "base:" << getMemBaseRegNum();
614 if (getMemOffsetIsReg()) {
615 OS << " offset:<register " << getMemOffsetRegNum();
616 if (getMemOffsetRegShifted()) {
617 OS << " offset-shift-type:" << getMemShiftType();
618 OS << " offset-shift-amount:" << *getMemShiftAmount();
621 OS << " offset:" << *getMemOffset();
623 if (getMemOffsetIsReg())
624 OS << " (offset-is-reg)";
625 if (getMemPreindexed())
626 OS << " (pre-indexed)";
627 if (getMemPostindexed())
628 OS << " (post-indexed)";
629 if (getMemNegative())
631 if (getMemWriteback())
632 OS << " (writeback)";
637 unsigned IFlags = getProcIFlags();
638 for (int i=2; i >= 0; --i)
639 if (IFlags & (1 << i))
640 OS << ARM_PROC::IFlagsToString(1 << i);
645 OS << "<register " << getReg() << ">";
648 case DPRRegisterList:
649 case SPRRegisterList: {
650 OS << "<register_list ";
652 const SmallVectorImpl<unsigned> &RegList = getRegList();
653 for (SmallVectorImpl<unsigned>::const_iterator
654 I = RegList.begin(), E = RegList.end(); I != E; ) {
656 if (++I < E) OS << ", ";
663 OS << "'" << getToken() << "'";
668 /// @name Auto-generated Match Functions
671 static unsigned MatchRegisterName(StringRef Name);
675 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
676 SMLoc &StartLoc, SMLoc &EndLoc) {
677 RegNo = TryParseRegister();
679 return (RegNo == (unsigned)-1);
682 /// Try to parse a register name. The token must be an Identifier when called,
683 /// and if it is a register name the token is eaten and the register number is
684 /// returned. Otherwise return -1.
686 int ARMAsmParser::TryParseRegister() {
687 const AsmToken &Tok = Parser.getTok();
688 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
690 // FIXME: Validate register for the current architecture; we have to do
691 // validation later, so maybe there is no need for this here.
692 std::string upperCase = Tok.getString().str();
693 std::string lowerCase = LowercaseString(upperCase);
694 unsigned RegNum = MatchRegisterName(lowerCase);
696 RegNum = StringSwitch<unsigned>(lowerCase)
697 .Case("r13", ARM::SP)
698 .Case("r14", ARM::LR)
699 .Case("r15", ARM::PC)
700 .Case("ip", ARM::R12)
703 if (!RegNum) return -1;
705 Parser.Lex(); // Eat identifier token.
709 /// Try to parse a register name. The token must be an Identifier when called.
710 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
711 /// if there is a "writeback". 'true' if it's not a register.
713 /// TODO this is likely to change to allow different register types and or to
714 /// parse for a specific register type.
716 TryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
717 SMLoc S = Parser.getTok().getLoc();
718 int RegNo = TryParseRegister();
722 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
724 const AsmToken &ExclaimTok = Parser.getTok();
725 if (ExclaimTok.is(AsmToken::Exclaim)) {
726 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
727 ExclaimTok.getLoc()));
728 Parser.Lex(); // Eat exclaim token
734 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
735 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
737 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
738 // Use the same layout as the tablegen'erated register name matcher. Ugly,
740 switch (Name.size()) {
743 if (Name[0] != CoprocOp)
760 if (Name[0] != CoprocOp || Name[1] != '1')
777 /// tryParseCoprocNumOperand - Try to parse an coprocessor number operand. The
778 /// token must be an Identifier when called, and if it is a coprocessor
779 /// number, the token is eaten and the operand is added to the operand list.
780 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
781 tryParseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
782 SMLoc S = Parser.getTok().getLoc();
783 const AsmToken &Tok = Parser.getTok();
784 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
786 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
788 return MatchOperand_NoMatch;
790 Parser.Lex(); // Eat identifier token.
791 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
792 return MatchOperand_Success;
795 /// tryParseCoprocRegOperand - Try to parse an coprocessor register operand. The
796 /// token must be an Identifier when called, and if it is a coprocessor
797 /// number, the token is eaten and the operand is added to the operand list.
798 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
799 tryParseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
800 SMLoc S = Parser.getTok().getLoc();
801 const AsmToken &Tok = Parser.getTok();
802 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
804 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
806 return MatchOperand_NoMatch;
808 Parser.Lex(); // Eat identifier token.
809 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
810 return MatchOperand_Success;
813 /// Parse a register list, return it if successful else return null. The first
814 /// token must be a '{' when called.
816 ParseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
817 assert(Parser.getTok().is(AsmToken::LCurly) &&
818 "Token is not a Left Curly Brace");
819 SMLoc S = Parser.getTok().getLoc();
821 // Read the rest of the registers in the list.
822 unsigned PrevRegNum = 0;
823 SmallVector<std::pair<unsigned, SMLoc>, 32> Registers;
826 bool IsRange = Parser.getTok().is(AsmToken::Minus);
827 Parser.Lex(); // Eat non-identifier token.
829 const AsmToken &RegTok = Parser.getTok();
830 SMLoc RegLoc = RegTok.getLoc();
831 if (RegTok.isNot(AsmToken::Identifier)) {
832 Error(RegLoc, "register expected");
836 int RegNum = TryParseRegister();
838 Error(RegLoc, "register expected");
843 int Reg = PrevRegNum;
846 Registers.push_back(std::make_pair(Reg, RegLoc));
847 } while (Reg != RegNum);
849 Registers.push_back(std::make_pair(RegNum, RegLoc));
853 } while (Parser.getTok().is(AsmToken::Comma) ||
854 Parser.getTok().is(AsmToken::Minus));
856 // Process the right curly brace of the list.
857 const AsmToken &RCurlyTok = Parser.getTok();
858 if (RCurlyTok.isNot(AsmToken::RCurly)) {
859 Error(RCurlyTok.getLoc(), "'}' expected");
863 SMLoc E = RCurlyTok.getLoc();
864 Parser.Lex(); // Eat right curly brace token.
866 // Verify the register list.
867 SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
868 RI = Registers.begin(), RE = Registers.end();
870 unsigned HighRegNum = getARMRegisterNumbering(RI->first);
871 bool EmittedWarning = false;
873 DenseMap<unsigned, bool> RegMap;
874 RegMap[HighRegNum] = true;
876 for (++RI; RI != RE; ++RI) {
877 const std::pair<unsigned, SMLoc> &RegInfo = *RI;
878 unsigned Reg = getARMRegisterNumbering(RegInfo.first);
881 Error(RegInfo.second, "register duplicated in register list");
885 if (!EmittedWarning && Reg < HighRegNum)
886 Warning(RegInfo.second,
887 "register not in ascending order in register list");
890 HighRegNum = std::max(Reg, HighRegNum);
893 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
897 /// tryParseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
898 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
899 tryParseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
900 SMLoc S = Parser.getTok().getLoc();
901 const AsmToken &Tok = Parser.getTok();
902 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
903 StringRef OptStr = Tok.getString();
905 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
906 .Case("sy", ARM_MB::SY)
907 .Case("st", ARM_MB::ST)
908 .Case("ish", ARM_MB::ISH)
909 .Case("ishst", ARM_MB::ISHST)
910 .Case("nsh", ARM_MB::NSH)
911 .Case("nshst", ARM_MB::NSHST)
912 .Case("osh", ARM_MB::OSH)
913 .Case("oshst", ARM_MB::OSHST)
917 return MatchOperand_NoMatch;
919 Parser.Lex(); // Eat identifier token.
920 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
921 return MatchOperand_Success;
924 /// ParseProcIFlagsOperand - Try to parse iflags from CPS instruction.
925 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
926 tryParseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
927 SMLoc S = Parser.getTok().getLoc();
928 const AsmToken &Tok = Parser.getTok();
929 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
930 StringRef IFlagsStr = Tok.getString();
933 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
934 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
935 .Case("a", ARM_PROC::A)
936 .Case("i", ARM_PROC::I)
937 .Case("f", ARM_PROC::F)
940 // If some specific iflag is already set, it means that some letter is
941 // present more than once, this is not acceptable.
942 if (Flag == ~0U || (IFlags & Flag))
943 return MatchOperand_NoMatch;
948 Parser.Lex(); // Eat identifier token.
949 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
950 return MatchOperand_Success;
953 /// Parse an ARM memory expression, return false if successful else return true
954 /// or an error. The first token must be a '[' when called.
956 /// TODO Only preindexing and postindexing addressing are started, unindexed
957 /// with option, etc are still to do.
959 ParseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
961 assert(Parser.getTok().is(AsmToken::LBrac) &&
962 "Token is not a Left Bracket");
963 S = Parser.getTok().getLoc();
964 Parser.Lex(); // Eat left bracket token.
966 const AsmToken &BaseRegTok = Parser.getTok();
967 if (BaseRegTok.isNot(AsmToken::Identifier)) {
968 Error(BaseRegTok.getLoc(), "register expected");
971 int BaseRegNum = TryParseRegister();
972 if (BaseRegNum == -1) {
973 Error(BaseRegTok.getLoc(), "register expected");
977 // The next token must either be a comma or a closing bracket.
978 const AsmToken &Tok = Parser.getTok();
979 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
982 bool Preindexed = false;
983 bool Postindexed = false;
984 bool OffsetIsReg = false;
985 bool Negative = false;
986 bool Writeback = false;
987 ARMOperand *WBOp = 0;
988 int OffsetRegNum = -1;
989 bool OffsetRegShifted = false;
990 enum ShiftType ShiftType = Lsl;
991 const MCExpr *ShiftAmount = 0;
992 const MCExpr *Offset = 0;
994 // First look for preindexed address forms, that is after the "[Rn" we now
995 // have to see if the next token is a comma.
996 if (Tok.is(AsmToken::Comma)) {
998 Parser.Lex(); // Eat comma token.
1000 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
1001 Offset, OffsetIsReg, OffsetRegNum, E))
1003 const AsmToken &RBracTok = Parser.getTok();
1004 if (RBracTok.isNot(AsmToken::RBrac)) {
1005 Error(RBracTok.getLoc(), "']' expected");
1008 E = RBracTok.getLoc();
1009 Parser.Lex(); // Eat right bracket token.
1011 const AsmToken &ExclaimTok = Parser.getTok();
1012 if (ExclaimTok.is(AsmToken::Exclaim)) {
1013 WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
1014 ExclaimTok.getLoc());
1016 Parser.Lex(); // Eat exclaim token
1019 // The "[Rn" we have so far was not followed by a comma.
1021 // If there's anything other than the right brace, this is a post indexing
1024 Parser.Lex(); // Eat right bracket token.
1026 const AsmToken &NextTok = Parser.getTok();
1028 if (NextTok.isNot(AsmToken::EndOfStatement)) {
1032 if (NextTok.isNot(AsmToken::Comma)) {
1033 Error(NextTok.getLoc(), "',' expected");
1037 Parser.Lex(); // Eat comma token.
1039 if (ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
1040 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
1046 // Force Offset to exist if used.
1049 Offset = MCConstantExpr::Create(0, getContext());
1052 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
1053 OffsetRegNum, OffsetRegShifted,
1054 ShiftType, ShiftAmount, Preindexed,
1055 Postindexed, Negative, Writeback,
1058 Operands.push_back(WBOp);
1063 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
1064 /// we will parse the following (were +/- means that a plus or minus is
1069 /// we return false on success or an error otherwise.
1070 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
1071 bool &OffsetRegShifted,
1072 enum ShiftType &ShiftType,
1073 const MCExpr *&ShiftAmount,
1074 const MCExpr *&Offset,
1079 OffsetRegShifted = false;
1080 OffsetIsReg = false;
1082 const AsmToken &NextTok = Parser.getTok();
1083 E = NextTok.getLoc();
1084 if (NextTok.is(AsmToken::Plus))
1085 Parser.Lex(); // Eat plus token.
1086 else if (NextTok.is(AsmToken::Minus)) {
1088 Parser.Lex(); // Eat minus token
1090 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
1091 const AsmToken &OffsetRegTok = Parser.getTok();
1092 if (OffsetRegTok.is(AsmToken::Identifier)) {
1093 SMLoc CurLoc = OffsetRegTok.getLoc();
1094 OffsetRegNum = TryParseRegister();
1095 if (OffsetRegNum != -1) {
1101 // If we parsed a register as the offset then there can be a shift after that.
1102 if (OffsetRegNum != -1) {
1103 // Look for a comma then a shift
1104 const AsmToken &Tok = Parser.getTok();
1105 if (Tok.is(AsmToken::Comma)) {
1106 Parser.Lex(); // Eat comma token.
1108 const AsmToken &Tok = Parser.getTok();
1109 if (ParseShift(ShiftType, ShiftAmount, E))
1110 return Error(Tok.getLoc(), "shift expected");
1111 OffsetRegShifted = true;
1114 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
1115 // Look for #offset following the "[Rn," or "[Rn],"
1116 const AsmToken &HashTok = Parser.getTok();
1117 if (HashTok.isNot(AsmToken::Hash))
1118 return Error(HashTok.getLoc(), "'#' expected");
1120 Parser.Lex(); // Eat hash token.
1122 if (getParser().ParseExpression(Offset))
1124 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1129 /// ParseShift as one of these two:
1130 /// ( lsl | lsr | asr | ror ) , # shift_amount
1132 /// and returns true if it parses a shift otherwise it returns false.
1133 bool ARMAsmParser::ParseShift(ShiftType &St, const MCExpr *&ShiftAmount,
1135 const AsmToken &Tok = Parser.getTok();
1136 if (Tok.isNot(AsmToken::Identifier))
1138 StringRef ShiftName = Tok.getString();
1139 if (ShiftName == "lsl" || ShiftName == "LSL")
1141 else if (ShiftName == "lsr" || ShiftName == "LSR")
1143 else if (ShiftName == "asr" || ShiftName == "ASR")
1145 else if (ShiftName == "ror" || ShiftName == "ROR")
1147 else if (ShiftName == "rrx" || ShiftName == "RRX")
1151 Parser.Lex(); // Eat shift type token.
1153 // Rrx stands alone.
1157 // Otherwise, there must be a '#' and a shift amount.
1158 const AsmToken &HashTok = Parser.getTok();
1159 if (HashTok.isNot(AsmToken::Hash))
1160 return Error(HashTok.getLoc(), "'#' expected");
1161 Parser.Lex(); // Eat hash token.
1163 if (getParser().ParseExpression(ShiftAmount))
1169 /// Parse a arm instruction operand. For now this parses the operand regardless
1170 /// of the mnemonic.
1171 bool ARMAsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1172 StringRef Mnemonic) {
1175 // Check if the current operand has a custom associated parser, if so, try to
1176 // custom parse the operand, or fallback to the general approach.
1177 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
1178 if (ResTy == MatchOperand_Success)
1180 // If there wasn't a custom match, try the generic matcher below. Otherwise,
1181 // there was a match, but an error occurred, in which case, just return that
1182 // the operand parsing failed.
1183 if (ResTy == MatchOperand_ParseFail)
1186 switch (getLexer().getKind()) {
1188 Error(Parser.getTok().getLoc(), "unexpected token in operand");
1190 case AsmToken::Identifier:
1191 if (!TryParseRegisterWithWriteBack(Operands))
1194 // Fall though for the Identifier case that is not a register or a
1196 case AsmToken::Integer: // things like 1f and 2b as a branch targets
1197 case AsmToken::Dot: { // . as a branch target
1198 // This was not a register so parse other operands that start with an
1199 // identifier (like labels) as expressions and create them as immediates.
1200 const MCExpr *IdVal;
1201 S = Parser.getTok().getLoc();
1202 if (getParser().ParseExpression(IdVal))
1204 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1205 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
1208 case AsmToken::LBrac:
1209 return ParseMemory(Operands);
1210 case AsmToken::LCurly:
1211 return ParseRegisterList(Operands);
1212 case AsmToken::Hash:
1213 // #42 -> immediate.
1214 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
1215 S = Parser.getTok().getLoc();
1217 const MCExpr *ImmVal;
1218 if (getParser().ParseExpression(ImmVal))
1220 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1221 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
1223 case AsmToken::Colon: {
1224 // ":lower16:" and ":upper16:" expression prefixes
1225 // FIXME: Check it's an expression prefix,
1226 // e.g. (FOO - :lower16:BAR) isn't legal.
1227 ARMMCExpr::VariantKind RefKind;
1228 if (ParsePrefix(RefKind))
1231 const MCExpr *SubExprVal;
1232 if (getParser().ParseExpression(SubExprVal))
1235 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
1237 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1238 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
1244 // ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
1245 // :lower16: and :upper16:.
1246 bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) {
1247 RefKind = ARMMCExpr::VK_ARM_None;
1249 // :lower16: and :upper16: modifiers
1250 assert(getLexer().is(AsmToken::Colon) && "expected a :");
1251 Parser.Lex(); // Eat ':'
1253 if (getLexer().isNot(AsmToken::Identifier)) {
1254 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
1258 StringRef IDVal = Parser.getTok().getIdentifier();
1259 if (IDVal == "lower16") {
1260 RefKind = ARMMCExpr::VK_ARM_LO16;
1261 } else if (IDVal == "upper16") {
1262 RefKind = ARMMCExpr::VK_ARM_HI16;
1264 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
1269 if (getLexer().isNot(AsmToken::Colon)) {
1270 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
1273 Parser.Lex(); // Eat the last ':'
1278 ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E,
1279 MCSymbolRefExpr::VariantKind Variant) {
1280 // Recurse over the given expression, rebuilding it to apply the given variant
1281 // to the leftmost symbol.
1282 if (Variant == MCSymbolRefExpr::VK_None)
1285 switch (E->getKind()) {
1286 case MCExpr::Target:
1287 llvm_unreachable("Can't handle target expr yet");
1288 case MCExpr::Constant:
1289 llvm_unreachable("Can't handle lower16/upper16 of constant yet");
1291 case MCExpr::SymbolRef: {
1292 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1294 if (SRE->getKind() != MCSymbolRefExpr::VK_None)
1297 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext());
1301 llvm_unreachable("Can't handle unary expressions yet");
1303 case MCExpr::Binary: {
1304 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1305 const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant);
1306 const MCExpr *RHS = BE->getRHS();
1310 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext());
1314 assert(0 && "Invalid expression kind!");
1318 /// \brief Given a mnemonic, split out possible predication code and carry
1319 /// setting letters to form a canonical mnemonic and flags.
1321 // FIXME: Would be nice to autogen this.
1322 static StringRef SplitMnemonic(StringRef Mnemonic,
1323 unsigned &PredicationCode,
1325 unsigned &ProcessorIMod) {
1326 PredicationCode = ARMCC::AL;
1327 CarrySetting = false;
1330 // Ignore some mnemonics we know aren't predicated forms.
1332 // FIXME: Would be nice to autogen this.
1333 if (Mnemonic == "teq" || Mnemonic == "vceq" ||
1334 Mnemonic == "movs" ||
1335 Mnemonic == "svc" ||
1336 (Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
1337 Mnemonic == "vmls" || Mnemonic == "vnmls") ||
1338 Mnemonic == "vacge" || Mnemonic == "vcge" ||
1339 Mnemonic == "vclt" ||
1340 Mnemonic == "vacgt" || Mnemonic == "vcgt" ||
1341 Mnemonic == "vcle" ||
1342 (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" ||
1343 Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" ||
1344 Mnemonic == "vqdmlal"))
1347 // First, split out any predication code.
1348 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
1349 .Case("eq", ARMCC::EQ)
1350 .Case("ne", ARMCC::NE)
1351 .Case("hs", ARMCC::HS)
1352 .Case("lo", ARMCC::LO)
1353 .Case("mi", ARMCC::MI)
1354 .Case("pl", ARMCC::PL)
1355 .Case("vs", ARMCC::VS)
1356 .Case("vc", ARMCC::VC)
1357 .Case("hi", ARMCC::HI)
1358 .Case("ls", ARMCC::LS)
1359 .Case("ge", ARMCC::GE)
1360 .Case("lt", ARMCC::LT)
1361 .Case("gt", ARMCC::GT)
1362 .Case("le", ARMCC::LE)
1363 .Case("al", ARMCC::AL)
1366 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
1367 PredicationCode = CC;
1370 // Next, determine if we have a carry setting bit. We explicitly ignore all
1371 // the instructions we know end in 's'.
1372 if (Mnemonic.endswith("s") &&
1373 !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" ||
1374 Mnemonic == "movs" || Mnemonic == "mrs" || Mnemonic == "smmls" ||
1375 Mnemonic == "vabs" || Mnemonic == "vcls" || Mnemonic == "vmls" ||
1376 Mnemonic == "vmrs" || Mnemonic == "vnmls" || Mnemonic == "vqabs" ||
1377 Mnemonic == "vrecps" || Mnemonic == "vrsqrts")) {
1378 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
1379 CarrySetting = true;
1382 // The "cps" instruction can have a interrupt mode operand which is glued into
1383 // the mnemonic. Check if this is the case, split it and parse the imod op
1384 if (Mnemonic.startswith("cps")) {
1385 // Split out any imod code.
1387 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
1388 .Case("ie", ARM_PROC::IE)
1389 .Case("id", ARM_PROC::ID)
1392 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
1393 ProcessorIMod = IMod;
1400 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
1401 /// inclusion of carry set or predication code operands.
1403 // FIXME: It would be nice to autogen this.
1405 GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
1406 bool &CanAcceptPredicationCode) {
1407 bool isThumb = TM.getSubtarget<ARMSubtarget>().isThumb();
1409 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
1410 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
1411 Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" ||
1412 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
1413 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mov" ||
1414 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
1415 Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" ||
1416 Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "mvn") {
1417 CanAcceptCarrySet = true;
1419 CanAcceptCarrySet = false;
1422 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
1423 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
1424 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
1425 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
1426 Mnemonic == "dsb" || Mnemonic == "movs" || Mnemonic == "isb" ||
1427 Mnemonic == "clrex" || Mnemonic.startswith("cps")) {
1428 CanAcceptPredicationCode = false;
1430 CanAcceptPredicationCode = true;
1434 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
1435 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
1436 CanAcceptPredicationCode = false;
1439 /// Parse an arm instruction mnemonic followed by its operands.
1440 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
1441 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1442 // Create the leading tokens for the mnemonic, split by '.' characters.
1443 size_t Start = 0, Next = Name.find('.');
1444 StringRef Head = Name.slice(Start, Next);
1446 // Split out the predication code and carry setting flag from the mnemonic.
1447 unsigned PredicationCode;
1448 unsigned ProcessorIMod;
1450 Head = SplitMnemonic(Head, PredicationCode, CarrySetting,
1453 Operands.push_back(ARMOperand::CreateToken(Head, NameLoc));
1455 // Next, add the CCOut and ConditionCode operands, if needed.
1457 // For mnemonics which can ever incorporate a carry setting bit or predication
1458 // code, our matching model involves us always generating CCOut and
1459 // ConditionCode operands to match the mnemonic "as written" and then we let
1460 // the matcher deal with finding the right instruction or generating an
1461 // appropriate error.
1462 bool CanAcceptCarrySet, CanAcceptPredicationCode;
1463 GetMnemonicAcceptInfo(Head, CanAcceptCarrySet, CanAcceptPredicationCode);
1465 // Add the carry setting operand, if necessary.
1467 // FIXME: It would be awesome if we could somehow invent a location such that
1468 // match errors on this operand would print a nice diagnostic about how the
1469 // 's' character in the mnemonic resulted in a CCOut operand.
1470 if (CanAcceptCarrySet) {
1471 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
1474 // This mnemonic can't ever accept a carry set, but the user wrote one (or
1475 // misspelled another mnemonic).
1477 // FIXME: Issue a nice error.
1480 // Add the predication code operand, if necessary.
1481 if (CanAcceptPredicationCode) {
1482 Operands.push_back(ARMOperand::CreateCondCode(
1483 ARMCC::CondCodes(PredicationCode), NameLoc));
1485 // This mnemonic can't ever accept a predication code, but the user wrote
1486 // one (or misspelled another mnemonic).
1488 // FIXME: Issue a nice error.
1491 // Add the processor imod operand, if necessary.
1492 if (ProcessorIMod) {
1493 Operands.push_back(ARMOperand::CreateImm(
1494 MCConstantExpr::Create(ProcessorIMod, getContext()),
1497 // This mnemonic can't ever accept a imod, but the user wrote
1498 // one (or misspelled another mnemonic).
1500 // FIXME: Issue a nice error.
1503 // Add the remaining tokens in the mnemonic.
1504 while (Next != StringRef::npos) {
1506 Next = Name.find('.', Start + 1);
1507 StringRef ExtraToken = Name.slice(Start, Next);
1509 Operands.push_back(ARMOperand::CreateToken(ExtraToken, NameLoc));
1512 // Read the remaining operands.
1513 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1514 // Read the first operand.
1515 if (ParseOperand(Operands, Head)) {
1516 Parser.EatToEndOfStatement();
1520 while (getLexer().is(AsmToken::Comma)) {
1521 Parser.Lex(); // Eat the comma.
1523 // Parse and remember the operand.
1524 if (ParseOperand(Operands, Head)) {
1525 Parser.EatToEndOfStatement();
1531 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1532 Parser.EatToEndOfStatement();
1533 return TokError("unexpected token in argument list");
1536 Parser.Lex(); // Consume the EndOfStatement
1541 MatchAndEmitInstruction(SMLoc IDLoc,
1542 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
1546 MatchResultTy MatchResult, MatchResult2;
1547 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1548 if (MatchResult != Match_Success) {
1549 // If we get a Match_InvalidOperand it might be some arithmetic instruction
1550 // that does not update the condition codes. So try adding a CCOut operand
1551 // with a value of reg0.
1552 if (MatchResult == Match_InvalidOperand) {
1553 Operands.insert(Operands.begin() + 1,
1554 ARMOperand::CreateCCOut(0,
1555 ((ARMOperand*)Operands[0])->getStartLoc()));
1556 MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1557 if (MatchResult2 == Match_Success)
1558 MatchResult = Match_Success;
1560 ARMOperand *CCOut = ((ARMOperand*)Operands[1]);
1561 Operands.erase(Operands.begin() + 1);
1565 // If we get a Match_MnemonicFail it might be some arithmetic instruction
1566 // that updates the condition codes if it ends in 's'. So see if the
1567 // mnemonic ends in 's' and if so try removing the 's' and adding a CCOut
1568 // operand with a value of CPSR.
1569 else if(MatchResult == Match_MnemonicFail) {
1570 // Get the instruction mnemonic, which is the first token.
1571 StringRef Mnemonic = ((ARMOperand*)Operands[0])->getToken();
1572 if (Mnemonic.substr(Mnemonic.size()-1) == "s") {
1573 // removed the 's' from the mnemonic for matching.
1574 StringRef MnemonicNoS = Mnemonic.slice(0, Mnemonic.size() - 1);
1575 SMLoc NameLoc = ((ARMOperand*)Operands[0])->getStartLoc();
1576 ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]);
1577 Operands.erase(Operands.begin());
1579 Operands.insert(Operands.begin(),
1580 ARMOperand::CreateToken(MnemonicNoS, NameLoc));
1581 Operands.insert(Operands.begin() + 1,
1582 ARMOperand::CreateCCOut(ARM::CPSR, NameLoc));
1583 MatchResult2 = MatchInstructionImpl(Operands, Inst, ErrorInfo);
1584 if (MatchResult2 == Match_Success)
1585 MatchResult = Match_Success;
1587 ARMOperand *OldMnemonic = ((ARMOperand*)Operands[0]);
1588 Operands.erase(Operands.begin());
1590 Operands.insert(Operands.begin(),
1591 ARMOperand::CreateToken(Mnemonic, NameLoc));
1592 ARMOperand *CCOut = ((ARMOperand*)Operands[1]);
1593 Operands.erase(Operands.begin() + 1);
1599 switch (MatchResult) {
1601 Out.EmitInstruction(Inst);
1603 case Match_MissingFeature:
1604 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
1606 case Match_InvalidOperand: {
1607 SMLoc ErrorLoc = IDLoc;
1608 if (ErrorInfo != ~0U) {
1609 if (ErrorInfo >= Operands.size())
1610 return Error(IDLoc, "too few operands for instruction");
1612 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
1613 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1616 return Error(ErrorLoc, "invalid operand for instruction");
1618 case Match_MnemonicFail:
1619 return Error(IDLoc, "unrecognized instruction mnemonic");
1620 case Match_ConversionFail:
1621 return Error(IDLoc, "unable to convert operands to instruction");
1624 llvm_unreachable("Implement any new match types added!");
1628 /// ParseDirective parses the arm specific directives
1629 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
1630 StringRef IDVal = DirectiveID.getIdentifier();
1631 if (IDVal == ".word")
1632 return ParseDirectiveWord(4, DirectiveID.getLoc());
1633 else if (IDVal == ".thumb")
1634 return ParseDirectiveThumb(DirectiveID.getLoc());
1635 else if (IDVal == ".thumb_func")
1636 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
1637 else if (IDVal == ".code")
1638 return ParseDirectiveCode(DirectiveID.getLoc());
1639 else if (IDVal == ".syntax")
1640 return ParseDirectiveSyntax(DirectiveID.getLoc());
1644 /// ParseDirectiveWord
1645 /// ::= .word [ expression (, expression)* ]
1646 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1647 if (getLexer().isNot(AsmToken::EndOfStatement)) {
1649 const MCExpr *Value;
1650 if (getParser().ParseExpression(Value))
1653 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
1655 if (getLexer().is(AsmToken::EndOfStatement))
1658 // FIXME: Improve diagnostic.
1659 if (getLexer().isNot(AsmToken::Comma))
1660 return Error(L, "unexpected token in directive");
1669 /// ParseDirectiveThumb
1671 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
1672 if (getLexer().isNot(AsmToken::EndOfStatement))
1673 return Error(L, "unexpected token in directive");
1676 // TODO: set thumb mode
1677 // TODO: tell the MC streamer the mode
1678 // getParser().getStreamer().Emit???();
1682 /// ParseDirectiveThumbFunc
1683 /// ::= .thumbfunc symbol_name
1684 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
1685 const AsmToken &Tok = Parser.getTok();
1686 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
1687 return Error(L, "unexpected token in .thumb_func directive");
1688 StringRef Name = Tok.getString();
1689 Parser.Lex(); // Consume the identifier token.
1690 if (getLexer().isNot(AsmToken::EndOfStatement))
1691 return Error(L, "unexpected token in directive");
1694 // Mark symbol as a thumb symbol.
1695 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
1696 getParser().getStreamer().EmitThumbFunc(Func);
1700 /// ParseDirectiveSyntax
1701 /// ::= .syntax unified | divided
1702 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
1703 const AsmToken &Tok = Parser.getTok();
1704 if (Tok.isNot(AsmToken::Identifier))
1705 return Error(L, "unexpected token in .syntax directive");
1706 StringRef Mode = Tok.getString();
1707 if (Mode == "unified" || Mode == "UNIFIED")
1709 else if (Mode == "divided" || Mode == "DIVIDED")
1710 return Error(L, "'.syntax divided' arm asssembly not supported");
1712 return Error(L, "unrecognized syntax mode in .syntax directive");
1714 if (getLexer().isNot(AsmToken::EndOfStatement))
1715 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1718 // TODO tell the MC streamer the mode
1719 // getParser().getStreamer().Emit???();
1723 /// ParseDirectiveCode
1724 /// ::= .code 16 | 32
1725 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
1726 const AsmToken &Tok = Parser.getTok();
1727 if (Tok.isNot(AsmToken::Integer))
1728 return Error(L, "unexpected token in .code directive");
1729 int64_t Val = Parser.getTok().getIntVal();
1735 return Error(L, "invalid operand to .code directive");
1737 if (getLexer().isNot(AsmToken::EndOfStatement))
1738 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
1741 // FIXME: We need to be able switch subtargets at this point so that
1742 // MatchInstructionImpl() will work when it gets the AvailableFeatures which
1743 // includes Feature_IsThumb or not to match the right instructions. This is
1744 // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine.
1746 assert(TM.getSubtarget<ARMSubtarget>().isThumb() &&
1747 "switching between arm/thumb not yet suppported via .code 16)");
1748 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
1751 assert(!TM.getSubtarget<ARMSubtarget>().isThumb() &&
1752 "switching between thumb/arm not yet suppported via .code 32)");
1753 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
1759 extern "C" void LLVMInitializeARMAsmLexer();
1761 /// Force static initialization.
1762 extern "C" void LLVMInitializeARMAsmParser() {
1763 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
1764 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
1765 LLVMInitializeARMAsmLexer();
1768 #define GET_REGISTER_MATCHER
1769 #define GET_MATCHER_IMPLEMENTATION
1770 #include "ARMGenAsmMatcher.inc"