1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/MapVector.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCAssembler.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCDisassembler.h"
28 #include "llvm/MC/MCELFStreamer.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCInstrInfo.h"
33 #include "llvm/MC/MCParser/MCAsmLexer.h"
34 #include "llvm/MC/MCParser/MCAsmParser.h"
35 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/MC/MCSection.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/MC/MCSubtargetInfo.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/MC/MCTargetAsmParser.h"
42 #include "llvm/Support/ARMBuildAttributes.h"
43 #include "llvm/Support/ARMEHABI.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/SourceMgr.h"
48 #include "llvm/Support/TargetRegistry.h"
49 #include "llvm/Support/raw_ostream.h"
57 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
62 typedef SmallVector<SMLoc, 4> Locs;
67 Locs PersonalityIndexLocs;
72 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
74 bool hasFnStart() const { return !FnStartLocs.empty(); }
75 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
76 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
77 bool hasPersonality() const {
78 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
81 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
82 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
83 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
84 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
85 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
87 void saveFPReg(int Reg) { FPReg = Reg; }
88 int getFPReg() const { return FPReg; }
90 void emitFnStartLocNotes() const {
91 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
93 Parser.Note(*FI, ".fnstart was specified here");
95 void emitCantUnwindLocNotes() const {
96 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
97 UE = CantUnwindLocs.end(); UI != UE; ++UI)
98 Parser.Note(*UI, ".cantunwind was specified here");
100 void emitHandlerDataLocNotes() const {
101 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
102 HE = HandlerDataLocs.end(); HI != HE; ++HI)
103 Parser.Note(*HI, ".handlerdata was specified here");
105 void emitPersonalityLocNotes() const {
106 for (Locs::const_iterator PI = PersonalityLocs.begin(),
107 PE = PersonalityLocs.end(),
108 PII = PersonalityIndexLocs.begin(),
109 PIE = PersonalityIndexLocs.end();
110 PI != PE || PII != PIE;) {
111 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
112 Parser.Note(*PI++, ".personality was specified here");
113 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
114 Parser.Note(*PII++, ".personalityindex was specified here");
116 llvm_unreachable(".personality and .personalityindex cannot be "
117 "at the same location");
122 FnStartLocs = Locs();
123 CantUnwindLocs = Locs();
124 PersonalityLocs = Locs();
125 HandlerDataLocs = Locs();
126 PersonalityIndexLocs = Locs();
131 class ARMAsmParser : public MCTargetAsmParser {
132 MCSubtargetInfo &STI;
134 const MCInstrInfo &MII;
135 const MCRegisterInfo *MRI;
138 ARMTargetStreamer &getTargetStreamer() {
139 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
140 return static_cast<ARMTargetStreamer &>(TS);
143 // Map of register aliases registers via the .req directive.
144 StringMap<unsigned> RegisterReqs;
146 bool NextSymbolIsThumb;
149 ARMCC::CondCodes Cond; // Condition for IT block.
150 unsigned Mask:4; // Condition mask for instructions.
151 // Starting at first 1 (from lsb).
152 // '1' condition as indicated in IT.
153 // '0' inverse of condition (else).
154 // Count of instructions in IT block is
155 // 4 - trailingzeroes(mask)
157 bool FirstCond; // Explicit flag for when we're parsing the
158 // First instruction in the IT block. It's
159 // implied in the mask, so needs special
162 unsigned CurPosition; // Current position in parsing of IT
163 // block. In range [0,3]. Initialized
164 // according to count of instructions in block.
165 // ~0U if no active IT block.
167 bool inITBlock() { return ITState.CurPosition != ~0U;}
168 void forwardITPosition() {
169 if (!inITBlock()) return;
170 // Move to the next instruction in the IT block, if there is one. If not,
171 // mark the block as done.
172 unsigned TZ = countTrailingZeros(ITState.Mask);
173 if (++ITState.CurPosition == 5 - TZ)
174 ITState.CurPosition = ~0U; // Done with the IT block after this.
178 MCAsmParser &getParser() const { return Parser; }
179 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
181 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
182 return Parser.Note(L, Msg, Ranges);
184 bool Warning(SMLoc L, const Twine &Msg,
185 ArrayRef<SMRange> Ranges = None) {
186 return Parser.Warning(L, Msg, Ranges);
188 bool Error(SMLoc L, const Twine &Msg,
189 ArrayRef<SMRange> Ranges = None) {
190 return Parser.Error(L, Msg, Ranges);
193 int tryParseRegister();
194 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
195 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
199 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
200 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
201 unsigned &ShiftAmount);
202 bool parseLiteralValues(unsigned Size, SMLoc L);
203 bool parseDirectiveThumb(SMLoc L);
204 bool parseDirectiveARM(SMLoc L);
205 bool parseDirectiveThumbFunc(SMLoc L);
206 bool parseDirectiveCode(SMLoc L);
207 bool parseDirectiveSyntax(SMLoc L);
208 bool parseDirectiveReq(StringRef Name, SMLoc L);
209 bool parseDirectiveUnreq(SMLoc L);
210 bool parseDirectiveArch(SMLoc L);
211 bool parseDirectiveEabiAttr(SMLoc L);
212 bool parseDirectiveCPU(SMLoc L);
213 bool parseDirectiveFPU(SMLoc L);
214 bool parseDirectiveFnStart(SMLoc L);
215 bool parseDirectiveFnEnd(SMLoc L);
216 bool parseDirectiveCantUnwind(SMLoc L);
217 bool parseDirectivePersonality(SMLoc L);
218 bool parseDirectiveHandlerData(SMLoc L);
219 bool parseDirectiveSetFP(SMLoc L);
220 bool parseDirectivePad(SMLoc L);
221 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
222 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
223 bool parseDirectiveLtorg(SMLoc L);
224 bool parseDirectiveEven(SMLoc L);
225 bool parseDirectivePersonalityIndex(SMLoc L);
226 bool parseDirectiveUnwindRaw(SMLoc L);
227 bool parseDirectiveTLSDescSeq(SMLoc L);
228 bool parseDirectiveMovSP(SMLoc L);
229 bool parseDirectiveObjectArch(SMLoc L);
230 bool parseDirectiveArchExtension(SMLoc L);
231 bool parseDirectiveAlign(SMLoc L);
233 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
234 bool &CarrySetting, unsigned &ProcessorIMod,
236 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
237 bool &CanAcceptCarrySet,
238 bool &CanAcceptPredicationCode);
240 bool isThumb() const {
241 // FIXME: Can tablegen auto-generate this?
242 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
244 bool isThumbOne() const {
245 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
247 bool isThumbTwo() const {
248 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
250 bool hasThumb() const {
251 return STI.getFeatureBits() & ARM::HasV4TOps;
253 bool hasV6Ops() const {
254 return STI.getFeatureBits() & ARM::HasV6Ops;
256 bool hasV6MOps() const {
257 return STI.getFeatureBits() & ARM::HasV6MOps;
259 bool hasV7Ops() const {
260 return STI.getFeatureBits() & ARM::HasV7Ops;
262 bool hasV8Ops() const {
263 return STI.getFeatureBits() & ARM::HasV8Ops;
265 bool hasARM() const {
266 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
270 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
271 setAvailableFeatures(FB);
273 bool isMClass() const {
274 return STI.getFeatureBits() & ARM::FeatureMClass;
277 /// @name Auto-generated Match Functions
280 #define GET_ASSEMBLER_HEADER
281 #include "ARMGenAsmMatcher.inc"
285 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
286 OperandMatchResultTy parseCoprocNumOperand(
287 SmallVectorImpl<MCParsedAsmOperand*>&);
288 OperandMatchResultTy parseCoprocRegOperand(
289 SmallVectorImpl<MCParsedAsmOperand*>&);
290 OperandMatchResultTy parseCoprocOptionOperand(
291 SmallVectorImpl<MCParsedAsmOperand*>&);
292 OperandMatchResultTy parseMemBarrierOptOperand(
293 SmallVectorImpl<MCParsedAsmOperand*>&);
294 OperandMatchResultTy parseInstSyncBarrierOptOperand(
295 SmallVectorImpl<MCParsedAsmOperand*>&);
296 OperandMatchResultTy parseProcIFlagsOperand(
297 SmallVectorImpl<MCParsedAsmOperand*>&);
298 OperandMatchResultTy parseMSRMaskOperand(
299 SmallVectorImpl<MCParsedAsmOperand*>&);
300 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
301 StringRef Op, int Low, int High);
302 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
303 return parsePKHImm(O, "lsl", 0, 31);
305 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
306 return parsePKHImm(O, "asr", 1, 32);
308 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
309 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
310 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
311 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
312 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
313 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
314 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
315 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
316 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
319 // Asm Match Converter Methods
320 void cvtThumbMultiply(MCInst &Inst,
321 const SmallVectorImpl<MCParsedAsmOperand*> &);
322 void cvtThumbBranches(MCInst &Inst,
323 const SmallVectorImpl<MCParsedAsmOperand*> &);
325 bool validateInstruction(MCInst &Inst,
326 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
327 bool processInstruction(MCInst &Inst,
328 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
329 bool shouldOmitCCOutOperand(StringRef Mnemonic,
330 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
331 bool shouldOmitPredicateOperand(StringRef Mnemonic,
332 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
334 enum ARMMatchResultTy {
335 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
336 Match_RequiresNotITBlock,
338 Match_RequiresThumb2,
339 #define GET_OPERAND_DIAGNOSTIC_TYPES
340 #include "ARMGenAsmMatcher.inc"
344 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
345 const MCInstrInfo &MII)
346 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
347 MCAsmParserExtension::Initialize(_Parser);
349 // Cache the MCRegisterInfo.
350 MRI = getContext().getRegisterInfo();
352 // Initialize the set of available features.
353 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
355 // Not in an ITBlock to start with.
356 ITState.CurPosition = ~0U;
358 NextSymbolIsThumb = false;
361 // Implementation of the MCTargetAsmParser interface:
362 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
364 ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
366 SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
367 bool ParseDirective(AsmToken DirectiveID) override;
369 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
370 unsigned Kind) override;
371 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
373 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
374 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
375 MCStreamer &Out, unsigned &ErrorInfo,
376 bool MatchingInlineAsm) override;
377 void onLabelParsed(MCSymbol *Symbol) override;
379 } // end anonymous namespace
383 /// ARMOperand - Instances of this class represent a parsed ARM machine
385 class ARMOperand : public MCParsedAsmOperand {
395 k_InstSyncBarrierOpt,
406 k_VectorListAllLanes,
412 k_BitfieldDescriptor,
416 SMLoc StartLoc, EndLoc;
417 SmallVector<unsigned, 8> Registers;
420 ARMCC::CondCodes Val;
427 struct CoprocOptionOp {
440 ARM_ISB::InstSyncBOpt Val;
444 ARM_PROC::IFlags Val;
460 // A vector register list is a sequential list of 1 to 4 registers.
461 struct VectorListOp {
468 struct VectorIndexOp {
476 /// Combined record for all forms of ARM address expressions.
479 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
481 const MCConstantExpr *OffsetImm; // Offset immediate value
482 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
483 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
484 unsigned ShiftImm; // shift for OffsetReg.
485 unsigned Alignment; // 0 = no alignment specified
486 // n = alignment in bytes (2, 4, 8, 16, or 32)
487 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
490 struct PostIdxRegOp {
493 ARM_AM::ShiftOpc ShiftTy;
497 struct ShifterImmOp {
502 struct RegShiftedRegOp {
503 ARM_AM::ShiftOpc ShiftTy;
509 struct RegShiftedImmOp {
510 ARM_AM::ShiftOpc ShiftTy;
527 struct CoprocOptionOp CoprocOption;
528 struct MBOptOp MBOpt;
529 struct ISBOptOp ISBOpt;
530 struct ITMaskOp ITMask;
531 struct IFlagsOp IFlags;
532 struct MMaskOp MMask;
535 struct VectorListOp VectorList;
536 struct VectorIndexOp VectorIndex;
538 struct MemoryOp Memory;
539 struct PostIdxRegOp PostIdxReg;
540 struct ShifterImmOp ShifterImm;
541 struct RegShiftedRegOp RegShiftedReg;
542 struct RegShiftedImmOp RegShiftedImm;
543 struct RotImmOp RotImm;
544 struct BitfieldOp Bitfield;
547 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
549 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
551 StartLoc = o.StartLoc;
568 case k_DPRRegisterList:
569 case k_SPRRegisterList:
570 Registers = o.Registers;
573 case k_VectorListAllLanes:
574 case k_VectorListIndexed:
575 VectorList = o.VectorList;
582 CoprocOption = o.CoprocOption;
587 case k_MemBarrierOpt:
590 case k_InstSyncBarrierOpt:
595 case k_PostIndexRegister:
596 PostIdxReg = o.PostIdxReg;
604 case k_ShifterImmediate:
605 ShifterImm = o.ShifterImm;
607 case k_ShiftedRegister:
608 RegShiftedReg = o.RegShiftedReg;
610 case k_ShiftedImmediate:
611 RegShiftedImm = o.RegShiftedImm;
613 case k_RotateImmediate:
616 case k_BitfieldDescriptor:
617 Bitfield = o.Bitfield;
620 VectorIndex = o.VectorIndex;
625 /// getStartLoc - Get the location of the first token of this operand.
626 SMLoc getStartLoc() const override { return StartLoc; }
627 /// getEndLoc - Get the location of the last token of this operand.
628 SMLoc getEndLoc() const override { return EndLoc; }
629 /// getLocRange - Get the range between the first and last token of this
631 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
633 ARMCC::CondCodes getCondCode() const {
634 assert(Kind == k_CondCode && "Invalid access!");
638 unsigned getCoproc() const {
639 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
643 StringRef getToken() const {
644 assert(Kind == k_Token && "Invalid access!");
645 return StringRef(Tok.Data, Tok.Length);
648 unsigned getReg() const override {
649 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
653 const SmallVectorImpl<unsigned> &getRegList() const {
654 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
655 Kind == k_SPRRegisterList) && "Invalid access!");
659 const MCExpr *getImm() const {
660 assert(isImm() && "Invalid access!");
664 unsigned getVectorIndex() const {
665 assert(Kind == k_VectorIndex && "Invalid access!");
666 return VectorIndex.Val;
669 ARM_MB::MemBOpt getMemBarrierOpt() const {
670 assert(Kind == k_MemBarrierOpt && "Invalid access!");
674 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
675 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
679 ARM_PROC::IFlags getProcIFlags() const {
680 assert(Kind == k_ProcIFlags && "Invalid access!");
684 unsigned getMSRMask() const {
685 assert(Kind == k_MSRMask && "Invalid access!");
689 bool isCoprocNum() const { return Kind == k_CoprocNum; }
690 bool isCoprocReg() const { return Kind == k_CoprocReg; }
691 bool isCoprocOption() const { return Kind == k_CoprocOption; }
692 bool isCondCode() const { return Kind == k_CondCode; }
693 bool isCCOut() const { return Kind == k_CCOut; }
694 bool isITMask() const { return Kind == k_ITCondMask; }
695 bool isITCondCode() const { return Kind == k_CondCode; }
696 bool isImm() const override { return Kind == k_Immediate; }
697 // checks whether this operand is an unsigned offset which fits is a field
698 // of specified width and scaled by a specific number of bits
699 template<unsigned width, unsigned scale>
700 bool isUnsignedOffset() const {
701 if (!isImm()) return false;
702 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
703 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
704 int64_t Val = CE->getValue();
705 int64_t Align = 1LL << scale;
706 int64_t Max = Align * ((1LL << width) - 1);
707 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
711 // checks whether this operand is an signed offset which fits is a field
712 // of specified width and scaled by a specific number of bits
713 template<unsigned width, unsigned scale>
714 bool isSignedOffset() const {
715 if (!isImm()) return false;
716 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
717 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
718 int64_t Val = CE->getValue();
719 int64_t Align = 1LL << scale;
720 int64_t Max = Align * ((1LL << (width-1)) - 1);
721 int64_t Min = -Align * (1LL << (width-1));
722 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
727 // checks whether this operand is a memory operand computed as an offset
728 // applied to PC. the offset may have 8 bits of magnitude and is represented
729 // with two bits of shift. textually it may be either [pc, #imm], #imm or
730 // relocable expression...
731 bool isThumbMemPC() const {
734 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
735 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
736 if (!CE) return false;
737 Val = CE->getValue();
740 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
741 if(Memory.BaseRegNum != ARM::PC) return false;
742 Val = Memory.OffsetImm->getValue();
745 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
747 bool isFPImm() const {
748 if (!isImm()) return false;
749 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
750 if (!CE) return false;
751 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
754 bool isFBits16() const {
755 if (!isImm()) return false;
756 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
757 if (!CE) return false;
758 int64_t Value = CE->getValue();
759 return Value >= 0 && Value <= 16;
761 bool isFBits32() const {
762 if (!isImm()) return false;
763 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764 if (!CE) return false;
765 int64_t Value = CE->getValue();
766 return Value >= 1 && Value <= 32;
768 bool isImm8s4() const {
769 if (!isImm()) return false;
770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
771 if (!CE) return false;
772 int64_t Value = CE->getValue();
773 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
775 bool isImm0_1020s4() const {
776 if (!isImm()) return false;
777 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
778 if (!CE) return false;
779 int64_t Value = CE->getValue();
780 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
782 bool isImm0_508s4() const {
783 if (!isImm()) return false;
784 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
785 if (!CE) return false;
786 int64_t Value = CE->getValue();
787 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
789 bool isImm0_508s4Neg() const {
790 if (!isImm()) return false;
791 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
792 if (!CE) return false;
793 int64_t Value = -CE->getValue();
794 // explicitly exclude zero. we want that to use the normal 0_508 version.
795 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
797 bool isImm0_239() const {
798 if (!isImm()) return false;
799 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
800 if (!CE) return false;
801 int64_t Value = CE->getValue();
802 return Value >= 0 && Value < 240;
804 bool isImm0_255() const {
805 if (!isImm()) return false;
806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
807 if (!CE) return false;
808 int64_t Value = CE->getValue();
809 return Value >= 0 && Value < 256;
811 bool isImm0_4095() const {
812 if (!isImm()) return false;
813 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
814 if (!CE) return false;
815 int64_t Value = CE->getValue();
816 return Value >= 0 && Value < 4096;
818 bool isImm0_4095Neg() const {
819 if (!isImm()) return false;
820 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
821 if (!CE) return false;
822 int64_t Value = -CE->getValue();
823 return Value > 0 && Value < 4096;
825 bool isImm0_1() const {
826 if (!isImm()) return false;
827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
828 if (!CE) return false;
829 int64_t Value = CE->getValue();
830 return Value >= 0 && Value < 2;
832 bool isImm0_3() const {
833 if (!isImm()) return false;
834 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
835 if (!CE) return false;
836 int64_t Value = CE->getValue();
837 return Value >= 0 && Value < 4;
839 bool isImm0_7() const {
840 if (!isImm()) return false;
841 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
842 if (!CE) return false;
843 int64_t Value = CE->getValue();
844 return Value >= 0 && Value < 8;
846 bool isImm0_15() const {
847 if (!isImm()) return false;
848 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
849 if (!CE) return false;
850 int64_t Value = CE->getValue();
851 return Value >= 0 && Value < 16;
853 bool isImm0_31() const {
854 if (!isImm()) return false;
855 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
856 if (!CE) return false;
857 int64_t Value = CE->getValue();
858 return Value >= 0 && Value < 32;
860 bool isImm0_63() const {
861 if (!isImm()) return false;
862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
863 if (!CE) return false;
864 int64_t Value = CE->getValue();
865 return Value >= 0 && Value < 64;
867 bool isImm8() const {
868 if (!isImm()) return false;
869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
870 if (!CE) return false;
871 int64_t Value = CE->getValue();
874 bool isImm16() const {
875 if (!isImm()) return false;
876 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
877 if (!CE) return false;
878 int64_t Value = CE->getValue();
881 bool isImm32() const {
882 if (!isImm()) return false;
883 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
884 if (!CE) return false;
885 int64_t Value = CE->getValue();
888 bool isShrImm8() const {
889 if (!isImm()) return false;
890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
891 if (!CE) return false;
892 int64_t Value = CE->getValue();
893 return Value > 0 && Value <= 8;
895 bool isShrImm16() const {
896 if (!isImm()) return false;
897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
898 if (!CE) return false;
899 int64_t Value = CE->getValue();
900 return Value > 0 && Value <= 16;
902 bool isShrImm32() const {
903 if (!isImm()) return false;
904 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
905 if (!CE) return false;
906 int64_t Value = CE->getValue();
907 return Value > 0 && Value <= 32;
909 bool isShrImm64() const {
910 if (!isImm()) return false;
911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
912 if (!CE) return false;
913 int64_t Value = CE->getValue();
914 return Value > 0 && Value <= 64;
916 bool isImm1_7() const {
917 if (!isImm()) return false;
918 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
919 if (!CE) return false;
920 int64_t Value = CE->getValue();
921 return Value > 0 && Value < 8;
923 bool isImm1_15() const {
924 if (!isImm()) return false;
925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
926 if (!CE) return false;
927 int64_t Value = CE->getValue();
928 return Value > 0 && Value < 16;
930 bool isImm1_31() const {
931 if (!isImm()) return false;
932 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933 if (!CE) return false;
934 int64_t Value = CE->getValue();
935 return Value > 0 && Value < 32;
937 bool isImm1_16() const {
938 if (!isImm()) return false;
939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940 if (!CE) return false;
941 int64_t Value = CE->getValue();
942 return Value > 0 && Value < 17;
944 bool isImm1_32() const {
945 if (!isImm()) return false;
946 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
947 if (!CE) return false;
948 int64_t Value = CE->getValue();
949 return Value > 0 && Value < 33;
951 bool isImm0_32() const {
952 if (!isImm()) return false;
953 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
954 if (!CE) return false;
955 int64_t Value = CE->getValue();
956 return Value >= 0 && Value < 33;
958 bool isImm0_65535() const {
959 if (!isImm()) return false;
960 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
961 if (!CE) return false;
962 int64_t Value = CE->getValue();
963 return Value >= 0 && Value < 65536;
965 bool isImm256_65535Expr() const {
966 if (!isImm()) return false;
967 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
968 // If it's not a constant expression, it'll generate a fixup and be
970 if (!CE) return true;
971 int64_t Value = CE->getValue();
972 return Value >= 256 && Value < 65536;
974 bool isImm0_65535Expr() const {
975 if (!isImm()) return false;
976 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
977 // If it's not a constant expression, it'll generate a fixup and be
979 if (!CE) return true;
980 int64_t Value = CE->getValue();
981 return Value >= 0 && Value < 65536;
983 bool isImm24bit() const {
984 if (!isImm()) return false;
985 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
986 if (!CE) return false;
987 int64_t Value = CE->getValue();
988 return Value >= 0 && Value <= 0xffffff;
990 bool isImmThumbSR() const {
991 if (!isImm()) return false;
992 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
993 if (!CE) return false;
994 int64_t Value = CE->getValue();
995 return Value > 0 && Value < 33;
997 bool isPKHLSLImm() const {
998 if (!isImm()) return false;
999 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1000 if (!CE) return false;
1001 int64_t Value = CE->getValue();
1002 return Value >= 0 && Value < 32;
1004 bool isPKHASRImm() const {
1005 if (!isImm()) return false;
1006 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1007 if (!CE) return false;
1008 int64_t Value = CE->getValue();
1009 return Value > 0 && Value <= 32;
1011 bool isAdrLabel() const {
1012 // If we have an immediate that's not a constant, treat it as a label
1013 // reference needing a fixup. If it is a constant, but it can't fit
1014 // into shift immediate encoding, we reject it.
1015 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1016 else return (isARMSOImm() || isARMSOImmNeg());
1018 bool isARMSOImm() const {
1019 if (!isImm()) return false;
1020 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1021 if (!CE) return false;
1022 int64_t Value = CE->getValue();
1023 return ARM_AM::getSOImmVal(Value) != -1;
1025 bool isARMSOImmNot() const {
1026 if (!isImm()) return false;
1027 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1028 if (!CE) return false;
1029 int64_t Value = CE->getValue();
1030 return ARM_AM::getSOImmVal(~Value) != -1;
1032 bool isARMSOImmNeg() const {
1033 if (!isImm()) return false;
1034 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1035 if (!CE) return false;
1036 int64_t Value = CE->getValue();
1037 // Only use this when not representable as a plain so_imm.
1038 return ARM_AM::getSOImmVal(Value) == -1 &&
1039 ARM_AM::getSOImmVal(-Value) != -1;
1041 bool isT2SOImm() const {
1042 if (!isImm()) return false;
1043 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1044 if (!CE) return false;
1045 int64_t Value = CE->getValue();
1046 return ARM_AM::getT2SOImmVal(Value) != -1;
1048 bool isT2SOImmNot() const {
1049 if (!isImm()) return false;
1050 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1051 if (!CE) return false;
1052 int64_t Value = CE->getValue();
1053 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1054 ARM_AM::getT2SOImmVal(~Value) != -1;
1056 bool isT2SOImmNeg() const {
1057 if (!isImm()) return false;
1058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1059 if (!CE) return false;
1060 int64_t Value = CE->getValue();
1061 // Only use this when not representable as a plain so_imm.
1062 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1063 ARM_AM::getT2SOImmVal(-Value) != -1;
1065 bool isSetEndImm() const {
1066 if (!isImm()) return false;
1067 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1068 if (!CE) return false;
1069 int64_t Value = CE->getValue();
1070 return Value == 1 || Value == 0;
1072 bool isReg() const override { return Kind == k_Register; }
1073 bool isRegList() const { return Kind == k_RegisterList; }
1074 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1075 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1076 bool isToken() const override { return Kind == k_Token; }
1077 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1078 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1079 bool isMem() const override { return Kind == k_Memory; }
1080 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1081 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1082 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1083 bool isRotImm() const { return Kind == k_RotateImmediate; }
1084 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1085 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1086 bool isPostIdxReg() const {
1087 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1089 bool isMemNoOffset(bool alignOK = false) const {
1092 // No offset of any kind.
1093 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1094 (alignOK || Memory.Alignment == 0);
1096 bool isMemPCRelImm12() const {
1097 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1099 // Base register must be PC.
1100 if (Memory.BaseRegNum != ARM::PC)
1102 // Immediate offset in range [-4095, 4095].
1103 if (!Memory.OffsetImm) return true;
1104 int64_t Val = Memory.OffsetImm->getValue();
1105 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1107 bool isAlignedMemory() const {
1108 return isMemNoOffset(true);
1110 bool isAddrMode2() const {
1111 if (!isMem() || Memory.Alignment != 0) return false;
1112 // Check for register offset.
1113 if (Memory.OffsetRegNum) return true;
1114 // Immediate offset in range [-4095, 4095].
1115 if (!Memory.OffsetImm) return true;
1116 int64_t Val = Memory.OffsetImm->getValue();
1117 return Val > -4096 && Val < 4096;
1119 bool isAM2OffsetImm() const {
1120 if (!isImm()) return false;
1121 // Immediate offset in range [-4095, 4095].
1122 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1123 if (!CE) return false;
1124 int64_t Val = CE->getValue();
1125 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1127 bool isAddrMode3() const {
1128 // If we have an immediate that's not a constant, treat it as a label
1129 // reference needing a fixup. If it is a constant, it's something else
1130 // and we reject it.
1131 if (isImm() && !isa<MCConstantExpr>(getImm()))
1133 if (!isMem() || Memory.Alignment != 0) return false;
1134 // No shifts are legal for AM3.
1135 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1136 // Check for register offset.
1137 if (Memory.OffsetRegNum) return true;
1138 // Immediate offset in range [-255, 255].
1139 if (!Memory.OffsetImm) return true;
1140 int64_t Val = Memory.OffsetImm->getValue();
1141 // The #-0 offset is encoded as INT32_MIN, and we have to check
1143 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1145 bool isAM3Offset() const {
1146 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1148 if (Kind == k_PostIndexRegister)
1149 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1150 // Immediate offset in range [-255, 255].
1151 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1152 if (!CE) return false;
1153 int64_t Val = CE->getValue();
1154 // Special case, #-0 is INT32_MIN.
1155 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1157 bool isAddrMode5() const {
1158 // If we have an immediate that's not a constant, treat it as a label
1159 // reference needing a fixup. If it is a constant, it's something else
1160 // and we reject it.
1161 if (isImm() && !isa<MCConstantExpr>(getImm()))
1163 if (!isMem() || Memory.Alignment != 0) return false;
1164 // Check for register offset.
1165 if (Memory.OffsetRegNum) return false;
1166 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1167 if (!Memory.OffsetImm) return true;
1168 int64_t Val = Memory.OffsetImm->getValue();
1169 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1172 bool isMemTBB() const {
1173 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1174 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1178 bool isMemTBH() const {
1179 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1180 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1181 Memory.Alignment != 0 )
1185 bool isMemRegOffset() const {
1186 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1190 bool isT2MemRegOffset() const {
1191 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1192 Memory.Alignment != 0)
1194 // Only lsl #{0, 1, 2, 3} allowed.
1195 if (Memory.ShiftType == ARM_AM::no_shift)
1197 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1201 bool isMemThumbRR() const {
1202 // Thumb reg+reg addressing is simple. Just two registers, a base and
1203 // an offset. No shifts, negations or any other complicating factors.
1204 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1205 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1207 return isARMLowRegister(Memory.BaseRegNum) &&
1208 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1210 bool isMemThumbRIs4() const {
1211 if (!isMem() || Memory.OffsetRegNum != 0 ||
1212 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1214 // Immediate offset, multiple of 4 in range [0, 124].
1215 if (!Memory.OffsetImm) return true;
1216 int64_t Val = Memory.OffsetImm->getValue();
1217 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1219 bool isMemThumbRIs2() const {
1220 if (!isMem() || Memory.OffsetRegNum != 0 ||
1221 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1223 // Immediate offset, multiple of 4 in range [0, 62].
1224 if (!Memory.OffsetImm) return true;
1225 int64_t Val = Memory.OffsetImm->getValue();
1226 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1228 bool isMemThumbRIs1() const {
1229 if (!isMem() || Memory.OffsetRegNum != 0 ||
1230 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1232 // Immediate offset in range [0, 31].
1233 if (!Memory.OffsetImm) return true;
1234 int64_t Val = Memory.OffsetImm->getValue();
1235 return Val >= 0 && Val <= 31;
1237 bool isMemThumbSPI() const {
1238 if (!isMem() || Memory.OffsetRegNum != 0 ||
1239 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1241 // Immediate offset, multiple of 4 in range [0, 1020].
1242 if (!Memory.OffsetImm) return true;
1243 int64_t Val = Memory.OffsetImm->getValue();
1244 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1246 bool isMemImm8s4Offset() const {
1247 // If we have an immediate that's not a constant, treat it as a label
1248 // reference needing a fixup. If it is a constant, it's something else
1249 // and we reject it.
1250 if (isImm() && !isa<MCConstantExpr>(getImm()))
1252 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1254 // Immediate offset a multiple of 4 in range [-1020, 1020].
1255 if (!Memory.OffsetImm) return true;
1256 int64_t Val = Memory.OffsetImm->getValue();
1257 // Special case, #-0 is INT32_MIN.
1258 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1260 bool isMemImm0_1020s4Offset() const {
1261 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1263 // Immediate offset a multiple of 4 in range [0, 1020].
1264 if (!Memory.OffsetImm) return true;
1265 int64_t Val = Memory.OffsetImm->getValue();
1266 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1268 bool isMemImm8Offset() const {
1269 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1271 // Base reg of PC isn't allowed for these encodings.
1272 if (Memory.BaseRegNum == ARM::PC) return false;
1273 // Immediate offset in range [-255, 255].
1274 if (!Memory.OffsetImm) return true;
1275 int64_t Val = Memory.OffsetImm->getValue();
1276 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1278 bool isMemPosImm8Offset() const {
1279 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1281 // Immediate offset in range [0, 255].
1282 if (!Memory.OffsetImm) return true;
1283 int64_t Val = Memory.OffsetImm->getValue();
1284 return Val >= 0 && Val < 256;
1286 bool isMemNegImm8Offset() const {
1287 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1289 // Base reg of PC isn't allowed for these encodings.
1290 if (Memory.BaseRegNum == ARM::PC) return false;
1291 // Immediate offset in range [-255, -1].
1292 if (!Memory.OffsetImm) return false;
1293 int64_t Val = Memory.OffsetImm->getValue();
1294 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1296 bool isMemUImm12Offset() const {
1297 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1299 // Immediate offset in range [0, 4095].
1300 if (!Memory.OffsetImm) return true;
1301 int64_t Val = Memory.OffsetImm->getValue();
1302 return (Val >= 0 && Val < 4096);
1304 bool isMemImm12Offset() const {
1305 // If we have an immediate that's not a constant, treat it as a label
1306 // reference needing a fixup. If it is a constant, it's something else
1307 // and we reject it.
1308 if (isImm() && !isa<MCConstantExpr>(getImm()))
1311 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1313 // Immediate offset in range [-4095, 4095].
1314 if (!Memory.OffsetImm) return true;
1315 int64_t Val = Memory.OffsetImm->getValue();
1316 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1318 bool isPostIdxImm8() const {
1319 if (!isImm()) return false;
1320 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1321 if (!CE) return false;
1322 int64_t Val = CE->getValue();
1323 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1325 bool isPostIdxImm8s4() const {
1326 if (!isImm()) return false;
1327 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1328 if (!CE) return false;
1329 int64_t Val = CE->getValue();
1330 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1334 bool isMSRMask() const { return Kind == k_MSRMask; }
1335 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1338 bool isSingleSpacedVectorList() const {
1339 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1341 bool isDoubleSpacedVectorList() const {
1342 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1344 bool isVecListOneD() const {
1345 if (!isSingleSpacedVectorList()) return false;
1346 return VectorList.Count == 1;
1349 bool isVecListDPair() const {
1350 if (!isSingleSpacedVectorList()) return false;
1351 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1352 .contains(VectorList.RegNum));
1355 bool isVecListThreeD() const {
1356 if (!isSingleSpacedVectorList()) return false;
1357 return VectorList.Count == 3;
1360 bool isVecListFourD() const {
1361 if (!isSingleSpacedVectorList()) return false;
1362 return VectorList.Count == 4;
1365 bool isVecListDPairSpaced() const {
1366 if (isSingleSpacedVectorList()) return false;
1367 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1368 .contains(VectorList.RegNum));
1371 bool isVecListThreeQ() const {
1372 if (!isDoubleSpacedVectorList()) return false;
1373 return VectorList.Count == 3;
1376 bool isVecListFourQ() const {
1377 if (!isDoubleSpacedVectorList()) return false;
1378 return VectorList.Count == 4;
1381 bool isSingleSpacedVectorAllLanes() const {
1382 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1384 bool isDoubleSpacedVectorAllLanes() const {
1385 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1387 bool isVecListOneDAllLanes() const {
1388 if (!isSingleSpacedVectorAllLanes()) return false;
1389 return VectorList.Count == 1;
1392 bool isVecListDPairAllLanes() const {
1393 if (!isSingleSpacedVectorAllLanes()) return false;
1394 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1395 .contains(VectorList.RegNum));
1398 bool isVecListDPairSpacedAllLanes() const {
1399 if (!isDoubleSpacedVectorAllLanes()) return false;
1400 return VectorList.Count == 2;
1403 bool isVecListThreeDAllLanes() const {
1404 if (!isSingleSpacedVectorAllLanes()) return false;
1405 return VectorList.Count == 3;
1408 bool isVecListThreeQAllLanes() const {
1409 if (!isDoubleSpacedVectorAllLanes()) return false;
1410 return VectorList.Count == 3;
1413 bool isVecListFourDAllLanes() const {
1414 if (!isSingleSpacedVectorAllLanes()) return false;
1415 return VectorList.Count == 4;
1418 bool isVecListFourQAllLanes() const {
1419 if (!isDoubleSpacedVectorAllLanes()) return false;
1420 return VectorList.Count == 4;
1423 bool isSingleSpacedVectorIndexed() const {
1424 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1426 bool isDoubleSpacedVectorIndexed() const {
1427 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1429 bool isVecListOneDByteIndexed() const {
1430 if (!isSingleSpacedVectorIndexed()) return false;
1431 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1434 bool isVecListOneDHWordIndexed() const {
1435 if (!isSingleSpacedVectorIndexed()) return false;
1436 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1439 bool isVecListOneDWordIndexed() const {
1440 if (!isSingleSpacedVectorIndexed()) return false;
1441 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1444 bool isVecListTwoDByteIndexed() const {
1445 if (!isSingleSpacedVectorIndexed()) return false;
1446 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1449 bool isVecListTwoDHWordIndexed() const {
1450 if (!isSingleSpacedVectorIndexed()) return false;
1451 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1454 bool isVecListTwoQWordIndexed() const {
1455 if (!isDoubleSpacedVectorIndexed()) return false;
1456 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1459 bool isVecListTwoQHWordIndexed() const {
1460 if (!isDoubleSpacedVectorIndexed()) return false;
1461 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1464 bool isVecListTwoDWordIndexed() const {
1465 if (!isSingleSpacedVectorIndexed()) return false;
1466 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1469 bool isVecListThreeDByteIndexed() const {
1470 if (!isSingleSpacedVectorIndexed()) return false;
1471 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1474 bool isVecListThreeDHWordIndexed() const {
1475 if (!isSingleSpacedVectorIndexed()) return false;
1476 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1479 bool isVecListThreeQWordIndexed() const {
1480 if (!isDoubleSpacedVectorIndexed()) return false;
1481 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1484 bool isVecListThreeQHWordIndexed() const {
1485 if (!isDoubleSpacedVectorIndexed()) return false;
1486 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1489 bool isVecListThreeDWordIndexed() const {
1490 if (!isSingleSpacedVectorIndexed()) return false;
1491 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1494 bool isVecListFourDByteIndexed() const {
1495 if (!isSingleSpacedVectorIndexed()) return false;
1496 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1499 bool isVecListFourDHWordIndexed() const {
1500 if (!isSingleSpacedVectorIndexed()) return false;
1501 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1504 bool isVecListFourQWordIndexed() const {
1505 if (!isDoubleSpacedVectorIndexed()) return false;
1506 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1509 bool isVecListFourQHWordIndexed() const {
1510 if (!isDoubleSpacedVectorIndexed()) return false;
1511 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1514 bool isVecListFourDWordIndexed() const {
1515 if (!isSingleSpacedVectorIndexed()) return false;
1516 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1519 bool isVectorIndex8() const {
1520 if (Kind != k_VectorIndex) return false;
1521 return VectorIndex.Val < 8;
1523 bool isVectorIndex16() const {
1524 if (Kind != k_VectorIndex) return false;
1525 return VectorIndex.Val < 4;
1527 bool isVectorIndex32() const {
1528 if (Kind != k_VectorIndex) return false;
1529 return VectorIndex.Val < 2;
1532 bool isNEONi8splat() const {
1533 if (!isImm()) return false;
1534 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1535 // Must be a constant.
1536 if (!CE) return false;
1537 int64_t Value = CE->getValue();
1538 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1540 return Value >= 0 && Value < 256;
1543 bool isNEONi16splat() const {
1544 if (!isImm()) return false;
1545 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1546 // Must be a constant.
1547 if (!CE) return false;
1548 int64_t Value = CE->getValue();
1549 // i16 value in the range [0,255] or [0x0100, 0xff00]
1550 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1553 bool isNEONi32splat() const {
1554 if (!isImm()) return false;
1555 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1556 // Must be a constant.
1557 if (!CE) return false;
1558 int64_t Value = CE->getValue();
1559 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1560 return (Value >= 0 && Value < 256) ||
1561 (Value >= 0x0100 && Value <= 0xff00) ||
1562 (Value >= 0x010000 && Value <= 0xff0000) ||
1563 (Value >= 0x01000000 && Value <= 0xff000000);
1566 bool isNEONi32vmov() const {
1567 if (!isImm()) return false;
1568 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1569 // Must be a constant.
1570 if (!CE) return false;
1571 int64_t Value = CE->getValue();
1572 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1573 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1574 return (Value >= 0 && Value < 256) ||
1575 (Value >= 0x0100 && Value <= 0xff00) ||
1576 (Value >= 0x010000 && Value <= 0xff0000) ||
1577 (Value >= 0x01000000 && Value <= 0xff000000) ||
1578 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1579 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1581 bool isNEONi32vmovNeg() const {
1582 if (!isImm()) return false;
1583 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1584 // Must be a constant.
1585 if (!CE) return false;
1586 int64_t Value = ~CE->getValue();
1587 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1588 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1589 return (Value >= 0 && Value < 256) ||
1590 (Value >= 0x0100 && Value <= 0xff00) ||
1591 (Value >= 0x010000 && Value <= 0xff0000) ||
1592 (Value >= 0x01000000 && Value <= 0xff000000) ||
1593 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1594 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1597 bool isNEONi64splat() const {
1598 if (!isImm()) return false;
1599 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1600 // Must be a constant.
1601 if (!CE) return false;
1602 uint64_t Value = CE->getValue();
1603 // i64 value with each byte being either 0 or 0xff.
1604 for (unsigned i = 0; i < 8; ++i)
1605 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1609 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1610 // Add as immediates when possible. Null MCExpr = 0.
1612 Inst.addOperand(MCOperand::CreateImm(0));
1613 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1614 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1616 Inst.addOperand(MCOperand::CreateExpr(Expr));
1619 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1620 assert(N == 2 && "Invalid number of operands!");
1621 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1622 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1623 Inst.addOperand(MCOperand::CreateReg(RegNum));
1626 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1627 assert(N == 1 && "Invalid number of operands!");
1628 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1631 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1632 assert(N == 1 && "Invalid number of operands!");
1633 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1636 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1637 assert(N == 1 && "Invalid number of operands!");
1638 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1641 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1642 assert(N == 1 && "Invalid number of operands!");
1643 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1646 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1647 assert(N == 1 && "Invalid number of operands!");
1648 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1651 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1652 assert(N == 1 && "Invalid number of operands!");
1653 Inst.addOperand(MCOperand::CreateReg(getReg()));
1656 void addRegOperands(MCInst &Inst, unsigned N) const {
1657 assert(N == 1 && "Invalid number of operands!");
1658 Inst.addOperand(MCOperand::CreateReg(getReg()));
1661 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1662 assert(N == 3 && "Invalid number of operands!");
1663 assert(isRegShiftedReg() &&
1664 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1665 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1666 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1667 Inst.addOperand(MCOperand::CreateImm(
1668 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1671 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1672 assert(N == 2 && "Invalid number of operands!");
1673 assert(isRegShiftedImm() &&
1674 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1675 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1676 // Shift of #32 is encoded as 0 where permitted
1677 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1678 Inst.addOperand(MCOperand::CreateImm(
1679 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1682 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1683 assert(N == 1 && "Invalid number of operands!");
1684 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1688 void addRegListOperands(MCInst &Inst, unsigned N) const {
1689 assert(N == 1 && "Invalid number of operands!");
1690 const SmallVectorImpl<unsigned> &RegList = getRegList();
1691 for (SmallVectorImpl<unsigned>::const_iterator
1692 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1693 Inst.addOperand(MCOperand::CreateReg(*I));
1696 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1697 addRegListOperands(Inst, N);
1700 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1701 addRegListOperands(Inst, N);
1704 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1705 assert(N == 1 && "Invalid number of operands!");
1706 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1707 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1710 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1711 assert(N == 1 && "Invalid number of operands!");
1712 // Munge the lsb/width into a bitfield mask.
1713 unsigned lsb = Bitfield.LSB;
1714 unsigned width = Bitfield.Width;
1715 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1716 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1717 (32 - (lsb + width)));
1718 Inst.addOperand(MCOperand::CreateImm(Mask));
1721 void addImmOperands(MCInst &Inst, unsigned N) const {
1722 assert(N == 1 && "Invalid number of operands!");
1723 addExpr(Inst, getImm());
1726 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1727 assert(N == 1 && "Invalid number of operands!");
1728 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1729 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1732 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1733 assert(N == 1 && "Invalid number of operands!");
1734 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1735 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1738 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1739 assert(N == 1 && "Invalid number of operands!");
1740 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1741 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1742 Inst.addOperand(MCOperand::CreateImm(Val));
1745 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1746 assert(N == 1 && "Invalid number of operands!");
1747 // FIXME: We really want to scale the value here, but the LDRD/STRD
1748 // instruction don't encode operands that way yet.
1749 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1750 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1753 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1754 assert(N == 1 && "Invalid number of operands!");
1755 // The immediate is scaled by four in the encoding and is stored
1756 // in the MCInst as such. Lop off the low two bits here.
1757 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1758 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1761 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1762 assert(N == 1 && "Invalid number of operands!");
1763 // The immediate is scaled by four in the encoding and is stored
1764 // in the MCInst as such. Lop off the low two bits here.
1765 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1766 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1769 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1770 assert(N == 1 && "Invalid number of operands!");
1771 // The immediate is scaled by four in the encoding and is stored
1772 // in the MCInst as such. Lop off the low two bits here.
1773 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1774 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1777 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1778 assert(N == 1 && "Invalid number of operands!");
1779 // The constant encodes as the immediate-1, and we store in the instruction
1780 // the bits as encoded, so subtract off one here.
1781 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1782 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1785 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1786 assert(N == 1 && "Invalid number of operands!");
1787 // The constant encodes as the immediate-1, and we store in the instruction
1788 // the bits as encoded, so subtract off one here.
1789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1790 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1793 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1794 assert(N == 1 && "Invalid number of operands!");
1795 // The constant encodes as the immediate, except for 32, which encodes as
1797 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1798 unsigned Imm = CE->getValue();
1799 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1802 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1803 assert(N == 1 && "Invalid number of operands!");
1804 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1805 // the instruction as well.
1806 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1807 int Val = CE->getValue();
1808 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1811 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1812 assert(N == 1 && "Invalid number of operands!");
1813 // The operand is actually a t2_so_imm, but we have its bitwise
1814 // negation in the assembly source, so twiddle it here.
1815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1816 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1819 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1820 assert(N == 1 && "Invalid number of operands!");
1821 // The operand is actually a t2_so_imm, but we have its
1822 // negation in the assembly source, so twiddle it here.
1823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1824 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1827 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1828 assert(N == 1 && "Invalid number of operands!");
1829 // The operand is actually an imm0_4095, but we have its
1830 // negation in the assembly source, so twiddle it here.
1831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1832 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1835 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1836 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1837 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1841 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1842 assert(SR && "Unknown value type!");
1843 Inst.addOperand(MCOperand::CreateExpr(SR));
1846 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1847 assert(N == 1 && "Invalid number of operands!");
1849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1851 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1855 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1856 assert(SR && "Unknown value type!");
1857 Inst.addOperand(MCOperand::CreateExpr(SR));
1861 assert(isMem() && "Unknown value type!");
1862 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1863 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1866 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1867 assert(N == 1 && "Invalid number of operands!");
1868 // The operand is actually a so_imm, but we have its bitwise
1869 // negation in the assembly source, so twiddle it here.
1870 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1871 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1874 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1875 assert(N == 1 && "Invalid number of operands!");
1876 // The operand is actually a so_imm, but we have its
1877 // negation in the assembly source, so twiddle it here.
1878 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1879 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1882 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1883 assert(N == 1 && "Invalid number of operands!");
1884 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1887 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1888 assert(N == 1 && "Invalid number of operands!");
1889 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1892 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1893 assert(N == 1 && "Invalid number of operands!");
1894 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1897 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1898 assert(N == 1 && "Invalid number of operands!");
1899 int32_t Imm = Memory.OffsetImm->getValue();
1900 Inst.addOperand(MCOperand::CreateImm(Imm));
1903 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1904 assert(N == 1 && "Invalid number of operands!");
1905 assert(isImm() && "Not an immediate!");
1907 // If we have an immediate that's not a constant, treat it as a label
1908 // reference needing a fixup.
1909 if (!isa<MCConstantExpr>(getImm())) {
1910 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1914 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1915 int Val = CE->getValue();
1916 Inst.addOperand(MCOperand::CreateImm(Val));
1919 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1920 assert(N == 2 && "Invalid number of operands!");
1921 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1922 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1925 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1926 assert(N == 3 && "Invalid number of operands!");
1927 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1928 if (!Memory.OffsetRegNum) {
1929 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1930 // Special case for #-0
1931 if (Val == INT32_MIN) Val = 0;
1932 if (Val < 0) Val = -Val;
1933 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1935 // For register offset, we encode the shift type and negation flag
1937 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1938 Memory.ShiftImm, Memory.ShiftType);
1940 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1941 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1942 Inst.addOperand(MCOperand::CreateImm(Val));
1945 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1946 assert(N == 2 && "Invalid number of operands!");
1947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1948 assert(CE && "non-constant AM2OffsetImm operand!");
1949 int32_t Val = CE->getValue();
1950 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1951 // Special case for #-0
1952 if (Val == INT32_MIN) Val = 0;
1953 if (Val < 0) Val = -Val;
1954 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1955 Inst.addOperand(MCOperand::CreateReg(0));
1956 Inst.addOperand(MCOperand::CreateImm(Val));
1959 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1960 assert(N == 3 && "Invalid number of operands!");
1961 // If we have an immediate that's not a constant, treat it as a label
1962 // reference needing a fixup. If it is a constant, it's something else
1963 // and we reject it.
1965 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1966 Inst.addOperand(MCOperand::CreateReg(0));
1967 Inst.addOperand(MCOperand::CreateImm(0));
1971 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1972 if (!Memory.OffsetRegNum) {
1973 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1974 // Special case for #-0
1975 if (Val == INT32_MIN) Val = 0;
1976 if (Val < 0) Val = -Val;
1977 Val = ARM_AM::getAM3Opc(AddSub, Val);
1979 // For register offset, we encode the shift type and negation flag
1981 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1983 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1984 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1985 Inst.addOperand(MCOperand::CreateImm(Val));
1988 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1989 assert(N == 2 && "Invalid number of operands!");
1990 if (Kind == k_PostIndexRegister) {
1992 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1993 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1994 Inst.addOperand(MCOperand::CreateImm(Val));
1999 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2000 int32_t Val = CE->getValue();
2001 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2002 // Special case for #-0
2003 if (Val == INT32_MIN) Val = 0;
2004 if (Val < 0) Val = -Val;
2005 Val = ARM_AM::getAM3Opc(AddSub, Val);
2006 Inst.addOperand(MCOperand::CreateReg(0));
2007 Inst.addOperand(MCOperand::CreateImm(Val));
2010 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2011 assert(N == 2 && "Invalid number of operands!");
2012 // If we have an immediate that's not a constant, treat it as a label
2013 // reference needing a fixup. If it is a constant, it's something else
2014 // and we reject it.
2016 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2017 Inst.addOperand(MCOperand::CreateImm(0));
2021 // The lower two bits are always zero and as such are not encoded.
2022 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2023 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2024 // Special case for #-0
2025 if (Val == INT32_MIN) Val = 0;
2026 if (Val < 0) Val = -Val;
2027 Val = ARM_AM::getAM5Opc(AddSub, Val);
2028 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2029 Inst.addOperand(MCOperand::CreateImm(Val));
2032 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2033 assert(N == 2 && "Invalid number of operands!");
2034 // If we have an immediate that's not a constant, treat it as a label
2035 // reference needing a fixup. If it is a constant, it's something else
2036 // and we reject it.
2038 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2039 Inst.addOperand(MCOperand::CreateImm(0));
2043 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2044 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2045 Inst.addOperand(MCOperand::CreateImm(Val));
2048 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2049 assert(N == 2 && "Invalid number of operands!");
2050 // The lower two bits are always zero and as such are not encoded.
2051 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2052 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2053 Inst.addOperand(MCOperand::CreateImm(Val));
2056 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2057 assert(N == 2 && "Invalid number of operands!");
2058 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2059 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2060 Inst.addOperand(MCOperand::CreateImm(Val));
2063 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2064 addMemImm8OffsetOperands(Inst, N);
2067 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2068 addMemImm8OffsetOperands(Inst, N);
2071 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2072 assert(N == 2 && "Invalid number of operands!");
2073 // If this is an immediate, it's a label reference.
2075 addExpr(Inst, getImm());
2076 Inst.addOperand(MCOperand::CreateImm(0));
2080 // Otherwise, it's a normal memory reg+offset.
2081 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2082 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2083 Inst.addOperand(MCOperand::CreateImm(Val));
2086 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2087 assert(N == 2 && "Invalid number of operands!");
2088 // If this is an immediate, it's a label reference.
2090 addExpr(Inst, getImm());
2091 Inst.addOperand(MCOperand::CreateImm(0));
2095 // Otherwise, it's a normal memory reg+offset.
2096 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2097 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2098 Inst.addOperand(MCOperand::CreateImm(Val));
2101 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2102 assert(N == 2 && "Invalid number of operands!");
2103 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2104 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2107 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2108 assert(N == 2 && "Invalid number of operands!");
2109 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2110 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2113 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2114 assert(N == 3 && "Invalid number of operands!");
2116 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2117 Memory.ShiftImm, Memory.ShiftType);
2118 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2119 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2120 Inst.addOperand(MCOperand::CreateImm(Val));
2123 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2124 assert(N == 3 && "Invalid number of operands!");
2125 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2126 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2127 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2130 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2131 assert(N == 2 && "Invalid number of operands!");
2132 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2133 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2136 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2137 assert(N == 2 && "Invalid number of operands!");
2138 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2139 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2140 Inst.addOperand(MCOperand::CreateImm(Val));
2143 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2144 assert(N == 2 && "Invalid number of operands!");
2145 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2146 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2147 Inst.addOperand(MCOperand::CreateImm(Val));
2150 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2151 assert(N == 2 && "Invalid number of operands!");
2152 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2153 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2154 Inst.addOperand(MCOperand::CreateImm(Val));
2157 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2158 assert(N == 2 && "Invalid number of operands!");
2159 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2160 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2161 Inst.addOperand(MCOperand::CreateImm(Val));
2164 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2165 assert(N == 1 && "Invalid number of operands!");
2166 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2167 assert(CE && "non-constant post-idx-imm8 operand!");
2168 int Imm = CE->getValue();
2169 bool isAdd = Imm >= 0;
2170 if (Imm == INT32_MIN) Imm = 0;
2171 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2172 Inst.addOperand(MCOperand::CreateImm(Imm));
2175 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2176 assert(N == 1 && "Invalid number of operands!");
2177 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2178 assert(CE && "non-constant post-idx-imm8s4 operand!");
2179 int Imm = CE->getValue();
2180 bool isAdd = Imm >= 0;
2181 if (Imm == INT32_MIN) Imm = 0;
2182 // Immediate is scaled by 4.
2183 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2184 Inst.addOperand(MCOperand::CreateImm(Imm));
2187 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2188 assert(N == 2 && "Invalid number of operands!");
2189 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2190 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2193 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2194 assert(N == 2 && "Invalid number of operands!");
2195 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2196 // The sign, shift type, and shift amount are encoded in a single operand
2197 // using the AM2 encoding helpers.
2198 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2199 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2200 PostIdxReg.ShiftTy);
2201 Inst.addOperand(MCOperand::CreateImm(Imm));
2204 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2205 assert(N == 1 && "Invalid number of operands!");
2206 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2209 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2210 assert(N == 1 && "Invalid number of operands!");
2211 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2214 void addVecListOperands(MCInst &Inst, unsigned N) const {
2215 assert(N == 1 && "Invalid number of operands!");
2216 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2219 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2220 assert(N == 2 && "Invalid number of operands!");
2221 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2222 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2225 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2226 assert(N == 1 && "Invalid number of operands!");
2227 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2230 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2231 assert(N == 1 && "Invalid number of operands!");
2232 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2235 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2236 assert(N == 1 && "Invalid number of operands!");
2237 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2240 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2241 assert(N == 1 && "Invalid number of operands!");
2242 // The immediate encodes the type of constant as well as the value.
2243 // Mask in that this is an i8 splat.
2244 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2245 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2248 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2249 assert(N == 1 && "Invalid number of operands!");
2250 // The immediate encodes the type of constant as well as the value.
2251 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2252 unsigned Value = CE->getValue();
2254 Value = (Value >> 8) | 0xa00;
2257 Inst.addOperand(MCOperand::CreateImm(Value));
2260 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2261 assert(N == 1 && "Invalid number of operands!");
2262 // The immediate encodes the type of constant as well as the value.
2263 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2264 unsigned Value = CE->getValue();
2265 if (Value >= 256 && Value <= 0xff00)
2266 Value = (Value >> 8) | 0x200;
2267 else if (Value > 0xffff && Value <= 0xff0000)
2268 Value = (Value >> 16) | 0x400;
2269 else if (Value > 0xffffff)
2270 Value = (Value >> 24) | 0x600;
2271 Inst.addOperand(MCOperand::CreateImm(Value));
2274 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2275 assert(N == 1 && "Invalid number of operands!");
2276 // The immediate encodes the type of constant as well as the value.
2277 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2278 unsigned Value = CE->getValue();
2279 if (Value >= 256 && Value <= 0xffff)
2280 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2281 else if (Value > 0xffff && Value <= 0xffffff)
2282 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2283 else if (Value > 0xffffff)
2284 Value = (Value >> 24) | 0x600;
2285 Inst.addOperand(MCOperand::CreateImm(Value));
2288 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2289 assert(N == 1 && "Invalid number of operands!");
2290 // The immediate encodes the type of constant as well as the value.
2291 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2292 unsigned Value = ~CE->getValue();
2293 if (Value >= 256 && Value <= 0xffff)
2294 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2295 else if (Value > 0xffff && Value <= 0xffffff)
2296 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2297 else if (Value > 0xffffff)
2298 Value = (Value >> 24) | 0x600;
2299 Inst.addOperand(MCOperand::CreateImm(Value));
2302 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2303 assert(N == 1 && "Invalid number of operands!");
2304 // The immediate encodes the type of constant as well as the value.
2305 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2306 uint64_t Value = CE->getValue();
2308 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2309 Imm |= (Value & 1) << i;
2311 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2314 void print(raw_ostream &OS) const override;
2316 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2317 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2318 Op->ITMask.Mask = Mask;
2324 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2325 ARMOperand *Op = new ARMOperand(k_CondCode);
2332 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2333 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2334 Op->Cop.Val = CopVal;
2340 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2341 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2342 Op->Cop.Val = CopVal;
2348 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2349 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2356 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2357 ARMOperand *Op = new ARMOperand(k_CCOut);
2358 Op->Reg.RegNum = RegNum;
2364 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2365 ARMOperand *Op = new ARMOperand(k_Token);
2366 Op->Tok.Data = Str.data();
2367 Op->Tok.Length = Str.size();
2373 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2374 ARMOperand *Op = new ARMOperand(k_Register);
2375 Op->Reg.RegNum = RegNum;
2381 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2386 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2387 Op->RegShiftedReg.ShiftTy = ShTy;
2388 Op->RegShiftedReg.SrcReg = SrcReg;
2389 Op->RegShiftedReg.ShiftReg = ShiftReg;
2390 Op->RegShiftedReg.ShiftImm = ShiftImm;
2396 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2400 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2401 Op->RegShiftedImm.ShiftTy = ShTy;
2402 Op->RegShiftedImm.SrcReg = SrcReg;
2403 Op->RegShiftedImm.ShiftImm = ShiftImm;
2409 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2411 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2412 Op->ShifterImm.isASR = isASR;
2413 Op->ShifterImm.Imm = Imm;
2419 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2420 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2421 Op->RotImm.Imm = Imm;
2427 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2429 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2430 Op->Bitfield.LSB = LSB;
2431 Op->Bitfield.Width = Width;
2438 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2439 SMLoc StartLoc, SMLoc EndLoc) {
2440 assert (Regs.size() > 0 && "RegList contains no registers?");
2441 KindTy Kind = k_RegisterList;
2443 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2444 Kind = k_DPRRegisterList;
2445 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2446 contains(Regs.front().second))
2447 Kind = k_SPRRegisterList;
2449 // Sort based on the register encoding values.
2450 array_pod_sort(Regs.begin(), Regs.end());
2452 ARMOperand *Op = new ARMOperand(Kind);
2453 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2454 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2455 Op->Registers.push_back(I->second);
2456 Op->StartLoc = StartLoc;
2457 Op->EndLoc = EndLoc;
2461 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2462 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2463 ARMOperand *Op = new ARMOperand(k_VectorList);
2464 Op->VectorList.RegNum = RegNum;
2465 Op->VectorList.Count = Count;
2466 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2472 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2473 bool isDoubleSpaced,
2475 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2476 Op->VectorList.RegNum = RegNum;
2477 Op->VectorList.Count = Count;
2478 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2484 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2486 bool isDoubleSpaced,
2488 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2489 Op->VectorList.RegNum = RegNum;
2490 Op->VectorList.Count = Count;
2491 Op->VectorList.LaneIndex = Index;
2492 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2498 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2500 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2501 Op->VectorIndex.Val = Idx;
2507 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2508 ARMOperand *Op = new ARMOperand(k_Immediate);
2515 static ARMOperand *CreateMem(unsigned BaseRegNum,
2516 const MCConstantExpr *OffsetImm,
2517 unsigned OffsetRegNum,
2518 ARM_AM::ShiftOpc ShiftType,
2523 ARMOperand *Op = new ARMOperand(k_Memory);
2524 Op->Memory.BaseRegNum = BaseRegNum;
2525 Op->Memory.OffsetImm = OffsetImm;
2526 Op->Memory.OffsetRegNum = OffsetRegNum;
2527 Op->Memory.ShiftType = ShiftType;
2528 Op->Memory.ShiftImm = ShiftImm;
2529 Op->Memory.Alignment = Alignment;
2530 Op->Memory.isNegative = isNegative;
2536 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2537 ARM_AM::ShiftOpc ShiftTy,
2540 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2541 Op->PostIdxReg.RegNum = RegNum;
2542 Op->PostIdxReg.isAdd = isAdd;
2543 Op->PostIdxReg.ShiftTy = ShiftTy;
2544 Op->PostIdxReg.ShiftImm = ShiftImm;
2550 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2551 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2552 Op->MBOpt.Val = Opt;
2558 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2560 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2561 Op->ISBOpt.Val = Opt;
2567 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2568 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2569 Op->IFlags.Val = IFlags;
2575 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2576 ARMOperand *Op = new ARMOperand(k_MSRMask);
2577 Op->MMask.Val = MMask;
2584 } // end anonymous namespace.
2586 void ARMOperand::print(raw_ostream &OS) const {
2589 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2592 OS << "<ccout " << getReg() << ">";
2594 case k_ITCondMask: {
2595 static const char *const MaskStr[] = {
2596 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2597 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2599 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2600 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2604 OS << "<coprocessor number: " << getCoproc() << ">";
2607 OS << "<coprocessor register: " << getCoproc() << ">";
2609 case k_CoprocOption:
2610 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2613 OS << "<mask: " << getMSRMask() << ">";
2616 getImm()->print(OS);
2618 case k_MemBarrierOpt:
2619 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2621 case k_InstSyncBarrierOpt:
2622 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2626 << " base:" << Memory.BaseRegNum;
2629 case k_PostIndexRegister:
2630 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2631 << PostIdxReg.RegNum;
2632 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2633 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2634 << PostIdxReg.ShiftImm;
2637 case k_ProcIFlags: {
2638 OS << "<ARM_PROC::";
2639 unsigned IFlags = getProcIFlags();
2640 for (int i=2; i >= 0; --i)
2641 if (IFlags & (1 << i))
2642 OS << ARM_PROC::IFlagsToString(1 << i);
2647 OS << "<register " << getReg() << ">";
2649 case k_ShifterImmediate:
2650 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2651 << " #" << ShifterImm.Imm << ">";
2653 case k_ShiftedRegister:
2654 OS << "<so_reg_reg "
2655 << RegShiftedReg.SrcReg << " "
2656 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2657 << " " << RegShiftedReg.ShiftReg << ">";
2659 case k_ShiftedImmediate:
2660 OS << "<so_reg_imm "
2661 << RegShiftedImm.SrcReg << " "
2662 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2663 << " #" << RegShiftedImm.ShiftImm << ">";
2665 case k_RotateImmediate:
2666 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2668 case k_BitfieldDescriptor:
2669 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2670 << ", width: " << Bitfield.Width << ">";
2672 case k_RegisterList:
2673 case k_DPRRegisterList:
2674 case k_SPRRegisterList: {
2675 OS << "<register_list ";
2677 const SmallVectorImpl<unsigned> &RegList = getRegList();
2678 for (SmallVectorImpl<unsigned>::const_iterator
2679 I = RegList.begin(), E = RegList.end(); I != E; ) {
2681 if (++I < E) OS << ", ";
2688 OS << "<vector_list " << VectorList.Count << " * "
2689 << VectorList.RegNum << ">";
2691 case k_VectorListAllLanes:
2692 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2693 << VectorList.RegNum << ">";
2695 case k_VectorListIndexed:
2696 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2697 << VectorList.Count << " * " << VectorList.RegNum << ">";
2700 OS << "'" << getToken() << "'";
2703 OS << "<vectorindex " << getVectorIndex() << ">";
2708 /// @name Auto-generated Match Functions
2711 static unsigned MatchRegisterName(StringRef Name);
2715 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2716 SMLoc &StartLoc, SMLoc &EndLoc) {
2717 StartLoc = Parser.getTok().getLoc();
2718 EndLoc = Parser.getTok().getEndLoc();
2719 RegNo = tryParseRegister();
2721 return (RegNo == (unsigned)-1);
2724 /// Try to parse a register name. The token must be an Identifier when called,
2725 /// and if it is a register name the token is eaten and the register number is
2726 /// returned. Otherwise return -1.
2728 int ARMAsmParser::tryParseRegister() {
2729 const AsmToken &Tok = Parser.getTok();
2730 if (Tok.isNot(AsmToken::Identifier)) return -1;
2732 std::string lowerCase = Tok.getString().lower();
2733 unsigned RegNum = MatchRegisterName(lowerCase);
2735 RegNum = StringSwitch<unsigned>(lowerCase)
2736 .Case("r13", ARM::SP)
2737 .Case("r14", ARM::LR)
2738 .Case("r15", ARM::PC)
2739 .Case("ip", ARM::R12)
2740 // Additional register name aliases for 'gas' compatibility.
2741 .Case("a1", ARM::R0)
2742 .Case("a2", ARM::R1)
2743 .Case("a3", ARM::R2)
2744 .Case("a4", ARM::R3)
2745 .Case("v1", ARM::R4)
2746 .Case("v2", ARM::R5)
2747 .Case("v3", ARM::R6)
2748 .Case("v4", ARM::R7)
2749 .Case("v5", ARM::R8)
2750 .Case("v6", ARM::R9)
2751 .Case("v7", ARM::R10)
2752 .Case("v8", ARM::R11)
2753 .Case("sb", ARM::R9)
2754 .Case("sl", ARM::R10)
2755 .Case("fp", ARM::R11)
2759 // Check for aliases registered via .req. Canonicalize to lower case.
2760 // That's more consistent since register names are case insensitive, and
2761 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2762 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2763 // If no match, return failure.
2764 if (Entry == RegisterReqs.end())
2766 Parser.Lex(); // Eat identifier token.
2767 return Entry->getValue();
2770 Parser.Lex(); // Eat identifier token.
2775 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2776 // If a recoverable error occurs, return 1. If an irrecoverable error
2777 // occurs, return -1. An irrecoverable error is one where tokens have been
2778 // consumed in the process of trying to parse the shifter (i.e., when it is
2779 // indeed a shifter operand, but malformed).
2780 int ARMAsmParser::tryParseShiftRegister(
2781 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2782 SMLoc S = Parser.getTok().getLoc();
2783 const AsmToken &Tok = Parser.getTok();
2784 if (Tok.isNot(AsmToken::Identifier))
2787 std::string lowerCase = Tok.getString().lower();
2788 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2789 .Case("asl", ARM_AM::lsl)
2790 .Case("lsl", ARM_AM::lsl)
2791 .Case("lsr", ARM_AM::lsr)
2792 .Case("asr", ARM_AM::asr)
2793 .Case("ror", ARM_AM::ror)
2794 .Case("rrx", ARM_AM::rrx)
2795 .Default(ARM_AM::no_shift);
2797 if (ShiftTy == ARM_AM::no_shift)
2800 Parser.Lex(); // Eat the operator.
2802 // The source register for the shift has already been added to the
2803 // operand list, so we need to pop it off and combine it into the shifted
2804 // register operand instead.
2805 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2806 if (!PrevOp->isReg())
2807 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2808 int SrcReg = PrevOp->getReg();
2813 if (ShiftTy == ARM_AM::rrx) {
2814 // RRX Doesn't have an explicit shift amount. The encoder expects
2815 // the shift register to be the same as the source register. Seems odd,
2819 // Figure out if this is shifted by a constant or a register (for non-RRX).
2820 if (Parser.getTok().is(AsmToken::Hash) ||
2821 Parser.getTok().is(AsmToken::Dollar)) {
2822 Parser.Lex(); // Eat hash.
2823 SMLoc ImmLoc = Parser.getTok().getLoc();
2824 const MCExpr *ShiftExpr = 0;
2825 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2826 Error(ImmLoc, "invalid immediate shift value");
2829 // The expression must be evaluatable as an immediate.
2830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2832 Error(ImmLoc, "invalid immediate shift value");
2835 // Range check the immediate.
2836 // lsl, ror: 0 <= imm <= 31
2837 // lsr, asr: 0 <= imm <= 32
2838 Imm = CE->getValue();
2840 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2841 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2842 Error(ImmLoc, "immediate shift value out of range");
2845 // shift by zero is a nop. Always send it through as lsl.
2846 // ('as' compatibility)
2848 ShiftTy = ARM_AM::lsl;
2849 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2850 SMLoc L = Parser.getTok().getLoc();
2851 EndLoc = Parser.getTok().getEndLoc();
2852 ShiftReg = tryParseRegister();
2853 if (ShiftReg == -1) {
2854 Error (L, "expected immediate or register in shift operand");
2858 Error (Parser.getTok().getLoc(),
2859 "expected immediate or register in shift operand");
2864 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2865 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2869 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2876 /// Try to parse a register name. The token must be an Identifier when called.
2877 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2878 /// if there is a "writeback". 'true' if it's not a register.
2880 /// TODO this is likely to change to allow different register types and or to
2881 /// parse for a specific register type.
2883 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2884 const AsmToken &RegTok = Parser.getTok();
2885 int RegNo = tryParseRegister();
2889 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2890 RegTok.getEndLoc()));
2892 const AsmToken &ExclaimTok = Parser.getTok();
2893 if (ExclaimTok.is(AsmToken::Exclaim)) {
2894 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2895 ExclaimTok.getLoc()));
2896 Parser.Lex(); // Eat exclaim token
2900 // Also check for an index operand. This is only legal for vector registers,
2901 // but that'll get caught OK in operand matching, so we don't need to
2902 // explicitly filter everything else out here.
2903 if (Parser.getTok().is(AsmToken::LBrac)) {
2904 SMLoc SIdx = Parser.getTok().getLoc();
2905 Parser.Lex(); // Eat left bracket token.
2907 const MCExpr *ImmVal;
2908 if (getParser().parseExpression(ImmVal))
2910 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2912 return TokError("immediate value expected for vector index");
2914 if (Parser.getTok().isNot(AsmToken::RBrac))
2915 return Error(Parser.getTok().getLoc(), "']' expected");
2917 SMLoc E = Parser.getTok().getEndLoc();
2918 Parser.Lex(); // Eat right bracket token.
2920 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2928 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2929 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2931 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2932 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2934 switch (Name.size()) {
2937 if (Name[0] != CoprocOp)
2953 if (Name[0] != CoprocOp || Name[1] != '1')
2957 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
2958 case '0': return CoprocOp == 'p'? -1: 10;
2959 case '1': return CoprocOp == 'p'? -1: 11;
2960 case '2': return 12;
2961 case '3': return 13;
2962 case '4': return 14;
2963 case '5': return 15;
2968 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2969 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2970 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2971 SMLoc S = Parser.getTok().getLoc();
2972 const AsmToken &Tok = Parser.getTok();
2973 if (!Tok.is(AsmToken::Identifier))
2974 return MatchOperand_NoMatch;
2975 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2976 .Case("eq", ARMCC::EQ)
2977 .Case("ne", ARMCC::NE)
2978 .Case("hs", ARMCC::HS)
2979 .Case("cs", ARMCC::HS)
2980 .Case("lo", ARMCC::LO)
2981 .Case("cc", ARMCC::LO)
2982 .Case("mi", ARMCC::MI)
2983 .Case("pl", ARMCC::PL)
2984 .Case("vs", ARMCC::VS)
2985 .Case("vc", ARMCC::VC)
2986 .Case("hi", ARMCC::HI)
2987 .Case("ls", ARMCC::LS)
2988 .Case("ge", ARMCC::GE)
2989 .Case("lt", ARMCC::LT)
2990 .Case("gt", ARMCC::GT)
2991 .Case("le", ARMCC::LE)
2992 .Case("al", ARMCC::AL)
2995 return MatchOperand_NoMatch;
2996 Parser.Lex(); // Eat the token.
2998 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3000 return MatchOperand_Success;
3003 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3004 /// token must be an Identifier when called, and if it is a coprocessor
3005 /// number, the token is eaten and the operand is added to the operand list.
3006 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3007 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3008 SMLoc S = Parser.getTok().getLoc();
3009 const AsmToken &Tok = Parser.getTok();
3010 if (Tok.isNot(AsmToken::Identifier))
3011 return MatchOperand_NoMatch;
3013 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3015 return MatchOperand_NoMatch;
3017 Parser.Lex(); // Eat identifier token.
3018 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3019 return MatchOperand_Success;
3022 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3023 /// token must be an Identifier when called, and if it is a coprocessor
3024 /// number, the token is eaten and the operand is added to the operand list.
3025 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3026 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3027 SMLoc S = Parser.getTok().getLoc();
3028 const AsmToken &Tok = Parser.getTok();
3029 if (Tok.isNot(AsmToken::Identifier))
3030 return MatchOperand_NoMatch;
3032 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3034 return MatchOperand_NoMatch;
3036 Parser.Lex(); // Eat identifier token.
3037 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3038 return MatchOperand_Success;
3041 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3042 /// coproc_option : '{' imm0_255 '}'
3043 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3044 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3045 SMLoc S = Parser.getTok().getLoc();
3047 // If this isn't a '{', this isn't a coprocessor immediate operand.
3048 if (Parser.getTok().isNot(AsmToken::LCurly))
3049 return MatchOperand_NoMatch;
3050 Parser.Lex(); // Eat the '{'
3053 SMLoc Loc = Parser.getTok().getLoc();
3054 if (getParser().parseExpression(Expr)) {
3055 Error(Loc, "illegal expression");
3056 return MatchOperand_ParseFail;
3058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3059 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3060 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3061 return MatchOperand_ParseFail;
3063 int Val = CE->getValue();
3065 // Check for and consume the closing '}'
3066 if (Parser.getTok().isNot(AsmToken::RCurly))
3067 return MatchOperand_ParseFail;
3068 SMLoc E = Parser.getTok().getEndLoc();
3069 Parser.Lex(); // Eat the '}'
3071 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3072 return MatchOperand_Success;
3075 // For register list parsing, we need to map from raw GPR register numbering
3076 // to the enumeration values. The enumeration values aren't sorted by
3077 // register number due to our using "sp", "lr" and "pc" as canonical names.
3078 static unsigned getNextRegister(unsigned Reg) {
3079 // If this is a GPR, we need to do it manually, otherwise we can rely
3080 // on the sort ordering of the enumeration since the other reg-classes
3082 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3085 default: llvm_unreachable("Invalid GPR number!");
3086 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3087 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3088 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3089 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3090 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3091 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3092 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3093 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3097 // Return the low-subreg of a given Q register.
3098 static unsigned getDRegFromQReg(unsigned QReg) {
3100 default: llvm_unreachable("expected a Q register!");
3101 case ARM::Q0: return ARM::D0;
3102 case ARM::Q1: return ARM::D2;
3103 case ARM::Q2: return ARM::D4;
3104 case ARM::Q3: return ARM::D6;
3105 case ARM::Q4: return ARM::D8;
3106 case ARM::Q5: return ARM::D10;
3107 case ARM::Q6: return ARM::D12;
3108 case ARM::Q7: return ARM::D14;
3109 case ARM::Q8: return ARM::D16;
3110 case ARM::Q9: return ARM::D18;
3111 case ARM::Q10: return ARM::D20;
3112 case ARM::Q11: return ARM::D22;
3113 case ARM::Q12: return ARM::D24;
3114 case ARM::Q13: return ARM::D26;
3115 case ARM::Q14: return ARM::D28;
3116 case ARM::Q15: return ARM::D30;
3120 /// Parse a register list.
3122 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3123 assert(Parser.getTok().is(AsmToken::LCurly) &&
3124 "Token is not a Left Curly Brace");
3125 SMLoc S = Parser.getTok().getLoc();
3126 Parser.Lex(); // Eat '{' token.
3127 SMLoc RegLoc = Parser.getTok().getLoc();
3129 // Check the first register in the list to see what register class
3130 // this is a list of.
3131 int Reg = tryParseRegister();
3133 return Error(RegLoc, "register expected");
3135 // The reglist instructions have at most 16 registers, so reserve
3136 // space for that many.
3138 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3140 // Allow Q regs and just interpret them as the two D sub-registers.
3141 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3142 Reg = getDRegFromQReg(Reg);
3143 EReg = MRI->getEncodingValue(Reg);
3144 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3147 const MCRegisterClass *RC;
3148 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3149 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3150 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3151 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3152 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3153 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3155 return Error(RegLoc, "invalid register in register list");
3157 // Store the register.
3158 EReg = MRI->getEncodingValue(Reg);
3159 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3161 // This starts immediately after the first register token in the list,
3162 // so we can see either a comma or a minus (range separator) as a legal
3164 while (Parser.getTok().is(AsmToken::Comma) ||
3165 Parser.getTok().is(AsmToken::Minus)) {
3166 if (Parser.getTok().is(AsmToken::Minus)) {
3167 Parser.Lex(); // Eat the minus.
3168 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3169 int EndReg = tryParseRegister();
3171 return Error(AfterMinusLoc, "register expected");
3172 // Allow Q regs and just interpret them as the two D sub-registers.
3173 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3174 EndReg = getDRegFromQReg(EndReg) + 1;
3175 // If the register is the same as the start reg, there's nothing
3179 // The register must be in the same register class as the first.
3180 if (!RC->contains(EndReg))
3181 return Error(AfterMinusLoc, "invalid register in register list");
3182 // Ranges must go from low to high.
3183 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3184 return Error(AfterMinusLoc, "bad range in register list");
3186 // Add all the registers in the range to the register list.
3187 while (Reg != EndReg) {
3188 Reg = getNextRegister(Reg);
3189 EReg = MRI->getEncodingValue(Reg);
3190 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3194 Parser.Lex(); // Eat the comma.
3195 RegLoc = Parser.getTok().getLoc();
3197 const AsmToken RegTok = Parser.getTok();
3198 Reg = tryParseRegister();
3200 return Error(RegLoc, "register expected");
3201 // Allow Q regs and just interpret them as the two D sub-registers.
3202 bool isQReg = false;
3203 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3204 Reg = getDRegFromQReg(Reg);
3207 // The register must be in the same register class as the first.
3208 if (!RC->contains(Reg))
3209 return Error(RegLoc, "invalid register in register list");
3210 // List must be monotonically increasing.
3211 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3212 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3213 Warning(RegLoc, "register list not in ascending order");
3215 return Error(RegLoc, "register list not in ascending order");
3217 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3218 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3219 ") in register list");
3222 // VFP register lists must also be contiguous.
3223 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3225 return Error(RegLoc, "non-contiguous register range");
3226 EReg = MRI->getEncodingValue(Reg);
3227 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3229 EReg = MRI->getEncodingValue(++Reg);
3230 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3234 if (Parser.getTok().isNot(AsmToken::RCurly))
3235 return Error(Parser.getTok().getLoc(), "'}' expected");
3236 SMLoc E = Parser.getTok().getEndLoc();
3237 Parser.Lex(); // Eat '}' token.
3239 // Push the register list operand.
3240 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3242 // The ARM system instruction variants for LDM/STM have a '^' token here.
3243 if (Parser.getTok().is(AsmToken::Caret)) {
3244 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3245 Parser.Lex(); // Eat '^' token.
3251 // Helper function to parse the lane index for vector lists.
3252 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3253 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3254 Index = 0; // Always return a defined index value.
3255 if (Parser.getTok().is(AsmToken::LBrac)) {
3256 Parser.Lex(); // Eat the '['.
3257 if (Parser.getTok().is(AsmToken::RBrac)) {
3258 // "Dn[]" is the 'all lanes' syntax.
3259 LaneKind = AllLanes;
3260 EndLoc = Parser.getTok().getEndLoc();
3261 Parser.Lex(); // Eat the ']'.
3262 return MatchOperand_Success;
3265 // There's an optional '#' token here. Normally there wouldn't be, but
3266 // inline assemble puts one in, and it's friendly to accept that.
3267 if (Parser.getTok().is(AsmToken::Hash))
3268 Parser.Lex(); // Eat '#' or '$'.
3270 const MCExpr *LaneIndex;
3271 SMLoc Loc = Parser.getTok().getLoc();
3272 if (getParser().parseExpression(LaneIndex)) {
3273 Error(Loc, "illegal expression");
3274 return MatchOperand_ParseFail;
3276 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3278 Error(Loc, "lane index must be empty or an integer");
3279 return MatchOperand_ParseFail;
3281 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3282 Error(Parser.getTok().getLoc(), "']' expected");
3283 return MatchOperand_ParseFail;
3285 EndLoc = Parser.getTok().getEndLoc();
3286 Parser.Lex(); // Eat the ']'.
3287 int64_t Val = CE->getValue();
3289 // FIXME: Make this range check context sensitive for .8, .16, .32.
3290 if (Val < 0 || Val > 7) {
3291 Error(Parser.getTok().getLoc(), "lane index out of range");
3292 return MatchOperand_ParseFail;
3295 LaneKind = IndexedLane;
3296 return MatchOperand_Success;
3299 return MatchOperand_Success;
3302 // parse a vector register list
3303 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3304 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3305 VectorLaneTy LaneKind;
3307 SMLoc S = Parser.getTok().getLoc();
3308 // As an extension (to match gas), support a plain D register or Q register
3309 // (without encosing curly braces) as a single or double entry list,
3311 if (Parser.getTok().is(AsmToken::Identifier)) {
3312 SMLoc E = Parser.getTok().getEndLoc();
3313 int Reg = tryParseRegister();
3315 return MatchOperand_NoMatch;
3316 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3317 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3318 if (Res != MatchOperand_Success)
3322 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3325 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3329 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3334 return MatchOperand_Success;
3336 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3337 Reg = getDRegFromQReg(Reg);
3338 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3339 if (Res != MatchOperand_Success)
3343 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3344 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3345 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3348 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3349 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3350 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3354 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3359 return MatchOperand_Success;
3361 Error(S, "vector register expected");
3362 return MatchOperand_ParseFail;
3365 if (Parser.getTok().isNot(AsmToken::LCurly))
3366 return MatchOperand_NoMatch;
3368 Parser.Lex(); // Eat '{' token.
3369 SMLoc RegLoc = Parser.getTok().getLoc();
3371 int Reg = tryParseRegister();
3373 Error(RegLoc, "register expected");
3374 return MatchOperand_ParseFail;
3378 unsigned FirstReg = Reg;
3379 // The list is of D registers, but we also allow Q regs and just interpret
3380 // them as the two D sub-registers.
3381 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3382 FirstReg = Reg = getDRegFromQReg(Reg);
3383 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3384 // it's ambiguous with four-register single spaced.
3390 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3391 return MatchOperand_ParseFail;
3393 while (Parser.getTok().is(AsmToken::Comma) ||
3394 Parser.getTok().is(AsmToken::Minus)) {
3395 if (Parser.getTok().is(AsmToken::Minus)) {
3397 Spacing = 1; // Register range implies a single spaced list.
3398 else if (Spacing == 2) {
3399 Error(Parser.getTok().getLoc(),
3400 "sequential registers in double spaced list");
3401 return MatchOperand_ParseFail;
3403 Parser.Lex(); // Eat the minus.
3404 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3405 int EndReg = tryParseRegister();
3407 Error(AfterMinusLoc, "register expected");
3408 return MatchOperand_ParseFail;
3410 // Allow Q regs and just interpret them as the two D sub-registers.
3411 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3412 EndReg = getDRegFromQReg(EndReg) + 1;
3413 // If the register is the same as the start reg, there's nothing
3417 // The register must be in the same register class as the first.
3418 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3419 Error(AfterMinusLoc, "invalid register in register list");
3420 return MatchOperand_ParseFail;
3422 // Ranges must go from low to high.
3424 Error(AfterMinusLoc, "bad range in register list");
3425 return MatchOperand_ParseFail;
3427 // Parse the lane specifier if present.
3428 VectorLaneTy NextLaneKind;
3429 unsigned NextLaneIndex;
3430 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3431 MatchOperand_Success)
3432 return MatchOperand_ParseFail;
3433 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3434 Error(AfterMinusLoc, "mismatched lane index in register list");
3435 return MatchOperand_ParseFail;
3438 // Add all the registers in the range to the register list.
3439 Count += EndReg - Reg;
3443 Parser.Lex(); // Eat the comma.
3444 RegLoc = Parser.getTok().getLoc();
3446 Reg = tryParseRegister();
3448 Error(RegLoc, "register expected");
3449 return MatchOperand_ParseFail;
3451 // vector register lists must be contiguous.
3452 // It's OK to use the enumeration values directly here rather, as the
3453 // VFP register classes have the enum sorted properly.
3455 // The list is of D registers, but we also allow Q regs and just interpret
3456 // them as the two D sub-registers.
3457 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3459 Spacing = 1; // Register range implies a single spaced list.
3460 else if (Spacing == 2) {
3462 "invalid register in double-spaced list (must be 'D' register')");
3463 return MatchOperand_ParseFail;
3465 Reg = getDRegFromQReg(Reg);
3466 if (Reg != OldReg + 1) {
3467 Error(RegLoc, "non-contiguous register range");
3468 return MatchOperand_ParseFail;
3472 // Parse the lane specifier if present.
3473 VectorLaneTy NextLaneKind;
3474 unsigned NextLaneIndex;
3475 SMLoc LaneLoc = Parser.getTok().getLoc();
3476 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3477 MatchOperand_Success)
3478 return MatchOperand_ParseFail;
3479 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3480 Error(LaneLoc, "mismatched lane index in register list");
3481 return MatchOperand_ParseFail;
3485 // Normal D register.
3486 // Figure out the register spacing (single or double) of the list if
3487 // we don't know it already.
3489 Spacing = 1 + (Reg == OldReg + 2);
3491 // Just check that it's contiguous and keep going.
3492 if (Reg != OldReg + Spacing) {
3493 Error(RegLoc, "non-contiguous register range");
3494 return MatchOperand_ParseFail;
3497 // Parse the lane specifier if present.
3498 VectorLaneTy NextLaneKind;
3499 unsigned NextLaneIndex;
3500 SMLoc EndLoc = Parser.getTok().getLoc();
3501 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3502 return MatchOperand_ParseFail;
3503 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3504 Error(EndLoc, "mismatched lane index in register list");
3505 return MatchOperand_ParseFail;
3509 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3510 Error(Parser.getTok().getLoc(), "'}' expected");
3511 return MatchOperand_ParseFail;
3513 E = Parser.getTok().getEndLoc();
3514 Parser.Lex(); // Eat '}' token.
3518 // Two-register operands have been converted to the
3519 // composite register classes.
3521 const MCRegisterClass *RC = (Spacing == 1) ?
3522 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3523 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3524 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3527 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3528 (Spacing == 2), S, E));
3531 // Two-register operands have been converted to the
3532 // composite register classes.
3534 const MCRegisterClass *RC = (Spacing == 1) ?
3535 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3536 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3537 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3539 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3544 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3550 return MatchOperand_Success;
3553 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3554 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3555 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3556 SMLoc S = Parser.getTok().getLoc();
3557 const AsmToken &Tok = Parser.getTok();
3560 if (Tok.is(AsmToken::Identifier)) {
3561 StringRef OptStr = Tok.getString();
3563 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3564 .Case("sy", ARM_MB::SY)
3565 .Case("st", ARM_MB::ST)
3566 .Case("ld", ARM_MB::LD)
3567 .Case("sh", ARM_MB::ISH)
3568 .Case("ish", ARM_MB::ISH)
3569 .Case("shst", ARM_MB::ISHST)
3570 .Case("ishst", ARM_MB::ISHST)
3571 .Case("ishld", ARM_MB::ISHLD)
3572 .Case("nsh", ARM_MB::NSH)
3573 .Case("un", ARM_MB::NSH)
3574 .Case("nshst", ARM_MB::NSHST)
3575 .Case("nshld", ARM_MB::NSHLD)
3576 .Case("unst", ARM_MB::NSHST)
3577 .Case("osh", ARM_MB::OSH)
3578 .Case("oshst", ARM_MB::OSHST)
3579 .Case("oshld", ARM_MB::OSHLD)
3582 // ishld, oshld, nshld and ld are only available from ARMv8.
3583 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3584 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3588 return MatchOperand_NoMatch;
3590 Parser.Lex(); // Eat identifier token.
3591 } else if (Tok.is(AsmToken::Hash) ||
3592 Tok.is(AsmToken::Dollar) ||
3593 Tok.is(AsmToken::Integer)) {
3594 if (Parser.getTok().isNot(AsmToken::Integer))
3595 Parser.Lex(); // Eat '#' or '$'.
3596 SMLoc Loc = Parser.getTok().getLoc();
3598 const MCExpr *MemBarrierID;
3599 if (getParser().parseExpression(MemBarrierID)) {
3600 Error(Loc, "illegal expression");
3601 return MatchOperand_ParseFail;
3604 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3606 Error(Loc, "constant expression expected");
3607 return MatchOperand_ParseFail;
3610 int Val = CE->getValue();
3612 Error(Loc, "immediate value out of range");
3613 return MatchOperand_ParseFail;
3616 Opt = ARM_MB::RESERVED_0 + Val;
3618 return MatchOperand_ParseFail;
3620 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3621 return MatchOperand_Success;
3624 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3625 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3626 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3627 SMLoc S = Parser.getTok().getLoc();
3628 const AsmToken &Tok = Parser.getTok();
3631 if (Tok.is(AsmToken::Identifier)) {
3632 StringRef OptStr = Tok.getString();
3634 if (OptStr.equals_lower("sy"))
3637 return MatchOperand_NoMatch;
3639 Parser.Lex(); // Eat identifier token.
3640 } else if (Tok.is(AsmToken::Hash) ||
3641 Tok.is(AsmToken::Dollar) ||
3642 Tok.is(AsmToken::Integer)) {
3643 if (Parser.getTok().isNot(AsmToken::Integer))
3644 Parser.Lex(); // Eat '#' or '$'.
3645 SMLoc Loc = Parser.getTok().getLoc();
3647 const MCExpr *ISBarrierID;
3648 if (getParser().parseExpression(ISBarrierID)) {
3649 Error(Loc, "illegal expression");
3650 return MatchOperand_ParseFail;
3653 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3655 Error(Loc, "constant expression expected");
3656 return MatchOperand_ParseFail;
3659 int Val = CE->getValue();
3661 Error(Loc, "immediate value out of range");
3662 return MatchOperand_ParseFail;
3665 Opt = ARM_ISB::RESERVED_0 + Val;
3667 return MatchOperand_ParseFail;
3669 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3670 (ARM_ISB::InstSyncBOpt)Opt, S));
3671 return MatchOperand_Success;
3675 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3676 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3677 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3678 SMLoc S = Parser.getTok().getLoc();
3679 const AsmToken &Tok = Parser.getTok();
3680 if (!Tok.is(AsmToken::Identifier))
3681 return MatchOperand_NoMatch;
3682 StringRef IFlagsStr = Tok.getString();
3684 // An iflags string of "none" is interpreted to mean that none of the AIF
3685 // bits are set. Not a terribly useful instruction, but a valid encoding.
3686 unsigned IFlags = 0;
3687 if (IFlagsStr != "none") {
3688 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3689 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3690 .Case("a", ARM_PROC::A)
3691 .Case("i", ARM_PROC::I)
3692 .Case("f", ARM_PROC::F)
3695 // If some specific iflag is already set, it means that some letter is
3696 // present more than once, this is not acceptable.
3697 if (Flag == ~0U || (IFlags & Flag))
3698 return MatchOperand_NoMatch;
3704 Parser.Lex(); // Eat identifier token.
3705 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3706 return MatchOperand_Success;
3709 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3710 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3711 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3712 SMLoc S = Parser.getTok().getLoc();
3713 const AsmToken &Tok = Parser.getTok();
3714 if (!Tok.is(AsmToken::Identifier))
3715 return MatchOperand_NoMatch;
3716 StringRef Mask = Tok.getString();
3719 // See ARMv6-M 10.1.1
3720 std::string Name = Mask.lower();
3721 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3722 // Note: in the documentation:
3723 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3724 // for MSR APSR_nzcvq.
3725 // but we do make it an alias here. This is so to get the "mask encoding"
3726 // bits correct on MSR APSR writes.
3728 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3729 // should really only be allowed when writing a special register. Note
3730 // they get dropped in the MRS instruction reading a special register as
3731 // the SYSm field is only 8 bits.
3733 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3734 // includes the DSP extension but that is not checked.
3735 .Case("apsr", 0x800)
3736 .Case("apsr_nzcvq", 0x800)
3737 .Case("apsr_g", 0x400)
3738 .Case("apsr_nzcvqg", 0xc00)
3739 .Case("iapsr", 0x801)
3740 .Case("iapsr_nzcvq", 0x801)
3741 .Case("iapsr_g", 0x401)
3742 .Case("iapsr_nzcvqg", 0xc01)
3743 .Case("eapsr", 0x802)
3744 .Case("eapsr_nzcvq", 0x802)
3745 .Case("eapsr_g", 0x402)
3746 .Case("eapsr_nzcvqg", 0xc02)
3747 .Case("xpsr", 0x803)
3748 .Case("xpsr_nzcvq", 0x803)
3749 .Case("xpsr_g", 0x403)
3750 .Case("xpsr_nzcvqg", 0xc03)
3751 .Case("ipsr", 0x805)
3752 .Case("epsr", 0x806)
3753 .Case("iepsr", 0x807)
3756 .Case("primask", 0x810)
3757 .Case("basepri", 0x811)
3758 .Case("basepri_max", 0x812)
3759 .Case("faultmask", 0x813)
3760 .Case("control", 0x814)
3763 if (FlagsVal == ~0U)
3764 return MatchOperand_NoMatch;
3766 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3767 // basepri, basepri_max and faultmask only valid for V7m.
3768 return MatchOperand_NoMatch;
3770 Parser.Lex(); // Eat identifier token.
3771 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3772 return MatchOperand_Success;
3775 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3776 size_t Start = 0, Next = Mask.find('_');
3777 StringRef Flags = "";
3778 std::string SpecReg = Mask.slice(Start, Next).lower();
3779 if (Next != StringRef::npos)
3780 Flags = Mask.slice(Next+1, Mask.size());
3782 // FlagsVal contains the complete mask:
3784 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3785 unsigned FlagsVal = 0;
3787 if (SpecReg == "apsr") {
3788 FlagsVal = StringSwitch<unsigned>(Flags)
3789 .Case("nzcvq", 0x8) // same as CPSR_f
3790 .Case("g", 0x4) // same as CPSR_s
3791 .Case("nzcvqg", 0xc) // same as CPSR_fs
3794 if (FlagsVal == ~0U) {
3796 return MatchOperand_NoMatch;
3798 FlagsVal = 8; // No flag
3800 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3801 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3802 if (Flags == "all" || Flags == "")
3804 for (int i = 0, e = Flags.size(); i != e; ++i) {
3805 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3812 // If some specific flag is already set, it means that some letter is
3813 // present more than once, this is not acceptable.
3814 if (FlagsVal == ~0U || (FlagsVal & Flag))
3815 return MatchOperand_NoMatch;
3818 } else // No match for special register.
3819 return MatchOperand_NoMatch;
3821 // Special register without flags is NOT equivalent to "fc" flags.
3822 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3823 // two lines would enable gas compatibility at the expense of breaking
3829 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3830 if (SpecReg == "spsr")
3833 Parser.Lex(); // Eat identifier token.
3834 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3835 return MatchOperand_Success;
3838 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3839 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3840 int Low, int High) {
3841 const AsmToken &Tok = Parser.getTok();
3842 if (Tok.isNot(AsmToken::Identifier)) {
3843 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3844 return MatchOperand_ParseFail;
3846 StringRef ShiftName = Tok.getString();
3847 std::string LowerOp = Op.lower();
3848 std::string UpperOp = Op.upper();
3849 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3850 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3851 return MatchOperand_ParseFail;
3853 Parser.Lex(); // Eat shift type token.
3855 // There must be a '#' and a shift amount.
3856 if (Parser.getTok().isNot(AsmToken::Hash) &&
3857 Parser.getTok().isNot(AsmToken::Dollar)) {
3858 Error(Parser.getTok().getLoc(), "'#' expected");
3859 return MatchOperand_ParseFail;
3861 Parser.Lex(); // Eat hash token.
3863 const MCExpr *ShiftAmount;
3864 SMLoc Loc = Parser.getTok().getLoc();
3866 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3867 Error(Loc, "illegal expression");
3868 return MatchOperand_ParseFail;
3870 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3872 Error(Loc, "constant expression expected");
3873 return MatchOperand_ParseFail;
3875 int Val = CE->getValue();
3876 if (Val < Low || Val > High) {
3877 Error(Loc, "immediate value out of range");
3878 return MatchOperand_ParseFail;
3881 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3883 return MatchOperand_Success;
3886 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3887 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3888 const AsmToken &Tok = Parser.getTok();
3889 SMLoc S = Tok.getLoc();
3890 if (Tok.isNot(AsmToken::Identifier)) {
3891 Error(S, "'be' or 'le' operand expected");
3892 return MatchOperand_ParseFail;
3894 int Val = StringSwitch<int>(Tok.getString().lower())
3898 Parser.Lex(); // Eat the token.
3901 Error(S, "'be' or 'le' operand expected");
3902 return MatchOperand_ParseFail;
3904 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3906 S, Tok.getEndLoc()));
3907 return MatchOperand_Success;
3910 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3911 /// instructions. Legal values are:
3912 /// lsl #n 'n' in [0,31]
3913 /// asr #n 'n' in [1,32]
3914 /// n == 32 encoded as n == 0.
3915 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3916 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3917 const AsmToken &Tok = Parser.getTok();
3918 SMLoc S = Tok.getLoc();
3919 if (Tok.isNot(AsmToken::Identifier)) {
3920 Error(S, "shift operator 'asr' or 'lsl' expected");
3921 return MatchOperand_ParseFail;
3923 StringRef ShiftName = Tok.getString();
3925 if (ShiftName == "lsl" || ShiftName == "LSL")
3927 else if (ShiftName == "asr" || ShiftName == "ASR")
3930 Error(S, "shift operator 'asr' or 'lsl' expected");
3931 return MatchOperand_ParseFail;
3933 Parser.Lex(); // Eat the operator.
3935 // A '#' and a shift amount.
3936 if (Parser.getTok().isNot(AsmToken::Hash) &&
3937 Parser.getTok().isNot(AsmToken::Dollar)) {
3938 Error(Parser.getTok().getLoc(), "'#' expected");
3939 return MatchOperand_ParseFail;
3941 Parser.Lex(); // Eat hash token.
3942 SMLoc ExLoc = Parser.getTok().getLoc();
3944 const MCExpr *ShiftAmount;
3946 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3947 Error(ExLoc, "malformed shift expression");
3948 return MatchOperand_ParseFail;
3950 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3952 Error(ExLoc, "shift amount must be an immediate");
3953 return MatchOperand_ParseFail;
3956 int64_t Val = CE->getValue();
3958 // Shift amount must be in [1,32]
3959 if (Val < 1 || Val > 32) {
3960 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3961 return MatchOperand_ParseFail;
3963 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3964 if (isThumb() && Val == 32) {
3965 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3966 return MatchOperand_ParseFail;
3968 if (Val == 32) Val = 0;
3970 // Shift amount must be in [1,32]
3971 if (Val < 0 || Val > 31) {
3972 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3973 return MatchOperand_ParseFail;
3977 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3979 return MatchOperand_Success;
3982 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3983 /// of instructions. Legal values are:
3984 /// ror #n 'n' in {0, 8, 16, 24}
3985 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3986 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3987 const AsmToken &Tok = Parser.getTok();
3988 SMLoc S = Tok.getLoc();
3989 if (Tok.isNot(AsmToken::Identifier))
3990 return MatchOperand_NoMatch;
3991 StringRef ShiftName = Tok.getString();
3992 if (ShiftName != "ror" && ShiftName != "ROR")
3993 return MatchOperand_NoMatch;
3994 Parser.Lex(); // Eat the operator.
3996 // A '#' and a rotate amount.
3997 if (Parser.getTok().isNot(AsmToken::Hash) &&
3998 Parser.getTok().isNot(AsmToken::Dollar)) {
3999 Error(Parser.getTok().getLoc(), "'#' expected");
4000 return MatchOperand_ParseFail;
4002 Parser.Lex(); // Eat hash token.
4003 SMLoc ExLoc = Parser.getTok().getLoc();
4005 const MCExpr *ShiftAmount;
4007 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4008 Error(ExLoc, "malformed rotate expression");
4009 return MatchOperand_ParseFail;
4011 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4013 Error(ExLoc, "rotate amount must be an immediate");
4014 return MatchOperand_ParseFail;
4017 int64_t Val = CE->getValue();
4018 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4019 // normally, zero is represented in asm by omitting the rotate operand
4021 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4022 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4023 return MatchOperand_ParseFail;
4026 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4028 return MatchOperand_Success;
4031 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4032 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4033 SMLoc S = Parser.getTok().getLoc();
4034 // The bitfield descriptor is really two operands, the LSB and the width.
4035 if (Parser.getTok().isNot(AsmToken::Hash) &&
4036 Parser.getTok().isNot(AsmToken::Dollar)) {
4037 Error(Parser.getTok().getLoc(), "'#' expected");
4038 return MatchOperand_ParseFail;
4040 Parser.Lex(); // Eat hash token.
4042 const MCExpr *LSBExpr;
4043 SMLoc E = Parser.getTok().getLoc();
4044 if (getParser().parseExpression(LSBExpr)) {
4045 Error(E, "malformed immediate expression");
4046 return MatchOperand_ParseFail;
4048 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4050 Error(E, "'lsb' operand must be an immediate");
4051 return MatchOperand_ParseFail;
4054 int64_t LSB = CE->getValue();
4055 // The LSB must be in the range [0,31]
4056 if (LSB < 0 || LSB > 31) {
4057 Error(E, "'lsb' operand must be in the range [0,31]");
4058 return MatchOperand_ParseFail;
4060 E = Parser.getTok().getLoc();
4062 // Expect another immediate operand.
4063 if (Parser.getTok().isNot(AsmToken::Comma)) {
4064 Error(Parser.getTok().getLoc(), "too few operands");
4065 return MatchOperand_ParseFail;
4067 Parser.Lex(); // Eat hash token.
4068 if (Parser.getTok().isNot(AsmToken::Hash) &&
4069 Parser.getTok().isNot(AsmToken::Dollar)) {
4070 Error(Parser.getTok().getLoc(), "'#' expected");
4071 return MatchOperand_ParseFail;
4073 Parser.Lex(); // Eat hash token.
4075 const MCExpr *WidthExpr;
4077 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4078 Error(E, "malformed immediate expression");
4079 return MatchOperand_ParseFail;
4081 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4083 Error(E, "'width' operand must be an immediate");
4084 return MatchOperand_ParseFail;
4087 int64_t Width = CE->getValue();
4088 // The LSB must be in the range [1,32-lsb]
4089 if (Width < 1 || Width > 32 - LSB) {
4090 Error(E, "'width' operand must be in the range [1,32-lsb]");
4091 return MatchOperand_ParseFail;
4094 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4096 return MatchOperand_Success;
4099 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4100 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4101 // Check for a post-index addressing register operand. Specifically:
4102 // postidx_reg := '+' register {, shift}
4103 // | '-' register {, shift}
4104 // | register {, shift}
4106 // This method must return MatchOperand_NoMatch without consuming any tokens
4107 // in the case where there is no match, as other alternatives take other
4109 AsmToken Tok = Parser.getTok();
4110 SMLoc S = Tok.getLoc();
4111 bool haveEaten = false;
4113 if (Tok.is(AsmToken::Plus)) {
4114 Parser.Lex(); // Eat the '+' token.
4116 } else if (Tok.is(AsmToken::Minus)) {
4117 Parser.Lex(); // Eat the '-' token.
4122 SMLoc E = Parser.getTok().getEndLoc();
4123 int Reg = tryParseRegister();
4126 return MatchOperand_NoMatch;
4127 Error(Parser.getTok().getLoc(), "register expected");
4128 return MatchOperand_ParseFail;
4131 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4132 unsigned ShiftImm = 0;
4133 if (Parser.getTok().is(AsmToken::Comma)) {
4134 Parser.Lex(); // Eat the ','.
4135 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4136 return MatchOperand_ParseFail;
4138 // FIXME: Only approximates end...may include intervening whitespace.
4139 E = Parser.getTok().getLoc();
4142 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4145 return MatchOperand_Success;
4148 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4149 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4150 // Check for a post-index addressing register operand. Specifically:
4151 // am3offset := '+' register
4158 // This method must return MatchOperand_NoMatch without consuming any tokens
4159 // in the case where there is no match, as other alternatives take other
4161 AsmToken Tok = Parser.getTok();
4162 SMLoc S = Tok.getLoc();
4164 // Do immediates first, as we always parse those if we have a '#'.
4165 if (Parser.getTok().is(AsmToken::Hash) ||
4166 Parser.getTok().is(AsmToken::Dollar)) {
4167 Parser.Lex(); // Eat '#' or '$'.
4168 // Explicitly look for a '-', as we need to encode negative zero
4170 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4171 const MCExpr *Offset;
4173 if (getParser().parseExpression(Offset, E))
4174 return MatchOperand_ParseFail;
4175 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4177 Error(S, "constant expression expected");
4178 return MatchOperand_ParseFail;
4180 // Negative zero is encoded as the flag value INT32_MIN.
4181 int32_t Val = CE->getValue();
4182 if (isNegative && Val == 0)
4186 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4188 return MatchOperand_Success;
4192 bool haveEaten = false;
4194 if (Tok.is(AsmToken::Plus)) {
4195 Parser.Lex(); // Eat the '+' token.
4197 } else if (Tok.is(AsmToken::Minus)) {
4198 Parser.Lex(); // Eat the '-' token.
4203 Tok = Parser.getTok();
4204 int Reg = tryParseRegister();
4207 return MatchOperand_NoMatch;
4208 Error(Tok.getLoc(), "register expected");
4209 return MatchOperand_ParseFail;
4212 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4213 0, S, Tok.getEndLoc()));
4215 return MatchOperand_Success;
4218 /// Convert parsed operands to MCInst. Needed here because this instruction
4219 /// only has two register operands, but multiplication is commutative so
4220 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4222 cvtThumbMultiply(MCInst &Inst,
4223 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4224 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4225 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4226 // If we have a three-operand form, make sure to set Rn to be the operand
4227 // that isn't the same as Rd.
4229 if (Operands.size() == 6 &&
4230 ((ARMOperand*)Operands[4])->getReg() ==
4231 ((ARMOperand*)Operands[3])->getReg())
4233 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4234 Inst.addOperand(Inst.getOperand(0));
4235 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4239 cvtThumbBranches(MCInst &Inst,
4240 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4241 int CondOp = -1, ImmOp = -1;
4242 switch(Inst.getOpcode()) {
4244 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4247 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4249 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4251 // first decide whether or not the branch should be conditional
4252 // by looking at it's location relative to an IT block
4254 // inside an IT block we cannot have any conditional branches. any
4255 // such instructions needs to be converted to unconditional form
4256 switch(Inst.getOpcode()) {
4257 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4258 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4261 // outside IT blocks we can only have unconditional branches with AL
4262 // condition code or conditional branches with non-AL condition code
4263 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4264 switch(Inst.getOpcode()) {
4267 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4271 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4276 // now decide on encoding size based on branch target range
4277 switch(Inst.getOpcode()) {
4278 // classify tB as either t2B or t1B based on range of immediate operand
4280 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4281 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4282 Inst.setOpcode(ARM::t2B);
4285 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4287 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4288 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4289 Inst.setOpcode(ARM::t2Bcc);
4293 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4294 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4297 /// Parse an ARM memory expression, return false if successful else return true
4298 /// or an error. The first token must be a '[' when called.
4300 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4302 assert(Parser.getTok().is(AsmToken::LBrac) &&
4303 "Token is not a Left Bracket");
4304 S = Parser.getTok().getLoc();
4305 Parser.Lex(); // Eat left bracket token.
4307 const AsmToken &BaseRegTok = Parser.getTok();
4308 int BaseRegNum = tryParseRegister();
4309 if (BaseRegNum == -1)
4310 return Error(BaseRegTok.getLoc(), "register expected");
4312 // The next token must either be a comma, a colon or a closing bracket.
4313 const AsmToken &Tok = Parser.getTok();
4314 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4315 !Tok.is(AsmToken::RBrac))
4316 return Error(Tok.getLoc(), "malformed memory operand");
4318 if (Tok.is(AsmToken::RBrac)) {
4319 E = Tok.getEndLoc();
4320 Parser.Lex(); // Eat right bracket token.
4322 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4323 0, 0, false, S, E));
4325 // If there's a pre-indexing writeback marker, '!', just add it as a token
4326 // operand. It's rather odd, but syntactically valid.
4327 if (Parser.getTok().is(AsmToken::Exclaim)) {
4328 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4329 Parser.Lex(); // Eat the '!'.
4335 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4336 "Lost colon or comma in memory operand?!");
4337 if (Tok.is(AsmToken::Comma)) {
4338 Parser.Lex(); // Eat the comma.
4341 // If we have a ':', it's an alignment specifier.
4342 if (Parser.getTok().is(AsmToken::Colon)) {
4343 Parser.Lex(); // Eat the ':'.
4344 E = Parser.getTok().getLoc();
4347 if (getParser().parseExpression(Expr))
4350 // The expression has to be a constant. Memory references with relocations
4351 // don't come through here, as they use the <label> forms of the relevant
4353 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4355 return Error (E, "constant expression expected");
4358 switch (CE->getValue()) {
4361 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4362 case 16: Align = 2; break;
4363 case 32: Align = 4; break;
4364 case 64: Align = 8; break;
4365 case 128: Align = 16; break;
4366 case 256: Align = 32; break;
4369 // Now we should have the closing ']'
4370 if (Parser.getTok().isNot(AsmToken::RBrac))
4371 return Error(Parser.getTok().getLoc(), "']' expected");
4372 E = Parser.getTok().getEndLoc();
4373 Parser.Lex(); // Eat right bracket token.
4375 // Don't worry about range checking the value here. That's handled by
4376 // the is*() predicates.
4377 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4378 ARM_AM::no_shift, 0, Align,
4381 // If there's a pre-indexing writeback marker, '!', just add it as a token
4383 if (Parser.getTok().is(AsmToken::Exclaim)) {
4384 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4385 Parser.Lex(); // Eat the '!'.
4391 // If we have a '#', it's an immediate offset, else assume it's a register
4392 // offset. Be friendly and also accept a plain integer (without a leading
4393 // hash) for gas compatibility.
4394 if (Parser.getTok().is(AsmToken::Hash) ||
4395 Parser.getTok().is(AsmToken::Dollar) ||
4396 Parser.getTok().is(AsmToken::Integer)) {
4397 if (Parser.getTok().isNot(AsmToken::Integer))
4398 Parser.Lex(); // Eat '#' or '$'.
4399 E = Parser.getTok().getLoc();
4401 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4402 const MCExpr *Offset;
4403 if (getParser().parseExpression(Offset))
4406 // The expression has to be a constant. Memory references with relocations
4407 // don't come through here, as they use the <label> forms of the relevant
4409 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4411 return Error (E, "constant expression expected");
4413 // If the constant was #-0, represent it as INT32_MIN.
4414 int32_t Val = CE->getValue();
4415 if (isNegative && Val == 0)
4416 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4418 // Now we should have the closing ']'
4419 if (Parser.getTok().isNot(AsmToken::RBrac))
4420 return Error(Parser.getTok().getLoc(), "']' expected");
4421 E = Parser.getTok().getEndLoc();
4422 Parser.Lex(); // Eat right bracket token.
4424 // Don't worry about range checking the value here. That's handled by
4425 // the is*() predicates.
4426 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4427 ARM_AM::no_shift, 0, 0,
4430 // If there's a pre-indexing writeback marker, '!', just add it as a token
4432 if (Parser.getTok().is(AsmToken::Exclaim)) {
4433 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4434 Parser.Lex(); // Eat the '!'.
4440 // The register offset is optionally preceded by a '+' or '-'
4441 bool isNegative = false;
4442 if (Parser.getTok().is(AsmToken::Minus)) {
4444 Parser.Lex(); // Eat the '-'.
4445 } else if (Parser.getTok().is(AsmToken::Plus)) {
4447 Parser.Lex(); // Eat the '+'.
4450 E = Parser.getTok().getLoc();
4451 int OffsetRegNum = tryParseRegister();
4452 if (OffsetRegNum == -1)
4453 return Error(E, "register expected");
4455 // If there's a shift operator, handle it.
4456 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4457 unsigned ShiftImm = 0;
4458 if (Parser.getTok().is(AsmToken::Comma)) {
4459 Parser.Lex(); // Eat the ','.
4460 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4464 // Now we should have the closing ']'
4465 if (Parser.getTok().isNot(AsmToken::RBrac))
4466 return Error(Parser.getTok().getLoc(), "']' expected");
4467 E = Parser.getTok().getEndLoc();
4468 Parser.Lex(); // Eat right bracket token.
4470 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4471 ShiftType, ShiftImm, 0, isNegative,
4474 // If there's a pre-indexing writeback marker, '!', just add it as a token
4476 if (Parser.getTok().is(AsmToken::Exclaim)) {
4477 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4478 Parser.Lex(); // Eat the '!'.
4484 /// parseMemRegOffsetShift - one of these two:
4485 /// ( lsl | lsr | asr | ror ) , # shift_amount
4487 /// return true if it parses a shift otherwise it returns false.
4488 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4490 SMLoc Loc = Parser.getTok().getLoc();
4491 const AsmToken &Tok = Parser.getTok();
4492 if (Tok.isNot(AsmToken::Identifier))
4494 StringRef ShiftName = Tok.getString();
4495 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4496 ShiftName == "asl" || ShiftName == "ASL")
4498 else if (ShiftName == "lsr" || ShiftName == "LSR")
4500 else if (ShiftName == "asr" || ShiftName == "ASR")
4502 else if (ShiftName == "ror" || ShiftName == "ROR")
4504 else if (ShiftName == "rrx" || ShiftName == "RRX")
4507 return Error(Loc, "illegal shift operator");
4508 Parser.Lex(); // Eat shift type token.
4510 // rrx stands alone.
4512 if (St != ARM_AM::rrx) {
4513 Loc = Parser.getTok().getLoc();
4514 // A '#' and a shift amount.
4515 const AsmToken &HashTok = Parser.getTok();
4516 if (HashTok.isNot(AsmToken::Hash) &&
4517 HashTok.isNot(AsmToken::Dollar))
4518 return Error(HashTok.getLoc(), "'#' expected");
4519 Parser.Lex(); // Eat hash token.
4522 if (getParser().parseExpression(Expr))
4524 // Range check the immediate.
4525 // lsl, ror: 0 <= imm <= 31
4526 // lsr, asr: 0 <= imm <= 32
4527 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4529 return Error(Loc, "shift amount must be an immediate");
4530 int64_t Imm = CE->getValue();
4532 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4533 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4534 return Error(Loc, "immediate shift value out of range");
4535 // If <ShiftTy> #0, turn it into a no_shift.
4538 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4547 /// parseFPImm - A floating point immediate expression operand.
4548 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4549 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4550 // Anything that can accept a floating point constant as an operand
4551 // needs to go through here, as the regular parseExpression is
4554 // This routine still creates a generic Immediate operand, containing
4555 // a bitcast of the 64-bit floating point value. The various operands
4556 // that accept floats can check whether the value is valid for them
4557 // via the standard is*() predicates.
4559 SMLoc S = Parser.getTok().getLoc();
4561 if (Parser.getTok().isNot(AsmToken::Hash) &&
4562 Parser.getTok().isNot(AsmToken::Dollar))
4563 return MatchOperand_NoMatch;
4565 // Disambiguate the VMOV forms that can accept an FP immediate.
4566 // vmov.f32 <sreg>, #imm
4567 // vmov.f64 <dreg>, #imm
4568 // vmov.f32 <dreg>, #imm @ vector f32x2
4569 // vmov.f32 <qreg>, #imm @ vector f32x4
4571 // There are also the NEON VMOV instructions which expect an
4572 // integer constant. Make sure we don't try to parse an FPImm
4574 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4575 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4576 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" ||
4577 TyOp->getToken() == ".f64");
4578 ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]);
4579 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" ||
4580 Mnemonic->getToken() == "fconsts");
4581 if (!(isVmovf || isFconst))
4582 return MatchOperand_NoMatch;
4584 Parser.Lex(); // Eat '#' or '$'.
4586 // Handle negation, as that still comes through as a separate token.
4587 bool isNegative = false;
4588 if (Parser.getTok().is(AsmToken::Minus)) {
4592 const AsmToken &Tok = Parser.getTok();
4593 SMLoc Loc = Tok.getLoc();
4594 if (Tok.is(AsmToken::Real) && isVmovf) {
4595 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4596 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4597 // If we had a '-' in front, toggle the sign bit.
4598 IntVal ^= (uint64_t)isNegative << 31;
4599 Parser.Lex(); // Eat the token.
4600 Operands.push_back(ARMOperand::CreateImm(
4601 MCConstantExpr::Create(IntVal, getContext()),
4602 S, Parser.getTok().getLoc()));
4603 return MatchOperand_Success;
4605 // Also handle plain integers. Instructions which allow floating point
4606 // immediates also allow a raw encoded 8-bit value.
4607 if (Tok.is(AsmToken::Integer) && isFconst) {
4608 int64_t Val = Tok.getIntVal();
4609 Parser.Lex(); // Eat the token.
4610 if (Val > 255 || Val < 0) {
4611 Error(Loc, "encoded floating point value out of range");
4612 return MatchOperand_ParseFail;
4614 float RealVal = ARM_AM::getFPImmFloat(Val);
4615 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4617 Operands.push_back(ARMOperand::CreateImm(
4618 MCConstantExpr::Create(Val, getContext()), S,
4619 Parser.getTok().getLoc()));
4620 return MatchOperand_Success;
4623 Error(Loc, "invalid floating point immediate");
4624 return MatchOperand_ParseFail;
4627 /// Parse a arm instruction operand. For now this parses the operand regardless
4628 /// of the mnemonic.
4629 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4630 StringRef Mnemonic) {
4633 // Check if the current operand has a custom associated parser, if so, try to
4634 // custom parse the operand, or fallback to the general approach.
4635 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4636 if (ResTy == MatchOperand_Success)
4638 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4639 // there was a match, but an error occurred, in which case, just return that
4640 // the operand parsing failed.
4641 if (ResTy == MatchOperand_ParseFail)
4644 switch (getLexer().getKind()) {
4646 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4648 case AsmToken::Identifier: {
4649 // If we've seen a branch mnemonic, the next operand must be a label. This
4650 // is true even if the label is a register name. So "br r1" means branch to
4652 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4654 if (!tryParseRegisterWithWriteBack(Operands))
4656 int Res = tryParseShiftRegister(Operands);
4657 if (Res == 0) // success
4659 else if (Res == -1) // irrecoverable error
4661 // If this is VMRS, check for the apsr_nzcv operand.
4662 if (Mnemonic == "vmrs" &&
4663 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4664 S = Parser.getTok().getLoc();
4666 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4671 // Fall though for the Identifier case that is not a register or a
4674 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4675 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4676 case AsmToken::String: // quoted label names.
4677 case AsmToken::Dot: { // . as a branch target
4678 // This was not a register so parse other operands that start with an
4679 // identifier (like labels) as expressions and create them as immediates.
4680 const MCExpr *IdVal;
4681 S = Parser.getTok().getLoc();
4682 if (getParser().parseExpression(IdVal))
4684 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4685 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4688 case AsmToken::LBrac:
4689 return parseMemory(Operands);
4690 case AsmToken::LCurly:
4691 return parseRegisterList(Operands);
4692 case AsmToken::Dollar:
4693 case AsmToken::Hash: {
4694 // #42 -> immediate.
4695 S = Parser.getTok().getLoc();
4698 if (Parser.getTok().isNot(AsmToken::Colon)) {
4699 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4700 const MCExpr *ImmVal;
4701 if (getParser().parseExpression(ImmVal))
4703 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4705 int32_t Val = CE->getValue();
4706 if (isNegative && Val == 0)
4707 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4709 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4710 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4712 // There can be a trailing '!' on operands that we want as a separate
4713 // '!' Token operand. Handle that here. For example, the compatibility
4714 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4715 if (Parser.getTok().is(AsmToken::Exclaim)) {
4716 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4717 Parser.getTok().getLoc()));
4718 Parser.Lex(); // Eat exclaim token
4722 // w/ a ':' after the '#', it's just like a plain ':'.
4725 case AsmToken::Colon: {
4726 // ":lower16:" and ":upper16:" expression prefixes
4727 // FIXME: Check it's an expression prefix,
4728 // e.g. (FOO - :lower16:BAR) isn't legal.
4729 ARMMCExpr::VariantKind RefKind;
4730 if (parsePrefix(RefKind))
4733 const MCExpr *SubExprVal;
4734 if (getParser().parseExpression(SubExprVal))
4737 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4739 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4740 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4743 case AsmToken::Equal: {
4744 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4745 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4747 Parser.Lex(); // Eat '='
4748 const MCExpr *SubExprVal;
4749 if (getParser().parseExpression(SubExprVal))
4751 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4753 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
4754 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4760 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4761 // :lower16: and :upper16:.
4762 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4763 RefKind = ARMMCExpr::VK_ARM_None;
4765 // consume an optional '#' (GNU compatibility)
4766 if (getLexer().is(AsmToken::Hash))
4769 // :lower16: and :upper16: modifiers
4770 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4771 Parser.Lex(); // Eat ':'
4773 if (getLexer().isNot(AsmToken::Identifier)) {
4774 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4778 StringRef IDVal = Parser.getTok().getIdentifier();
4779 if (IDVal == "lower16") {
4780 RefKind = ARMMCExpr::VK_ARM_LO16;
4781 } else if (IDVal == "upper16") {
4782 RefKind = ARMMCExpr::VK_ARM_HI16;
4784 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4789 if (getLexer().isNot(AsmToken::Colon)) {
4790 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4793 Parser.Lex(); // Eat the last ':'
4797 /// \brief Given a mnemonic, split out possible predication code and carry
4798 /// setting letters to form a canonical mnemonic and flags.
4800 // FIXME: Would be nice to autogen this.
4801 // FIXME: This is a bit of a maze of special cases.
4802 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4803 unsigned &PredicationCode,
4805 unsigned &ProcessorIMod,
4806 StringRef &ITMask) {
4807 PredicationCode = ARMCC::AL;
4808 CarrySetting = false;
4811 // Ignore some mnemonics we know aren't predicated forms.
4813 // FIXME: Would be nice to autogen this.
4814 if ((Mnemonic == "movs" && isThumb()) ||
4815 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4816 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4817 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4818 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4819 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4820 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4821 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4822 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4823 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4824 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4825 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4826 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4829 // First, split out any predication code. Ignore mnemonics we know aren't
4830 // predicated but do have a carry-set and so weren't caught above.
4831 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4832 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4833 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4834 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4835 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4836 .Case("eq", ARMCC::EQ)
4837 .Case("ne", ARMCC::NE)
4838 .Case("hs", ARMCC::HS)
4839 .Case("cs", ARMCC::HS)
4840 .Case("lo", ARMCC::LO)
4841 .Case("cc", ARMCC::LO)
4842 .Case("mi", ARMCC::MI)
4843 .Case("pl", ARMCC::PL)
4844 .Case("vs", ARMCC::VS)
4845 .Case("vc", ARMCC::VC)
4846 .Case("hi", ARMCC::HI)
4847 .Case("ls", ARMCC::LS)
4848 .Case("ge", ARMCC::GE)
4849 .Case("lt", ARMCC::LT)
4850 .Case("gt", ARMCC::GT)
4851 .Case("le", ARMCC::LE)
4852 .Case("al", ARMCC::AL)
4855 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4856 PredicationCode = CC;
4860 // Next, determine if we have a carry setting bit. We explicitly ignore all
4861 // the instructions we know end in 's'.
4862 if (Mnemonic.endswith("s") &&
4863 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4864 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4865 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4866 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4867 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4868 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4869 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4870 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4871 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
4872 (Mnemonic == "movs" && isThumb()))) {
4873 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4874 CarrySetting = true;
4877 // The "cps" instruction can have a interrupt mode operand which is glued into
4878 // the mnemonic. Check if this is the case, split it and parse the imod op
4879 if (Mnemonic.startswith("cps")) {
4880 // Split out any imod code.
4882 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4883 .Case("ie", ARM_PROC::IE)
4884 .Case("id", ARM_PROC::ID)
4887 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4888 ProcessorIMod = IMod;
4892 // The "it" instruction has the condition mask on the end of the mnemonic.
4893 if (Mnemonic.startswith("it")) {
4894 ITMask = Mnemonic.slice(2, Mnemonic.size());
4895 Mnemonic = Mnemonic.slice(0, 2);
4901 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4902 /// inclusion of carry set or predication code operands.
4904 // FIXME: It would be nice to autogen this.
4906 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4907 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
4908 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4909 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4910 Mnemonic == "add" || Mnemonic == "adc" ||
4911 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4912 Mnemonic == "orr" || Mnemonic == "mvn" ||
4913 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4914 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4915 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4916 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4917 Mnemonic == "mla" || Mnemonic == "smlal" ||
4918 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4919 CanAcceptCarrySet = true;
4921 CanAcceptCarrySet = false;
4923 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4924 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4925 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
4926 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4927 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4928 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4929 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4930 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
4931 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
4932 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
4933 // These mnemonics are never predicable
4934 CanAcceptPredicationCode = false;
4935 } else if (!isThumb()) {
4936 // Some instructions are only predicable in Thumb mode
4937 CanAcceptPredicationCode
4938 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4939 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4940 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4941 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4942 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4943 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4944 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4945 } else if (isThumbOne()) {
4947 CanAcceptPredicationCode = Mnemonic != "movs";
4949 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4951 CanAcceptPredicationCode = true;
4954 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4955 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4956 // FIXME: This is all horribly hacky. We really need a better way to deal
4957 // with optional operands like this in the matcher table.
4959 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4960 // another does not. Specifically, the MOVW instruction does not. So we
4961 // special case it here and remove the defaulted (non-setting) cc_out
4962 // operand if that's the instruction we're trying to match.
4964 // We do this as post-processing of the explicit operands rather than just
4965 // conditionally adding the cc_out in the first place because we need
4966 // to check the type of the parsed immediate operand.
4967 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4968 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4969 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4970 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4973 // Register-register 'add' for thumb does not have a cc_out operand
4974 // when there are only two register operands.
4975 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4976 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4977 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4978 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4980 // Register-register 'add' for thumb does not have a cc_out operand
4981 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4982 // have to check the immediate range here since Thumb2 has a variant
4983 // that can handle a different range and has a cc_out operand.
4984 if (((isThumb() && Mnemonic == "add") ||
4985 (isThumbTwo() && Mnemonic == "sub")) &&
4986 Operands.size() == 6 &&
4987 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4988 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4989 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4990 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4991 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4992 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4994 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4995 // imm0_4095 variant. That's the least-preferred variant when
4996 // selecting via the generic "add" mnemonic, so to know that we
4997 // should remove the cc_out operand, we have to explicitly check that
4998 // it's not one of the other variants. Ugh.
4999 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5000 Operands.size() == 6 &&
5001 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5002 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5003 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5004 // Nest conditions rather than one big 'if' statement for readability.
5006 // If both registers are low, we're in an IT block, and the immediate is
5007 // in range, we should use encoding T1 instead, which has a cc_out.
5009 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5010 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5011 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5013 // Check against T3. If the second register is the PC, this is an
5014 // alternate form of ADR, which uses encoding T4, so check for that too.
5015 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5016 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5019 // Otherwise, we use encoding T4, which does not have a cc_out
5024 // The thumb2 multiply instruction doesn't have a CCOut register, so
5025 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5026 // use the 16-bit encoding or not.
5027 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5028 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5029 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5030 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5031 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5032 // If the registers aren't low regs, the destination reg isn't the
5033 // same as one of the source regs, or the cc_out operand is zero
5034 // outside of an IT block, we have to use the 32-bit encoding, so
5035 // remove the cc_out operand.
5036 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5037 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5038 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5040 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5041 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5042 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5043 static_cast<ARMOperand*>(Operands[4])->getReg())))
5046 // Also check the 'mul' syntax variant that doesn't specify an explicit
5047 // destination register.
5048 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5049 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5050 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5051 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5052 // If the registers aren't low regs or the cc_out operand is zero
5053 // outside of an IT block, we have to use the 32-bit encoding, so
5054 // remove the cc_out operand.
5055 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5056 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5062 // Register-register 'add/sub' for thumb does not have a cc_out operand
5063 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5064 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5065 // right, this will result in better diagnostics (which operand is off)
5067 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5068 (Operands.size() == 5 || Operands.size() == 6) &&
5069 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5070 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5071 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5072 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5073 (Operands.size() == 6 &&
5074 static_cast<ARMOperand*>(Operands[5])->isImm())))
5080 bool ARMAsmParser::shouldOmitPredicateOperand(
5081 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5082 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5083 unsigned RegIdx = 3;
5084 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5085 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5086 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5087 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5090 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5091 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5092 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5093 ARMMCRegisterClasses[ARM::QPRRegClassID]
5094 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5100 static bool isDataTypeToken(StringRef Tok) {
5101 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5102 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5103 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5104 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5105 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5106 Tok == ".f" || Tok == ".d";
5109 // FIXME: This bit should probably be handled via an explicit match class
5110 // in the .td files that matches the suffix instead of having it be
5111 // a literal string token the way it is now.
5112 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5113 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5115 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5116 unsigned VariantID);
5118 static bool RequiresVFPRegListValidation(StringRef Inst,
5119 bool &AcceptSinglePrecisionOnly,
5120 bool &AcceptDoublePrecisionOnly) {
5121 if (Inst.size() < 7)
5124 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5125 StringRef AddressingMode = Inst.substr(4, 2);
5126 if (AddressingMode == "ia" || AddressingMode == "db" ||
5127 AddressingMode == "ea" || AddressingMode == "fd") {
5128 AcceptSinglePrecisionOnly = Inst[6] == 's';
5129 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5137 /// Parse an arm instruction mnemonic followed by its operands.
5138 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5140 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5141 // FIXME: Can this be done via tablegen in some fashion?
5142 bool RequireVFPRegisterListCheck;
5143 bool AcceptSinglePrecisionOnly;
5144 bool AcceptDoublePrecisionOnly;
5145 RequireVFPRegisterListCheck =
5146 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5147 AcceptDoublePrecisionOnly);
5149 // Apply mnemonic aliases before doing anything else, as the destination
5150 // mnemonic may include suffices and we want to handle them normally.
5151 // The generic tblgen'erated code does this later, at the start of
5152 // MatchInstructionImpl(), but that's too late for aliases that include
5153 // any sort of suffix.
5154 unsigned AvailableFeatures = getAvailableFeatures();
5155 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5156 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5158 // First check for the ARM-specific .req directive.
5159 if (Parser.getTok().is(AsmToken::Identifier) &&
5160 Parser.getTok().getIdentifier() == ".req") {
5161 parseDirectiveReq(Name, NameLoc);
5162 // We always return 'error' for this, as we're done with this
5163 // statement and don't need to match the 'instruction."
5167 // Create the leading tokens for the mnemonic, split by '.' characters.
5168 size_t Start = 0, Next = Name.find('.');
5169 StringRef Mnemonic = Name.slice(Start, Next);
5171 // Split out the predication code and carry setting flag from the mnemonic.
5172 unsigned PredicationCode;
5173 unsigned ProcessorIMod;
5176 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5177 ProcessorIMod, ITMask);
5179 // In Thumb1, only the branch (B) instruction can be predicated.
5180 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5181 Parser.eatToEndOfStatement();
5182 return Error(NameLoc, "conditional execution not supported in Thumb1");
5185 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5187 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5188 // is the mask as it will be for the IT encoding if the conditional
5189 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5190 // where the conditional bit0 is zero, the instruction post-processing
5191 // will adjust the mask accordingly.
5192 if (Mnemonic == "it") {
5193 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5194 if (ITMask.size() > 3) {
5195 Parser.eatToEndOfStatement();
5196 return Error(Loc, "too many conditions on IT instruction");
5199 for (unsigned i = ITMask.size(); i != 0; --i) {
5200 char pos = ITMask[i - 1];
5201 if (pos != 't' && pos != 'e') {
5202 Parser.eatToEndOfStatement();
5203 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5206 if (ITMask[i - 1] == 't')
5209 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5212 // FIXME: This is all a pretty gross hack. We should automatically handle
5213 // optional operands like this via tblgen.
5215 // Next, add the CCOut and ConditionCode operands, if needed.
5217 // For mnemonics which can ever incorporate a carry setting bit or predication
5218 // code, our matching model involves us always generating CCOut and
5219 // ConditionCode operands to match the mnemonic "as written" and then we let
5220 // the matcher deal with finding the right instruction or generating an
5221 // appropriate error.
5222 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5223 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5225 // If we had a carry-set on an instruction that can't do that, issue an
5227 if (!CanAcceptCarrySet && CarrySetting) {
5228 Parser.eatToEndOfStatement();
5229 return Error(NameLoc, "instruction '" + Mnemonic +
5230 "' can not set flags, but 's' suffix specified");
5232 // If we had a predication code on an instruction that can't do that, issue an
5234 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5235 Parser.eatToEndOfStatement();
5236 return Error(NameLoc, "instruction '" + Mnemonic +
5237 "' is not predicable, but condition code specified");
5240 // Add the carry setting operand, if necessary.
5241 if (CanAcceptCarrySet) {
5242 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5243 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5247 // Add the predication code operand, if necessary.
5248 if (CanAcceptPredicationCode) {
5249 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5251 Operands.push_back(ARMOperand::CreateCondCode(
5252 ARMCC::CondCodes(PredicationCode), Loc));
5255 // Add the processor imod operand, if necessary.
5256 if (ProcessorIMod) {
5257 Operands.push_back(ARMOperand::CreateImm(
5258 MCConstantExpr::Create(ProcessorIMod, getContext()),
5262 // Add the remaining tokens in the mnemonic.
5263 while (Next != StringRef::npos) {
5265 Next = Name.find('.', Start + 1);
5266 StringRef ExtraToken = Name.slice(Start, Next);
5268 // Some NEON instructions have an optional datatype suffix that is
5269 // completely ignored. Check for that.
5270 if (isDataTypeToken(ExtraToken) &&
5271 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5274 // For for ARM mode generate an error if the .n qualifier is used.
5275 if (ExtraToken == ".n" && !isThumb()) {
5276 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5277 Parser.eatToEndOfStatement();
5278 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5282 // The .n qualifier is always discarded as that is what the tables
5283 // and matcher expect. In ARM mode the .w qualifier has no effect,
5284 // so discard it to avoid errors that can be caused by the matcher.
5285 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5286 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5287 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5291 // Read the remaining operands.
5292 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5293 // Read the first operand.
5294 if (parseOperand(Operands, Mnemonic)) {
5295 Parser.eatToEndOfStatement();
5299 while (getLexer().is(AsmToken::Comma)) {
5300 Parser.Lex(); // Eat the comma.
5302 // Parse and remember the operand.
5303 if (parseOperand(Operands, Mnemonic)) {
5304 Parser.eatToEndOfStatement();
5310 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5311 SMLoc Loc = getLexer().getLoc();
5312 Parser.eatToEndOfStatement();
5313 return Error(Loc, "unexpected token in argument list");
5316 Parser.Lex(); // Consume the EndOfStatement
5318 if (RequireVFPRegisterListCheck) {
5319 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5320 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5321 return Error(Op->getStartLoc(),
5322 "VFP/Neon single precision register expected");
5323 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5324 return Error(Op->getStartLoc(),
5325 "VFP/Neon double precision register expected");
5328 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5329 // do and don't have a cc_out optional-def operand. With some spot-checks
5330 // of the operand list, we can figure out which variant we're trying to
5331 // parse and adjust accordingly before actually matching. We shouldn't ever
5332 // try to remove a cc_out operand that was explicitly set on the the
5333 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5334 // table driven matcher doesn't fit well with the ARM instruction set.
5335 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5336 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5337 Operands.erase(Operands.begin() + 1);
5341 // Some instructions have the same mnemonic, but don't always
5342 // have a predicate. Distinguish them here and delete the
5343 // predicate if needed.
5344 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5345 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5346 Operands.erase(Operands.begin() + 1);
5350 // ARM mode 'blx' need special handling, as the register operand version
5351 // is predicable, but the label operand version is not. So, we can't rely
5352 // on the Mnemonic based checking to correctly figure out when to put
5353 // a k_CondCode operand in the list. If we're trying to match the label
5354 // version, remove the k_CondCode operand here.
5355 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5356 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5357 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5358 Operands.erase(Operands.begin() + 1);
5362 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5363 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5364 // a single GPRPair reg operand is used in the .td file to replace the two
5365 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5366 // expressed as a GPRPair, so we have to manually merge them.
5367 // FIXME: We would really like to be able to tablegen'erate this.
5368 if (!isThumb() && Operands.size() > 4 &&
5369 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5370 Mnemonic == "stlexd")) {
5371 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5372 unsigned Idx = isLoad ? 2 : 3;
5373 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5374 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5376 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5377 // Adjust only if Op1 and Op2 are GPRs.
5378 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5379 MRC.contains(Op2->getReg())) {
5380 unsigned Reg1 = Op1->getReg();
5381 unsigned Reg2 = Op2->getReg();
5382 unsigned Rt = MRI->getEncodingValue(Reg1);
5383 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5385 // Rt2 must be Rt + 1 and Rt must be even.
5386 if (Rt + 1 != Rt2 || (Rt & 1)) {
5387 Error(Op2->getStartLoc(), isLoad ?
5388 "destination operands must be sequential" :
5389 "source operands must be sequential");
5392 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5393 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5394 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5395 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5396 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5402 // GNU Assembler extension (compatibility)
5403 if ((Mnemonic == "ldrd" || Mnemonic == "strd") && !isThumb() &&
5404 Operands.size() == 4) {
5405 ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]);
5406 assert(Op->isReg() && "expected register argument");
5407 assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0,
5408 &MRI->getRegClass(ARM::GPRPairRegClassID))
5409 && "expected register pair");
5410 Operands.insert(Operands.begin() + 3,
5411 ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(),
5415 // FIXME: As said above, this is all a pretty gross hack. This instruction
5416 // does not fit with other "subs" and tblgen.
5417 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5418 // so the Mnemonic is the original name "subs" and delete the predicate
5419 // operand so it will match the table entry.
5420 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5421 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5422 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5423 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5424 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5425 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5426 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5427 Operands.erase(Operands.begin());
5429 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5431 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5432 Operands.erase(Operands.begin() + 1);
5438 // Validate context-sensitive operand constraints.
5440 // return 'true' if register list contains non-low GPR registers,
5441 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5442 // 'containsReg' to true.
5443 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5444 unsigned HiReg, bool &containsReg) {
5445 containsReg = false;
5446 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5447 unsigned OpReg = Inst.getOperand(i).getReg();
5450 // Anything other than a low register isn't legal here.
5451 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5457 // Check if the specified regisgter is in the register list of the inst,
5458 // starting at the indicated operand number.
5459 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5460 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5461 unsigned OpReg = Inst.getOperand(i).getReg();
5468 // Return true if instruction has the interesting property of being
5469 // allowed in IT blocks, but not being predicable.
5470 static bool instIsBreakpoint(const MCInst &Inst) {
5471 return Inst.getOpcode() == ARM::tBKPT ||
5472 Inst.getOpcode() == ARM::BKPT ||
5473 Inst.getOpcode() == ARM::tHLT ||
5474 Inst.getOpcode() == ARM::HLT;
5478 // FIXME: We would really like to be able to tablegen'erate this.
5480 validateInstruction(MCInst &Inst,
5481 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5482 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5483 SMLoc Loc = Operands[0]->getStartLoc();
5485 // Check the IT block state first.
5486 // NOTE: BKPT and HLT instructions have the interesting property of being
5487 // allowed in IT blocks, but not being predicable. They just always execute.
5488 if (inITBlock() && !instIsBreakpoint(Inst)) {
5490 if (ITState.FirstCond)
5491 ITState.FirstCond = false;
5493 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5494 // The instruction must be predicable.
5495 if (!MCID.isPredicable())
5496 return Error(Loc, "instructions in IT block must be predicable");
5497 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5498 unsigned ITCond = Bit ? ITState.Cond :
5499 ARMCC::getOppositeCondition(ITState.Cond);
5500 if (Cond != ITCond) {
5501 // Find the condition code Operand to get its SMLoc information.
5503 for (unsigned I = 1; I < Operands.size(); ++I)
5504 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5505 CondLoc = Operands[I]->getStartLoc();
5506 return Error(CondLoc, "incorrect condition in IT block; got '" +
5507 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5508 "', but expected '" +
5509 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5511 // Check for non-'al' condition codes outside of the IT block.
5512 } else if (isThumbTwo() && MCID.isPredicable() &&
5513 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5514 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5515 Inst.getOpcode() != ARM::t2Bcc)
5516 return Error(Loc, "predicated instructions must be in IT block");
5518 const unsigned Opcode = Inst.getOpcode();
5522 case ARM::LDRD_POST: {
5523 const unsigned RtReg = Inst.getOperand(0).getReg();
5526 if (RtReg == ARM::LR)
5527 return Error(Operands[3]->getStartLoc(),
5530 const unsigned Rt = MRI->getEncodingValue(RtReg);
5531 // Rt must be even-numbered.
5533 return Error(Operands[3]->getStartLoc(),
5534 "Rt must be even-numbered");
5536 // Rt2 must be Rt + 1.
5537 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5539 return Error(Operands[3]->getStartLoc(),
5540 "destination operands must be sequential");
5542 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5543 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5544 // For addressing modes with writeback, the base register needs to be
5545 // different from the destination registers.
5546 if (Rn == Rt || Rn == Rt2)
5547 return Error(Operands[3]->getStartLoc(),
5548 "base register needs to be different from destination "
5555 case ARM::t2LDRD_PRE:
5556 case ARM::t2LDRD_POST: {
5557 // Rt2 must be different from Rt.
5558 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5559 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5561 return Error(Operands[3]->getStartLoc(),
5562 "destination operands can't be identical");
5566 // Rt2 must be Rt + 1.
5567 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5568 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5570 return Error(Operands[3]->getStartLoc(),
5571 "source operands must be sequential");
5575 case ARM::STRD_POST: {
5576 // Rt2 must be Rt + 1.
5577 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5578 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5580 return Error(Operands[3]->getStartLoc(),
5581 "source operands must be sequential");
5586 // Width must be in range [1, 32-lsb].
5587 unsigned LSB = Inst.getOperand(2).getImm();
5588 unsigned Widthm1 = Inst.getOperand(3).getImm();
5589 if (Widthm1 >= 32 - LSB)
5590 return Error(Operands[5]->getStartLoc(),
5591 "bitfield width must be in range [1,32-lsb]");
5594 // Notionally handles ARM::tLDMIA_UPD too.
5596 // If we're parsing Thumb2, the .w variant is available and handles
5597 // most cases that are normally illegal for a Thumb1 LDM instruction.
5598 // We'll make the transformation in processInstruction() if necessary.
5600 // Thumb LDM instructions are writeback iff the base register is not
5601 // in the register list.
5602 unsigned Rn = Inst.getOperand(0).getReg();
5603 bool HasWritebackToken =
5604 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5605 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5606 bool ListContainsBase;
5607 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5608 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5609 "registers must be in range r0-r7");
5610 // If we should have writeback, then there should be a '!' token.
5611 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5612 return Error(Operands[2]->getStartLoc(),
5613 "writeback operator '!' expected");
5614 // If we should not have writeback, there must not be a '!'. This is
5615 // true even for the 32-bit wide encodings.
5616 if (ListContainsBase && HasWritebackToken)
5617 return Error(Operands[3]->getStartLoc(),
5618 "writeback operator '!' not allowed when base register "
5619 "in register list");
5623 case ARM::LDMIA_UPD:
5624 case ARM::LDMDB_UPD:
5625 case ARM::LDMIB_UPD:
5626 case ARM::LDMDA_UPD:
5627 // ARM variants loading and updating the same register are only officially
5628 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5632 case ARM::t2LDMIA_UPD:
5633 case ARM::t2LDMDB_UPD:
5634 case ARM::t2STMIA_UPD:
5635 case ARM::t2STMDB_UPD: {
5636 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5637 return Error(Operands.back()->getStartLoc(),
5638 "writeback register not allowed in register list");
5641 case ARM::sysLDMIA_UPD:
5642 case ARM::sysLDMDA_UPD:
5643 case ARM::sysLDMDB_UPD:
5644 case ARM::sysLDMIB_UPD:
5645 if (!listContainsReg(Inst, 3, ARM::PC))
5646 return Error(Operands[4]->getStartLoc(),
5647 "writeback register only allowed on system LDM "
5648 "if PC in register-list");
5650 case ARM::sysSTMIA_UPD:
5651 case ARM::sysSTMDA_UPD:
5652 case ARM::sysSTMDB_UPD:
5653 case ARM::sysSTMIB_UPD:
5654 return Error(Operands[2]->getStartLoc(),
5655 "system STM cannot have writeback register");
5657 // The second source operand must be the same register as the destination
5660 // In this case, we must directly check the parsed operands because the
5661 // cvtThumbMultiply() function is written in such a way that it guarantees
5662 // this first statement is always true for the new Inst. Essentially, the
5663 // destination is unconditionally copied into the second source operand
5664 // without checking to see if it matches what we actually parsed.
5665 if (Operands.size() == 6 &&
5666 (((ARMOperand*)Operands[3])->getReg() !=
5667 ((ARMOperand*)Operands[5])->getReg()) &&
5668 (((ARMOperand*)Operands[3])->getReg() !=
5669 ((ARMOperand*)Operands[4])->getReg())) {
5670 return Error(Operands[3]->getStartLoc(),
5671 "destination register must match source register");
5675 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5676 // so only issue a diagnostic for thumb1. The instructions will be
5677 // switched to the t2 encodings in processInstruction() if necessary.
5679 bool ListContainsBase;
5680 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5682 return Error(Operands[2]->getStartLoc(),
5683 "registers must be in range r0-r7 or pc");
5687 bool ListContainsBase;
5688 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5690 return Error(Operands[2]->getStartLoc(),
5691 "registers must be in range r0-r7 or lr");
5694 case ARM::tSTMIA_UPD: {
5695 bool ListContainsBase, InvalidLowList;
5696 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5697 0, ListContainsBase);
5698 if (InvalidLowList && !isThumbTwo())
5699 return Error(Operands[4]->getStartLoc(),
5700 "registers must be in range r0-r7");
5702 // This would be converted to a 32-bit stm, but that's not valid if the
5703 // writeback register is in the list.
5704 if (InvalidLowList && ListContainsBase)
5705 return Error(Operands[4]->getStartLoc(),
5706 "writeback operator '!' not allowed when base register "
5707 "in register list");
5710 case ARM::tADDrSP: {
5711 // If the non-SP source operand and the destination operand are not the
5712 // same, we need thumb2 (for the wide encoding), or we have an error.
5713 if (!isThumbTwo() &&
5714 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5715 return Error(Operands[4]->getStartLoc(),
5716 "source register must be the same as destination");
5720 // Final range checking for Thumb unconditional branch instructions.
5722 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5723 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5726 int op = (Operands[2]->isImm()) ? 2 : 3;
5727 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5728 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5731 // Final range checking for Thumb conditional branch instructions.
5733 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5734 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5737 int Op = (Operands[2]->isImm()) ? 2 : 3;
5738 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5739 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5747 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5749 default: llvm_unreachable("unexpected opcode!");
5751 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5752 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5753 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5754 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5755 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5756 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5757 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5758 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5759 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5762 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5763 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5764 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5765 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5766 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5768 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5769 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5770 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5771 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5772 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5774 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5775 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5776 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5777 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5778 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5781 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5782 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5783 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5784 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5785 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5786 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5787 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5788 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5789 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5790 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5791 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5792 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5793 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5794 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5795 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5798 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5799 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5800 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5801 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5802 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5803 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5804 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5805 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5806 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5807 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5808 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5809 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5810 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5811 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5812 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5813 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5814 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5815 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5818 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5819 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5820 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5821 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5822 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5823 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5824 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5825 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5826 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5827 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5828 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5829 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5830 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5831 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5832 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5835 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5836 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5837 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5838 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5839 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5840 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5841 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5842 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5843 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5844 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5845 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5846 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5847 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5848 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5849 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5850 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5851 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5852 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5856 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5858 default: llvm_unreachable("unexpected opcode!");
5860 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5861 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5862 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5863 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5864 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5865 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5866 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5867 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5868 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5871 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5872 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5873 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5874 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5875 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5876 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5877 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5878 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5879 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5880 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5881 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5882 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5883 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5884 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5885 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5888 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5889 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5890 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5891 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5892 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5893 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5894 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5895 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5896 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5897 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5898 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5899 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5900 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5901 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5902 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5903 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5904 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5905 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5908 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5909 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5910 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5911 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5912 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5913 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5914 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5915 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5916 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5917 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5918 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5919 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5920 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5921 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5922 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5925 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5926 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5927 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5928 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5929 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5930 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5931 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5932 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5933 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5934 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5935 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5936 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5937 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5938 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5939 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5940 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5941 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5942 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5945 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5946 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5947 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5948 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5949 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5950 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5951 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5952 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5953 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5954 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5955 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5956 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5957 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5958 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5959 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5962 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5963 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5964 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5965 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5966 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5967 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5968 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5969 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5970 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5971 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5972 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5973 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5974 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5975 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5976 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5977 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5978 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5979 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5982 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5983 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5984 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5985 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5986 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5987 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5988 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5989 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5990 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5991 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5992 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5993 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5994 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5995 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5996 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5997 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5998 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5999 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6004 processInstruction(MCInst &Inst,
6005 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6006 switch (Inst.getOpcode()) {
6007 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6008 case ARM::LDRT_POST:
6009 case ARM::LDRBT_POST: {
6010 const unsigned Opcode =
6011 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6012 : ARM::LDRBT_POST_IMM;
6014 TmpInst.setOpcode(Opcode);
6015 TmpInst.addOperand(Inst.getOperand(0));
6016 TmpInst.addOperand(Inst.getOperand(1));
6017 TmpInst.addOperand(Inst.getOperand(1));
6018 TmpInst.addOperand(MCOperand::CreateReg(0));
6019 TmpInst.addOperand(MCOperand::CreateImm(0));
6020 TmpInst.addOperand(Inst.getOperand(2));
6021 TmpInst.addOperand(Inst.getOperand(3));
6025 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6026 case ARM::STRT_POST:
6027 case ARM::STRBT_POST: {
6028 const unsigned Opcode =
6029 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6030 : ARM::STRBT_POST_IMM;
6032 TmpInst.setOpcode(Opcode);
6033 TmpInst.addOperand(Inst.getOperand(1));
6034 TmpInst.addOperand(Inst.getOperand(0));
6035 TmpInst.addOperand(Inst.getOperand(1));
6036 TmpInst.addOperand(MCOperand::CreateReg(0));
6037 TmpInst.addOperand(MCOperand::CreateImm(0));
6038 TmpInst.addOperand(Inst.getOperand(2));
6039 TmpInst.addOperand(Inst.getOperand(3));
6043 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6045 if (Inst.getOperand(1).getReg() != ARM::PC ||
6046 Inst.getOperand(5).getReg() != 0)
6049 TmpInst.setOpcode(ARM::ADR);
6050 TmpInst.addOperand(Inst.getOperand(0));
6051 TmpInst.addOperand(Inst.getOperand(2));
6052 TmpInst.addOperand(Inst.getOperand(3));
6053 TmpInst.addOperand(Inst.getOperand(4));
6057 // Aliases for alternate PC+imm syntax of LDR instructions.
6058 case ARM::t2LDRpcrel:
6059 // Select the narrow version if the immediate will fit.
6060 if (Inst.getOperand(1).getImm() > 0 &&
6061 Inst.getOperand(1).getImm() <= 0xff &&
6062 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
6063 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
6064 Inst.setOpcode(ARM::tLDRpci);
6066 Inst.setOpcode(ARM::t2LDRpci);
6068 case ARM::t2LDRBpcrel:
6069 Inst.setOpcode(ARM::t2LDRBpci);
6071 case ARM::t2LDRHpcrel:
6072 Inst.setOpcode(ARM::t2LDRHpci);
6074 case ARM::t2LDRSBpcrel:
6075 Inst.setOpcode(ARM::t2LDRSBpci);
6077 case ARM::t2LDRSHpcrel:
6078 Inst.setOpcode(ARM::t2LDRSHpci);
6080 // Handle NEON VST complex aliases.
6081 case ARM::VST1LNdWB_register_Asm_8:
6082 case ARM::VST1LNdWB_register_Asm_16:
6083 case ARM::VST1LNdWB_register_Asm_32: {
6085 // Shuffle the operands around so the lane index operand is in the
6088 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6089 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6090 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6091 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6092 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6093 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6094 TmpInst.addOperand(Inst.getOperand(1)); // lane
6095 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6096 TmpInst.addOperand(Inst.getOperand(6));
6101 case ARM::VST2LNdWB_register_Asm_8:
6102 case ARM::VST2LNdWB_register_Asm_16:
6103 case ARM::VST2LNdWB_register_Asm_32:
6104 case ARM::VST2LNqWB_register_Asm_16:
6105 case ARM::VST2LNqWB_register_Asm_32: {
6107 // Shuffle the operands around so the lane index operand is in the
6110 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6111 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6112 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6113 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6114 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6115 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6116 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6118 TmpInst.addOperand(Inst.getOperand(1)); // lane
6119 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6120 TmpInst.addOperand(Inst.getOperand(6));
6125 case ARM::VST3LNdWB_register_Asm_8:
6126 case ARM::VST3LNdWB_register_Asm_16:
6127 case ARM::VST3LNdWB_register_Asm_32:
6128 case ARM::VST3LNqWB_register_Asm_16:
6129 case ARM::VST3LNqWB_register_Asm_32: {
6131 // Shuffle the operands around so the lane index operand is in the
6134 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6135 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6136 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6137 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6138 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6139 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6140 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6142 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6144 TmpInst.addOperand(Inst.getOperand(1)); // lane
6145 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6146 TmpInst.addOperand(Inst.getOperand(6));
6151 case ARM::VST4LNdWB_register_Asm_8:
6152 case ARM::VST4LNdWB_register_Asm_16:
6153 case ARM::VST4LNdWB_register_Asm_32:
6154 case ARM::VST4LNqWB_register_Asm_16:
6155 case ARM::VST4LNqWB_register_Asm_32: {
6157 // Shuffle the operands around so the lane index operand is in the
6160 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6161 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6162 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6163 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6164 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6165 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6166 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6168 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6170 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6172 TmpInst.addOperand(Inst.getOperand(1)); // lane
6173 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6174 TmpInst.addOperand(Inst.getOperand(6));
6179 case ARM::VST1LNdWB_fixed_Asm_8:
6180 case ARM::VST1LNdWB_fixed_Asm_16:
6181 case ARM::VST1LNdWB_fixed_Asm_32: {
6183 // Shuffle the operands around so the lane index operand is in the
6186 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6187 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6188 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6189 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6190 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6191 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6192 TmpInst.addOperand(Inst.getOperand(1)); // lane
6193 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6194 TmpInst.addOperand(Inst.getOperand(5));
6199 case ARM::VST2LNdWB_fixed_Asm_8:
6200 case ARM::VST2LNdWB_fixed_Asm_16:
6201 case ARM::VST2LNdWB_fixed_Asm_32:
6202 case ARM::VST2LNqWB_fixed_Asm_16:
6203 case ARM::VST2LNqWB_fixed_Asm_32: {
6205 // Shuffle the operands around so the lane index operand is in the
6208 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6209 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6210 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6211 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6212 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6213 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6214 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6216 TmpInst.addOperand(Inst.getOperand(1)); // lane
6217 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6218 TmpInst.addOperand(Inst.getOperand(5));
6223 case ARM::VST3LNdWB_fixed_Asm_8:
6224 case ARM::VST3LNdWB_fixed_Asm_16:
6225 case ARM::VST3LNdWB_fixed_Asm_32:
6226 case ARM::VST3LNqWB_fixed_Asm_16:
6227 case ARM::VST3LNqWB_fixed_Asm_32: {
6229 // Shuffle the operands around so the lane index operand is in the
6232 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6233 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6234 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6235 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6236 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6237 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6238 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6240 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6242 TmpInst.addOperand(Inst.getOperand(1)); // lane
6243 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6244 TmpInst.addOperand(Inst.getOperand(5));
6249 case ARM::VST4LNdWB_fixed_Asm_8:
6250 case ARM::VST4LNdWB_fixed_Asm_16:
6251 case ARM::VST4LNdWB_fixed_Asm_32:
6252 case ARM::VST4LNqWB_fixed_Asm_16:
6253 case ARM::VST4LNqWB_fixed_Asm_32: {
6255 // Shuffle the operands around so the lane index operand is in the
6258 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6259 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6260 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6261 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6262 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6263 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6264 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6266 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6268 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6270 TmpInst.addOperand(Inst.getOperand(1)); // lane
6271 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6272 TmpInst.addOperand(Inst.getOperand(5));
6277 case ARM::VST1LNdAsm_8:
6278 case ARM::VST1LNdAsm_16:
6279 case ARM::VST1LNdAsm_32: {
6281 // Shuffle the operands around so the lane index operand is in the
6284 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6285 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6286 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6287 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6288 TmpInst.addOperand(Inst.getOperand(1)); // lane
6289 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6290 TmpInst.addOperand(Inst.getOperand(5));
6295 case ARM::VST2LNdAsm_8:
6296 case ARM::VST2LNdAsm_16:
6297 case ARM::VST2LNdAsm_32:
6298 case ARM::VST2LNqAsm_16:
6299 case ARM::VST2LNqAsm_32: {
6301 // Shuffle the operands around so the lane index operand is in the
6304 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6305 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6306 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6307 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6308 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6310 TmpInst.addOperand(Inst.getOperand(1)); // lane
6311 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6312 TmpInst.addOperand(Inst.getOperand(5));
6317 case ARM::VST3LNdAsm_8:
6318 case ARM::VST3LNdAsm_16:
6319 case ARM::VST3LNdAsm_32:
6320 case ARM::VST3LNqAsm_16:
6321 case ARM::VST3LNqAsm_32: {
6323 // Shuffle the operands around so the lane index operand is in the
6326 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6327 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6328 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6329 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6330 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6332 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6334 TmpInst.addOperand(Inst.getOperand(1)); // lane
6335 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6336 TmpInst.addOperand(Inst.getOperand(5));
6341 case ARM::VST4LNdAsm_8:
6342 case ARM::VST4LNdAsm_16:
6343 case ARM::VST4LNdAsm_32:
6344 case ARM::VST4LNqAsm_16:
6345 case ARM::VST4LNqAsm_32: {
6347 // Shuffle the operands around so the lane index operand is in the
6350 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6351 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6352 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6353 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6354 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6356 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6358 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6360 TmpInst.addOperand(Inst.getOperand(1)); // lane
6361 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6362 TmpInst.addOperand(Inst.getOperand(5));
6367 // Handle NEON VLD complex aliases.
6368 case ARM::VLD1LNdWB_register_Asm_8:
6369 case ARM::VLD1LNdWB_register_Asm_16:
6370 case ARM::VLD1LNdWB_register_Asm_32: {
6372 // Shuffle the operands around so the lane index operand is in the
6375 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6376 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6377 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6378 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6379 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6380 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6381 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6382 TmpInst.addOperand(Inst.getOperand(1)); // lane
6383 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6384 TmpInst.addOperand(Inst.getOperand(6));
6389 case ARM::VLD2LNdWB_register_Asm_8:
6390 case ARM::VLD2LNdWB_register_Asm_16:
6391 case ARM::VLD2LNdWB_register_Asm_32:
6392 case ARM::VLD2LNqWB_register_Asm_16:
6393 case ARM::VLD2LNqWB_register_Asm_32: {
6395 // Shuffle the operands around so the lane index operand is in the
6398 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6399 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6400 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6402 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6403 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6404 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6405 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6406 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6407 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6409 TmpInst.addOperand(Inst.getOperand(1)); // lane
6410 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6411 TmpInst.addOperand(Inst.getOperand(6));
6416 case ARM::VLD3LNdWB_register_Asm_8:
6417 case ARM::VLD3LNdWB_register_Asm_16:
6418 case ARM::VLD3LNdWB_register_Asm_32:
6419 case ARM::VLD3LNqWB_register_Asm_16:
6420 case ARM::VLD3LNqWB_register_Asm_32: {
6422 // Shuffle the operands around so the lane index operand is in the
6425 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6426 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6427 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6429 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6431 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6432 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6433 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6434 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6435 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6436 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6438 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6440 TmpInst.addOperand(Inst.getOperand(1)); // lane
6441 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6442 TmpInst.addOperand(Inst.getOperand(6));
6447 case ARM::VLD4LNdWB_register_Asm_8:
6448 case ARM::VLD4LNdWB_register_Asm_16:
6449 case ARM::VLD4LNdWB_register_Asm_32:
6450 case ARM::VLD4LNqWB_register_Asm_16:
6451 case ARM::VLD4LNqWB_register_Asm_32: {
6453 // Shuffle the operands around so the lane index operand is in the
6456 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6457 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6458 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6460 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6462 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6464 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6465 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6466 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6467 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6468 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6469 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6471 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6473 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6475 TmpInst.addOperand(Inst.getOperand(1)); // lane
6476 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6477 TmpInst.addOperand(Inst.getOperand(6));
6482 case ARM::VLD1LNdWB_fixed_Asm_8:
6483 case ARM::VLD1LNdWB_fixed_Asm_16:
6484 case ARM::VLD1LNdWB_fixed_Asm_32: {
6486 // Shuffle the operands around so the lane index operand is in the
6489 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6490 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6491 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6492 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6493 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6494 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6495 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6496 TmpInst.addOperand(Inst.getOperand(1)); // lane
6497 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6498 TmpInst.addOperand(Inst.getOperand(5));
6503 case ARM::VLD2LNdWB_fixed_Asm_8:
6504 case ARM::VLD2LNdWB_fixed_Asm_16:
6505 case ARM::VLD2LNdWB_fixed_Asm_32:
6506 case ARM::VLD2LNqWB_fixed_Asm_16:
6507 case ARM::VLD2LNqWB_fixed_Asm_32: {
6509 // Shuffle the operands around so the lane index operand is in the
6512 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6513 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6514 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6516 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6517 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6518 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6519 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6520 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6521 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6523 TmpInst.addOperand(Inst.getOperand(1)); // lane
6524 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6525 TmpInst.addOperand(Inst.getOperand(5));
6530 case ARM::VLD3LNdWB_fixed_Asm_8:
6531 case ARM::VLD3LNdWB_fixed_Asm_16:
6532 case ARM::VLD3LNdWB_fixed_Asm_32:
6533 case ARM::VLD3LNqWB_fixed_Asm_16:
6534 case ARM::VLD3LNqWB_fixed_Asm_32: {
6536 // Shuffle the operands around so the lane index operand is in the
6539 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6540 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6541 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6543 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6545 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6546 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6547 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6548 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6549 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6550 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6552 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6554 TmpInst.addOperand(Inst.getOperand(1)); // lane
6555 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6556 TmpInst.addOperand(Inst.getOperand(5));
6561 case ARM::VLD4LNdWB_fixed_Asm_8:
6562 case ARM::VLD4LNdWB_fixed_Asm_16:
6563 case ARM::VLD4LNdWB_fixed_Asm_32:
6564 case ARM::VLD4LNqWB_fixed_Asm_16:
6565 case ARM::VLD4LNqWB_fixed_Asm_32: {
6567 // Shuffle the operands around so the lane index operand is in the
6570 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6571 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6572 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6574 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6576 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6578 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6579 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6580 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6581 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6582 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6583 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6585 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6587 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6589 TmpInst.addOperand(Inst.getOperand(1)); // lane
6590 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6591 TmpInst.addOperand(Inst.getOperand(5));
6596 case ARM::VLD1LNdAsm_8:
6597 case ARM::VLD1LNdAsm_16:
6598 case ARM::VLD1LNdAsm_32: {
6600 // Shuffle the operands around so the lane index operand is in the
6603 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6604 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6605 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6606 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6607 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6608 TmpInst.addOperand(Inst.getOperand(1)); // lane
6609 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6610 TmpInst.addOperand(Inst.getOperand(5));
6615 case ARM::VLD2LNdAsm_8:
6616 case ARM::VLD2LNdAsm_16:
6617 case ARM::VLD2LNdAsm_32:
6618 case ARM::VLD2LNqAsm_16:
6619 case ARM::VLD2LNqAsm_32: {
6621 // Shuffle the operands around so the lane index operand is in the
6624 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6625 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6626 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6628 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6629 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6630 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6631 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6633 TmpInst.addOperand(Inst.getOperand(1)); // lane
6634 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6635 TmpInst.addOperand(Inst.getOperand(5));
6640 case ARM::VLD3LNdAsm_8:
6641 case ARM::VLD3LNdAsm_16:
6642 case ARM::VLD3LNdAsm_32:
6643 case ARM::VLD3LNqAsm_16:
6644 case ARM::VLD3LNqAsm_32: {
6646 // Shuffle the operands around so the lane index operand is in the
6649 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6650 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6651 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6653 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6655 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6656 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6657 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6658 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6660 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6662 TmpInst.addOperand(Inst.getOperand(1)); // lane
6663 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6664 TmpInst.addOperand(Inst.getOperand(5));
6669 case ARM::VLD4LNdAsm_8:
6670 case ARM::VLD4LNdAsm_16:
6671 case ARM::VLD4LNdAsm_32:
6672 case ARM::VLD4LNqAsm_16:
6673 case ARM::VLD4LNqAsm_32: {
6675 // Shuffle the operands around so the lane index operand is in the
6678 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6679 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6680 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6682 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6684 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6686 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6687 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6688 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6689 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6691 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6693 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6695 TmpInst.addOperand(Inst.getOperand(1)); // lane
6696 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6697 TmpInst.addOperand(Inst.getOperand(5));
6702 // VLD3DUP single 3-element structure to all lanes instructions.
6703 case ARM::VLD3DUPdAsm_8:
6704 case ARM::VLD3DUPdAsm_16:
6705 case ARM::VLD3DUPdAsm_32:
6706 case ARM::VLD3DUPqAsm_8:
6707 case ARM::VLD3DUPqAsm_16:
6708 case ARM::VLD3DUPqAsm_32: {
6711 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6712 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6713 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6715 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6717 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6718 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6719 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6720 TmpInst.addOperand(Inst.getOperand(4));
6725 case ARM::VLD3DUPdWB_fixed_Asm_8:
6726 case ARM::VLD3DUPdWB_fixed_Asm_16:
6727 case ARM::VLD3DUPdWB_fixed_Asm_32:
6728 case ARM::VLD3DUPqWB_fixed_Asm_8:
6729 case ARM::VLD3DUPqWB_fixed_Asm_16:
6730 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6733 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6734 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6735 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6737 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6739 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6740 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6741 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6742 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6743 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6744 TmpInst.addOperand(Inst.getOperand(4));
6749 case ARM::VLD3DUPdWB_register_Asm_8:
6750 case ARM::VLD3DUPdWB_register_Asm_16:
6751 case ARM::VLD3DUPdWB_register_Asm_32:
6752 case ARM::VLD3DUPqWB_register_Asm_8:
6753 case ARM::VLD3DUPqWB_register_Asm_16:
6754 case ARM::VLD3DUPqWB_register_Asm_32: {
6757 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6758 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6759 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6761 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6763 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6764 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6765 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6766 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6767 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6768 TmpInst.addOperand(Inst.getOperand(5));
6773 // VLD3 multiple 3-element structure instructions.
6774 case ARM::VLD3dAsm_8:
6775 case ARM::VLD3dAsm_16:
6776 case ARM::VLD3dAsm_32:
6777 case ARM::VLD3qAsm_8:
6778 case ARM::VLD3qAsm_16:
6779 case ARM::VLD3qAsm_32: {
6782 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6783 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6784 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6786 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6788 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6789 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6790 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6791 TmpInst.addOperand(Inst.getOperand(4));
6796 case ARM::VLD3dWB_fixed_Asm_8:
6797 case ARM::VLD3dWB_fixed_Asm_16:
6798 case ARM::VLD3dWB_fixed_Asm_32:
6799 case ARM::VLD3qWB_fixed_Asm_8:
6800 case ARM::VLD3qWB_fixed_Asm_16:
6801 case ARM::VLD3qWB_fixed_Asm_32: {
6804 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6805 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6806 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6808 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6810 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6811 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6812 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6813 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6814 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6815 TmpInst.addOperand(Inst.getOperand(4));
6820 case ARM::VLD3dWB_register_Asm_8:
6821 case ARM::VLD3dWB_register_Asm_16:
6822 case ARM::VLD3dWB_register_Asm_32:
6823 case ARM::VLD3qWB_register_Asm_8:
6824 case ARM::VLD3qWB_register_Asm_16:
6825 case ARM::VLD3qWB_register_Asm_32: {
6828 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6829 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6830 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6832 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6834 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6835 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6836 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6837 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6838 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6839 TmpInst.addOperand(Inst.getOperand(5));
6844 // VLD4DUP single 3-element structure to all lanes instructions.
6845 case ARM::VLD4DUPdAsm_8:
6846 case ARM::VLD4DUPdAsm_16:
6847 case ARM::VLD4DUPdAsm_32:
6848 case ARM::VLD4DUPqAsm_8:
6849 case ARM::VLD4DUPqAsm_16:
6850 case ARM::VLD4DUPqAsm_32: {
6853 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6854 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6855 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6857 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6859 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6861 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6862 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6863 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6864 TmpInst.addOperand(Inst.getOperand(4));
6869 case ARM::VLD4DUPdWB_fixed_Asm_8:
6870 case ARM::VLD4DUPdWB_fixed_Asm_16:
6871 case ARM::VLD4DUPdWB_fixed_Asm_32:
6872 case ARM::VLD4DUPqWB_fixed_Asm_8:
6873 case ARM::VLD4DUPqWB_fixed_Asm_16:
6874 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6877 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6878 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6879 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6881 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6883 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6885 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6886 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6887 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6888 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6889 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6890 TmpInst.addOperand(Inst.getOperand(4));
6895 case ARM::VLD4DUPdWB_register_Asm_8:
6896 case ARM::VLD4DUPdWB_register_Asm_16:
6897 case ARM::VLD4DUPdWB_register_Asm_32:
6898 case ARM::VLD4DUPqWB_register_Asm_8:
6899 case ARM::VLD4DUPqWB_register_Asm_16:
6900 case ARM::VLD4DUPqWB_register_Asm_32: {
6903 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6904 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6905 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6907 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6909 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6911 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6912 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6913 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6914 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6915 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6916 TmpInst.addOperand(Inst.getOperand(5));
6921 // VLD4 multiple 4-element structure instructions.
6922 case ARM::VLD4dAsm_8:
6923 case ARM::VLD4dAsm_16:
6924 case ARM::VLD4dAsm_32:
6925 case ARM::VLD4qAsm_8:
6926 case ARM::VLD4qAsm_16:
6927 case ARM::VLD4qAsm_32: {
6930 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6931 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6932 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6934 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6936 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6938 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6939 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6940 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6941 TmpInst.addOperand(Inst.getOperand(4));
6946 case ARM::VLD4dWB_fixed_Asm_8:
6947 case ARM::VLD4dWB_fixed_Asm_16:
6948 case ARM::VLD4dWB_fixed_Asm_32:
6949 case ARM::VLD4qWB_fixed_Asm_8:
6950 case ARM::VLD4qWB_fixed_Asm_16:
6951 case ARM::VLD4qWB_fixed_Asm_32: {
6954 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6955 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6956 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6958 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6960 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6962 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6963 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6964 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6965 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6966 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6967 TmpInst.addOperand(Inst.getOperand(4));
6972 case ARM::VLD4dWB_register_Asm_8:
6973 case ARM::VLD4dWB_register_Asm_16:
6974 case ARM::VLD4dWB_register_Asm_32:
6975 case ARM::VLD4qWB_register_Asm_8:
6976 case ARM::VLD4qWB_register_Asm_16:
6977 case ARM::VLD4qWB_register_Asm_32: {
6980 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6981 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6982 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6984 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6986 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6988 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6989 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6990 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6991 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6992 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6993 TmpInst.addOperand(Inst.getOperand(5));
6998 // VST3 multiple 3-element structure instructions.
6999 case ARM::VST3dAsm_8:
7000 case ARM::VST3dAsm_16:
7001 case ARM::VST3dAsm_32:
7002 case ARM::VST3qAsm_8:
7003 case ARM::VST3qAsm_16:
7004 case ARM::VST3qAsm_32: {
7007 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7008 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7009 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7010 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7011 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7013 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7015 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7016 TmpInst.addOperand(Inst.getOperand(4));
7021 case ARM::VST3dWB_fixed_Asm_8:
7022 case ARM::VST3dWB_fixed_Asm_16:
7023 case ARM::VST3dWB_fixed_Asm_32:
7024 case ARM::VST3qWB_fixed_Asm_8:
7025 case ARM::VST3qWB_fixed_Asm_16:
7026 case ARM::VST3qWB_fixed_Asm_32: {
7029 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7030 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7031 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7032 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7033 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7034 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7035 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7037 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7039 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7040 TmpInst.addOperand(Inst.getOperand(4));
7045 case ARM::VST3dWB_register_Asm_8:
7046 case ARM::VST3dWB_register_Asm_16:
7047 case ARM::VST3dWB_register_Asm_32:
7048 case ARM::VST3qWB_register_Asm_8:
7049 case ARM::VST3qWB_register_Asm_16:
7050 case ARM::VST3qWB_register_Asm_32: {
7053 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7054 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7055 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7056 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7057 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7058 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7059 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7061 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7063 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7064 TmpInst.addOperand(Inst.getOperand(5));
7069 // VST4 multiple 3-element structure instructions.
7070 case ARM::VST4dAsm_8:
7071 case ARM::VST4dAsm_16:
7072 case ARM::VST4dAsm_32:
7073 case ARM::VST4qAsm_8:
7074 case ARM::VST4qAsm_16:
7075 case ARM::VST4qAsm_32: {
7078 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7079 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7080 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7081 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7082 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7084 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7086 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7088 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7089 TmpInst.addOperand(Inst.getOperand(4));
7094 case ARM::VST4dWB_fixed_Asm_8:
7095 case ARM::VST4dWB_fixed_Asm_16:
7096 case ARM::VST4dWB_fixed_Asm_32:
7097 case ARM::VST4qWB_fixed_Asm_8:
7098 case ARM::VST4qWB_fixed_Asm_16:
7099 case ARM::VST4qWB_fixed_Asm_32: {
7102 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7103 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7104 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7105 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7106 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7107 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7108 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7110 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7112 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7114 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7115 TmpInst.addOperand(Inst.getOperand(4));
7120 case ARM::VST4dWB_register_Asm_8:
7121 case ARM::VST4dWB_register_Asm_16:
7122 case ARM::VST4dWB_register_Asm_32:
7123 case ARM::VST4qWB_register_Asm_8:
7124 case ARM::VST4qWB_register_Asm_16:
7125 case ARM::VST4qWB_register_Asm_32: {
7128 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7129 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7130 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7131 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7132 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7133 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7134 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7136 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7138 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7140 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7141 TmpInst.addOperand(Inst.getOperand(5));
7146 // Handle encoding choice for the shift-immediate instructions.
7149 case ARM::t2ASRri: {
7150 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7151 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7152 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7153 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7154 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7156 switch (Inst.getOpcode()) {
7157 default: llvm_unreachable("unexpected opcode");
7158 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7159 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7160 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7162 // The Thumb1 operands aren't in the same order. Awesome, eh?
7164 TmpInst.setOpcode(NewOpc);
7165 TmpInst.addOperand(Inst.getOperand(0));
7166 TmpInst.addOperand(Inst.getOperand(5));
7167 TmpInst.addOperand(Inst.getOperand(1));
7168 TmpInst.addOperand(Inst.getOperand(2));
7169 TmpInst.addOperand(Inst.getOperand(3));
7170 TmpInst.addOperand(Inst.getOperand(4));
7177 // Handle the Thumb2 mode MOV complex aliases.
7179 case ARM::t2MOVSsr: {
7180 // Which instruction to expand to depends on the CCOut operand and
7181 // whether we're in an IT block if the register operands are low
7183 bool isNarrow = false;
7184 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7185 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7186 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7187 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7188 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7192 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7193 default: llvm_unreachable("unexpected opcode!");
7194 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7195 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7196 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7197 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7199 TmpInst.setOpcode(newOpc);
7200 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7202 TmpInst.addOperand(MCOperand::CreateReg(
7203 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7204 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7205 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7206 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7207 TmpInst.addOperand(Inst.getOperand(5));
7209 TmpInst.addOperand(MCOperand::CreateReg(
7210 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7215 case ARM::t2MOVSsi: {
7216 // Which instruction to expand to depends on the CCOut operand and
7217 // whether we're in an IT block if the register operands are low
7219 bool isNarrow = false;
7220 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7221 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7222 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7226 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7227 default: llvm_unreachable("unexpected opcode!");
7228 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7229 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7230 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7231 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7232 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7234 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7235 if (Amount == 32) Amount = 0;
7236 TmpInst.setOpcode(newOpc);
7237 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7239 TmpInst.addOperand(MCOperand::CreateReg(
7240 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7241 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7242 if (newOpc != ARM::t2RRX)
7243 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7244 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7245 TmpInst.addOperand(Inst.getOperand(4));
7247 TmpInst.addOperand(MCOperand::CreateReg(
7248 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7252 // Handle the ARM mode MOV complex aliases.
7257 ARM_AM::ShiftOpc ShiftTy;
7258 switch(Inst.getOpcode()) {
7259 default: llvm_unreachable("unexpected opcode!");
7260 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7261 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7262 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7263 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7265 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7267 TmpInst.setOpcode(ARM::MOVsr);
7268 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7269 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7270 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7271 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7272 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7273 TmpInst.addOperand(Inst.getOperand(4));
7274 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7282 ARM_AM::ShiftOpc ShiftTy;
7283 switch(Inst.getOpcode()) {
7284 default: llvm_unreachable("unexpected opcode!");
7285 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7286 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7287 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7288 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7290 // A shift by zero is a plain MOVr, not a MOVsi.
7291 unsigned Amt = Inst.getOperand(2).getImm();
7292 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7293 // A shift by 32 should be encoded as 0 when permitted
7294 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7296 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7298 TmpInst.setOpcode(Opc);
7299 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7300 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7301 if (Opc == ARM::MOVsi)
7302 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7303 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7304 TmpInst.addOperand(Inst.getOperand(4));
7305 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7310 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7312 TmpInst.setOpcode(ARM::MOVsi);
7313 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7314 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7315 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7316 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7317 TmpInst.addOperand(Inst.getOperand(3));
7318 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7322 case ARM::t2LDMIA_UPD: {
7323 // If this is a load of a single register, then we should use
7324 // a post-indexed LDR instruction instead, per the ARM ARM.
7325 if (Inst.getNumOperands() != 5)
7328 TmpInst.setOpcode(ARM::t2LDR_POST);
7329 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7330 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7331 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7332 TmpInst.addOperand(MCOperand::CreateImm(4));
7333 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7334 TmpInst.addOperand(Inst.getOperand(3));
7338 case ARM::t2STMDB_UPD: {
7339 // If this is a store of a single register, then we should use
7340 // a pre-indexed STR instruction instead, per the ARM ARM.
7341 if (Inst.getNumOperands() != 5)
7344 TmpInst.setOpcode(ARM::t2STR_PRE);
7345 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7346 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7347 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7348 TmpInst.addOperand(MCOperand::CreateImm(-4));
7349 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7350 TmpInst.addOperand(Inst.getOperand(3));
7354 case ARM::LDMIA_UPD:
7355 // If this is a load of a single register via a 'pop', then we should use
7356 // a post-indexed LDR instruction instead, per the ARM ARM.
7357 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7358 Inst.getNumOperands() == 5) {
7360 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7361 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7362 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7363 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7364 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7365 TmpInst.addOperand(MCOperand::CreateImm(4));
7366 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7367 TmpInst.addOperand(Inst.getOperand(3));
7372 case ARM::STMDB_UPD:
7373 // If this is a store of a single register via a 'push', then we should use
7374 // a pre-indexed STR instruction instead, per the ARM ARM.
7375 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7376 Inst.getNumOperands() == 5) {
7378 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7379 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7380 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7381 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7382 TmpInst.addOperand(MCOperand::CreateImm(-4));
7383 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7384 TmpInst.addOperand(Inst.getOperand(3));
7388 case ARM::t2ADDri12:
7389 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7390 // mnemonic was used (not "addw"), encoding T3 is preferred.
7391 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7392 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7394 Inst.setOpcode(ARM::t2ADDri);
7395 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7397 case ARM::t2SUBri12:
7398 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7399 // mnemonic was used (not "subw"), encoding T3 is preferred.
7400 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7401 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7403 Inst.setOpcode(ARM::t2SUBri);
7404 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7407 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7408 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7409 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7410 // to encoding T1 if <Rd> is omitted."
7411 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7412 Inst.setOpcode(ARM::tADDi3);
7417 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7418 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7419 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7420 // to encoding T1 if <Rd> is omitted."
7421 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7422 Inst.setOpcode(ARM::tSUBi3);
7427 case ARM::t2SUBri: {
7428 // If the destination and first source operand are the same, and
7429 // the flags are compatible with the current IT status, use encoding T2
7430 // instead of T3. For compatibility with the system 'as'. Make sure the
7431 // wide encoding wasn't explicit.
7432 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7433 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7434 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7435 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7436 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7437 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7438 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7441 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7442 ARM::tADDi8 : ARM::tSUBi8);
7443 TmpInst.addOperand(Inst.getOperand(0));
7444 TmpInst.addOperand(Inst.getOperand(5));
7445 TmpInst.addOperand(Inst.getOperand(0));
7446 TmpInst.addOperand(Inst.getOperand(2));
7447 TmpInst.addOperand(Inst.getOperand(3));
7448 TmpInst.addOperand(Inst.getOperand(4));
7452 case ARM::t2ADDrr: {
7453 // If the destination and first source operand are the same, and
7454 // there's no setting of the flags, use encoding T2 instead of T3.
7455 // Note that this is only for ADD, not SUB. This mirrors the system
7456 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7457 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7458 Inst.getOperand(5).getReg() != 0 ||
7459 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7460 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7463 TmpInst.setOpcode(ARM::tADDhirr);
7464 TmpInst.addOperand(Inst.getOperand(0));
7465 TmpInst.addOperand(Inst.getOperand(0));
7466 TmpInst.addOperand(Inst.getOperand(2));
7467 TmpInst.addOperand(Inst.getOperand(3));
7468 TmpInst.addOperand(Inst.getOperand(4));
7472 case ARM::tADDrSP: {
7473 // If the non-SP source operand and the destination operand are not the
7474 // same, we need to use the 32-bit encoding if it's available.
7475 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7476 Inst.setOpcode(ARM::t2ADDrr);
7477 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7483 // A Thumb conditional branch outside of an IT block is a tBcc.
7484 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7485 Inst.setOpcode(ARM::tBcc);
7490 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7491 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7492 Inst.setOpcode(ARM::t2Bcc);
7497 // If the conditional is AL or we're in an IT block, we really want t2B.
7498 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7499 Inst.setOpcode(ARM::t2B);
7504 // If the conditional is AL, we really want tB.
7505 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7506 Inst.setOpcode(ARM::tB);
7511 // If the register list contains any high registers, or if the writeback
7512 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7513 // instead if we're in Thumb2. Otherwise, this should have generated
7514 // an error in validateInstruction().
7515 unsigned Rn = Inst.getOperand(0).getReg();
7516 bool hasWritebackToken =
7517 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7518 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7519 bool listContainsBase;
7520 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7521 (!listContainsBase && !hasWritebackToken) ||
7522 (listContainsBase && hasWritebackToken)) {
7523 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7524 assert (isThumbTwo());
7525 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7526 // If we're switching to the updating version, we need to insert
7527 // the writeback tied operand.
7528 if (hasWritebackToken)
7529 Inst.insert(Inst.begin(),
7530 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7535 case ARM::tSTMIA_UPD: {
7536 // If the register list contains any high registers, we need to use
7537 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7538 // should have generated an error in validateInstruction().
7539 unsigned Rn = Inst.getOperand(0).getReg();
7540 bool listContainsBase;
7541 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7542 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7543 assert (isThumbTwo());
7544 Inst.setOpcode(ARM::t2STMIA_UPD);
7550 bool listContainsBase;
7551 // If the register list contains any high registers, we need to use
7552 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7553 // should have generated an error in validateInstruction().
7554 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7556 assert (isThumbTwo());
7557 Inst.setOpcode(ARM::t2LDMIA_UPD);
7558 // Add the base register and writeback operands.
7559 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7560 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7564 bool listContainsBase;
7565 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7567 assert (isThumbTwo());
7568 Inst.setOpcode(ARM::t2STMDB_UPD);
7569 // Add the base register and writeback operands.
7570 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7571 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7575 // If we can use the 16-bit encoding and the user didn't explicitly
7576 // request the 32-bit variant, transform it here.
7577 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7578 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7579 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7580 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7581 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7582 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7583 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7584 // The operands aren't in the same order for tMOVi8...
7586 TmpInst.setOpcode(ARM::tMOVi8);
7587 TmpInst.addOperand(Inst.getOperand(0));
7588 TmpInst.addOperand(Inst.getOperand(4));
7589 TmpInst.addOperand(Inst.getOperand(1));
7590 TmpInst.addOperand(Inst.getOperand(2));
7591 TmpInst.addOperand(Inst.getOperand(3));
7598 // If we can use the 16-bit encoding and the user didn't explicitly
7599 // request the 32-bit variant, transform it here.
7600 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7601 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7602 Inst.getOperand(2).getImm() == ARMCC::AL &&
7603 Inst.getOperand(4).getReg() == ARM::CPSR &&
7604 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7605 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7606 // The operands aren't the same for tMOV[S]r... (no cc_out)
7608 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7609 TmpInst.addOperand(Inst.getOperand(0));
7610 TmpInst.addOperand(Inst.getOperand(1));
7611 TmpInst.addOperand(Inst.getOperand(2));
7612 TmpInst.addOperand(Inst.getOperand(3));
7622 // If we can use the 16-bit encoding and the user didn't explicitly
7623 // request the 32-bit variant, transform it here.
7624 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7625 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7626 Inst.getOperand(2).getImm() == 0 &&
7627 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7628 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7630 switch (Inst.getOpcode()) {
7631 default: llvm_unreachable("Illegal opcode!");
7632 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7633 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7634 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7635 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7637 // The operands aren't the same for thumb1 (no rotate operand).
7639 TmpInst.setOpcode(NewOpc);
7640 TmpInst.addOperand(Inst.getOperand(0));
7641 TmpInst.addOperand(Inst.getOperand(1));
7642 TmpInst.addOperand(Inst.getOperand(3));
7643 TmpInst.addOperand(Inst.getOperand(4));
7650 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7651 // rrx shifts and asr/lsr of #32 is encoded as 0
7652 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7654 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7655 // Shifting by zero is accepted as a vanilla 'MOVr'
7657 TmpInst.setOpcode(ARM::MOVr);
7658 TmpInst.addOperand(Inst.getOperand(0));
7659 TmpInst.addOperand(Inst.getOperand(1));
7660 TmpInst.addOperand(Inst.getOperand(3));
7661 TmpInst.addOperand(Inst.getOperand(4));
7662 TmpInst.addOperand(Inst.getOperand(5));
7675 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7676 if (SOpc == ARM_AM::rrx) return false;
7677 switch (Inst.getOpcode()) {
7678 default: llvm_unreachable("unexpected opcode!");
7679 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7680 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7681 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7682 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7683 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7684 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7686 // If the shift is by zero, use the non-shifted instruction definition.
7687 // The exception is for right shifts, where 0 == 32
7688 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7689 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7691 TmpInst.setOpcode(newOpc);
7692 TmpInst.addOperand(Inst.getOperand(0));
7693 TmpInst.addOperand(Inst.getOperand(1));
7694 TmpInst.addOperand(Inst.getOperand(2));
7695 TmpInst.addOperand(Inst.getOperand(4));
7696 TmpInst.addOperand(Inst.getOperand(5));
7697 TmpInst.addOperand(Inst.getOperand(6));
7705 // The mask bits for all but the first condition are represented as
7706 // the low bit of the condition code value implies 't'. We currently
7707 // always have 1 implies 't', so XOR toggle the bits if the low bit
7708 // of the condition code is zero.
7709 MCOperand &MO = Inst.getOperand(1);
7710 unsigned Mask = MO.getImm();
7711 unsigned OrigMask = Mask;
7712 unsigned TZ = countTrailingZeros(Mask);
7713 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7714 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7715 Mask ^= (0xE << TZ) & 0xF;
7719 // Set up the IT block state according to the IT instruction we just
7721 assert(!inITBlock() && "nested IT blocks?!");
7722 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7723 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7724 ITState.CurPosition = 0;
7725 ITState.FirstCond = true;
7735 // Assemblers should use the narrow encodings of these instructions when permissible.
7736 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7737 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7738 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7739 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7740 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7741 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7742 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7744 switch (Inst.getOpcode()) {
7745 default: llvm_unreachable("unexpected opcode");
7746 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7747 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7748 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7749 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7750 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7751 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7754 TmpInst.setOpcode(NewOpc);
7755 TmpInst.addOperand(Inst.getOperand(0));
7756 TmpInst.addOperand(Inst.getOperand(5));
7757 TmpInst.addOperand(Inst.getOperand(1));
7758 TmpInst.addOperand(Inst.getOperand(2));
7759 TmpInst.addOperand(Inst.getOperand(3));
7760 TmpInst.addOperand(Inst.getOperand(4));
7771 // Assemblers should use the narrow encodings of these instructions when permissible.
7772 // These instructions are special in that they are commutable, so shorter encodings
7773 // are available more often.
7774 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7775 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7776 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7777 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7778 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7779 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7780 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7781 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7783 switch (Inst.getOpcode()) {
7784 default: llvm_unreachable("unexpected opcode");
7785 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7786 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7787 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7788 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7791 TmpInst.setOpcode(NewOpc);
7792 TmpInst.addOperand(Inst.getOperand(0));
7793 TmpInst.addOperand(Inst.getOperand(5));
7794 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7795 TmpInst.addOperand(Inst.getOperand(1));
7796 TmpInst.addOperand(Inst.getOperand(2));
7798 TmpInst.addOperand(Inst.getOperand(2));
7799 TmpInst.addOperand(Inst.getOperand(1));
7801 TmpInst.addOperand(Inst.getOperand(3));
7802 TmpInst.addOperand(Inst.getOperand(4));
7812 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7813 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7814 // suffix depending on whether they're in an IT block or not.
7815 unsigned Opc = Inst.getOpcode();
7816 const MCInstrDesc &MCID = MII.get(Opc);
7817 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7818 assert(MCID.hasOptionalDef() &&
7819 "optionally flag setting instruction missing optional def operand");
7820 assert(MCID.NumOperands == Inst.getNumOperands() &&
7821 "operand count mismatch!");
7822 // Find the optional-def operand (cc_out).
7825 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7828 // If we're parsing Thumb1, reject it completely.
7829 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7830 return Match_MnemonicFail;
7831 // If we're parsing Thumb2, which form is legal depends on whether we're
7833 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7835 return Match_RequiresITBlock;
7836 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7838 return Match_RequiresNotITBlock;
7840 // Some high-register supporting Thumb1 encodings only allow both registers
7841 // to be from r0-r7 when in Thumb2.
7842 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7843 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7844 isARMLowRegister(Inst.getOperand(2).getReg()))
7845 return Match_RequiresThumb2;
7846 // Others only require ARMv6 or later.
7847 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7848 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7849 isARMLowRegister(Inst.getOperand(1).getReg()))
7850 return Match_RequiresV6;
7851 return Match_Success;
7854 template<> inline bool IsCPSRDead<MCInst>(MCInst* Instr) {
7855 return true; // In an assembly source, no need to second-guess
7858 static const char *getSubtargetFeatureName(unsigned Val);
7860 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7861 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7862 MCStreamer &Out, unsigned &ErrorInfo,
7863 bool MatchingInlineAsm) {
7865 unsigned MatchResult;
7867 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7869 switch (MatchResult) {
7872 // Context sensitive operand constraints aren't handled by the matcher,
7873 // so check them here.
7874 if (validateInstruction(Inst, Operands)) {
7875 // Still progress the IT block, otherwise one wrong condition causes
7876 // nasty cascading errors.
7877 forwardITPosition();
7881 { // processInstruction() updates inITBlock state, we need to save it away
7882 bool wasInITBlock = inITBlock();
7884 // Some instructions need post-processing to, for example, tweak which
7885 // encoding is selected. Loop on it while changes happen so the
7886 // individual transformations can chain off each other. E.g.,
7887 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7888 while (processInstruction(Inst, Operands))
7891 // Only after the instruction is fully processed, we can validate it
7892 if (wasInITBlock && hasV8Ops() && isThumb() &&
7893 !isV8EligibleForIT(&Inst)) {
7894 Warning(IDLoc, "deprecated instruction in IT block");
7898 // Only move forward at the very end so that everything in validate
7899 // and process gets a consistent answer about whether we're in an IT
7901 forwardITPosition();
7903 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7904 // doesn't actually encode.
7905 if (Inst.getOpcode() == ARM::ITasm)
7909 Out.EmitInstruction(Inst, STI);
7911 case Match_MissingFeature: {
7912 assert(ErrorInfo && "Unknown missing feature!");
7913 // Special case the error message for the very common case where only
7914 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7915 std::string Msg = "instruction requires:";
7917 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7918 if (ErrorInfo & Mask) {
7920 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7924 return Error(IDLoc, Msg);
7926 case Match_InvalidOperand: {
7927 SMLoc ErrorLoc = IDLoc;
7928 if (ErrorInfo != ~0U) {
7929 if (ErrorInfo >= Operands.size())
7930 return Error(IDLoc, "too few operands for instruction");
7932 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7933 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7936 return Error(ErrorLoc, "invalid operand for instruction");
7938 case Match_MnemonicFail:
7939 return Error(IDLoc, "invalid instruction",
7940 ((ARMOperand*)Operands[0])->getLocRange());
7941 case Match_RequiresNotITBlock:
7942 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7943 case Match_RequiresITBlock:
7944 return Error(IDLoc, "instruction only valid inside IT block");
7945 case Match_RequiresV6:
7946 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7947 case Match_RequiresThumb2:
7948 return Error(IDLoc, "instruction variant requires Thumb2");
7949 case Match_ImmRange0_15: {
7950 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7951 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7952 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7954 case Match_ImmRange0_239: {
7955 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7956 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7957 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
7961 llvm_unreachable("Implement any new match types added!");
7964 /// parseDirective parses the arm specific directives
7965 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7966 StringRef IDVal = DirectiveID.getIdentifier();
7967 if (IDVal == ".word")
7968 return parseLiteralValues(4, DirectiveID.getLoc());
7969 else if (IDVal == ".short" || IDVal == ".hword")
7970 return parseLiteralValues(2, DirectiveID.getLoc());
7971 else if (IDVal == ".thumb")
7972 return parseDirectiveThumb(DirectiveID.getLoc());
7973 else if (IDVal == ".arm")
7974 return parseDirectiveARM(DirectiveID.getLoc());
7975 else if (IDVal == ".thumb_func")
7976 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7977 else if (IDVal == ".code")
7978 return parseDirectiveCode(DirectiveID.getLoc());
7979 else if (IDVal == ".syntax")
7980 return parseDirectiveSyntax(DirectiveID.getLoc());
7981 else if (IDVal == ".unreq")
7982 return parseDirectiveUnreq(DirectiveID.getLoc());
7983 else if (IDVal == ".arch")
7984 return parseDirectiveArch(DirectiveID.getLoc());
7985 else if (IDVal == ".eabi_attribute")
7986 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7987 else if (IDVal == ".cpu")
7988 return parseDirectiveCPU(DirectiveID.getLoc());
7989 else if (IDVal == ".fpu")
7990 return parseDirectiveFPU(DirectiveID.getLoc());
7991 else if (IDVal == ".fnstart")
7992 return parseDirectiveFnStart(DirectiveID.getLoc());
7993 else if (IDVal == ".fnend")
7994 return parseDirectiveFnEnd(DirectiveID.getLoc());
7995 else if (IDVal == ".cantunwind")
7996 return parseDirectiveCantUnwind(DirectiveID.getLoc());
7997 else if (IDVal == ".personality")
7998 return parseDirectivePersonality(DirectiveID.getLoc());
7999 else if (IDVal == ".handlerdata")
8000 return parseDirectiveHandlerData(DirectiveID.getLoc());
8001 else if (IDVal == ".setfp")
8002 return parseDirectiveSetFP(DirectiveID.getLoc());
8003 else if (IDVal == ".pad")
8004 return parseDirectivePad(DirectiveID.getLoc());
8005 else if (IDVal == ".save")
8006 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8007 else if (IDVal == ".vsave")
8008 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8009 else if (IDVal == ".inst")
8010 return parseDirectiveInst(DirectiveID.getLoc());
8011 else if (IDVal == ".inst.n")
8012 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8013 else if (IDVal == ".inst.w")
8014 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8015 else if (IDVal == ".ltorg" || IDVal == ".pool")
8016 return parseDirectiveLtorg(DirectiveID.getLoc());
8017 else if (IDVal == ".even")
8018 return parseDirectiveEven(DirectiveID.getLoc());
8019 else if (IDVal == ".personalityindex")
8020 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8021 else if (IDVal == ".unwind_raw")
8022 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8023 else if (IDVal == ".tlsdescseq")
8024 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8025 else if (IDVal == ".movsp")
8026 return parseDirectiveMovSP(DirectiveID.getLoc());
8027 else if (IDVal == ".object_arch")
8028 return parseDirectiveObjectArch(DirectiveID.getLoc());
8029 else if (IDVal == ".arch_extension")
8030 return parseDirectiveArchExtension(DirectiveID.getLoc());
8031 else if (IDVal == ".align")
8032 return parseDirectiveAlign(DirectiveID.getLoc());
8036 /// parseLiteralValues
8037 /// ::= .hword expression [, expression]*
8038 /// ::= .short expression [, expression]*
8039 /// ::= .word expression [, expression]*
8040 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8041 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8043 const MCExpr *Value;
8044 if (getParser().parseExpression(Value)) {
8045 Parser.eatToEndOfStatement();
8049 getParser().getStreamer().EmitValue(Value, Size);
8051 if (getLexer().is(AsmToken::EndOfStatement))
8054 // FIXME: Improve diagnostic.
8055 if (getLexer().isNot(AsmToken::Comma)) {
8056 Error(L, "unexpected token in directive");
8067 /// parseDirectiveThumb
8069 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8070 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8071 Error(L, "unexpected token in directive");
8077 Error(L, "target does not support Thumb mode");
8083 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8087 /// parseDirectiveARM
8089 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8090 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8091 Error(L, "unexpected token in directive");
8097 Error(L, "target does not support ARM mode");
8103 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8107 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8108 if (NextSymbolIsThumb) {
8109 getParser().getStreamer().EmitThumbFunc(Symbol);
8110 NextSymbolIsThumb = false;
8114 /// parseDirectiveThumbFunc
8115 /// ::= .thumbfunc symbol_name
8116 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8117 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8118 bool isMachO = MAI->hasSubsectionsViaSymbols();
8120 // Darwin asm has (optionally) function name after .thumb_func direction
8123 const AsmToken &Tok = Parser.getTok();
8124 if (Tok.isNot(AsmToken::EndOfStatement)) {
8125 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8126 Error(L, "unexpected token in .thumb_func directive");
8131 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8132 getParser().getStreamer().EmitThumbFunc(Func);
8133 Parser.Lex(); // Consume the identifier token.
8138 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8139 Error(L, "unexpected token in directive");
8143 NextSymbolIsThumb = true;
8147 /// parseDirectiveSyntax
8148 /// ::= .syntax unified | divided
8149 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8150 const AsmToken &Tok = Parser.getTok();
8151 if (Tok.isNot(AsmToken::Identifier)) {
8152 Error(L, "unexpected token in .syntax directive");
8156 StringRef Mode = Tok.getString();
8157 if (Mode == "unified" || Mode == "UNIFIED") {
8159 } else if (Mode == "divided" || Mode == "DIVIDED") {
8160 Error(L, "'.syntax divided' arm asssembly not supported");
8163 Error(L, "unrecognized syntax mode in .syntax directive");
8167 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8168 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8173 // TODO tell the MC streamer the mode
8174 // getParser().getStreamer().Emit???();
8178 /// parseDirectiveCode
8179 /// ::= .code 16 | 32
8180 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8181 const AsmToken &Tok = Parser.getTok();
8182 if (Tok.isNot(AsmToken::Integer)) {
8183 Error(L, "unexpected token in .code directive");
8186 int64_t Val = Parser.getTok().getIntVal();
8187 if (Val != 16 && Val != 32) {
8188 Error(L, "invalid operand to .code directive");
8193 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8194 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8201 Error(L, "target does not support Thumb mode");
8207 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8210 Error(L, "target does not support ARM mode");
8216 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8222 /// parseDirectiveReq
8223 /// ::= name .req registername
8224 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8225 Parser.Lex(); // Eat the '.req' token.
8227 SMLoc SRegLoc, ERegLoc;
8228 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8229 Parser.eatToEndOfStatement();
8230 Error(SRegLoc, "register name expected");
8234 // Shouldn't be anything else.
8235 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8236 Parser.eatToEndOfStatement();
8237 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8241 Parser.Lex(); // Consume the EndOfStatement
8243 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8244 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8251 /// parseDirectiveUneq
8252 /// ::= .unreq registername
8253 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8254 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8255 Parser.eatToEndOfStatement();
8256 Error(L, "unexpected input in .unreq directive.");
8259 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
8260 Parser.Lex(); // Eat the identifier.
8264 /// parseDirectiveArch
8266 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8267 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8269 unsigned ID = StringSwitch<unsigned>(Arch)
8270 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8271 .Case(NAME, ARM::ID)
8272 #define ARM_ARCH_ALIAS(NAME, ID) \
8273 .Case(NAME, ARM::ID)
8274 #include "MCTargetDesc/ARMArchName.def"
8275 .Default(ARM::INVALID_ARCH);
8277 if (ID == ARM::INVALID_ARCH) {
8278 Error(L, "Unknown arch name");
8282 getTargetStreamer().emitArch(ID);
8286 /// parseDirectiveEabiAttr
8287 /// ::= .eabi_attribute int, int [, "str"]
8288 /// ::= .eabi_attribute Tag_name, int [, "str"]
8289 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8293 TagLoc = Parser.getTok().getLoc();
8294 if (Parser.getTok().is(AsmToken::Identifier)) {
8295 StringRef Name = Parser.getTok().getIdentifier();
8296 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8298 Error(TagLoc, "attribute name not recognised: " + Name);
8299 Parser.eatToEndOfStatement();
8304 const MCExpr *AttrExpr;
8306 TagLoc = Parser.getTok().getLoc();
8307 if (Parser.parseExpression(AttrExpr)) {
8308 Parser.eatToEndOfStatement();
8312 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8314 Error(TagLoc, "expected numeric constant");
8315 Parser.eatToEndOfStatement();
8319 Tag = CE->getValue();
8322 if (Parser.getTok().isNot(AsmToken::Comma)) {
8323 Error(Parser.getTok().getLoc(), "comma expected");
8324 Parser.eatToEndOfStatement();
8327 Parser.Lex(); // skip comma
8329 StringRef StringValue = "";
8330 bool IsStringValue = false;
8332 int64_t IntegerValue = 0;
8333 bool IsIntegerValue = false;
8335 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8336 IsStringValue = true;
8337 else if (Tag == ARMBuildAttrs::compatibility) {
8338 IsStringValue = true;
8339 IsIntegerValue = true;
8340 } else if (Tag < 32 || Tag % 2 == 0)
8341 IsIntegerValue = true;
8342 else if (Tag % 2 == 1)
8343 IsStringValue = true;
8345 llvm_unreachable("invalid tag type");
8347 if (IsIntegerValue) {
8348 const MCExpr *ValueExpr;
8349 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8350 if (Parser.parseExpression(ValueExpr)) {
8351 Parser.eatToEndOfStatement();
8355 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8357 Error(ValueExprLoc, "expected numeric constant");
8358 Parser.eatToEndOfStatement();
8362 IntegerValue = CE->getValue();
8365 if (Tag == ARMBuildAttrs::compatibility) {
8366 if (Parser.getTok().isNot(AsmToken::Comma))
8367 IsStringValue = false;
8372 if (IsStringValue) {
8373 if (Parser.getTok().isNot(AsmToken::String)) {
8374 Error(Parser.getTok().getLoc(), "bad string constant");
8375 Parser.eatToEndOfStatement();
8379 StringValue = Parser.getTok().getStringContents();
8383 if (IsIntegerValue && IsStringValue) {
8384 assert(Tag == ARMBuildAttrs::compatibility);
8385 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8386 } else if (IsIntegerValue)
8387 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8388 else if (IsStringValue)
8389 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8393 /// parseDirectiveCPU
8395 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8396 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8397 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8401 /// parseDirectiveFPU
8403 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8404 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8406 unsigned ID = StringSwitch<unsigned>(FPU)
8407 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8408 #include "ARMFPUName.def"
8409 .Default(ARM::INVALID_FPU);
8411 if (ID == ARM::INVALID_FPU) {
8412 Error(L, "Unknown FPU name");
8416 getTargetStreamer().emitFPU(ID);
8420 /// parseDirectiveFnStart
8422 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8423 if (UC.hasFnStart()) {
8424 Error(L, ".fnstart starts before the end of previous one");
8425 UC.emitFnStartLocNotes();
8429 // Reset the unwind directives parser state
8432 getTargetStreamer().emitFnStart();
8434 UC.recordFnStart(L);
8438 /// parseDirectiveFnEnd
8440 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8441 // Check the ordering of unwind directives
8442 if (!UC.hasFnStart()) {
8443 Error(L, ".fnstart must precede .fnend directive");
8447 // Reset the unwind directives parser state
8448 getTargetStreamer().emitFnEnd();
8454 /// parseDirectiveCantUnwind
8456 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8457 UC.recordCantUnwind(L);
8459 // Check the ordering of unwind directives
8460 if (!UC.hasFnStart()) {
8461 Error(L, ".fnstart must precede .cantunwind directive");
8464 if (UC.hasHandlerData()) {
8465 Error(L, ".cantunwind can't be used with .handlerdata directive");
8466 UC.emitHandlerDataLocNotes();
8469 if (UC.hasPersonality()) {
8470 Error(L, ".cantunwind can't be used with .personality directive");
8471 UC.emitPersonalityLocNotes();
8475 getTargetStreamer().emitCantUnwind();
8479 /// parseDirectivePersonality
8480 /// ::= .personality name
8481 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8482 bool HasExistingPersonality = UC.hasPersonality();
8484 UC.recordPersonality(L);
8486 // Check the ordering of unwind directives
8487 if (!UC.hasFnStart()) {
8488 Error(L, ".fnstart must precede .personality directive");
8491 if (UC.cantUnwind()) {
8492 Error(L, ".personality can't be used with .cantunwind directive");
8493 UC.emitCantUnwindLocNotes();
8496 if (UC.hasHandlerData()) {
8497 Error(L, ".personality must precede .handlerdata directive");
8498 UC.emitHandlerDataLocNotes();
8501 if (HasExistingPersonality) {
8502 Parser.eatToEndOfStatement();
8503 Error(L, "multiple personality directives");
8504 UC.emitPersonalityLocNotes();
8508 // Parse the name of the personality routine
8509 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8510 Parser.eatToEndOfStatement();
8511 Error(L, "unexpected input in .personality directive.");
8514 StringRef Name(Parser.getTok().getIdentifier());
8517 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8518 getTargetStreamer().emitPersonality(PR);
8522 /// parseDirectiveHandlerData
8523 /// ::= .handlerdata
8524 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8525 UC.recordHandlerData(L);
8527 // Check the ordering of unwind directives
8528 if (!UC.hasFnStart()) {
8529 Error(L, ".fnstart must precede .personality directive");
8532 if (UC.cantUnwind()) {
8533 Error(L, ".handlerdata can't be used with .cantunwind directive");
8534 UC.emitCantUnwindLocNotes();
8538 getTargetStreamer().emitHandlerData();
8542 /// parseDirectiveSetFP
8543 /// ::= .setfp fpreg, spreg [, offset]
8544 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8545 // Check the ordering of unwind directives
8546 if (!UC.hasFnStart()) {
8547 Error(L, ".fnstart must precede .setfp directive");
8550 if (UC.hasHandlerData()) {
8551 Error(L, ".setfp must precede .handlerdata directive");
8556 SMLoc FPRegLoc = Parser.getTok().getLoc();
8557 int FPReg = tryParseRegister();
8559 Error(FPRegLoc, "frame pointer register expected");
8564 if (Parser.getTok().isNot(AsmToken::Comma)) {
8565 Error(Parser.getTok().getLoc(), "comma expected");
8568 Parser.Lex(); // skip comma
8571 SMLoc SPRegLoc = Parser.getTok().getLoc();
8572 int SPReg = tryParseRegister();
8574 Error(SPRegLoc, "stack pointer register expected");
8578 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8579 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8583 // Update the frame pointer register
8584 UC.saveFPReg(FPReg);
8588 if (Parser.getTok().is(AsmToken::Comma)) {
8589 Parser.Lex(); // skip comma
8591 if (Parser.getTok().isNot(AsmToken::Hash) &&
8592 Parser.getTok().isNot(AsmToken::Dollar)) {
8593 Error(Parser.getTok().getLoc(), "'#' expected");
8596 Parser.Lex(); // skip hash token.
8598 const MCExpr *OffsetExpr;
8599 SMLoc ExLoc = Parser.getTok().getLoc();
8601 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8602 Error(ExLoc, "malformed setfp offset");
8605 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8607 Error(ExLoc, "setfp offset must be an immediate");
8611 Offset = CE->getValue();
8614 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8615 static_cast<unsigned>(SPReg), Offset);
8621 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8622 // Check the ordering of unwind directives
8623 if (!UC.hasFnStart()) {
8624 Error(L, ".fnstart must precede .pad directive");
8627 if (UC.hasHandlerData()) {
8628 Error(L, ".pad must precede .handlerdata directive");
8633 if (Parser.getTok().isNot(AsmToken::Hash) &&
8634 Parser.getTok().isNot(AsmToken::Dollar)) {
8635 Error(Parser.getTok().getLoc(), "'#' expected");
8638 Parser.Lex(); // skip hash token.
8640 const MCExpr *OffsetExpr;
8641 SMLoc ExLoc = Parser.getTok().getLoc();
8643 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8644 Error(ExLoc, "malformed pad offset");
8647 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8649 Error(ExLoc, "pad offset must be an immediate");
8653 getTargetStreamer().emitPad(CE->getValue());
8657 /// parseDirectiveRegSave
8658 /// ::= .save { registers }
8659 /// ::= .vsave { registers }
8660 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8661 // Check the ordering of unwind directives
8662 if (!UC.hasFnStart()) {
8663 Error(L, ".fnstart must precede .save or .vsave directives");
8666 if (UC.hasHandlerData()) {
8667 Error(L, ".save or .vsave must precede .handlerdata directive");
8671 // RAII object to make sure parsed operands are deleted.
8672 struct CleanupObject {
8673 SmallVector<MCParsedAsmOperand *, 1> Operands;
8675 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8680 // Parse the register list
8681 if (parseRegisterList(CO.Operands))
8683 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8684 if (!IsVector && !Op->isRegList()) {
8685 Error(L, ".save expects GPR registers");
8688 if (IsVector && !Op->isDPRRegList()) {
8689 Error(L, ".vsave expects DPR registers");
8693 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8697 /// parseDirectiveInst
8698 /// ::= .inst opcode [, ...]
8699 /// ::= .inst.n opcode [, ...]
8700 /// ::= .inst.w opcode [, ...]
8701 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8713 Parser.eatToEndOfStatement();
8714 Error(Loc, "cannot determine Thumb instruction size, "
8715 "use inst.n/inst.w instead");
8720 Parser.eatToEndOfStatement();
8721 Error(Loc, "width suffixes are invalid in ARM mode");
8727 if (getLexer().is(AsmToken::EndOfStatement)) {
8728 Parser.eatToEndOfStatement();
8729 Error(Loc, "expected expression following directive");
8736 if (getParser().parseExpression(Expr)) {
8737 Error(Loc, "expected expression");
8741 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8743 Error(Loc, "expected constant expression");
8749 if (Value->getValue() > 0xffff) {
8750 Error(Loc, "inst.n operand is too big, use inst.w instead");
8755 if (Value->getValue() > 0xffffffff) {
8757 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8762 llvm_unreachable("only supported widths are 2 and 4");
8765 getTargetStreamer().emitInst(Value->getValue(), Suffix);
8767 if (getLexer().is(AsmToken::EndOfStatement))
8770 if (getLexer().isNot(AsmToken::Comma)) {
8771 Error(Loc, "unexpected token in directive");
8782 /// parseDirectiveLtorg
8783 /// ::= .ltorg | .pool
8784 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
8785 getTargetStreamer().emitCurrentConstantPool();
8789 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
8790 const MCSection *Section = getStreamer().getCurrentSection().first;
8792 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8793 TokError("unexpected token in directive");
8798 getStreamer().InitSections();
8799 Section = getStreamer().getCurrentSection().first;
8802 assert(Section && "must have section to emit alignment");
8803 if (Section->UseCodeAlign())
8804 getStreamer().EmitCodeAlignment(2);
8806 getStreamer().EmitValueToAlignment(2);
8811 /// parseDirectivePersonalityIndex
8812 /// ::= .personalityindex index
8813 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
8814 bool HasExistingPersonality = UC.hasPersonality();
8816 UC.recordPersonalityIndex(L);
8818 if (!UC.hasFnStart()) {
8819 Parser.eatToEndOfStatement();
8820 Error(L, ".fnstart must precede .personalityindex directive");
8823 if (UC.cantUnwind()) {
8824 Parser.eatToEndOfStatement();
8825 Error(L, ".personalityindex cannot be used with .cantunwind");
8826 UC.emitCantUnwindLocNotes();
8829 if (UC.hasHandlerData()) {
8830 Parser.eatToEndOfStatement();
8831 Error(L, ".personalityindex must precede .handlerdata directive");
8832 UC.emitHandlerDataLocNotes();
8835 if (HasExistingPersonality) {
8836 Parser.eatToEndOfStatement();
8837 Error(L, "multiple personality directives");
8838 UC.emitPersonalityLocNotes();
8842 const MCExpr *IndexExpression;
8843 SMLoc IndexLoc = Parser.getTok().getLoc();
8844 if (Parser.parseExpression(IndexExpression)) {
8845 Parser.eatToEndOfStatement();
8849 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
8851 Parser.eatToEndOfStatement();
8852 Error(IndexLoc, "index must be a constant number");
8855 if (CE->getValue() < 0 ||
8856 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
8857 Parser.eatToEndOfStatement();
8858 Error(IndexLoc, "personality routine index should be in range [0-3]");
8862 getTargetStreamer().emitPersonalityIndex(CE->getValue());
8866 /// parseDirectiveUnwindRaw
8867 /// ::= .unwind_raw offset, opcode [, opcode...]
8868 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
8869 if (!UC.hasFnStart()) {
8870 Parser.eatToEndOfStatement();
8871 Error(L, ".fnstart must precede .unwind_raw directives");
8875 int64_t StackOffset;
8877 const MCExpr *OffsetExpr;
8878 SMLoc OffsetLoc = getLexer().getLoc();
8879 if (getLexer().is(AsmToken::EndOfStatement) ||
8880 getParser().parseExpression(OffsetExpr)) {
8881 Error(OffsetLoc, "expected expression");
8882 Parser.eatToEndOfStatement();
8886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8888 Error(OffsetLoc, "offset must be a constant");
8889 Parser.eatToEndOfStatement();
8893 StackOffset = CE->getValue();
8895 if (getLexer().isNot(AsmToken::Comma)) {
8896 Error(getLexer().getLoc(), "expected comma");
8897 Parser.eatToEndOfStatement();
8902 SmallVector<uint8_t, 16> Opcodes;
8906 SMLoc OpcodeLoc = getLexer().getLoc();
8907 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
8908 Error(OpcodeLoc, "expected opcode expression");
8909 Parser.eatToEndOfStatement();
8913 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
8915 Error(OpcodeLoc, "opcode value must be a constant");
8916 Parser.eatToEndOfStatement();
8920 const int64_t Opcode = OC->getValue();
8921 if (Opcode & ~0xff) {
8922 Error(OpcodeLoc, "invalid opcode");
8923 Parser.eatToEndOfStatement();
8927 Opcodes.push_back(uint8_t(Opcode));
8929 if (getLexer().is(AsmToken::EndOfStatement))
8932 if (getLexer().isNot(AsmToken::Comma)) {
8933 Error(getLexer().getLoc(), "unexpected token in directive");
8934 Parser.eatToEndOfStatement();
8941 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
8947 /// parseDirectiveTLSDescSeq
8948 /// ::= .tlsdescseq tls-variable
8949 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
8950 if (getLexer().isNot(AsmToken::Identifier)) {
8951 TokError("expected variable after '.tlsdescseq' directive");
8952 Parser.eatToEndOfStatement();
8956 const MCSymbolRefExpr *SRE =
8957 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
8958 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
8961 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8962 Error(Parser.getTok().getLoc(), "unexpected token");
8963 Parser.eatToEndOfStatement();
8967 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
8971 /// parseDirectiveMovSP
8972 /// ::= .movsp reg [, #offset]
8973 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
8974 if (!UC.hasFnStart()) {
8975 Parser.eatToEndOfStatement();
8976 Error(L, ".fnstart must precede .movsp directives");
8979 if (UC.getFPReg() != ARM::SP) {
8980 Parser.eatToEndOfStatement();
8981 Error(L, "unexpected .movsp directive");
8985 SMLoc SPRegLoc = Parser.getTok().getLoc();
8986 int SPReg = tryParseRegister();
8988 Parser.eatToEndOfStatement();
8989 Error(SPRegLoc, "register expected");
8993 if (SPReg == ARM::SP || SPReg == ARM::PC) {
8994 Parser.eatToEndOfStatement();
8995 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9000 if (Parser.getTok().is(AsmToken::Comma)) {
9003 if (Parser.getTok().isNot(AsmToken::Hash)) {
9004 Error(Parser.getTok().getLoc(), "expected #constant");
9005 Parser.eatToEndOfStatement();
9010 const MCExpr *OffsetExpr;
9011 SMLoc OffsetLoc = Parser.getTok().getLoc();
9012 if (Parser.parseExpression(OffsetExpr)) {
9013 Parser.eatToEndOfStatement();
9014 Error(OffsetLoc, "malformed offset expression");
9018 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9020 Parser.eatToEndOfStatement();
9021 Error(OffsetLoc, "offset must be an immediate constant");
9025 Offset = CE->getValue();
9028 getTargetStreamer().emitMovSP(SPReg, Offset);
9029 UC.saveFPReg(SPReg);
9034 /// parseDirectiveObjectArch
9035 /// ::= .object_arch name
9036 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9037 if (getLexer().isNot(AsmToken::Identifier)) {
9038 Error(getLexer().getLoc(), "unexpected token");
9039 Parser.eatToEndOfStatement();
9043 StringRef Arch = Parser.getTok().getString();
9044 SMLoc ArchLoc = Parser.getTok().getLoc();
9047 unsigned ID = StringSwitch<unsigned>(Arch)
9048 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9049 .Case(NAME, ARM::ID)
9050 #define ARM_ARCH_ALIAS(NAME, ID) \
9051 .Case(NAME, ARM::ID)
9052 #include "MCTargetDesc/ARMArchName.def"
9053 #undef ARM_ARCH_NAME
9054 #undef ARM_ARCH_ALIAS
9055 .Default(ARM::INVALID_ARCH);
9057 if (ID == ARM::INVALID_ARCH) {
9058 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9059 Parser.eatToEndOfStatement();
9063 getTargetStreamer().emitObjectArch(ID);
9065 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9066 Error(getLexer().getLoc(), "unexpected token");
9067 Parser.eatToEndOfStatement();
9073 /// parseDirectiveAlign
9075 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9076 // NOTE: if this is not the end of the statement, fall back to the target
9077 // agnostic handling for this directive which will correctly handle this.
9078 if (getLexer().isNot(AsmToken::EndOfStatement))
9081 // '.align' is target specifically handled to mean 2**2 byte alignment.
9082 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9083 getStreamer().EmitCodeAlignment(4, 0);
9085 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9090 /// Force static initialization.
9091 extern "C" void LLVMInitializeARMAsmParser() {
9092 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
9093 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
9096 #define GET_REGISTER_MATCHER
9097 #define GET_SUBTARGET_FEATURE_NAME
9098 #define GET_MATCHER_IMPLEMENTATION
9099 #include "ARMGenAsmMatcher.inc"
9101 static const struct ExtMapEntry {
9102 const char *Extension;
9103 const unsigned ArchCheck;
9104 const uint64_t Features;
9106 { "crc", Feature_HasV8, ARM::FeatureCRC },
9107 { "crypto", Feature_HasV8,
9108 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9109 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9110 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9111 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9112 // FIXME: iWMMXT not supported
9113 { "iwmmxt", Feature_None, 0 },
9114 // FIXME: iWMMXT2 not supported
9115 { "iwmmxt2", Feature_None, 0 },
9116 // FIXME: Maverick not supported
9117 { "maverick", Feature_None, 0 },
9118 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9119 // FIXME: ARMv6-m OS Extensions feature not checked
9120 { "os", Feature_None, 0 },
9121 // FIXME: Also available in ARMv6-K
9122 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9123 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9124 // FIXME: Only available in A-class, isel not predicated
9125 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9126 // FIXME: xscale not supported
9127 { "xscale", Feature_None, 0 },
9130 /// parseDirectiveArchExtension
9131 /// ::= .arch_extension [no]feature
9132 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9133 if (getLexer().isNot(AsmToken::Identifier)) {
9134 Error(getLexer().getLoc(), "unexpected token");
9135 Parser.eatToEndOfStatement();
9139 StringRef Extension = Parser.getTok().getString();
9140 SMLoc ExtLoc = Parser.getTok().getLoc();
9143 bool EnableFeature = true;
9144 if (Extension.startswith_lower("no")) {
9145 EnableFeature = false;
9146 Extension = Extension.substr(2);
9149 for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) {
9150 if (Extensions[EI].Extension != Extension)
9153 unsigned FB = getAvailableFeatures();
9154 if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) {
9155 Error(ExtLoc, "architectural extension '" + Extension + "' is not "
9156 "allowed for the current base architecture");
9160 if (!Extensions[EI].Features)
9161 report_fatal_error("unsupported architectural extension: " + Extension);
9164 FB |= ComputeAvailableFeatures(Extensions[EI].Features);
9166 FB &= ~ComputeAvailableFeatures(Extensions[EI].Features);
9168 setAvailableFeatures(FB);
9172 Error(ExtLoc, "unknown architectural extension: " + Extension);
9173 Parser.eatToEndOfStatement();
9177 // Define this matcher function after the auto-generated include so we
9178 // have the match class enum definitions.
9179 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
9181 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
9182 // If the kind is a token for a literal immediate, check if our asm
9183 // operand matches. This is for InstAliases which have a fixed-value
9184 // immediate in the syntax.
9189 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()))
9190 if (CE->getValue() == 0)
9191 return Match_Success;
9195 const MCExpr *SOExpr = Op->getImm();
9197 if (!SOExpr->EvaluateAsAbsolute(Value))
9198 return Match_Success;
9199 assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
9200 "expression value must be representiable in 32 bits");
9205 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg()))
9206 return Match_Success;
9209 return Match_InvalidOperand;