1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCTargetAsmParser.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/OwningPtr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCParser/MCAsmLexer.h"
28 #include "llvm/MC/MCParser/MCAsmParser.h"
29 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
30 #include "llvm/MC/MCRegisterInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/Support/ELF.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/SourceMgr.h"
36 #include "llvm/Support/TargetRegistry.h"
37 #include "llvm/Support/raw_ostream.h"
45 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
47 class ARMAsmParser : public MCTargetAsmParser {
50 const MCRegisterInfo *MRI;
52 // Unwind directives state
58 void resetUnwindDirectiveParserState() {
60 CantUnwindLoc = SMLoc();
61 PersonalityLoc = SMLoc();
62 HandlerDataLoc = SMLoc();
66 // Map of register aliases registers via the .req directive.
67 StringMap<unsigned> RegisterReqs;
70 ARMCC::CondCodes Cond; // Condition for IT block.
71 unsigned Mask:4; // Condition mask for instructions.
72 // Starting at first 1 (from lsb).
73 // '1' condition as indicated in IT.
74 // '0' inverse of condition (else).
75 // Count of instructions in IT block is
76 // 4 - trailingzeroes(mask)
78 bool FirstCond; // Explicit flag for when we're parsing the
79 // First instruction in the IT block. It's
80 // implied in the mask, so needs special
83 unsigned CurPosition; // Current position in parsing of IT
84 // block. In range [0,3]. Initialized
85 // according to count of instructions in block.
86 // ~0U if no active IT block.
88 bool inITBlock() { return ITState.CurPosition != ~0U;}
89 void forwardITPosition() {
90 if (!inITBlock()) return;
91 // Move to the next instruction in the IT block, if there is one. If not,
92 // mark the block as done.
93 unsigned TZ = countTrailingZeros(ITState.Mask);
94 if (++ITState.CurPosition == 5 - TZ)
95 ITState.CurPosition = ~0U; // Done with the IT block after this.
99 MCAsmParser &getParser() const { return Parser; }
100 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
102 bool Warning(SMLoc L, const Twine &Msg,
103 ArrayRef<SMRange> Ranges = None) {
104 return Parser.Warning(L, Msg, Ranges);
106 bool Error(SMLoc L, const Twine &Msg,
107 ArrayRef<SMRange> Ranges = None) {
108 return Parser.Error(L, Msg, Ranges);
111 int tryParseRegister();
112 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
113 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
114 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
115 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
116 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
117 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
118 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
119 unsigned &ShiftAmount);
120 bool parseDirectiveWord(unsigned Size, SMLoc L);
121 bool parseDirectiveThumb(SMLoc L);
122 bool parseDirectiveARM(SMLoc L);
123 bool parseDirectiveThumbFunc(SMLoc L);
124 bool parseDirectiveCode(SMLoc L);
125 bool parseDirectiveSyntax(SMLoc L);
126 bool parseDirectiveReq(StringRef Name, SMLoc L);
127 bool parseDirectiveUnreq(SMLoc L);
128 bool parseDirectiveArch(SMLoc L);
129 bool parseDirectiveEabiAttr(SMLoc L);
130 bool parseDirectiveFnStart(SMLoc L);
131 bool parseDirectiveFnEnd(SMLoc L);
132 bool parseDirectiveCantUnwind(SMLoc L);
133 bool parseDirectivePersonality(SMLoc L);
134 bool parseDirectiveHandlerData(SMLoc L);
135 bool parseDirectiveSetFP(SMLoc L);
136 bool parseDirectivePad(SMLoc L);
137 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
139 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
140 bool &CarrySetting, unsigned &ProcessorIMod,
142 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
143 bool &CanAcceptPredicationCode);
145 bool isThumb() const {
146 // FIXME: Can tablegen auto-generate this?
147 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
149 bool isThumbOne() const {
150 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
152 bool isThumbTwo() const {
153 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
155 bool hasThumb() const {
156 return STI.getFeatureBits() & ARM::HasV4TOps;
158 bool hasV6Ops() const {
159 return STI.getFeatureBits() & ARM::HasV6Ops;
161 bool hasV7Ops() const {
162 return STI.getFeatureBits() & ARM::HasV7Ops;
164 bool hasV8Ops() const {
165 return STI.getFeatureBits() & ARM::HasV8Ops;
167 bool hasARM() const {
168 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
172 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
173 setAvailableFeatures(FB);
175 bool isMClass() const {
176 return STI.getFeatureBits() & ARM::FeatureMClass;
179 /// @name Auto-generated Match Functions
182 #define GET_ASSEMBLER_HEADER
183 #include "ARMGenAsmMatcher.inc"
187 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
188 OperandMatchResultTy parseCoprocNumOperand(
189 SmallVectorImpl<MCParsedAsmOperand*>&);
190 OperandMatchResultTy parseCoprocRegOperand(
191 SmallVectorImpl<MCParsedAsmOperand*>&);
192 OperandMatchResultTy parseCoprocOptionOperand(
193 SmallVectorImpl<MCParsedAsmOperand*>&);
194 OperandMatchResultTy parseMemBarrierOptOperand(
195 SmallVectorImpl<MCParsedAsmOperand*>&);
196 OperandMatchResultTy parseInstSyncBarrierOptOperand(
197 SmallVectorImpl<MCParsedAsmOperand*>&);
198 OperandMatchResultTy parseProcIFlagsOperand(
199 SmallVectorImpl<MCParsedAsmOperand*>&);
200 OperandMatchResultTy parseMSRMaskOperand(
201 SmallVectorImpl<MCParsedAsmOperand*>&);
202 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
203 StringRef Op, int Low, int High);
204 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
205 return parsePKHImm(O, "lsl", 0, 31);
207 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
208 return parsePKHImm(O, "asr", 1, 32);
210 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
211 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
212 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
213 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
214 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
215 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
216 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
217 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
218 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
221 // Asm Match Converter Methods
222 void cvtThumbMultiply(MCInst &Inst,
223 const SmallVectorImpl<MCParsedAsmOperand*> &);
224 void cvtThumbBranches(MCInst &Inst,
225 const SmallVectorImpl<MCParsedAsmOperand*> &);
227 bool validateInstruction(MCInst &Inst,
228 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
229 bool processInstruction(MCInst &Inst,
230 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
231 bool shouldOmitCCOutOperand(StringRef Mnemonic,
232 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
233 bool shouldOmitPredicateOperand(StringRef Mnemonic,
234 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
235 bool isDeprecated(MCInst &Inst, StringRef &Info);
238 enum ARMMatchResultTy {
239 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
240 Match_RequiresNotITBlock,
242 Match_RequiresThumb2,
243 #define GET_OPERAND_DIAGNOSTIC_TYPES
244 #include "ARMGenAsmMatcher.inc"
248 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
249 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), FPReg(-1) {
250 MCAsmParserExtension::Initialize(_Parser);
252 // Cache the MCRegisterInfo.
253 MRI = getContext().getRegisterInfo();
255 // Initialize the set of available features.
256 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
258 // Not in an ITBlock to start with.
259 ITState.CurPosition = ~0U;
261 // Set ELF header flags.
262 // FIXME: This should eventually end up somewhere else where more
263 // intelligent flag decisions can be made. For now we are just maintaining
264 // the statu/parseDirects quo for ARM and setting EF_ARM_EABI_VER5 as the default.
265 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&Parser.getStreamer()))
266 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
269 // Implementation of the MCTargetAsmParser interface:
270 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
271 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
273 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
274 bool ParseDirective(AsmToken DirectiveID);
276 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
277 unsigned checkTargetMatchPredicate(MCInst &Inst);
279 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
280 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
281 MCStreamer &Out, unsigned &ErrorInfo,
282 bool MatchingInlineAsm);
284 } // end anonymous namespace
288 /// ARMOperand - Instances of this class represent a parsed ARM machine
290 class ARMOperand : public MCParsedAsmOperand {
300 k_InstSyncBarrierOpt,
311 k_VectorListAllLanes,
317 k_BitfieldDescriptor,
321 SMLoc StartLoc, EndLoc;
322 SmallVector<unsigned, 8> Registers;
325 ARMCC::CondCodes Val;
332 struct CoprocOptionOp {
345 ARM_ISB::InstSyncBOpt Val;
349 ARM_PROC::IFlags Val;
365 // A vector register list is a sequential list of 1 to 4 registers.
366 struct VectorListOp {
373 struct VectorIndexOp {
381 /// Combined record for all forms of ARM address expressions.
384 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
386 const MCConstantExpr *OffsetImm; // Offset immediate value
387 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
388 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
389 unsigned ShiftImm; // shift for OffsetReg.
390 unsigned Alignment; // 0 = no alignment specified
391 // n = alignment in bytes (2, 4, 8, 16, or 32)
392 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
395 struct PostIdxRegOp {
398 ARM_AM::ShiftOpc ShiftTy;
402 struct ShifterImmOp {
407 struct RegShiftedRegOp {
408 ARM_AM::ShiftOpc ShiftTy;
414 struct RegShiftedImmOp {
415 ARM_AM::ShiftOpc ShiftTy;
432 struct CoprocOptionOp CoprocOption;
433 struct MBOptOp MBOpt;
434 struct ISBOptOp ISBOpt;
435 struct ITMaskOp ITMask;
436 struct IFlagsOp IFlags;
437 struct MMaskOp MMask;
440 struct VectorListOp VectorList;
441 struct VectorIndexOp VectorIndex;
443 struct MemoryOp Memory;
444 struct PostIdxRegOp PostIdxReg;
445 struct ShifterImmOp ShifterImm;
446 struct RegShiftedRegOp RegShiftedReg;
447 struct RegShiftedImmOp RegShiftedImm;
448 struct RotImmOp RotImm;
449 struct BitfieldOp Bitfield;
452 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
454 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
456 StartLoc = o.StartLoc;
473 case k_DPRRegisterList:
474 case k_SPRRegisterList:
475 Registers = o.Registers;
478 case k_VectorListAllLanes:
479 case k_VectorListIndexed:
480 VectorList = o.VectorList;
487 CoprocOption = o.CoprocOption;
492 case k_MemBarrierOpt:
495 case k_InstSyncBarrierOpt:
500 case k_PostIndexRegister:
501 PostIdxReg = o.PostIdxReg;
509 case k_ShifterImmediate:
510 ShifterImm = o.ShifterImm;
512 case k_ShiftedRegister:
513 RegShiftedReg = o.RegShiftedReg;
515 case k_ShiftedImmediate:
516 RegShiftedImm = o.RegShiftedImm;
518 case k_RotateImmediate:
521 case k_BitfieldDescriptor:
522 Bitfield = o.Bitfield;
525 VectorIndex = o.VectorIndex;
530 /// getStartLoc - Get the location of the first token of this operand.
531 SMLoc getStartLoc() const { return StartLoc; }
532 /// getEndLoc - Get the location of the last token of this operand.
533 SMLoc getEndLoc() const { return EndLoc; }
534 /// getLocRange - Get the range between the first and last token of this
536 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
538 ARMCC::CondCodes getCondCode() const {
539 assert(Kind == k_CondCode && "Invalid access!");
543 unsigned getCoproc() const {
544 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
548 StringRef getToken() const {
549 assert(Kind == k_Token && "Invalid access!");
550 return StringRef(Tok.Data, Tok.Length);
553 unsigned getReg() const {
554 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
558 const SmallVectorImpl<unsigned> &getRegList() const {
559 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
560 Kind == k_SPRRegisterList) && "Invalid access!");
564 const MCExpr *getImm() const {
565 assert(isImm() && "Invalid access!");
569 unsigned getVectorIndex() const {
570 assert(Kind == k_VectorIndex && "Invalid access!");
571 return VectorIndex.Val;
574 ARM_MB::MemBOpt getMemBarrierOpt() const {
575 assert(Kind == k_MemBarrierOpt && "Invalid access!");
579 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
580 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
584 ARM_PROC::IFlags getProcIFlags() const {
585 assert(Kind == k_ProcIFlags && "Invalid access!");
589 unsigned getMSRMask() const {
590 assert(Kind == k_MSRMask && "Invalid access!");
594 bool isCoprocNum() const { return Kind == k_CoprocNum; }
595 bool isCoprocReg() const { return Kind == k_CoprocReg; }
596 bool isCoprocOption() const { return Kind == k_CoprocOption; }
597 bool isCondCode() const { return Kind == k_CondCode; }
598 bool isCCOut() const { return Kind == k_CCOut; }
599 bool isITMask() const { return Kind == k_ITCondMask; }
600 bool isITCondCode() const { return Kind == k_CondCode; }
601 bool isImm() const { return Kind == k_Immediate; }
602 // checks whether this operand is an unsigned offset which fits is a field
603 // of specified width and scaled by a specific number of bits
604 template<unsigned width, unsigned scale>
605 bool isUnsignedOffset() const {
606 if (!isImm()) return false;
607 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
608 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
609 int64_t Val = CE->getValue();
610 int64_t Align = 1LL << scale;
611 int64_t Max = Align * ((1LL << width) - 1);
612 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
616 // checks whether this operand is an signed offset which fits is a field
617 // of specified width and scaled by a specific number of bits
618 template<unsigned width, unsigned scale>
619 bool isSignedOffset() const {
620 if (!isImm()) return false;
621 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
622 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
623 int64_t Val = CE->getValue();
624 int64_t Align = 1LL << scale;
625 int64_t Max = Align * ((1LL << (width-1)) - 1);
626 int64_t Min = -Align * (1LL << (width-1));
627 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
632 // checks whether this operand is a memory operand computed as an offset
633 // applied to PC. the offset may have 8 bits of magnitude and is represented
634 // with two bits of shift. textually it may be either [pc, #imm], #imm or
635 // relocable expression...
636 bool isThumbMemPC() const {
639 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
640 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
641 if (!CE) return false;
642 Val = CE->getValue();
645 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
646 if(Memory.BaseRegNum != ARM::PC) return false;
647 Val = Memory.OffsetImm->getValue();
650 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
652 bool isFPImm() const {
653 if (!isImm()) return false;
654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
655 if (!CE) return false;
656 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
659 bool isFBits16() const {
660 if (!isImm()) return false;
661 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
662 if (!CE) return false;
663 int64_t Value = CE->getValue();
664 return Value >= 0 && Value <= 16;
666 bool isFBits32() const {
667 if (!isImm()) return false;
668 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
669 if (!CE) return false;
670 int64_t Value = CE->getValue();
671 return Value >= 1 && Value <= 32;
673 bool isImm8s4() const {
674 if (!isImm()) return false;
675 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
676 if (!CE) return false;
677 int64_t Value = CE->getValue();
678 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
680 bool isImm0_4() const {
681 if (!isImm()) return false;
682 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
683 if (!CE) return false;
684 int64_t Value = CE->getValue();
685 return Value >= 0 && Value < 5;
687 bool isImm0_1020s4() const {
688 if (!isImm()) return false;
689 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
690 if (!CE) return false;
691 int64_t Value = CE->getValue();
692 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
694 bool isImm0_508s4() const {
695 if (!isImm()) return false;
696 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
697 if (!CE) return false;
698 int64_t Value = CE->getValue();
699 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
701 bool isImm0_508s4Neg() const {
702 if (!isImm()) return false;
703 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
704 if (!CE) return false;
705 int64_t Value = -CE->getValue();
706 // explicitly exclude zero. we want that to use the normal 0_508 version.
707 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
709 bool isImm0_255() const {
710 if (!isImm()) return false;
711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
712 if (!CE) return false;
713 int64_t Value = CE->getValue();
714 return Value >= 0 && Value < 256;
716 bool isImm0_4095() const {
717 if (!isImm()) return false;
718 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
719 if (!CE) return false;
720 int64_t Value = CE->getValue();
721 return Value >= 0 && Value < 4096;
723 bool isImm0_4095Neg() const {
724 if (!isImm()) return false;
725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
726 if (!CE) return false;
727 int64_t Value = -CE->getValue();
728 return Value > 0 && Value < 4096;
730 bool isImm0_1() const {
731 if (!isImm()) return false;
732 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
733 if (!CE) return false;
734 int64_t Value = CE->getValue();
735 return Value >= 0 && Value < 2;
737 bool isImm0_3() const {
738 if (!isImm()) return false;
739 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
740 if (!CE) return false;
741 int64_t Value = CE->getValue();
742 return Value >= 0 && Value < 4;
744 bool isImm0_7() const {
745 if (!isImm()) return false;
746 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
747 if (!CE) return false;
748 int64_t Value = CE->getValue();
749 return Value >= 0 && Value < 8;
751 bool isImm0_15() const {
752 if (!isImm()) return false;
753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
754 if (!CE) return false;
755 int64_t Value = CE->getValue();
756 return Value >= 0 && Value < 16;
758 bool isImm0_31() const {
759 if (!isImm()) return false;
760 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
761 if (!CE) return false;
762 int64_t Value = CE->getValue();
763 return Value >= 0 && Value < 32;
765 bool isImm0_63() const {
766 if (!isImm()) return false;
767 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
768 if (!CE) return false;
769 int64_t Value = CE->getValue();
770 return Value >= 0 && Value < 64;
772 bool isImm8() const {
773 if (!isImm()) return false;
774 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
775 if (!CE) return false;
776 int64_t Value = CE->getValue();
779 bool isImm16() const {
780 if (!isImm()) return false;
781 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
782 if (!CE) return false;
783 int64_t Value = CE->getValue();
786 bool isImm32() const {
787 if (!isImm()) return false;
788 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
789 if (!CE) return false;
790 int64_t Value = CE->getValue();
793 bool isShrImm8() const {
794 if (!isImm()) return false;
795 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
796 if (!CE) return false;
797 int64_t Value = CE->getValue();
798 return Value > 0 && Value <= 8;
800 bool isShrImm16() const {
801 if (!isImm()) return false;
802 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
803 if (!CE) return false;
804 int64_t Value = CE->getValue();
805 return Value > 0 && Value <= 16;
807 bool isShrImm32() const {
808 if (!isImm()) return false;
809 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
810 if (!CE) return false;
811 int64_t Value = CE->getValue();
812 return Value > 0 && Value <= 32;
814 bool isShrImm64() const {
815 if (!isImm()) return false;
816 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
817 if (!CE) return false;
818 int64_t Value = CE->getValue();
819 return Value > 0 && Value <= 64;
821 bool isImm1_7() const {
822 if (!isImm()) return false;
823 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
824 if (!CE) return false;
825 int64_t Value = CE->getValue();
826 return Value > 0 && Value < 8;
828 bool isImm1_15() const {
829 if (!isImm()) return false;
830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
831 if (!CE) return false;
832 int64_t Value = CE->getValue();
833 return Value > 0 && Value < 16;
835 bool isImm1_31() const {
836 if (!isImm()) return false;
837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
838 if (!CE) return false;
839 int64_t Value = CE->getValue();
840 return Value > 0 && Value < 32;
842 bool isImm1_16() const {
843 if (!isImm()) return false;
844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
845 if (!CE) return false;
846 int64_t Value = CE->getValue();
847 return Value > 0 && Value < 17;
849 bool isImm1_32() const {
850 if (!isImm()) return false;
851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
852 if (!CE) return false;
853 int64_t Value = CE->getValue();
854 return Value > 0 && Value < 33;
856 bool isImm0_32() const {
857 if (!isImm()) return false;
858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859 if (!CE) return false;
860 int64_t Value = CE->getValue();
861 return Value >= 0 && Value < 33;
863 bool isImm0_65535() const {
864 if (!isImm()) return false;
865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866 if (!CE) return false;
867 int64_t Value = CE->getValue();
868 return Value >= 0 && Value < 65536;
870 bool isImm256_65535Expr() const {
871 if (!isImm()) return false;
872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873 // If it's not a constant expression, it'll generate a fixup and be
875 if (!CE) return true;
876 int64_t Value = CE->getValue();
877 return Value >= 256 && Value < 65536;
879 bool isImm0_65535Expr() const {
880 if (!isImm()) return false;
881 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
882 // If it's not a constant expression, it'll generate a fixup and be
884 if (!CE) return true;
885 int64_t Value = CE->getValue();
886 return Value >= 0 && Value < 65536;
888 bool isImm24bit() const {
889 if (!isImm()) return false;
890 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
891 if (!CE) return false;
892 int64_t Value = CE->getValue();
893 return Value >= 0 && Value <= 0xffffff;
895 bool isImmThumbSR() const {
896 if (!isImm()) return false;
897 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
898 if (!CE) return false;
899 int64_t Value = CE->getValue();
900 return Value > 0 && Value < 33;
902 bool isPKHLSLImm() const {
903 if (!isImm()) return false;
904 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
905 if (!CE) return false;
906 int64_t Value = CE->getValue();
907 return Value >= 0 && Value < 32;
909 bool isPKHASRImm() const {
910 if (!isImm()) return false;
911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
912 if (!CE) return false;
913 int64_t Value = CE->getValue();
914 return Value > 0 && Value <= 32;
916 bool isAdrLabel() const {
917 // If we have an immediate that's not a constant, treat it as a label
918 // reference needing a fixup. If it is a constant, but it can't fit
919 // into shift immediate encoding, we reject it.
920 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
921 else return (isARMSOImm() || isARMSOImmNeg());
923 bool isARMSOImm() const {
924 if (!isImm()) return false;
925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
926 if (!CE) return false;
927 int64_t Value = CE->getValue();
928 return ARM_AM::getSOImmVal(Value) != -1;
930 bool isARMSOImmNot() const {
931 if (!isImm()) return false;
932 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
933 if (!CE) return false;
934 int64_t Value = CE->getValue();
935 return ARM_AM::getSOImmVal(~Value) != -1;
937 bool isARMSOImmNeg() const {
938 if (!isImm()) return false;
939 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
940 if (!CE) return false;
941 int64_t Value = CE->getValue();
942 // Only use this when not representable as a plain so_imm.
943 return ARM_AM::getSOImmVal(Value) == -1 &&
944 ARM_AM::getSOImmVal(-Value) != -1;
946 bool isT2SOImm() const {
947 if (!isImm()) return false;
948 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
949 if (!CE) return false;
950 int64_t Value = CE->getValue();
951 return ARM_AM::getT2SOImmVal(Value) != -1;
953 bool isT2SOImmNot() const {
954 if (!isImm()) return false;
955 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
956 if (!CE) return false;
957 int64_t Value = CE->getValue();
958 return ARM_AM::getT2SOImmVal(Value) == -1 &&
959 ARM_AM::getT2SOImmVal(~Value) != -1;
961 bool isT2SOImmNeg() const {
962 if (!isImm()) return false;
963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964 if (!CE) return false;
965 int64_t Value = CE->getValue();
966 // Only use this when not representable as a plain so_imm.
967 return ARM_AM::getT2SOImmVal(Value) == -1 &&
968 ARM_AM::getT2SOImmVal(-Value) != -1;
970 bool isSetEndImm() const {
971 if (!isImm()) return false;
972 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
973 if (!CE) return false;
974 int64_t Value = CE->getValue();
975 return Value == 1 || Value == 0;
977 bool isReg() const { return Kind == k_Register; }
978 bool isRegList() const { return Kind == k_RegisterList; }
979 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
980 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
981 bool isToken() const { return Kind == k_Token; }
982 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
983 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
984 bool isMem() const { return Kind == k_Memory; }
985 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
986 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
987 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
988 bool isRotImm() const { return Kind == k_RotateImmediate; }
989 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
990 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
991 bool isPostIdxReg() const {
992 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
994 bool isMemNoOffset(bool alignOK = false) const {
997 // No offset of any kind.
998 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
999 (alignOK || Memory.Alignment == 0);
1001 bool isMemPCRelImm12() const {
1002 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1004 // Base register must be PC.
1005 if (Memory.BaseRegNum != ARM::PC)
1007 // Immediate offset in range [-4095, 4095].
1008 if (!Memory.OffsetImm) return true;
1009 int64_t Val = Memory.OffsetImm->getValue();
1010 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1012 bool isAlignedMemory() const {
1013 return isMemNoOffset(true);
1015 bool isAddrMode2() const {
1016 if (!isMem() || Memory.Alignment != 0) return false;
1017 // Check for register offset.
1018 if (Memory.OffsetRegNum) return true;
1019 // Immediate offset in range [-4095, 4095].
1020 if (!Memory.OffsetImm) return true;
1021 int64_t Val = Memory.OffsetImm->getValue();
1022 return Val > -4096 && Val < 4096;
1024 bool isAM2OffsetImm() const {
1025 if (!isImm()) return false;
1026 // Immediate offset in range [-4095, 4095].
1027 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1028 if (!CE) return false;
1029 int64_t Val = CE->getValue();
1030 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1032 bool isAddrMode3() const {
1033 // If we have an immediate that's not a constant, treat it as a label
1034 // reference needing a fixup. If it is a constant, it's something else
1035 // and we reject it.
1036 if (isImm() && !isa<MCConstantExpr>(getImm()))
1038 if (!isMem() || Memory.Alignment != 0) return false;
1039 // No shifts are legal for AM3.
1040 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1041 // Check for register offset.
1042 if (Memory.OffsetRegNum) return true;
1043 // Immediate offset in range [-255, 255].
1044 if (!Memory.OffsetImm) return true;
1045 int64_t Val = Memory.OffsetImm->getValue();
1046 // The #-0 offset is encoded as INT32_MIN, and we have to check
1048 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1050 bool isAM3Offset() const {
1051 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1053 if (Kind == k_PostIndexRegister)
1054 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1055 // Immediate offset in range [-255, 255].
1056 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1057 if (!CE) return false;
1058 int64_t Val = CE->getValue();
1059 // Special case, #-0 is INT32_MIN.
1060 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1062 bool isAddrMode5() const {
1063 // If we have an immediate that's not a constant, treat it as a label
1064 // reference needing a fixup. If it is a constant, it's something else
1065 // and we reject it.
1066 if (isImm() && !isa<MCConstantExpr>(getImm()))
1068 if (!isMem() || Memory.Alignment != 0) return false;
1069 // Check for register offset.
1070 if (Memory.OffsetRegNum) return false;
1071 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1072 if (!Memory.OffsetImm) return true;
1073 int64_t Val = Memory.OffsetImm->getValue();
1074 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1077 bool isMemTBB() const {
1078 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1079 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1083 bool isMemTBH() const {
1084 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1085 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1086 Memory.Alignment != 0 )
1090 bool isMemRegOffset() const {
1091 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1095 bool isT2MemRegOffset() const {
1096 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1097 Memory.Alignment != 0)
1099 // Only lsl #{0, 1, 2, 3} allowed.
1100 if (Memory.ShiftType == ARM_AM::no_shift)
1102 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1106 bool isMemThumbRR() const {
1107 // Thumb reg+reg addressing is simple. Just two registers, a base and
1108 // an offset. No shifts, negations or any other complicating factors.
1109 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1110 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1112 return isARMLowRegister(Memory.BaseRegNum) &&
1113 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1115 bool isMemThumbRIs4() const {
1116 if (!isMem() || Memory.OffsetRegNum != 0 ||
1117 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1119 // Immediate offset, multiple of 4 in range [0, 124].
1120 if (!Memory.OffsetImm) return true;
1121 int64_t Val = Memory.OffsetImm->getValue();
1122 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1124 bool isMemThumbRIs2() const {
1125 if (!isMem() || Memory.OffsetRegNum != 0 ||
1126 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1128 // Immediate offset, multiple of 4 in range [0, 62].
1129 if (!Memory.OffsetImm) return true;
1130 int64_t Val = Memory.OffsetImm->getValue();
1131 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1133 bool isMemThumbRIs1() const {
1134 if (!isMem() || Memory.OffsetRegNum != 0 ||
1135 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1137 // Immediate offset in range [0, 31].
1138 if (!Memory.OffsetImm) return true;
1139 int64_t Val = Memory.OffsetImm->getValue();
1140 return Val >= 0 && Val <= 31;
1142 bool isMemThumbSPI() const {
1143 if (!isMem() || Memory.OffsetRegNum != 0 ||
1144 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1146 // Immediate offset, multiple of 4 in range [0, 1020].
1147 if (!Memory.OffsetImm) return true;
1148 int64_t Val = Memory.OffsetImm->getValue();
1149 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1151 bool isMemImm8s4Offset() const {
1152 // If we have an immediate that's not a constant, treat it as a label
1153 // reference needing a fixup. If it is a constant, it's something else
1154 // and we reject it.
1155 if (isImm() && !isa<MCConstantExpr>(getImm()))
1157 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1159 // Immediate offset a multiple of 4 in range [-1020, 1020].
1160 if (!Memory.OffsetImm) return true;
1161 int64_t Val = Memory.OffsetImm->getValue();
1162 // Special case, #-0 is INT32_MIN.
1163 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1165 bool isMemImm0_1020s4Offset() const {
1166 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1168 // Immediate offset a multiple of 4 in range [0, 1020].
1169 if (!Memory.OffsetImm) return true;
1170 int64_t Val = Memory.OffsetImm->getValue();
1171 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1173 bool isMemImm8Offset() const {
1174 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1176 // Base reg of PC isn't allowed for these encodings.
1177 if (Memory.BaseRegNum == ARM::PC) return false;
1178 // Immediate offset in range [-255, 255].
1179 if (!Memory.OffsetImm) return true;
1180 int64_t Val = Memory.OffsetImm->getValue();
1181 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1183 bool isMemPosImm8Offset() const {
1184 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1186 // Immediate offset in range [0, 255].
1187 if (!Memory.OffsetImm) return true;
1188 int64_t Val = Memory.OffsetImm->getValue();
1189 return Val >= 0 && Val < 256;
1191 bool isMemNegImm8Offset() const {
1192 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1194 // Base reg of PC isn't allowed for these encodings.
1195 if (Memory.BaseRegNum == ARM::PC) return false;
1196 // Immediate offset in range [-255, -1].
1197 if (!Memory.OffsetImm) return false;
1198 int64_t Val = Memory.OffsetImm->getValue();
1199 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1201 bool isMemUImm12Offset() const {
1202 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1204 // Immediate offset in range [0, 4095].
1205 if (!Memory.OffsetImm) return true;
1206 int64_t Val = Memory.OffsetImm->getValue();
1207 return (Val >= 0 && Val < 4096);
1209 bool isMemImm12Offset() const {
1210 // If we have an immediate that's not a constant, treat it as a label
1211 // reference needing a fixup. If it is a constant, it's something else
1212 // and we reject it.
1213 if (isImm() && !isa<MCConstantExpr>(getImm()))
1216 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1218 // Immediate offset in range [-4095, 4095].
1219 if (!Memory.OffsetImm) return true;
1220 int64_t Val = Memory.OffsetImm->getValue();
1221 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1223 bool isPostIdxImm8() const {
1224 if (!isImm()) return false;
1225 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1226 if (!CE) return false;
1227 int64_t Val = CE->getValue();
1228 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1230 bool isPostIdxImm8s4() const {
1231 if (!isImm()) return false;
1232 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1233 if (!CE) return false;
1234 int64_t Val = CE->getValue();
1235 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1239 bool isMSRMask() const { return Kind == k_MSRMask; }
1240 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1243 bool isSingleSpacedVectorList() const {
1244 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1246 bool isDoubleSpacedVectorList() const {
1247 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1249 bool isVecListOneD() const {
1250 if (!isSingleSpacedVectorList()) return false;
1251 return VectorList.Count == 1;
1254 bool isVecListDPair() const {
1255 if (!isSingleSpacedVectorList()) return false;
1256 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1257 .contains(VectorList.RegNum));
1260 bool isVecListThreeD() const {
1261 if (!isSingleSpacedVectorList()) return false;
1262 return VectorList.Count == 3;
1265 bool isVecListFourD() const {
1266 if (!isSingleSpacedVectorList()) return false;
1267 return VectorList.Count == 4;
1270 bool isVecListDPairSpaced() const {
1271 if (isSingleSpacedVectorList()) return false;
1272 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1273 .contains(VectorList.RegNum));
1276 bool isVecListThreeQ() const {
1277 if (!isDoubleSpacedVectorList()) return false;
1278 return VectorList.Count == 3;
1281 bool isVecListFourQ() const {
1282 if (!isDoubleSpacedVectorList()) return false;
1283 return VectorList.Count == 4;
1286 bool isSingleSpacedVectorAllLanes() const {
1287 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1289 bool isDoubleSpacedVectorAllLanes() const {
1290 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1292 bool isVecListOneDAllLanes() const {
1293 if (!isSingleSpacedVectorAllLanes()) return false;
1294 return VectorList.Count == 1;
1297 bool isVecListDPairAllLanes() const {
1298 if (!isSingleSpacedVectorAllLanes()) return false;
1299 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1300 .contains(VectorList.RegNum));
1303 bool isVecListDPairSpacedAllLanes() const {
1304 if (!isDoubleSpacedVectorAllLanes()) return false;
1305 return VectorList.Count == 2;
1308 bool isVecListThreeDAllLanes() const {
1309 if (!isSingleSpacedVectorAllLanes()) return false;
1310 return VectorList.Count == 3;
1313 bool isVecListThreeQAllLanes() const {
1314 if (!isDoubleSpacedVectorAllLanes()) return false;
1315 return VectorList.Count == 3;
1318 bool isVecListFourDAllLanes() const {
1319 if (!isSingleSpacedVectorAllLanes()) return false;
1320 return VectorList.Count == 4;
1323 bool isVecListFourQAllLanes() const {
1324 if (!isDoubleSpacedVectorAllLanes()) return false;
1325 return VectorList.Count == 4;
1328 bool isSingleSpacedVectorIndexed() const {
1329 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1331 bool isDoubleSpacedVectorIndexed() const {
1332 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1334 bool isVecListOneDByteIndexed() const {
1335 if (!isSingleSpacedVectorIndexed()) return false;
1336 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1339 bool isVecListOneDHWordIndexed() const {
1340 if (!isSingleSpacedVectorIndexed()) return false;
1341 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1344 bool isVecListOneDWordIndexed() const {
1345 if (!isSingleSpacedVectorIndexed()) return false;
1346 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1349 bool isVecListTwoDByteIndexed() const {
1350 if (!isSingleSpacedVectorIndexed()) return false;
1351 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1354 bool isVecListTwoDHWordIndexed() const {
1355 if (!isSingleSpacedVectorIndexed()) return false;
1356 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1359 bool isVecListTwoQWordIndexed() const {
1360 if (!isDoubleSpacedVectorIndexed()) return false;
1361 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1364 bool isVecListTwoQHWordIndexed() const {
1365 if (!isDoubleSpacedVectorIndexed()) return false;
1366 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1369 bool isVecListTwoDWordIndexed() const {
1370 if (!isSingleSpacedVectorIndexed()) return false;
1371 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1374 bool isVecListThreeDByteIndexed() const {
1375 if (!isSingleSpacedVectorIndexed()) return false;
1376 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1379 bool isVecListThreeDHWordIndexed() const {
1380 if (!isSingleSpacedVectorIndexed()) return false;
1381 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1384 bool isVecListThreeQWordIndexed() const {
1385 if (!isDoubleSpacedVectorIndexed()) return false;
1386 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1389 bool isVecListThreeQHWordIndexed() const {
1390 if (!isDoubleSpacedVectorIndexed()) return false;
1391 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1394 bool isVecListThreeDWordIndexed() const {
1395 if (!isSingleSpacedVectorIndexed()) return false;
1396 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1399 bool isVecListFourDByteIndexed() const {
1400 if (!isSingleSpacedVectorIndexed()) return false;
1401 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1404 bool isVecListFourDHWordIndexed() const {
1405 if (!isSingleSpacedVectorIndexed()) return false;
1406 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1409 bool isVecListFourQWordIndexed() const {
1410 if (!isDoubleSpacedVectorIndexed()) return false;
1411 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1414 bool isVecListFourQHWordIndexed() const {
1415 if (!isDoubleSpacedVectorIndexed()) return false;
1416 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1419 bool isVecListFourDWordIndexed() const {
1420 if (!isSingleSpacedVectorIndexed()) return false;
1421 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1424 bool isVectorIndex8() const {
1425 if (Kind != k_VectorIndex) return false;
1426 return VectorIndex.Val < 8;
1428 bool isVectorIndex16() const {
1429 if (Kind != k_VectorIndex) return false;
1430 return VectorIndex.Val < 4;
1432 bool isVectorIndex32() const {
1433 if (Kind != k_VectorIndex) return false;
1434 return VectorIndex.Val < 2;
1437 bool isNEONi8splat() const {
1438 if (!isImm()) return false;
1439 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1440 // Must be a constant.
1441 if (!CE) return false;
1442 int64_t Value = CE->getValue();
1443 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1445 return Value >= 0 && Value < 256;
1448 bool isNEONi16splat() const {
1449 if (!isImm()) return false;
1450 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1451 // Must be a constant.
1452 if (!CE) return false;
1453 int64_t Value = CE->getValue();
1454 // i16 value in the range [0,255] or [0x0100, 0xff00]
1455 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1458 bool isNEONi32splat() const {
1459 if (!isImm()) return false;
1460 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1461 // Must be a constant.
1462 if (!CE) return false;
1463 int64_t Value = CE->getValue();
1464 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1465 return (Value >= 0 && Value < 256) ||
1466 (Value >= 0x0100 && Value <= 0xff00) ||
1467 (Value >= 0x010000 && Value <= 0xff0000) ||
1468 (Value >= 0x01000000 && Value <= 0xff000000);
1471 bool isNEONi32vmov() const {
1472 if (!isImm()) return false;
1473 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1474 // Must be a constant.
1475 if (!CE) return false;
1476 int64_t Value = CE->getValue();
1477 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1478 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1479 return (Value >= 0 && Value < 256) ||
1480 (Value >= 0x0100 && Value <= 0xff00) ||
1481 (Value >= 0x010000 && Value <= 0xff0000) ||
1482 (Value >= 0x01000000 && Value <= 0xff000000) ||
1483 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1484 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1486 bool isNEONi32vmovNeg() const {
1487 if (!isImm()) return false;
1488 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1489 // Must be a constant.
1490 if (!CE) return false;
1491 int64_t Value = ~CE->getValue();
1492 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1493 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1494 return (Value >= 0 && Value < 256) ||
1495 (Value >= 0x0100 && Value <= 0xff00) ||
1496 (Value >= 0x010000 && Value <= 0xff0000) ||
1497 (Value >= 0x01000000 && Value <= 0xff000000) ||
1498 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1499 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1502 bool isNEONi64splat() const {
1503 if (!isImm()) return false;
1504 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1505 // Must be a constant.
1506 if (!CE) return false;
1507 uint64_t Value = CE->getValue();
1508 // i64 value with each byte being either 0 or 0xff.
1509 for (unsigned i = 0; i < 8; ++i)
1510 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1514 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1515 // Add as immediates when possible. Null MCExpr = 0.
1517 Inst.addOperand(MCOperand::CreateImm(0));
1518 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1519 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1521 Inst.addOperand(MCOperand::CreateExpr(Expr));
1524 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1525 assert(N == 2 && "Invalid number of operands!");
1526 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1527 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1528 Inst.addOperand(MCOperand::CreateReg(RegNum));
1531 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1532 assert(N == 1 && "Invalid number of operands!");
1533 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1536 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1537 assert(N == 1 && "Invalid number of operands!");
1538 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1541 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1542 assert(N == 1 && "Invalid number of operands!");
1543 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1546 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1547 assert(N == 1 && "Invalid number of operands!");
1548 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1551 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1552 assert(N == 1 && "Invalid number of operands!");
1553 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1556 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1557 assert(N == 1 && "Invalid number of operands!");
1558 Inst.addOperand(MCOperand::CreateReg(getReg()));
1561 void addRegOperands(MCInst &Inst, unsigned N) const {
1562 assert(N == 1 && "Invalid number of operands!");
1563 Inst.addOperand(MCOperand::CreateReg(getReg()));
1566 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1567 assert(N == 3 && "Invalid number of operands!");
1568 assert(isRegShiftedReg() &&
1569 "addRegShiftedRegOperands() on non RegShiftedReg!");
1570 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1571 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1572 Inst.addOperand(MCOperand::CreateImm(
1573 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1576 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1577 assert(N == 2 && "Invalid number of operands!");
1578 assert(isRegShiftedImm() &&
1579 "addRegShiftedImmOperands() on non RegShiftedImm!");
1580 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1581 // Shift of #32 is encoded as 0 where permitted
1582 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1583 Inst.addOperand(MCOperand::CreateImm(
1584 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1587 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1588 assert(N == 1 && "Invalid number of operands!");
1589 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1593 void addRegListOperands(MCInst &Inst, unsigned N) const {
1594 assert(N == 1 && "Invalid number of operands!");
1595 const SmallVectorImpl<unsigned> &RegList = getRegList();
1596 for (SmallVectorImpl<unsigned>::const_iterator
1597 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1598 Inst.addOperand(MCOperand::CreateReg(*I));
1601 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1602 addRegListOperands(Inst, N);
1605 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1606 addRegListOperands(Inst, N);
1609 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1610 assert(N == 1 && "Invalid number of operands!");
1611 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1612 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1615 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1616 assert(N == 1 && "Invalid number of operands!");
1617 // Munge the lsb/width into a bitfield mask.
1618 unsigned lsb = Bitfield.LSB;
1619 unsigned width = Bitfield.Width;
1620 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1621 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1622 (32 - (lsb + width)));
1623 Inst.addOperand(MCOperand::CreateImm(Mask));
1626 void addImmOperands(MCInst &Inst, unsigned N) const {
1627 assert(N == 1 && "Invalid number of operands!");
1628 addExpr(Inst, getImm());
1631 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1632 assert(N == 1 && "Invalid number of operands!");
1633 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1634 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1637 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1638 assert(N == 1 && "Invalid number of operands!");
1639 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1640 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1643 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1644 assert(N == 1 && "Invalid number of operands!");
1645 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1646 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1647 Inst.addOperand(MCOperand::CreateImm(Val));
1650 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1651 assert(N == 1 && "Invalid number of operands!");
1652 // FIXME: We really want to scale the value here, but the LDRD/STRD
1653 // instruction don't encode operands that way yet.
1654 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1655 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1658 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1659 assert(N == 1 && "Invalid number of operands!");
1660 // The immediate is scaled by four in the encoding and is stored
1661 // in the MCInst as such. Lop off the low two bits here.
1662 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1663 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1666 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1667 assert(N == 1 && "Invalid number of operands!");
1668 // The immediate is scaled by four in the encoding and is stored
1669 // in the MCInst as such. Lop off the low two bits here.
1670 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1671 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1674 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1675 assert(N == 1 && "Invalid number of operands!");
1676 // The immediate is scaled by four in the encoding and is stored
1677 // in the MCInst as such. Lop off the low two bits here.
1678 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1679 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1682 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1683 assert(N == 1 && "Invalid number of operands!");
1684 // The constant encodes as the immediate-1, and we store in the instruction
1685 // the bits as encoded, so subtract off one here.
1686 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1687 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1690 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1691 assert(N == 1 && "Invalid number of operands!");
1692 // The constant encodes as the immediate-1, and we store in the instruction
1693 // the bits as encoded, so subtract off one here.
1694 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1695 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1698 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1699 assert(N == 1 && "Invalid number of operands!");
1700 // The constant encodes as the immediate, except for 32, which encodes as
1702 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1703 unsigned Imm = CE->getValue();
1704 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1707 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1708 assert(N == 1 && "Invalid number of operands!");
1709 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1710 // the instruction as well.
1711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1712 int Val = CE->getValue();
1713 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1716 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1717 assert(N == 1 && "Invalid number of operands!");
1718 // The operand is actually a t2_so_imm, but we have its bitwise
1719 // negation in the assembly source, so twiddle it here.
1720 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1721 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1724 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1725 assert(N == 1 && "Invalid number of operands!");
1726 // The operand is actually a t2_so_imm, but we have its
1727 // negation in the assembly source, so twiddle it here.
1728 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1729 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1732 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1733 assert(N == 1 && "Invalid number of operands!");
1734 // The operand is actually an imm0_4095, but we have its
1735 // negation in the assembly source, so twiddle it here.
1736 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1737 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1740 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1741 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1742 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1746 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1747 assert(SR && "Unknown value type!");
1748 Inst.addOperand(MCOperand::CreateExpr(SR));
1751 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1752 assert(N == 1 && "Invalid number of operands!");
1754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1756 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1760 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1761 assert(SR && "Unknown value type!");
1762 Inst.addOperand(MCOperand::CreateExpr(SR));
1766 assert(isMem() && "Unknown value type!");
1767 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1768 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1771 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1772 assert(N == 1 && "Invalid number of operands!");
1773 // The operand is actually a so_imm, but we have its bitwise
1774 // negation in the assembly source, so twiddle it here.
1775 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1776 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1779 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1780 assert(N == 1 && "Invalid number of operands!");
1781 // The operand is actually a so_imm, but we have its
1782 // negation in the assembly source, so twiddle it here.
1783 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1784 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1787 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1788 assert(N == 1 && "Invalid number of operands!");
1789 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1792 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1793 assert(N == 1 && "Invalid number of operands!");
1794 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1797 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1798 assert(N == 1 && "Invalid number of operands!");
1799 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1802 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1803 assert(N == 1 && "Invalid number of operands!");
1804 int32_t Imm = Memory.OffsetImm->getValue();
1805 Inst.addOperand(MCOperand::CreateImm(Imm));
1808 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1809 assert(N == 1 && "Invalid number of operands!");
1810 assert(isImm() && "Not an immediate!");
1812 // If we have an immediate that's not a constant, treat it as a label
1813 // reference needing a fixup.
1814 if (!isa<MCConstantExpr>(getImm())) {
1815 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1819 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1820 int Val = CE->getValue();
1821 Inst.addOperand(MCOperand::CreateImm(Val));
1824 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1825 assert(N == 2 && "Invalid number of operands!");
1826 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1827 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1830 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1831 assert(N == 3 && "Invalid number of operands!");
1832 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1833 if (!Memory.OffsetRegNum) {
1834 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1835 // Special case for #-0
1836 if (Val == INT32_MIN) Val = 0;
1837 if (Val < 0) Val = -Val;
1838 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1840 // For register offset, we encode the shift type and negation flag
1842 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1843 Memory.ShiftImm, Memory.ShiftType);
1845 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1846 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1847 Inst.addOperand(MCOperand::CreateImm(Val));
1850 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1851 assert(N == 2 && "Invalid number of operands!");
1852 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1853 assert(CE && "non-constant AM2OffsetImm operand!");
1854 int32_t Val = CE->getValue();
1855 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1856 // Special case for #-0
1857 if (Val == INT32_MIN) Val = 0;
1858 if (Val < 0) Val = -Val;
1859 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1860 Inst.addOperand(MCOperand::CreateReg(0));
1861 Inst.addOperand(MCOperand::CreateImm(Val));
1864 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1865 assert(N == 3 && "Invalid number of operands!");
1866 // If we have an immediate that's not a constant, treat it as a label
1867 // reference needing a fixup. If it is a constant, it's something else
1868 // and we reject it.
1870 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1871 Inst.addOperand(MCOperand::CreateReg(0));
1872 Inst.addOperand(MCOperand::CreateImm(0));
1876 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1877 if (!Memory.OffsetRegNum) {
1878 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1879 // Special case for #-0
1880 if (Val == INT32_MIN) Val = 0;
1881 if (Val < 0) Val = -Val;
1882 Val = ARM_AM::getAM3Opc(AddSub, Val);
1884 // For register offset, we encode the shift type and negation flag
1886 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1888 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1889 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1890 Inst.addOperand(MCOperand::CreateImm(Val));
1893 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1894 assert(N == 2 && "Invalid number of operands!");
1895 if (Kind == k_PostIndexRegister) {
1897 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1898 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1899 Inst.addOperand(MCOperand::CreateImm(Val));
1904 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1905 int32_t Val = CE->getValue();
1906 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1907 // Special case for #-0
1908 if (Val == INT32_MIN) Val = 0;
1909 if (Val < 0) Val = -Val;
1910 Val = ARM_AM::getAM3Opc(AddSub, Val);
1911 Inst.addOperand(MCOperand::CreateReg(0));
1912 Inst.addOperand(MCOperand::CreateImm(Val));
1915 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1916 assert(N == 2 && "Invalid number of operands!");
1917 // If we have an immediate that's not a constant, treat it as a label
1918 // reference needing a fixup. If it is a constant, it's something else
1919 // and we reject it.
1921 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1922 Inst.addOperand(MCOperand::CreateImm(0));
1926 // The lower two bits are always zero and as such are not encoded.
1927 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1928 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1929 // Special case for #-0
1930 if (Val == INT32_MIN) Val = 0;
1931 if (Val < 0) Val = -Val;
1932 Val = ARM_AM::getAM5Opc(AddSub, Val);
1933 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1934 Inst.addOperand(MCOperand::CreateImm(Val));
1937 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1938 assert(N == 2 && "Invalid number of operands!");
1939 // If we have an immediate that's not a constant, treat it as a label
1940 // reference needing a fixup. If it is a constant, it's something else
1941 // and we reject it.
1943 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1944 Inst.addOperand(MCOperand::CreateImm(0));
1948 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1949 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1950 Inst.addOperand(MCOperand::CreateImm(Val));
1953 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1954 assert(N == 2 && "Invalid number of operands!");
1955 // The lower two bits are always zero and as such are not encoded.
1956 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1957 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1958 Inst.addOperand(MCOperand::CreateImm(Val));
1961 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1962 assert(N == 2 && "Invalid number of operands!");
1963 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1964 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1965 Inst.addOperand(MCOperand::CreateImm(Val));
1968 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1969 addMemImm8OffsetOperands(Inst, N);
1972 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1973 addMemImm8OffsetOperands(Inst, N);
1976 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1977 assert(N == 2 && "Invalid number of operands!");
1978 // If this is an immediate, it's a label reference.
1980 addExpr(Inst, getImm());
1981 Inst.addOperand(MCOperand::CreateImm(0));
1985 // Otherwise, it's a normal memory reg+offset.
1986 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1987 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1988 Inst.addOperand(MCOperand::CreateImm(Val));
1991 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1992 assert(N == 2 && "Invalid number of operands!");
1993 // If this is an immediate, it's a label reference.
1995 addExpr(Inst, getImm());
1996 Inst.addOperand(MCOperand::CreateImm(0));
2000 // Otherwise, it's a normal memory reg+offset.
2001 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2002 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2003 Inst.addOperand(MCOperand::CreateImm(Val));
2006 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2007 assert(N == 2 && "Invalid number of operands!");
2008 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2009 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2012 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2013 assert(N == 2 && "Invalid number of operands!");
2014 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2015 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2018 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2019 assert(N == 3 && "Invalid number of operands!");
2021 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2022 Memory.ShiftImm, Memory.ShiftType);
2023 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2024 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2025 Inst.addOperand(MCOperand::CreateImm(Val));
2028 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2029 assert(N == 3 && "Invalid number of operands!");
2030 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2031 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2032 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2035 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2036 assert(N == 2 && "Invalid number of operands!");
2037 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2038 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2041 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2042 assert(N == 2 && "Invalid number of operands!");
2043 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2044 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2045 Inst.addOperand(MCOperand::CreateImm(Val));
2048 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2049 assert(N == 2 && "Invalid number of operands!");
2050 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2051 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2052 Inst.addOperand(MCOperand::CreateImm(Val));
2055 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2056 assert(N == 2 && "Invalid number of operands!");
2057 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2058 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2059 Inst.addOperand(MCOperand::CreateImm(Val));
2062 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2063 assert(N == 2 && "Invalid number of operands!");
2064 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2065 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2066 Inst.addOperand(MCOperand::CreateImm(Val));
2069 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2070 assert(N == 1 && "Invalid number of operands!");
2071 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2072 assert(CE && "non-constant post-idx-imm8 operand!");
2073 int Imm = CE->getValue();
2074 bool isAdd = Imm >= 0;
2075 if (Imm == INT32_MIN) Imm = 0;
2076 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2077 Inst.addOperand(MCOperand::CreateImm(Imm));
2080 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2081 assert(N == 1 && "Invalid number of operands!");
2082 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2083 assert(CE && "non-constant post-idx-imm8s4 operand!");
2084 int Imm = CE->getValue();
2085 bool isAdd = Imm >= 0;
2086 if (Imm == INT32_MIN) Imm = 0;
2087 // Immediate is scaled by 4.
2088 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2089 Inst.addOperand(MCOperand::CreateImm(Imm));
2092 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2093 assert(N == 2 && "Invalid number of operands!");
2094 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2095 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2098 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2099 assert(N == 2 && "Invalid number of operands!");
2100 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2101 // The sign, shift type, and shift amount are encoded in a single operand
2102 // using the AM2 encoding helpers.
2103 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2104 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2105 PostIdxReg.ShiftTy);
2106 Inst.addOperand(MCOperand::CreateImm(Imm));
2109 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2110 assert(N == 1 && "Invalid number of operands!");
2111 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2114 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2115 assert(N == 1 && "Invalid number of operands!");
2116 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2119 void addVecListOperands(MCInst &Inst, unsigned N) const {
2120 assert(N == 1 && "Invalid number of operands!");
2121 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2124 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2125 assert(N == 2 && "Invalid number of operands!");
2126 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2127 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2130 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2131 assert(N == 1 && "Invalid number of operands!");
2132 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2135 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2136 assert(N == 1 && "Invalid number of operands!");
2137 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2140 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2141 assert(N == 1 && "Invalid number of operands!");
2142 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2145 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2146 assert(N == 1 && "Invalid number of operands!");
2147 // The immediate encodes the type of constant as well as the value.
2148 // Mask in that this is an i8 splat.
2149 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2150 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2153 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2154 assert(N == 1 && "Invalid number of operands!");
2155 // The immediate encodes the type of constant as well as the value.
2156 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2157 unsigned Value = CE->getValue();
2159 Value = (Value >> 8) | 0xa00;
2162 Inst.addOperand(MCOperand::CreateImm(Value));
2165 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2166 assert(N == 1 && "Invalid number of operands!");
2167 // The immediate encodes the type of constant as well as the value.
2168 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2169 unsigned Value = CE->getValue();
2170 if (Value >= 256 && Value <= 0xff00)
2171 Value = (Value >> 8) | 0x200;
2172 else if (Value > 0xffff && Value <= 0xff0000)
2173 Value = (Value >> 16) | 0x400;
2174 else if (Value > 0xffffff)
2175 Value = (Value >> 24) | 0x600;
2176 Inst.addOperand(MCOperand::CreateImm(Value));
2179 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2180 assert(N == 1 && "Invalid number of operands!");
2181 // The immediate encodes the type of constant as well as the value.
2182 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2183 unsigned Value = CE->getValue();
2184 if (Value >= 256 && Value <= 0xffff)
2185 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2186 else if (Value > 0xffff && Value <= 0xffffff)
2187 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2188 else if (Value > 0xffffff)
2189 Value = (Value >> 24) | 0x600;
2190 Inst.addOperand(MCOperand::CreateImm(Value));
2193 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2194 assert(N == 1 && "Invalid number of operands!");
2195 // The immediate encodes the type of constant as well as the value.
2196 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2197 unsigned Value = ~CE->getValue();
2198 if (Value >= 256 && Value <= 0xffff)
2199 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2200 else if (Value > 0xffff && Value <= 0xffffff)
2201 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2202 else if (Value > 0xffffff)
2203 Value = (Value >> 24) | 0x600;
2204 Inst.addOperand(MCOperand::CreateImm(Value));
2207 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2208 assert(N == 1 && "Invalid number of operands!");
2209 // The immediate encodes the type of constant as well as the value.
2210 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2211 uint64_t Value = CE->getValue();
2213 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2214 Imm |= (Value & 1) << i;
2216 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2219 virtual void print(raw_ostream &OS) const;
2221 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2222 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2223 Op->ITMask.Mask = Mask;
2229 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2230 ARMOperand *Op = new ARMOperand(k_CondCode);
2237 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2238 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2239 Op->Cop.Val = CopVal;
2245 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2246 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2247 Op->Cop.Val = CopVal;
2253 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2254 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2261 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2262 ARMOperand *Op = new ARMOperand(k_CCOut);
2263 Op->Reg.RegNum = RegNum;
2269 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2270 ARMOperand *Op = new ARMOperand(k_Token);
2271 Op->Tok.Data = Str.data();
2272 Op->Tok.Length = Str.size();
2278 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2279 ARMOperand *Op = new ARMOperand(k_Register);
2280 Op->Reg.RegNum = RegNum;
2286 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2291 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2292 Op->RegShiftedReg.ShiftTy = ShTy;
2293 Op->RegShiftedReg.SrcReg = SrcReg;
2294 Op->RegShiftedReg.ShiftReg = ShiftReg;
2295 Op->RegShiftedReg.ShiftImm = ShiftImm;
2301 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2305 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2306 Op->RegShiftedImm.ShiftTy = ShTy;
2307 Op->RegShiftedImm.SrcReg = SrcReg;
2308 Op->RegShiftedImm.ShiftImm = ShiftImm;
2314 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2316 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2317 Op->ShifterImm.isASR = isASR;
2318 Op->ShifterImm.Imm = Imm;
2324 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2325 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2326 Op->RotImm.Imm = Imm;
2332 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2334 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2335 Op->Bitfield.LSB = LSB;
2336 Op->Bitfield.Width = Width;
2343 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2344 SMLoc StartLoc, SMLoc EndLoc) {
2345 assert (Regs.size() > 0 && "RegList contains no registers?");
2346 KindTy Kind = k_RegisterList;
2348 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2349 Kind = k_DPRRegisterList;
2350 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2351 contains(Regs.front().second))
2352 Kind = k_SPRRegisterList;
2354 // Sort based on the register encoding values.
2355 array_pod_sort(Regs.begin(), Regs.end());
2357 ARMOperand *Op = new ARMOperand(Kind);
2358 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2359 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2360 Op->Registers.push_back(I->second);
2361 Op->StartLoc = StartLoc;
2362 Op->EndLoc = EndLoc;
2366 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2367 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2368 ARMOperand *Op = new ARMOperand(k_VectorList);
2369 Op->VectorList.RegNum = RegNum;
2370 Op->VectorList.Count = Count;
2371 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2377 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2378 bool isDoubleSpaced,
2380 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2381 Op->VectorList.RegNum = RegNum;
2382 Op->VectorList.Count = Count;
2383 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2389 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2391 bool isDoubleSpaced,
2393 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2394 Op->VectorList.RegNum = RegNum;
2395 Op->VectorList.Count = Count;
2396 Op->VectorList.LaneIndex = Index;
2397 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2403 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2405 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2406 Op->VectorIndex.Val = Idx;
2412 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2413 ARMOperand *Op = new ARMOperand(k_Immediate);
2420 static ARMOperand *CreateMem(unsigned BaseRegNum,
2421 const MCConstantExpr *OffsetImm,
2422 unsigned OffsetRegNum,
2423 ARM_AM::ShiftOpc ShiftType,
2428 ARMOperand *Op = new ARMOperand(k_Memory);
2429 Op->Memory.BaseRegNum = BaseRegNum;
2430 Op->Memory.OffsetImm = OffsetImm;
2431 Op->Memory.OffsetRegNum = OffsetRegNum;
2432 Op->Memory.ShiftType = ShiftType;
2433 Op->Memory.ShiftImm = ShiftImm;
2434 Op->Memory.Alignment = Alignment;
2435 Op->Memory.isNegative = isNegative;
2441 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2442 ARM_AM::ShiftOpc ShiftTy,
2445 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2446 Op->PostIdxReg.RegNum = RegNum;
2447 Op->PostIdxReg.isAdd = isAdd;
2448 Op->PostIdxReg.ShiftTy = ShiftTy;
2449 Op->PostIdxReg.ShiftImm = ShiftImm;
2455 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2456 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2457 Op->MBOpt.Val = Opt;
2463 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2465 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2466 Op->ISBOpt.Val = Opt;
2472 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2473 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2474 Op->IFlags.Val = IFlags;
2480 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2481 ARMOperand *Op = new ARMOperand(k_MSRMask);
2482 Op->MMask.Val = MMask;
2489 } // end anonymous namespace.
2491 void ARMOperand::print(raw_ostream &OS) const {
2494 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2497 OS << "<ccout " << getReg() << ">";
2499 case k_ITCondMask: {
2500 static const char *const MaskStr[] = {
2501 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2502 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2504 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2505 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2509 OS << "<coprocessor number: " << getCoproc() << ">";
2512 OS << "<coprocessor register: " << getCoproc() << ">";
2514 case k_CoprocOption:
2515 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2518 OS << "<mask: " << getMSRMask() << ">";
2521 getImm()->print(OS);
2523 case k_MemBarrierOpt:
2524 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2526 case k_InstSyncBarrierOpt:
2527 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2531 << " base:" << Memory.BaseRegNum;
2534 case k_PostIndexRegister:
2535 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2536 << PostIdxReg.RegNum;
2537 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2538 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2539 << PostIdxReg.ShiftImm;
2542 case k_ProcIFlags: {
2543 OS << "<ARM_PROC::";
2544 unsigned IFlags = getProcIFlags();
2545 for (int i=2; i >= 0; --i)
2546 if (IFlags & (1 << i))
2547 OS << ARM_PROC::IFlagsToString(1 << i);
2552 OS << "<register " << getReg() << ">";
2554 case k_ShifterImmediate:
2555 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2556 << " #" << ShifterImm.Imm << ">";
2558 case k_ShiftedRegister:
2559 OS << "<so_reg_reg "
2560 << RegShiftedReg.SrcReg << " "
2561 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2562 << " " << RegShiftedReg.ShiftReg << ">";
2564 case k_ShiftedImmediate:
2565 OS << "<so_reg_imm "
2566 << RegShiftedImm.SrcReg << " "
2567 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2568 << " #" << RegShiftedImm.ShiftImm << ">";
2570 case k_RotateImmediate:
2571 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2573 case k_BitfieldDescriptor:
2574 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2575 << ", width: " << Bitfield.Width << ">";
2577 case k_RegisterList:
2578 case k_DPRRegisterList:
2579 case k_SPRRegisterList: {
2580 OS << "<register_list ";
2582 const SmallVectorImpl<unsigned> &RegList = getRegList();
2583 for (SmallVectorImpl<unsigned>::const_iterator
2584 I = RegList.begin(), E = RegList.end(); I != E; ) {
2586 if (++I < E) OS << ", ";
2593 OS << "<vector_list " << VectorList.Count << " * "
2594 << VectorList.RegNum << ">";
2596 case k_VectorListAllLanes:
2597 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2598 << VectorList.RegNum << ">";
2600 case k_VectorListIndexed:
2601 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2602 << VectorList.Count << " * " << VectorList.RegNum << ">";
2605 OS << "'" << getToken() << "'";
2608 OS << "<vectorindex " << getVectorIndex() << ">";
2613 /// @name Auto-generated Match Functions
2616 static unsigned MatchRegisterName(StringRef Name);
2620 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2621 SMLoc &StartLoc, SMLoc &EndLoc) {
2622 StartLoc = Parser.getTok().getLoc();
2623 EndLoc = Parser.getTok().getEndLoc();
2624 RegNo = tryParseRegister();
2626 return (RegNo == (unsigned)-1);
2629 /// Try to parse a register name. The token must be an Identifier when called,
2630 /// and if it is a register name the token is eaten and the register number is
2631 /// returned. Otherwise return -1.
2633 int ARMAsmParser::tryParseRegister() {
2634 const AsmToken &Tok = Parser.getTok();
2635 if (Tok.isNot(AsmToken::Identifier)) return -1;
2637 std::string lowerCase = Tok.getString().lower();
2638 unsigned RegNum = MatchRegisterName(lowerCase);
2640 RegNum = StringSwitch<unsigned>(lowerCase)
2641 .Case("r13", ARM::SP)
2642 .Case("r14", ARM::LR)
2643 .Case("r15", ARM::PC)
2644 .Case("ip", ARM::R12)
2645 // Additional register name aliases for 'gas' compatibility.
2646 .Case("a1", ARM::R0)
2647 .Case("a2", ARM::R1)
2648 .Case("a3", ARM::R2)
2649 .Case("a4", ARM::R3)
2650 .Case("v1", ARM::R4)
2651 .Case("v2", ARM::R5)
2652 .Case("v3", ARM::R6)
2653 .Case("v4", ARM::R7)
2654 .Case("v5", ARM::R8)
2655 .Case("v6", ARM::R9)
2656 .Case("v7", ARM::R10)
2657 .Case("v8", ARM::R11)
2658 .Case("sb", ARM::R9)
2659 .Case("sl", ARM::R10)
2660 .Case("fp", ARM::R11)
2664 // Check for aliases registered via .req. Canonicalize to lower case.
2665 // That's more consistent since register names are case insensitive, and
2666 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2667 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2668 // If no match, return failure.
2669 if (Entry == RegisterReqs.end())
2671 Parser.Lex(); // Eat identifier token.
2672 return Entry->getValue();
2675 Parser.Lex(); // Eat identifier token.
2680 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2681 // If a recoverable error occurs, return 1. If an irrecoverable error
2682 // occurs, return -1. An irrecoverable error is one where tokens have been
2683 // consumed in the process of trying to parse the shifter (i.e., when it is
2684 // indeed a shifter operand, but malformed).
2685 int ARMAsmParser::tryParseShiftRegister(
2686 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2687 SMLoc S = Parser.getTok().getLoc();
2688 const AsmToken &Tok = Parser.getTok();
2689 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2691 std::string lowerCase = Tok.getString().lower();
2692 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2693 .Case("asl", ARM_AM::lsl)
2694 .Case("lsl", ARM_AM::lsl)
2695 .Case("lsr", ARM_AM::lsr)
2696 .Case("asr", ARM_AM::asr)
2697 .Case("ror", ARM_AM::ror)
2698 .Case("rrx", ARM_AM::rrx)
2699 .Default(ARM_AM::no_shift);
2701 if (ShiftTy == ARM_AM::no_shift)
2704 Parser.Lex(); // Eat the operator.
2706 // The source register for the shift has already been added to the
2707 // operand list, so we need to pop it off and combine it into the shifted
2708 // register operand instead.
2709 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2710 if (!PrevOp->isReg())
2711 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2712 int SrcReg = PrevOp->getReg();
2717 if (ShiftTy == ARM_AM::rrx) {
2718 // RRX Doesn't have an explicit shift amount. The encoder expects
2719 // the shift register to be the same as the source register. Seems odd,
2723 // Figure out if this is shifted by a constant or a register (for non-RRX).
2724 if (Parser.getTok().is(AsmToken::Hash) ||
2725 Parser.getTok().is(AsmToken::Dollar)) {
2726 Parser.Lex(); // Eat hash.
2727 SMLoc ImmLoc = Parser.getTok().getLoc();
2728 const MCExpr *ShiftExpr = 0;
2729 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2730 Error(ImmLoc, "invalid immediate shift value");
2733 // The expression must be evaluatable as an immediate.
2734 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2736 Error(ImmLoc, "invalid immediate shift value");
2739 // Range check the immediate.
2740 // lsl, ror: 0 <= imm <= 31
2741 // lsr, asr: 0 <= imm <= 32
2742 Imm = CE->getValue();
2744 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2745 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2746 Error(ImmLoc, "immediate shift value out of range");
2749 // shift by zero is a nop. Always send it through as lsl.
2750 // ('as' compatibility)
2752 ShiftTy = ARM_AM::lsl;
2753 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2754 SMLoc L = Parser.getTok().getLoc();
2755 EndLoc = Parser.getTok().getEndLoc();
2756 ShiftReg = tryParseRegister();
2757 if (ShiftReg == -1) {
2758 Error (L, "expected immediate or register in shift operand");
2762 Error (Parser.getTok().getLoc(),
2763 "expected immediate or register in shift operand");
2768 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2769 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2773 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2780 /// Try to parse a register name. The token must be an Identifier when called.
2781 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2782 /// if there is a "writeback". 'true' if it's not a register.
2784 /// TODO this is likely to change to allow different register types and or to
2785 /// parse for a specific register type.
2787 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2788 const AsmToken &RegTok = Parser.getTok();
2789 int RegNo = tryParseRegister();
2793 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2794 RegTok.getEndLoc()));
2796 const AsmToken &ExclaimTok = Parser.getTok();
2797 if (ExclaimTok.is(AsmToken::Exclaim)) {
2798 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2799 ExclaimTok.getLoc()));
2800 Parser.Lex(); // Eat exclaim token
2804 // Also check for an index operand. This is only legal for vector registers,
2805 // but that'll get caught OK in operand matching, so we don't need to
2806 // explicitly filter everything else out here.
2807 if (Parser.getTok().is(AsmToken::LBrac)) {
2808 SMLoc SIdx = Parser.getTok().getLoc();
2809 Parser.Lex(); // Eat left bracket token.
2811 const MCExpr *ImmVal;
2812 if (getParser().parseExpression(ImmVal))
2814 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2816 return TokError("immediate value expected for vector index");
2818 if (Parser.getTok().isNot(AsmToken::RBrac))
2819 return Error(Parser.getTok().getLoc(), "']' expected");
2821 SMLoc E = Parser.getTok().getEndLoc();
2822 Parser.Lex(); // Eat right bracket token.
2824 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2832 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2833 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2835 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2836 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2838 switch (Name.size()) {
2841 if (Name[0] != CoprocOp)
2857 if (Name[0] != CoprocOp || Name[1] != '1')
2861 case '0': return 10;
2862 case '1': return 11;
2863 case '2': return 12;
2864 case '3': return 13;
2865 case '4': return 14;
2866 case '5': return 15;
2871 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2872 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2873 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2874 SMLoc S = Parser.getTok().getLoc();
2875 const AsmToken &Tok = Parser.getTok();
2876 if (!Tok.is(AsmToken::Identifier))
2877 return MatchOperand_NoMatch;
2878 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2879 .Case("eq", ARMCC::EQ)
2880 .Case("ne", ARMCC::NE)
2881 .Case("hs", ARMCC::HS)
2882 .Case("cs", ARMCC::HS)
2883 .Case("lo", ARMCC::LO)
2884 .Case("cc", ARMCC::LO)
2885 .Case("mi", ARMCC::MI)
2886 .Case("pl", ARMCC::PL)
2887 .Case("vs", ARMCC::VS)
2888 .Case("vc", ARMCC::VC)
2889 .Case("hi", ARMCC::HI)
2890 .Case("ls", ARMCC::LS)
2891 .Case("ge", ARMCC::GE)
2892 .Case("lt", ARMCC::LT)
2893 .Case("gt", ARMCC::GT)
2894 .Case("le", ARMCC::LE)
2895 .Case("al", ARMCC::AL)
2898 return MatchOperand_NoMatch;
2899 Parser.Lex(); // Eat the token.
2901 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2903 return MatchOperand_Success;
2906 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2907 /// token must be an Identifier when called, and if it is a coprocessor
2908 /// number, the token is eaten and the operand is added to the operand list.
2909 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2910 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2911 SMLoc S = Parser.getTok().getLoc();
2912 const AsmToken &Tok = Parser.getTok();
2913 if (Tok.isNot(AsmToken::Identifier))
2914 return MatchOperand_NoMatch;
2916 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2918 return MatchOperand_NoMatch;
2920 Parser.Lex(); // Eat identifier token.
2921 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2922 return MatchOperand_Success;
2925 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2926 /// token must be an Identifier when called, and if it is a coprocessor
2927 /// number, the token is eaten and the operand is added to the operand list.
2928 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2929 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2930 SMLoc S = Parser.getTok().getLoc();
2931 const AsmToken &Tok = Parser.getTok();
2932 if (Tok.isNot(AsmToken::Identifier))
2933 return MatchOperand_NoMatch;
2935 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2937 return MatchOperand_NoMatch;
2939 Parser.Lex(); // Eat identifier token.
2940 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2941 return MatchOperand_Success;
2944 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2945 /// coproc_option : '{' imm0_255 '}'
2946 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2947 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2948 SMLoc S = Parser.getTok().getLoc();
2950 // If this isn't a '{', this isn't a coprocessor immediate operand.
2951 if (Parser.getTok().isNot(AsmToken::LCurly))
2952 return MatchOperand_NoMatch;
2953 Parser.Lex(); // Eat the '{'
2956 SMLoc Loc = Parser.getTok().getLoc();
2957 if (getParser().parseExpression(Expr)) {
2958 Error(Loc, "illegal expression");
2959 return MatchOperand_ParseFail;
2961 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2962 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2963 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2964 return MatchOperand_ParseFail;
2966 int Val = CE->getValue();
2968 // Check for and consume the closing '}'
2969 if (Parser.getTok().isNot(AsmToken::RCurly))
2970 return MatchOperand_ParseFail;
2971 SMLoc E = Parser.getTok().getEndLoc();
2972 Parser.Lex(); // Eat the '}'
2974 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2975 return MatchOperand_Success;
2978 // For register list parsing, we need to map from raw GPR register numbering
2979 // to the enumeration values. The enumeration values aren't sorted by
2980 // register number due to our using "sp", "lr" and "pc" as canonical names.
2981 static unsigned getNextRegister(unsigned Reg) {
2982 // If this is a GPR, we need to do it manually, otherwise we can rely
2983 // on the sort ordering of the enumeration since the other reg-classes
2985 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2988 default: llvm_unreachable("Invalid GPR number!");
2989 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2990 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2991 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2992 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2993 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2994 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2995 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2996 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3000 // Return the low-subreg of a given Q register.
3001 static unsigned getDRegFromQReg(unsigned QReg) {
3003 default: llvm_unreachable("expected a Q register!");
3004 case ARM::Q0: return ARM::D0;
3005 case ARM::Q1: return ARM::D2;
3006 case ARM::Q2: return ARM::D4;
3007 case ARM::Q3: return ARM::D6;
3008 case ARM::Q4: return ARM::D8;
3009 case ARM::Q5: return ARM::D10;
3010 case ARM::Q6: return ARM::D12;
3011 case ARM::Q7: return ARM::D14;
3012 case ARM::Q8: return ARM::D16;
3013 case ARM::Q9: return ARM::D18;
3014 case ARM::Q10: return ARM::D20;
3015 case ARM::Q11: return ARM::D22;
3016 case ARM::Q12: return ARM::D24;
3017 case ARM::Q13: return ARM::D26;
3018 case ARM::Q14: return ARM::D28;
3019 case ARM::Q15: return ARM::D30;
3023 /// Parse a register list.
3025 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3026 assert(Parser.getTok().is(AsmToken::LCurly) &&
3027 "Token is not a Left Curly Brace");
3028 SMLoc S = Parser.getTok().getLoc();
3029 Parser.Lex(); // Eat '{' token.
3030 SMLoc RegLoc = Parser.getTok().getLoc();
3032 // Check the first register in the list to see what register class
3033 // this is a list of.
3034 int Reg = tryParseRegister();
3036 return Error(RegLoc, "register expected");
3038 // The reglist instructions have at most 16 registers, so reserve
3039 // space for that many.
3041 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3043 // Allow Q regs and just interpret them as the two D sub-registers.
3044 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3045 Reg = getDRegFromQReg(Reg);
3046 EReg = MRI->getEncodingValue(Reg);
3047 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3050 const MCRegisterClass *RC;
3051 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3052 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3053 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3054 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3055 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3056 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3058 return Error(RegLoc, "invalid register in register list");
3060 // Store the register.
3061 EReg = MRI->getEncodingValue(Reg);
3062 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3064 // This starts immediately after the first register token in the list,
3065 // so we can see either a comma or a minus (range separator) as a legal
3067 while (Parser.getTok().is(AsmToken::Comma) ||
3068 Parser.getTok().is(AsmToken::Minus)) {
3069 if (Parser.getTok().is(AsmToken::Minus)) {
3070 Parser.Lex(); // Eat the minus.
3071 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3072 int EndReg = tryParseRegister();
3074 return Error(AfterMinusLoc, "register expected");
3075 // Allow Q regs and just interpret them as the two D sub-registers.
3076 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3077 EndReg = getDRegFromQReg(EndReg) + 1;
3078 // If the register is the same as the start reg, there's nothing
3082 // The register must be in the same register class as the first.
3083 if (!RC->contains(EndReg))
3084 return Error(AfterMinusLoc, "invalid register in register list");
3085 // Ranges must go from low to high.
3086 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3087 return Error(AfterMinusLoc, "bad range in register list");
3089 // Add all the registers in the range to the register list.
3090 while (Reg != EndReg) {
3091 Reg = getNextRegister(Reg);
3092 EReg = MRI->getEncodingValue(Reg);
3093 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3097 Parser.Lex(); // Eat the comma.
3098 RegLoc = Parser.getTok().getLoc();
3100 const AsmToken RegTok = Parser.getTok();
3101 Reg = tryParseRegister();
3103 return Error(RegLoc, "register expected");
3104 // Allow Q regs and just interpret them as the two D sub-registers.
3105 bool isQReg = false;
3106 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3107 Reg = getDRegFromQReg(Reg);
3110 // The register must be in the same register class as the first.
3111 if (!RC->contains(Reg))
3112 return Error(RegLoc, "invalid register in register list");
3113 // List must be monotonically increasing.
3114 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3115 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3116 Warning(RegLoc, "register list not in ascending order");
3118 return Error(RegLoc, "register list not in ascending order");
3120 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3121 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3122 ") in register list");
3125 // VFP register lists must also be contiguous.
3126 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3128 return Error(RegLoc, "non-contiguous register range");
3129 EReg = MRI->getEncodingValue(Reg);
3130 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3132 EReg = MRI->getEncodingValue(++Reg);
3133 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3137 if (Parser.getTok().isNot(AsmToken::RCurly))
3138 return Error(Parser.getTok().getLoc(), "'}' expected");
3139 SMLoc E = Parser.getTok().getEndLoc();
3140 Parser.Lex(); // Eat '}' token.
3142 // Push the register list operand.
3143 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3145 // The ARM system instruction variants for LDM/STM have a '^' token here.
3146 if (Parser.getTok().is(AsmToken::Caret)) {
3147 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3148 Parser.Lex(); // Eat '^' token.
3154 // Helper function to parse the lane index for vector lists.
3155 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3156 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3157 Index = 0; // Always return a defined index value.
3158 if (Parser.getTok().is(AsmToken::LBrac)) {
3159 Parser.Lex(); // Eat the '['.
3160 if (Parser.getTok().is(AsmToken::RBrac)) {
3161 // "Dn[]" is the 'all lanes' syntax.
3162 LaneKind = AllLanes;
3163 EndLoc = Parser.getTok().getEndLoc();
3164 Parser.Lex(); // Eat the ']'.
3165 return MatchOperand_Success;
3168 // There's an optional '#' token here. Normally there wouldn't be, but
3169 // inline assemble puts one in, and it's friendly to accept that.
3170 if (Parser.getTok().is(AsmToken::Hash))
3171 Parser.Lex(); // Eat '#' or '$'.
3173 const MCExpr *LaneIndex;
3174 SMLoc Loc = Parser.getTok().getLoc();
3175 if (getParser().parseExpression(LaneIndex)) {
3176 Error(Loc, "illegal expression");
3177 return MatchOperand_ParseFail;
3179 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3181 Error(Loc, "lane index must be empty or an integer");
3182 return MatchOperand_ParseFail;
3184 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3185 Error(Parser.getTok().getLoc(), "']' expected");
3186 return MatchOperand_ParseFail;
3188 EndLoc = Parser.getTok().getEndLoc();
3189 Parser.Lex(); // Eat the ']'.
3190 int64_t Val = CE->getValue();
3192 // FIXME: Make this range check context sensitive for .8, .16, .32.
3193 if (Val < 0 || Val > 7) {
3194 Error(Parser.getTok().getLoc(), "lane index out of range");
3195 return MatchOperand_ParseFail;
3198 LaneKind = IndexedLane;
3199 return MatchOperand_Success;
3202 return MatchOperand_Success;
3205 // parse a vector register list
3206 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3207 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3208 VectorLaneTy LaneKind;
3210 SMLoc S = Parser.getTok().getLoc();
3211 // As an extension (to match gas), support a plain D register or Q register
3212 // (without encosing curly braces) as a single or double entry list,
3214 if (Parser.getTok().is(AsmToken::Identifier)) {
3215 SMLoc E = Parser.getTok().getEndLoc();
3216 int Reg = tryParseRegister();
3218 return MatchOperand_NoMatch;
3219 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3220 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3221 if (Res != MatchOperand_Success)
3225 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3228 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3232 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3237 return MatchOperand_Success;
3239 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3240 Reg = getDRegFromQReg(Reg);
3241 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3242 if (Res != MatchOperand_Success)
3246 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3247 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3248 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3251 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3252 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3253 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3257 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3262 return MatchOperand_Success;
3264 Error(S, "vector register expected");
3265 return MatchOperand_ParseFail;
3268 if (Parser.getTok().isNot(AsmToken::LCurly))
3269 return MatchOperand_NoMatch;
3271 Parser.Lex(); // Eat '{' token.
3272 SMLoc RegLoc = Parser.getTok().getLoc();
3274 int Reg = tryParseRegister();
3276 Error(RegLoc, "register expected");
3277 return MatchOperand_ParseFail;
3281 unsigned FirstReg = Reg;
3282 // The list is of D registers, but we also allow Q regs and just interpret
3283 // them as the two D sub-registers.
3284 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3285 FirstReg = Reg = getDRegFromQReg(Reg);
3286 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3287 // it's ambiguous with four-register single spaced.
3293 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3294 return MatchOperand_ParseFail;
3296 while (Parser.getTok().is(AsmToken::Comma) ||
3297 Parser.getTok().is(AsmToken::Minus)) {
3298 if (Parser.getTok().is(AsmToken::Minus)) {
3300 Spacing = 1; // Register range implies a single spaced list.
3301 else if (Spacing == 2) {
3302 Error(Parser.getTok().getLoc(),
3303 "sequential registers in double spaced list");
3304 return MatchOperand_ParseFail;
3306 Parser.Lex(); // Eat the minus.
3307 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3308 int EndReg = tryParseRegister();
3310 Error(AfterMinusLoc, "register expected");
3311 return MatchOperand_ParseFail;
3313 // Allow Q regs and just interpret them as the two D sub-registers.
3314 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3315 EndReg = getDRegFromQReg(EndReg) + 1;
3316 // If the register is the same as the start reg, there's nothing
3320 // The register must be in the same register class as the first.
3321 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3322 Error(AfterMinusLoc, "invalid register in register list");
3323 return MatchOperand_ParseFail;
3325 // Ranges must go from low to high.
3327 Error(AfterMinusLoc, "bad range in register list");
3328 return MatchOperand_ParseFail;
3330 // Parse the lane specifier if present.
3331 VectorLaneTy NextLaneKind;
3332 unsigned NextLaneIndex;
3333 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3334 MatchOperand_Success)
3335 return MatchOperand_ParseFail;
3336 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3337 Error(AfterMinusLoc, "mismatched lane index in register list");
3338 return MatchOperand_ParseFail;
3341 // Add all the registers in the range to the register list.
3342 Count += EndReg - Reg;
3346 Parser.Lex(); // Eat the comma.
3347 RegLoc = Parser.getTok().getLoc();
3349 Reg = tryParseRegister();
3351 Error(RegLoc, "register expected");
3352 return MatchOperand_ParseFail;
3354 // vector register lists must be contiguous.
3355 // It's OK to use the enumeration values directly here rather, as the
3356 // VFP register classes have the enum sorted properly.
3358 // The list is of D registers, but we also allow Q regs and just interpret
3359 // them as the two D sub-registers.
3360 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3362 Spacing = 1; // Register range implies a single spaced list.
3363 else if (Spacing == 2) {
3365 "invalid register in double-spaced list (must be 'D' register')");
3366 return MatchOperand_ParseFail;
3368 Reg = getDRegFromQReg(Reg);
3369 if (Reg != OldReg + 1) {
3370 Error(RegLoc, "non-contiguous register range");
3371 return MatchOperand_ParseFail;
3375 // Parse the lane specifier if present.
3376 VectorLaneTy NextLaneKind;
3377 unsigned NextLaneIndex;
3378 SMLoc LaneLoc = Parser.getTok().getLoc();
3379 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3380 MatchOperand_Success)
3381 return MatchOperand_ParseFail;
3382 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3383 Error(LaneLoc, "mismatched lane index in register list");
3384 return MatchOperand_ParseFail;
3388 // Normal D register.
3389 // Figure out the register spacing (single or double) of the list if
3390 // we don't know it already.
3392 Spacing = 1 + (Reg == OldReg + 2);
3394 // Just check that it's contiguous and keep going.
3395 if (Reg != OldReg + Spacing) {
3396 Error(RegLoc, "non-contiguous register range");
3397 return MatchOperand_ParseFail;
3400 // Parse the lane specifier if present.
3401 VectorLaneTy NextLaneKind;
3402 unsigned NextLaneIndex;
3403 SMLoc EndLoc = Parser.getTok().getLoc();
3404 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3405 return MatchOperand_ParseFail;
3406 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3407 Error(EndLoc, "mismatched lane index in register list");
3408 return MatchOperand_ParseFail;
3412 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3413 Error(Parser.getTok().getLoc(), "'}' expected");
3414 return MatchOperand_ParseFail;
3416 E = Parser.getTok().getEndLoc();
3417 Parser.Lex(); // Eat '}' token.
3421 // Two-register operands have been converted to the
3422 // composite register classes.
3424 const MCRegisterClass *RC = (Spacing == 1) ?
3425 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3426 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3427 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3430 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3431 (Spacing == 2), S, E));
3434 // Two-register operands have been converted to the
3435 // composite register classes.
3437 const MCRegisterClass *RC = (Spacing == 1) ?
3438 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3439 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3440 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3442 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3447 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3453 return MatchOperand_Success;
3456 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3457 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3458 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3459 SMLoc S = Parser.getTok().getLoc();
3460 const AsmToken &Tok = Parser.getTok();
3463 if (Tok.is(AsmToken::Identifier)) {
3464 StringRef OptStr = Tok.getString();
3466 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3467 .Case("sy", ARM_MB::SY)
3468 .Case("st", ARM_MB::ST)
3469 .Case("sh", ARM_MB::ISH)
3470 .Case("ish", ARM_MB::ISH)
3471 .Case("shst", ARM_MB::ISHST)
3472 .Case("ishst", ARM_MB::ISHST)
3473 .Case("nsh", ARM_MB::NSH)
3474 .Case("un", ARM_MB::NSH)
3475 .Case("nshst", ARM_MB::NSHST)
3476 .Case("unst", ARM_MB::NSHST)
3477 .Case("osh", ARM_MB::OSH)
3478 .Case("oshst", ARM_MB::OSHST)
3482 return MatchOperand_NoMatch;
3484 Parser.Lex(); // Eat identifier token.
3485 } else if (Tok.is(AsmToken::Hash) ||
3486 Tok.is(AsmToken::Dollar) ||
3487 Tok.is(AsmToken::Integer)) {
3488 if (Parser.getTok().isNot(AsmToken::Integer))
3489 Parser.Lex(); // Eat '#' or '$'.
3490 SMLoc Loc = Parser.getTok().getLoc();
3492 const MCExpr *MemBarrierID;
3493 if (getParser().parseExpression(MemBarrierID)) {
3494 Error(Loc, "illegal expression");
3495 return MatchOperand_ParseFail;
3498 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3500 Error(Loc, "constant expression expected");
3501 return MatchOperand_ParseFail;
3504 int Val = CE->getValue();
3506 Error(Loc, "immediate value out of range");
3507 return MatchOperand_ParseFail;
3510 Opt = ARM_MB::RESERVED_0 + Val;
3512 return MatchOperand_ParseFail;
3514 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3515 return MatchOperand_Success;
3518 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3519 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3520 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3521 SMLoc S = Parser.getTok().getLoc();
3522 const AsmToken &Tok = Parser.getTok();
3525 if (Tok.is(AsmToken::Identifier)) {
3526 StringRef OptStr = Tok.getString();
3528 if (OptStr.lower() == "sy")
3531 return MatchOperand_NoMatch;
3533 Parser.Lex(); // Eat identifier token.
3534 } else if (Tok.is(AsmToken::Hash) ||
3535 Tok.is(AsmToken::Dollar) ||
3536 Tok.is(AsmToken::Integer)) {
3537 if (Parser.getTok().isNot(AsmToken::Integer))
3538 Parser.Lex(); // Eat '#' or '$'.
3539 SMLoc Loc = Parser.getTok().getLoc();
3541 const MCExpr *ISBarrierID;
3542 if (getParser().parseExpression(ISBarrierID)) {
3543 Error(Loc, "illegal expression");
3544 return MatchOperand_ParseFail;
3547 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3549 Error(Loc, "constant expression expected");
3550 return MatchOperand_ParseFail;
3553 int Val = CE->getValue();
3555 Error(Loc, "immediate value out of range");
3556 return MatchOperand_ParseFail;
3559 Opt = ARM_ISB::RESERVED_0 + Val;
3561 return MatchOperand_ParseFail;
3563 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3564 (ARM_ISB::InstSyncBOpt)Opt, S));
3565 return MatchOperand_Success;
3569 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3570 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3571 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3572 SMLoc S = Parser.getTok().getLoc();
3573 const AsmToken &Tok = Parser.getTok();
3574 if (!Tok.is(AsmToken::Identifier))
3575 return MatchOperand_NoMatch;
3576 StringRef IFlagsStr = Tok.getString();
3578 // An iflags string of "none" is interpreted to mean that none of the AIF
3579 // bits are set. Not a terribly useful instruction, but a valid encoding.
3580 unsigned IFlags = 0;
3581 if (IFlagsStr != "none") {
3582 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3583 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3584 .Case("a", ARM_PROC::A)
3585 .Case("i", ARM_PROC::I)
3586 .Case("f", ARM_PROC::F)
3589 // If some specific iflag is already set, it means that some letter is
3590 // present more than once, this is not acceptable.
3591 if (Flag == ~0U || (IFlags & Flag))
3592 return MatchOperand_NoMatch;
3598 Parser.Lex(); // Eat identifier token.
3599 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3600 return MatchOperand_Success;
3603 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3604 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3605 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3606 SMLoc S = Parser.getTok().getLoc();
3607 const AsmToken &Tok = Parser.getTok();
3608 if (!Tok.is(AsmToken::Identifier))
3609 return MatchOperand_NoMatch;
3610 StringRef Mask = Tok.getString();
3613 // See ARMv6-M 10.1.1
3614 std::string Name = Mask.lower();
3615 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3616 // Note: in the documentation:
3617 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3618 // for MSR APSR_nzcvq.
3619 // but we do make it an alias here. This is so to get the "mask encoding"
3620 // bits correct on MSR APSR writes.
3622 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3623 // should really only be allowed when writing a special register. Note
3624 // they get dropped in the MRS instruction reading a special register as
3625 // the SYSm field is only 8 bits.
3627 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3628 // includes the DSP extension but that is not checked.
3629 .Case("apsr", 0x800)
3630 .Case("apsr_nzcvq", 0x800)
3631 .Case("apsr_g", 0x400)
3632 .Case("apsr_nzcvqg", 0xc00)
3633 .Case("iapsr", 0x801)
3634 .Case("iapsr_nzcvq", 0x801)
3635 .Case("iapsr_g", 0x401)
3636 .Case("iapsr_nzcvqg", 0xc01)
3637 .Case("eapsr", 0x802)
3638 .Case("eapsr_nzcvq", 0x802)
3639 .Case("eapsr_g", 0x402)
3640 .Case("eapsr_nzcvqg", 0xc02)
3641 .Case("xpsr", 0x803)
3642 .Case("xpsr_nzcvq", 0x803)
3643 .Case("xpsr_g", 0x403)
3644 .Case("xpsr_nzcvqg", 0xc03)
3645 .Case("ipsr", 0x805)
3646 .Case("epsr", 0x806)
3647 .Case("iepsr", 0x807)
3650 .Case("primask", 0x810)
3651 .Case("basepri", 0x811)
3652 .Case("basepri_max", 0x812)
3653 .Case("faultmask", 0x813)
3654 .Case("control", 0x814)
3657 if (FlagsVal == ~0U)
3658 return MatchOperand_NoMatch;
3660 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3661 // basepri, basepri_max and faultmask only valid for V7m.
3662 return MatchOperand_NoMatch;
3664 Parser.Lex(); // Eat identifier token.
3665 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3666 return MatchOperand_Success;
3669 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3670 size_t Start = 0, Next = Mask.find('_');
3671 StringRef Flags = "";
3672 std::string SpecReg = Mask.slice(Start, Next).lower();
3673 if (Next != StringRef::npos)
3674 Flags = Mask.slice(Next+1, Mask.size());
3676 // FlagsVal contains the complete mask:
3678 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3679 unsigned FlagsVal = 0;
3681 if (SpecReg == "apsr") {
3682 FlagsVal = StringSwitch<unsigned>(Flags)
3683 .Case("nzcvq", 0x8) // same as CPSR_f
3684 .Case("g", 0x4) // same as CPSR_s
3685 .Case("nzcvqg", 0xc) // same as CPSR_fs
3688 if (FlagsVal == ~0U) {
3690 return MatchOperand_NoMatch;
3692 FlagsVal = 8; // No flag
3694 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3695 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3696 if (Flags == "all" || Flags == "")
3698 for (int i = 0, e = Flags.size(); i != e; ++i) {
3699 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3706 // If some specific flag is already set, it means that some letter is
3707 // present more than once, this is not acceptable.
3708 if (FlagsVal == ~0U || (FlagsVal & Flag))
3709 return MatchOperand_NoMatch;
3712 } else // No match for special register.
3713 return MatchOperand_NoMatch;
3715 // Special register without flags is NOT equivalent to "fc" flags.
3716 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3717 // two lines would enable gas compatibility at the expense of breaking
3723 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3724 if (SpecReg == "spsr")
3727 Parser.Lex(); // Eat identifier token.
3728 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3729 return MatchOperand_Success;
3732 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3733 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3734 int Low, int High) {
3735 const AsmToken &Tok = Parser.getTok();
3736 if (Tok.isNot(AsmToken::Identifier)) {
3737 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3738 return MatchOperand_ParseFail;
3740 StringRef ShiftName = Tok.getString();
3741 std::string LowerOp = Op.lower();
3742 std::string UpperOp = Op.upper();
3743 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3744 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3745 return MatchOperand_ParseFail;
3747 Parser.Lex(); // Eat shift type token.
3749 // There must be a '#' and a shift amount.
3750 if (Parser.getTok().isNot(AsmToken::Hash) &&
3751 Parser.getTok().isNot(AsmToken::Dollar)) {
3752 Error(Parser.getTok().getLoc(), "'#' expected");
3753 return MatchOperand_ParseFail;
3755 Parser.Lex(); // Eat hash token.
3757 const MCExpr *ShiftAmount;
3758 SMLoc Loc = Parser.getTok().getLoc();
3760 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3761 Error(Loc, "illegal expression");
3762 return MatchOperand_ParseFail;
3764 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3766 Error(Loc, "constant expression expected");
3767 return MatchOperand_ParseFail;
3769 int Val = CE->getValue();
3770 if (Val < Low || Val > High) {
3771 Error(Loc, "immediate value out of range");
3772 return MatchOperand_ParseFail;
3775 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3777 return MatchOperand_Success;
3780 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3781 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3782 const AsmToken &Tok = Parser.getTok();
3783 SMLoc S = Tok.getLoc();
3784 if (Tok.isNot(AsmToken::Identifier)) {
3785 Error(S, "'be' or 'le' operand expected");
3786 return MatchOperand_ParseFail;
3788 int Val = StringSwitch<int>(Tok.getString().lower())
3792 Parser.Lex(); // Eat the token.
3795 Error(S, "'be' or 'le' operand expected");
3796 return MatchOperand_ParseFail;
3798 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3800 S, Tok.getEndLoc()));
3801 return MatchOperand_Success;
3804 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3805 /// instructions. Legal values are:
3806 /// lsl #n 'n' in [0,31]
3807 /// asr #n 'n' in [1,32]
3808 /// n == 32 encoded as n == 0.
3809 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3810 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3811 const AsmToken &Tok = Parser.getTok();
3812 SMLoc S = Tok.getLoc();
3813 if (Tok.isNot(AsmToken::Identifier)) {
3814 Error(S, "shift operator 'asr' or 'lsl' expected");
3815 return MatchOperand_ParseFail;
3817 StringRef ShiftName = Tok.getString();
3819 if (ShiftName == "lsl" || ShiftName == "LSL")
3821 else if (ShiftName == "asr" || ShiftName == "ASR")
3824 Error(S, "shift operator 'asr' or 'lsl' expected");
3825 return MatchOperand_ParseFail;
3827 Parser.Lex(); // Eat the operator.
3829 // A '#' and a shift amount.
3830 if (Parser.getTok().isNot(AsmToken::Hash) &&
3831 Parser.getTok().isNot(AsmToken::Dollar)) {
3832 Error(Parser.getTok().getLoc(), "'#' expected");
3833 return MatchOperand_ParseFail;
3835 Parser.Lex(); // Eat hash token.
3836 SMLoc ExLoc = Parser.getTok().getLoc();
3838 const MCExpr *ShiftAmount;
3840 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3841 Error(ExLoc, "malformed shift expression");
3842 return MatchOperand_ParseFail;
3844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3846 Error(ExLoc, "shift amount must be an immediate");
3847 return MatchOperand_ParseFail;
3850 int64_t Val = CE->getValue();
3852 // Shift amount must be in [1,32]
3853 if (Val < 1 || Val > 32) {
3854 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3855 return MatchOperand_ParseFail;
3857 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3858 if (isThumb() && Val == 32) {
3859 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3860 return MatchOperand_ParseFail;
3862 if (Val == 32) Val = 0;
3864 // Shift amount must be in [1,32]
3865 if (Val < 0 || Val > 31) {
3866 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3867 return MatchOperand_ParseFail;
3871 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3873 return MatchOperand_Success;
3876 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3877 /// of instructions. Legal values are:
3878 /// ror #n 'n' in {0, 8, 16, 24}
3879 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3880 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3881 const AsmToken &Tok = Parser.getTok();
3882 SMLoc S = Tok.getLoc();
3883 if (Tok.isNot(AsmToken::Identifier))
3884 return MatchOperand_NoMatch;
3885 StringRef ShiftName = Tok.getString();
3886 if (ShiftName != "ror" && ShiftName != "ROR")
3887 return MatchOperand_NoMatch;
3888 Parser.Lex(); // Eat the operator.
3890 // A '#' and a rotate amount.
3891 if (Parser.getTok().isNot(AsmToken::Hash) &&
3892 Parser.getTok().isNot(AsmToken::Dollar)) {
3893 Error(Parser.getTok().getLoc(), "'#' expected");
3894 return MatchOperand_ParseFail;
3896 Parser.Lex(); // Eat hash token.
3897 SMLoc ExLoc = Parser.getTok().getLoc();
3899 const MCExpr *ShiftAmount;
3901 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3902 Error(ExLoc, "malformed rotate expression");
3903 return MatchOperand_ParseFail;
3905 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3907 Error(ExLoc, "rotate amount must be an immediate");
3908 return MatchOperand_ParseFail;
3911 int64_t Val = CE->getValue();
3912 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3913 // normally, zero is represented in asm by omitting the rotate operand
3915 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3916 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3917 return MatchOperand_ParseFail;
3920 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3922 return MatchOperand_Success;
3925 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3926 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3927 SMLoc S = Parser.getTok().getLoc();
3928 // The bitfield descriptor is really two operands, the LSB and the width.
3929 if (Parser.getTok().isNot(AsmToken::Hash) &&
3930 Parser.getTok().isNot(AsmToken::Dollar)) {
3931 Error(Parser.getTok().getLoc(), "'#' expected");
3932 return MatchOperand_ParseFail;
3934 Parser.Lex(); // Eat hash token.
3936 const MCExpr *LSBExpr;
3937 SMLoc E = Parser.getTok().getLoc();
3938 if (getParser().parseExpression(LSBExpr)) {
3939 Error(E, "malformed immediate expression");
3940 return MatchOperand_ParseFail;
3942 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3944 Error(E, "'lsb' operand must be an immediate");
3945 return MatchOperand_ParseFail;
3948 int64_t LSB = CE->getValue();
3949 // The LSB must be in the range [0,31]
3950 if (LSB < 0 || LSB > 31) {
3951 Error(E, "'lsb' operand must be in the range [0,31]");
3952 return MatchOperand_ParseFail;
3954 E = Parser.getTok().getLoc();
3956 // Expect another immediate operand.
3957 if (Parser.getTok().isNot(AsmToken::Comma)) {
3958 Error(Parser.getTok().getLoc(), "too few operands");
3959 return MatchOperand_ParseFail;
3961 Parser.Lex(); // Eat hash token.
3962 if (Parser.getTok().isNot(AsmToken::Hash) &&
3963 Parser.getTok().isNot(AsmToken::Dollar)) {
3964 Error(Parser.getTok().getLoc(), "'#' expected");
3965 return MatchOperand_ParseFail;
3967 Parser.Lex(); // Eat hash token.
3969 const MCExpr *WidthExpr;
3971 if (getParser().parseExpression(WidthExpr, EndLoc)) {
3972 Error(E, "malformed immediate expression");
3973 return MatchOperand_ParseFail;
3975 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3977 Error(E, "'width' operand must be an immediate");
3978 return MatchOperand_ParseFail;
3981 int64_t Width = CE->getValue();
3982 // The LSB must be in the range [1,32-lsb]
3983 if (Width < 1 || Width > 32 - LSB) {
3984 Error(E, "'width' operand must be in the range [1,32-lsb]");
3985 return MatchOperand_ParseFail;
3988 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3990 return MatchOperand_Success;
3993 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3994 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3995 // Check for a post-index addressing register operand. Specifically:
3996 // postidx_reg := '+' register {, shift}
3997 // | '-' register {, shift}
3998 // | register {, shift}
4000 // This method must return MatchOperand_NoMatch without consuming any tokens
4001 // in the case where there is no match, as other alternatives take other
4003 AsmToken Tok = Parser.getTok();
4004 SMLoc S = Tok.getLoc();
4005 bool haveEaten = false;
4007 if (Tok.is(AsmToken::Plus)) {
4008 Parser.Lex(); // Eat the '+' token.
4010 } else if (Tok.is(AsmToken::Minus)) {
4011 Parser.Lex(); // Eat the '-' token.
4016 SMLoc E = Parser.getTok().getEndLoc();
4017 int Reg = tryParseRegister();
4020 return MatchOperand_NoMatch;
4021 Error(Parser.getTok().getLoc(), "register expected");
4022 return MatchOperand_ParseFail;
4025 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4026 unsigned ShiftImm = 0;
4027 if (Parser.getTok().is(AsmToken::Comma)) {
4028 Parser.Lex(); // Eat the ','.
4029 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4030 return MatchOperand_ParseFail;
4032 // FIXME: Only approximates end...may include intervening whitespace.
4033 E = Parser.getTok().getLoc();
4036 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4039 return MatchOperand_Success;
4042 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4043 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4044 // Check for a post-index addressing register operand. Specifically:
4045 // am3offset := '+' register
4052 // This method must return MatchOperand_NoMatch without consuming any tokens
4053 // in the case where there is no match, as other alternatives take other
4055 AsmToken Tok = Parser.getTok();
4056 SMLoc S = Tok.getLoc();
4058 // Do immediates first, as we always parse those if we have a '#'.
4059 if (Parser.getTok().is(AsmToken::Hash) ||
4060 Parser.getTok().is(AsmToken::Dollar)) {
4061 Parser.Lex(); // Eat '#' or '$'.
4062 // Explicitly look for a '-', as we need to encode negative zero
4064 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4065 const MCExpr *Offset;
4067 if (getParser().parseExpression(Offset, E))
4068 return MatchOperand_ParseFail;
4069 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4071 Error(S, "constant expression expected");
4072 return MatchOperand_ParseFail;
4074 // Negative zero is encoded as the flag value INT32_MIN.
4075 int32_t Val = CE->getValue();
4076 if (isNegative && Val == 0)
4080 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4082 return MatchOperand_Success;
4086 bool haveEaten = false;
4088 if (Tok.is(AsmToken::Plus)) {
4089 Parser.Lex(); // Eat the '+' token.
4091 } else if (Tok.is(AsmToken::Minus)) {
4092 Parser.Lex(); // Eat the '-' token.
4097 Tok = Parser.getTok();
4098 int Reg = tryParseRegister();
4101 return MatchOperand_NoMatch;
4102 Error(Tok.getLoc(), "register expected");
4103 return MatchOperand_ParseFail;
4106 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4107 0, S, Tok.getEndLoc()));
4109 return MatchOperand_Success;
4112 /// Convert parsed operands to MCInst. Needed here because this instruction
4113 /// only has two register operands, but multiplication is commutative so
4114 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4116 cvtThumbMultiply(MCInst &Inst,
4117 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4118 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4119 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4120 // If we have a three-operand form, make sure to set Rn to be the operand
4121 // that isn't the same as Rd.
4123 if (Operands.size() == 6 &&
4124 ((ARMOperand*)Operands[4])->getReg() ==
4125 ((ARMOperand*)Operands[3])->getReg())
4127 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4128 Inst.addOperand(Inst.getOperand(0));
4129 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4133 cvtThumbBranches(MCInst &Inst,
4134 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4135 int CondOp = -1, ImmOp = -1;
4136 switch(Inst.getOpcode()) {
4138 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4141 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4143 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4145 // first decide whether or not the branch should be conditional
4146 // by looking at it's location relative to an IT block
4148 // inside an IT block we cannot have any conditional branches. any
4149 // such instructions needs to be converted to unconditional form
4150 switch(Inst.getOpcode()) {
4151 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4152 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4155 // outside IT blocks we can only have unconditional branches with AL
4156 // condition code or conditional branches with non-AL condition code
4157 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4158 switch(Inst.getOpcode()) {
4161 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4165 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4170 // now decide on encoding size based on branch target range
4171 switch(Inst.getOpcode()) {
4172 // classify tB as either t2B or t1B based on range of immediate operand
4174 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4175 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4176 Inst.setOpcode(ARM::t2B);
4179 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4181 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4182 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4183 Inst.setOpcode(ARM::t2Bcc);
4187 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4188 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4191 /// Parse an ARM memory expression, return false if successful else return true
4192 /// or an error. The first token must be a '[' when called.
4194 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4196 assert(Parser.getTok().is(AsmToken::LBrac) &&
4197 "Token is not a Left Bracket");
4198 S = Parser.getTok().getLoc();
4199 Parser.Lex(); // Eat left bracket token.
4201 const AsmToken &BaseRegTok = Parser.getTok();
4202 int BaseRegNum = tryParseRegister();
4203 if (BaseRegNum == -1)
4204 return Error(BaseRegTok.getLoc(), "register expected");
4206 // The next token must either be a comma, a colon or a closing bracket.
4207 const AsmToken &Tok = Parser.getTok();
4208 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4209 !Tok.is(AsmToken::RBrac))
4210 return Error(Tok.getLoc(), "malformed memory operand");
4212 if (Tok.is(AsmToken::RBrac)) {
4213 E = Tok.getEndLoc();
4214 Parser.Lex(); // Eat right bracket token.
4216 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4217 0, 0, false, S, E));
4219 // If there's a pre-indexing writeback marker, '!', just add it as a token
4220 // operand. It's rather odd, but syntactically valid.
4221 if (Parser.getTok().is(AsmToken::Exclaim)) {
4222 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4223 Parser.Lex(); // Eat the '!'.
4229 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4230 "Lost colon or comma in memory operand?!");
4231 if (Tok.is(AsmToken::Comma)) {
4232 Parser.Lex(); // Eat the comma.
4235 // If we have a ':', it's an alignment specifier.
4236 if (Parser.getTok().is(AsmToken::Colon)) {
4237 Parser.Lex(); // Eat the ':'.
4238 E = Parser.getTok().getLoc();
4241 if (getParser().parseExpression(Expr))
4244 // The expression has to be a constant. Memory references with relocations
4245 // don't come through here, as they use the <label> forms of the relevant
4247 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4249 return Error (E, "constant expression expected");
4252 switch (CE->getValue()) {
4255 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4256 case 16: Align = 2; break;
4257 case 32: Align = 4; break;
4258 case 64: Align = 8; break;
4259 case 128: Align = 16; break;
4260 case 256: Align = 32; break;
4263 // Now we should have the closing ']'
4264 if (Parser.getTok().isNot(AsmToken::RBrac))
4265 return Error(Parser.getTok().getLoc(), "']' expected");
4266 E = Parser.getTok().getEndLoc();
4267 Parser.Lex(); // Eat right bracket token.
4269 // Don't worry about range checking the value here. That's handled by
4270 // the is*() predicates.
4271 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4272 ARM_AM::no_shift, 0, Align,
4275 // If there's a pre-indexing writeback marker, '!', just add it as a token
4277 if (Parser.getTok().is(AsmToken::Exclaim)) {
4278 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4279 Parser.Lex(); // Eat the '!'.
4285 // If we have a '#', it's an immediate offset, else assume it's a register
4286 // offset. Be friendly and also accept a plain integer (without a leading
4287 // hash) for gas compatibility.
4288 if (Parser.getTok().is(AsmToken::Hash) ||
4289 Parser.getTok().is(AsmToken::Dollar) ||
4290 Parser.getTok().is(AsmToken::Integer)) {
4291 if (Parser.getTok().isNot(AsmToken::Integer))
4292 Parser.Lex(); // Eat '#' or '$'.
4293 E = Parser.getTok().getLoc();
4295 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4296 const MCExpr *Offset;
4297 if (getParser().parseExpression(Offset))
4300 // The expression has to be a constant. Memory references with relocations
4301 // don't come through here, as they use the <label> forms of the relevant
4303 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4305 return Error (E, "constant expression expected");
4307 // If the constant was #-0, represent it as INT32_MIN.
4308 int32_t Val = CE->getValue();
4309 if (isNegative && Val == 0)
4310 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4312 // Now we should have the closing ']'
4313 if (Parser.getTok().isNot(AsmToken::RBrac))
4314 return Error(Parser.getTok().getLoc(), "']' expected");
4315 E = Parser.getTok().getEndLoc();
4316 Parser.Lex(); // Eat right bracket token.
4318 // Don't worry about range checking the value here. That's handled by
4319 // the is*() predicates.
4320 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4321 ARM_AM::no_shift, 0, 0,
4324 // If there's a pre-indexing writeback marker, '!', just add it as a token
4326 if (Parser.getTok().is(AsmToken::Exclaim)) {
4327 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4328 Parser.Lex(); // Eat the '!'.
4334 // The register offset is optionally preceded by a '+' or '-'
4335 bool isNegative = false;
4336 if (Parser.getTok().is(AsmToken::Minus)) {
4338 Parser.Lex(); // Eat the '-'.
4339 } else if (Parser.getTok().is(AsmToken::Plus)) {
4341 Parser.Lex(); // Eat the '+'.
4344 E = Parser.getTok().getLoc();
4345 int OffsetRegNum = tryParseRegister();
4346 if (OffsetRegNum == -1)
4347 return Error(E, "register expected");
4349 // If there's a shift operator, handle it.
4350 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4351 unsigned ShiftImm = 0;
4352 if (Parser.getTok().is(AsmToken::Comma)) {
4353 Parser.Lex(); // Eat the ','.
4354 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4358 // Now we should have the closing ']'
4359 if (Parser.getTok().isNot(AsmToken::RBrac))
4360 return Error(Parser.getTok().getLoc(), "']' expected");
4361 E = Parser.getTok().getEndLoc();
4362 Parser.Lex(); // Eat right bracket token.
4364 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4365 ShiftType, ShiftImm, 0, isNegative,
4368 // If there's a pre-indexing writeback marker, '!', just add it as a token
4370 if (Parser.getTok().is(AsmToken::Exclaim)) {
4371 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4372 Parser.Lex(); // Eat the '!'.
4378 /// parseMemRegOffsetShift - one of these two:
4379 /// ( lsl | lsr | asr | ror ) , # shift_amount
4381 /// return true if it parses a shift otherwise it returns false.
4382 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4384 SMLoc Loc = Parser.getTok().getLoc();
4385 const AsmToken &Tok = Parser.getTok();
4386 if (Tok.isNot(AsmToken::Identifier))
4388 StringRef ShiftName = Tok.getString();
4389 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4390 ShiftName == "asl" || ShiftName == "ASL")
4392 else if (ShiftName == "lsr" || ShiftName == "LSR")
4394 else if (ShiftName == "asr" || ShiftName == "ASR")
4396 else if (ShiftName == "ror" || ShiftName == "ROR")
4398 else if (ShiftName == "rrx" || ShiftName == "RRX")
4401 return Error(Loc, "illegal shift operator");
4402 Parser.Lex(); // Eat shift type token.
4404 // rrx stands alone.
4406 if (St != ARM_AM::rrx) {
4407 Loc = Parser.getTok().getLoc();
4408 // A '#' and a shift amount.
4409 const AsmToken &HashTok = Parser.getTok();
4410 if (HashTok.isNot(AsmToken::Hash) &&
4411 HashTok.isNot(AsmToken::Dollar))
4412 return Error(HashTok.getLoc(), "'#' expected");
4413 Parser.Lex(); // Eat hash token.
4416 if (getParser().parseExpression(Expr))
4418 // Range check the immediate.
4419 // lsl, ror: 0 <= imm <= 31
4420 // lsr, asr: 0 <= imm <= 32
4421 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4423 return Error(Loc, "shift amount must be an immediate");
4424 int64_t Imm = CE->getValue();
4426 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4427 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4428 return Error(Loc, "immediate shift value out of range");
4429 // If <ShiftTy> #0, turn it into a no_shift.
4432 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4441 /// parseFPImm - A floating point immediate expression operand.
4442 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4443 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4444 // Anything that can accept a floating point constant as an operand
4445 // needs to go through here, as the regular parseExpression is
4448 // This routine still creates a generic Immediate operand, containing
4449 // a bitcast of the 64-bit floating point value. The various operands
4450 // that accept floats can check whether the value is valid for them
4451 // via the standard is*() predicates.
4453 SMLoc S = Parser.getTok().getLoc();
4455 if (Parser.getTok().isNot(AsmToken::Hash) &&
4456 Parser.getTok().isNot(AsmToken::Dollar))
4457 return MatchOperand_NoMatch;
4459 // Disambiguate the VMOV forms that can accept an FP immediate.
4460 // vmov.f32 <sreg>, #imm
4461 // vmov.f64 <dreg>, #imm
4462 // vmov.f32 <dreg>, #imm @ vector f32x2
4463 // vmov.f32 <qreg>, #imm @ vector f32x4
4465 // There are also the NEON VMOV instructions which expect an
4466 // integer constant. Make sure we don't try to parse an FPImm
4468 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4469 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4470 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4471 TyOp->getToken() != ".f64"))
4472 return MatchOperand_NoMatch;
4474 Parser.Lex(); // Eat '#' or '$'.
4476 // Handle negation, as that still comes through as a separate token.
4477 bool isNegative = false;
4478 if (Parser.getTok().is(AsmToken::Minus)) {
4482 const AsmToken &Tok = Parser.getTok();
4483 SMLoc Loc = Tok.getLoc();
4484 if (Tok.is(AsmToken::Real)) {
4485 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4486 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4487 // If we had a '-' in front, toggle the sign bit.
4488 IntVal ^= (uint64_t)isNegative << 31;
4489 Parser.Lex(); // Eat the token.
4490 Operands.push_back(ARMOperand::CreateImm(
4491 MCConstantExpr::Create(IntVal, getContext()),
4492 S, Parser.getTok().getLoc()));
4493 return MatchOperand_Success;
4495 // Also handle plain integers. Instructions which allow floating point
4496 // immediates also allow a raw encoded 8-bit value.
4497 if (Tok.is(AsmToken::Integer)) {
4498 int64_t Val = Tok.getIntVal();
4499 Parser.Lex(); // Eat the token.
4500 if (Val > 255 || Val < 0) {
4501 Error(Loc, "encoded floating point value out of range");
4502 return MatchOperand_ParseFail;
4504 double RealVal = ARM_AM::getFPImmFloat(Val);
4505 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4506 Operands.push_back(ARMOperand::CreateImm(
4507 MCConstantExpr::Create(Val, getContext()), S,
4508 Parser.getTok().getLoc()));
4509 return MatchOperand_Success;
4512 Error(Loc, "invalid floating point immediate");
4513 return MatchOperand_ParseFail;
4516 /// Parse a arm instruction operand. For now this parses the operand regardless
4517 /// of the mnemonic.
4518 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4519 StringRef Mnemonic) {
4522 // Check if the current operand has a custom associated parser, if so, try to
4523 // custom parse the operand, or fallback to the general approach.
4524 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4525 if (ResTy == MatchOperand_Success)
4527 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4528 // there was a match, but an error occurred, in which case, just return that
4529 // the operand parsing failed.
4530 if (ResTy == MatchOperand_ParseFail)
4533 switch (getLexer().getKind()) {
4535 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4537 case AsmToken::Identifier: {
4538 // If we've seen a branch mnemonic, the next operand must be a label. This
4539 // is true even if the label is a register name. So "br r1" means branch to
4541 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4543 if (!tryParseRegisterWithWriteBack(Operands))
4545 int Res = tryParseShiftRegister(Operands);
4546 if (Res == 0) // success
4548 else if (Res == -1) // irrecoverable error
4550 // If this is VMRS, check for the apsr_nzcv operand.
4551 if (Mnemonic == "vmrs" &&
4552 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4553 S = Parser.getTok().getLoc();
4555 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4560 // Fall though for the Identifier case that is not a register or a
4563 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4564 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4565 case AsmToken::String: // quoted label names.
4566 case AsmToken::Dot: { // . as a branch target
4567 // This was not a register so parse other operands that start with an
4568 // identifier (like labels) as expressions and create them as immediates.
4569 const MCExpr *IdVal;
4570 S = Parser.getTok().getLoc();
4571 if (getParser().parseExpression(IdVal))
4573 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4574 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4577 case AsmToken::LBrac:
4578 return parseMemory(Operands);
4579 case AsmToken::LCurly:
4580 return parseRegisterList(Operands);
4581 case AsmToken::Dollar:
4582 case AsmToken::Hash: {
4583 // #42 -> immediate.
4584 S = Parser.getTok().getLoc();
4587 if (Parser.getTok().isNot(AsmToken::Colon)) {
4588 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4589 const MCExpr *ImmVal;
4590 if (getParser().parseExpression(ImmVal))
4592 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4594 int32_t Val = CE->getValue();
4595 if (isNegative && Val == 0)
4596 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4598 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4599 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4601 // There can be a trailing '!' on operands that we want as a separate
4602 // '!' Token operand. Handle that here. For example, the compatibilty
4603 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4604 if (Parser.getTok().is(AsmToken::Exclaim)) {
4605 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4606 Parser.getTok().getLoc()));
4607 Parser.Lex(); // Eat exclaim token
4611 // w/ a ':' after the '#', it's just like a plain ':'.
4614 case AsmToken::Colon: {
4615 // ":lower16:" and ":upper16:" expression prefixes
4616 // FIXME: Check it's an expression prefix,
4617 // e.g. (FOO - :lower16:BAR) isn't legal.
4618 ARMMCExpr::VariantKind RefKind;
4619 if (parsePrefix(RefKind))
4622 const MCExpr *SubExprVal;
4623 if (getParser().parseExpression(SubExprVal))
4626 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4628 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4629 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4635 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4636 // :lower16: and :upper16:.
4637 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4638 RefKind = ARMMCExpr::VK_ARM_None;
4640 // :lower16: and :upper16: modifiers
4641 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4642 Parser.Lex(); // Eat ':'
4644 if (getLexer().isNot(AsmToken::Identifier)) {
4645 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4649 StringRef IDVal = Parser.getTok().getIdentifier();
4650 if (IDVal == "lower16") {
4651 RefKind = ARMMCExpr::VK_ARM_LO16;
4652 } else if (IDVal == "upper16") {
4653 RefKind = ARMMCExpr::VK_ARM_HI16;
4655 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4660 if (getLexer().isNot(AsmToken::Colon)) {
4661 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4664 Parser.Lex(); // Eat the last ':'
4668 /// \brief Given a mnemonic, split out possible predication code and carry
4669 /// setting letters to form a canonical mnemonic and flags.
4671 // FIXME: Would be nice to autogen this.
4672 // FIXME: This is a bit of a maze of special cases.
4673 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4674 unsigned &PredicationCode,
4676 unsigned &ProcessorIMod,
4677 StringRef &ITMask) {
4678 PredicationCode = ARMCC::AL;
4679 CarrySetting = false;
4682 // Ignore some mnemonics we know aren't predicated forms.
4684 // FIXME: Would be nice to autogen this.
4685 if ((Mnemonic == "movs" && isThumb()) ||
4686 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4687 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4688 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4689 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4690 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4691 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4692 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4693 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4694 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4695 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4696 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4697 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4700 // First, split out any predication code. Ignore mnemonics we know aren't
4701 // predicated but do have a carry-set and so weren't caught above.
4702 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4703 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4704 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4705 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4706 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4707 .Case("eq", ARMCC::EQ)
4708 .Case("ne", ARMCC::NE)
4709 .Case("hs", ARMCC::HS)
4710 .Case("cs", ARMCC::HS)
4711 .Case("lo", ARMCC::LO)
4712 .Case("cc", ARMCC::LO)
4713 .Case("mi", ARMCC::MI)
4714 .Case("pl", ARMCC::PL)
4715 .Case("vs", ARMCC::VS)
4716 .Case("vc", ARMCC::VC)
4717 .Case("hi", ARMCC::HI)
4718 .Case("ls", ARMCC::LS)
4719 .Case("ge", ARMCC::GE)
4720 .Case("lt", ARMCC::LT)
4721 .Case("gt", ARMCC::GT)
4722 .Case("le", ARMCC::LE)
4723 .Case("al", ARMCC::AL)
4726 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4727 PredicationCode = CC;
4731 // Next, determine if we have a carry setting bit. We explicitly ignore all
4732 // the instructions we know end in 's'.
4733 if (Mnemonic.endswith("s") &&
4734 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4735 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4736 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4737 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4738 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4739 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4740 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4741 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4742 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4743 (Mnemonic == "movs" && isThumb()))) {
4744 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4745 CarrySetting = true;
4748 // The "cps" instruction can have a interrupt mode operand which is glued into
4749 // the mnemonic. Check if this is the case, split it and parse the imod op
4750 if (Mnemonic.startswith("cps")) {
4751 // Split out any imod code.
4753 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4754 .Case("ie", ARM_PROC::IE)
4755 .Case("id", ARM_PROC::ID)
4758 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4759 ProcessorIMod = IMod;
4763 // The "it" instruction has the condition mask on the end of the mnemonic.
4764 if (Mnemonic.startswith("it")) {
4765 ITMask = Mnemonic.slice(2, Mnemonic.size());
4766 Mnemonic = Mnemonic.slice(0, 2);
4772 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4773 /// inclusion of carry set or predication code operands.
4775 // FIXME: It would be nice to autogen this.
4777 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4778 bool &CanAcceptPredicationCode) {
4779 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4780 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4781 Mnemonic == "add" || Mnemonic == "adc" ||
4782 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4783 Mnemonic == "orr" || Mnemonic == "mvn" ||
4784 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4785 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4786 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4787 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4788 Mnemonic == "mla" || Mnemonic == "smlal" ||
4789 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4790 CanAcceptCarrySet = true;
4792 CanAcceptCarrySet = false;
4794 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4795 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4796 Mnemonic == "trap" || Mnemonic == "hlt" ||
4797 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4798 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4799 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4800 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4801 Mnemonic == "vrintm") {
4802 // These mnemonics are never predicable
4803 CanAcceptPredicationCode = false;
4804 } else if (!isThumb()) {
4805 // Some instructions are only predicable in Thumb mode
4806 CanAcceptPredicationCode
4807 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4808 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4809 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4810 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4811 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4812 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4813 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4814 } else if (isThumbOne()) {
4815 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4817 CanAcceptPredicationCode = true;
4820 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4821 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4822 // FIXME: This is all horribly hacky. We really need a better way to deal
4823 // with optional operands like this in the matcher table.
4825 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4826 // another does not. Specifically, the MOVW instruction does not. So we
4827 // special case it here and remove the defaulted (non-setting) cc_out
4828 // operand if that's the instruction we're trying to match.
4830 // We do this as post-processing of the explicit operands rather than just
4831 // conditionally adding the cc_out in the first place because we need
4832 // to check the type of the parsed immediate operand.
4833 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4834 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4835 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4836 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4839 // Register-register 'add' for thumb does not have a cc_out operand
4840 // when there are only two register operands.
4841 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4842 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4843 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4844 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4846 // Register-register 'add' for thumb does not have a cc_out operand
4847 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4848 // have to check the immediate range here since Thumb2 has a variant
4849 // that can handle a different range and has a cc_out operand.
4850 if (((isThumb() && Mnemonic == "add") ||
4851 (isThumbTwo() && Mnemonic == "sub")) &&
4852 Operands.size() == 6 &&
4853 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4854 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4855 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4856 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4857 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4858 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4860 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4861 // imm0_4095 variant. That's the least-preferred variant when
4862 // selecting via the generic "add" mnemonic, so to know that we
4863 // should remove the cc_out operand, we have to explicitly check that
4864 // it's not one of the other variants. Ugh.
4865 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4866 Operands.size() == 6 &&
4867 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4868 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4869 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4870 // Nest conditions rather than one big 'if' statement for readability.
4872 // If both registers are low, we're in an IT block, and the immediate is
4873 // in range, we should use encoding T1 instead, which has a cc_out.
4875 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4876 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4877 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4879 // Check against T3. If the second register is the PC, this is an
4880 // alternate form of ADR, which uses encoding T4, so check for that too.
4881 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4882 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4885 // Otherwise, we use encoding T4, which does not have a cc_out
4890 // The thumb2 multiply instruction doesn't have a CCOut register, so
4891 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4892 // use the 16-bit encoding or not.
4893 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4894 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4895 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4896 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4897 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4898 // If the registers aren't low regs, the destination reg isn't the
4899 // same as one of the source regs, or the cc_out operand is zero
4900 // outside of an IT block, we have to use the 32-bit encoding, so
4901 // remove the cc_out operand.
4902 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4903 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4904 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4906 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4907 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4908 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4909 static_cast<ARMOperand*>(Operands[4])->getReg())))
4912 // Also check the 'mul' syntax variant that doesn't specify an explicit
4913 // destination register.
4914 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4915 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4916 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4917 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4918 // If the registers aren't low regs or the cc_out operand is zero
4919 // outside of an IT block, we have to use the 32-bit encoding, so
4920 // remove the cc_out operand.
4921 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4922 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4928 // Register-register 'add/sub' for thumb does not have a cc_out operand
4929 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4930 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4931 // right, this will result in better diagnostics (which operand is off)
4933 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4934 (Operands.size() == 5 || Operands.size() == 6) &&
4935 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4936 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4937 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4938 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4939 (Operands.size() == 6 &&
4940 static_cast<ARMOperand*>(Operands[5])->isImm())))
4946 bool ARMAsmParser::shouldOmitPredicateOperand(
4947 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
4948 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
4949 unsigned RegIdx = 3;
4950 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
4951 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
4952 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
4953 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
4956 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
4957 (ARMMCRegisterClasses[ARM::DPRRegClassID]
4958 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
4959 ARMMCRegisterClasses[ARM::QPRRegClassID]
4960 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
4966 bool ARMAsmParser::isDeprecated(MCInst &Inst, StringRef &Info) {
4967 if (hasV8Ops() && Inst.getOpcode() == ARM::SETEND) {
4974 static bool isDataTypeToken(StringRef Tok) {
4975 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4976 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4977 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4978 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4979 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4980 Tok == ".f" || Tok == ".d";
4983 // FIXME: This bit should probably be handled via an explicit match class
4984 // in the .td files that matches the suffix instead of having it be
4985 // a literal string token the way it is now.
4986 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4987 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4989 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
4990 unsigned VariantID);
4991 /// Parse an arm instruction mnemonic followed by its operands.
4992 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
4994 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4995 // Apply mnemonic aliases before doing anything else, as the destination
4996 // mnemnonic may include suffices and we want to handle them normally.
4997 // The generic tblgen'erated code does this later, at the start of
4998 // MatchInstructionImpl(), but that's too late for aliases that include
4999 // any sort of suffix.
5000 unsigned AvailableFeatures = getAvailableFeatures();
5001 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5002 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5004 // First check for the ARM-specific .req directive.
5005 if (Parser.getTok().is(AsmToken::Identifier) &&
5006 Parser.getTok().getIdentifier() == ".req") {
5007 parseDirectiveReq(Name, NameLoc);
5008 // We always return 'error' for this, as we're done with this
5009 // statement and don't need to match the 'instruction."
5013 // Create the leading tokens for the mnemonic, split by '.' characters.
5014 size_t Start = 0, Next = Name.find('.');
5015 StringRef Mnemonic = Name.slice(Start, Next);
5017 // Split out the predication code and carry setting flag from the mnemonic.
5018 unsigned PredicationCode;
5019 unsigned ProcessorIMod;
5022 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5023 ProcessorIMod, ITMask);
5025 // In Thumb1, only the branch (B) instruction can be predicated.
5026 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5027 Parser.eatToEndOfStatement();
5028 return Error(NameLoc, "conditional execution not supported in Thumb1");
5031 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5033 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5034 // is the mask as it will be for the IT encoding if the conditional
5035 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5036 // where the conditional bit0 is zero, the instruction post-processing
5037 // will adjust the mask accordingly.
5038 if (Mnemonic == "it") {
5039 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5040 if (ITMask.size() > 3) {
5041 Parser.eatToEndOfStatement();
5042 return Error(Loc, "too many conditions on IT instruction");
5045 for (unsigned i = ITMask.size(); i != 0; --i) {
5046 char pos = ITMask[i - 1];
5047 if (pos != 't' && pos != 'e') {
5048 Parser.eatToEndOfStatement();
5049 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5052 if (ITMask[i - 1] == 't')
5055 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5058 // FIXME: This is all a pretty gross hack. We should automatically handle
5059 // optional operands like this via tblgen.
5061 // Next, add the CCOut and ConditionCode operands, if needed.
5063 // For mnemonics which can ever incorporate a carry setting bit or predication
5064 // code, our matching model involves us always generating CCOut and
5065 // ConditionCode operands to match the mnemonic "as written" and then we let
5066 // the matcher deal with finding the right instruction or generating an
5067 // appropriate error.
5068 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5069 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5071 // If we had a carry-set on an instruction that can't do that, issue an
5073 if (!CanAcceptCarrySet && CarrySetting) {
5074 Parser.eatToEndOfStatement();
5075 return Error(NameLoc, "instruction '" + Mnemonic +
5076 "' can not set flags, but 's' suffix specified");
5078 // If we had a predication code on an instruction that can't do that, issue an
5080 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5081 Parser.eatToEndOfStatement();
5082 return Error(NameLoc, "instruction '" + Mnemonic +
5083 "' is not predicable, but condition code specified");
5086 // Add the carry setting operand, if necessary.
5087 if (CanAcceptCarrySet) {
5088 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5089 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5093 // Add the predication code operand, if necessary.
5094 if (CanAcceptPredicationCode) {
5095 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5097 Operands.push_back(ARMOperand::CreateCondCode(
5098 ARMCC::CondCodes(PredicationCode), Loc));
5101 // Add the processor imod operand, if necessary.
5102 if (ProcessorIMod) {
5103 Operands.push_back(ARMOperand::CreateImm(
5104 MCConstantExpr::Create(ProcessorIMod, getContext()),
5108 // Add the remaining tokens in the mnemonic.
5109 while (Next != StringRef::npos) {
5111 Next = Name.find('.', Start + 1);
5112 StringRef ExtraToken = Name.slice(Start, Next);
5114 // Some NEON instructions have an optional datatype suffix that is
5115 // completely ignored. Check for that.
5116 if (isDataTypeToken(ExtraToken) &&
5117 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5120 // For for ARM mode generate an error if the .n qualifier is used.
5121 if (ExtraToken == ".n" && !isThumb()) {
5122 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5123 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5127 // The .n qualifier is always discarded as that is what the tables
5128 // and matcher expect. In ARM mode the .w qualifier has no effect,
5129 // so discard it to avoid errors that can be caused by the matcher.
5130 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5131 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5132 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5136 // Read the remaining operands.
5137 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5138 // Read the first operand.
5139 if (parseOperand(Operands, Mnemonic)) {
5140 Parser.eatToEndOfStatement();
5144 while (getLexer().is(AsmToken::Comma)) {
5145 Parser.Lex(); // Eat the comma.
5147 // Parse and remember the operand.
5148 if (parseOperand(Operands, Mnemonic)) {
5149 Parser.eatToEndOfStatement();
5155 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5156 SMLoc Loc = getLexer().getLoc();
5157 Parser.eatToEndOfStatement();
5158 return Error(Loc, "unexpected token in argument list");
5161 Parser.Lex(); // Consume the EndOfStatement
5163 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5164 // do and don't have a cc_out optional-def operand. With some spot-checks
5165 // of the operand list, we can figure out which variant we're trying to
5166 // parse and adjust accordingly before actually matching. We shouldn't ever
5167 // try to remove a cc_out operand that was explicitly set on the the
5168 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5169 // table driven matcher doesn't fit well with the ARM instruction set.
5170 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5171 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5172 Operands.erase(Operands.begin() + 1);
5176 // Some instructions have the same mnemonic, but don't always
5177 // have a predicate. Distinguish them here and delete the
5178 // predicate if needed.
5179 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5180 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5181 Operands.erase(Operands.begin() + 1);
5185 // ARM mode 'blx' need special handling, as the register operand version
5186 // is predicable, but the label operand version is not. So, we can't rely
5187 // on the Mnemonic based checking to correctly figure out when to put
5188 // a k_CondCode operand in the list. If we're trying to match the label
5189 // version, remove the k_CondCode operand here.
5190 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5191 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5192 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5193 Operands.erase(Operands.begin() + 1);
5197 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5198 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5199 // a single GPRPair reg operand is used in the .td file to replace the two
5200 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5201 // expressed as a GPRPair, so we have to manually merge them.
5202 // FIXME: We would really like to be able to tablegen'erate this.
5203 if (!isThumb() && Operands.size() > 4 &&
5204 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5205 Mnemonic == "stlexd")) {
5206 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5207 unsigned Idx = isLoad ? 2 : 3;
5208 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5209 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5211 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5212 // Adjust only if Op1 and Op2 are GPRs.
5213 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5214 MRC.contains(Op2->getReg())) {
5215 unsigned Reg1 = Op1->getReg();
5216 unsigned Reg2 = Op2->getReg();
5217 unsigned Rt = MRI->getEncodingValue(Reg1);
5218 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5220 // Rt2 must be Rt + 1 and Rt must be even.
5221 if (Rt + 1 != Rt2 || (Rt & 1)) {
5222 Error(Op2->getStartLoc(), isLoad ?
5223 "destination operands must be sequential" :
5224 "source operands must be sequential");
5227 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5228 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5229 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5230 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5231 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5237 // FIXME: As said above, this is all a pretty gross hack. This instruction
5238 // does not fit with other "subs" and tblgen.
5239 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5240 // so the Mnemonic is the original name "subs" and delete the predicate
5241 // operand so it will match the table entry.
5242 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5243 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5244 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5245 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5246 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5247 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5248 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5249 Operands.erase(Operands.begin());
5251 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5253 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5254 Operands.erase(Operands.begin() + 1);
5260 // Validate context-sensitive operand constraints.
5262 // return 'true' if register list contains non-low GPR registers,
5263 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5264 // 'containsReg' to true.
5265 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5266 unsigned HiReg, bool &containsReg) {
5267 containsReg = false;
5268 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5269 unsigned OpReg = Inst.getOperand(i).getReg();
5272 // Anything other than a low register isn't legal here.
5273 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5279 // Check if the specified regisgter is in the register list of the inst,
5280 // starting at the indicated operand number.
5281 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5282 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5283 unsigned OpReg = Inst.getOperand(i).getReg();
5290 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5291 // the ARMInsts array) instead. Getting that here requires awkward
5292 // API changes, though. Better way?
5294 extern const MCInstrDesc ARMInsts[];
5296 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5297 return ARMInsts[Opcode];
5300 // Return true if instruction has the interesting property of being
5301 // allowed in IT blocks, but not being predicable.
5302 static bool instIsBreakpoint(const MCInst &Inst) {
5303 return Inst.getOpcode() == ARM::tBKPT ||
5304 Inst.getOpcode() == ARM::BKPT ||
5305 Inst.getOpcode() == ARM::tHLT ||
5306 Inst.getOpcode() == ARM::HLT;
5310 // FIXME: We would really like to be able to tablegen'erate this.
5312 validateInstruction(MCInst &Inst,
5313 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5314 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5315 SMLoc Loc = Operands[0]->getStartLoc();
5317 // Check the IT block state first.
5318 // NOTE: BKPT and HLT instructions have the interesting property of being
5319 // allowed in IT blocks, but not being predicable. They just always
5321 if (inITBlock() && !instIsBreakpoint(Inst)) {
5323 if (ITState.FirstCond)
5324 ITState.FirstCond = false;
5326 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5327 // The instruction must be predicable.
5328 if (!MCID.isPredicable())
5329 return Error(Loc, "instructions in IT block must be predicable");
5330 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5331 unsigned ITCond = bit ? ITState.Cond :
5332 ARMCC::getOppositeCondition(ITState.Cond);
5333 if (Cond != ITCond) {
5334 // Find the condition code Operand to get its SMLoc information.
5336 for (unsigned i = 1; i < Operands.size(); ++i)
5337 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5338 CondLoc = Operands[i]->getStartLoc();
5339 return Error(CondLoc, "incorrect condition in IT block; got '" +
5340 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5341 "', but expected '" +
5342 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5344 // Check for non-'al' condition codes outside of the IT block.
5345 } else if (isThumbTwo() && MCID.isPredicable() &&
5346 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5347 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5348 Inst.getOpcode() != ARM::t2Bcc)
5349 return Error(Loc, "predicated instructions must be in IT block");
5351 switch (Inst.getOpcode()) {
5354 case ARM::LDRD_POST: {
5355 // Rt2 must be Rt + 1.
5356 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5357 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5359 return Error(Operands[3]->getStartLoc(),
5360 "destination operands must be sequential");
5364 // Rt2 must be Rt + 1.
5365 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5366 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5368 return Error(Operands[3]->getStartLoc(),
5369 "source operands must be sequential");
5373 case ARM::STRD_POST: {
5374 // Rt2 must be Rt + 1.
5375 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5376 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5378 return Error(Operands[3]->getStartLoc(),
5379 "source operands must be sequential");
5384 // width must be in range [1, 32-lsb]
5385 unsigned lsb = Inst.getOperand(2).getImm();
5386 unsigned widthm1 = Inst.getOperand(3).getImm();
5387 if (widthm1 >= 32 - lsb)
5388 return Error(Operands[5]->getStartLoc(),
5389 "bitfield width must be in range [1,32-lsb]");
5393 // If we're parsing Thumb2, the .w variant is available and handles
5394 // most cases that are normally illegal for a Thumb1 LDM
5395 // instruction. We'll make the transformation in processInstruction()
5398 // Thumb LDM instructions are writeback iff the base register is not
5399 // in the register list.
5400 unsigned Rn = Inst.getOperand(0).getReg();
5401 bool hasWritebackToken =
5402 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5403 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5404 bool listContainsBase;
5405 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5406 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5407 "registers must be in range r0-r7");
5408 // If we should have writeback, then there should be a '!' token.
5409 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5410 return Error(Operands[2]->getStartLoc(),
5411 "writeback operator '!' expected");
5412 // If we should not have writeback, there must not be a '!'. This is
5413 // true even for the 32-bit wide encodings.
5414 if (listContainsBase && hasWritebackToken)
5415 return Error(Operands[3]->getStartLoc(),
5416 "writeback operator '!' not allowed when base register "
5417 "in register list");
5421 case ARM::t2LDMIA_UPD: {
5422 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5423 return Error(Operands[4]->getStartLoc(),
5424 "writeback operator '!' not allowed when base register "
5425 "in register list");
5429 // The second source operand must be the same register as the destination
5432 // In this case, we must directly check the parsed operands because the
5433 // cvtThumbMultiply() function is written in such a way that it guarantees
5434 // this first statement is always true for the new Inst. Essentially, the
5435 // destination is unconditionally copied into the second source operand
5436 // without checking to see if it matches what we actually parsed.
5437 if (Operands.size() == 6 &&
5438 (((ARMOperand*)Operands[3])->getReg() !=
5439 ((ARMOperand*)Operands[5])->getReg()) &&
5440 (((ARMOperand*)Operands[3])->getReg() !=
5441 ((ARMOperand*)Operands[4])->getReg())) {
5442 return Error(Operands[3]->getStartLoc(),
5443 "destination register must match source register");
5447 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5448 // so only issue a diagnostic for thumb1. The instructions will be
5449 // switched to the t2 encodings in processInstruction() if necessary.
5451 bool listContainsBase;
5452 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5454 return Error(Operands[2]->getStartLoc(),
5455 "registers must be in range r0-r7 or pc");
5459 bool listContainsBase;
5460 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5462 return Error(Operands[2]->getStartLoc(),
5463 "registers must be in range r0-r7 or lr");
5466 case ARM::tSTMIA_UPD: {
5467 bool listContainsBase;
5468 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5469 return Error(Operands[4]->getStartLoc(),
5470 "registers must be in range r0-r7");
5473 case ARM::tADDrSP: {
5474 // If the non-SP source operand and the destination operand are not the
5475 // same, we need thumb2 (for the wide encoding), or we have an error.
5476 if (!isThumbTwo() &&
5477 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5478 return Error(Operands[4]->getStartLoc(),
5479 "source register must be the same as destination");
5483 // final range checking for Thumb unconditional branch instructions
5485 if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5486 return Error(Operands[2]->getStartLoc(), "Branch target out of range");
5489 int op = (Operands[2]->isImm()) ? 2 : 3;
5490 if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5491 return Error(Operands[op]->getStartLoc(), "Branch target out of range");
5494 // final range checking for Thumb conditional branch instructions
5496 if(!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5497 return Error(Operands[2]->getStartLoc(), "Branch target out of range");
5500 int op = (Operands[2]->isImm()) ? 2 : 3;
5501 if(!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<20, 1>())
5502 return Error(Operands[op]->getStartLoc(), "Branch target out of range");
5508 if (isDeprecated(Inst, DepInfo))
5509 Warning(Loc, "deprecated on " + DepInfo);
5514 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5516 default: llvm_unreachable("unexpected opcode!");
5518 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5519 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5520 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5521 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5522 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5523 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5524 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5525 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5526 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5529 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5530 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5531 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5532 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5533 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5535 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5536 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5537 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5538 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5539 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5541 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5542 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5543 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5544 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5545 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5548 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5549 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5550 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5551 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5552 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5553 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5554 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5555 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5556 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5557 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5558 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5559 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5560 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5561 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5562 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5565 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5566 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5567 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5568 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5569 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5570 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5571 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5572 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5573 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5574 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5575 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5576 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5577 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5578 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5579 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5580 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5581 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5582 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5585 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5586 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5587 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5588 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5589 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5590 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5591 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5592 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5593 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5594 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5595 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5596 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5597 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5598 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5599 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5602 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5603 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5604 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5605 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5606 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5607 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5608 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5609 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5610 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5611 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5612 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5613 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5614 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5615 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5616 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5617 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5618 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5619 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5623 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5625 default: llvm_unreachable("unexpected opcode!");
5627 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5628 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5629 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5630 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5631 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5632 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5633 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5634 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5635 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5638 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5639 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5640 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5641 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5642 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5643 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5644 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5645 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5646 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5647 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5648 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5649 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5650 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5651 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5652 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5655 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5656 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5657 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5658 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5659 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5660 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5661 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5662 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5663 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5664 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5665 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5666 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5667 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5668 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5669 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5670 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5671 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5672 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5675 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5676 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5677 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5678 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5679 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5680 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5681 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5682 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5683 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5684 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5685 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5686 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5687 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5688 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5689 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5692 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5693 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5694 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5695 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5696 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5697 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5698 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5699 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5700 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5701 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5702 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5703 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5704 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5705 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5706 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5707 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5708 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5709 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5712 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5713 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5714 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5715 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5716 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5717 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5718 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5719 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5720 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5721 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5722 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5723 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5724 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5725 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5726 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5729 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5730 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5731 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5732 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5733 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5734 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5735 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5736 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5737 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5738 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5739 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5740 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5741 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5742 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5743 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5744 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5745 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5746 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5749 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5750 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5751 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5752 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5753 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5754 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5755 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5756 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5757 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5758 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5759 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5760 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5761 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5762 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5763 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5764 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5765 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5766 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5771 processInstruction(MCInst &Inst,
5772 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5773 switch (Inst.getOpcode()) {
5774 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5776 if (Inst.getOperand(1).getReg() != ARM::PC ||
5777 Inst.getOperand(5).getReg() != 0)
5780 TmpInst.setOpcode(ARM::ADR);
5781 TmpInst.addOperand(Inst.getOperand(0));
5782 TmpInst.addOperand(Inst.getOperand(2));
5783 TmpInst.addOperand(Inst.getOperand(3));
5784 TmpInst.addOperand(Inst.getOperand(4));
5788 // Aliases for alternate PC+imm syntax of LDR instructions.
5789 case ARM::t2LDRpcrel:
5790 // Select the narrow version if the immediate will fit.
5791 if (Inst.getOperand(1).getImm() > 0 &&
5792 Inst.getOperand(1).getImm() <= 0xff &&
5793 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
5794 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
5795 Inst.setOpcode(ARM::tLDRpci);
5797 Inst.setOpcode(ARM::t2LDRpci);
5799 case ARM::t2LDRBpcrel:
5800 Inst.setOpcode(ARM::t2LDRBpci);
5802 case ARM::t2LDRHpcrel:
5803 Inst.setOpcode(ARM::t2LDRHpci);
5805 case ARM::t2LDRSBpcrel:
5806 Inst.setOpcode(ARM::t2LDRSBpci);
5808 case ARM::t2LDRSHpcrel:
5809 Inst.setOpcode(ARM::t2LDRSHpci);
5811 // Handle NEON VST complex aliases.
5812 case ARM::VST1LNdWB_register_Asm_8:
5813 case ARM::VST1LNdWB_register_Asm_16:
5814 case ARM::VST1LNdWB_register_Asm_32: {
5816 // Shuffle the operands around so the lane index operand is in the
5819 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5820 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5821 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5822 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5823 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5824 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5825 TmpInst.addOperand(Inst.getOperand(1)); // lane
5826 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5827 TmpInst.addOperand(Inst.getOperand(6));
5832 case ARM::VST2LNdWB_register_Asm_8:
5833 case ARM::VST2LNdWB_register_Asm_16:
5834 case ARM::VST2LNdWB_register_Asm_32:
5835 case ARM::VST2LNqWB_register_Asm_16:
5836 case ARM::VST2LNqWB_register_Asm_32: {
5838 // Shuffle the operands around so the lane index operand is in the
5841 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5842 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5843 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5844 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5845 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5846 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5847 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5849 TmpInst.addOperand(Inst.getOperand(1)); // lane
5850 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5851 TmpInst.addOperand(Inst.getOperand(6));
5856 case ARM::VST3LNdWB_register_Asm_8:
5857 case ARM::VST3LNdWB_register_Asm_16:
5858 case ARM::VST3LNdWB_register_Asm_32:
5859 case ARM::VST3LNqWB_register_Asm_16:
5860 case ARM::VST3LNqWB_register_Asm_32: {
5862 // Shuffle the operands around so the lane index operand is in the
5865 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5866 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5867 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5868 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5869 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5870 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5871 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5873 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5875 TmpInst.addOperand(Inst.getOperand(1)); // lane
5876 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5877 TmpInst.addOperand(Inst.getOperand(6));
5882 case ARM::VST4LNdWB_register_Asm_8:
5883 case ARM::VST4LNdWB_register_Asm_16:
5884 case ARM::VST4LNdWB_register_Asm_32:
5885 case ARM::VST4LNqWB_register_Asm_16:
5886 case ARM::VST4LNqWB_register_Asm_32: {
5888 // Shuffle the operands around so the lane index operand is in the
5891 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5892 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5893 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5894 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5895 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5896 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5897 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5899 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5901 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5903 TmpInst.addOperand(Inst.getOperand(1)); // lane
5904 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5905 TmpInst.addOperand(Inst.getOperand(6));
5910 case ARM::VST1LNdWB_fixed_Asm_8:
5911 case ARM::VST1LNdWB_fixed_Asm_16:
5912 case ARM::VST1LNdWB_fixed_Asm_32: {
5914 // Shuffle the operands around so the lane index operand is in the
5917 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5918 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5919 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5920 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5921 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5922 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5923 TmpInst.addOperand(Inst.getOperand(1)); // lane
5924 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5925 TmpInst.addOperand(Inst.getOperand(5));
5930 case ARM::VST2LNdWB_fixed_Asm_8:
5931 case ARM::VST2LNdWB_fixed_Asm_16:
5932 case ARM::VST2LNdWB_fixed_Asm_32:
5933 case ARM::VST2LNqWB_fixed_Asm_16:
5934 case ARM::VST2LNqWB_fixed_Asm_32: {
5936 // Shuffle the operands around so the lane index operand is in the
5939 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5940 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5941 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5942 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5943 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5944 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5945 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5947 TmpInst.addOperand(Inst.getOperand(1)); // lane
5948 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5949 TmpInst.addOperand(Inst.getOperand(5));
5954 case ARM::VST3LNdWB_fixed_Asm_8:
5955 case ARM::VST3LNdWB_fixed_Asm_16:
5956 case ARM::VST3LNdWB_fixed_Asm_32:
5957 case ARM::VST3LNqWB_fixed_Asm_16:
5958 case ARM::VST3LNqWB_fixed_Asm_32: {
5960 // Shuffle the operands around so the lane index operand is in the
5963 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5964 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5965 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5966 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5967 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5968 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5969 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5971 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5973 TmpInst.addOperand(Inst.getOperand(1)); // lane
5974 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5975 TmpInst.addOperand(Inst.getOperand(5));
5980 case ARM::VST4LNdWB_fixed_Asm_8:
5981 case ARM::VST4LNdWB_fixed_Asm_16:
5982 case ARM::VST4LNdWB_fixed_Asm_32:
5983 case ARM::VST4LNqWB_fixed_Asm_16:
5984 case ARM::VST4LNqWB_fixed_Asm_32: {
5986 // Shuffle the operands around so the lane index operand is in the
5989 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5990 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5991 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5992 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5993 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5994 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5995 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5997 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5999 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6001 TmpInst.addOperand(Inst.getOperand(1)); // lane
6002 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6003 TmpInst.addOperand(Inst.getOperand(5));
6008 case ARM::VST1LNdAsm_8:
6009 case ARM::VST1LNdAsm_16:
6010 case ARM::VST1LNdAsm_32: {
6012 // Shuffle the operands around so the lane index operand is in the
6015 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6016 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6017 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6018 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6019 TmpInst.addOperand(Inst.getOperand(1)); // lane
6020 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6021 TmpInst.addOperand(Inst.getOperand(5));
6026 case ARM::VST2LNdAsm_8:
6027 case ARM::VST2LNdAsm_16:
6028 case ARM::VST2LNdAsm_32:
6029 case ARM::VST2LNqAsm_16:
6030 case ARM::VST2LNqAsm_32: {
6032 // Shuffle the operands around so the lane index operand is in the
6035 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6036 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6037 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6038 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6039 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6041 TmpInst.addOperand(Inst.getOperand(1)); // lane
6042 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6043 TmpInst.addOperand(Inst.getOperand(5));
6048 case ARM::VST3LNdAsm_8:
6049 case ARM::VST3LNdAsm_16:
6050 case ARM::VST3LNdAsm_32:
6051 case ARM::VST3LNqAsm_16:
6052 case ARM::VST3LNqAsm_32: {
6054 // Shuffle the operands around so the lane index operand is in the
6057 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6058 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6059 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6060 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6061 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6063 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6065 TmpInst.addOperand(Inst.getOperand(1)); // lane
6066 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6067 TmpInst.addOperand(Inst.getOperand(5));
6072 case ARM::VST4LNdAsm_8:
6073 case ARM::VST4LNdAsm_16:
6074 case ARM::VST4LNdAsm_32:
6075 case ARM::VST4LNqAsm_16:
6076 case ARM::VST4LNqAsm_32: {
6078 // Shuffle the operands around so the lane index operand is in the
6081 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6082 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6083 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6084 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6085 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6087 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6089 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6091 TmpInst.addOperand(Inst.getOperand(1)); // lane
6092 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6093 TmpInst.addOperand(Inst.getOperand(5));
6098 // Handle NEON VLD complex aliases.
6099 case ARM::VLD1LNdWB_register_Asm_8:
6100 case ARM::VLD1LNdWB_register_Asm_16:
6101 case ARM::VLD1LNdWB_register_Asm_32: {
6103 // Shuffle the operands around so the lane index operand is in the
6106 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6107 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6108 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6109 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6110 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6111 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6112 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6113 TmpInst.addOperand(Inst.getOperand(1)); // lane
6114 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6115 TmpInst.addOperand(Inst.getOperand(6));
6120 case ARM::VLD2LNdWB_register_Asm_8:
6121 case ARM::VLD2LNdWB_register_Asm_16:
6122 case ARM::VLD2LNdWB_register_Asm_32:
6123 case ARM::VLD2LNqWB_register_Asm_16:
6124 case ARM::VLD2LNqWB_register_Asm_32: {
6126 // Shuffle the operands around so the lane index operand is in the
6129 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6130 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6131 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6133 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6134 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6135 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6136 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6137 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6138 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6140 TmpInst.addOperand(Inst.getOperand(1)); // lane
6141 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6142 TmpInst.addOperand(Inst.getOperand(6));
6147 case ARM::VLD3LNdWB_register_Asm_8:
6148 case ARM::VLD3LNdWB_register_Asm_16:
6149 case ARM::VLD3LNdWB_register_Asm_32:
6150 case ARM::VLD3LNqWB_register_Asm_16:
6151 case ARM::VLD3LNqWB_register_Asm_32: {
6153 // Shuffle the operands around so the lane index operand is in the
6156 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6157 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6158 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6160 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6162 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6163 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6164 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6165 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6166 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6167 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6169 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6171 TmpInst.addOperand(Inst.getOperand(1)); // lane
6172 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6173 TmpInst.addOperand(Inst.getOperand(6));
6178 case ARM::VLD4LNdWB_register_Asm_8:
6179 case ARM::VLD4LNdWB_register_Asm_16:
6180 case ARM::VLD4LNdWB_register_Asm_32:
6181 case ARM::VLD4LNqWB_register_Asm_16:
6182 case ARM::VLD4LNqWB_register_Asm_32: {
6184 // Shuffle the operands around so the lane index operand is in the
6187 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6188 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6189 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6191 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6193 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6195 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6196 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6197 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6198 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6199 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6200 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6202 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6204 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6206 TmpInst.addOperand(Inst.getOperand(1)); // lane
6207 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6208 TmpInst.addOperand(Inst.getOperand(6));
6213 case ARM::VLD1LNdWB_fixed_Asm_8:
6214 case ARM::VLD1LNdWB_fixed_Asm_16:
6215 case ARM::VLD1LNdWB_fixed_Asm_32: {
6217 // Shuffle the operands around so the lane index operand is in the
6220 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6221 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6222 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6223 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6224 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6225 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6226 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6227 TmpInst.addOperand(Inst.getOperand(1)); // lane
6228 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6229 TmpInst.addOperand(Inst.getOperand(5));
6234 case ARM::VLD2LNdWB_fixed_Asm_8:
6235 case ARM::VLD2LNdWB_fixed_Asm_16:
6236 case ARM::VLD2LNdWB_fixed_Asm_32:
6237 case ARM::VLD2LNqWB_fixed_Asm_16:
6238 case ARM::VLD2LNqWB_fixed_Asm_32: {
6240 // Shuffle the operands around so the lane index operand is in the
6243 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6244 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6245 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6247 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6248 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6249 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6250 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6251 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6252 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6254 TmpInst.addOperand(Inst.getOperand(1)); // lane
6255 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6256 TmpInst.addOperand(Inst.getOperand(5));
6261 case ARM::VLD3LNdWB_fixed_Asm_8:
6262 case ARM::VLD3LNdWB_fixed_Asm_16:
6263 case ARM::VLD3LNdWB_fixed_Asm_32:
6264 case ARM::VLD3LNqWB_fixed_Asm_16:
6265 case ARM::VLD3LNqWB_fixed_Asm_32: {
6267 // Shuffle the operands around so the lane index operand is in the
6270 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6271 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6272 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6274 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6276 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6277 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6278 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6279 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6280 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6281 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6283 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6285 TmpInst.addOperand(Inst.getOperand(1)); // lane
6286 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6287 TmpInst.addOperand(Inst.getOperand(5));
6292 case ARM::VLD4LNdWB_fixed_Asm_8:
6293 case ARM::VLD4LNdWB_fixed_Asm_16:
6294 case ARM::VLD4LNdWB_fixed_Asm_32:
6295 case ARM::VLD4LNqWB_fixed_Asm_16:
6296 case ARM::VLD4LNqWB_fixed_Asm_32: {
6298 // Shuffle the operands around so the lane index operand is in the
6301 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6302 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6303 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6305 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6307 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6309 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6310 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6311 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6312 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6313 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6314 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6316 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6318 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6320 TmpInst.addOperand(Inst.getOperand(1)); // lane
6321 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6322 TmpInst.addOperand(Inst.getOperand(5));
6327 case ARM::VLD1LNdAsm_8:
6328 case ARM::VLD1LNdAsm_16:
6329 case ARM::VLD1LNdAsm_32: {
6331 // Shuffle the operands around so the lane index operand is in the
6334 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6335 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6336 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6337 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6338 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6339 TmpInst.addOperand(Inst.getOperand(1)); // lane
6340 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6341 TmpInst.addOperand(Inst.getOperand(5));
6346 case ARM::VLD2LNdAsm_8:
6347 case ARM::VLD2LNdAsm_16:
6348 case ARM::VLD2LNdAsm_32:
6349 case ARM::VLD2LNqAsm_16:
6350 case ARM::VLD2LNqAsm_32: {
6352 // Shuffle the operands around so the lane index operand is in the
6355 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6356 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6357 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6359 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6360 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6361 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6362 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6364 TmpInst.addOperand(Inst.getOperand(1)); // lane
6365 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6366 TmpInst.addOperand(Inst.getOperand(5));
6371 case ARM::VLD3LNdAsm_8:
6372 case ARM::VLD3LNdAsm_16:
6373 case ARM::VLD3LNdAsm_32:
6374 case ARM::VLD3LNqAsm_16:
6375 case ARM::VLD3LNqAsm_32: {
6377 // Shuffle the operands around so the lane index operand is in the
6380 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6381 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6382 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6384 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6386 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6387 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6388 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6389 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6391 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6393 TmpInst.addOperand(Inst.getOperand(1)); // lane
6394 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6395 TmpInst.addOperand(Inst.getOperand(5));
6400 case ARM::VLD4LNdAsm_8:
6401 case ARM::VLD4LNdAsm_16:
6402 case ARM::VLD4LNdAsm_32:
6403 case ARM::VLD4LNqAsm_16:
6404 case ARM::VLD4LNqAsm_32: {
6406 // Shuffle the operands around so the lane index operand is in the
6409 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6410 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6411 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6413 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6415 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6417 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6418 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6419 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6420 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6422 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6424 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6426 TmpInst.addOperand(Inst.getOperand(1)); // lane
6427 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6428 TmpInst.addOperand(Inst.getOperand(5));
6433 // VLD3DUP single 3-element structure to all lanes instructions.
6434 case ARM::VLD3DUPdAsm_8:
6435 case ARM::VLD3DUPdAsm_16:
6436 case ARM::VLD3DUPdAsm_32:
6437 case ARM::VLD3DUPqAsm_8:
6438 case ARM::VLD3DUPqAsm_16:
6439 case ARM::VLD3DUPqAsm_32: {
6442 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6443 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6444 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6446 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6448 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6449 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6450 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6451 TmpInst.addOperand(Inst.getOperand(4));
6456 case ARM::VLD3DUPdWB_fixed_Asm_8:
6457 case ARM::VLD3DUPdWB_fixed_Asm_16:
6458 case ARM::VLD3DUPdWB_fixed_Asm_32:
6459 case ARM::VLD3DUPqWB_fixed_Asm_8:
6460 case ARM::VLD3DUPqWB_fixed_Asm_16:
6461 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6464 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6465 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6466 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6468 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6470 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6471 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6472 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6473 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6474 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6475 TmpInst.addOperand(Inst.getOperand(4));
6480 case ARM::VLD3DUPdWB_register_Asm_8:
6481 case ARM::VLD3DUPdWB_register_Asm_16:
6482 case ARM::VLD3DUPdWB_register_Asm_32:
6483 case ARM::VLD3DUPqWB_register_Asm_8:
6484 case ARM::VLD3DUPqWB_register_Asm_16:
6485 case ARM::VLD3DUPqWB_register_Asm_32: {
6488 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6489 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6490 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6492 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6494 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6495 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6496 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6497 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6498 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6499 TmpInst.addOperand(Inst.getOperand(5));
6504 // VLD3 multiple 3-element structure instructions.
6505 case ARM::VLD3dAsm_8:
6506 case ARM::VLD3dAsm_16:
6507 case ARM::VLD3dAsm_32:
6508 case ARM::VLD3qAsm_8:
6509 case ARM::VLD3qAsm_16:
6510 case ARM::VLD3qAsm_32: {
6513 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6514 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6515 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6517 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6519 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6520 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6521 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6522 TmpInst.addOperand(Inst.getOperand(4));
6527 case ARM::VLD3dWB_fixed_Asm_8:
6528 case ARM::VLD3dWB_fixed_Asm_16:
6529 case ARM::VLD3dWB_fixed_Asm_32:
6530 case ARM::VLD3qWB_fixed_Asm_8:
6531 case ARM::VLD3qWB_fixed_Asm_16:
6532 case ARM::VLD3qWB_fixed_Asm_32: {
6535 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6536 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6537 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6539 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6541 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6542 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6543 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6544 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6545 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6546 TmpInst.addOperand(Inst.getOperand(4));
6551 case ARM::VLD3dWB_register_Asm_8:
6552 case ARM::VLD3dWB_register_Asm_16:
6553 case ARM::VLD3dWB_register_Asm_32:
6554 case ARM::VLD3qWB_register_Asm_8:
6555 case ARM::VLD3qWB_register_Asm_16:
6556 case ARM::VLD3qWB_register_Asm_32: {
6559 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6560 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6561 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6563 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6565 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6566 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6567 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6568 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6569 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6570 TmpInst.addOperand(Inst.getOperand(5));
6575 // VLD4DUP single 3-element structure to all lanes instructions.
6576 case ARM::VLD4DUPdAsm_8:
6577 case ARM::VLD4DUPdAsm_16:
6578 case ARM::VLD4DUPdAsm_32:
6579 case ARM::VLD4DUPqAsm_8:
6580 case ARM::VLD4DUPqAsm_16:
6581 case ARM::VLD4DUPqAsm_32: {
6584 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6585 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6586 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6588 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6590 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6592 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6593 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6594 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6595 TmpInst.addOperand(Inst.getOperand(4));
6600 case ARM::VLD4DUPdWB_fixed_Asm_8:
6601 case ARM::VLD4DUPdWB_fixed_Asm_16:
6602 case ARM::VLD4DUPdWB_fixed_Asm_32:
6603 case ARM::VLD4DUPqWB_fixed_Asm_8:
6604 case ARM::VLD4DUPqWB_fixed_Asm_16:
6605 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6608 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6609 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6610 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6612 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6614 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6616 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6617 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6618 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6619 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6620 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6621 TmpInst.addOperand(Inst.getOperand(4));
6626 case ARM::VLD4DUPdWB_register_Asm_8:
6627 case ARM::VLD4DUPdWB_register_Asm_16:
6628 case ARM::VLD4DUPdWB_register_Asm_32:
6629 case ARM::VLD4DUPqWB_register_Asm_8:
6630 case ARM::VLD4DUPqWB_register_Asm_16:
6631 case ARM::VLD4DUPqWB_register_Asm_32: {
6634 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6635 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6636 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6638 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6640 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6642 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6643 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6644 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6645 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6646 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6647 TmpInst.addOperand(Inst.getOperand(5));
6652 // VLD4 multiple 4-element structure instructions.
6653 case ARM::VLD4dAsm_8:
6654 case ARM::VLD4dAsm_16:
6655 case ARM::VLD4dAsm_32:
6656 case ARM::VLD4qAsm_8:
6657 case ARM::VLD4qAsm_16:
6658 case ARM::VLD4qAsm_32: {
6661 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6662 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6663 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6665 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6667 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6669 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6670 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6671 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6672 TmpInst.addOperand(Inst.getOperand(4));
6677 case ARM::VLD4dWB_fixed_Asm_8:
6678 case ARM::VLD4dWB_fixed_Asm_16:
6679 case ARM::VLD4dWB_fixed_Asm_32:
6680 case ARM::VLD4qWB_fixed_Asm_8:
6681 case ARM::VLD4qWB_fixed_Asm_16:
6682 case ARM::VLD4qWB_fixed_Asm_32: {
6685 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6686 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6687 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6689 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6691 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6693 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6694 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6695 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6696 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6697 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6698 TmpInst.addOperand(Inst.getOperand(4));
6703 case ARM::VLD4dWB_register_Asm_8:
6704 case ARM::VLD4dWB_register_Asm_16:
6705 case ARM::VLD4dWB_register_Asm_32:
6706 case ARM::VLD4qWB_register_Asm_8:
6707 case ARM::VLD4qWB_register_Asm_16:
6708 case ARM::VLD4qWB_register_Asm_32: {
6711 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6712 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6713 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6715 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6717 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6719 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6720 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6721 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6722 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6723 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6724 TmpInst.addOperand(Inst.getOperand(5));
6729 // VST3 multiple 3-element structure instructions.
6730 case ARM::VST3dAsm_8:
6731 case ARM::VST3dAsm_16:
6732 case ARM::VST3dAsm_32:
6733 case ARM::VST3qAsm_8:
6734 case ARM::VST3qAsm_16:
6735 case ARM::VST3qAsm_32: {
6738 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6739 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6740 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6741 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6742 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6744 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6746 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6747 TmpInst.addOperand(Inst.getOperand(4));
6752 case ARM::VST3dWB_fixed_Asm_8:
6753 case ARM::VST3dWB_fixed_Asm_16:
6754 case ARM::VST3dWB_fixed_Asm_32:
6755 case ARM::VST3qWB_fixed_Asm_8:
6756 case ARM::VST3qWB_fixed_Asm_16:
6757 case ARM::VST3qWB_fixed_Asm_32: {
6760 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6761 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6762 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6763 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6764 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6765 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6766 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6768 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6770 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6771 TmpInst.addOperand(Inst.getOperand(4));
6776 case ARM::VST3dWB_register_Asm_8:
6777 case ARM::VST3dWB_register_Asm_16:
6778 case ARM::VST3dWB_register_Asm_32:
6779 case ARM::VST3qWB_register_Asm_8:
6780 case ARM::VST3qWB_register_Asm_16:
6781 case ARM::VST3qWB_register_Asm_32: {
6784 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6785 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6786 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6787 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6788 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6789 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6790 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6792 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6794 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6795 TmpInst.addOperand(Inst.getOperand(5));
6800 // VST4 multiple 3-element structure instructions.
6801 case ARM::VST4dAsm_8:
6802 case ARM::VST4dAsm_16:
6803 case ARM::VST4dAsm_32:
6804 case ARM::VST4qAsm_8:
6805 case ARM::VST4qAsm_16:
6806 case ARM::VST4qAsm_32: {
6809 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6810 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6811 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6812 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6813 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6815 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6817 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6819 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6820 TmpInst.addOperand(Inst.getOperand(4));
6825 case ARM::VST4dWB_fixed_Asm_8:
6826 case ARM::VST4dWB_fixed_Asm_16:
6827 case ARM::VST4dWB_fixed_Asm_32:
6828 case ARM::VST4qWB_fixed_Asm_8:
6829 case ARM::VST4qWB_fixed_Asm_16:
6830 case ARM::VST4qWB_fixed_Asm_32: {
6833 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6834 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6835 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6836 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6837 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6838 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6839 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6841 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6843 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6845 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6846 TmpInst.addOperand(Inst.getOperand(4));
6851 case ARM::VST4dWB_register_Asm_8:
6852 case ARM::VST4dWB_register_Asm_16:
6853 case ARM::VST4dWB_register_Asm_32:
6854 case ARM::VST4qWB_register_Asm_8:
6855 case ARM::VST4qWB_register_Asm_16:
6856 case ARM::VST4qWB_register_Asm_32: {
6859 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6860 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6861 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6862 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6863 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6864 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6865 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6867 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6869 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6871 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6872 TmpInst.addOperand(Inst.getOperand(5));
6877 // Handle encoding choice for the shift-immediate instructions.
6880 case ARM::t2ASRri: {
6881 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6882 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6883 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6884 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6885 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6887 switch (Inst.getOpcode()) {
6888 default: llvm_unreachable("unexpected opcode");
6889 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6890 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6891 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6893 // The Thumb1 operands aren't in the same order. Awesome, eh?
6895 TmpInst.setOpcode(NewOpc);
6896 TmpInst.addOperand(Inst.getOperand(0));
6897 TmpInst.addOperand(Inst.getOperand(5));
6898 TmpInst.addOperand(Inst.getOperand(1));
6899 TmpInst.addOperand(Inst.getOperand(2));
6900 TmpInst.addOperand(Inst.getOperand(3));
6901 TmpInst.addOperand(Inst.getOperand(4));
6908 // Handle the Thumb2 mode MOV complex aliases.
6910 case ARM::t2MOVSsr: {
6911 // Which instruction to expand to depends on the CCOut operand and
6912 // whether we're in an IT block if the register operands are low
6914 bool isNarrow = false;
6915 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6916 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6917 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6918 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6919 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6923 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6924 default: llvm_unreachable("unexpected opcode!");
6925 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6926 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6927 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6928 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6930 TmpInst.setOpcode(newOpc);
6931 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6933 TmpInst.addOperand(MCOperand::CreateReg(
6934 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6935 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6936 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6937 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6938 TmpInst.addOperand(Inst.getOperand(5));
6940 TmpInst.addOperand(MCOperand::CreateReg(
6941 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6946 case ARM::t2MOVSsi: {
6947 // Which instruction to expand to depends on the CCOut operand and
6948 // whether we're in an IT block if the register operands are low
6950 bool isNarrow = false;
6951 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6952 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6953 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6957 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6958 default: llvm_unreachable("unexpected opcode!");
6959 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6960 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6961 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6962 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6963 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6965 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6966 if (Amount == 32) Amount = 0;
6967 TmpInst.setOpcode(newOpc);
6968 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6970 TmpInst.addOperand(MCOperand::CreateReg(
6971 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6972 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6973 if (newOpc != ARM::t2RRX)
6974 TmpInst.addOperand(MCOperand::CreateImm(Amount));
6975 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6976 TmpInst.addOperand(Inst.getOperand(4));
6978 TmpInst.addOperand(MCOperand::CreateReg(
6979 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6983 // Handle the ARM mode MOV complex aliases.
6988 ARM_AM::ShiftOpc ShiftTy;
6989 switch(Inst.getOpcode()) {
6990 default: llvm_unreachable("unexpected opcode!");
6991 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6992 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6993 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6994 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6996 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6998 TmpInst.setOpcode(ARM::MOVsr);
6999 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7000 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7001 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7002 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7003 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7004 TmpInst.addOperand(Inst.getOperand(4));
7005 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7013 ARM_AM::ShiftOpc ShiftTy;
7014 switch(Inst.getOpcode()) {
7015 default: llvm_unreachable("unexpected opcode!");
7016 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7017 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7018 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7019 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7021 // A shift by zero is a plain MOVr, not a MOVsi.
7022 unsigned Amt = Inst.getOperand(2).getImm();
7023 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7024 // A shift by 32 should be encoded as 0 when permitted
7025 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7027 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7029 TmpInst.setOpcode(Opc);
7030 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7031 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7032 if (Opc == ARM::MOVsi)
7033 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7034 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7035 TmpInst.addOperand(Inst.getOperand(4));
7036 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7041 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7043 TmpInst.setOpcode(ARM::MOVsi);
7044 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7045 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7046 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7047 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7048 TmpInst.addOperand(Inst.getOperand(3));
7049 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7053 case ARM::t2LDMIA_UPD: {
7054 // If this is a load of a single register, then we should use
7055 // a post-indexed LDR instruction instead, per the ARM ARM.
7056 if (Inst.getNumOperands() != 5)
7059 TmpInst.setOpcode(ARM::t2LDR_POST);
7060 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7061 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7062 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7063 TmpInst.addOperand(MCOperand::CreateImm(4));
7064 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7065 TmpInst.addOperand(Inst.getOperand(3));
7069 case ARM::t2STMDB_UPD: {
7070 // If this is a store of a single register, then we should use
7071 // a pre-indexed STR instruction instead, per the ARM ARM.
7072 if (Inst.getNumOperands() != 5)
7075 TmpInst.setOpcode(ARM::t2STR_PRE);
7076 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7077 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7078 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7079 TmpInst.addOperand(MCOperand::CreateImm(-4));
7080 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7081 TmpInst.addOperand(Inst.getOperand(3));
7085 case ARM::LDMIA_UPD:
7086 // If this is a load of a single register via a 'pop', then we should use
7087 // a post-indexed LDR instruction instead, per the ARM ARM.
7088 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7089 Inst.getNumOperands() == 5) {
7091 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7092 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7093 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7094 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7095 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7096 TmpInst.addOperand(MCOperand::CreateImm(4));
7097 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7098 TmpInst.addOperand(Inst.getOperand(3));
7103 case ARM::STMDB_UPD:
7104 // If this is a store of a single register via a 'push', then we should use
7105 // a pre-indexed STR instruction instead, per the ARM ARM.
7106 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7107 Inst.getNumOperands() == 5) {
7109 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7110 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7111 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7112 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7113 TmpInst.addOperand(MCOperand::CreateImm(-4));
7114 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7115 TmpInst.addOperand(Inst.getOperand(3));
7119 case ARM::t2ADDri12:
7120 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7121 // mnemonic was used (not "addw"), encoding T3 is preferred.
7122 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7123 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7125 Inst.setOpcode(ARM::t2ADDri);
7126 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7128 case ARM::t2SUBri12:
7129 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7130 // mnemonic was used (not "subw"), encoding T3 is preferred.
7131 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7132 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7134 Inst.setOpcode(ARM::t2SUBri);
7135 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7138 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7139 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7140 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7141 // to encoding T1 if <Rd> is omitted."
7142 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7143 Inst.setOpcode(ARM::tADDi3);
7148 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7149 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7150 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7151 // to encoding T1 if <Rd> is omitted."
7152 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7153 Inst.setOpcode(ARM::tSUBi3);
7158 case ARM::t2SUBri: {
7159 // If the destination and first source operand are the same, and
7160 // the flags are compatible with the current IT status, use encoding T2
7161 // instead of T3. For compatibility with the system 'as'. Make sure the
7162 // wide encoding wasn't explicit.
7163 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7164 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7165 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7166 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7167 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7168 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7169 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7172 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7173 ARM::tADDi8 : ARM::tSUBi8);
7174 TmpInst.addOperand(Inst.getOperand(0));
7175 TmpInst.addOperand(Inst.getOperand(5));
7176 TmpInst.addOperand(Inst.getOperand(0));
7177 TmpInst.addOperand(Inst.getOperand(2));
7178 TmpInst.addOperand(Inst.getOperand(3));
7179 TmpInst.addOperand(Inst.getOperand(4));
7183 case ARM::t2ADDrr: {
7184 // If the destination and first source operand are the same, and
7185 // there's no setting of the flags, use encoding T2 instead of T3.
7186 // Note that this is only for ADD, not SUB. This mirrors the system
7187 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7188 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7189 Inst.getOperand(5).getReg() != 0 ||
7190 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7191 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7194 TmpInst.setOpcode(ARM::tADDhirr);
7195 TmpInst.addOperand(Inst.getOperand(0));
7196 TmpInst.addOperand(Inst.getOperand(0));
7197 TmpInst.addOperand(Inst.getOperand(2));
7198 TmpInst.addOperand(Inst.getOperand(3));
7199 TmpInst.addOperand(Inst.getOperand(4));
7203 case ARM::tADDrSP: {
7204 // If the non-SP source operand and the destination operand are not the
7205 // same, we need to use the 32-bit encoding if it's available.
7206 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7207 Inst.setOpcode(ARM::t2ADDrr);
7208 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7214 // A Thumb conditional branch outside of an IT block is a tBcc.
7215 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7216 Inst.setOpcode(ARM::tBcc);
7221 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7222 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7223 Inst.setOpcode(ARM::t2Bcc);
7228 // If the conditional is AL or we're in an IT block, we really want t2B.
7229 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7230 Inst.setOpcode(ARM::t2B);
7235 // If the conditional is AL, we really want tB.
7236 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7237 Inst.setOpcode(ARM::tB);
7242 // If the register list contains any high registers, or if the writeback
7243 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7244 // instead if we're in Thumb2. Otherwise, this should have generated
7245 // an error in validateInstruction().
7246 unsigned Rn = Inst.getOperand(0).getReg();
7247 bool hasWritebackToken =
7248 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7249 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7250 bool listContainsBase;
7251 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7252 (!listContainsBase && !hasWritebackToken) ||
7253 (listContainsBase && hasWritebackToken)) {
7254 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7255 assert (isThumbTwo());
7256 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7257 // If we're switching to the updating version, we need to insert
7258 // the writeback tied operand.
7259 if (hasWritebackToken)
7260 Inst.insert(Inst.begin(),
7261 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7266 case ARM::tSTMIA_UPD: {
7267 // If the register list contains any high registers, we need to use
7268 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7269 // should have generated an error in validateInstruction().
7270 unsigned Rn = Inst.getOperand(0).getReg();
7271 bool listContainsBase;
7272 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7273 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7274 assert (isThumbTwo());
7275 Inst.setOpcode(ARM::t2STMIA_UPD);
7281 bool listContainsBase;
7282 // If the register list contains any high registers, we need to use
7283 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7284 // should have generated an error in validateInstruction().
7285 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7287 assert (isThumbTwo());
7288 Inst.setOpcode(ARM::t2LDMIA_UPD);
7289 // Add the base register and writeback operands.
7290 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7291 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7295 bool listContainsBase;
7296 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7298 assert (isThumbTwo());
7299 Inst.setOpcode(ARM::t2STMDB_UPD);
7300 // Add the base register and writeback operands.
7301 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7302 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7306 // If we can use the 16-bit encoding and the user didn't explicitly
7307 // request the 32-bit variant, transform it here.
7308 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7309 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7310 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7311 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7312 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7313 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7314 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7315 // The operands aren't in the same order for tMOVi8...
7317 TmpInst.setOpcode(ARM::tMOVi8);
7318 TmpInst.addOperand(Inst.getOperand(0));
7319 TmpInst.addOperand(Inst.getOperand(4));
7320 TmpInst.addOperand(Inst.getOperand(1));
7321 TmpInst.addOperand(Inst.getOperand(2));
7322 TmpInst.addOperand(Inst.getOperand(3));
7329 // If we can use the 16-bit encoding and the user didn't explicitly
7330 // request the 32-bit variant, transform it here.
7331 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7332 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7333 Inst.getOperand(2).getImm() == ARMCC::AL &&
7334 Inst.getOperand(4).getReg() == ARM::CPSR &&
7335 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7336 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7337 // The operands aren't the same for tMOV[S]r... (no cc_out)
7339 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7340 TmpInst.addOperand(Inst.getOperand(0));
7341 TmpInst.addOperand(Inst.getOperand(1));
7342 TmpInst.addOperand(Inst.getOperand(2));
7343 TmpInst.addOperand(Inst.getOperand(3));
7353 // If we can use the 16-bit encoding and the user didn't explicitly
7354 // request the 32-bit variant, transform it here.
7355 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7356 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7357 Inst.getOperand(2).getImm() == 0 &&
7358 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7359 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7361 switch (Inst.getOpcode()) {
7362 default: llvm_unreachable("Illegal opcode!");
7363 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7364 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7365 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7366 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7368 // The operands aren't the same for thumb1 (no rotate operand).
7370 TmpInst.setOpcode(NewOpc);
7371 TmpInst.addOperand(Inst.getOperand(0));
7372 TmpInst.addOperand(Inst.getOperand(1));
7373 TmpInst.addOperand(Inst.getOperand(3));
7374 TmpInst.addOperand(Inst.getOperand(4));
7381 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7382 // rrx shifts and asr/lsr of #32 is encoded as 0
7383 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7385 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7386 // Shifting by zero is accepted as a vanilla 'MOVr'
7388 TmpInst.setOpcode(ARM::MOVr);
7389 TmpInst.addOperand(Inst.getOperand(0));
7390 TmpInst.addOperand(Inst.getOperand(1));
7391 TmpInst.addOperand(Inst.getOperand(3));
7392 TmpInst.addOperand(Inst.getOperand(4));
7393 TmpInst.addOperand(Inst.getOperand(5));
7406 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7407 if (SOpc == ARM_AM::rrx) return false;
7408 switch (Inst.getOpcode()) {
7409 default: llvm_unreachable("unexpected opcode!");
7410 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7411 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7412 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7413 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7414 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7415 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7417 // If the shift is by zero, use the non-shifted instruction definition.
7418 // The exception is for right shifts, where 0 == 32
7419 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7420 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7422 TmpInst.setOpcode(newOpc);
7423 TmpInst.addOperand(Inst.getOperand(0));
7424 TmpInst.addOperand(Inst.getOperand(1));
7425 TmpInst.addOperand(Inst.getOperand(2));
7426 TmpInst.addOperand(Inst.getOperand(4));
7427 TmpInst.addOperand(Inst.getOperand(5));
7428 TmpInst.addOperand(Inst.getOperand(6));
7436 // The mask bits for all but the first condition are represented as
7437 // the low bit of the condition code value implies 't'. We currently
7438 // always have 1 implies 't', so XOR toggle the bits if the low bit
7439 // of the condition code is zero.
7440 MCOperand &MO = Inst.getOperand(1);
7441 unsigned Mask = MO.getImm();
7442 unsigned OrigMask = Mask;
7443 unsigned TZ = countTrailingZeros(Mask);
7444 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7445 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7446 Mask ^= (0xE << TZ) & 0xF;
7450 // Set up the IT block state according to the IT instruction we just
7452 assert(!inITBlock() && "nested IT blocks?!");
7453 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7454 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7455 ITState.CurPosition = 0;
7456 ITState.FirstCond = true;
7466 // Assemblers should use the narrow encodings of these instructions when permissible.
7467 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7468 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7469 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7470 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7471 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7472 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7473 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7475 switch (Inst.getOpcode()) {
7476 default: llvm_unreachable("unexpected opcode");
7477 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7478 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7479 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7480 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7481 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7482 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7485 TmpInst.setOpcode(NewOpc);
7486 TmpInst.addOperand(Inst.getOperand(0));
7487 TmpInst.addOperand(Inst.getOperand(5));
7488 TmpInst.addOperand(Inst.getOperand(1));
7489 TmpInst.addOperand(Inst.getOperand(2));
7490 TmpInst.addOperand(Inst.getOperand(3));
7491 TmpInst.addOperand(Inst.getOperand(4));
7502 // Assemblers should use the narrow encodings of these instructions when permissible.
7503 // These instructions are special in that they are commutable, so shorter encodings
7504 // are available more often.
7505 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7506 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7507 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7508 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7509 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7510 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7511 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7512 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7514 switch (Inst.getOpcode()) {
7515 default: llvm_unreachable("unexpected opcode");
7516 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7517 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7518 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7519 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7522 TmpInst.setOpcode(NewOpc);
7523 TmpInst.addOperand(Inst.getOperand(0));
7524 TmpInst.addOperand(Inst.getOperand(5));
7525 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7526 TmpInst.addOperand(Inst.getOperand(1));
7527 TmpInst.addOperand(Inst.getOperand(2));
7529 TmpInst.addOperand(Inst.getOperand(2));
7530 TmpInst.addOperand(Inst.getOperand(1));
7532 TmpInst.addOperand(Inst.getOperand(3));
7533 TmpInst.addOperand(Inst.getOperand(4));
7543 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7544 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7545 // suffix depending on whether they're in an IT block or not.
7546 unsigned Opc = Inst.getOpcode();
7547 const MCInstrDesc &MCID = getInstDesc(Opc);
7548 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7549 assert(MCID.hasOptionalDef() &&
7550 "optionally flag setting instruction missing optional def operand");
7551 assert(MCID.NumOperands == Inst.getNumOperands() &&
7552 "operand count mismatch!");
7553 // Find the optional-def operand (cc_out).
7556 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7559 // If we're parsing Thumb1, reject it completely.
7560 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7561 return Match_MnemonicFail;
7562 // If we're parsing Thumb2, which form is legal depends on whether we're
7564 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7566 return Match_RequiresITBlock;
7567 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7569 return Match_RequiresNotITBlock;
7571 // Some high-register supporting Thumb1 encodings only allow both registers
7572 // to be from r0-r7 when in Thumb2.
7573 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7574 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7575 isARMLowRegister(Inst.getOperand(2).getReg()))
7576 return Match_RequiresThumb2;
7577 // Others only require ARMv6 or later.
7578 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7579 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7580 isARMLowRegister(Inst.getOperand(1).getReg()))
7581 return Match_RequiresV6;
7582 return Match_Success;
7585 static const char *getSubtargetFeatureName(unsigned Val);
7587 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7588 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7589 MCStreamer &Out, unsigned &ErrorInfo,
7590 bool MatchingInlineAsm) {
7592 unsigned MatchResult;
7594 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7596 switch (MatchResult) {
7599 // Context sensitive operand constraints aren't handled by the matcher,
7600 // so check them here.
7601 if (validateInstruction(Inst, Operands)) {
7602 // Still progress the IT block, otherwise one wrong condition causes
7603 // nasty cascading errors.
7604 forwardITPosition();
7608 // Some instructions need post-processing to, for example, tweak which
7609 // encoding is selected. Loop on it while changes happen so the
7610 // individual transformations can chain off each other. E.g.,
7611 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7612 while (processInstruction(Inst, Operands))
7615 // Only move forward at the very end so that everything in validate
7616 // and process gets a consistent answer about whether we're in an IT
7618 forwardITPosition();
7620 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7621 // doesn't actually encode.
7622 if (Inst.getOpcode() == ARM::ITasm)
7626 Out.EmitInstruction(Inst);
7628 case Match_MissingFeature: {
7629 assert(ErrorInfo && "Unknown missing feature!");
7630 // Special case the error message for the very common case where only
7631 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7632 std::string Msg = "instruction requires:";
7634 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7635 if (ErrorInfo & Mask) {
7637 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7641 return Error(IDLoc, Msg);
7643 case Match_InvalidOperand: {
7644 SMLoc ErrorLoc = IDLoc;
7645 if (ErrorInfo != ~0U) {
7646 if (ErrorInfo >= Operands.size())
7647 return Error(IDLoc, "too few operands for instruction");
7649 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7650 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7653 return Error(ErrorLoc, "invalid operand for instruction");
7655 case Match_MnemonicFail:
7656 return Error(IDLoc, "invalid instruction",
7657 ((ARMOperand*)Operands[0])->getLocRange());
7658 case Match_RequiresNotITBlock:
7659 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7660 case Match_RequiresITBlock:
7661 return Error(IDLoc, "instruction only valid inside IT block");
7662 case Match_RequiresV6:
7663 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7664 case Match_RequiresThumb2:
7665 return Error(IDLoc, "instruction variant requires Thumb2");
7666 case Match_ImmRange0_4: {
7667 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7668 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7669 return Error(ErrorLoc, "immediate operand must be in the range [0,4]");
7671 case Match_ImmRange0_15: {
7672 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7673 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7674 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7678 llvm_unreachable("Implement any new match types added!");
7681 /// parseDirective parses the arm specific directives
7682 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7683 StringRef IDVal = DirectiveID.getIdentifier();
7684 if (IDVal == ".word")
7685 return parseDirectiveWord(4, DirectiveID.getLoc());
7686 else if (IDVal == ".thumb")
7687 return parseDirectiveThumb(DirectiveID.getLoc());
7688 else if (IDVal == ".arm")
7689 return parseDirectiveARM(DirectiveID.getLoc());
7690 else if (IDVal == ".thumb_func")
7691 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7692 else if (IDVal == ".code")
7693 return parseDirectiveCode(DirectiveID.getLoc());
7694 else if (IDVal == ".syntax")
7695 return parseDirectiveSyntax(DirectiveID.getLoc());
7696 else if (IDVal == ".unreq")
7697 return parseDirectiveUnreq(DirectiveID.getLoc());
7698 else if (IDVal == ".arch")
7699 return parseDirectiveArch(DirectiveID.getLoc());
7700 else if (IDVal == ".eabi_attribute")
7701 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7702 else if (IDVal == ".fnstart")
7703 return parseDirectiveFnStart(DirectiveID.getLoc());
7704 else if (IDVal == ".fnend")
7705 return parseDirectiveFnEnd(DirectiveID.getLoc());
7706 else if (IDVal == ".cantunwind")
7707 return parseDirectiveCantUnwind(DirectiveID.getLoc());
7708 else if (IDVal == ".personality")
7709 return parseDirectivePersonality(DirectiveID.getLoc());
7710 else if (IDVal == ".handlerdata")
7711 return parseDirectiveHandlerData(DirectiveID.getLoc());
7712 else if (IDVal == ".setfp")
7713 return parseDirectiveSetFP(DirectiveID.getLoc());
7714 else if (IDVal == ".pad")
7715 return parseDirectivePad(DirectiveID.getLoc());
7716 else if (IDVal == ".save")
7717 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
7718 else if (IDVal == ".vsave")
7719 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
7723 /// parseDirectiveWord
7724 /// ::= .word [ expression (, expression)* ]
7725 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7726 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7728 const MCExpr *Value;
7729 if (getParser().parseExpression(Value))
7732 getParser().getStreamer().EmitValue(Value, Size);
7734 if (getLexer().is(AsmToken::EndOfStatement))
7737 // FIXME: Improve diagnostic.
7738 if (getLexer().isNot(AsmToken::Comma))
7739 return Error(L, "unexpected token in directive");
7748 /// parseDirectiveThumb
7750 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7751 if (getLexer().isNot(AsmToken::EndOfStatement))
7752 return Error(L, "unexpected token in directive");
7756 return Error(L, "target does not support Thumb mode");
7760 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7764 /// parseDirectiveARM
7766 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7767 if (getLexer().isNot(AsmToken::EndOfStatement))
7768 return Error(L, "unexpected token in directive");
7772 return Error(L, "target does not support ARM mode");
7776 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7780 /// parseDirectiveThumbFunc
7781 /// ::= .thumbfunc symbol_name
7782 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7783 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
7784 bool isMachO = MAI->hasSubsectionsViaSymbols();
7786 bool needFuncName = true;
7788 // Darwin asm has (optionally) function name after .thumb_func direction
7791 const AsmToken &Tok = Parser.getTok();
7792 if (Tok.isNot(AsmToken::EndOfStatement)) {
7793 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7794 return Error(L, "unexpected token in .thumb_func directive");
7795 Name = Tok.getIdentifier();
7796 Parser.Lex(); // Consume the identifier token.
7797 needFuncName = false;
7801 if (getLexer().isNot(AsmToken::EndOfStatement))
7802 return Error(L, "unexpected token in directive");
7804 // Eat the end of statement and any blank lines that follow.
7805 while (getLexer().is(AsmToken::EndOfStatement))
7808 // FIXME: assuming function name will be the line following .thumb_func
7809 // We really should be checking the next symbol definition even if there's
7810 // stuff in between.
7812 Name = Parser.getTok().getIdentifier();
7815 // Mark symbol as a thumb symbol.
7816 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7817 getParser().getStreamer().EmitThumbFunc(Func);
7821 /// parseDirectiveSyntax
7822 /// ::= .syntax unified | divided
7823 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7824 const AsmToken &Tok = Parser.getTok();
7825 if (Tok.isNot(AsmToken::Identifier))
7826 return Error(L, "unexpected token in .syntax directive");
7827 StringRef Mode = Tok.getString();
7828 if (Mode == "unified" || Mode == "UNIFIED")
7830 else if (Mode == "divided" || Mode == "DIVIDED")
7831 return Error(L, "'.syntax divided' arm asssembly not supported");
7833 return Error(L, "unrecognized syntax mode in .syntax directive");
7835 if (getLexer().isNot(AsmToken::EndOfStatement))
7836 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7839 // TODO tell the MC streamer the mode
7840 // getParser().getStreamer().Emit???();
7844 /// parseDirectiveCode
7845 /// ::= .code 16 | 32
7846 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7847 const AsmToken &Tok = Parser.getTok();
7848 if (Tok.isNot(AsmToken::Integer))
7849 return Error(L, "unexpected token in .code directive");
7850 int64_t Val = Parser.getTok().getIntVal();
7856 return Error(L, "invalid operand to .code directive");
7858 if (getLexer().isNot(AsmToken::EndOfStatement))
7859 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7864 return Error(L, "target does not support Thumb mode");
7868 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7871 return Error(L, "target does not support ARM mode");
7875 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7881 /// parseDirectiveReq
7882 /// ::= name .req registername
7883 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7884 Parser.Lex(); // Eat the '.req' token.
7886 SMLoc SRegLoc, ERegLoc;
7887 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7888 Parser.eatToEndOfStatement();
7889 return Error(SRegLoc, "register name expected");
7892 // Shouldn't be anything else.
7893 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7894 Parser.eatToEndOfStatement();
7895 return Error(Parser.getTok().getLoc(),
7896 "unexpected input in .req directive.");
7899 Parser.Lex(); // Consume the EndOfStatement
7901 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7902 return Error(SRegLoc, "redefinition of '" + Name +
7903 "' does not match original.");
7908 /// parseDirectiveUneq
7909 /// ::= .unreq registername
7910 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7911 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7912 Parser.eatToEndOfStatement();
7913 return Error(L, "unexpected input in .unreq directive.");
7915 RegisterReqs.erase(Parser.getTok().getIdentifier());
7916 Parser.Lex(); // Eat the identifier.
7920 /// parseDirectiveArch
7922 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7926 /// parseDirectiveEabiAttr
7927 /// ::= .eabi_attribute int, int
7928 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7932 /// parseDirectiveFnStart
7934 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
7935 if (FnStartLoc.isValid()) {
7936 Error(L, ".fnstart starts before the end of previous one");
7937 Error(FnStartLoc, "previous .fnstart starts here");
7942 getParser().getStreamer().EmitFnStart();
7946 /// parseDirectiveFnEnd
7948 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
7949 // Check the ordering of unwind directives
7950 if (!FnStartLoc.isValid())
7951 return Error(L, ".fnstart must precede .fnend directive");
7953 // Reset the unwind directives parser state
7954 resetUnwindDirectiveParserState();
7956 getParser().getStreamer().EmitFnEnd();
7960 /// parseDirectiveCantUnwind
7962 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
7963 // Check the ordering of unwind directives
7965 if (!FnStartLoc.isValid())
7966 return Error(L, ".fnstart must precede .cantunwind directive");
7967 if (HandlerDataLoc.isValid()) {
7968 Error(L, ".cantunwind can't be used with .handlerdata directive");
7969 Error(HandlerDataLoc, ".handlerdata was specified here");
7972 if (PersonalityLoc.isValid()) {
7973 Error(L, ".cantunwind can't be used with .personality directive");
7974 Error(PersonalityLoc, ".personality was specified here");
7978 getParser().getStreamer().EmitCantUnwind();
7982 /// parseDirectivePersonality
7983 /// ::= .personality name
7984 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
7985 // Check the ordering of unwind directives
7987 if (!FnStartLoc.isValid())
7988 return Error(L, ".fnstart must precede .personality directive");
7989 if (CantUnwindLoc.isValid()) {
7990 Error(L, ".personality can't be used with .cantunwind directive");
7991 Error(CantUnwindLoc, ".cantunwind was specified here");
7994 if (HandlerDataLoc.isValid()) {
7995 Error(L, ".personality must precede .handlerdata directive");
7996 Error(HandlerDataLoc, ".handlerdata was specified here");
8000 // Parse the name of the personality routine
8001 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8002 Parser.eatToEndOfStatement();
8003 return Error(L, "unexpected input in .personality directive.");
8005 StringRef Name(Parser.getTok().getIdentifier());
8008 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8009 getParser().getStreamer().EmitPersonality(PR);
8013 /// parseDirectiveHandlerData
8014 /// ::= .handlerdata
8015 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8016 // Check the ordering of unwind directives
8018 if (!FnStartLoc.isValid())
8019 return Error(L, ".fnstart must precede .personality directive");
8020 if (CantUnwindLoc.isValid()) {
8021 Error(L, ".handlerdata can't be used with .cantunwind directive");
8022 Error(CantUnwindLoc, ".cantunwind was specified here");
8026 getParser().getStreamer().EmitHandlerData();
8030 /// parseDirectiveSetFP
8031 /// ::= .setfp fpreg, spreg [, offset]
8032 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8033 // Check the ordering of unwind directives
8034 if (!FnStartLoc.isValid())
8035 return Error(L, ".fnstart must precede .setfp directive");
8036 if (HandlerDataLoc.isValid())
8037 return Error(L, ".setfp must precede .handlerdata directive");
8040 SMLoc NewFPRegLoc = Parser.getTok().getLoc();
8041 int NewFPReg = tryParseRegister();
8043 return Error(NewFPRegLoc, "frame pointer register expected");
8046 if (!Parser.getTok().is(AsmToken::Comma))
8047 return Error(Parser.getTok().getLoc(), "comma expected");
8048 Parser.Lex(); // skip comma
8051 SMLoc NewSPRegLoc = Parser.getTok().getLoc();
8052 int NewSPReg = tryParseRegister();
8054 return Error(NewSPRegLoc, "stack pointer register expected");
8056 if (NewSPReg != ARM::SP && NewSPReg != FPReg)
8057 return Error(NewSPRegLoc,
8058 "register should be either $sp or the latest fp register");
8060 // Update the frame pointer register
8065 if (Parser.getTok().is(AsmToken::Comma)) {
8066 Parser.Lex(); // skip comma
8068 if (Parser.getTok().isNot(AsmToken::Hash) &&
8069 Parser.getTok().isNot(AsmToken::Dollar)) {
8070 return Error(Parser.getTok().getLoc(), "'#' expected");
8072 Parser.Lex(); // skip hash token.
8074 const MCExpr *OffsetExpr;
8075 SMLoc ExLoc = Parser.getTok().getLoc();
8077 if (getParser().parseExpression(OffsetExpr, EndLoc))
8078 return Error(ExLoc, "malformed setfp offset");
8079 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8081 return Error(ExLoc, "setfp offset must be an immediate");
8083 Offset = CE->getValue();
8086 getParser().getStreamer().EmitSetFP(static_cast<unsigned>(NewFPReg),
8087 static_cast<unsigned>(NewSPReg),
8094 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8095 // Check the ordering of unwind directives
8096 if (!FnStartLoc.isValid())
8097 return Error(L, ".fnstart must precede .pad directive");
8098 if (HandlerDataLoc.isValid())
8099 return Error(L, ".pad must precede .handlerdata directive");
8102 if (Parser.getTok().isNot(AsmToken::Hash) &&
8103 Parser.getTok().isNot(AsmToken::Dollar)) {
8104 return Error(Parser.getTok().getLoc(), "'#' expected");
8106 Parser.Lex(); // skip hash token.
8108 const MCExpr *OffsetExpr;
8109 SMLoc ExLoc = Parser.getTok().getLoc();
8111 if (getParser().parseExpression(OffsetExpr, EndLoc))
8112 return Error(ExLoc, "malformed pad offset");
8113 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8115 return Error(ExLoc, "pad offset must be an immediate");
8117 getParser().getStreamer().EmitPad(CE->getValue());
8121 /// parseDirectiveRegSave
8122 /// ::= .save { registers }
8123 /// ::= .vsave { registers }
8124 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8125 // Check the ordering of unwind directives
8126 if (!FnStartLoc.isValid())
8127 return Error(L, ".fnstart must precede .save or .vsave directives");
8128 if (HandlerDataLoc.isValid())
8129 return Error(L, ".save or .vsave must precede .handlerdata directive");
8131 // RAII object to make sure parsed operands are deleted.
8132 struct CleanupObject {
8133 SmallVector<MCParsedAsmOperand *, 1> Operands;
8135 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8140 // Parse the register list
8141 if (parseRegisterList(CO.Operands))
8143 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8144 if (!IsVector && !Op->isRegList())
8145 return Error(L, ".save expects GPR registers");
8146 if (IsVector && !Op->isDPRRegList())
8147 return Error(L, ".vsave expects DPR registers");
8149 getParser().getStreamer().EmitRegSave(Op->getRegList(), IsVector);
8153 /// Force static initialization.
8154 extern "C" void LLVMInitializeARMAsmParser() {
8155 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
8156 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
8159 #define GET_REGISTER_MATCHER
8160 #define GET_SUBTARGET_FEATURE_NAME
8161 #define GET_MATCHER_IMPLEMENTATION
8162 #include "ARMGenAsmMatcher.inc"
8164 // Define this matcher function after the auto-generated include so we
8165 // have the match class enum definitions.
8166 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
8168 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
8169 // If the kind is a token for a literal immediate, check if our asm
8170 // operand matches. This is for InstAliases which have a fixed-value
8171 // immediate in the syntax.
8172 if (Kind == MCK__35_0 && Op->isImm()) {
8173 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
8175 return Match_InvalidOperand;
8176 if (CE->getValue() == 0)
8177 return Match_Success;
8179 return Match_InvalidOperand;