1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "llvm/MC/MCTargetAsmParser.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/BitVector.h"
15 #include "llvm/ADT/OwningPtr.h"
16 #include "llvm/ADT/STLExtras.h"
17 #include "llvm/ADT/SmallVector.h"
18 #include "llvm/ADT/StringSwitch.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCExpr.h"
23 #include "llvm/MC/MCInst.h"
24 #include "llvm/MC/MCInstrDesc.h"
25 #include "llvm/MC/MCParser/MCAsmLexer.h"
26 #include "llvm/MC/MCParser/MCAsmParser.h"
27 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
28 #include "llvm/MC/MCRegisterInfo.h"
29 #include "llvm/MC/MCStreamer.h"
30 #include "llvm/MC/MCSubtargetInfo.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/SourceMgr.h"
33 #include "llvm/Support/TargetRegistry.h"
34 #include "llvm/Support/raw_ostream.h"
42 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
44 class ARMAsmParser : public MCTargetAsmParser {
47 const MCRegisterInfo *MRI;
49 // Map of register aliases registers via the .req directive.
50 StringMap<unsigned> RegisterReqs;
53 ARMCC::CondCodes Cond; // Condition for IT block.
54 unsigned Mask:4; // Condition mask for instructions.
55 // Starting at first 1 (from lsb).
56 // '1' condition as indicated in IT.
57 // '0' inverse of condition (else).
58 // Count of instructions in IT block is
59 // 4 - trailingzeroes(mask)
61 bool FirstCond; // Explicit flag for when we're parsing the
62 // First instruction in the IT block. It's
63 // implied in the mask, so needs special
66 unsigned CurPosition; // Current position in parsing of IT
67 // block. In range [0,3]. Initialized
68 // according to count of instructions in block.
69 // ~0U if no active IT block.
71 bool inITBlock() { return ITState.CurPosition != ~0U;}
72 void forwardITPosition() {
73 if (!inITBlock()) return;
74 // Move to the next instruction in the IT block, if there is one. If not,
75 // mark the block as done.
76 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
77 if (++ITState.CurPosition == 5 - TZ)
78 ITState.CurPosition = ~0U; // Done with the IT block after this.
82 MCAsmParser &getParser() const { return Parser; }
83 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
85 bool Warning(SMLoc L, const Twine &Msg,
86 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
87 return Parser.Warning(L, Msg, Ranges);
89 bool Error(SMLoc L, const Twine &Msg,
90 ArrayRef<SMRange> Ranges = ArrayRef<SMRange>()) {
91 return Parser.Error(L, Msg, Ranges);
94 int tryParseRegister();
95 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
96 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
97 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
98 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
99 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
100 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
101 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
102 unsigned &ShiftAmount);
103 bool parseDirectiveWord(unsigned Size, SMLoc L);
104 bool parseDirectiveThumb(SMLoc L);
105 bool parseDirectiveARM(SMLoc L);
106 bool parseDirectiveThumbFunc(SMLoc L);
107 bool parseDirectiveCode(SMLoc L);
108 bool parseDirectiveSyntax(SMLoc L);
109 bool parseDirectiveReq(StringRef Name, SMLoc L);
110 bool parseDirectiveUnreq(SMLoc L);
111 bool parseDirectiveArch(SMLoc L);
112 bool parseDirectiveEabiAttr(SMLoc L);
114 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
115 bool &CarrySetting, unsigned &ProcessorIMod,
117 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
118 bool &CanAcceptPredicationCode);
120 bool isThumb() const {
121 // FIXME: Can tablegen auto-generate this?
122 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
124 bool isThumbOne() const {
125 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
127 bool isThumbTwo() const {
128 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
130 bool hasV6Ops() const {
131 return STI.getFeatureBits() & ARM::HasV6Ops;
133 bool hasV7Ops() const {
134 return STI.getFeatureBits() & ARM::HasV7Ops;
137 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
138 setAvailableFeatures(FB);
140 bool isMClass() const {
141 return STI.getFeatureBits() & ARM::FeatureMClass;
144 /// @name Auto-generated Match Functions
147 #define GET_ASSEMBLER_HEADER
148 #include "ARMGenAsmMatcher.inc"
152 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
153 OperandMatchResultTy parseCoprocNumOperand(
154 SmallVectorImpl<MCParsedAsmOperand*>&);
155 OperandMatchResultTy parseCoprocRegOperand(
156 SmallVectorImpl<MCParsedAsmOperand*>&);
157 OperandMatchResultTy parseCoprocOptionOperand(
158 SmallVectorImpl<MCParsedAsmOperand*>&);
159 OperandMatchResultTy parseMemBarrierOptOperand(
160 SmallVectorImpl<MCParsedAsmOperand*>&);
161 OperandMatchResultTy parseProcIFlagsOperand(
162 SmallVectorImpl<MCParsedAsmOperand*>&);
163 OperandMatchResultTy parseMSRMaskOperand(
164 SmallVectorImpl<MCParsedAsmOperand*>&);
165 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
166 StringRef Op, int Low, int High);
167 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
168 return parsePKHImm(O, "lsl", 0, 31);
170 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
171 return parsePKHImm(O, "asr", 1, 32);
173 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
174 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
175 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
176 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
177 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
178 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
179 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
180 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
181 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
184 // Asm Match Converter Methods
185 void cvtT2LdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
186 void cvtT2StrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
187 void cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
188 const SmallVectorImpl<MCParsedAsmOperand*> &);
189 void cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
190 const SmallVectorImpl<MCParsedAsmOperand*> &);
191 void cvtLdWriteBackRegAddrMode2(MCInst &Inst,
192 const SmallVectorImpl<MCParsedAsmOperand*> &);
193 void cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
194 const SmallVectorImpl<MCParsedAsmOperand*> &);
195 void cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
196 const SmallVectorImpl<MCParsedAsmOperand*> &);
197 void cvtStWriteBackRegAddrMode2(MCInst &Inst,
198 const SmallVectorImpl<MCParsedAsmOperand*> &);
199 void cvtStWriteBackRegAddrMode3(MCInst &Inst,
200 const SmallVectorImpl<MCParsedAsmOperand*> &);
201 void cvtLdExtTWriteBackImm(MCInst &Inst,
202 const SmallVectorImpl<MCParsedAsmOperand*> &);
203 void cvtLdExtTWriteBackReg(MCInst &Inst,
204 const SmallVectorImpl<MCParsedAsmOperand*> &);
205 void cvtStExtTWriteBackImm(MCInst &Inst,
206 const SmallVectorImpl<MCParsedAsmOperand*> &);
207 void cvtStExtTWriteBackReg(MCInst &Inst,
208 const SmallVectorImpl<MCParsedAsmOperand*> &);
209 void cvtLdrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
210 void cvtStrdPre(MCInst &Inst, const SmallVectorImpl<MCParsedAsmOperand*> &);
211 void cvtLdWriteBackRegAddrMode3(MCInst &Inst,
212 const SmallVectorImpl<MCParsedAsmOperand*> &);
213 void cvtThumbMultiply(MCInst &Inst,
214 const SmallVectorImpl<MCParsedAsmOperand*> &);
215 void cvtVLDwbFixed(MCInst &Inst,
216 const SmallVectorImpl<MCParsedAsmOperand*> &);
217 void cvtVLDwbRegister(MCInst &Inst,
218 const SmallVectorImpl<MCParsedAsmOperand*> &);
219 void cvtVSTwbFixed(MCInst &Inst,
220 const SmallVectorImpl<MCParsedAsmOperand*> &);
221 void cvtVSTwbRegister(MCInst &Inst,
222 const SmallVectorImpl<MCParsedAsmOperand*> &);
223 bool validateInstruction(MCInst &Inst,
224 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
225 bool processInstruction(MCInst &Inst,
226 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
227 bool shouldOmitCCOutOperand(StringRef Mnemonic,
228 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
231 enum ARMMatchResultTy {
232 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
233 Match_RequiresNotITBlock,
235 Match_RequiresThumb2,
236 #define GET_OPERAND_DIAGNOSTIC_TYPES
237 #include "ARMGenAsmMatcher.inc"
241 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
242 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
243 MCAsmParserExtension::Initialize(_Parser);
245 // Cache the MCRegisterInfo.
246 MRI = &getContext().getRegisterInfo();
248 // Initialize the set of available features.
249 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
251 // Not in an ITBlock to start with.
252 ITState.CurPosition = ~0U;
255 // Implementation of the MCTargetAsmParser interface:
256 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
257 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
259 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
260 bool ParseDirective(AsmToken DirectiveID);
262 unsigned checkTargetMatchPredicate(MCInst &Inst);
264 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
265 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
266 MCStreamer &Out, unsigned &ErrorInfo,
267 bool MatchingInlineAsm);
269 } // end anonymous namespace
273 /// ARMOperand - Instances of this class represent a parsed ARM machine
275 class ARMOperand : public MCParsedAsmOperand {
295 k_VectorListAllLanes,
301 k_BitfieldDescriptor,
305 SMLoc StartLoc, EndLoc;
306 SmallVector<unsigned, 8> Registers;
310 ARMCC::CondCodes Val;
330 ARM_PROC::IFlags Val;
346 // A vector register list is a sequential list of 1 to 4 registers.
362 /// Combined record for all forms of ARM address expressions.
365 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
367 const MCConstantExpr *OffsetImm; // Offset immediate value
368 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
369 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
370 unsigned ShiftImm; // shift for OffsetReg.
371 unsigned Alignment; // 0 = no alignment specified
372 // n = alignment in bytes (2, 4, 8, 16, or 32)
373 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
379 ARM_AM::ShiftOpc ShiftTy;
388 ARM_AM::ShiftOpc ShiftTy;
394 ARM_AM::ShiftOpc ShiftTy;
407 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
409 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
411 StartLoc = o.StartLoc;
428 case k_DPRRegisterList:
429 case k_SPRRegisterList:
430 Registers = o.Registers;
433 case k_VectorListAllLanes:
434 case k_VectorListIndexed:
435 VectorList = o.VectorList;
442 CoprocOption = o.CoprocOption;
447 case k_MemBarrierOpt:
453 case k_PostIndexRegister:
454 PostIdxReg = o.PostIdxReg;
462 case k_ShifterImmediate:
463 ShifterImm = o.ShifterImm;
465 case k_ShiftedRegister:
466 RegShiftedReg = o.RegShiftedReg;
468 case k_ShiftedImmediate:
469 RegShiftedImm = o.RegShiftedImm;
471 case k_RotateImmediate:
474 case k_BitfieldDescriptor:
475 Bitfield = o.Bitfield;
478 VectorIndex = o.VectorIndex;
483 /// getStartLoc - Get the location of the first token of this operand.
484 SMLoc getStartLoc() const { return StartLoc; }
485 /// getEndLoc - Get the location of the last token of this operand.
486 SMLoc getEndLoc() const { return EndLoc; }
487 /// getLocRange - Get the range between the first and last token of this
489 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
491 ARMCC::CondCodes getCondCode() const {
492 assert(Kind == k_CondCode && "Invalid access!");
496 unsigned getCoproc() const {
497 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
501 StringRef getToken() const {
502 assert(Kind == k_Token && "Invalid access!");
503 return StringRef(Tok.Data, Tok.Length);
506 unsigned getReg() const {
507 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
511 const SmallVectorImpl<unsigned> &getRegList() const {
512 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
513 Kind == k_SPRRegisterList) && "Invalid access!");
517 const MCExpr *getImm() const {
518 assert(isImm() && "Invalid access!");
522 unsigned getVectorIndex() const {
523 assert(Kind == k_VectorIndex && "Invalid access!");
524 return VectorIndex.Val;
527 ARM_MB::MemBOpt getMemBarrierOpt() const {
528 assert(Kind == k_MemBarrierOpt && "Invalid access!");
532 ARM_PROC::IFlags getProcIFlags() const {
533 assert(Kind == k_ProcIFlags && "Invalid access!");
537 unsigned getMSRMask() const {
538 assert(Kind == k_MSRMask && "Invalid access!");
542 bool isCoprocNum() const { return Kind == k_CoprocNum; }
543 bool isCoprocReg() const { return Kind == k_CoprocReg; }
544 bool isCoprocOption() const { return Kind == k_CoprocOption; }
545 bool isCondCode() const { return Kind == k_CondCode; }
546 bool isCCOut() const { return Kind == k_CCOut; }
547 bool isITMask() const { return Kind == k_ITCondMask; }
548 bool isITCondCode() const { return Kind == k_CondCode; }
549 bool isImm() const { return Kind == k_Immediate; }
550 bool isFPImm() const {
551 if (!isImm()) return false;
552 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
553 if (!CE) return false;
554 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
557 bool isFBits16() const {
558 if (!isImm()) return false;
559 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
560 if (!CE) return false;
561 int64_t Value = CE->getValue();
562 return Value >= 0 && Value <= 16;
564 bool isFBits32() const {
565 if (!isImm()) return false;
566 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
567 if (!CE) return false;
568 int64_t Value = CE->getValue();
569 return Value >= 1 && Value <= 32;
571 bool isImm8s4() const {
572 if (!isImm()) return false;
573 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
574 if (!CE) return false;
575 int64_t Value = CE->getValue();
576 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
578 bool isImm0_1020s4() const {
579 if (!isImm()) return false;
580 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
581 if (!CE) return false;
582 int64_t Value = CE->getValue();
583 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
585 bool isImm0_508s4() const {
586 if (!isImm()) return false;
587 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
588 if (!CE) return false;
589 int64_t Value = CE->getValue();
590 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
592 bool isImm0_508s4Neg() const {
593 if (!isImm()) return false;
594 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
595 if (!CE) return false;
596 int64_t Value = -CE->getValue();
597 // explicitly exclude zero. we want that to use the normal 0_508 version.
598 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
600 bool isImm0_255() const {
601 if (!isImm()) return false;
602 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
603 if (!CE) return false;
604 int64_t Value = CE->getValue();
605 return Value >= 0 && Value < 256;
607 bool isImm0_4095() const {
608 if (!isImm()) return false;
609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
610 if (!CE) return false;
611 int64_t Value = CE->getValue();
612 return Value >= 0 && Value < 4096;
614 bool isImm0_4095Neg() const {
615 if (!isImm()) return false;
616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
617 if (!CE) return false;
618 int64_t Value = -CE->getValue();
619 return Value > 0 && Value < 4096;
621 bool isImm0_1() const {
622 if (!isImm()) return false;
623 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
624 if (!CE) return false;
625 int64_t Value = CE->getValue();
626 return Value >= 0 && Value < 2;
628 bool isImm0_3() const {
629 if (!isImm()) return false;
630 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
631 if (!CE) return false;
632 int64_t Value = CE->getValue();
633 return Value >= 0 && Value < 4;
635 bool isImm0_7() const {
636 if (!isImm()) return false;
637 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
638 if (!CE) return false;
639 int64_t Value = CE->getValue();
640 return Value >= 0 && Value < 8;
642 bool isImm0_15() const {
643 if (!isImm()) return false;
644 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
645 if (!CE) return false;
646 int64_t Value = CE->getValue();
647 return Value >= 0 && Value < 16;
649 bool isImm0_31() const {
650 if (!isImm()) return false;
651 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
652 if (!CE) return false;
653 int64_t Value = CE->getValue();
654 return Value >= 0 && Value < 32;
656 bool isImm0_63() const {
657 if (!isImm()) return false;
658 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
659 if (!CE) return false;
660 int64_t Value = CE->getValue();
661 return Value >= 0 && Value < 64;
663 bool isImm8() const {
664 if (!isImm()) return false;
665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
666 if (!CE) return false;
667 int64_t Value = CE->getValue();
670 bool isImm16() const {
671 if (!isImm()) return false;
672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
673 if (!CE) return false;
674 int64_t Value = CE->getValue();
677 bool isImm32() const {
678 if (!isImm()) return false;
679 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
680 if (!CE) return false;
681 int64_t Value = CE->getValue();
684 bool isShrImm8() const {
685 if (!isImm()) return false;
686 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
687 if (!CE) return false;
688 int64_t Value = CE->getValue();
689 return Value > 0 && Value <= 8;
691 bool isShrImm16() const {
692 if (!isImm()) return false;
693 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
694 if (!CE) return false;
695 int64_t Value = CE->getValue();
696 return Value > 0 && Value <= 16;
698 bool isShrImm32() const {
699 if (!isImm()) return false;
700 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
701 if (!CE) return false;
702 int64_t Value = CE->getValue();
703 return Value > 0 && Value <= 32;
705 bool isShrImm64() const {
706 if (!isImm()) return false;
707 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
708 if (!CE) return false;
709 int64_t Value = CE->getValue();
710 return Value > 0 && Value <= 64;
712 bool isImm1_7() const {
713 if (!isImm()) return false;
714 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
715 if (!CE) return false;
716 int64_t Value = CE->getValue();
717 return Value > 0 && Value < 8;
719 bool isImm1_15() const {
720 if (!isImm()) return false;
721 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
722 if (!CE) return false;
723 int64_t Value = CE->getValue();
724 return Value > 0 && Value < 16;
726 bool isImm1_31() const {
727 if (!isImm()) return false;
728 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
729 if (!CE) return false;
730 int64_t Value = CE->getValue();
731 return Value > 0 && Value < 32;
733 bool isImm1_16() const {
734 if (!isImm()) return false;
735 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
736 if (!CE) return false;
737 int64_t Value = CE->getValue();
738 return Value > 0 && Value < 17;
740 bool isImm1_32() const {
741 if (!isImm()) return false;
742 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
743 if (!CE) return false;
744 int64_t Value = CE->getValue();
745 return Value > 0 && Value < 33;
747 bool isImm0_32() const {
748 if (!isImm()) return false;
749 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
750 if (!CE) return false;
751 int64_t Value = CE->getValue();
752 return Value >= 0 && Value < 33;
754 bool isImm0_65535() const {
755 if (!isImm()) return false;
756 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
757 if (!CE) return false;
758 int64_t Value = CE->getValue();
759 return Value >= 0 && Value < 65536;
761 bool isImm0_65535Expr() const {
762 if (!isImm()) return false;
763 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
764 // If it's not a constant expression, it'll generate a fixup and be
766 if (!CE) return true;
767 int64_t Value = CE->getValue();
768 return Value >= 0 && Value < 65536;
770 bool isImm24bit() const {
771 if (!isImm()) return false;
772 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
773 if (!CE) return false;
774 int64_t Value = CE->getValue();
775 return Value >= 0 && Value <= 0xffffff;
777 bool isImmThumbSR() const {
778 if (!isImm()) return false;
779 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
780 if (!CE) return false;
781 int64_t Value = CE->getValue();
782 return Value > 0 && Value < 33;
784 bool isPKHLSLImm() const {
785 if (!isImm()) return false;
786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
787 if (!CE) return false;
788 int64_t Value = CE->getValue();
789 return Value >= 0 && Value < 32;
791 bool isPKHASRImm() const {
792 if (!isImm()) return false;
793 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
794 if (!CE) return false;
795 int64_t Value = CE->getValue();
796 return Value > 0 && Value <= 32;
798 bool isAdrLabel() const {
799 // If we have an immediate that's not a constant, treat it as a label
800 // reference needing a fixup. If it is a constant, but it can't fit
801 // into shift immediate encoding, we reject it.
802 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
803 else return (isARMSOImm() || isARMSOImmNeg());
805 bool isARMSOImm() const {
806 if (!isImm()) return false;
807 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
808 if (!CE) return false;
809 int64_t Value = CE->getValue();
810 return ARM_AM::getSOImmVal(Value) != -1;
812 bool isARMSOImmNot() const {
813 if (!isImm()) return false;
814 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
815 if (!CE) return false;
816 int64_t Value = CE->getValue();
817 return ARM_AM::getSOImmVal(~Value) != -1;
819 bool isARMSOImmNeg() const {
820 if (!isImm()) return false;
821 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
822 if (!CE) return false;
823 int64_t Value = CE->getValue();
824 // Only use this when not representable as a plain so_imm.
825 return ARM_AM::getSOImmVal(Value) == -1 &&
826 ARM_AM::getSOImmVal(-Value) != -1;
828 bool isT2SOImm() const {
829 if (!isImm()) return false;
830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
831 if (!CE) return false;
832 int64_t Value = CE->getValue();
833 return ARM_AM::getT2SOImmVal(Value) != -1;
835 bool isT2SOImmNot() const {
836 if (!isImm()) return false;
837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
838 if (!CE) return false;
839 int64_t Value = CE->getValue();
840 return ARM_AM::getT2SOImmVal(~Value) != -1;
842 bool isT2SOImmNeg() const {
843 if (!isImm()) return false;
844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
845 if (!CE) return false;
846 int64_t Value = CE->getValue();
847 // Only use this when not representable as a plain so_imm.
848 return ARM_AM::getT2SOImmVal(Value) == -1 &&
849 ARM_AM::getT2SOImmVal(-Value) != -1;
851 bool isSetEndImm() const {
852 if (!isImm()) return false;
853 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
854 if (!CE) return false;
855 int64_t Value = CE->getValue();
856 return Value == 1 || Value == 0;
858 bool isReg() const { return Kind == k_Register; }
859 bool isRegList() const { return Kind == k_RegisterList; }
860 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
861 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
862 bool isToken() const { return Kind == k_Token; }
863 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
864 bool isMem() const { return Kind == k_Memory; }
865 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
866 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
867 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
868 bool isRotImm() const { return Kind == k_RotateImmediate; }
869 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
870 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
871 bool isPostIdxReg() const {
872 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
874 bool isMemNoOffset(bool alignOK = false) const {
877 // No offset of any kind.
878 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
879 (alignOK || Memory.Alignment == 0);
881 bool isMemPCRelImm12() const {
882 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
884 // Base register must be PC.
885 if (Memory.BaseRegNum != ARM::PC)
887 // Immediate offset in range [-4095, 4095].
888 if (!Memory.OffsetImm) return true;
889 int64_t Val = Memory.OffsetImm->getValue();
890 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
892 bool isAlignedMemory() const {
893 return isMemNoOffset(true);
895 bool isAddrMode2() const {
896 if (!isMem() || Memory.Alignment != 0) return false;
897 // Check for register offset.
898 if (Memory.OffsetRegNum) return true;
899 // Immediate offset in range [-4095, 4095].
900 if (!Memory.OffsetImm) return true;
901 int64_t Val = Memory.OffsetImm->getValue();
902 return Val > -4096 && Val < 4096;
904 bool isAM2OffsetImm() const {
905 if (!isImm()) return false;
906 // Immediate offset in range [-4095, 4095].
907 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
908 if (!CE) return false;
909 int64_t Val = CE->getValue();
910 return Val > -4096 && Val < 4096;
912 bool isAddrMode3() const {
913 // If we have an immediate that's not a constant, treat it as a label
914 // reference needing a fixup. If it is a constant, it's something else
916 if (isImm() && !isa<MCConstantExpr>(getImm()))
918 if (!isMem() || Memory.Alignment != 0) return false;
919 // No shifts are legal for AM3.
920 if (Memory.ShiftType != ARM_AM::no_shift) return false;
921 // Check for register offset.
922 if (Memory.OffsetRegNum) return true;
923 // Immediate offset in range [-255, 255].
924 if (!Memory.OffsetImm) return true;
925 int64_t Val = Memory.OffsetImm->getValue();
926 // The #-0 offset is encoded as INT32_MIN, and we have to check
928 return (Val > -256 && Val < 256) || Val == INT32_MIN;
930 bool isAM3Offset() const {
931 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
933 if (Kind == k_PostIndexRegister)
934 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
935 // Immediate offset in range [-255, 255].
936 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
937 if (!CE) return false;
938 int64_t Val = CE->getValue();
939 // Special case, #-0 is INT32_MIN.
940 return (Val > -256 && Val < 256) || Val == INT32_MIN;
942 bool isAddrMode5() const {
943 // If we have an immediate that's not a constant, treat it as a label
944 // reference needing a fixup. If it is a constant, it's something else
946 if (isImm() && !isa<MCConstantExpr>(getImm()))
948 if (!isMem() || Memory.Alignment != 0) return false;
949 // Check for register offset.
950 if (Memory.OffsetRegNum) return false;
951 // Immediate offset in range [-1020, 1020] and a multiple of 4.
952 if (!Memory.OffsetImm) return true;
953 int64_t Val = Memory.OffsetImm->getValue();
954 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
957 bool isMemTBB() const {
958 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
959 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
963 bool isMemTBH() const {
964 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
965 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
966 Memory.Alignment != 0 )
970 bool isMemRegOffset() const {
971 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
975 bool isT2MemRegOffset() const {
976 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
977 Memory.Alignment != 0)
979 // Only lsl #{0, 1, 2, 3} allowed.
980 if (Memory.ShiftType == ARM_AM::no_shift)
982 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
986 bool isMemThumbRR() const {
987 // Thumb reg+reg addressing is simple. Just two registers, a base and
988 // an offset. No shifts, negations or any other complicating factors.
989 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
990 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
992 return isARMLowRegister(Memory.BaseRegNum) &&
993 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
995 bool isMemThumbRIs4() const {
996 if (!isMem() || Memory.OffsetRegNum != 0 ||
997 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
999 // Immediate offset, multiple of 4 in range [0, 124].
1000 if (!Memory.OffsetImm) return true;
1001 int64_t Val = Memory.OffsetImm->getValue();
1002 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1004 bool isMemThumbRIs2() const {
1005 if (!isMem() || Memory.OffsetRegNum != 0 ||
1006 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1008 // Immediate offset, multiple of 4 in range [0, 62].
1009 if (!Memory.OffsetImm) return true;
1010 int64_t Val = Memory.OffsetImm->getValue();
1011 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1013 bool isMemThumbRIs1() const {
1014 if (!isMem() || Memory.OffsetRegNum != 0 ||
1015 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1017 // Immediate offset in range [0, 31].
1018 if (!Memory.OffsetImm) return true;
1019 int64_t Val = Memory.OffsetImm->getValue();
1020 return Val >= 0 && Val <= 31;
1022 bool isMemThumbSPI() const {
1023 if (!isMem() || Memory.OffsetRegNum != 0 ||
1024 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1026 // Immediate offset, multiple of 4 in range [0, 1020].
1027 if (!Memory.OffsetImm) return true;
1028 int64_t Val = Memory.OffsetImm->getValue();
1029 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1031 bool isMemImm8s4Offset() const {
1032 // If we have an immediate that's not a constant, treat it as a label
1033 // reference needing a fixup. If it is a constant, it's something else
1034 // and we reject it.
1035 if (isImm() && !isa<MCConstantExpr>(getImm()))
1037 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1039 // Immediate offset a multiple of 4 in range [-1020, 1020].
1040 if (!Memory.OffsetImm) return true;
1041 int64_t Val = Memory.OffsetImm->getValue();
1042 // Special case, #-0 is INT32_MIN.
1043 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1045 bool isMemImm0_1020s4Offset() const {
1046 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1048 // Immediate offset a multiple of 4 in range [0, 1020].
1049 if (!Memory.OffsetImm) return true;
1050 int64_t Val = Memory.OffsetImm->getValue();
1051 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1053 bool isMemImm8Offset() const {
1054 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1056 // Base reg of PC isn't allowed for these encodings.
1057 if (Memory.BaseRegNum == ARM::PC) return false;
1058 // Immediate offset in range [-255, 255].
1059 if (!Memory.OffsetImm) return true;
1060 int64_t Val = Memory.OffsetImm->getValue();
1061 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1063 bool isMemPosImm8Offset() const {
1064 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1066 // Immediate offset in range [0, 255].
1067 if (!Memory.OffsetImm) return true;
1068 int64_t Val = Memory.OffsetImm->getValue();
1069 return Val >= 0 && Val < 256;
1071 bool isMemNegImm8Offset() const {
1072 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1074 // Base reg of PC isn't allowed for these encodings.
1075 if (Memory.BaseRegNum == ARM::PC) return false;
1076 // Immediate offset in range [-255, -1].
1077 if (!Memory.OffsetImm) return false;
1078 int64_t Val = Memory.OffsetImm->getValue();
1079 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1081 bool isMemUImm12Offset() const {
1082 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1084 // Immediate offset in range [0, 4095].
1085 if (!Memory.OffsetImm) return true;
1086 int64_t Val = Memory.OffsetImm->getValue();
1087 return (Val >= 0 && Val < 4096);
1089 bool isMemImm12Offset() const {
1090 // If we have an immediate that's not a constant, treat it as a label
1091 // reference needing a fixup. If it is a constant, it's something else
1092 // and we reject it.
1093 if (isImm() && !isa<MCConstantExpr>(getImm()))
1096 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1098 // Immediate offset in range [-4095, 4095].
1099 if (!Memory.OffsetImm) return true;
1100 int64_t Val = Memory.OffsetImm->getValue();
1101 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1103 bool isPostIdxImm8() const {
1104 if (!isImm()) return false;
1105 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1106 if (!CE) return false;
1107 int64_t Val = CE->getValue();
1108 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1110 bool isPostIdxImm8s4() const {
1111 if (!isImm()) return false;
1112 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1113 if (!CE) return false;
1114 int64_t Val = CE->getValue();
1115 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1119 bool isMSRMask() const { return Kind == k_MSRMask; }
1120 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1123 bool isSingleSpacedVectorList() const {
1124 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1126 bool isDoubleSpacedVectorList() const {
1127 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1129 bool isVecListOneD() const {
1130 if (!isSingleSpacedVectorList()) return false;
1131 return VectorList.Count == 1;
1134 bool isVecListDPair() const {
1135 if (!isSingleSpacedVectorList()) return false;
1136 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1137 .contains(VectorList.RegNum));
1140 bool isVecListThreeD() const {
1141 if (!isSingleSpacedVectorList()) return false;
1142 return VectorList.Count == 3;
1145 bool isVecListFourD() const {
1146 if (!isSingleSpacedVectorList()) return false;
1147 return VectorList.Count == 4;
1150 bool isVecListDPairSpaced() const {
1151 if (isSingleSpacedVectorList()) return false;
1152 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1153 .contains(VectorList.RegNum));
1156 bool isVecListThreeQ() const {
1157 if (!isDoubleSpacedVectorList()) return false;
1158 return VectorList.Count == 3;
1161 bool isVecListFourQ() const {
1162 if (!isDoubleSpacedVectorList()) return false;
1163 return VectorList.Count == 4;
1166 bool isSingleSpacedVectorAllLanes() const {
1167 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1169 bool isDoubleSpacedVectorAllLanes() const {
1170 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1172 bool isVecListOneDAllLanes() const {
1173 if (!isSingleSpacedVectorAllLanes()) return false;
1174 return VectorList.Count == 1;
1177 bool isVecListDPairAllLanes() const {
1178 if (!isSingleSpacedVectorAllLanes()) return false;
1179 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1180 .contains(VectorList.RegNum));
1183 bool isVecListDPairSpacedAllLanes() const {
1184 if (!isDoubleSpacedVectorAllLanes()) return false;
1185 return VectorList.Count == 2;
1188 bool isVecListThreeDAllLanes() const {
1189 if (!isSingleSpacedVectorAllLanes()) return false;
1190 return VectorList.Count == 3;
1193 bool isVecListThreeQAllLanes() const {
1194 if (!isDoubleSpacedVectorAllLanes()) return false;
1195 return VectorList.Count == 3;
1198 bool isVecListFourDAllLanes() const {
1199 if (!isSingleSpacedVectorAllLanes()) return false;
1200 return VectorList.Count == 4;
1203 bool isVecListFourQAllLanes() const {
1204 if (!isDoubleSpacedVectorAllLanes()) return false;
1205 return VectorList.Count == 4;
1208 bool isSingleSpacedVectorIndexed() const {
1209 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1211 bool isDoubleSpacedVectorIndexed() const {
1212 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1214 bool isVecListOneDByteIndexed() const {
1215 if (!isSingleSpacedVectorIndexed()) return false;
1216 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1219 bool isVecListOneDHWordIndexed() const {
1220 if (!isSingleSpacedVectorIndexed()) return false;
1221 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1224 bool isVecListOneDWordIndexed() const {
1225 if (!isSingleSpacedVectorIndexed()) return false;
1226 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1229 bool isVecListTwoDByteIndexed() const {
1230 if (!isSingleSpacedVectorIndexed()) return false;
1231 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1234 bool isVecListTwoDHWordIndexed() const {
1235 if (!isSingleSpacedVectorIndexed()) return false;
1236 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1239 bool isVecListTwoQWordIndexed() const {
1240 if (!isDoubleSpacedVectorIndexed()) return false;
1241 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1244 bool isVecListTwoQHWordIndexed() const {
1245 if (!isDoubleSpacedVectorIndexed()) return false;
1246 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1249 bool isVecListTwoDWordIndexed() const {
1250 if (!isSingleSpacedVectorIndexed()) return false;
1251 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1254 bool isVecListThreeDByteIndexed() const {
1255 if (!isSingleSpacedVectorIndexed()) return false;
1256 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1259 bool isVecListThreeDHWordIndexed() const {
1260 if (!isSingleSpacedVectorIndexed()) return false;
1261 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1264 bool isVecListThreeQWordIndexed() const {
1265 if (!isDoubleSpacedVectorIndexed()) return false;
1266 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1269 bool isVecListThreeQHWordIndexed() const {
1270 if (!isDoubleSpacedVectorIndexed()) return false;
1271 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1274 bool isVecListThreeDWordIndexed() const {
1275 if (!isSingleSpacedVectorIndexed()) return false;
1276 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1279 bool isVecListFourDByteIndexed() const {
1280 if (!isSingleSpacedVectorIndexed()) return false;
1281 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1284 bool isVecListFourDHWordIndexed() const {
1285 if (!isSingleSpacedVectorIndexed()) return false;
1286 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1289 bool isVecListFourQWordIndexed() const {
1290 if (!isDoubleSpacedVectorIndexed()) return false;
1291 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1294 bool isVecListFourQHWordIndexed() const {
1295 if (!isDoubleSpacedVectorIndexed()) return false;
1296 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1299 bool isVecListFourDWordIndexed() const {
1300 if (!isSingleSpacedVectorIndexed()) return false;
1301 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1304 bool isVectorIndex8() const {
1305 if (Kind != k_VectorIndex) return false;
1306 return VectorIndex.Val < 8;
1308 bool isVectorIndex16() const {
1309 if (Kind != k_VectorIndex) return false;
1310 return VectorIndex.Val < 4;
1312 bool isVectorIndex32() const {
1313 if (Kind != k_VectorIndex) return false;
1314 return VectorIndex.Val < 2;
1317 bool isNEONi8splat() const {
1318 if (!isImm()) return false;
1319 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1320 // Must be a constant.
1321 if (!CE) return false;
1322 int64_t Value = CE->getValue();
1323 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1325 return Value >= 0 && Value < 256;
1328 bool isNEONi16splat() const {
1329 if (!isImm()) return false;
1330 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1331 // Must be a constant.
1332 if (!CE) return false;
1333 int64_t Value = CE->getValue();
1334 // i16 value in the range [0,255] or [0x0100, 0xff00]
1335 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1338 bool isNEONi32splat() const {
1339 if (!isImm()) return false;
1340 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1341 // Must be a constant.
1342 if (!CE) return false;
1343 int64_t Value = CE->getValue();
1344 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1345 return (Value >= 0 && Value < 256) ||
1346 (Value >= 0x0100 && Value <= 0xff00) ||
1347 (Value >= 0x010000 && Value <= 0xff0000) ||
1348 (Value >= 0x01000000 && Value <= 0xff000000);
1351 bool isNEONi32vmov() const {
1352 if (!isImm()) return false;
1353 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1354 // Must be a constant.
1355 if (!CE) return false;
1356 int64_t Value = CE->getValue();
1357 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1358 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1359 return (Value >= 0 && Value < 256) ||
1360 (Value >= 0x0100 && Value <= 0xff00) ||
1361 (Value >= 0x010000 && Value <= 0xff0000) ||
1362 (Value >= 0x01000000 && Value <= 0xff000000) ||
1363 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1364 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1366 bool isNEONi32vmovNeg() const {
1367 if (!isImm()) return false;
1368 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1369 // Must be a constant.
1370 if (!CE) return false;
1371 int64_t Value = ~CE->getValue();
1372 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1373 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1374 return (Value >= 0 && Value < 256) ||
1375 (Value >= 0x0100 && Value <= 0xff00) ||
1376 (Value >= 0x010000 && Value <= 0xff0000) ||
1377 (Value >= 0x01000000 && Value <= 0xff000000) ||
1378 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1379 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1382 bool isNEONi64splat() const {
1383 if (!isImm()) return false;
1384 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1385 // Must be a constant.
1386 if (!CE) return false;
1387 uint64_t Value = CE->getValue();
1388 // i64 value with each byte being either 0 or 0xff.
1389 for (unsigned i = 0; i < 8; ++i)
1390 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1394 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1395 // Add as immediates when possible. Null MCExpr = 0.
1397 Inst.addOperand(MCOperand::CreateImm(0));
1398 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1399 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1401 Inst.addOperand(MCOperand::CreateExpr(Expr));
1404 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1405 assert(N == 2 && "Invalid number of operands!");
1406 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1407 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1408 Inst.addOperand(MCOperand::CreateReg(RegNum));
1411 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1412 assert(N == 1 && "Invalid number of operands!");
1413 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1416 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1417 assert(N == 1 && "Invalid number of operands!");
1418 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1421 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1422 assert(N == 1 && "Invalid number of operands!");
1423 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1426 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1427 assert(N == 1 && "Invalid number of operands!");
1428 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1431 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1432 assert(N == 1 && "Invalid number of operands!");
1433 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1436 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1437 assert(N == 1 && "Invalid number of operands!");
1438 Inst.addOperand(MCOperand::CreateReg(getReg()));
1441 void addRegOperands(MCInst &Inst, unsigned N) const {
1442 assert(N == 1 && "Invalid number of operands!");
1443 Inst.addOperand(MCOperand::CreateReg(getReg()));
1446 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1447 assert(N == 3 && "Invalid number of operands!");
1448 assert(isRegShiftedReg() &&
1449 "addRegShiftedRegOperands() on non RegShiftedReg!");
1450 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1451 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1452 Inst.addOperand(MCOperand::CreateImm(
1453 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1456 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1457 assert(N == 2 && "Invalid number of operands!");
1458 assert(isRegShiftedImm() &&
1459 "addRegShiftedImmOperands() on non RegShiftedImm!");
1460 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1461 // Shift of #32 is encoded as 0 where permitted
1462 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1463 Inst.addOperand(MCOperand::CreateImm(
1464 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1467 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1468 assert(N == 1 && "Invalid number of operands!");
1469 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1473 void addRegListOperands(MCInst &Inst, unsigned N) const {
1474 assert(N == 1 && "Invalid number of operands!");
1475 const SmallVectorImpl<unsigned> &RegList = getRegList();
1476 for (SmallVectorImpl<unsigned>::const_iterator
1477 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1478 Inst.addOperand(MCOperand::CreateReg(*I));
1481 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1482 addRegListOperands(Inst, N);
1485 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1486 addRegListOperands(Inst, N);
1489 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1490 assert(N == 1 && "Invalid number of operands!");
1491 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1492 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1495 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1496 assert(N == 1 && "Invalid number of operands!");
1497 // Munge the lsb/width into a bitfield mask.
1498 unsigned lsb = Bitfield.LSB;
1499 unsigned width = Bitfield.Width;
1500 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1501 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1502 (32 - (lsb + width)));
1503 Inst.addOperand(MCOperand::CreateImm(Mask));
1506 void addImmOperands(MCInst &Inst, unsigned N) const {
1507 assert(N == 1 && "Invalid number of operands!");
1508 addExpr(Inst, getImm());
1511 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1512 assert(N == 1 && "Invalid number of operands!");
1513 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1514 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1517 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1518 assert(N == 1 && "Invalid number of operands!");
1519 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1520 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1523 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1524 assert(N == 1 && "Invalid number of operands!");
1525 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1526 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1527 Inst.addOperand(MCOperand::CreateImm(Val));
1530 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1531 assert(N == 1 && "Invalid number of operands!");
1532 // FIXME: We really want to scale the value here, but the LDRD/STRD
1533 // instruction don't encode operands that way yet.
1534 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1535 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1538 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1539 assert(N == 1 && "Invalid number of operands!");
1540 // The immediate is scaled by four in the encoding and is stored
1541 // in the MCInst as such. Lop off the low two bits here.
1542 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1543 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1546 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1547 assert(N == 1 && "Invalid number of operands!");
1548 // The immediate is scaled by four in the encoding and is stored
1549 // in the MCInst as such. Lop off the low two bits here.
1550 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1551 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1554 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1555 assert(N == 1 && "Invalid number of operands!");
1556 // The immediate is scaled by four in the encoding and is stored
1557 // in the MCInst as such. Lop off the low two bits here.
1558 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1559 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1562 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1563 assert(N == 1 && "Invalid number of operands!");
1564 // The constant encodes as the immediate-1, and we store in the instruction
1565 // the bits as encoded, so subtract off one here.
1566 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1567 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1570 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1571 assert(N == 1 && "Invalid number of operands!");
1572 // The constant encodes as the immediate-1, and we store in the instruction
1573 // the bits as encoded, so subtract off one here.
1574 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1575 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1578 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1579 assert(N == 1 && "Invalid number of operands!");
1580 // The constant encodes as the immediate, except for 32, which encodes as
1582 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1583 unsigned Imm = CE->getValue();
1584 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1587 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1588 assert(N == 1 && "Invalid number of operands!");
1589 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1590 // the instruction as well.
1591 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1592 int Val = CE->getValue();
1593 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1596 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1597 assert(N == 1 && "Invalid number of operands!");
1598 // The operand is actually a t2_so_imm, but we have its bitwise
1599 // negation in the assembly source, so twiddle it here.
1600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1601 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1604 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1605 assert(N == 1 && "Invalid number of operands!");
1606 // The operand is actually a t2_so_imm, but we have its
1607 // negation in the assembly source, so twiddle it here.
1608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1609 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1612 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1613 assert(N == 1 && "Invalid number of operands!");
1614 // The operand is actually an imm0_4095, but we have its
1615 // negation in the assembly source, so twiddle it here.
1616 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1617 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1620 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1621 assert(N == 1 && "Invalid number of operands!");
1622 // The operand is actually a so_imm, but we have its bitwise
1623 // negation in the assembly source, so twiddle it here.
1624 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1625 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1628 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1629 assert(N == 1 && "Invalid number of operands!");
1630 // The operand is actually a so_imm, but we have its
1631 // negation in the assembly source, so twiddle it here.
1632 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1633 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1636 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1637 assert(N == 1 && "Invalid number of operands!");
1638 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1641 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1642 assert(N == 1 && "Invalid number of operands!");
1643 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1646 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1647 assert(N == 1 && "Invalid number of operands!");
1648 int32_t Imm = Memory.OffsetImm->getValue();
1649 // FIXME: Handle #-0
1650 if (Imm == INT32_MIN) Imm = 0;
1651 Inst.addOperand(MCOperand::CreateImm(Imm));
1654 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1655 assert(N == 1 && "Invalid number of operands!");
1656 assert(isImm() && "Not an immediate!");
1658 // If we have an immediate that's not a constant, treat it as a label
1659 // reference needing a fixup.
1660 if (!isa<MCConstantExpr>(getImm())) {
1661 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1665 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1666 int Val = CE->getValue();
1667 Inst.addOperand(MCOperand::CreateImm(Val));
1670 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1671 assert(N == 2 && "Invalid number of operands!");
1672 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1673 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1676 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1677 assert(N == 3 && "Invalid number of operands!");
1678 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1679 if (!Memory.OffsetRegNum) {
1680 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1681 // Special case for #-0
1682 if (Val == INT32_MIN) Val = 0;
1683 if (Val < 0) Val = -Val;
1684 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1686 // For register offset, we encode the shift type and negation flag
1688 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1689 Memory.ShiftImm, Memory.ShiftType);
1691 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1692 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1693 Inst.addOperand(MCOperand::CreateImm(Val));
1696 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1697 assert(N == 2 && "Invalid number of operands!");
1698 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1699 assert(CE && "non-constant AM2OffsetImm operand!");
1700 int32_t Val = CE->getValue();
1701 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1702 // Special case for #-0
1703 if (Val == INT32_MIN) Val = 0;
1704 if (Val < 0) Val = -Val;
1705 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1706 Inst.addOperand(MCOperand::CreateReg(0));
1707 Inst.addOperand(MCOperand::CreateImm(Val));
1710 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1711 assert(N == 3 && "Invalid number of operands!");
1712 // If we have an immediate that's not a constant, treat it as a label
1713 // reference needing a fixup. If it is a constant, it's something else
1714 // and we reject it.
1716 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1717 Inst.addOperand(MCOperand::CreateReg(0));
1718 Inst.addOperand(MCOperand::CreateImm(0));
1722 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1723 if (!Memory.OffsetRegNum) {
1724 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1725 // Special case for #-0
1726 if (Val == INT32_MIN) Val = 0;
1727 if (Val < 0) Val = -Val;
1728 Val = ARM_AM::getAM3Opc(AddSub, Val);
1730 // For register offset, we encode the shift type and negation flag
1732 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1734 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1735 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1736 Inst.addOperand(MCOperand::CreateImm(Val));
1739 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1740 assert(N == 2 && "Invalid number of operands!");
1741 if (Kind == k_PostIndexRegister) {
1743 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1744 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1745 Inst.addOperand(MCOperand::CreateImm(Val));
1750 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1751 int32_t Val = CE->getValue();
1752 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1753 // Special case for #-0
1754 if (Val == INT32_MIN) Val = 0;
1755 if (Val < 0) Val = -Val;
1756 Val = ARM_AM::getAM3Opc(AddSub, Val);
1757 Inst.addOperand(MCOperand::CreateReg(0));
1758 Inst.addOperand(MCOperand::CreateImm(Val));
1761 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1762 assert(N == 2 && "Invalid number of operands!");
1763 // If we have an immediate that's not a constant, treat it as a label
1764 // reference needing a fixup. If it is a constant, it's something else
1765 // and we reject it.
1767 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1768 Inst.addOperand(MCOperand::CreateImm(0));
1772 // The lower two bits are always zero and as such are not encoded.
1773 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1774 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1775 // Special case for #-0
1776 if (Val == INT32_MIN) Val = 0;
1777 if (Val < 0) Val = -Val;
1778 Val = ARM_AM::getAM5Opc(AddSub, Val);
1779 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1780 Inst.addOperand(MCOperand::CreateImm(Val));
1783 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1784 assert(N == 2 && "Invalid number of operands!");
1785 // If we have an immediate that's not a constant, treat it as a label
1786 // reference needing a fixup. If it is a constant, it's something else
1787 // and we reject it.
1789 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1790 Inst.addOperand(MCOperand::CreateImm(0));
1794 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1795 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1796 Inst.addOperand(MCOperand::CreateImm(Val));
1799 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1800 assert(N == 2 && "Invalid number of operands!");
1801 // The lower two bits are always zero and as such are not encoded.
1802 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
1803 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1804 Inst.addOperand(MCOperand::CreateImm(Val));
1807 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1808 assert(N == 2 && "Invalid number of operands!");
1809 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1810 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1811 Inst.addOperand(MCOperand::CreateImm(Val));
1814 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1815 addMemImm8OffsetOperands(Inst, N);
1818 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1819 addMemImm8OffsetOperands(Inst, N);
1822 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1823 assert(N == 2 && "Invalid number of operands!");
1824 // If this is an immediate, it's a label reference.
1826 addExpr(Inst, getImm());
1827 Inst.addOperand(MCOperand::CreateImm(0));
1831 // Otherwise, it's a normal memory reg+offset.
1832 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1833 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1834 Inst.addOperand(MCOperand::CreateImm(Val));
1837 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1838 assert(N == 2 && "Invalid number of operands!");
1839 // If this is an immediate, it's a label reference.
1841 addExpr(Inst, getImm());
1842 Inst.addOperand(MCOperand::CreateImm(0));
1846 // Otherwise, it's a normal memory reg+offset.
1847 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1848 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1849 Inst.addOperand(MCOperand::CreateImm(Val));
1852 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
1853 assert(N == 2 && "Invalid number of operands!");
1854 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1855 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1858 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
1859 assert(N == 2 && "Invalid number of operands!");
1860 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1861 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1864 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1865 assert(N == 3 && "Invalid number of operands!");
1867 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1868 Memory.ShiftImm, Memory.ShiftType);
1869 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1870 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1871 Inst.addOperand(MCOperand::CreateImm(Val));
1874 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1875 assert(N == 3 && "Invalid number of operands!");
1876 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1877 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1878 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
1881 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1882 assert(N == 2 && "Invalid number of operands!");
1883 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1884 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1887 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1888 assert(N == 2 && "Invalid number of operands!");
1889 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1890 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1891 Inst.addOperand(MCOperand::CreateImm(Val));
1894 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1895 assert(N == 2 && "Invalid number of operands!");
1896 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
1897 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1898 Inst.addOperand(MCOperand::CreateImm(Val));
1901 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1902 assert(N == 2 && "Invalid number of operands!");
1903 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
1904 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1905 Inst.addOperand(MCOperand::CreateImm(Val));
1908 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1909 assert(N == 2 && "Invalid number of operands!");
1910 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
1911 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1912 Inst.addOperand(MCOperand::CreateImm(Val));
1915 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1916 assert(N == 1 && "Invalid number of operands!");
1917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1918 assert(CE && "non-constant post-idx-imm8 operand!");
1919 int Imm = CE->getValue();
1920 bool isAdd = Imm >= 0;
1921 if (Imm == INT32_MIN) Imm = 0;
1922 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1923 Inst.addOperand(MCOperand::CreateImm(Imm));
1926 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
1927 assert(N == 1 && "Invalid number of operands!");
1928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1929 assert(CE && "non-constant post-idx-imm8s4 operand!");
1930 int Imm = CE->getValue();
1931 bool isAdd = Imm >= 0;
1932 if (Imm == INT32_MIN) Imm = 0;
1933 // Immediate is scaled by 4.
1934 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
1935 Inst.addOperand(MCOperand::CreateImm(Imm));
1938 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1939 assert(N == 2 && "Invalid number of operands!");
1940 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1941 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1944 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1945 assert(N == 2 && "Invalid number of operands!");
1946 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1947 // The sign, shift type, and shift amount are encoded in a single operand
1948 // using the AM2 encoding helpers.
1949 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1950 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1951 PostIdxReg.ShiftTy);
1952 Inst.addOperand(MCOperand::CreateImm(Imm));
1955 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1956 assert(N == 1 && "Invalid number of operands!");
1957 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1960 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1961 assert(N == 1 && "Invalid number of operands!");
1962 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1965 void addVecListOperands(MCInst &Inst, unsigned N) const {
1966 assert(N == 1 && "Invalid number of operands!");
1967 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1970 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
1971 assert(N == 2 && "Invalid number of operands!");
1972 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
1973 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
1976 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
1977 assert(N == 1 && "Invalid number of operands!");
1978 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1981 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
1982 assert(N == 1 && "Invalid number of operands!");
1983 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1986 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
1987 assert(N == 1 && "Invalid number of operands!");
1988 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1991 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
1992 assert(N == 1 && "Invalid number of operands!");
1993 // The immediate encodes the type of constant as well as the value.
1994 // Mask in that this is an i8 splat.
1995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1996 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
1999 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2000 assert(N == 1 && "Invalid number of operands!");
2001 // The immediate encodes the type of constant as well as the value.
2002 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2003 unsigned Value = CE->getValue();
2005 Value = (Value >> 8) | 0xa00;
2008 Inst.addOperand(MCOperand::CreateImm(Value));
2011 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2012 assert(N == 1 && "Invalid number of operands!");
2013 // The immediate encodes the type of constant as well as the value.
2014 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2015 unsigned Value = CE->getValue();
2016 if (Value >= 256 && Value <= 0xff00)
2017 Value = (Value >> 8) | 0x200;
2018 else if (Value > 0xffff && Value <= 0xff0000)
2019 Value = (Value >> 16) | 0x400;
2020 else if (Value > 0xffffff)
2021 Value = (Value >> 24) | 0x600;
2022 Inst.addOperand(MCOperand::CreateImm(Value));
2025 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2026 assert(N == 1 && "Invalid number of operands!");
2027 // The immediate encodes the type of constant as well as the value.
2028 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2029 unsigned Value = CE->getValue();
2030 if (Value >= 256 && Value <= 0xffff)
2031 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2032 else if (Value > 0xffff && Value <= 0xffffff)
2033 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2034 else if (Value > 0xffffff)
2035 Value = (Value >> 24) | 0x600;
2036 Inst.addOperand(MCOperand::CreateImm(Value));
2039 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2040 assert(N == 1 && "Invalid number of operands!");
2041 // The immediate encodes the type of constant as well as the value.
2042 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2043 unsigned Value = ~CE->getValue();
2044 if (Value >= 256 && Value <= 0xffff)
2045 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2046 else if (Value > 0xffff && Value <= 0xffffff)
2047 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2048 else if (Value > 0xffffff)
2049 Value = (Value >> 24) | 0x600;
2050 Inst.addOperand(MCOperand::CreateImm(Value));
2053 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2054 assert(N == 1 && "Invalid number of operands!");
2055 // The immediate encodes the type of constant as well as the value.
2056 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2057 uint64_t Value = CE->getValue();
2059 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2060 Imm |= (Value & 1) << i;
2062 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2065 virtual void print(raw_ostream &OS) const;
2067 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2068 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2069 Op->ITMask.Mask = Mask;
2075 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2076 ARMOperand *Op = new ARMOperand(k_CondCode);
2083 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2084 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2085 Op->Cop.Val = CopVal;
2091 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2092 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2093 Op->Cop.Val = CopVal;
2099 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2100 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2107 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2108 ARMOperand *Op = new ARMOperand(k_CCOut);
2109 Op->Reg.RegNum = RegNum;
2115 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2116 ARMOperand *Op = new ARMOperand(k_Token);
2117 Op->Tok.Data = Str.data();
2118 Op->Tok.Length = Str.size();
2124 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2125 ARMOperand *Op = new ARMOperand(k_Register);
2126 Op->Reg.RegNum = RegNum;
2132 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2137 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2138 Op->RegShiftedReg.ShiftTy = ShTy;
2139 Op->RegShiftedReg.SrcReg = SrcReg;
2140 Op->RegShiftedReg.ShiftReg = ShiftReg;
2141 Op->RegShiftedReg.ShiftImm = ShiftImm;
2147 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2151 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2152 Op->RegShiftedImm.ShiftTy = ShTy;
2153 Op->RegShiftedImm.SrcReg = SrcReg;
2154 Op->RegShiftedImm.ShiftImm = ShiftImm;
2160 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2162 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2163 Op->ShifterImm.isASR = isASR;
2164 Op->ShifterImm.Imm = Imm;
2170 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2171 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2172 Op->RotImm.Imm = Imm;
2178 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2180 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2181 Op->Bitfield.LSB = LSB;
2182 Op->Bitfield.Width = Width;
2189 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
2190 SMLoc StartLoc, SMLoc EndLoc) {
2191 KindTy Kind = k_RegisterList;
2193 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
2194 Kind = k_DPRRegisterList;
2195 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2196 contains(Regs.front().first))
2197 Kind = k_SPRRegisterList;
2199 ARMOperand *Op = new ARMOperand(Kind);
2200 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
2201 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2202 Op->Registers.push_back(I->first);
2203 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
2204 Op->StartLoc = StartLoc;
2205 Op->EndLoc = EndLoc;
2209 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2210 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2211 ARMOperand *Op = new ARMOperand(k_VectorList);
2212 Op->VectorList.RegNum = RegNum;
2213 Op->VectorList.Count = Count;
2214 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2220 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2221 bool isDoubleSpaced,
2223 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2224 Op->VectorList.RegNum = RegNum;
2225 Op->VectorList.Count = Count;
2226 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2232 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2234 bool isDoubleSpaced,
2236 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2237 Op->VectorList.RegNum = RegNum;
2238 Op->VectorList.Count = Count;
2239 Op->VectorList.LaneIndex = Index;
2240 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2246 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2248 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2249 Op->VectorIndex.Val = Idx;
2255 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2256 ARMOperand *Op = new ARMOperand(k_Immediate);
2263 static ARMOperand *CreateMem(unsigned BaseRegNum,
2264 const MCConstantExpr *OffsetImm,
2265 unsigned OffsetRegNum,
2266 ARM_AM::ShiftOpc ShiftType,
2271 ARMOperand *Op = new ARMOperand(k_Memory);
2272 Op->Memory.BaseRegNum = BaseRegNum;
2273 Op->Memory.OffsetImm = OffsetImm;
2274 Op->Memory.OffsetRegNum = OffsetRegNum;
2275 Op->Memory.ShiftType = ShiftType;
2276 Op->Memory.ShiftImm = ShiftImm;
2277 Op->Memory.Alignment = Alignment;
2278 Op->Memory.isNegative = isNegative;
2284 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2285 ARM_AM::ShiftOpc ShiftTy,
2288 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2289 Op->PostIdxReg.RegNum = RegNum;
2290 Op->PostIdxReg.isAdd = isAdd;
2291 Op->PostIdxReg.ShiftTy = ShiftTy;
2292 Op->PostIdxReg.ShiftImm = ShiftImm;
2298 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2299 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2300 Op->MBOpt.Val = Opt;
2306 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2307 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2308 Op->IFlags.Val = IFlags;
2314 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2315 ARMOperand *Op = new ARMOperand(k_MSRMask);
2316 Op->MMask.Val = MMask;
2323 } // end anonymous namespace.
2325 void ARMOperand::print(raw_ostream &OS) const {
2328 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2331 OS << "<ccout " << getReg() << ">";
2333 case k_ITCondMask: {
2334 static const char *const MaskStr[] = {
2335 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2336 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2338 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2339 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2343 OS << "<coprocessor number: " << getCoproc() << ">";
2346 OS << "<coprocessor register: " << getCoproc() << ">";
2348 case k_CoprocOption:
2349 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2352 OS << "<mask: " << getMSRMask() << ">";
2355 getImm()->print(OS);
2357 case k_MemBarrierOpt:
2358 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
2362 << " base:" << Memory.BaseRegNum;
2365 case k_PostIndexRegister:
2366 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2367 << PostIdxReg.RegNum;
2368 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2369 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2370 << PostIdxReg.ShiftImm;
2373 case k_ProcIFlags: {
2374 OS << "<ARM_PROC::";
2375 unsigned IFlags = getProcIFlags();
2376 for (int i=2; i >= 0; --i)
2377 if (IFlags & (1 << i))
2378 OS << ARM_PROC::IFlagsToString(1 << i);
2383 OS << "<register " << getReg() << ">";
2385 case k_ShifterImmediate:
2386 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2387 << " #" << ShifterImm.Imm << ">";
2389 case k_ShiftedRegister:
2390 OS << "<so_reg_reg "
2391 << RegShiftedReg.SrcReg << " "
2392 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2393 << " " << RegShiftedReg.ShiftReg << ">";
2395 case k_ShiftedImmediate:
2396 OS << "<so_reg_imm "
2397 << RegShiftedImm.SrcReg << " "
2398 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2399 << " #" << RegShiftedImm.ShiftImm << ">";
2401 case k_RotateImmediate:
2402 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2404 case k_BitfieldDescriptor:
2405 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2406 << ", width: " << Bitfield.Width << ">";
2408 case k_RegisterList:
2409 case k_DPRRegisterList:
2410 case k_SPRRegisterList: {
2411 OS << "<register_list ";
2413 const SmallVectorImpl<unsigned> &RegList = getRegList();
2414 for (SmallVectorImpl<unsigned>::const_iterator
2415 I = RegList.begin(), E = RegList.end(); I != E; ) {
2417 if (++I < E) OS << ", ";
2424 OS << "<vector_list " << VectorList.Count << " * "
2425 << VectorList.RegNum << ">";
2427 case k_VectorListAllLanes:
2428 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2429 << VectorList.RegNum << ">";
2431 case k_VectorListIndexed:
2432 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2433 << VectorList.Count << " * " << VectorList.RegNum << ">";
2436 OS << "'" << getToken() << "'";
2439 OS << "<vectorindex " << getVectorIndex() << ">";
2444 /// @name Auto-generated Match Functions
2447 static unsigned MatchRegisterName(StringRef Name);
2451 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2452 SMLoc &StartLoc, SMLoc &EndLoc) {
2453 StartLoc = Parser.getTok().getLoc();
2454 EndLoc = Parser.getTok().getEndLoc();
2455 RegNo = tryParseRegister();
2457 return (RegNo == (unsigned)-1);
2460 /// Try to parse a register name. The token must be an Identifier when called,
2461 /// and if it is a register name the token is eaten and the register number is
2462 /// returned. Otherwise return -1.
2464 int ARMAsmParser::tryParseRegister() {
2465 const AsmToken &Tok = Parser.getTok();
2466 if (Tok.isNot(AsmToken::Identifier)) return -1;
2468 std::string lowerCase = Tok.getString().lower();
2469 unsigned RegNum = MatchRegisterName(lowerCase);
2471 RegNum = StringSwitch<unsigned>(lowerCase)
2472 .Case("r13", ARM::SP)
2473 .Case("r14", ARM::LR)
2474 .Case("r15", ARM::PC)
2475 .Case("ip", ARM::R12)
2476 // Additional register name aliases for 'gas' compatibility.
2477 .Case("a1", ARM::R0)
2478 .Case("a2", ARM::R1)
2479 .Case("a3", ARM::R2)
2480 .Case("a4", ARM::R3)
2481 .Case("v1", ARM::R4)
2482 .Case("v2", ARM::R5)
2483 .Case("v3", ARM::R6)
2484 .Case("v4", ARM::R7)
2485 .Case("v5", ARM::R8)
2486 .Case("v6", ARM::R9)
2487 .Case("v7", ARM::R10)
2488 .Case("v8", ARM::R11)
2489 .Case("sb", ARM::R9)
2490 .Case("sl", ARM::R10)
2491 .Case("fp", ARM::R11)
2495 // Check for aliases registered via .req. Canonicalize to lower case.
2496 // That's more consistent since register names are case insensitive, and
2497 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2498 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2499 // If no match, return failure.
2500 if (Entry == RegisterReqs.end())
2502 Parser.Lex(); // Eat identifier token.
2503 return Entry->getValue();
2506 Parser.Lex(); // Eat identifier token.
2511 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2512 // If a recoverable error occurs, return 1. If an irrecoverable error
2513 // occurs, return -1. An irrecoverable error is one where tokens have been
2514 // consumed in the process of trying to parse the shifter (i.e., when it is
2515 // indeed a shifter operand, but malformed).
2516 int ARMAsmParser::tryParseShiftRegister(
2517 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2518 SMLoc S = Parser.getTok().getLoc();
2519 const AsmToken &Tok = Parser.getTok();
2520 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2522 std::string lowerCase = Tok.getString().lower();
2523 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2524 .Case("asl", ARM_AM::lsl)
2525 .Case("lsl", ARM_AM::lsl)
2526 .Case("lsr", ARM_AM::lsr)
2527 .Case("asr", ARM_AM::asr)
2528 .Case("ror", ARM_AM::ror)
2529 .Case("rrx", ARM_AM::rrx)
2530 .Default(ARM_AM::no_shift);
2532 if (ShiftTy == ARM_AM::no_shift)
2535 Parser.Lex(); // Eat the operator.
2537 // The source register for the shift has already been added to the
2538 // operand list, so we need to pop it off and combine it into the shifted
2539 // register operand instead.
2540 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2541 if (!PrevOp->isReg())
2542 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2543 int SrcReg = PrevOp->getReg();
2548 if (ShiftTy == ARM_AM::rrx) {
2549 // RRX Doesn't have an explicit shift amount. The encoder expects
2550 // the shift register to be the same as the source register. Seems odd,
2554 // Figure out if this is shifted by a constant or a register (for non-RRX).
2555 if (Parser.getTok().is(AsmToken::Hash) ||
2556 Parser.getTok().is(AsmToken::Dollar)) {
2557 Parser.Lex(); // Eat hash.
2558 SMLoc ImmLoc = Parser.getTok().getLoc();
2559 const MCExpr *ShiftExpr = 0;
2560 if (getParser().ParseExpression(ShiftExpr, EndLoc)) {
2561 Error(ImmLoc, "invalid immediate shift value");
2564 // The expression must be evaluatable as an immediate.
2565 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2567 Error(ImmLoc, "invalid immediate shift value");
2570 // Range check the immediate.
2571 // lsl, ror: 0 <= imm <= 31
2572 // lsr, asr: 0 <= imm <= 32
2573 Imm = CE->getValue();
2575 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2576 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2577 Error(ImmLoc, "immediate shift value out of range");
2580 // shift by zero is a nop. Always send it through as lsl.
2581 // ('as' compatibility)
2583 ShiftTy = ARM_AM::lsl;
2584 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2585 SMLoc L = Parser.getTok().getLoc();
2586 EndLoc = Parser.getTok().getEndLoc();
2587 ShiftReg = tryParseRegister();
2588 if (ShiftReg == -1) {
2589 Error (L, "expected immediate or register in shift operand");
2593 Error (Parser.getTok().getLoc(),
2594 "expected immediate or register in shift operand");
2599 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2600 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2604 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2611 /// Try to parse a register name. The token must be an Identifier when called.
2612 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2613 /// if there is a "writeback". 'true' if it's not a register.
2615 /// TODO this is likely to change to allow different register types and or to
2616 /// parse for a specific register type.
2618 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2619 const AsmToken &RegTok = Parser.getTok();
2620 int RegNo = tryParseRegister();
2624 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2625 RegTok.getEndLoc()));
2627 const AsmToken &ExclaimTok = Parser.getTok();
2628 if (ExclaimTok.is(AsmToken::Exclaim)) {
2629 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2630 ExclaimTok.getLoc()));
2631 Parser.Lex(); // Eat exclaim token
2635 // Also check for an index operand. This is only legal for vector registers,
2636 // but that'll get caught OK in operand matching, so we don't need to
2637 // explicitly filter everything else out here.
2638 if (Parser.getTok().is(AsmToken::LBrac)) {
2639 SMLoc SIdx = Parser.getTok().getLoc();
2640 Parser.Lex(); // Eat left bracket token.
2642 const MCExpr *ImmVal;
2643 if (getParser().ParseExpression(ImmVal))
2645 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2647 return TokError("immediate value expected for vector index");
2649 if (Parser.getTok().isNot(AsmToken::RBrac))
2650 return Error(Parser.getTok().getLoc(), "']' expected");
2652 SMLoc E = Parser.getTok().getEndLoc();
2653 Parser.Lex(); // Eat right bracket token.
2655 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2663 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2664 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2666 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2667 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2669 switch (Name.size()) {
2672 if (Name[0] != CoprocOp)
2688 if (Name[0] != CoprocOp || Name[1] != '1')
2692 case '0': return 10;
2693 case '1': return 11;
2694 case '2': return 12;
2695 case '3': return 13;
2696 case '4': return 14;
2697 case '5': return 15;
2702 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2703 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2704 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2705 SMLoc S = Parser.getTok().getLoc();
2706 const AsmToken &Tok = Parser.getTok();
2707 if (!Tok.is(AsmToken::Identifier))
2708 return MatchOperand_NoMatch;
2709 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2710 .Case("eq", ARMCC::EQ)
2711 .Case("ne", ARMCC::NE)
2712 .Case("hs", ARMCC::HS)
2713 .Case("cs", ARMCC::HS)
2714 .Case("lo", ARMCC::LO)
2715 .Case("cc", ARMCC::LO)
2716 .Case("mi", ARMCC::MI)
2717 .Case("pl", ARMCC::PL)
2718 .Case("vs", ARMCC::VS)
2719 .Case("vc", ARMCC::VC)
2720 .Case("hi", ARMCC::HI)
2721 .Case("ls", ARMCC::LS)
2722 .Case("ge", ARMCC::GE)
2723 .Case("lt", ARMCC::LT)
2724 .Case("gt", ARMCC::GT)
2725 .Case("le", ARMCC::LE)
2726 .Case("al", ARMCC::AL)
2729 return MatchOperand_NoMatch;
2730 Parser.Lex(); // Eat the token.
2732 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2734 return MatchOperand_Success;
2737 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
2738 /// token must be an Identifier when called, and if it is a coprocessor
2739 /// number, the token is eaten and the operand is added to the operand list.
2740 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2741 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2742 SMLoc S = Parser.getTok().getLoc();
2743 const AsmToken &Tok = Parser.getTok();
2744 if (Tok.isNot(AsmToken::Identifier))
2745 return MatchOperand_NoMatch;
2747 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
2749 return MatchOperand_NoMatch;
2751 Parser.Lex(); // Eat identifier token.
2752 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
2753 return MatchOperand_Success;
2756 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
2757 /// token must be an Identifier when called, and if it is a coprocessor
2758 /// number, the token is eaten and the operand is added to the operand list.
2759 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2760 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2761 SMLoc S = Parser.getTok().getLoc();
2762 const AsmToken &Tok = Parser.getTok();
2763 if (Tok.isNot(AsmToken::Identifier))
2764 return MatchOperand_NoMatch;
2766 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
2768 return MatchOperand_NoMatch;
2770 Parser.Lex(); // Eat identifier token.
2771 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
2772 return MatchOperand_Success;
2775 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
2776 /// coproc_option : '{' imm0_255 '}'
2777 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2778 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2779 SMLoc S = Parser.getTok().getLoc();
2781 // If this isn't a '{', this isn't a coprocessor immediate operand.
2782 if (Parser.getTok().isNot(AsmToken::LCurly))
2783 return MatchOperand_NoMatch;
2784 Parser.Lex(); // Eat the '{'
2787 SMLoc Loc = Parser.getTok().getLoc();
2788 if (getParser().ParseExpression(Expr)) {
2789 Error(Loc, "illegal expression");
2790 return MatchOperand_ParseFail;
2792 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2793 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
2794 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
2795 return MatchOperand_ParseFail;
2797 int Val = CE->getValue();
2799 // Check for and consume the closing '}'
2800 if (Parser.getTok().isNot(AsmToken::RCurly))
2801 return MatchOperand_ParseFail;
2802 SMLoc E = Parser.getTok().getEndLoc();
2803 Parser.Lex(); // Eat the '}'
2805 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
2806 return MatchOperand_Success;
2809 // For register list parsing, we need to map from raw GPR register numbering
2810 // to the enumeration values. The enumeration values aren't sorted by
2811 // register number due to our using "sp", "lr" and "pc" as canonical names.
2812 static unsigned getNextRegister(unsigned Reg) {
2813 // If this is a GPR, we need to do it manually, otherwise we can rely
2814 // on the sort ordering of the enumeration since the other reg-classes
2816 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2819 default: llvm_unreachable("Invalid GPR number!");
2820 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
2821 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
2822 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
2823 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
2824 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
2825 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
2826 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
2827 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
2831 // Return the low-subreg of a given Q register.
2832 static unsigned getDRegFromQReg(unsigned QReg) {
2834 default: llvm_unreachable("expected a Q register!");
2835 case ARM::Q0: return ARM::D0;
2836 case ARM::Q1: return ARM::D2;
2837 case ARM::Q2: return ARM::D4;
2838 case ARM::Q3: return ARM::D6;
2839 case ARM::Q4: return ARM::D8;
2840 case ARM::Q5: return ARM::D10;
2841 case ARM::Q6: return ARM::D12;
2842 case ARM::Q7: return ARM::D14;
2843 case ARM::Q8: return ARM::D16;
2844 case ARM::Q9: return ARM::D18;
2845 case ARM::Q10: return ARM::D20;
2846 case ARM::Q11: return ARM::D22;
2847 case ARM::Q12: return ARM::D24;
2848 case ARM::Q13: return ARM::D26;
2849 case ARM::Q14: return ARM::D28;
2850 case ARM::Q15: return ARM::D30;
2854 /// Parse a register list.
2856 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2857 assert(Parser.getTok().is(AsmToken::LCurly) &&
2858 "Token is not a Left Curly Brace");
2859 SMLoc S = Parser.getTok().getLoc();
2860 Parser.Lex(); // Eat '{' token.
2861 SMLoc RegLoc = Parser.getTok().getLoc();
2863 // Check the first register in the list to see what register class
2864 // this is a list of.
2865 int Reg = tryParseRegister();
2867 return Error(RegLoc, "register expected");
2869 // The reglist instructions have at most 16 registers, so reserve
2870 // space for that many.
2871 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
2873 // Allow Q regs and just interpret them as the two D sub-registers.
2874 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2875 Reg = getDRegFromQReg(Reg);
2876 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2879 const MCRegisterClass *RC;
2880 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2881 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
2882 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
2883 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
2884 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
2885 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
2887 return Error(RegLoc, "invalid register in register list");
2889 // Store the register.
2890 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2892 // This starts immediately after the first register token in the list,
2893 // so we can see either a comma or a minus (range separator) as a legal
2895 while (Parser.getTok().is(AsmToken::Comma) ||
2896 Parser.getTok().is(AsmToken::Minus)) {
2897 if (Parser.getTok().is(AsmToken::Minus)) {
2898 Parser.Lex(); // Eat the minus.
2899 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
2900 int EndReg = tryParseRegister();
2902 return Error(AfterMinusLoc, "register expected");
2903 // Allow Q regs and just interpret them as the two D sub-registers.
2904 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
2905 EndReg = getDRegFromQReg(EndReg) + 1;
2906 // If the register is the same as the start reg, there's nothing
2910 // The register must be in the same register class as the first.
2911 if (!RC->contains(EndReg))
2912 return Error(AfterMinusLoc, "invalid register in register list");
2913 // Ranges must go from low to high.
2914 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
2915 return Error(AfterMinusLoc, "bad range in register list");
2917 // Add all the registers in the range to the register list.
2918 while (Reg != EndReg) {
2919 Reg = getNextRegister(Reg);
2920 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2924 Parser.Lex(); // Eat the comma.
2925 RegLoc = Parser.getTok().getLoc();
2927 const AsmToken RegTok = Parser.getTok();
2928 Reg = tryParseRegister();
2930 return Error(RegLoc, "register expected");
2931 // Allow Q regs and just interpret them as the two D sub-registers.
2932 bool isQReg = false;
2933 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
2934 Reg = getDRegFromQReg(Reg);
2937 // The register must be in the same register class as the first.
2938 if (!RC->contains(Reg))
2939 return Error(RegLoc, "invalid register in register list");
2940 // List must be monotonically increasing.
2941 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
2942 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
2943 Warning(RegLoc, "register list not in ascending order");
2945 return Error(RegLoc, "register list not in ascending order");
2947 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
2948 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
2949 ") in register list");
2952 // VFP register lists must also be contiguous.
2953 // It's OK to use the enumeration values directly here rather, as the
2954 // VFP register classes have the enum sorted properly.
2955 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
2957 return Error(RegLoc, "non-contiguous register range");
2958 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
2960 Registers.push_back(std::pair<unsigned, SMLoc>(++Reg, RegLoc));
2963 if (Parser.getTok().isNot(AsmToken::RCurly))
2964 return Error(Parser.getTok().getLoc(), "'}' expected");
2965 SMLoc E = Parser.getTok().getEndLoc();
2966 Parser.Lex(); // Eat '}' token.
2968 // Push the register list operand.
2969 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
2971 // The ARM system instruction variants for LDM/STM have a '^' token here.
2972 if (Parser.getTok().is(AsmToken::Caret)) {
2973 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
2974 Parser.Lex(); // Eat '^' token.
2980 // Helper function to parse the lane index for vector lists.
2981 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2982 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
2983 Index = 0; // Always return a defined index value.
2984 if (Parser.getTok().is(AsmToken::LBrac)) {
2985 Parser.Lex(); // Eat the '['.
2986 if (Parser.getTok().is(AsmToken::RBrac)) {
2987 // "Dn[]" is the 'all lanes' syntax.
2988 LaneKind = AllLanes;
2989 EndLoc = Parser.getTok().getEndLoc();
2990 Parser.Lex(); // Eat the ']'.
2991 return MatchOperand_Success;
2994 // There's an optional '#' token here. Normally there wouldn't be, but
2995 // inline assemble puts one in, and it's friendly to accept that.
2996 if (Parser.getTok().is(AsmToken::Hash))
2997 Parser.Lex(); // Eat the '#'
2999 const MCExpr *LaneIndex;
3000 SMLoc Loc = Parser.getTok().getLoc();
3001 if (getParser().ParseExpression(LaneIndex)) {
3002 Error(Loc, "illegal expression");
3003 return MatchOperand_ParseFail;
3005 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3007 Error(Loc, "lane index must be empty or an integer");
3008 return MatchOperand_ParseFail;
3010 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3011 Error(Parser.getTok().getLoc(), "']' expected");
3012 return MatchOperand_ParseFail;
3014 EndLoc = Parser.getTok().getEndLoc();
3015 Parser.Lex(); // Eat the ']'.
3016 int64_t Val = CE->getValue();
3018 // FIXME: Make this range check context sensitive for .8, .16, .32.
3019 if (Val < 0 || Val > 7) {
3020 Error(Parser.getTok().getLoc(), "lane index out of range");
3021 return MatchOperand_ParseFail;
3024 LaneKind = IndexedLane;
3025 return MatchOperand_Success;
3028 return MatchOperand_Success;
3031 // parse a vector register list
3032 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3033 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3034 VectorLaneTy LaneKind;
3036 SMLoc S = Parser.getTok().getLoc();
3037 // As an extension (to match gas), support a plain D register or Q register
3038 // (without encosing curly braces) as a single or double entry list,
3040 if (Parser.getTok().is(AsmToken::Identifier)) {
3041 SMLoc E = Parser.getTok().getEndLoc();
3042 int Reg = tryParseRegister();
3044 return MatchOperand_NoMatch;
3045 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3046 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3047 if (Res != MatchOperand_Success)
3051 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3054 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3058 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3063 return MatchOperand_Success;
3065 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3066 Reg = getDRegFromQReg(Reg);
3067 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3068 if (Res != MatchOperand_Success)
3072 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3073 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3074 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3077 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3078 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3079 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3083 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3088 return MatchOperand_Success;
3090 Error(S, "vector register expected");
3091 return MatchOperand_ParseFail;
3094 if (Parser.getTok().isNot(AsmToken::LCurly))
3095 return MatchOperand_NoMatch;
3097 Parser.Lex(); // Eat '{' token.
3098 SMLoc RegLoc = Parser.getTok().getLoc();
3100 int Reg = tryParseRegister();
3102 Error(RegLoc, "register expected");
3103 return MatchOperand_ParseFail;
3107 unsigned FirstReg = Reg;
3108 // The list is of D registers, but we also allow Q regs and just interpret
3109 // them as the two D sub-registers.
3110 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3111 FirstReg = Reg = getDRegFromQReg(Reg);
3112 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3113 // it's ambiguous with four-register single spaced.
3119 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3120 return MatchOperand_ParseFail;
3122 while (Parser.getTok().is(AsmToken::Comma) ||
3123 Parser.getTok().is(AsmToken::Minus)) {
3124 if (Parser.getTok().is(AsmToken::Minus)) {
3126 Spacing = 1; // Register range implies a single spaced list.
3127 else if (Spacing == 2) {
3128 Error(Parser.getTok().getLoc(),
3129 "sequential registers in double spaced list");
3130 return MatchOperand_ParseFail;
3132 Parser.Lex(); // Eat the minus.
3133 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3134 int EndReg = tryParseRegister();
3136 Error(AfterMinusLoc, "register expected");
3137 return MatchOperand_ParseFail;
3139 // Allow Q regs and just interpret them as the two D sub-registers.
3140 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3141 EndReg = getDRegFromQReg(EndReg) + 1;
3142 // If the register is the same as the start reg, there's nothing
3146 // The register must be in the same register class as the first.
3147 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3148 Error(AfterMinusLoc, "invalid register in register list");
3149 return MatchOperand_ParseFail;
3151 // Ranges must go from low to high.
3153 Error(AfterMinusLoc, "bad range in register list");
3154 return MatchOperand_ParseFail;
3156 // Parse the lane specifier if present.
3157 VectorLaneTy NextLaneKind;
3158 unsigned NextLaneIndex;
3159 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3160 MatchOperand_Success)
3161 return MatchOperand_ParseFail;
3162 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3163 Error(AfterMinusLoc, "mismatched lane index in register list");
3164 return MatchOperand_ParseFail;
3167 // Add all the registers in the range to the register list.
3168 Count += EndReg - Reg;
3172 Parser.Lex(); // Eat the comma.
3173 RegLoc = Parser.getTok().getLoc();
3175 Reg = tryParseRegister();
3177 Error(RegLoc, "register expected");
3178 return MatchOperand_ParseFail;
3180 // vector register lists must be contiguous.
3181 // It's OK to use the enumeration values directly here rather, as the
3182 // VFP register classes have the enum sorted properly.
3184 // The list is of D registers, but we also allow Q regs and just interpret
3185 // them as the two D sub-registers.
3186 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3188 Spacing = 1; // Register range implies a single spaced list.
3189 else if (Spacing == 2) {
3191 "invalid register in double-spaced list (must be 'D' register')");
3192 return MatchOperand_ParseFail;
3194 Reg = getDRegFromQReg(Reg);
3195 if (Reg != OldReg + 1) {
3196 Error(RegLoc, "non-contiguous register range");
3197 return MatchOperand_ParseFail;
3201 // Parse the lane specifier if present.
3202 VectorLaneTy NextLaneKind;
3203 unsigned NextLaneIndex;
3204 SMLoc LaneLoc = Parser.getTok().getLoc();
3205 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3206 MatchOperand_Success)
3207 return MatchOperand_ParseFail;
3208 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3209 Error(LaneLoc, "mismatched lane index in register list");
3210 return MatchOperand_ParseFail;
3214 // Normal D register.
3215 // Figure out the register spacing (single or double) of the list if
3216 // we don't know it already.
3218 Spacing = 1 + (Reg == OldReg + 2);
3220 // Just check that it's contiguous and keep going.
3221 if (Reg != OldReg + Spacing) {
3222 Error(RegLoc, "non-contiguous register range");
3223 return MatchOperand_ParseFail;
3226 // Parse the lane specifier if present.
3227 VectorLaneTy NextLaneKind;
3228 unsigned NextLaneIndex;
3229 SMLoc EndLoc = Parser.getTok().getLoc();
3230 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3231 return MatchOperand_ParseFail;
3232 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3233 Error(EndLoc, "mismatched lane index in register list");
3234 return MatchOperand_ParseFail;
3238 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3239 Error(Parser.getTok().getLoc(), "'}' expected");
3240 return MatchOperand_ParseFail;
3242 E = Parser.getTok().getEndLoc();
3243 Parser.Lex(); // Eat '}' token.
3247 // Two-register operands have been converted to the
3248 // composite register classes.
3250 const MCRegisterClass *RC = (Spacing == 1) ?
3251 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3252 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3253 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3256 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3257 (Spacing == 2), S, E));
3260 // Two-register operands have been converted to the
3261 // composite register classes.
3263 const MCRegisterClass *RC = (Spacing == 1) ?
3264 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3265 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3266 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3268 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3273 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3279 return MatchOperand_Success;
3282 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3283 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3284 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3285 SMLoc S = Parser.getTok().getLoc();
3286 const AsmToken &Tok = Parser.getTok();
3289 if (Tok.is(AsmToken::Identifier)) {
3290 StringRef OptStr = Tok.getString();
3292 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3293 .Case("sy", ARM_MB::SY)
3294 .Case("st", ARM_MB::ST)
3295 .Case("sh", ARM_MB::ISH)
3296 .Case("ish", ARM_MB::ISH)
3297 .Case("shst", ARM_MB::ISHST)
3298 .Case("ishst", ARM_MB::ISHST)
3299 .Case("nsh", ARM_MB::NSH)
3300 .Case("un", ARM_MB::NSH)
3301 .Case("nshst", ARM_MB::NSHST)
3302 .Case("unst", ARM_MB::NSHST)
3303 .Case("osh", ARM_MB::OSH)
3304 .Case("oshst", ARM_MB::OSHST)
3308 return MatchOperand_NoMatch;
3310 Parser.Lex(); // Eat identifier token.
3311 } else if (Tok.is(AsmToken::Hash) ||
3312 Tok.is(AsmToken::Dollar) ||
3313 Tok.is(AsmToken::Integer)) {
3314 if (Parser.getTok().isNot(AsmToken::Integer))
3315 Parser.Lex(); // Eat the '#'.
3316 SMLoc Loc = Parser.getTok().getLoc();
3318 const MCExpr *MemBarrierID;
3319 if (getParser().ParseExpression(MemBarrierID)) {
3320 Error(Loc, "illegal expression");
3321 return MatchOperand_ParseFail;
3324 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3326 Error(Loc, "constant expression expected");
3327 return MatchOperand_ParseFail;
3330 int Val = CE->getValue();
3332 Error(Loc, "immediate value out of range");
3333 return MatchOperand_ParseFail;
3336 Opt = ARM_MB::RESERVED_0 + Val;
3338 return MatchOperand_ParseFail;
3340 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3341 return MatchOperand_Success;
3344 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3345 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3346 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3347 SMLoc S = Parser.getTok().getLoc();
3348 const AsmToken &Tok = Parser.getTok();
3349 if (!Tok.is(AsmToken::Identifier))
3350 return MatchOperand_NoMatch;
3351 StringRef IFlagsStr = Tok.getString();
3353 // An iflags string of "none" is interpreted to mean that none of the AIF
3354 // bits are set. Not a terribly useful instruction, but a valid encoding.
3355 unsigned IFlags = 0;
3356 if (IFlagsStr != "none") {
3357 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3358 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3359 .Case("a", ARM_PROC::A)
3360 .Case("i", ARM_PROC::I)
3361 .Case("f", ARM_PROC::F)
3364 // If some specific iflag is already set, it means that some letter is
3365 // present more than once, this is not acceptable.
3366 if (Flag == ~0U || (IFlags & Flag))
3367 return MatchOperand_NoMatch;
3373 Parser.Lex(); // Eat identifier token.
3374 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3375 return MatchOperand_Success;
3378 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3379 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3380 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3381 SMLoc S = Parser.getTok().getLoc();
3382 const AsmToken &Tok = Parser.getTok();
3383 if (!Tok.is(AsmToken::Identifier))
3384 return MatchOperand_NoMatch;
3385 StringRef Mask = Tok.getString();
3388 // See ARMv6-M 10.1.1
3389 std::string Name = Mask.lower();
3390 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3391 // Note: in the documentation:
3392 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3393 // for MSR APSR_nzcvq.
3394 // but we do make it an alias here. This is so to get the "mask encoding"
3395 // bits correct on MSR APSR writes.
3397 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3398 // should really only be allowed when writing a special register. Note
3399 // they get dropped in the MRS instruction reading a special register as
3400 // the SYSm field is only 8 bits.
3402 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3403 // includes the DSP extension but that is not checked.
3404 .Case("apsr", 0x800)
3405 .Case("apsr_nzcvq", 0x800)
3406 .Case("apsr_g", 0x400)
3407 .Case("apsr_nzcvqg", 0xc00)
3408 .Case("iapsr", 0x801)
3409 .Case("iapsr_nzcvq", 0x801)
3410 .Case("iapsr_g", 0x401)
3411 .Case("iapsr_nzcvqg", 0xc01)
3412 .Case("eapsr", 0x802)
3413 .Case("eapsr_nzcvq", 0x802)
3414 .Case("eapsr_g", 0x402)
3415 .Case("eapsr_nzcvqg", 0xc02)
3416 .Case("xpsr", 0x803)
3417 .Case("xpsr_nzcvq", 0x803)
3418 .Case("xpsr_g", 0x403)
3419 .Case("xpsr_nzcvqg", 0xc03)
3420 .Case("ipsr", 0x805)
3421 .Case("epsr", 0x806)
3422 .Case("iepsr", 0x807)
3425 .Case("primask", 0x810)
3426 .Case("basepri", 0x811)
3427 .Case("basepri_max", 0x812)
3428 .Case("faultmask", 0x813)
3429 .Case("control", 0x814)
3432 if (FlagsVal == ~0U)
3433 return MatchOperand_NoMatch;
3435 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3436 // basepri, basepri_max and faultmask only valid for V7m.
3437 return MatchOperand_NoMatch;
3439 Parser.Lex(); // Eat identifier token.
3440 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3441 return MatchOperand_Success;
3444 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3445 size_t Start = 0, Next = Mask.find('_');
3446 StringRef Flags = "";
3447 std::string SpecReg = Mask.slice(Start, Next).lower();
3448 if (Next != StringRef::npos)
3449 Flags = Mask.slice(Next+1, Mask.size());
3451 // FlagsVal contains the complete mask:
3453 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3454 unsigned FlagsVal = 0;
3456 if (SpecReg == "apsr") {
3457 FlagsVal = StringSwitch<unsigned>(Flags)
3458 .Case("nzcvq", 0x8) // same as CPSR_f
3459 .Case("g", 0x4) // same as CPSR_s
3460 .Case("nzcvqg", 0xc) // same as CPSR_fs
3463 if (FlagsVal == ~0U) {
3465 return MatchOperand_NoMatch;
3467 FlagsVal = 8; // No flag
3469 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3470 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3471 if (Flags == "all" || Flags == "")
3473 for (int i = 0, e = Flags.size(); i != e; ++i) {
3474 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3481 // If some specific flag is already set, it means that some letter is
3482 // present more than once, this is not acceptable.
3483 if (FlagsVal == ~0U || (FlagsVal & Flag))
3484 return MatchOperand_NoMatch;
3487 } else // No match for special register.
3488 return MatchOperand_NoMatch;
3490 // Special register without flags is NOT equivalent to "fc" flags.
3491 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3492 // two lines would enable gas compatibility at the expense of breaking
3498 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3499 if (SpecReg == "spsr")
3502 Parser.Lex(); // Eat identifier token.
3503 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3504 return MatchOperand_Success;
3507 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3508 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3509 int Low, int High) {
3510 const AsmToken &Tok = Parser.getTok();
3511 if (Tok.isNot(AsmToken::Identifier)) {
3512 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3513 return MatchOperand_ParseFail;
3515 StringRef ShiftName = Tok.getString();
3516 std::string LowerOp = Op.lower();
3517 std::string UpperOp = Op.upper();
3518 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3519 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3520 return MatchOperand_ParseFail;
3522 Parser.Lex(); // Eat shift type token.
3524 // There must be a '#' and a shift amount.
3525 if (Parser.getTok().isNot(AsmToken::Hash) &&
3526 Parser.getTok().isNot(AsmToken::Dollar)) {
3527 Error(Parser.getTok().getLoc(), "'#' expected");
3528 return MatchOperand_ParseFail;
3530 Parser.Lex(); // Eat hash token.
3532 const MCExpr *ShiftAmount;
3533 SMLoc Loc = Parser.getTok().getLoc();
3535 if (getParser().ParseExpression(ShiftAmount, EndLoc)) {
3536 Error(Loc, "illegal expression");
3537 return MatchOperand_ParseFail;
3539 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3541 Error(Loc, "constant expression expected");
3542 return MatchOperand_ParseFail;
3544 int Val = CE->getValue();
3545 if (Val < Low || Val > High) {
3546 Error(Loc, "immediate value out of range");
3547 return MatchOperand_ParseFail;
3550 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3552 return MatchOperand_Success;
3555 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3556 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3557 const AsmToken &Tok = Parser.getTok();
3558 SMLoc S = Tok.getLoc();
3559 if (Tok.isNot(AsmToken::Identifier)) {
3560 Error(S, "'be' or 'le' operand expected");
3561 return MatchOperand_ParseFail;
3563 int Val = StringSwitch<int>(Tok.getString())
3567 Parser.Lex(); // Eat the token.
3570 Error(S, "'be' or 'le' operand expected");
3571 return MatchOperand_ParseFail;
3573 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3575 S, Tok.getEndLoc()));
3576 return MatchOperand_Success;
3579 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3580 /// instructions. Legal values are:
3581 /// lsl #n 'n' in [0,31]
3582 /// asr #n 'n' in [1,32]
3583 /// n == 32 encoded as n == 0.
3584 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3585 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3586 const AsmToken &Tok = Parser.getTok();
3587 SMLoc S = Tok.getLoc();
3588 if (Tok.isNot(AsmToken::Identifier)) {
3589 Error(S, "shift operator 'asr' or 'lsl' expected");
3590 return MatchOperand_ParseFail;
3592 StringRef ShiftName = Tok.getString();
3594 if (ShiftName == "lsl" || ShiftName == "LSL")
3596 else if (ShiftName == "asr" || ShiftName == "ASR")
3599 Error(S, "shift operator 'asr' or 'lsl' expected");
3600 return MatchOperand_ParseFail;
3602 Parser.Lex(); // Eat the operator.
3604 // A '#' and a shift amount.
3605 if (Parser.getTok().isNot(AsmToken::Hash) &&
3606 Parser.getTok().isNot(AsmToken::Dollar)) {
3607 Error(Parser.getTok().getLoc(), "'#' expected");
3608 return MatchOperand_ParseFail;
3610 Parser.Lex(); // Eat hash token.
3611 SMLoc ExLoc = Parser.getTok().getLoc();
3613 const MCExpr *ShiftAmount;
3615 if (getParser().ParseExpression(ShiftAmount, EndLoc)) {
3616 Error(ExLoc, "malformed shift expression");
3617 return MatchOperand_ParseFail;
3619 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3621 Error(ExLoc, "shift amount must be an immediate");
3622 return MatchOperand_ParseFail;
3625 int64_t Val = CE->getValue();
3627 // Shift amount must be in [1,32]
3628 if (Val < 1 || Val > 32) {
3629 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3630 return MatchOperand_ParseFail;
3632 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3633 if (isThumb() && Val == 32) {
3634 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3635 return MatchOperand_ParseFail;
3637 if (Val == 32) Val = 0;
3639 // Shift amount must be in [1,32]
3640 if (Val < 0 || Val > 31) {
3641 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3642 return MatchOperand_ParseFail;
3646 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3648 return MatchOperand_Success;
3651 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3652 /// of instructions. Legal values are:
3653 /// ror #n 'n' in {0, 8, 16, 24}
3654 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3655 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3656 const AsmToken &Tok = Parser.getTok();
3657 SMLoc S = Tok.getLoc();
3658 if (Tok.isNot(AsmToken::Identifier))
3659 return MatchOperand_NoMatch;
3660 StringRef ShiftName = Tok.getString();
3661 if (ShiftName != "ror" && ShiftName != "ROR")
3662 return MatchOperand_NoMatch;
3663 Parser.Lex(); // Eat the operator.
3665 // A '#' and a rotate amount.
3666 if (Parser.getTok().isNot(AsmToken::Hash) &&
3667 Parser.getTok().isNot(AsmToken::Dollar)) {
3668 Error(Parser.getTok().getLoc(), "'#' expected");
3669 return MatchOperand_ParseFail;
3671 Parser.Lex(); // Eat hash token.
3672 SMLoc ExLoc = Parser.getTok().getLoc();
3674 const MCExpr *ShiftAmount;
3676 if (getParser().ParseExpression(ShiftAmount, EndLoc)) {
3677 Error(ExLoc, "malformed rotate expression");
3678 return MatchOperand_ParseFail;
3680 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3682 Error(ExLoc, "rotate amount must be an immediate");
3683 return MatchOperand_ParseFail;
3686 int64_t Val = CE->getValue();
3687 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
3688 // normally, zero is represented in asm by omitting the rotate operand
3690 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
3691 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
3692 return MatchOperand_ParseFail;
3695 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
3697 return MatchOperand_Success;
3700 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3701 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3702 SMLoc S = Parser.getTok().getLoc();
3703 // The bitfield descriptor is really two operands, the LSB and the width.
3704 if (Parser.getTok().isNot(AsmToken::Hash) &&
3705 Parser.getTok().isNot(AsmToken::Dollar)) {
3706 Error(Parser.getTok().getLoc(), "'#' expected");
3707 return MatchOperand_ParseFail;
3709 Parser.Lex(); // Eat hash token.
3711 const MCExpr *LSBExpr;
3712 SMLoc E = Parser.getTok().getLoc();
3713 if (getParser().ParseExpression(LSBExpr)) {
3714 Error(E, "malformed immediate expression");
3715 return MatchOperand_ParseFail;
3717 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
3719 Error(E, "'lsb' operand must be an immediate");
3720 return MatchOperand_ParseFail;
3723 int64_t LSB = CE->getValue();
3724 // The LSB must be in the range [0,31]
3725 if (LSB < 0 || LSB > 31) {
3726 Error(E, "'lsb' operand must be in the range [0,31]");
3727 return MatchOperand_ParseFail;
3729 E = Parser.getTok().getLoc();
3731 // Expect another immediate operand.
3732 if (Parser.getTok().isNot(AsmToken::Comma)) {
3733 Error(Parser.getTok().getLoc(), "too few operands");
3734 return MatchOperand_ParseFail;
3736 Parser.Lex(); // Eat hash token.
3737 if (Parser.getTok().isNot(AsmToken::Hash) &&
3738 Parser.getTok().isNot(AsmToken::Dollar)) {
3739 Error(Parser.getTok().getLoc(), "'#' expected");
3740 return MatchOperand_ParseFail;
3742 Parser.Lex(); // Eat hash token.
3744 const MCExpr *WidthExpr;
3746 if (getParser().ParseExpression(WidthExpr, EndLoc)) {
3747 Error(E, "malformed immediate expression");
3748 return MatchOperand_ParseFail;
3750 CE = dyn_cast<MCConstantExpr>(WidthExpr);
3752 Error(E, "'width' operand must be an immediate");
3753 return MatchOperand_ParseFail;
3756 int64_t Width = CE->getValue();
3757 // The LSB must be in the range [1,32-lsb]
3758 if (Width < 1 || Width > 32 - LSB) {
3759 Error(E, "'width' operand must be in the range [1,32-lsb]");
3760 return MatchOperand_ParseFail;
3763 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
3765 return MatchOperand_Success;
3768 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3769 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3770 // Check for a post-index addressing register operand. Specifically:
3771 // postidx_reg := '+' register {, shift}
3772 // | '-' register {, shift}
3773 // | register {, shift}
3775 // This method must return MatchOperand_NoMatch without consuming any tokens
3776 // in the case where there is no match, as other alternatives take other
3778 AsmToken Tok = Parser.getTok();
3779 SMLoc S = Tok.getLoc();
3780 bool haveEaten = false;
3782 if (Tok.is(AsmToken::Plus)) {
3783 Parser.Lex(); // Eat the '+' token.
3785 } else if (Tok.is(AsmToken::Minus)) {
3786 Parser.Lex(); // Eat the '-' token.
3791 SMLoc E = Parser.getTok().getEndLoc();
3792 int Reg = tryParseRegister();
3795 return MatchOperand_NoMatch;
3796 Error(Parser.getTok().getLoc(), "register expected");
3797 return MatchOperand_ParseFail;
3800 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
3801 unsigned ShiftImm = 0;
3802 if (Parser.getTok().is(AsmToken::Comma)) {
3803 Parser.Lex(); // Eat the ','.
3804 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
3805 return MatchOperand_ParseFail;
3807 // FIXME: Only approximates end...may include intervening whitespace.
3808 E = Parser.getTok().getLoc();
3811 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
3814 return MatchOperand_Success;
3817 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3818 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3819 // Check for a post-index addressing register operand. Specifically:
3820 // am3offset := '+' register
3827 // This method must return MatchOperand_NoMatch without consuming any tokens
3828 // in the case where there is no match, as other alternatives take other
3830 AsmToken Tok = Parser.getTok();
3831 SMLoc S = Tok.getLoc();
3833 // Do immediates first, as we always parse those if we have a '#'.
3834 if (Parser.getTok().is(AsmToken::Hash) ||
3835 Parser.getTok().is(AsmToken::Dollar)) {
3836 Parser.Lex(); // Eat the '#'.
3837 // Explicitly look for a '-', as we need to encode negative zero
3839 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3840 const MCExpr *Offset;
3842 if (getParser().ParseExpression(Offset, E))
3843 return MatchOperand_ParseFail;
3844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
3846 Error(S, "constant expression expected");
3847 return MatchOperand_ParseFail;
3849 // Negative zero is encoded as the flag value INT32_MIN.
3850 int32_t Val = CE->getValue();
3851 if (isNegative && Val == 0)
3855 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
3857 return MatchOperand_Success;
3861 bool haveEaten = false;
3863 if (Tok.is(AsmToken::Plus)) {
3864 Parser.Lex(); // Eat the '+' token.
3866 } else if (Tok.is(AsmToken::Minus)) {
3867 Parser.Lex(); // Eat the '-' token.
3872 Tok = Parser.getTok();
3873 int Reg = tryParseRegister();
3876 return MatchOperand_NoMatch;
3877 Error(Tok.getLoc(), "register expected");
3878 return MatchOperand_ParseFail;
3881 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
3882 0, S, Tok.getEndLoc()));
3884 return MatchOperand_Success;
3887 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
3888 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3889 /// when they refer multiple MIOperands inside a single one.
3891 cvtT2LdrdPre(MCInst &Inst,
3892 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3894 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3895 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3896 // Create a writeback register dummy placeholder.
3897 Inst.addOperand(MCOperand::CreateReg(0));
3899 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3901 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3904 /// cvtT2StrdPre - Convert parsed operands to MCInst.
3905 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3906 /// when they refer multiple MIOperands inside a single one.
3908 cvtT2StrdPre(MCInst &Inst,
3909 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3910 // Create a writeback register dummy placeholder.
3911 Inst.addOperand(MCOperand::CreateReg(0));
3913 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3914 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
3916 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
3918 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3921 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3922 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3923 /// when they refer multiple MIOperands inside a single one.
3925 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst,
3926 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3927 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3929 // Create a writeback register dummy placeholder.
3930 Inst.addOperand(MCOperand::CreateImm(0));
3932 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3933 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3936 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
3937 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3938 /// when they refer multiple MIOperands inside a single one.
3940 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst,
3941 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3942 // Create a writeback register dummy placeholder.
3943 Inst.addOperand(MCOperand::CreateImm(0));
3944 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3945 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
3946 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3949 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3950 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3951 /// when they refer multiple MIOperands inside a single one.
3953 cvtLdWriteBackRegAddrMode2(MCInst &Inst,
3954 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3955 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3957 // Create a writeback register dummy placeholder.
3958 Inst.addOperand(MCOperand::CreateImm(0));
3960 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
3961 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3964 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3965 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3966 /// when they refer multiple MIOperands inside a single one.
3968 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst,
3969 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3970 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3972 // Create a writeback register dummy placeholder.
3973 Inst.addOperand(MCOperand::CreateImm(0));
3975 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3976 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3980 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
3981 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3982 /// when they refer multiple MIOperands inside a single one.
3984 cvtStWriteBackRegAddrModeImm12(MCInst &Inst,
3985 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3986 // Create a writeback register dummy placeholder.
3987 Inst.addOperand(MCOperand::CreateImm(0));
3988 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
3989 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
3990 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
3993 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
3994 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
3995 /// when they refer multiple MIOperands inside a single one.
3997 cvtStWriteBackRegAddrMode2(MCInst &Inst,
3998 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3999 // Create a writeback register dummy placeholder.
4000 Inst.addOperand(MCOperand::CreateImm(0));
4001 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4002 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
4003 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4006 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4007 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4008 /// when they refer multiple MIOperands inside a single one.
4010 cvtStWriteBackRegAddrMode3(MCInst &Inst,
4011 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4012 // Create a writeback register dummy placeholder.
4013 Inst.addOperand(MCOperand::CreateImm(0));
4014 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4015 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4016 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4019 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
4020 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4021 /// when they refer multiple MIOperands inside a single one.
4023 cvtLdExtTWriteBackImm(MCInst &Inst,
4024 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4026 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4027 // Create a writeback register dummy placeholder.
4028 Inst.addOperand(MCOperand::CreateImm(0));
4030 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4032 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4034 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4037 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
4038 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4039 /// when they refer multiple MIOperands inside a single one.
4041 cvtLdExtTWriteBackReg(MCInst &Inst,
4042 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4044 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4045 // Create a writeback register dummy placeholder.
4046 Inst.addOperand(MCOperand::CreateImm(0));
4048 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4050 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4052 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4055 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
4056 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4057 /// when they refer multiple MIOperands inside a single one.
4059 cvtStExtTWriteBackImm(MCInst &Inst,
4060 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4061 // Create a writeback register dummy placeholder.
4062 Inst.addOperand(MCOperand::CreateImm(0));
4064 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4066 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4068 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
4070 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4073 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
4074 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4075 /// when they refer multiple MIOperands inside a single one.
4077 cvtStExtTWriteBackReg(MCInst &Inst,
4078 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4079 // Create a writeback register dummy placeholder.
4080 Inst.addOperand(MCOperand::CreateImm(0));
4082 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4084 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
4086 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
4088 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4091 /// cvtLdrdPre - Convert parsed operands to MCInst.
4092 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4093 /// when they refer multiple MIOperands inside a single one.
4095 cvtLdrdPre(MCInst &Inst,
4096 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4098 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4099 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4100 // Create a writeback register dummy placeholder.
4101 Inst.addOperand(MCOperand::CreateImm(0));
4103 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4105 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4108 /// cvtStrdPre - Convert parsed operands to MCInst.
4109 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4110 /// when they refer multiple MIOperands inside a single one.
4112 cvtStrdPre(MCInst &Inst,
4113 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4114 // Create a writeback register dummy placeholder.
4115 Inst.addOperand(MCOperand::CreateImm(0));
4117 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4118 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4120 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
4122 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4125 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
4126 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4127 /// when they refer multiple MIOperands inside a single one.
4129 cvtLdWriteBackRegAddrMode3(MCInst &Inst,
4130 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4131 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
4132 // Create a writeback register dummy placeholder.
4133 Inst.addOperand(MCOperand::CreateImm(0));
4134 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
4135 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4138 /// cvtThumbMultiply - Convert parsed operands to MCInst.
4139 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
4140 /// when they refer multiple MIOperands inside a single one.
4142 cvtThumbMultiply(MCInst &Inst,
4143 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4144 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4145 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4146 // If we have a three-operand form, make sure to set Rn to be the operand
4147 // that isn't the same as Rd.
4149 if (Operands.size() == 6 &&
4150 ((ARMOperand*)Operands[4])->getReg() ==
4151 ((ARMOperand*)Operands[3])->getReg())
4153 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4154 Inst.addOperand(Inst.getOperand(0));
4155 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4159 cvtVLDwbFixed(MCInst &Inst,
4160 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4162 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4163 // Create a writeback register dummy placeholder.
4164 Inst.addOperand(MCOperand::CreateImm(0));
4166 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4168 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4172 cvtVLDwbRegister(MCInst &Inst,
4173 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4175 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4176 // Create a writeback register dummy placeholder.
4177 Inst.addOperand(MCOperand::CreateImm(0));
4179 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4181 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4183 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4187 cvtVSTwbFixed(MCInst &Inst,
4188 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4189 // Create a writeback register dummy placeholder.
4190 Inst.addOperand(MCOperand::CreateImm(0));
4192 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4194 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4196 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4200 cvtVSTwbRegister(MCInst &Inst,
4201 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4202 // Create a writeback register dummy placeholder.
4203 Inst.addOperand(MCOperand::CreateImm(0));
4205 ((ARMOperand*)Operands[4])->addAlignedMemoryOperands(Inst, 2);
4207 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
4209 ((ARMOperand*)Operands[3])->addVecListOperands(Inst, 1);
4211 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
4214 /// Parse an ARM memory expression, return false if successful else return true
4215 /// or an error. The first token must be a '[' when called.
4217 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4219 assert(Parser.getTok().is(AsmToken::LBrac) &&
4220 "Token is not a Left Bracket");
4221 S = Parser.getTok().getLoc();
4222 Parser.Lex(); // Eat left bracket token.
4224 const AsmToken &BaseRegTok = Parser.getTok();
4225 int BaseRegNum = tryParseRegister();
4226 if (BaseRegNum == -1)
4227 return Error(BaseRegTok.getLoc(), "register expected");
4229 // The next token must either be a comma or a closing bracket.
4230 const AsmToken &Tok = Parser.getTok();
4231 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
4232 return Error(Tok.getLoc(), "malformed memory operand");
4234 if (Tok.is(AsmToken::RBrac)) {
4235 E = Tok.getEndLoc();
4236 Parser.Lex(); // Eat right bracket token.
4238 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4239 0, 0, false, S, E));
4241 // If there's a pre-indexing writeback marker, '!', just add it as a token
4242 // operand. It's rather odd, but syntactically valid.
4243 if (Parser.getTok().is(AsmToken::Exclaim)) {
4244 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4245 Parser.Lex(); // Eat the '!'.
4251 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
4252 Parser.Lex(); // Eat the comma.
4254 // If we have a ':', it's an alignment specifier.
4255 if (Parser.getTok().is(AsmToken::Colon)) {
4256 Parser.Lex(); // Eat the ':'.
4257 E = Parser.getTok().getLoc();
4260 if (getParser().ParseExpression(Expr))
4263 // The expression has to be a constant. Memory references with relocations
4264 // don't come through here, as they use the <label> forms of the relevant
4266 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4268 return Error (E, "constant expression expected");
4271 switch (CE->getValue()) {
4274 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4275 case 16: Align = 2; break;
4276 case 32: Align = 4; break;
4277 case 64: Align = 8; break;
4278 case 128: Align = 16; break;
4279 case 256: Align = 32; break;
4282 // Now we should have the closing ']'
4283 if (Parser.getTok().isNot(AsmToken::RBrac))
4284 return Error(Parser.getTok().getLoc(), "']' expected");
4285 E = Parser.getTok().getEndLoc();
4286 Parser.Lex(); // Eat right bracket token.
4288 // Don't worry about range checking the value here. That's handled by
4289 // the is*() predicates.
4290 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4291 ARM_AM::no_shift, 0, Align,
4294 // If there's a pre-indexing writeback marker, '!', just add it as a token
4296 if (Parser.getTok().is(AsmToken::Exclaim)) {
4297 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4298 Parser.Lex(); // Eat the '!'.
4304 // If we have a '#', it's an immediate offset, else assume it's a register
4305 // offset. Be friendly and also accept a plain integer (without a leading
4306 // hash) for gas compatibility.
4307 if (Parser.getTok().is(AsmToken::Hash) ||
4308 Parser.getTok().is(AsmToken::Dollar) ||
4309 Parser.getTok().is(AsmToken::Integer)) {
4310 if (Parser.getTok().isNot(AsmToken::Integer))
4311 Parser.Lex(); // Eat the '#'.
4312 E = Parser.getTok().getLoc();
4314 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4315 const MCExpr *Offset;
4316 if (getParser().ParseExpression(Offset))
4319 // The expression has to be a constant. Memory references with relocations
4320 // don't come through here, as they use the <label> forms of the relevant
4322 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4324 return Error (E, "constant expression expected");
4326 // If the constant was #-0, represent it as INT32_MIN.
4327 int32_t Val = CE->getValue();
4328 if (isNegative && Val == 0)
4329 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4331 // Now we should have the closing ']'
4332 if (Parser.getTok().isNot(AsmToken::RBrac))
4333 return Error(Parser.getTok().getLoc(), "']' expected");
4334 E = Parser.getTok().getEndLoc();
4335 Parser.Lex(); // Eat right bracket token.
4337 // Don't worry about range checking the value here. That's handled by
4338 // the is*() predicates.
4339 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4340 ARM_AM::no_shift, 0, 0,
4343 // If there's a pre-indexing writeback marker, '!', just add it as a token
4345 if (Parser.getTok().is(AsmToken::Exclaim)) {
4346 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4347 Parser.Lex(); // Eat the '!'.
4353 // The register offset is optionally preceded by a '+' or '-'
4354 bool isNegative = false;
4355 if (Parser.getTok().is(AsmToken::Minus)) {
4357 Parser.Lex(); // Eat the '-'.
4358 } else if (Parser.getTok().is(AsmToken::Plus)) {
4360 Parser.Lex(); // Eat the '+'.
4363 E = Parser.getTok().getLoc();
4364 int OffsetRegNum = tryParseRegister();
4365 if (OffsetRegNum == -1)
4366 return Error(E, "register expected");
4368 // If there's a shift operator, handle it.
4369 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4370 unsigned ShiftImm = 0;
4371 if (Parser.getTok().is(AsmToken::Comma)) {
4372 Parser.Lex(); // Eat the ','.
4373 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4377 // Now we should have the closing ']'
4378 if (Parser.getTok().isNot(AsmToken::RBrac))
4379 return Error(Parser.getTok().getLoc(), "']' expected");
4380 E = Parser.getTok().getEndLoc();
4381 Parser.Lex(); // Eat right bracket token.
4383 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4384 ShiftType, ShiftImm, 0, isNegative,
4387 // If there's a pre-indexing writeback marker, '!', just add it as a token
4389 if (Parser.getTok().is(AsmToken::Exclaim)) {
4390 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4391 Parser.Lex(); // Eat the '!'.
4397 /// parseMemRegOffsetShift - one of these two:
4398 /// ( lsl | lsr | asr | ror ) , # shift_amount
4400 /// return true if it parses a shift otherwise it returns false.
4401 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4403 SMLoc Loc = Parser.getTok().getLoc();
4404 const AsmToken &Tok = Parser.getTok();
4405 if (Tok.isNot(AsmToken::Identifier))
4407 StringRef ShiftName = Tok.getString();
4408 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4409 ShiftName == "asl" || ShiftName == "ASL")
4411 else if (ShiftName == "lsr" || ShiftName == "LSR")
4413 else if (ShiftName == "asr" || ShiftName == "ASR")
4415 else if (ShiftName == "ror" || ShiftName == "ROR")
4417 else if (ShiftName == "rrx" || ShiftName == "RRX")
4420 return Error(Loc, "illegal shift operator");
4421 Parser.Lex(); // Eat shift type token.
4423 // rrx stands alone.
4425 if (St != ARM_AM::rrx) {
4426 Loc = Parser.getTok().getLoc();
4427 // A '#' and a shift amount.
4428 const AsmToken &HashTok = Parser.getTok();
4429 if (HashTok.isNot(AsmToken::Hash) &&
4430 HashTok.isNot(AsmToken::Dollar))
4431 return Error(HashTok.getLoc(), "'#' expected");
4432 Parser.Lex(); // Eat hash token.
4435 if (getParser().ParseExpression(Expr))
4437 // Range check the immediate.
4438 // lsl, ror: 0 <= imm <= 31
4439 // lsr, asr: 0 <= imm <= 32
4440 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4442 return Error(Loc, "shift amount must be an immediate");
4443 int64_t Imm = CE->getValue();
4445 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4446 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4447 return Error(Loc, "immediate shift value out of range");
4448 // If <ShiftTy> #0, turn it into a no_shift.
4451 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4460 /// parseFPImm - A floating point immediate expression operand.
4461 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4462 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4463 // Anything that can accept a floating point constant as an operand
4464 // needs to go through here, as the regular ParseExpression is
4467 // This routine still creates a generic Immediate operand, containing
4468 // a bitcast of the 64-bit floating point value. The various operands
4469 // that accept floats can check whether the value is valid for them
4470 // via the standard is*() predicates.
4472 SMLoc S = Parser.getTok().getLoc();
4474 if (Parser.getTok().isNot(AsmToken::Hash) &&
4475 Parser.getTok().isNot(AsmToken::Dollar))
4476 return MatchOperand_NoMatch;
4478 // Disambiguate the VMOV forms that can accept an FP immediate.
4479 // vmov.f32 <sreg>, #imm
4480 // vmov.f64 <dreg>, #imm
4481 // vmov.f32 <dreg>, #imm @ vector f32x2
4482 // vmov.f32 <qreg>, #imm @ vector f32x4
4484 // There are also the NEON VMOV instructions which expect an
4485 // integer constant. Make sure we don't try to parse an FPImm
4487 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4488 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4489 if (!TyOp->isToken() || (TyOp->getToken() != ".f32" &&
4490 TyOp->getToken() != ".f64"))
4491 return MatchOperand_NoMatch;
4493 Parser.Lex(); // Eat the '#'.
4495 // Handle negation, as that still comes through as a separate token.
4496 bool isNegative = false;
4497 if (Parser.getTok().is(AsmToken::Minus)) {
4501 const AsmToken &Tok = Parser.getTok();
4502 SMLoc Loc = Tok.getLoc();
4503 if (Tok.is(AsmToken::Real)) {
4504 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4505 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4506 // If we had a '-' in front, toggle the sign bit.
4507 IntVal ^= (uint64_t)isNegative << 31;
4508 Parser.Lex(); // Eat the token.
4509 Operands.push_back(ARMOperand::CreateImm(
4510 MCConstantExpr::Create(IntVal, getContext()),
4511 S, Parser.getTok().getLoc()));
4512 return MatchOperand_Success;
4514 // Also handle plain integers. Instructions which allow floating point
4515 // immediates also allow a raw encoded 8-bit value.
4516 if (Tok.is(AsmToken::Integer)) {
4517 int64_t Val = Tok.getIntVal();
4518 Parser.Lex(); // Eat the token.
4519 if (Val > 255 || Val < 0) {
4520 Error(Loc, "encoded floating point value out of range");
4521 return MatchOperand_ParseFail;
4523 double RealVal = ARM_AM::getFPImmFloat(Val);
4524 Val = APFloat(APFloat::IEEEdouble, RealVal).bitcastToAPInt().getZExtValue();
4525 Operands.push_back(ARMOperand::CreateImm(
4526 MCConstantExpr::Create(Val, getContext()), S,
4527 Parser.getTok().getLoc()));
4528 return MatchOperand_Success;
4531 Error(Loc, "invalid floating point immediate");
4532 return MatchOperand_ParseFail;
4535 /// Parse a arm instruction operand. For now this parses the operand regardless
4536 /// of the mnemonic.
4537 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4538 StringRef Mnemonic) {
4541 // Check if the current operand has a custom associated parser, if so, try to
4542 // custom parse the operand, or fallback to the general approach.
4543 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4544 if (ResTy == MatchOperand_Success)
4546 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4547 // there was a match, but an error occurred, in which case, just return that
4548 // the operand parsing failed.
4549 if (ResTy == MatchOperand_ParseFail)
4552 switch (getLexer().getKind()) {
4554 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4556 case AsmToken::Identifier: {
4557 if (!tryParseRegisterWithWriteBack(Operands))
4559 int Res = tryParseShiftRegister(Operands);
4560 if (Res == 0) // success
4562 else if (Res == -1) // irrecoverable error
4564 // If this is VMRS, check for the apsr_nzcv operand.
4565 if (Mnemonic == "vmrs" &&
4566 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4567 S = Parser.getTok().getLoc();
4569 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4573 // Fall though for the Identifier case that is not a register or a
4576 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4577 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4578 case AsmToken::String: // quoted label names.
4579 case AsmToken::Dot: { // . as a branch target
4580 // This was not a register so parse other operands that start with an
4581 // identifier (like labels) as expressions and create them as immediates.
4582 const MCExpr *IdVal;
4583 S = Parser.getTok().getLoc();
4584 if (getParser().ParseExpression(IdVal))
4586 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4587 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4590 case AsmToken::LBrac:
4591 return parseMemory(Operands);
4592 case AsmToken::LCurly:
4593 return parseRegisterList(Operands);
4594 case AsmToken::Dollar:
4595 case AsmToken::Hash: {
4596 // #42 -> immediate.
4597 S = Parser.getTok().getLoc();
4600 if (Parser.getTok().isNot(AsmToken::Colon)) {
4601 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4602 const MCExpr *ImmVal;
4603 if (getParser().ParseExpression(ImmVal))
4605 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4607 int32_t Val = CE->getValue();
4608 if (isNegative && Val == 0)
4609 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4611 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4612 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4615 // w/ a ':' after the '#', it's just like a plain ':'.
4618 case AsmToken::Colon: {
4619 // ":lower16:" and ":upper16:" expression prefixes
4620 // FIXME: Check it's an expression prefix,
4621 // e.g. (FOO - :lower16:BAR) isn't legal.
4622 ARMMCExpr::VariantKind RefKind;
4623 if (parsePrefix(RefKind))
4626 const MCExpr *SubExprVal;
4627 if (getParser().ParseExpression(SubExprVal))
4630 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4632 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4633 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4639 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4640 // :lower16: and :upper16:.
4641 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4642 RefKind = ARMMCExpr::VK_ARM_None;
4644 // :lower16: and :upper16: modifiers
4645 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4646 Parser.Lex(); // Eat ':'
4648 if (getLexer().isNot(AsmToken::Identifier)) {
4649 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4653 StringRef IDVal = Parser.getTok().getIdentifier();
4654 if (IDVal == "lower16") {
4655 RefKind = ARMMCExpr::VK_ARM_LO16;
4656 } else if (IDVal == "upper16") {
4657 RefKind = ARMMCExpr::VK_ARM_HI16;
4659 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4664 if (getLexer().isNot(AsmToken::Colon)) {
4665 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4668 Parser.Lex(); // Eat the last ':'
4672 /// \brief Given a mnemonic, split out possible predication code and carry
4673 /// setting letters to form a canonical mnemonic and flags.
4675 // FIXME: Would be nice to autogen this.
4676 // FIXME: This is a bit of a maze of special cases.
4677 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4678 unsigned &PredicationCode,
4680 unsigned &ProcessorIMod,
4681 StringRef &ITMask) {
4682 PredicationCode = ARMCC::AL;
4683 CarrySetting = false;
4686 // Ignore some mnemonics we know aren't predicated forms.
4688 // FIXME: Would be nice to autogen this.
4689 if ((Mnemonic == "movs" && isThumb()) ||
4690 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4691 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4692 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4693 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4694 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4695 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4696 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4697 Mnemonic == "fmuls")
4700 // First, split out any predication code. Ignore mnemonics we know aren't
4701 // predicated but do have a carry-set and so weren't caught above.
4702 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4703 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4704 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4705 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4706 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4707 .Case("eq", ARMCC::EQ)
4708 .Case("ne", ARMCC::NE)
4709 .Case("hs", ARMCC::HS)
4710 .Case("cs", ARMCC::HS)
4711 .Case("lo", ARMCC::LO)
4712 .Case("cc", ARMCC::LO)
4713 .Case("mi", ARMCC::MI)
4714 .Case("pl", ARMCC::PL)
4715 .Case("vs", ARMCC::VS)
4716 .Case("vc", ARMCC::VC)
4717 .Case("hi", ARMCC::HI)
4718 .Case("ls", ARMCC::LS)
4719 .Case("ge", ARMCC::GE)
4720 .Case("lt", ARMCC::LT)
4721 .Case("gt", ARMCC::GT)
4722 .Case("le", ARMCC::LE)
4723 .Case("al", ARMCC::AL)
4726 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4727 PredicationCode = CC;
4731 // Next, determine if we have a carry setting bit. We explicitly ignore all
4732 // the instructions we know end in 's'.
4733 if (Mnemonic.endswith("s") &&
4734 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4735 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4736 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4737 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4738 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4739 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4740 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4741 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4742 Mnemonic == "vfms" || Mnemonic == "vfnms" ||
4743 (Mnemonic == "movs" && isThumb()))) {
4744 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4745 CarrySetting = true;
4748 // The "cps" instruction can have a interrupt mode operand which is glued into
4749 // the mnemonic. Check if this is the case, split it and parse the imod op
4750 if (Mnemonic.startswith("cps")) {
4751 // Split out any imod code.
4753 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4754 .Case("ie", ARM_PROC::IE)
4755 .Case("id", ARM_PROC::ID)
4758 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4759 ProcessorIMod = IMod;
4763 // The "it" instruction has the condition mask on the end of the mnemonic.
4764 if (Mnemonic.startswith("it")) {
4765 ITMask = Mnemonic.slice(2, Mnemonic.size());
4766 Mnemonic = Mnemonic.slice(0, 2);
4772 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4773 /// inclusion of carry set or predication code operands.
4775 // FIXME: It would be nice to autogen this.
4777 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
4778 bool &CanAcceptPredicationCode) {
4779 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4780 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4781 Mnemonic == "add" || Mnemonic == "adc" ||
4782 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4783 Mnemonic == "orr" || Mnemonic == "mvn" ||
4784 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4785 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4786 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4787 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4788 Mnemonic == "mla" || Mnemonic == "smlal" ||
4789 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4790 CanAcceptCarrySet = true;
4792 CanAcceptCarrySet = false;
4794 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
4795 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
4796 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
4797 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
4798 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
4799 (Mnemonic == "clrex" && !isThumb()) ||
4800 (Mnemonic == "nop" && isThumbOne()) ||
4801 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw" ||
4802 Mnemonic == "ldc2" || Mnemonic == "ldc2l" ||
4803 Mnemonic == "stc2" || Mnemonic == "stc2l") && !isThumb()) ||
4804 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
4806 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
4807 CanAcceptPredicationCode = false;
4809 CanAcceptPredicationCode = true;
4812 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
4813 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
4814 CanAcceptPredicationCode = false;
4818 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4819 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4820 // FIXME: This is all horribly hacky. We really need a better way to deal
4821 // with optional operands like this in the matcher table.
4823 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4824 // another does not. Specifically, the MOVW instruction does not. So we
4825 // special case it here and remove the defaulted (non-setting) cc_out
4826 // operand if that's the instruction we're trying to match.
4828 // We do this as post-processing of the explicit operands rather than just
4829 // conditionally adding the cc_out in the first place because we need
4830 // to check the type of the parsed immediate operand.
4831 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4832 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4833 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4834 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4837 // Register-register 'add' for thumb does not have a cc_out operand
4838 // when there are only two register operands.
4839 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4840 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4841 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4842 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4844 // Register-register 'add' for thumb does not have a cc_out operand
4845 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4846 // have to check the immediate range here since Thumb2 has a variant
4847 // that can handle a different range and has a cc_out operand.
4848 if (((isThumb() && Mnemonic == "add") ||
4849 (isThumbTwo() && Mnemonic == "sub")) &&
4850 Operands.size() == 6 &&
4851 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4852 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4853 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4854 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4855 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4856 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4858 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4859 // imm0_4095 variant. That's the least-preferred variant when
4860 // selecting via the generic "add" mnemonic, so to know that we
4861 // should remove the cc_out operand, we have to explicitly check that
4862 // it's not one of the other variants. Ugh.
4863 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4864 Operands.size() == 6 &&
4865 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4866 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4867 static_cast<ARMOperand*>(Operands[5])->isImm()) {
4868 // Nest conditions rather than one big 'if' statement for readability.
4870 // If either register is a high reg, it's either one of the SP
4871 // variants (handled above) or a 32-bit encoding, so we just
4872 // check against T3. If the second register is the PC, this is an
4873 // alternate form of ADR, which uses encoding T4, so check for that too.
4874 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4875 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
4876 static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
4877 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
4879 // If both registers are low, we're in an IT block, and the immediate is
4880 // in range, we should use encoding T1 instead, which has a cc_out.
4882 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
4883 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
4884 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
4887 // Otherwise, we use encoding T4, which does not have a cc_out
4892 // The thumb2 multiply instruction doesn't have a CCOut register, so
4893 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
4894 // use the 16-bit encoding or not.
4895 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
4896 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4897 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4898 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4899 static_cast<ARMOperand*>(Operands[5])->isReg() &&
4900 // If the registers aren't low regs, the destination reg isn't the
4901 // same as one of the source regs, or the cc_out operand is zero
4902 // outside of an IT block, we have to use the 32-bit encoding, so
4903 // remove the cc_out operand.
4904 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4905 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4906 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
4908 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
4909 static_cast<ARMOperand*>(Operands[5])->getReg() &&
4910 static_cast<ARMOperand*>(Operands[3])->getReg() !=
4911 static_cast<ARMOperand*>(Operands[4])->getReg())))
4914 // Also check the 'mul' syntax variant that doesn't specify an explicit
4915 // destination register.
4916 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
4917 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4918 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4919 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4920 // If the registers aren't low regs or the cc_out operand is zero
4921 // outside of an IT block, we have to use the 32-bit encoding, so
4922 // remove the cc_out operand.
4923 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
4924 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
4930 // Register-register 'add/sub' for thumb does not have a cc_out operand
4931 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
4932 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
4933 // right, this will result in better diagnostics (which operand is off)
4935 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
4936 (Operands.size() == 5 || Operands.size() == 6) &&
4937 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4938 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
4939 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4940 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
4941 (Operands.size() == 6 &&
4942 static_cast<ARMOperand*>(Operands[5])->isImm())))
4948 static bool isDataTypeToken(StringRef Tok) {
4949 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
4950 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
4951 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
4952 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
4953 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
4954 Tok == ".f" || Tok == ".d";
4957 // FIXME: This bit should probably be handled via an explicit match class
4958 // in the .td files that matches the suffix instead of having it be
4959 // a literal string token the way it is now.
4960 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
4961 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
4964 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features);
4965 /// Parse an arm instruction mnemonic followed by its operands.
4966 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
4968 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4969 // Apply mnemonic aliases before doing anything else, as the destination
4970 // mnemnonic may include suffices and we want to handle them normally.
4971 // The generic tblgen'erated code does this later, at the start of
4972 // MatchInstructionImpl(), but that's too late for aliases that include
4973 // any sort of suffix.
4974 unsigned AvailableFeatures = getAvailableFeatures();
4975 applyMnemonicAliases(Name, AvailableFeatures);
4977 // First check for the ARM-specific .req directive.
4978 if (Parser.getTok().is(AsmToken::Identifier) &&
4979 Parser.getTok().getIdentifier() == ".req") {
4980 parseDirectiveReq(Name, NameLoc);
4981 // We always return 'error' for this, as we're done with this
4982 // statement and don't need to match the 'instruction."
4986 // Create the leading tokens for the mnemonic, split by '.' characters.
4987 size_t Start = 0, Next = Name.find('.');
4988 StringRef Mnemonic = Name.slice(Start, Next);
4990 // Split out the predication code and carry setting flag from the mnemonic.
4991 unsigned PredicationCode;
4992 unsigned ProcessorIMod;
4995 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
4996 ProcessorIMod, ITMask);
4998 // In Thumb1, only the branch (B) instruction can be predicated.
4999 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5000 Parser.EatToEndOfStatement();
5001 return Error(NameLoc, "conditional execution not supported in Thumb1");
5004 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5006 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5007 // is the mask as it will be for the IT encoding if the conditional
5008 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5009 // where the conditional bit0 is zero, the instruction post-processing
5010 // will adjust the mask accordingly.
5011 if (Mnemonic == "it") {
5012 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5013 if (ITMask.size() > 3) {
5014 Parser.EatToEndOfStatement();
5015 return Error(Loc, "too many conditions on IT instruction");
5018 for (unsigned i = ITMask.size(); i != 0; --i) {
5019 char pos = ITMask[i - 1];
5020 if (pos != 't' && pos != 'e') {
5021 Parser.EatToEndOfStatement();
5022 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5025 if (ITMask[i - 1] == 't')
5028 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5031 // FIXME: This is all a pretty gross hack. We should automatically handle
5032 // optional operands like this via tblgen.
5034 // Next, add the CCOut and ConditionCode operands, if needed.
5036 // For mnemonics which can ever incorporate a carry setting bit or predication
5037 // code, our matching model involves us always generating CCOut and
5038 // ConditionCode operands to match the mnemonic "as written" and then we let
5039 // the matcher deal with finding the right instruction or generating an
5040 // appropriate error.
5041 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5042 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
5044 // If we had a carry-set on an instruction that can't do that, issue an
5046 if (!CanAcceptCarrySet && CarrySetting) {
5047 Parser.EatToEndOfStatement();
5048 return Error(NameLoc, "instruction '" + Mnemonic +
5049 "' can not set flags, but 's' suffix specified");
5051 // If we had a predication code on an instruction that can't do that, issue an
5053 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5054 Parser.EatToEndOfStatement();
5055 return Error(NameLoc, "instruction '" + Mnemonic +
5056 "' is not predicable, but condition code specified");
5059 // Add the carry setting operand, if necessary.
5060 if (CanAcceptCarrySet) {
5061 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5062 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5066 // Add the predication code operand, if necessary.
5067 if (CanAcceptPredicationCode) {
5068 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5070 Operands.push_back(ARMOperand::CreateCondCode(
5071 ARMCC::CondCodes(PredicationCode), Loc));
5074 // Add the processor imod operand, if necessary.
5075 if (ProcessorIMod) {
5076 Operands.push_back(ARMOperand::CreateImm(
5077 MCConstantExpr::Create(ProcessorIMod, getContext()),
5081 // Add the remaining tokens in the mnemonic.
5082 while (Next != StringRef::npos) {
5084 Next = Name.find('.', Start + 1);
5085 StringRef ExtraToken = Name.slice(Start, Next);
5087 // Some NEON instructions have an optional datatype suffix that is
5088 // completely ignored. Check for that.
5089 if (isDataTypeToken(ExtraToken) &&
5090 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5093 if (ExtraToken != ".n") {
5094 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5095 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5099 // Read the remaining operands.
5100 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5101 // Read the first operand.
5102 if (parseOperand(Operands, Mnemonic)) {
5103 Parser.EatToEndOfStatement();
5107 while (getLexer().is(AsmToken::Comma)) {
5108 Parser.Lex(); // Eat the comma.
5110 // Parse and remember the operand.
5111 if (parseOperand(Operands, Mnemonic)) {
5112 Parser.EatToEndOfStatement();
5118 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5119 SMLoc Loc = getLexer().getLoc();
5120 Parser.EatToEndOfStatement();
5121 return Error(Loc, "unexpected token in argument list");
5124 Parser.Lex(); // Consume the EndOfStatement
5126 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5127 // do and don't have a cc_out optional-def operand. With some spot-checks
5128 // of the operand list, we can figure out which variant we're trying to
5129 // parse and adjust accordingly before actually matching. We shouldn't ever
5130 // try to remove a cc_out operand that was explicitly set on the the
5131 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5132 // table driven matcher doesn't fit well with the ARM instruction set.
5133 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5134 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5135 Operands.erase(Operands.begin() + 1);
5139 // ARM mode 'blx' need special handling, as the register operand version
5140 // is predicable, but the label operand version is not. So, we can't rely
5141 // on the Mnemonic based checking to correctly figure out when to put
5142 // a k_CondCode operand in the list. If we're trying to match the label
5143 // version, remove the k_CondCode operand here.
5144 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5145 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5146 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5147 Operands.erase(Operands.begin() + 1);
5151 // The vector-compare-to-zero instructions have a literal token "#0" at
5152 // the end that comes to here as an immediate operand. Convert it to a
5153 // token to play nicely with the matcher.
5154 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
5155 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
5156 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5157 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5158 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5159 if (CE && CE->getValue() == 0) {
5160 Operands.erase(Operands.begin() + 5);
5161 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5165 // VCMP{E} does the same thing, but with a different operand count.
5166 if ((Mnemonic == "vcmp" || Mnemonic == "vcmpe") && Operands.size() == 5 &&
5167 static_cast<ARMOperand*>(Operands[4])->isImm()) {
5168 ARMOperand *Op = static_cast<ARMOperand*>(Operands[4]);
5169 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5170 if (CE && CE->getValue() == 0) {
5171 Operands.erase(Operands.begin() + 4);
5172 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5176 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
5177 // end. Convert it to a token here. Take care not to convert those
5178 // that should hit the Thumb2 encoding.
5179 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
5180 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5181 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5182 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5183 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
5184 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
5185 if (CE && CE->getValue() == 0 &&
5187 // The cc_out operand matches the IT block.
5188 ((inITBlock() != CarrySetting) &&
5189 // Neither register operand is a high register.
5190 (isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5191 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()))))){
5192 Operands.erase(Operands.begin() + 5);
5193 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
5198 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5199 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5200 // a single GPRPair reg operand is used in the .td file to replace the two
5201 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5202 // expressed as a GPRPair, so we have to manually merge them.
5203 // FIXME: We would really like to be able to tablegen'erate this.
5204 if (!isThumb() && Operands.size() > 4 &&
5205 (Mnemonic == "ldrexd" || Mnemonic == "strexd")) {
5206 bool isLoad = (Mnemonic == "ldrexd");
5207 unsigned Idx = isLoad ? 2 : 3;
5208 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5209 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5211 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5212 // Adjust only if Op1 and Op2 are GPRs.
5213 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5214 MRC.contains(Op2->getReg())) {
5215 unsigned Reg1 = Op1->getReg();
5216 unsigned Reg2 = Op2->getReg();
5217 unsigned Rt = MRI->getEncodingValue(Reg1);
5218 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5220 // Rt2 must be Rt + 1 and Rt must be even.
5221 if (Rt + 1 != Rt2 || (Rt & 1)) {
5222 Error(Op2->getStartLoc(), isLoad ?
5223 "destination operands must be sequential" :
5224 "source operands must be sequential");
5227 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5228 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5229 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5230 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5231 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5240 // Validate context-sensitive operand constraints.
5242 // return 'true' if register list contains non-low GPR registers,
5243 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5244 // 'containsReg' to true.
5245 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5246 unsigned HiReg, bool &containsReg) {
5247 containsReg = false;
5248 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5249 unsigned OpReg = Inst.getOperand(i).getReg();
5252 // Anything other than a low register isn't legal here.
5253 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5259 // Check if the specified regisgter is in the register list of the inst,
5260 // starting at the indicated operand number.
5261 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5262 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5263 unsigned OpReg = Inst.getOperand(i).getReg();
5270 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
5271 // the ARMInsts array) instead. Getting that here requires awkward
5272 // API changes, though. Better way?
5274 extern const MCInstrDesc ARMInsts[];
5276 static const MCInstrDesc &getInstDesc(unsigned Opcode) {
5277 return ARMInsts[Opcode];
5280 // FIXME: We would really like to be able to tablegen'erate this.
5282 validateInstruction(MCInst &Inst,
5283 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5284 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
5285 SMLoc Loc = Operands[0]->getStartLoc();
5286 // Check the IT block state first.
5287 // NOTE: BKPT instruction has the interesting property of being
5288 // allowed in IT blocks, but not being predicable. It just always
5290 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT &&
5291 Inst.getOpcode() != ARM::BKPT) {
5293 if (ITState.FirstCond)
5294 ITState.FirstCond = false;
5296 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5297 // The instruction must be predicable.
5298 if (!MCID.isPredicable())
5299 return Error(Loc, "instructions in IT block must be predicable");
5300 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5301 unsigned ITCond = bit ? ITState.Cond :
5302 ARMCC::getOppositeCondition(ITState.Cond);
5303 if (Cond != ITCond) {
5304 // Find the condition code Operand to get its SMLoc information.
5306 for (unsigned i = 1; i < Operands.size(); ++i)
5307 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
5308 CondLoc = Operands[i]->getStartLoc();
5309 return Error(CondLoc, "incorrect condition in IT block; got '" +
5310 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5311 "', but expected '" +
5312 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5314 // Check for non-'al' condition codes outside of the IT block.
5315 } else if (isThumbTwo() && MCID.isPredicable() &&
5316 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5317 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
5318 Inst.getOpcode() != ARM::t2B)
5319 return Error(Loc, "predicated instructions must be in IT block");
5321 switch (Inst.getOpcode()) {
5324 case ARM::LDRD_POST: {
5325 // Rt2 must be Rt + 1.
5326 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5327 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5329 return Error(Operands[3]->getStartLoc(),
5330 "destination operands must be sequential");
5334 // Rt2 must be Rt + 1.
5335 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5336 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5338 return Error(Operands[3]->getStartLoc(),
5339 "source operands must be sequential");
5343 case ARM::STRD_POST: {
5344 // Rt2 must be Rt + 1.
5345 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5346 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5348 return Error(Operands[3]->getStartLoc(),
5349 "source operands must be sequential");
5354 // width must be in range [1, 32-lsb]
5355 unsigned lsb = Inst.getOperand(2).getImm();
5356 unsigned widthm1 = Inst.getOperand(3).getImm();
5357 if (widthm1 >= 32 - lsb)
5358 return Error(Operands[5]->getStartLoc(),
5359 "bitfield width must be in range [1,32-lsb]");
5363 // If we're parsing Thumb2, the .w variant is available and handles
5364 // most cases that are normally illegal for a Thumb1 LDM
5365 // instruction. We'll make the transformation in processInstruction()
5368 // Thumb LDM instructions are writeback iff the base register is not
5369 // in the register list.
5370 unsigned Rn = Inst.getOperand(0).getReg();
5371 bool hasWritebackToken =
5372 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5373 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5374 bool listContainsBase;
5375 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
5376 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
5377 "registers must be in range r0-r7");
5378 // If we should have writeback, then there should be a '!' token.
5379 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
5380 return Error(Operands[2]->getStartLoc(),
5381 "writeback operator '!' expected");
5382 // If we should not have writeback, there must not be a '!'. This is
5383 // true even for the 32-bit wide encodings.
5384 if (listContainsBase && hasWritebackToken)
5385 return Error(Operands[3]->getStartLoc(),
5386 "writeback operator '!' not allowed when base register "
5387 "in register list");
5391 case ARM::t2LDMIA_UPD: {
5392 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5393 return Error(Operands[4]->getStartLoc(),
5394 "writeback operator '!' not allowed when base register "
5395 "in register list");
5399 // The second source operand must be the same register as the destination
5402 // In this case, we must directly check the parsed operands because the
5403 // cvtThumbMultiply() function is written in such a way that it guarantees
5404 // this first statement is always true for the new Inst. Essentially, the
5405 // destination is unconditionally copied into the second source operand
5406 // without checking to see if it matches what we actually parsed.
5407 if (Operands.size() == 6 &&
5408 (((ARMOperand*)Operands[3])->getReg() !=
5409 ((ARMOperand*)Operands[5])->getReg()) &&
5410 (((ARMOperand*)Operands[3])->getReg() !=
5411 ((ARMOperand*)Operands[4])->getReg())) {
5412 return Error(Operands[3]->getStartLoc(),
5413 "destination register must match source register");
5417 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5418 // so only issue a diagnostic for thumb1. The instructions will be
5419 // switched to the t2 encodings in processInstruction() if necessary.
5421 bool listContainsBase;
5422 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase) &&
5424 return Error(Operands[2]->getStartLoc(),
5425 "registers must be in range r0-r7 or pc");
5429 bool listContainsBase;
5430 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase) &&
5432 return Error(Operands[2]->getStartLoc(),
5433 "registers must be in range r0-r7 or lr");
5436 case ARM::tSTMIA_UPD: {
5437 bool listContainsBase;
5438 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
5439 return Error(Operands[4]->getStartLoc(),
5440 "registers must be in range r0-r7");
5443 case ARM::tADDrSP: {
5444 // If the non-SP source operand and the destination operand are not the
5445 // same, we need thumb2 (for the wide encoding), or we have an error.
5446 if (!isThumbTwo() &&
5447 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5448 return Error(Operands[4]->getStartLoc(),
5449 "source register must be the same as destination");
5458 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5460 default: llvm_unreachable("unexpected opcode!");
5462 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5463 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5464 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5465 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5466 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5467 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5468 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5469 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5470 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5473 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5474 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5475 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5476 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5477 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5479 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5480 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5481 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5482 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5483 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5485 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5486 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5487 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5488 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5489 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5492 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5493 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5494 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5495 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5496 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5497 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5498 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5499 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5500 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5501 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5502 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5503 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5504 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5505 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5506 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5509 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5510 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5511 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5512 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5513 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5514 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5515 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5516 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5517 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5518 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5519 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5520 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5521 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5522 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5523 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5524 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5525 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5526 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5529 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5530 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5531 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5532 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5533 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5534 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5535 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5536 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5537 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5538 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5539 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5540 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5541 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5542 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5543 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5546 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5547 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5548 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5549 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5550 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5551 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5552 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5553 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5554 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5555 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5556 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5557 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5558 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5559 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5560 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5561 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5562 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5563 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5567 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5569 default: llvm_unreachable("unexpected opcode!");
5571 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5572 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5573 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5574 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5575 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5576 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5577 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5578 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5579 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5582 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5583 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5584 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5585 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5586 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5587 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5588 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5589 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5590 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5591 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5592 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5593 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5594 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5595 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5596 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5599 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5600 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5601 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5602 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5603 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5604 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5605 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5606 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5607 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5608 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5609 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5610 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5611 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5612 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5613 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5614 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5615 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5616 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5619 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5620 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5621 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5622 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5623 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5624 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5625 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5626 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5627 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5628 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5629 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5630 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5631 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5632 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5633 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5636 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5637 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5638 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5639 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5640 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5641 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5642 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5643 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5644 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5645 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5646 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5647 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5648 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5649 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5650 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5651 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5652 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5653 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5656 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5657 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5658 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5659 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5660 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5661 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5662 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5663 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5664 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5665 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5666 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5667 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5668 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5669 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5670 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5673 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5674 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5675 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5676 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5677 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5678 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5679 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5680 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5681 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5682 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5683 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5684 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5685 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5686 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5687 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5688 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5689 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5690 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5693 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5694 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5695 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5696 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5697 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5698 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5699 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5700 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5701 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5702 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5703 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5704 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5705 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5706 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5707 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5708 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5709 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5710 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
5715 processInstruction(MCInst &Inst,
5716 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5717 switch (Inst.getOpcode()) {
5718 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5720 if (Inst.getOperand(1).getReg() != ARM::PC ||
5721 Inst.getOperand(5).getReg() != 0)
5724 TmpInst.setOpcode(ARM::ADR);
5725 TmpInst.addOperand(Inst.getOperand(0));
5726 TmpInst.addOperand(Inst.getOperand(2));
5727 TmpInst.addOperand(Inst.getOperand(3));
5728 TmpInst.addOperand(Inst.getOperand(4));
5732 // Aliases for alternate PC+imm syntax of LDR instructions.
5733 case ARM::t2LDRpcrel:
5734 // Select the narrow version if the immediate will fit.
5735 if (Inst.getOperand(1).getImm() > 0 &&
5736 Inst.getOperand(1).getImm() <= 0xff)
5737 Inst.setOpcode(ARM::tLDRpci);
5739 Inst.setOpcode(ARM::t2LDRpci);
5741 case ARM::t2LDRBpcrel:
5742 Inst.setOpcode(ARM::t2LDRBpci);
5744 case ARM::t2LDRHpcrel:
5745 Inst.setOpcode(ARM::t2LDRHpci);
5747 case ARM::t2LDRSBpcrel:
5748 Inst.setOpcode(ARM::t2LDRSBpci);
5750 case ARM::t2LDRSHpcrel:
5751 Inst.setOpcode(ARM::t2LDRSHpci);
5753 // Handle NEON VST complex aliases.
5754 case ARM::VST1LNdWB_register_Asm_8:
5755 case ARM::VST1LNdWB_register_Asm_16:
5756 case ARM::VST1LNdWB_register_Asm_32: {
5758 // Shuffle the operands around so the lane index operand is in the
5761 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5762 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5763 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5764 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5765 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5766 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5767 TmpInst.addOperand(Inst.getOperand(1)); // lane
5768 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5769 TmpInst.addOperand(Inst.getOperand(6));
5774 case ARM::VST2LNdWB_register_Asm_8:
5775 case ARM::VST2LNdWB_register_Asm_16:
5776 case ARM::VST2LNdWB_register_Asm_32:
5777 case ARM::VST2LNqWB_register_Asm_16:
5778 case ARM::VST2LNqWB_register_Asm_32: {
5780 // Shuffle the operands around so the lane index operand is in the
5783 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5784 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5785 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5786 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5787 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5788 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5789 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5791 TmpInst.addOperand(Inst.getOperand(1)); // lane
5792 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5793 TmpInst.addOperand(Inst.getOperand(6));
5798 case ARM::VST3LNdWB_register_Asm_8:
5799 case ARM::VST3LNdWB_register_Asm_16:
5800 case ARM::VST3LNdWB_register_Asm_32:
5801 case ARM::VST3LNqWB_register_Asm_16:
5802 case ARM::VST3LNqWB_register_Asm_32: {
5804 // Shuffle the operands around so the lane index operand is in the
5807 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5808 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5809 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5810 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5811 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5812 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5813 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5815 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5817 TmpInst.addOperand(Inst.getOperand(1)); // lane
5818 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5819 TmpInst.addOperand(Inst.getOperand(6));
5824 case ARM::VST4LNdWB_register_Asm_8:
5825 case ARM::VST4LNdWB_register_Asm_16:
5826 case ARM::VST4LNdWB_register_Asm_32:
5827 case ARM::VST4LNqWB_register_Asm_16:
5828 case ARM::VST4LNqWB_register_Asm_32: {
5830 // Shuffle the operands around so the lane index operand is in the
5833 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5834 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5835 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5836 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5837 TmpInst.addOperand(Inst.getOperand(4)); // Rm
5838 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5839 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5841 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5843 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5845 TmpInst.addOperand(Inst.getOperand(1)); // lane
5846 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
5847 TmpInst.addOperand(Inst.getOperand(6));
5852 case ARM::VST1LNdWB_fixed_Asm_8:
5853 case ARM::VST1LNdWB_fixed_Asm_16:
5854 case ARM::VST1LNdWB_fixed_Asm_32: {
5856 // Shuffle the operands around so the lane index operand is in the
5859 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5860 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5861 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5862 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5863 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5864 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5865 TmpInst.addOperand(Inst.getOperand(1)); // lane
5866 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5867 TmpInst.addOperand(Inst.getOperand(5));
5872 case ARM::VST2LNdWB_fixed_Asm_8:
5873 case ARM::VST2LNdWB_fixed_Asm_16:
5874 case ARM::VST2LNdWB_fixed_Asm_32:
5875 case ARM::VST2LNqWB_fixed_Asm_16:
5876 case ARM::VST2LNqWB_fixed_Asm_32: {
5878 // Shuffle the operands around so the lane index operand is in the
5881 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5882 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5883 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5884 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5885 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5886 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5887 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5889 TmpInst.addOperand(Inst.getOperand(1)); // lane
5890 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5891 TmpInst.addOperand(Inst.getOperand(5));
5896 case ARM::VST3LNdWB_fixed_Asm_8:
5897 case ARM::VST3LNdWB_fixed_Asm_16:
5898 case ARM::VST3LNdWB_fixed_Asm_32:
5899 case ARM::VST3LNqWB_fixed_Asm_16:
5900 case ARM::VST3LNqWB_fixed_Asm_32: {
5902 // Shuffle the operands around so the lane index operand is in the
5905 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5906 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5907 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5908 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5909 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5910 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5911 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5913 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5915 TmpInst.addOperand(Inst.getOperand(1)); // lane
5916 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5917 TmpInst.addOperand(Inst.getOperand(5));
5922 case ARM::VST4LNdWB_fixed_Asm_8:
5923 case ARM::VST4LNdWB_fixed_Asm_16:
5924 case ARM::VST4LNdWB_fixed_Asm_32:
5925 case ARM::VST4LNqWB_fixed_Asm_16:
5926 case ARM::VST4LNqWB_fixed_Asm_32: {
5928 // Shuffle the operands around so the lane index operand is in the
5931 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5932 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
5933 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5934 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5935 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
5936 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5937 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5939 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5941 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5943 TmpInst.addOperand(Inst.getOperand(1)); // lane
5944 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5945 TmpInst.addOperand(Inst.getOperand(5));
5950 case ARM::VST1LNdAsm_8:
5951 case ARM::VST1LNdAsm_16:
5952 case ARM::VST1LNdAsm_32: {
5954 // Shuffle the operands around so the lane index operand is in the
5957 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5958 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5959 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5960 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5961 TmpInst.addOperand(Inst.getOperand(1)); // lane
5962 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5963 TmpInst.addOperand(Inst.getOperand(5));
5968 case ARM::VST2LNdAsm_8:
5969 case ARM::VST2LNdAsm_16:
5970 case ARM::VST2LNdAsm_32:
5971 case ARM::VST2LNqAsm_16:
5972 case ARM::VST2LNqAsm_32: {
5974 // Shuffle the operands around so the lane index operand is in the
5977 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
5978 TmpInst.addOperand(Inst.getOperand(2)); // Rn
5979 TmpInst.addOperand(Inst.getOperand(3)); // alignment
5980 TmpInst.addOperand(Inst.getOperand(0)); // Vd
5981 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
5983 TmpInst.addOperand(Inst.getOperand(1)); // lane
5984 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
5985 TmpInst.addOperand(Inst.getOperand(5));
5990 case ARM::VST3LNdAsm_8:
5991 case ARM::VST3LNdAsm_16:
5992 case ARM::VST3LNdAsm_32:
5993 case ARM::VST3LNqAsm_16:
5994 case ARM::VST3LNqAsm_32: {
5996 // Shuffle the operands around so the lane index operand is in the
5999 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6000 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6001 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6002 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6003 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6005 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6007 TmpInst.addOperand(Inst.getOperand(1)); // lane
6008 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6009 TmpInst.addOperand(Inst.getOperand(5));
6014 case ARM::VST4LNdAsm_8:
6015 case ARM::VST4LNdAsm_16:
6016 case ARM::VST4LNdAsm_32:
6017 case ARM::VST4LNqAsm_16:
6018 case ARM::VST4LNqAsm_32: {
6020 // Shuffle the operands around so the lane index operand is in the
6023 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6024 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6025 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6026 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6027 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6029 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6031 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6033 TmpInst.addOperand(Inst.getOperand(1)); // lane
6034 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6035 TmpInst.addOperand(Inst.getOperand(5));
6040 // Handle NEON VLD complex aliases.
6041 case ARM::VLD1LNdWB_register_Asm_8:
6042 case ARM::VLD1LNdWB_register_Asm_16:
6043 case ARM::VLD1LNdWB_register_Asm_32: {
6045 // Shuffle the operands around so the lane index operand is in the
6048 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6049 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6050 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6051 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6052 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6053 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6054 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6055 TmpInst.addOperand(Inst.getOperand(1)); // lane
6056 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6057 TmpInst.addOperand(Inst.getOperand(6));
6062 case ARM::VLD2LNdWB_register_Asm_8:
6063 case ARM::VLD2LNdWB_register_Asm_16:
6064 case ARM::VLD2LNdWB_register_Asm_32:
6065 case ARM::VLD2LNqWB_register_Asm_16:
6066 case ARM::VLD2LNqWB_register_Asm_32: {
6068 // Shuffle the operands around so the lane index operand is in the
6071 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6072 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6073 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6075 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6076 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6077 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6078 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6079 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6080 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6082 TmpInst.addOperand(Inst.getOperand(1)); // lane
6083 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6084 TmpInst.addOperand(Inst.getOperand(6));
6089 case ARM::VLD3LNdWB_register_Asm_8:
6090 case ARM::VLD3LNdWB_register_Asm_16:
6091 case ARM::VLD3LNdWB_register_Asm_32:
6092 case ARM::VLD3LNqWB_register_Asm_16:
6093 case ARM::VLD3LNqWB_register_Asm_32: {
6095 // Shuffle the operands around so the lane index operand is in the
6098 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6099 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6100 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6102 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6104 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6105 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6106 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6107 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6108 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6109 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6111 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6113 TmpInst.addOperand(Inst.getOperand(1)); // lane
6114 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6115 TmpInst.addOperand(Inst.getOperand(6));
6120 case ARM::VLD4LNdWB_register_Asm_8:
6121 case ARM::VLD4LNdWB_register_Asm_16:
6122 case ARM::VLD4LNdWB_register_Asm_32:
6123 case ARM::VLD4LNqWB_register_Asm_16:
6124 case ARM::VLD4LNqWB_register_Asm_32: {
6126 // Shuffle the operands around so the lane index operand is in the
6129 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6130 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6131 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6133 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6135 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6137 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6138 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6139 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6140 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6141 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6142 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6144 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6146 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6148 TmpInst.addOperand(Inst.getOperand(1)); // lane
6149 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6150 TmpInst.addOperand(Inst.getOperand(6));
6155 case ARM::VLD1LNdWB_fixed_Asm_8:
6156 case ARM::VLD1LNdWB_fixed_Asm_16:
6157 case ARM::VLD1LNdWB_fixed_Asm_32: {
6159 // Shuffle the operands around so the lane index operand is in the
6162 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6163 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6164 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6165 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6166 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6167 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6168 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6169 TmpInst.addOperand(Inst.getOperand(1)); // lane
6170 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6171 TmpInst.addOperand(Inst.getOperand(5));
6176 case ARM::VLD2LNdWB_fixed_Asm_8:
6177 case ARM::VLD2LNdWB_fixed_Asm_16:
6178 case ARM::VLD2LNdWB_fixed_Asm_32:
6179 case ARM::VLD2LNqWB_fixed_Asm_16:
6180 case ARM::VLD2LNqWB_fixed_Asm_32: {
6182 // Shuffle the operands around so the lane index operand is in the
6185 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6186 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6187 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6189 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6190 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6191 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6192 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6193 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6194 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6196 TmpInst.addOperand(Inst.getOperand(1)); // lane
6197 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6198 TmpInst.addOperand(Inst.getOperand(5));
6203 case ARM::VLD3LNdWB_fixed_Asm_8:
6204 case ARM::VLD3LNdWB_fixed_Asm_16:
6205 case ARM::VLD3LNdWB_fixed_Asm_32:
6206 case ARM::VLD3LNqWB_fixed_Asm_16:
6207 case ARM::VLD3LNqWB_fixed_Asm_32: {
6209 // Shuffle the operands around so the lane index operand is in the
6212 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6213 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6214 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6216 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6218 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6219 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6220 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6221 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6222 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6223 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6225 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6227 TmpInst.addOperand(Inst.getOperand(1)); // lane
6228 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6229 TmpInst.addOperand(Inst.getOperand(5));
6234 case ARM::VLD4LNdWB_fixed_Asm_8:
6235 case ARM::VLD4LNdWB_fixed_Asm_16:
6236 case ARM::VLD4LNdWB_fixed_Asm_32:
6237 case ARM::VLD4LNqWB_fixed_Asm_16:
6238 case ARM::VLD4LNqWB_fixed_Asm_32: {
6240 // Shuffle the operands around so the lane index operand is in the
6243 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6244 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6245 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6247 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6249 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6251 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6252 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6253 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6254 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6255 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6256 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6258 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6260 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6262 TmpInst.addOperand(Inst.getOperand(1)); // lane
6263 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6264 TmpInst.addOperand(Inst.getOperand(5));
6269 case ARM::VLD1LNdAsm_8:
6270 case ARM::VLD1LNdAsm_16:
6271 case ARM::VLD1LNdAsm_32: {
6273 // Shuffle the operands around so the lane index operand is in the
6276 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6277 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6278 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6279 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6280 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6281 TmpInst.addOperand(Inst.getOperand(1)); // lane
6282 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6283 TmpInst.addOperand(Inst.getOperand(5));
6288 case ARM::VLD2LNdAsm_8:
6289 case ARM::VLD2LNdAsm_16:
6290 case ARM::VLD2LNdAsm_32:
6291 case ARM::VLD2LNqAsm_16:
6292 case ARM::VLD2LNqAsm_32: {
6294 // Shuffle the operands around so the lane index operand is in the
6297 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6298 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6299 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6301 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6302 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6303 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6304 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6306 TmpInst.addOperand(Inst.getOperand(1)); // lane
6307 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6308 TmpInst.addOperand(Inst.getOperand(5));
6313 case ARM::VLD3LNdAsm_8:
6314 case ARM::VLD3LNdAsm_16:
6315 case ARM::VLD3LNdAsm_32:
6316 case ARM::VLD3LNqAsm_16:
6317 case ARM::VLD3LNqAsm_32: {
6319 // Shuffle the operands around so the lane index operand is in the
6322 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6323 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6324 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6326 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6328 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6329 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6330 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6331 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6333 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6335 TmpInst.addOperand(Inst.getOperand(1)); // lane
6336 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6337 TmpInst.addOperand(Inst.getOperand(5));
6342 case ARM::VLD4LNdAsm_8:
6343 case ARM::VLD4LNdAsm_16:
6344 case ARM::VLD4LNdAsm_32:
6345 case ARM::VLD4LNqAsm_16:
6346 case ARM::VLD4LNqAsm_32: {
6348 // Shuffle the operands around so the lane index operand is in the
6351 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6352 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6353 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6355 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6357 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6359 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6360 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6361 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6362 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6364 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6366 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6368 TmpInst.addOperand(Inst.getOperand(1)); // lane
6369 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6370 TmpInst.addOperand(Inst.getOperand(5));
6375 // VLD3DUP single 3-element structure to all lanes instructions.
6376 case ARM::VLD3DUPdAsm_8:
6377 case ARM::VLD3DUPdAsm_16:
6378 case ARM::VLD3DUPdAsm_32:
6379 case ARM::VLD3DUPqAsm_8:
6380 case ARM::VLD3DUPqAsm_16:
6381 case ARM::VLD3DUPqAsm_32: {
6384 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6385 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6386 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6388 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6390 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6391 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6392 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6393 TmpInst.addOperand(Inst.getOperand(4));
6398 case ARM::VLD3DUPdWB_fixed_Asm_8:
6399 case ARM::VLD3DUPdWB_fixed_Asm_16:
6400 case ARM::VLD3DUPdWB_fixed_Asm_32:
6401 case ARM::VLD3DUPqWB_fixed_Asm_8:
6402 case ARM::VLD3DUPqWB_fixed_Asm_16:
6403 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6406 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6407 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6408 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6410 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6412 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6413 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6414 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6415 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6416 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6417 TmpInst.addOperand(Inst.getOperand(4));
6422 case ARM::VLD3DUPdWB_register_Asm_8:
6423 case ARM::VLD3DUPdWB_register_Asm_16:
6424 case ARM::VLD3DUPdWB_register_Asm_32:
6425 case ARM::VLD3DUPqWB_register_Asm_8:
6426 case ARM::VLD3DUPqWB_register_Asm_16:
6427 case ARM::VLD3DUPqWB_register_Asm_32: {
6430 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6431 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6432 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6434 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6436 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6437 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6438 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6439 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6440 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6441 TmpInst.addOperand(Inst.getOperand(5));
6446 // VLD3 multiple 3-element structure instructions.
6447 case ARM::VLD3dAsm_8:
6448 case ARM::VLD3dAsm_16:
6449 case ARM::VLD3dAsm_32:
6450 case ARM::VLD3qAsm_8:
6451 case ARM::VLD3qAsm_16:
6452 case ARM::VLD3qAsm_32: {
6455 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6456 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6457 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6459 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6461 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6462 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6463 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6464 TmpInst.addOperand(Inst.getOperand(4));
6469 case ARM::VLD3dWB_fixed_Asm_8:
6470 case ARM::VLD3dWB_fixed_Asm_16:
6471 case ARM::VLD3dWB_fixed_Asm_32:
6472 case ARM::VLD3qWB_fixed_Asm_8:
6473 case ARM::VLD3qWB_fixed_Asm_16:
6474 case ARM::VLD3qWB_fixed_Asm_32: {
6477 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6478 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6479 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6481 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6483 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6484 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6485 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6486 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6487 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6488 TmpInst.addOperand(Inst.getOperand(4));
6493 case ARM::VLD3dWB_register_Asm_8:
6494 case ARM::VLD3dWB_register_Asm_16:
6495 case ARM::VLD3dWB_register_Asm_32:
6496 case ARM::VLD3qWB_register_Asm_8:
6497 case ARM::VLD3qWB_register_Asm_16:
6498 case ARM::VLD3qWB_register_Asm_32: {
6501 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6502 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6503 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6505 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6507 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6508 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6509 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6510 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6511 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6512 TmpInst.addOperand(Inst.getOperand(5));
6517 // VLD4DUP single 3-element structure to all lanes instructions.
6518 case ARM::VLD4DUPdAsm_8:
6519 case ARM::VLD4DUPdAsm_16:
6520 case ARM::VLD4DUPdAsm_32:
6521 case ARM::VLD4DUPqAsm_8:
6522 case ARM::VLD4DUPqAsm_16:
6523 case ARM::VLD4DUPqAsm_32: {
6526 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6527 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6528 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6530 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6532 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6534 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6535 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6536 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6537 TmpInst.addOperand(Inst.getOperand(4));
6542 case ARM::VLD4DUPdWB_fixed_Asm_8:
6543 case ARM::VLD4DUPdWB_fixed_Asm_16:
6544 case ARM::VLD4DUPdWB_fixed_Asm_32:
6545 case ARM::VLD4DUPqWB_fixed_Asm_8:
6546 case ARM::VLD4DUPqWB_fixed_Asm_16:
6547 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6550 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6551 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6552 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6554 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6556 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6558 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6559 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6560 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6561 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6562 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6563 TmpInst.addOperand(Inst.getOperand(4));
6568 case ARM::VLD4DUPdWB_register_Asm_8:
6569 case ARM::VLD4DUPdWB_register_Asm_16:
6570 case ARM::VLD4DUPdWB_register_Asm_32:
6571 case ARM::VLD4DUPqWB_register_Asm_8:
6572 case ARM::VLD4DUPqWB_register_Asm_16:
6573 case ARM::VLD4DUPqWB_register_Asm_32: {
6576 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6577 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6578 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6580 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6582 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6584 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6585 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6586 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6587 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6588 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6589 TmpInst.addOperand(Inst.getOperand(5));
6594 // VLD4 multiple 4-element structure instructions.
6595 case ARM::VLD4dAsm_8:
6596 case ARM::VLD4dAsm_16:
6597 case ARM::VLD4dAsm_32:
6598 case ARM::VLD4qAsm_8:
6599 case ARM::VLD4qAsm_16:
6600 case ARM::VLD4qAsm_32: {
6603 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6604 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6605 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6607 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6609 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6611 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6612 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6613 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6614 TmpInst.addOperand(Inst.getOperand(4));
6619 case ARM::VLD4dWB_fixed_Asm_8:
6620 case ARM::VLD4dWB_fixed_Asm_16:
6621 case ARM::VLD4dWB_fixed_Asm_32:
6622 case ARM::VLD4qWB_fixed_Asm_8:
6623 case ARM::VLD4qWB_fixed_Asm_16:
6624 case ARM::VLD4qWB_fixed_Asm_32: {
6627 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6628 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6629 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6631 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6633 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6635 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6636 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6637 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6638 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6639 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6640 TmpInst.addOperand(Inst.getOperand(4));
6645 case ARM::VLD4dWB_register_Asm_8:
6646 case ARM::VLD4dWB_register_Asm_16:
6647 case ARM::VLD4dWB_register_Asm_32:
6648 case ARM::VLD4qWB_register_Asm_8:
6649 case ARM::VLD4qWB_register_Asm_16:
6650 case ARM::VLD4qWB_register_Asm_32: {
6653 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6654 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6655 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6657 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6659 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6661 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6662 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6663 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6664 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6665 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6666 TmpInst.addOperand(Inst.getOperand(5));
6671 // VST3 multiple 3-element structure instructions.
6672 case ARM::VST3dAsm_8:
6673 case ARM::VST3dAsm_16:
6674 case ARM::VST3dAsm_32:
6675 case ARM::VST3qAsm_8:
6676 case ARM::VST3qAsm_16:
6677 case ARM::VST3qAsm_32: {
6680 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6681 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6682 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6683 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6684 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6686 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6688 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6689 TmpInst.addOperand(Inst.getOperand(4));
6694 case ARM::VST3dWB_fixed_Asm_8:
6695 case ARM::VST3dWB_fixed_Asm_16:
6696 case ARM::VST3dWB_fixed_Asm_32:
6697 case ARM::VST3qWB_fixed_Asm_8:
6698 case ARM::VST3qWB_fixed_Asm_16:
6699 case ARM::VST3qWB_fixed_Asm_32: {
6702 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6703 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6704 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6705 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6706 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6707 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6708 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6710 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6712 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6713 TmpInst.addOperand(Inst.getOperand(4));
6718 case ARM::VST3dWB_register_Asm_8:
6719 case ARM::VST3dWB_register_Asm_16:
6720 case ARM::VST3dWB_register_Asm_32:
6721 case ARM::VST3qWB_register_Asm_8:
6722 case ARM::VST3qWB_register_Asm_16:
6723 case ARM::VST3qWB_register_Asm_32: {
6726 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6727 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6728 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6729 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6730 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6731 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6732 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6734 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6736 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6737 TmpInst.addOperand(Inst.getOperand(5));
6742 // VST4 multiple 3-element structure instructions.
6743 case ARM::VST4dAsm_8:
6744 case ARM::VST4dAsm_16:
6745 case ARM::VST4dAsm_32:
6746 case ARM::VST4qAsm_8:
6747 case ARM::VST4qAsm_16:
6748 case ARM::VST4qAsm_32: {
6751 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6752 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6753 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6754 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6755 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6757 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6759 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6761 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6762 TmpInst.addOperand(Inst.getOperand(4));
6767 case ARM::VST4dWB_fixed_Asm_8:
6768 case ARM::VST4dWB_fixed_Asm_16:
6769 case ARM::VST4dWB_fixed_Asm_32:
6770 case ARM::VST4qWB_fixed_Asm_8:
6771 case ARM::VST4qWB_fixed_Asm_16:
6772 case ARM::VST4qWB_fixed_Asm_32: {
6775 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6776 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6777 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6778 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6779 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6780 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6781 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6783 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6785 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6787 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6788 TmpInst.addOperand(Inst.getOperand(4));
6793 case ARM::VST4dWB_register_Asm_8:
6794 case ARM::VST4dWB_register_Asm_16:
6795 case ARM::VST4dWB_register_Asm_32:
6796 case ARM::VST4qWB_register_Asm_8:
6797 case ARM::VST4qWB_register_Asm_16:
6798 case ARM::VST4qWB_register_Asm_32: {
6801 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6802 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6803 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6804 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6805 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6806 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6807 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6809 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6811 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6813 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6814 TmpInst.addOperand(Inst.getOperand(5));
6819 // Handle encoding choice for the shift-immediate instructions.
6822 case ARM::t2ASRri: {
6823 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6824 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6825 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
6826 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
6827 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
6829 switch (Inst.getOpcode()) {
6830 default: llvm_unreachable("unexpected opcode");
6831 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
6832 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
6833 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
6835 // The Thumb1 operands aren't in the same order. Awesome, eh?
6837 TmpInst.setOpcode(NewOpc);
6838 TmpInst.addOperand(Inst.getOperand(0));
6839 TmpInst.addOperand(Inst.getOperand(5));
6840 TmpInst.addOperand(Inst.getOperand(1));
6841 TmpInst.addOperand(Inst.getOperand(2));
6842 TmpInst.addOperand(Inst.getOperand(3));
6843 TmpInst.addOperand(Inst.getOperand(4));
6850 // Handle the Thumb2 mode MOV complex aliases.
6852 case ARM::t2MOVSsr: {
6853 // Which instruction to expand to depends on the CCOut operand and
6854 // whether we're in an IT block if the register operands are low
6856 bool isNarrow = false;
6857 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6858 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6859 isARMLowRegister(Inst.getOperand(2).getReg()) &&
6860 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
6861 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
6865 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
6866 default: llvm_unreachable("unexpected opcode!");
6867 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
6868 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
6869 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
6870 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
6872 TmpInst.setOpcode(newOpc);
6873 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6875 TmpInst.addOperand(MCOperand::CreateReg(
6876 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6877 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6878 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6879 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6880 TmpInst.addOperand(Inst.getOperand(5));
6882 TmpInst.addOperand(MCOperand::CreateReg(
6883 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
6888 case ARM::t2MOVSsi: {
6889 // Which instruction to expand to depends on the CCOut operand and
6890 // whether we're in an IT block if the register operands are low
6892 bool isNarrow = false;
6893 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
6894 isARMLowRegister(Inst.getOperand(1).getReg()) &&
6895 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
6899 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
6900 default: llvm_unreachable("unexpected opcode!");
6901 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
6902 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
6903 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
6904 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
6905 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
6907 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6908 if (Amount == 32) Amount = 0;
6909 TmpInst.setOpcode(newOpc);
6910 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6912 TmpInst.addOperand(MCOperand::CreateReg(
6913 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6914 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6915 if (newOpc != ARM::t2RRX)
6916 TmpInst.addOperand(MCOperand::CreateImm(Amount));
6917 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6918 TmpInst.addOperand(Inst.getOperand(4));
6920 TmpInst.addOperand(MCOperand::CreateReg(
6921 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
6925 // Handle the ARM mode MOV complex aliases.
6930 ARM_AM::ShiftOpc ShiftTy;
6931 switch(Inst.getOpcode()) {
6932 default: llvm_unreachable("unexpected opcode!");
6933 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
6934 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
6935 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
6936 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
6938 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
6940 TmpInst.setOpcode(ARM::MOVsr);
6941 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6942 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6943 TmpInst.addOperand(Inst.getOperand(2)); // Rm
6944 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6945 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6946 TmpInst.addOperand(Inst.getOperand(4));
6947 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6955 ARM_AM::ShiftOpc ShiftTy;
6956 switch(Inst.getOpcode()) {
6957 default: llvm_unreachable("unexpected opcode!");
6958 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
6959 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
6960 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
6961 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
6963 // A shift by zero is a plain MOVr, not a MOVsi.
6964 unsigned Amt = Inst.getOperand(2).getImm();
6965 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
6966 // A shift by 32 should be encoded as 0 when permitted
6967 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
6969 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
6971 TmpInst.setOpcode(Opc);
6972 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6973 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6974 if (Opc == ARM::MOVsi)
6975 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6976 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6977 TmpInst.addOperand(Inst.getOperand(4));
6978 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
6983 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
6985 TmpInst.setOpcode(ARM::MOVsi);
6986 TmpInst.addOperand(Inst.getOperand(0)); // Rd
6987 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6988 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
6989 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
6990 TmpInst.addOperand(Inst.getOperand(3));
6991 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
6995 case ARM::t2LDMIA_UPD: {
6996 // If this is a load of a single register, then we should use
6997 // a post-indexed LDR instruction instead, per the ARM ARM.
6998 if (Inst.getNumOperands() != 5)
7001 TmpInst.setOpcode(ARM::t2LDR_POST);
7002 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7003 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7004 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7005 TmpInst.addOperand(MCOperand::CreateImm(4));
7006 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7007 TmpInst.addOperand(Inst.getOperand(3));
7011 case ARM::t2STMDB_UPD: {
7012 // If this is a store of a single register, then we should use
7013 // a pre-indexed STR instruction instead, per the ARM ARM.
7014 if (Inst.getNumOperands() != 5)
7017 TmpInst.setOpcode(ARM::t2STR_PRE);
7018 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7019 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7020 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7021 TmpInst.addOperand(MCOperand::CreateImm(-4));
7022 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7023 TmpInst.addOperand(Inst.getOperand(3));
7027 case ARM::LDMIA_UPD:
7028 // If this is a load of a single register via a 'pop', then we should use
7029 // a post-indexed LDR instruction instead, per the ARM ARM.
7030 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7031 Inst.getNumOperands() == 5) {
7033 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7034 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7035 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7036 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7037 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7038 TmpInst.addOperand(MCOperand::CreateImm(4));
7039 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7040 TmpInst.addOperand(Inst.getOperand(3));
7045 case ARM::STMDB_UPD:
7046 // If this is a store of a single register via a 'push', then we should use
7047 // a pre-indexed STR instruction instead, per the ARM ARM.
7048 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7049 Inst.getNumOperands() == 5) {
7051 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7052 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7053 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7054 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7055 TmpInst.addOperand(MCOperand::CreateImm(-4));
7056 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7057 TmpInst.addOperand(Inst.getOperand(3));
7061 case ARM::t2ADDri12:
7062 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7063 // mnemonic was used (not "addw"), encoding T3 is preferred.
7064 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7065 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7067 Inst.setOpcode(ARM::t2ADDri);
7068 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7070 case ARM::t2SUBri12:
7071 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7072 // mnemonic was used (not "subw"), encoding T3 is preferred.
7073 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7074 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7076 Inst.setOpcode(ARM::t2SUBri);
7077 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7080 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7081 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7082 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7083 // to encoding T1 if <Rd> is omitted."
7084 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7085 Inst.setOpcode(ARM::tADDi3);
7090 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7091 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7092 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7093 // to encoding T1 if <Rd> is omitted."
7094 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7095 Inst.setOpcode(ARM::tSUBi3);
7100 case ARM::t2SUBri: {
7101 // If the destination and first source operand are the same, and
7102 // the flags are compatible with the current IT status, use encoding T2
7103 // instead of T3. For compatibility with the system 'as'. Make sure the
7104 // wide encoding wasn't explicit.
7105 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7106 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7107 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7108 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7109 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7110 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7111 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7114 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7115 ARM::tADDi8 : ARM::tSUBi8);
7116 TmpInst.addOperand(Inst.getOperand(0));
7117 TmpInst.addOperand(Inst.getOperand(5));
7118 TmpInst.addOperand(Inst.getOperand(0));
7119 TmpInst.addOperand(Inst.getOperand(2));
7120 TmpInst.addOperand(Inst.getOperand(3));
7121 TmpInst.addOperand(Inst.getOperand(4));
7125 case ARM::t2ADDrr: {
7126 // If the destination and first source operand are the same, and
7127 // there's no setting of the flags, use encoding T2 instead of T3.
7128 // Note that this is only for ADD, not SUB. This mirrors the system
7129 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7130 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7131 Inst.getOperand(5).getReg() != 0 ||
7132 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7133 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7136 TmpInst.setOpcode(ARM::tADDhirr);
7137 TmpInst.addOperand(Inst.getOperand(0));
7138 TmpInst.addOperand(Inst.getOperand(0));
7139 TmpInst.addOperand(Inst.getOperand(2));
7140 TmpInst.addOperand(Inst.getOperand(3));
7141 TmpInst.addOperand(Inst.getOperand(4));
7145 case ARM::tADDrSP: {
7146 // If the non-SP source operand and the destination operand are not the
7147 // same, we need to use the 32-bit encoding if it's available.
7148 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7149 Inst.setOpcode(ARM::t2ADDrr);
7150 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7156 // A Thumb conditional branch outside of an IT block is a tBcc.
7157 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7158 Inst.setOpcode(ARM::tBcc);
7163 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7164 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7165 Inst.setOpcode(ARM::t2Bcc);
7170 // If the conditional is AL or we're in an IT block, we really want t2B.
7171 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7172 Inst.setOpcode(ARM::t2B);
7177 // If the conditional is AL, we really want tB.
7178 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7179 Inst.setOpcode(ARM::tB);
7184 // If the register list contains any high registers, or if the writeback
7185 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7186 // instead if we're in Thumb2. Otherwise, this should have generated
7187 // an error in validateInstruction().
7188 unsigned Rn = Inst.getOperand(0).getReg();
7189 bool hasWritebackToken =
7190 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7191 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7192 bool listContainsBase;
7193 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7194 (!listContainsBase && !hasWritebackToken) ||
7195 (listContainsBase && hasWritebackToken)) {
7196 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7197 assert (isThumbTwo());
7198 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7199 // If we're switching to the updating version, we need to insert
7200 // the writeback tied operand.
7201 if (hasWritebackToken)
7202 Inst.insert(Inst.begin(),
7203 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7208 case ARM::tSTMIA_UPD: {
7209 // If the register list contains any high registers, we need to use
7210 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7211 // should have generated an error in validateInstruction().
7212 unsigned Rn = Inst.getOperand(0).getReg();
7213 bool listContainsBase;
7214 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7215 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7216 assert (isThumbTwo());
7217 Inst.setOpcode(ARM::t2STMIA_UPD);
7223 bool listContainsBase;
7224 // If the register list contains any high registers, we need to use
7225 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7226 // should have generated an error in validateInstruction().
7227 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7229 assert (isThumbTwo());
7230 Inst.setOpcode(ARM::t2LDMIA_UPD);
7231 // Add the base register and writeback operands.
7232 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7233 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7237 bool listContainsBase;
7238 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7240 assert (isThumbTwo());
7241 Inst.setOpcode(ARM::t2STMDB_UPD);
7242 // Add the base register and writeback operands.
7243 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7244 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7248 // If we can use the 16-bit encoding and the user didn't explicitly
7249 // request the 32-bit variant, transform it here.
7250 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7251 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7252 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7253 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7254 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7255 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7256 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7257 // The operands aren't in the same order for tMOVi8...
7259 TmpInst.setOpcode(ARM::tMOVi8);
7260 TmpInst.addOperand(Inst.getOperand(0));
7261 TmpInst.addOperand(Inst.getOperand(4));
7262 TmpInst.addOperand(Inst.getOperand(1));
7263 TmpInst.addOperand(Inst.getOperand(2));
7264 TmpInst.addOperand(Inst.getOperand(3));
7271 // If we can use the 16-bit encoding and the user didn't explicitly
7272 // request the 32-bit variant, transform it here.
7273 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7274 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7275 Inst.getOperand(2).getImm() == ARMCC::AL &&
7276 Inst.getOperand(4).getReg() == ARM::CPSR &&
7277 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7278 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7279 // The operands aren't the same for tMOV[S]r... (no cc_out)
7281 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7282 TmpInst.addOperand(Inst.getOperand(0));
7283 TmpInst.addOperand(Inst.getOperand(1));
7284 TmpInst.addOperand(Inst.getOperand(2));
7285 TmpInst.addOperand(Inst.getOperand(3));
7295 // If we can use the 16-bit encoding and the user didn't explicitly
7296 // request the 32-bit variant, transform it here.
7297 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7298 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7299 Inst.getOperand(2).getImm() == 0 &&
7300 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7301 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7303 switch (Inst.getOpcode()) {
7304 default: llvm_unreachable("Illegal opcode!");
7305 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7306 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7307 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7308 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7310 // The operands aren't the same for thumb1 (no rotate operand).
7312 TmpInst.setOpcode(NewOpc);
7313 TmpInst.addOperand(Inst.getOperand(0));
7314 TmpInst.addOperand(Inst.getOperand(1));
7315 TmpInst.addOperand(Inst.getOperand(3));
7316 TmpInst.addOperand(Inst.getOperand(4));
7323 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7324 // rrx shifts and asr/lsr of #32 is encoded as 0
7325 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7327 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7328 // Shifting by zero is accepted as a vanilla 'MOVr'
7330 TmpInst.setOpcode(ARM::MOVr);
7331 TmpInst.addOperand(Inst.getOperand(0));
7332 TmpInst.addOperand(Inst.getOperand(1));
7333 TmpInst.addOperand(Inst.getOperand(3));
7334 TmpInst.addOperand(Inst.getOperand(4));
7335 TmpInst.addOperand(Inst.getOperand(5));
7348 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7349 if (SOpc == ARM_AM::rrx) return false;
7350 switch (Inst.getOpcode()) {
7351 default: llvm_unreachable("unexpected opcode!");
7352 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7353 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7354 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7355 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7356 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7357 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7359 // If the shift is by zero, use the non-shifted instruction definition.
7360 // The exception is for right shifts, where 0 == 32
7361 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7362 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7364 TmpInst.setOpcode(newOpc);
7365 TmpInst.addOperand(Inst.getOperand(0));
7366 TmpInst.addOperand(Inst.getOperand(1));
7367 TmpInst.addOperand(Inst.getOperand(2));
7368 TmpInst.addOperand(Inst.getOperand(4));
7369 TmpInst.addOperand(Inst.getOperand(5));
7370 TmpInst.addOperand(Inst.getOperand(6));
7378 // The mask bits for all but the first condition are represented as
7379 // the low bit of the condition code value implies 't'. We currently
7380 // always have 1 implies 't', so XOR toggle the bits if the low bit
7381 // of the condition code is zero.
7382 MCOperand &MO = Inst.getOperand(1);
7383 unsigned Mask = MO.getImm();
7384 unsigned OrigMask = Mask;
7385 unsigned TZ = CountTrailingZeros_32(Mask);
7386 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7387 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7388 for (unsigned i = 3; i != TZ; --i)
7393 // Set up the IT block state according to the IT instruction we just
7395 assert(!inITBlock() && "nested IT blocks?!");
7396 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7397 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7398 ITState.CurPosition = 0;
7399 ITState.FirstCond = true;
7409 // Assemblers should use the narrow encodings of these instructions when permissible.
7410 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7411 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7412 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7413 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7414 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7415 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7416 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7418 switch (Inst.getOpcode()) {
7419 default: llvm_unreachable("unexpected opcode");
7420 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7421 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7422 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7423 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7424 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7425 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7428 TmpInst.setOpcode(NewOpc);
7429 TmpInst.addOperand(Inst.getOperand(0));
7430 TmpInst.addOperand(Inst.getOperand(5));
7431 TmpInst.addOperand(Inst.getOperand(1));
7432 TmpInst.addOperand(Inst.getOperand(2));
7433 TmpInst.addOperand(Inst.getOperand(3));
7434 TmpInst.addOperand(Inst.getOperand(4));
7445 // Assemblers should use the narrow encodings of these instructions when permissible.
7446 // These instructions are special in that they are commutable, so shorter encodings
7447 // are available more often.
7448 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7449 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7450 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7451 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7452 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7453 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7454 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7455 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7457 switch (Inst.getOpcode()) {
7458 default: llvm_unreachable("unexpected opcode");
7459 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7460 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7461 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7462 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7465 TmpInst.setOpcode(NewOpc);
7466 TmpInst.addOperand(Inst.getOperand(0));
7467 TmpInst.addOperand(Inst.getOperand(5));
7468 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7469 TmpInst.addOperand(Inst.getOperand(1));
7470 TmpInst.addOperand(Inst.getOperand(2));
7472 TmpInst.addOperand(Inst.getOperand(2));
7473 TmpInst.addOperand(Inst.getOperand(1));
7475 TmpInst.addOperand(Inst.getOperand(3));
7476 TmpInst.addOperand(Inst.getOperand(4));
7486 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7487 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7488 // suffix depending on whether they're in an IT block or not.
7489 unsigned Opc = Inst.getOpcode();
7490 const MCInstrDesc &MCID = getInstDesc(Opc);
7491 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7492 assert(MCID.hasOptionalDef() &&
7493 "optionally flag setting instruction missing optional def operand");
7494 assert(MCID.NumOperands == Inst.getNumOperands() &&
7495 "operand count mismatch!");
7496 // Find the optional-def operand (cc_out).
7499 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7502 // If we're parsing Thumb1, reject it completely.
7503 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7504 return Match_MnemonicFail;
7505 // If we're parsing Thumb2, which form is legal depends on whether we're
7507 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7509 return Match_RequiresITBlock;
7510 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7512 return Match_RequiresNotITBlock;
7514 // Some high-register supporting Thumb1 encodings only allow both registers
7515 // to be from r0-r7 when in Thumb2.
7516 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7517 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7518 isARMLowRegister(Inst.getOperand(2).getReg()))
7519 return Match_RequiresThumb2;
7520 // Others only require ARMv6 or later.
7521 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7522 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7523 isARMLowRegister(Inst.getOperand(1).getReg()))
7524 return Match_RequiresV6;
7525 return Match_Success;
7528 static const char *getSubtargetFeatureName(unsigned Val);
7530 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7531 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7532 MCStreamer &Out, unsigned &ErrorInfo,
7533 bool MatchingInlineAsm) {
7535 unsigned MatchResult;
7537 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7539 switch (MatchResult) {
7542 // Context sensitive operand constraints aren't handled by the matcher,
7543 // so check them here.
7544 if (validateInstruction(Inst, Operands)) {
7545 // Still progress the IT block, otherwise one wrong condition causes
7546 // nasty cascading errors.
7547 forwardITPosition();
7551 // Some instructions need post-processing to, for example, tweak which
7552 // encoding is selected. Loop on it while changes happen so the
7553 // individual transformations can chain off each other. E.g.,
7554 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7555 while (processInstruction(Inst, Operands))
7558 // Only move forward at the very end so that everything in validate
7559 // and process gets a consistent answer about whether we're in an IT
7561 forwardITPosition();
7563 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7564 // doesn't actually encode.
7565 if (Inst.getOpcode() == ARM::ITasm)
7569 Out.EmitInstruction(Inst);
7571 case Match_MissingFeature: {
7572 assert(ErrorInfo && "Unknown missing feature!");
7573 // Special case the error message for the very common case where only
7574 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7575 std::string Msg = "instruction requires:";
7577 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7578 if (ErrorInfo & Mask) {
7580 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7584 return Error(IDLoc, Msg);
7586 case Match_InvalidOperand: {
7587 SMLoc ErrorLoc = IDLoc;
7588 if (ErrorInfo != ~0U) {
7589 if (ErrorInfo >= Operands.size())
7590 return Error(IDLoc, "too few operands for instruction");
7592 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7593 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7596 return Error(ErrorLoc, "invalid operand for instruction");
7598 case Match_MnemonicFail:
7599 return Error(IDLoc, "invalid instruction",
7600 ((ARMOperand*)Operands[0])->getLocRange());
7601 case Match_RequiresNotITBlock:
7602 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7603 case Match_RequiresITBlock:
7604 return Error(IDLoc, "instruction only valid inside IT block");
7605 case Match_RequiresV6:
7606 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7607 case Match_RequiresThumb2:
7608 return Error(IDLoc, "instruction variant requires Thumb2");
7609 case Match_ImmRange0_15: {
7610 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7611 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7612 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7616 llvm_unreachable("Implement any new match types added!");
7619 /// parseDirective parses the arm specific directives
7620 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7621 StringRef IDVal = DirectiveID.getIdentifier();
7622 if (IDVal == ".word")
7623 return parseDirectiveWord(4, DirectiveID.getLoc());
7624 else if (IDVal == ".thumb")
7625 return parseDirectiveThumb(DirectiveID.getLoc());
7626 else if (IDVal == ".arm")
7627 return parseDirectiveARM(DirectiveID.getLoc());
7628 else if (IDVal == ".thumb_func")
7629 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7630 else if (IDVal == ".code")
7631 return parseDirectiveCode(DirectiveID.getLoc());
7632 else if (IDVal == ".syntax")
7633 return parseDirectiveSyntax(DirectiveID.getLoc());
7634 else if (IDVal == ".unreq")
7635 return parseDirectiveUnreq(DirectiveID.getLoc());
7636 else if (IDVal == ".arch")
7637 return parseDirectiveArch(DirectiveID.getLoc());
7638 else if (IDVal == ".eabi_attribute")
7639 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7643 /// parseDirectiveWord
7644 /// ::= .word [ expression (, expression)* ]
7645 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
7646 if (getLexer().isNot(AsmToken::EndOfStatement)) {
7648 const MCExpr *Value;
7649 if (getParser().ParseExpression(Value))
7652 getParser().getStreamer().EmitValue(Value, Size);
7654 if (getLexer().is(AsmToken::EndOfStatement))
7657 // FIXME: Improve diagnostic.
7658 if (getLexer().isNot(AsmToken::Comma))
7659 return Error(L, "unexpected token in directive");
7668 /// parseDirectiveThumb
7670 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
7671 if (getLexer().isNot(AsmToken::EndOfStatement))
7672 return Error(L, "unexpected token in directive");
7677 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7681 /// parseDirectiveARM
7683 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
7684 if (getLexer().isNot(AsmToken::EndOfStatement))
7685 return Error(L, "unexpected token in directive");
7690 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7694 /// parseDirectiveThumbFunc
7695 /// ::= .thumbfunc symbol_name
7696 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
7697 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
7698 bool isMachO = MAI.hasSubsectionsViaSymbols();
7700 bool needFuncName = true;
7702 // Darwin asm has (optionally) function name after .thumb_func direction
7705 const AsmToken &Tok = Parser.getTok();
7706 if (Tok.isNot(AsmToken::EndOfStatement)) {
7707 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
7708 return Error(L, "unexpected token in .thumb_func directive");
7709 Name = Tok.getIdentifier();
7710 Parser.Lex(); // Consume the identifier token.
7711 needFuncName = false;
7715 if (getLexer().isNot(AsmToken::EndOfStatement))
7716 return Error(L, "unexpected token in directive");
7718 // Eat the end of statement and any blank lines that follow.
7719 while (getLexer().is(AsmToken::EndOfStatement))
7722 // FIXME: assuming function name will be the line following .thumb_func
7723 // We really should be checking the next symbol definition even if there's
7724 // stuff in between.
7726 Name = Parser.getTok().getIdentifier();
7729 // Mark symbol as a thumb symbol.
7730 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
7731 getParser().getStreamer().EmitThumbFunc(Func);
7735 /// parseDirectiveSyntax
7736 /// ::= .syntax unified | divided
7737 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
7738 const AsmToken &Tok = Parser.getTok();
7739 if (Tok.isNot(AsmToken::Identifier))
7740 return Error(L, "unexpected token in .syntax directive");
7741 StringRef Mode = Tok.getString();
7742 if (Mode == "unified" || Mode == "UNIFIED")
7744 else if (Mode == "divided" || Mode == "DIVIDED")
7745 return Error(L, "'.syntax divided' arm asssembly not supported");
7747 return Error(L, "unrecognized syntax mode in .syntax directive");
7749 if (getLexer().isNot(AsmToken::EndOfStatement))
7750 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7753 // TODO tell the MC streamer the mode
7754 // getParser().getStreamer().Emit???();
7758 /// parseDirectiveCode
7759 /// ::= .code 16 | 32
7760 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
7761 const AsmToken &Tok = Parser.getTok();
7762 if (Tok.isNot(AsmToken::Integer))
7763 return Error(L, "unexpected token in .code directive");
7764 int64_t Val = Parser.getTok().getIntVal();
7770 return Error(L, "invalid operand to .code directive");
7772 if (getLexer().isNot(AsmToken::EndOfStatement))
7773 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
7779 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
7783 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
7789 /// parseDirectiveReq
7790 /// ::= name .req registername
7791 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
7792 Parser.Lex(); // Eat the '.req' token.
7794 SMLoc SRegLoc, ERegLoc;
7795 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
7796 Parser.EatToEndOfStatement();
7797 return Error(SRegLoc, "register name expected");
7800 // Shouldn't be anything else.
7801 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
7802 Parser.EatToEndOfStatement();
7803 return Error(Parser.getTok().getLoc(),
7804 "unexpected input in .req directive.");
7807 Parser.Lex(); // Consume the EndOfStatement
7809 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg)
7810 return Error(SRegLoc, "redefinition of '" + Name +
7811 "' does not match original.");
7816 /// parseDirectiveUneq
7817 /// ::= .unreq registername
7818 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
7819 if (Parser.getTok().isNot(AsmToken::Identifier)) {
7820 Parser.EatToEndOfStatement();
7821 return Error(L, "unexpected input in .unreq directive.");
7823 RegisterReqs.erase(Parser.getTok().getIdentifier());
7824 Parser.Lex(); // Eat the identifier.
7828 /// parseDirectiveArch
7830 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
7834 /// parseDirectiveEabiAttr
7835 /// ::= .eabi_attribute int, int
7836 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
7840 /// Force static initialization.
7841 extern "C" void LLVMInitializeARMAsmParser() {
7842 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
7843 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
7846 #define GET_REGISTER_MATCHER
7847 #define GET_SUBTARGET_FEATURE_NAME
7848 #define GET_MATCHER_IMPLEMENTATION
7849 #include "ARMGenAsmMatcher.inc"