1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFPUName.h"
11 #include "ARMFeatures.h"
12 #include "MCTargetDesc/ARMAddressingModes.h"
13 #include "MCTargetDesc/ARMArchName.h"
14 #include "MCTargetDesc/ARMBaseInfo.h"
15 #include "MCTargetDesc/ARMMCExpr.h"
16 #include "llvm/ADT/BitVector.h"
17 #include "llvm/ADT/MapVector.h"
18 #include "llvm/ADT/OwningPtr.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/MC/MCAsmInfo.h"
25 #include "llvm/MC/MCAssembler.h"
26 #include "llvm/MC/MCContext.h"
27 #include "llvm/MC/MCDisassembler.h"
28 #include "llvm/MC/MCELFStreamer.h"
29 #include "llvm/MC/MCExpr.h"
30 #include "llvm/MC/MCInst.h"
31 #include "llvm/MC/MCInstrDesc.h"
32 #include "llvm/MC/MCInstrInfo.h"
33 #include "llvm/MC/MCParser/MCAsmLexer.h"
34 #include "llvm/MC/MCParser/MCAsmParser.h"
35 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
36 #include "llvm/MC/MCRegisterInfo.h"
37 #include "llvm/MC/MCSection.h"
38 #include "llvm/MC/MCStreamer.h"
39 #include "llvm/MC/MCSubtargetInfo.h"
40 #include "llvm/MC/MCSymbol.h"
41 #include "llvm/MC/MCTargetAsmParser.h"
42 #include "llvm/Support/ARMBuildAttributes.h"
43 #include "llvm/Support/ARMEHABI.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/SourceMgr.h"
48 #include "llvm/Support/TargetRegistry.h"
49 #include "llvm/Support/raw_ostream.h"
57 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
62 typedef SmallVector<SMLoc, 4> Locs;
67 Locs PersonalityIndexLocs;
72 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
74 bool hasFnStart() const { return !FnStartLocs.empty(); }
75 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
76 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
77 bool hasPersonality() const {
78 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
81 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
82 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
83 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
84 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
85 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
87 void saveFPReg(int Reg) { FPReg = Reg; }
88 int getFPReg() const { return FPReg; }
90 void emitFnStartLocNotes() const {
91 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
93 Parser.Note(*FI, ".fnstart was specified here");
95 void emitCantUnwindLocNotes() const {
96 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
97 UE = CantUnwindLocs.end(); UI != UE; ++UI)
98 Parser.Note(*UI, ".cantunwind was specified here");
100 void emitHandlerDataLocNotes() const {
101 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
102 HE = HandlerDataLocs.end(); HI != HE; ++HI)
103 Parser.Note(*HI, ".handlerdata was specified here");
105 void emitPersonalityLocNotes() const {
106 for (Locs::const_iterator PI = PersonalityLocs.begin(),
107 PE = PersonalityLocs.end(),
108 PII = PersonalityIndexLocs.begin(),
109 PIE = PersonalityIndexLocs.end();
110 PI != PE || PII != PIE;) {
111 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
112 Parser.Note(*PI++, ".personality was specified here");
113 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
114 Parser.Note(*PII++, ".personalityindex was specified here");
116 llvm_unreachable(".personality and .personalityindex cannot be "
117 "at the same location");
122 FnStartLocs = Locs();
123 CantUnwindLocs = Locs();
124 PersonalityLocs = Locs();
125 HandlerDataLocs = Locs();
126 PersonalityIndexLocs = Locs();
131 class ARMAsmParser : public MCTargetAsmParser {
132 MCSubtargetInfo &STI;
134 const MCInstrInfo &MII;
135 const MCRegisterInfo *MRI;
138 ARMTargetStreamer &getTargetStreamer() {
139 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
140 return static_cast<ARMTargetStreamer &>(TS);
143 // Map of register aliases registers via the .req directive.
144 StringMap<unsigned> RegisterReqs;
146 bool NextSymbolIsThumb;
149 ARMCC::CondCodes Cond; // Condition for IT block.
150 unsigned Mask:4; // Condition mask for instructions.
151 // Starting at first 1 (from lsb).
152 // '1' condition as indicated in IT.
153 // '0' inverse of condition (else).
154 // Count of instructions in IT block is
155 // 4 - trailingzeroes(mask)
157 bool FirstCond; // Explicit flag for when we're parsing the
158 // First instruction in the IT block. It's
159 // implied in the mask, so needs special
162 unsigned CurPosition; // Current position in parsing of IT
163 // block. In range [0,3]. Initialized
164 // according to count of instructions in block.
165 // ~0U if no active IT block.
167 bool inITBlock() { return ITState.CurPosition != ~0U;}
168 void forwardITPosition() {
169 if (!inITBlock()) return;
170 // Move to the next instruction in the IT block, if there is one. If not,
171 // mark the block as done.
172 unsigned TZ = countTrailingZeros(ITState.Mask);
173 if (++ITState.CurPosition == 5 - TZ)
174 ITState.CurPosition = ~0U; // Done with the IT block after this.
178 MCAsmParser &getParser() const { return Parser; }
179 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
181 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
182 return Parser.Note(L, Msg, Ranges);
184 bool Warning(SMLoc L, const Twine &Msg,
185 ArrayRef<SMRange> Ranges = None) {
186 return Parser.Warning(L, Msg, Ranges);
188 bool Error(SMLoc L, const Twine &Msg,
189 ArrayRef<SMRange> Ranges = None) {
190 return Parser.Error(L, Msg, Ranges);
193 int tryParseRegister();
194 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
195 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
196 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
197 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
198 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
199 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
200 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
201 unsigned &ShiftAmount);
202 bool parseLiteralValues(unsigned Size, SMLoc L);
203 bool parseDirectiveThumb(SMLoc L);
204 bool parseDirectiveARM(SMLoc L);
205 bool parseDirectiveThumbFunc(SMLoc L);
206 bool parseDirectiveCode(SMLoc L);
207 bool parseDirectiveSyntax(SMLoc L);
208 bool parseDirectiveReq(StringRef Name, SMLoc L);
209 bool parseDirectiveUnreq(SMLoc L);
210 bool parseDirectiveArch(SMLoc L);
211 bool parseDirectiveEabiAttr(SMLoc L);
212 bool parseDirectiveCPU(SMLoc L);
213 bool parseDirectiveFPU(SMLoc L);
214 bool parseDirectiveFnStart(SMLoc L);
215 bool parseDirectiveFnEnd(SMLoc L);
216 bool parseDirectiveCantUnwind(SMLoc L);
217 bool parseDirectivePersonality(SMLoc L);
218 bool parseDirectiveHandlerData(SMLoc L);
219 bool parseDirectiveSetFP(SMLoc L);
220 bool parseDirectivePad(SMLoc L);
221 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
222 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
223 bool parseDirectiveLtorg(SMLoc L);
224 bool parseDirectiveEven(SMLoc L);
225 bool parseDirectivePersonalityIndex(SMLoc L);
226 bool parseDirectiveUnwindRaw(SMLoc L);
227 bool parseDirectiveTLSDescSeq(SMLoc L);
228 bool parseDirectiveMovSP(SMLoc L);
229 bool parseDirectiveObjectArch(SMLoc L);
230 bool parseDirectiveArchExtension(SMLoc L);
232 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
233 bool &CarrySetting, unsigned &ProcessorIMod,
235 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
236 bool &CanAcceptCarrySet,
237 bool &CanAcceptPredicationCode);
239 bool isThumb() const {
240 // FIXME: Can tablegen auto-generate this?
241 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
243 bool isThumbOne() const {
244 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
246 bool isThumbTwo() const {
247 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
249 bool hasThumb() const {
250 return STI.getFeatureBits() & ARM::HasV4TOps;
252 bool hasV6Ops() const {
253 return STI.getFeatureBits() & ARM::HasV6Ops;
255 bool hasV6MOps() const {
256 return STI.getFeatureBits() & ARM::HasV6MOps;
258 bool hasV7Ops() const {
259 return STI.getFeatureBits() & ARM::HasV7Ops;
261 bool hasV8Ops() const {
262 return STI.getFeatureBits() & ARM::HasV8Ops;
264 bool hasARM() const {
265 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
269 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
270 setAvailableFeatures(FB);
272 bool isMClass() const {
273 return STI.getFeatureBits() & ARM::FeatureMClass;
276 /// @name Auto-generated Match Functions
279 #define GET_ASSEMBLER_HEADER
280 #include "ARMGenAsmMatcher.inc"
284 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
285 OperandMatchResultTy parseCoprocNumOperand(
286 SmallVectorImpl<MCParsedAsmOperand*>&);
287 OperandMatchResultTy parseCoprocRegOperand(
288 SmallVectorImpl<MCParsedAsmOperand*>&);
289 OperandMatchResultTy parseCoprocOptionOperand(
290 SmallVectorImpl<MCParsedAsmOperand*>&);
291 OperandMatchResultTy parseMemBarrierOptOperand(
292 SmallVectorImpl<MCParsedAsmOperand*>&);
293 OperandMatchResultTy parseInstSyncBarrierOptOperand(
294 SmallVectorImpl<MCParsedAsmOperand*>&);
295 OperandMatchResultTy parseProcIFlagsOperand(
296 SmallVectorImpl<MCParsedAsmOperand*>&);
297 OperandMatchResultTy parseMSRMaskOperand(
298 SmallVectorImpl<MCParsedAsmOperand*>&);
299 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
300 StringRef Op, int Low, int High);
301 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
302 return parsePKHImm(O, "lsl", 0, 31);
304 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
305 return parsePKHImm(O, "asr", 1, 32);
307 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
308 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
309 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
310 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
311 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
312 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
313 OperandMatchResultTy parseFPImm(SmallVectorImpl<MCParsedAsmOperand*>&);
314 OperandMatchResultTy parseVectorList(SmallVectorImpl<MCParsedAsmOperand*>&);
315 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
318 // Asm Match Converter Methods
319 void cvtThumbMultiply(MCInst &Inst,
320 const SmallVectorImpl<MCParsedAsmOperand*> &);
321 void cvtThumbBranches(MCInst &Inst,
322 const SmallVectorImpl<MCParsedAsmOperand*> &);
324 bool validateInstruction(MCInst &Inst,
325 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
326 bool processInstruction(MCInst &Inst,
327 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
328 bool shouldOmitCCOutOperand(StringRef Mnemonic,
329 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
330 bool shouldOmitPredicateOperand(StringRef Mnemonic,
331 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
333 enum ARMMatchResultTy {
334 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
335 Match_RequiresNotITBlock,
337 Match_RequiresThumb2,
338 #define GET_OPERAND_DIAGNOSTIC_TYPES
339 #include "ARMGenAsmMatcher.inc"
343 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
344 const MCInstrInfo &MII)
345 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(MII), UC(_Parser) {
346 MCAsmParserExtension::Initialize(_Parser);
348 // Cache the MCRegisterInfo.
349 MRI = getContext().getRegisterInfo();
351 // Initialize the set of available features.
352 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
354 // Not in an ITBlock to start with.
355 ITState.CurPosition = ~0U;
357 NextSymbolIsThumb = false;
360 // Implementation of the MCTargetAsmParser interface:
361 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
362 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
364 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
365 bool ParseDirective(AsmToken DirectiveID);
367 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind);
368 unsigned checkTargetMatchPredicate(MCInst &Inst);
370 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
371 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
372 MCStreamer &Out, unsigned &ErrorInfo,
373 bool MatchingInlineAsm);
374 void onLabelParsed(MCSymbol *Symbol);
376 } // end anonymous namespace
380 /// ARMOperand - Instances of this class represent a parsed ARM machine
382 class ARMOperand : public MCParsedAsmOperand {
392 k_InstSyncBarrierOpt,
403 k_VectorListAllLanes,
409 k_BitfieldDescriptor,
413 SMLoc StartLoc, EndLoc;
414 SmallVector<unsigned, 8> Registers;
417 ARMCC::CondCodes Val;
424 struct CoprocOptionOp {
437 ARM_ISB::InstSyncBOpt Val;
441 ARM_PROC::IFlags Val;
457 // A vector register list is a sequential list of 1 to 4 registers.
458 struct VectorListOp {
465 struct VectorIndexOp {
473 /// Combined record for all forms of ARM address expressions.
476 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
478 const MCConstantExpr *OffsetImm; // Offset immediate value
479 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
480 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
481 unsigned ShiftImm; // shift for OffsetReg.
482 unsigned Alignment; // 0 = no alignment specified
483 // n = alignment in bytes (2, 4, 8, 16, or 32)
484 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
487 struct PostIdxRegOp {
490 ARM_AM::ShiftOpc ShiftTy;
494 struct ShifterImmOp {
499 struct RegShiftedRegOp {
500 ARM_AM::ShiftOpc ShiftTy;
506 struct RegShiftedImmOp {
507 ARM_AM::ShiftOpc ShiftTy;
524 struct CoprocOptionOp CoprocOption;
525 struct MBOptOp MBOpt;
526 struct ISBOptOp ISBOpt;
527 struct ITMaskOp ITMask;
528 struct IFlagsOp IFlags;
529 struct MMaskOp MMask;
532 struct VectorListOp VectorList;
533 struct VectorIndexOp VectorIndex;
535 struct MemoryOp Memory;
536 struct PostIdxRegOp PostIdxReg;
537 struct ShifterImmOp ShifterImm;
538 struct RegShiftedRegOp RegShiftedReg;
539 struct RegShiftedImmOp RegShiftedImm;
540 struct RotImmOp RotImm;
541 struct BitfieldOp Bitfield;
544 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
546 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
548 StartLoc = o.StartLoc;
565 case k_DPRRegisterList:
566 case k_SPRRegisterList:
567 Registers = o.Registers;
570 case k_VectorListAllLanes:
571 case k_VectorListIndexed:
572 VectorList = o.VectorList;
579 CoprocOption = o.CoprocOption;
584 case k_MemBarrierOpt:
587 case k_InstSyncBarrierOpt:
592 case k_PostIndexRegister:
593 PostIdxReg = o.PostIdxReg;
601 case k_ShifterImmediate:
602 ShifterImm = o.ShifterImm;
604 case k_ShiftedRegister:
605 RegShiftedReg = o.RegShiftedReg;
607 case k_ShiftedImmediate:
608 RegShiftedImm = o.RegShiftedImm;
610 case k_RotateImmediate:
613 case k_BitfieldDescriptor:
614 Bitfield = o.Bitfield;
617 VectorIndex = o.VectorIndex;
622 /// getStartLoc - Get the location of the first token of this operand.
623 SMLoc getStartLoc() const { return StartLoc; }
624 /// getEndLoc - Get the location of the last token of this operand.
625 SMLoc getEndLoc() const { return EndLoc; }
626 /// getLocRange - Get the range between the first and last token of this
628 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
630 ARMCC::CondCodes getCondCode() const {
631 assert(Kind == k_CondCode && "Invalid access!");
635 unsigned getCoproc() const {
636 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
640 StringRef getToken() const {
641 assert(Kind == k_Token && "Invalid access!");
642 return StringRef(Tok.Data, Tok.Length);
645 unsigned getReg() const {
646 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
650 const SmallVectorImpl<unsigned> &getRegList() const {
651 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
652 Kind == k_SPRRegisterList) && "Invalid access!");
656 const MCExpr *getImm() const {
657 assert(isImm() && "Invalid access!");
661 unsigned getVectorIndex() const {
662 assert(Kind == k_VectorIndex && "Invalid access!");
663 return VectorIndex.Val;
666 ARM_MB::MemBOpt getMemBarrierOpt() const {
667 assert(Kind == k_MemBarrierOpt && "Invalid access!");
671 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
672 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
676 ARM_PROC::IFlags getProcIFlags() const {
677 assert(Kind == k_ProcIFlags && "Invalid access!");
681 unsigned getMSRMask() const {
682 assert(Kind == k_MSRMask && "Invalid access!");
686 bool isCoprocNum() const { return Kind == k_CoprocNum; }
687 bool isCoprocReg() const { return Kind == k_CoprocReg; }
688 bool isCoprocOption() const { return Kind == k_CoprocOption; }
689 bool isCondCode() const { return Kind == k_CondCode; }
690 bool isCCOut() const { return Kind == k_CCOut; }
691 bool isITMask() const { return Kind == k_ITCondMask; }
692 bool isITCondCode() const { return Kind == k_CondCode; }
693 bool isImm() const { return Kind == k_Immediate; }
694 // checks whether this operand is an unsigned offset which fits is a field
695 // of specified width and scaled by a specific number of bits
696 template<unsigned width, unsigned scale>
697 bool isUnsignedOffset() const {
698 if (!isImm()) return false;
699 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
700 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
701 int64_t Val = CE->getValue();
702 int64_t Align = 1LL << scale;
703 int64_t Max = Align * ((1LL << width) - 1);
704 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
708 // checks whether this operand is an signed offset which fits is a field
709 // of specified width and scaled by a specific number of bits
710 template<unsigned width, unsigned scale>
711 bool isSignedOffset() const {
712 if (!isImm()) return false;
713 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
714 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
715 int64_t Val = CE->getValue();
716 int64_t Align = 1LL << scale;
717 int64_t Max = Align * ((1LL << (width-1)) - 1);
718 int64_t Min = -Align * (1LL << (width-1));
719 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
724 // checks whether this operand is a memory operand computed as an offset
725 // applied to PC. the offset may have 8 bits of magnitude and is represented
726 // with two bits of shift. textually it may be either [pc, #imm], #imm or
727 // relocable expression...
728 bool isThumbMemPC() const {
731 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
732 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
733 if (!CE) return false;
734 Val = CE->getValue();
737 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
738 if(Memory.BaseRegNum != ARM::PC) return false;
739 Val = Memory.OffsetImm->getValue();
742 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
744 bool isFPImm() const {
745 if (!isImm()) return false;
746 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
747 if (!CE) return false;
748 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
751 bool isFBits16() const {
752 if (!isImm()) return false;
753 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
754 if (!CE) return false;
755 int64_t Value = CE->getValue();
756 return Value >= 0 && Value <= 16;
758 bool isFBits32() const {
759 if (!isImm()) return false;
760 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
761 if (!CE) return false;
762 int64_t Value = CE->getValue();
763 return Value >= 1 && Value <= 32;
765 bool isImm8s4() const {
766 if (!isImm()) return false;
767 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
768 if (!CE) return false;
769 int64_t Value = CE->getValue();
770 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
772 bool isImm0_1020s4() const {
773 if (!isImm()) return false;
774 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
775 if (!CE) return false;
776 int64_t Value = CE->getValue();
777 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
779 bool isImm0_508s4() const {
780 if (!isImm()) return false;
781 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
782 if (!CE) return false;
783 int64_t Value = CE->getValue();
784 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
786 bool isImm0_508s4Neg() const {
787 if (!isImm()) return false;
788 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
789 if (!CE) return false;
790 int64_t Value = -CE->getValue();
791 // explicitly exclude zero. we want that to use the normal 0_508 version.
792 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
794 bool isImm0_239() const {
795 if (!isImm()) return false;
796 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
797 if (!CE) return false;
798 int64_t Value = CE->getValue();
799 return Value >= 0 && Value < 240;
801 bool isImm0_255() const {
802 if (!isImm()) return false;
803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804 if (!CE) return false;
805 int64_t Value = CE->getValue();
806 return Value >= 0 && Value < 256;
808 bool isImm0_4095() const {
809 if (!isImm()) return false;
810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
811 if (!CE) return false;
812 int64_t Value = CE->getValue();
813 return Value >= 0 && Value < 4096;
815 bool isImm0_4095Neg() const {
816 if (!isImm()) return false;
817 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818 if (!CE) return false;
819 int64_t Value = -CE->getValue();
820 return Value > 0 && Value < 4096;
822 bool isImm0_1() const {
823 if (!isImm()) return false;
824 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825 if (!CE) return false;
826 int64_t Value = CE->getValue();
827 return Value >= 0 && Value < 2;
829 bool isImm0_3() const {
830 if (!isImm()) return false;
831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832 if (!CE) return false;
833 int64_t Value = CE->getValue();
834 return Value >= 0 && Value < 4;
836 bool isImm0_7() const {
837 if (!isImm()) return false;
838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839 if (!CE) return false;
840 int64_t Value = CE->getValue();
841 return Value >= 0 && Value < 8;
843 bool isImm0_15() const {
844 if (!isImm()) return false;
845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846 if (!CE) return false;
847 int64_t Value = CE->getValue();
848 return Value >= 0 && Value < 16;
850 bool isImm0_31() const {
851 if (!isImm()) return false;
852 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853 if (!CE) return false;
854 int64_t Value = CE->getValue();
855 return Value >= 0 && Value < 32;
857 bool isImm0_63() const {
858 if (!isImm()) return false;
859 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
860 if (!CE) return false;
861 int64_t Value = CE->getValue();
862 return Value >= 0 && Value < 64;
864 bool isImm8() const {
865 if (!isImm()) return false;
866 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
867 if (!CE) return false;
868 int64_t Value = CE->getValue();
871 bool isImm16() const {
872 if (!isImm()) return false;
873 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
874 if (!CE) return false;
875 int64_t Value = CE->getValue();
878 bool isImm32() const {
879 if (!isImm()) return false;
880 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
881 if (!CE) return false;
882 int64_t Value = CE->getValue();
885 bool isShrImm8() const {
886 if (!isImm()) return false;
887 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
888 if (!CE) return false;
889 int64_t Value = CE->getValue();
890 return Value > 0 && Value <= 8;
892 bool isShrImm16() const {
893 if (!isImm()) return false;
894 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
895 if (!CE) return false;
896 int64_t Value = CE->getValue();
897 return Value > 0 && Value <= 16;
899 bool isShrImm32() const {
900 if (!isImm()) return false;
901 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
902 if (!CE) return false;
903 int64_t Value = CE->getValue();
904 return Value > 0 && Value <= 32;
906 bool isShrImm64() const {
907 if (!isImm()) return false;
908 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
909 if (!CE) return false;
910 int64_t Value = CE->getValue();
911 return Value > 0 && Value <= 64;
913 bool isImm1_7() const {
914 if (!isImm()) return false;
915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
916 if (!CE) return false;
917 int64_t Value = CE->getValue();
918 return Value > 0 && Value < 8;
920 bool isImm1_15() const {
921 if (!isImm()) return false;
922 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
923 if (!CE) return false;
924 int64_t Value = CE->getValue();
925 return Value > 0 && Value < 16;
927 bool isImm1_31() const {
928 if (!isImm()) return false;
929 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
930 if (!CE) return false;
931 int64_t Value = CE->getValue();
932 return Value > 0 && Value < 32;
934 bool isImm1_16() const {
935 if (!isImm()) return false;
936 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
937 if (!CE) return false;
938 int64_t Value = CE->getValue();
939 return Value > 0 && Value < 17;
941 bool isImm1_32() const {
942 if (!isImm()) return false;
943 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
944 if (!CE) return false;
945 int64_t Value = CE->getValue();
946 return Value > 0 && Value < 33;
948 bool isImm0_32() const {
949 if (!isImm()) return false;
950 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
951 if (!CE) return false;
952 int64_t Value = CE->getValue();
953 return Value >= 0 && Value < 33;
955 bool isImm0_65535() const {
956 if (!isImm()) return false;
957 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
958 if (!CE) return false;
959 int64_t Value = CE->getValue();
960 return Value >= 0 && Value < 65536;
962 bool isImm256_65535Expr() const {
963 if (!isImm()) return false;
964 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
965 // If it's not a constant expression, it'll generate a fixup and be
967 if (!CE) return true;
968 int64_t Value = CE->getValue();
969 return Value >= 256 && Value < 65536;
971 bool isImm0_65535Expr() const {
972 if (!isImm()) return false;
973 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
974 // If it's not a constant expression, it'll generate a fixup and be
976 if (!CE) return true;
977 int64_t Value = CE->getValue();
978 return Value >= 0 && Value < 65536;
980 bool isImm24bit() const {
981 if (!isImm()) return false;
982 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
983 if (!CE) return false;
984 int64_t Value = CE->getValue();
985 return Value >= 0 && Value <= 0xffffff;
987 bool isImmThumbSR() const {
988 if (!isImm()) return false;
989 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
990 if (!CE) return false;
991 int64_t Value = CE->getValue();
992 return Value > 0 && Value < 33;
994 bool isPKHLSLImm() const {
995 if (!isImm()) return false;
996 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
997 if (!CE) return false;
998 int64_t Value = CE->getValue();
999 return Value >= 0 && Value < 32;
1001 bool isPKHASRImm() const {
1002 if (!isImm()) return false;
1003 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1004 if (!CE) return false;
1005 int64_t Value = CE->getValue();
1006 return Value > 0 && Value <= 32;
1008 bool isAdrLabel() const {
1009 // If we have an immediate that's not a constant, treat it as a label
1010 // reference needing a fixup. If it is a constant, but it can't fit
1011 // into shift immediate encoding, we reject it.
1012 if (isImm() && !isa<MCConstantExpr>(getImm())) return true;
1013 else return (isARMSOImm() || isARMSOImmNeg());
1015 bool isARMSOImm() const {
1016 if (!isImm()) return false;
1017 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1018 if (!CE) return false;
1019 int64_t Value = CE->getValue();
1020 return ARM_AM::getSOImmVal(Value) != -1;
1022 bool isARMSOImmNot() const {
1023 if (!isImm()) return false;
1024 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1025 if (!CE) return false;
1026 int64_t Value = CE->getValue();
1027 return ARM_AM::getSOImmVal(~Value) != -1;
1029 bool isARMSOImmNeg() const {
1030 if (!isImm()) return false;
1031 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1032 if (!CE) return false;
1033 int64_t Value = CE->getValue();
1034 // Only use this when not representable as a plain so_imm.
1035 return ARM_AM::getSOImmVal(Value) == -1 &&
1036 ARM_AM::getSOImmVal(-Value) != -1;
1038 bool isT2SOImm() const {
1039 if (!isImm()) return false;
1040 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1041 if (!CE) return false;
1042 int64_t Value = CE->getValue();
1043 return ARM_AM::getT2SOImmVal(Value) != -1;
1045 bool isT2SOImmNot() const {
1046 if (!isImm()) return false;
1047 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1048 if (!CE) return false;
1049 int64_t Value = CE->getValue();
1050 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1051 ARM_AM::getT2SOImmVal(~Value) != -1;
1053 bool isT2SOImmNeg() const {
1054 if (!isImm()) return false;
1055 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1056 if (!CE) return false;
1057 int64_t Value = CE->getValue();
1058 // Only use this when not representable as a plain so_imm.
1059 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1060 ARM_AM::getT2SOImmVal(-Value) != -1;
1062 bool isSetEndImm() const {
1063 if (!isImm()) return false;
1064 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1065 if (!CE) return false;
1066 int64_t Value = CE->getValue();
1067 return Value == 1 || Value == 0;
1069 bool isReg() const { return Kind == k_Register; }
1070 bool isRegList() const { return Kind == k_RegisterList; }
1071 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1072 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1073 bool isToken() const { return Kind == k_Token; }
1074 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1075 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1076 bool isMem() const { return Kind == k_Memory; }
1077 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1078 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1079 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1080 bool isRotImm() const { return Kind == k_RotateImmediate; }
1081 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1082 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1083 bool isPostIdxReg() const {
1084 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1086 bool isMemNoOffset(bool alignOK = false) const {
1089 // No offset of any kind.
1090 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == 0 &&
1091 (alignOK || Memory.Alignment == 0);
1093 bool isMemPCRelImm12() const {
1094 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1096 // Base register must be PC.
1097 if (Memory.BaseRegNum != ARM::PC)
1099 // Immediate offset in range [-4095, 4095].
1100 if (!Memory.OffsetImm) return true;
1101 int64_t Val = Memory.OffsetImm->getValue();
1102 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1104 bool isAlignedMemory() const {
1105 return isMemNoOffset(true);
1107 bool isAddrMode2() const {
1108 if (!isMem() || Memory.Alignment != 0) return false;
1109 // Check for register offset.
1110 if (Memory.OffsetRegNum) return true;
1111 // Immediate offset in range [-4095, 4095].
1112 if (!Memory.OffsetImm) return true;
1113 int64_t Val = Memory.OffsetImm->getValue();
1114 return Val > -4096 && Val < 4096;
1116 bool isAM2OffsetImm() const {
1117 if (!isImm()) return false;
1118 // Immediate offset in range [-4095, 4095].
1119 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1120 if (!CE) return false;
1121 int64_t Val = CE->getValue();
1122 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1124 bool isAddrMode3() const {
1125 // If we have an immediate that's not a constant, treat it as a label
1126 // reference needing a fixup. If it is a constant, it's something else
1127 // and we reject it.
1128 if (isImm() && !isa<MCConstantExpr>(getImm()))
1130 if (!isMem() || Memory.Alignment != 0) return false;
1131 // No shifts are legal for AM3.
1132 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1133 // Check for register offset.
1134 if (Memory.OffsetRegNum) return true;
1135 // Immediate offset in range [-255, 255].
1136 if (!Memory.OffsetImm) return true;
1137 int64_t Val = Memory.OffsetImm->getValue();
1138 // The #-0 offset is encoded as INT32_MIN, and we have to check
1140 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1142 bool isAM3Offset() const {
1143 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1145 if (Kind == k_PostIndexRegister)
1146 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1147 // Immediate offset in range [-255, 255].
1148 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1149 if (!CE) return false;
1150 int64_t Val = CE->getValue();
1151 // Special case, #-0 is INT32_MIN.
1152 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1154 bool isAddrMode5() const {
1155 // If we have an immediate that's not a constant, treat it as a label
1156 // reference needing a fixup. If it is a constant, it's something else
1157 // and we reject it.
1158 if (isImm() && !isa<MCConstantExpr>(getImm()))
1160 if (!isMem() || Memory.Alignment != 0) return false;
1161 // Check for register offset.
1162 if (Memory.OffsetRegNum) return false;
1163 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1164 if (!Memory.OffsetImm) return true;
1165 int64_t Val = Memory.OffsetImm->getValue();
1166 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1169 bool isMemTBB() const {
1170 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1171 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1175 bool isMemTBH() const {
1176 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1177 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1178 Memory.Alignment != 0 )
1182 bool isMemRegOffset() const {
1183 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1187 bool isT2MemRegOffset() const {
1188 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1189 Memory.Alignment != 0)
1191 // Only lsl #{0, 1, 2, 3} allowed.
1192 if (Memory.ShiftType == ARM_AM::no_shift)
1194 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1198 bool isMemThumbRR() const {
1199 // Thumb reg+reg addressing is simple. Just two registers, a base and
1200 // an offset. No shifts, negations or any other complicating factors.
1201 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1202 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1204 return isARMLowRegister(Memory.BaseRegNum) &&
1205 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1207 bool isMemThumbRIs4() const {
1208 if (!isMem() || Memory.OffsetRegNum != 0 ||
1209 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1211 // Immediate offset, multiple of 4 in range [0, 124].
1212 if (!Memory.OffsetImm) return true;
1213 int64_t Val = Memory.OffsetImm->getValue();
1214 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1216 bool isMemThumbRIs2() const {
1217 if (!isMem() || Memory.OffsetRegNum != 0 ||
1218 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1220 // Immediate offset, multiple of 4 in range [0, 62].
1221 if (!Memory.OffsetImm) return true;
1222 int64_t Val = Memory.OffsetImm->getValue();
1223 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1225 bool isMemThumbRIs1() const {
1226 if (!isMem() || Memory.OffsetRegNum != 0 ||
1227 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1229 // Immediate offset in range [0, 31].
1230 if (!Memory.OffsetImm) return true;
1231 int64_t Val = Memory.OffsetImm->getValue();
1232 return Val >= 0 && Val <= 31;
1234 bool isMemThumbSPI() const {
1235 if (!isMem() || Memory.OffsetRegNum != 0 ||
1236 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1238 // Immediate offset, multiple of 4 in range [0, 1020].
1239 if (!Memory.OffsetImm) return true;
1240 int64_t Val = Memory.OffsetImm->getValue();
1241 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1243 bool isMemImm8s4Offset() const {
1244 // If we have an immediate that's not a constant, treat it as a label
1245 // reference needing a fixup. If it is a constant, it's something else
1246 // and we reject it.
1247 if (isImm() && !isa<MCConstantExpr>(getImm()))
1249 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1251 // Immediate offset a multiple of 4 in range [-1020, 1020].
1252 if (!Memory.OffsetImm) return true;
1253 int64_t Val = Memory.OffsetImm->getValue();
1254 // Special case, #-0 is INT32_MIN.
1255 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1257 bool isMemImm0_1020s4Offset() const {
1258 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1260 // Immediate offset a multiple of 4 in range [0, 1020].
1261 if (!Memory.OffsetImm) return true;
1262 int64_t Val = Memory.OffsetImm->getValue();
1263 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1265 bool isMemImm8Offset() const {
1266 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1268 // Base reg of PC isn't allowed for these encodings.
1269 if (Memory.BaseRegNum == ARM::PC) return false;
1270 // Immediate offset in range [-255, 255].
1271 if (!Memory.OffsetImm) return true;
1272 int64_t Val = Memory.OffsetImm->getValue();
1273 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1275 bool isMemPosImm8Offset() const {
1276 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1278 // Immediate offset in range [0, 255].
1279 if (!Memory.OffsetImm) return true;
1280 int64_t Val = Memory.OffsetImm->getValue();
1281 return Val >= 0 && Val < 256;
1283 bool isMemNegImm8Offset() const {
1284 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1286 // Base reg of PC isn't allowed for these encodings.
1287 if (Memory.BaseRegNum == ARM::PC) return false;
1288 // Immediate offset in range [-255, -1].
1289 if (!Memory.OffsetImm) return false;
1290 int64_t Val = Memory.OffsetImm->getValue();
1291 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1293 bool isMemUImm12Offset() const {
1294 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1296 // Immediate offset in range [0, 4095].
1297 if (!Memory.OffsetImm) return true;
1298 int64_t Val = Memory.OffsetImm->getValue();
1299 return (Val >= 0 && Val < 4096);
1301 bool isMemImm12Offset() const {
1302 // If we have an immediate that's not a constant, treat it as a label
1303 // reference needing a fixup. If it is a constant, it's something else
1304 // and we reject it.
1305 if (isImm() && !isa<MCConstantExpr>(getImm()))
1308 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1310 // Immediate offset in range [-4095, 4095].
1311 if (!Memory.OffsetImm) return true;
1312 int64_t Val = Memory.OffsetImm->getValue();
1313 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1315 bool isPostIdxImm8() const {
1316 if (!isImm()) return false;
1317 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1318 if (!CE) return false;
1319 int64_t Val = CE->getValue();
1320 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1322 bool isPostIdxImm8s4() const {
1323 if (!isImm()) return false;
1324 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1325 if (!CE) return false;
1326 int64_t Val = CE->getValue();
1327 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1331 bool isMSRMask() const { return Kind == k_MSRMask; }
1332 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1335 bool isSingleSpacedVectorList() const {
1336 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1338 bool isDoubleSpacedVectorList() const {
1339 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1341 bool isVecListOneD() const {
1342 if (!isSingleSpacedVectorList()) return false;
1343 return VectorList.Count == 1;
1346 bool isVecListDPair() const {
1347 if (!isSingleSpacedVectorList()) return false;
1348 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1349 .contains(VectorList.RegNum));
1352 bool isVecListThreeD() const {
1353 if (!isSingleSpacedVectorList()) return false;
1354 return VectorList.Count == 3;
1357 bool isVecListFourD() const {
1358 if (!isSingleSpacedVectorList()) return false;
1359 return VectorList.Count == 4;
1362 bool isVecListDPairSpaced() const {
1363 if (isSingleSpacedVectorList()) return false;
1364 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1365 .contains(VectorList.RegNum));
1368 bool isVecListThreeQ() const {
1369 if (!isDoubleSpacedVectorList()) return false;
1370 return VectorList.Count == 3;
1373 bool isVecListFourQ() const {
1374 if (!isDoubleSpacedVectorList()) return false;
1375 return VectorList.Count == 4;
1378 bool isSingleSpacedVectorAllLanes() const {
1379 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1381 bool isDoubleSpacedVectorAllLanes() const {
1382 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1384 bool isVecListOneDAllLanes() const {
1385 if (!isSingleSpacedVectorAllLanes()) return false;
1386 return VectorList.Count == 1;
1389 bool isVecListDPairAllLanes() const {
1390 if (!isSingleSpacedVectorAllLanes()) return false;
1391 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1392 .contains(VectorList.RegNum));
1395 bool isVecListDPairSpacedAllLanes() const {
1396 if (!isDoubleSpacedVectorAllLanes()) return false;
1397 return VectorList.Count == 2;
1400 bool isVecListThreeDAllLanes() const {
1401 if (!isSingleSpacedVectorAllLanes()) return false;
1402 return VectorList.Count == 3;
1405 bool isVecListThreeQAllLanes() const {
1406 if (!isDoubleSpacedVectorAllLanes()) return false;
1407 return VectorList.Count == 3;
1410 bool isVecListFourDAllLanes() const {
1411 if (!isSingleSpacedVectorAllLanes()) return false;
1412 return VectorList.Count == 4;
1415 bool isVecListFourQAllLanes() const {
1416 if (!isDoubleSpacedVectorAllLanes()) return false;
1417 return VectorList.Count == 4;
1420 bool isSingleSpacedVectorIndexed() const {
1421 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1423 bool isDoubleSpacedVectorIndexed() const {
1424 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1426 bool isVecListOneDByteIndexed() const {
1427 if (!isSingleSpacedVectorIndexed()) return false;
1428 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1431 bool isVecListOneDHWordIndexed() const {
1432 if (!isSingleSpacedVectorIndexed()) return false;
1433 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1436 bool isVecListOneDWordIndexed() const {
1437 if (!isSingleSpacedVectorIndexed()) return false;
1438 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1441 bool isVecListTwoDByteIndexed() const {
1442 if (!isSingleSpacedVectorIndexed()) return false;
1443 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1446 bool isVecListTwoDHWordIndexed() const {
1447 if (!isSingleSpacedVectorIndexed()) return false;
1448 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1451 bool isVecListTwoQWordIndexed() const {
1452 if (!isDoubleSpacedVectorIndexed()) return false;
1453 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1456 bool isVecListTwoQHWordIndexed() const {
1457 if (!isDoubleSpacedVectorIndexed()) return false;
1458 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1461 bool isVecListTwoDWordIndexed() const {
1462 if (!isSingleSpacedVectorIndexed()) return false;
1463 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1466 bool isVecListThreeDByteIndexed() const {
1467 if (!isSingleSpacedVectorIndexed()) return false;
1468 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1471 bool isVecListThreeDHWordIndexed() const {
1472 if (!isSingleSpacedVectorIndexed()) return false;
1473 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1476 bool isVecListThreeQWordIndexed() const {
1477 if (!isDoubleSpacedVectorIndexed()) return false;
1478 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1481 bool isVecListThreeQHWordIndexed() const {
1482 if (!isDoubleSpacedVectorIndexed()) return false;
1483 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1486 bool isVecListThreeDWordIndexed() const {
1487 if (!isSingleSpacedVectorIndexed()) return false;
1488 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1491 bool isVecListFourDByteIndexed() const {
1492 if (!isSingleSpacedVectorIndexed()) return false;
1493 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1496 bool isVecListFourDHWordIndexed() const {
1497 if (!isSingleSpacedVectorIndexed()) return false;
1498 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1501 bool isVecListFourQWordIndexed() const {
1502 if (!isDoubleSpacedVectorIndexed()) return false;
1503 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1506 bool isVecListFourQHWordIndexed() const {
1507 if (!isDoubleSpacedVectorIndexed()) return false;
1508 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1511 bool isVecListFourDWordIndexed() const {
1512 if (!isSingleSpacedVectorIndexed()) return false;
1513 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1516 bool isVectorIndex8() const {
1517 if (Kind != k_VectorIndex) return false;
1518 return VectorIndex.Val < 8;
1520 bool isVectorIndex16() const {
1521 if (Kind != k_VectorIndex) return false;
1522 return VectorIndex.Val < 4;
1524 bool isVectorIndex32() const {
1525 if (Kind != k_VectorIndex) return false;
1526 return VectorIndex.Val < 2;
1529 bool isNEONi8splat() const {
1530 if (!isImm()) return false;
1531 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1532 // Must be a constant.
1533 if (!CE) return false;
1534 int64_t Value = CE->getValue();
1535 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1537 return Value >= 0 && Value < 256;
1540 bool isNEONi16splat() const {
1541 if (!isImm()) return false;
1542 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1543 // Must be a constant.
1544 if (!CE) return false;
1545 int64_t Value = CE->getValue();
1546 // i16 value in the range [0,255] or [0x0100, 0xff00]
1547 return (Value >= 0 && Value < 256) || (Value >= 0x0100 && Value <= 0xff00);
1550 bool isNEONi32splat() const {
1551 if (!isImm()) return false;
1552 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1553 // Must be a constant.
1554 if (!CE) return false;
1555 int64_t Value = CE->getValue();
1556 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X.
1557 return (Value >= 0 && Value < 256) ||
1558 (Value >= 0x0100 && Value <= 0xff00) ||
1559 (Value >= 0x010000 && Value <= 0xff0000) ||
1560 (Value >= 0x01000000 && Value <= 0xff000000);
1563 bool isNEONi32vmov() const {
1564 if (!isImm()) return false;
1565 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1566 // Must be a constant.
1567 if (!CE) return false;
1568 int64_t Value = CE->getValue();
1569 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1570 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1571 return (Value >= 0 && Value < 256) ||
1572 (Value >= 0x0100 && Value <= 0xff00) ||
1573 (Value >= 0x010000 && Value <= 0xff0000) ||
1574 (Value >= 0x01000000 && Value <= 0xff000000) ||
1575 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1576 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1578 bool isNEONi32vmovNeg() const {
1579 if (!isImm()) return false;
1580 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1581 // Must be a constant.
1582 if (!CE) return false;
1583 int64_t Value = ~CE->getValue();
1584 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1585 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1586 return (Value >= 0 && Value < 256) ||
1587 (Value >= 0x0100 && Value <= 0xff00) ||
1588 (Value >= 0x010000 && Value <= 0xff0000) ||
1589 (Value >= 0x01000000 && Value <= 0xff000000) ||
1590 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1591 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1594 bool isNEONi64splat() const {
1595 if (!isImm()) return false;
1596 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1597 // Must be a constant.
1598 if (!CE) return false;
1599 uint64_t Value = CE->getValue();
1600 // i64 value with each byte being either 0 or 0xff.
1601 for (unsigned i = 0; i < 8; ++i)
1602 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1606 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1607 // Add as immediates when possible. Null MCExpr = 0.
1609 Inst.addOperand(MCOperand::CreateImm(0));
1610 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1611 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1613 Inst.addOperand(MCOperand::CreateExpr(Expr));
1616 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1617 assert(N == 2 && "Invalid number of operands!");
1618 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1619 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1620 Inst.addOperand(MCOperand::CreateReg(RegNum));
1623 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1624 assert(N == 1 && "Invalid number of operands!");
1625 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1628 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1629 assert(N == 1 && "Invalid number of operands!");
1630 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1633 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1634 assert(N == 1 && "Invalid number of operands!");
1635 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1638 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1639 assert(N == 1 && "Invalid number of operands!");
1640 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1643 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1644 assert(N == 1 && "Invalid number of operands!");
1645 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1648 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1649 assert(N == 1 && "Invalid number of operands!");
1650 Inst.addOperand(MCOperand::CreateReg(getReg()));
1653 void addRegOperands(MCInst &Inst, unsigned N) const {
1654 assert(N == 1 && "Invalid number of operands!");
1655 Inst.addOperand(MCOperand::CreateReg(getReg()));
1658 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1659 assert(N == 3 && "Invalid number of operands!");
1660 assert(isRegShiftedReg() &&
1661 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1662 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1663 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1664 Inst.addOperand(MCOperand::CreateImm(
1665 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1668 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1669 assert(N == 2 && "Invalid number of operands!");
1670 assert(isRegShiftedImm() &&
1671 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1672 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1673 // Shift of #32 is encoded as 0 where permitted
1674 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1675 Inst.addOperand(MCOperand::CreateImm(
1676 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1679 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1680 assert(N == 1 && "Invalid number of operands!");
1681 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1685 void addRegListOperands(MCInst &Inst, unsigned N) const {
1686 assert(N == 1 && "Invalid number of operands!");
1687 const SmallVectorImpl<unsigned> &RegList = getRegList();
1688 for (SmallVectorImpl<unsigned>::const_iterator
1689 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1690 Inst.addOperand(MCOperand::CreateReg(*I));
1693 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1694 addRegListOperands(Inst, N);
1697 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1698 addRegListOperands(Inst, N);
1701 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1702 assert(N == 1 && "Invalid number of operands!");
1703 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1704 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1707 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1708 assert(N == 1 && "Invalid number of operands!");
1709 // Munge the lsb/width into a bitfield mask.
1710 unsigned lsb = Bitfield.LSB;
1711 unsigned width = Bitfield.Width;
1712 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1713 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1714 (32 - (lsb + width)));
1715 Inst.addOperand(MCOperand::CreateImm(Mask));
1718 void addImmOperands(MCInst &Inst, unsigned N) const {
1719 assert(N == 1 && "Invalid number of operands!");
1720 addExpr(Inst, getImm());
1723 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1724 assert(N == 1 && "Invalid number of operands!");
1725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1726 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1729 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1730 assert(N == 1 && "Invalid number of operands!");
1731 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1732 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1735 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1736 assert(N == 1 && "Invalid number of operands!");
1737 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1738 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1739 Inst.addOperand(MCOperand::CreateImm(Val));
1742 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1743 assert(N == 1 && "Invalid number of operands!");
1744 // FIXME: We really want to scale the value here, but the LDRD/STRD
1745 // instruction don't encode operands that way yet.
1746 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1747 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1750 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1751 assert(N == 1 && "Invalid number of operands!");
1752 // The immediate is scaled by four in the encoding and is stored
1753 // in the MCInst as such. Lop off the low two bits here.
1754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1755 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1758 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1759 assert(N == 1 && "Invalid number of operands!");
1760 // The immediate is scaled by four in the encoding and is stored
1761 // in the MCInst as such. Lop off the low two bits here.
1762 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1763 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1766 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1767 assert(N == 1 && "Invalid number of operands!");
1768 // The immediate is scaled by four in the encoding and is stored
1769 // in the MCInst as such. Lop off the low two bits here.
1770 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1771 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1774 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1775 assert(N == 1 && "Invalid number of operands!");
1776 // The constant encodes as the immediate-1, and we store in the instruction
1777 // the bits as encoded, so subtract off one here.
1778 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1779 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1782 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1783 assert(N == 1 && "Invalid number of operands!");
1784 // The constant encodes as the immediate-1, and we store in the instruction
1785 // the bits as encoded, so subtract off one here.
1786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1787 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1790 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1791 assert(N == 1 && "Invalid number of operands!");
1792 // The constant encodes as the immediate, except for 32, which encodes as
1794 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1795 unsigned Imm = CE->getValue();
1796 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1799 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1800 assert(N == 1 && "Invalid number of operands!");
1801 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1802 // the instruction as well.
1803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1804 int Val = CE->getValue();
1805 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1808 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1809 assert(N == 1 && "Invalid number of operands!");
1810 // The operand is actually a t2_so_imm, but we have its bitwise
1811 // negation in the assembly source, so twiddle it here.
1812 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1813 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1816 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1817 assert(N == 1 && "Invalid number of operands!");
1818 // The operand is actually a t2_so_imm, but we have its
1819 // negation in the assembly source, so twiddle it here.
1820 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1821 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1824 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1825 assert(N == 1 && "Invalid number of operands!");
1826 // The operand is actually an imm0_4095, but we have its
1827 // negation in the assembly source, so twiddle it here.
1828 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1829 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1832 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1833 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1834 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
1838 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1839 assert(SR && "Unknown value type!");
1840 Inst.addOperand(MCOperand::CreateExpr(SR));
1843 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1844 assert(N == 1 && "Invalid number of operands!");
1846 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1848 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1852 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1853 assert(SR && "Unknown value type!");
1854 Inst.addOperand(MCOperand::CreateExpr(SR));
1858 assert(isMem() && "Unknown value type!");
1859 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1860 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
1863 void addARMSOImmNotOperands(MCInst &Inst, unsigned N) const {
1864 assert(N == 1 && "Invalid number of operands!");
1865 // The operand is actually a so_imm, but we have its bitwise
1866 // negation in the assembly source, so twiddle it here.
1867 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1868 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1871 void addARMSOImmNegOperands(MCInst &Inst, unsigned N) const {
1872 assert(N == 1 && "Invalid number of operands!");
1873 // The operand is actually a so_imm, but we have its
1874 // negation in the assembly source, so twiddle it here.
1875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1876 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1879 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1880 assert(N == 1 && "Invalid number of operands!");
1881 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1884 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1885 assert(N == 1 && "Invalid number of operands!");
1886 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
1889 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1890 assert(N == 1 && "Invalid number of operands!");
1891 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1894 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1895 assert(N == 1 && "Invalid number of operands!");
1896 int32_t Imm = Memory.OffsetImm->getValue();
1897 Inst.addOperand(MCOperand::CreateImm(Imm));
1900 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1901 assert(N == 1 && "Invalid number of operands!");
1902 assert(isImm() && "Not an immediate!");
1904 // If we have an immediate that's not a constant, treat it as a label
1905 // reference needing a fixup.
1906 if (!isa<MCConstantExpr>(getImm())) {
1907 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1911 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1912 int Val = CE->getValue();
1913 Inst.addOperand(MCOperand::CreateImm(Val));
1916 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
1917 assert(N == 2 && "Invalid number of operands!");
1918 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1919 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
1922 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1923 assert(N == 3 && "Invalid number of operands!");
1924 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1925 if (!Memory.OffsetRegNum) {
1926 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1927 // Special case for #-0
1928 if (Val == INT32_MIN) Val = 0;
1929 if (Val < 0) Val = -Val;
1930 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1932 // For register offset, we encode the shift type and negation flag
1934 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
1935 Memory.ShiftImm, Memory.ShiftType);
1937 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1938 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1939 Inst.addOperand(MCOperand::CreateImm(Val));
1942 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1943 assert(N == 2 && "Invalid number of operands!");
1944 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1945 assert(CE && "non-constant AM2OffsetImm operand!");
1946 int32_t Val = CE->getValue();
1947 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1948 // Special case for #-0
1949 if (Val == INT32_MIN) Val = 0;
1950 if (Val < 0) Val = -Val;
1951 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1952 Inst.addOperand(MCOperand::CreateReg(0));
1953 Inst.addOperand(MCOperand::CreateImm(Val));
1956 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1957 assert(N == 3 && "Invalid number of operands!");
1958 // If we have an immediate that's not a constant, treat it as a label
1959 // reference needing a fixup. If it is a constant, it's something else
1960 // and we reject it.
1962 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1963 Inst.addOperand(MCOperand::CreateReg(0));
1964 Inst.addOperand(MCOperand::CreateImm(0));
1968 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
1969 if (!Memory.OffsetRegNum) {
1970 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1971 // Special case for #-0
1972 if (Val == INT32_MIN) Val = 0;
1973 if (Val < 0) Val = -Val;
1974 Val = ARM_AM::getAM3Opc(AddSub, Val);
1976 // For register offset, we encode the shift type and negation flag
1978 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1980 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
1981 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
1982 Inst.addOperand(MCOperand::CreateImm(Val));
1985 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1986 assert(N == 2 && "Invalid number of operands!");
1987 if (Kind == k_PostIndexRegister) {
1989 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1990 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1991 Inst.addOperand(MCOperand::CreateImm(Val));
1996 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1997 int32_t Val = CE->getValue();
1998 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1999 // Special case for #-0
2000 if (Val == INT32_MIN) Val = 0;
2001 if (Val < 0) Val = -Val;
2002 Val = ARM_AM::getAM3Opc(AddSub, Val);
2003 Inst.addOperand(MCOperand::CreateReg(0));
2004 Inst.addOperand(MCOperand::CreateImm(Val));
2007 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2008 assert(N == 2 && "Invalid number of operands!");
2009 // If we have an immediate that's not a constant, treat it as a label
2010 // reference needing a fixup. If it is a constant, it's something else
2011 // and we reject it.
2013 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2014 Inst.addOperand(MCOperand::CreateImm(0));
2018 // The lower two bits are always zero and as such are not encoded.
2019 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2020 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2021 // Special case for #-0
2022 if (Val == INT32_MIN) Val = 0;
2023 if (Val < 0) Val = -Val;
2024 Val = ARM_AM::getAM5Opc(AddSub, Val);
2025 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2026 Inst.addOperand(MCOperand::CreateImm(Val));
2029 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2030 assert(N == 2 && "Invalid number of operands!");
2031 // If we have an immediate that's not a constant, treat it as a label
2032 // reference needing a fixup. If it is a constant, it's something else
2033 // and we reject it.
2035 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2036 Inst.addOperand(MCOperand::CreateImm(0));
2040 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2041 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2042 Inst.addOperand(MCOperand::CreateImm(Val));
2045 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2046 assert(N == 2 && "Invalid number of operands!");
2047 // The lower two bits are always zero and as such are not encoded.
2048 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2049 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2050 Inst.addOperand(MCOperand::CreateImm(Val));
2053 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2054 assert(N == 2 && "Invalid number of operands!");
2055 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2056 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2057 Inst.addOperand(MCOperand::CreateImm(Val));
2060 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2061 addMemImm8OffsetOperands(Inst, N);
2064 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2065 addMemImm8OffsetOperands(Inst, N);
2068 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2069 assert(N == 2 && "Invalid number of operands!");
2070 // If this is an immediate, it's a label reference.
2072 addExpr(Inst, getImm());
2073 Inst.addOperand(MCOperand::CreateImm(0));
2077 // Otherwise, it's a normal memory reg+offset.
2078 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2079 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2080 Inst.addOperand(MCOperand::CreateImm(Val));
2083 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2084 assert(N == 2 && "Invalid number of operands!");
2085 // If this is an immediate, it's a label reference.
2087 addExpr(Inst, getImm());
2088 Inst.addOperand(MCOperand::CreateImm(0));
2092 // Otherwise, it's a normal memory reg+offset.
2093 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2094 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2095 Inst.addOperand(MCOperand::CreateImm(Val));
2098 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2099 assert(N == 2 && "Invalid number of operands!");
2100 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2101 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2104 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2105 assert(N == 2 && "Invalid number of operands!");
2106 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2107 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2110 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2111 assert(N == 3 && "Invalid number of operands!");
2113 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2114 Memory.ShiftImm, Memory.ShiftType);
2115 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2116 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2117 Inst.addOperand(MCOperand::CreateImm(Val));
2120 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2121 assert(N == 3 && "Invalid number of operands!");
2122 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2123 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2124 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2127 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2128 assert(N == 2 && "Invalid number of operands!");
2129 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2130 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2133 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2134 assert(N == 2 && "Invalid number of operands!");
2135 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2136 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2137 Inst.addOperand(MCOperand::CreateImm(Val));
2140 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2141 assert(N == 2 && "Invalid number of operands!");
2142 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2143 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2144 Inst.addOperand(MCOperand::CreateImm(Val));
2147 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2148 assert(N == 2 && "Invalid number of operands!");
2149 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2150 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2151 Inst.addOperand(MCOperand::CreateImm(Val));
2154 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2155 assert(N == 2 && "Invalid number of operands!");
2156 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2157 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2158 Inst.addOperand(MCOperand::CreateImm(Val));
2161 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2162 assert(N == 1 && "Invalid number of operands!");
2163 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2164 assert(CE && "non-constant post-idx-imm8 operand!");
2165 int Imm = CE->getValue();
2166 bool isAdd = Imm >= 0;
2167 if (Imm == INT32_MIN) Imm = 0;
2168 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2169 Inst.addOperand(MCOperand::CreateImm(Imm));
2172 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2173 assert(N == 1 && "Invalid number of operands!");
2174 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2175 assert(CE && "non-constant post-idx-imm8s4 operand!");
2176 int Imm = CE->getValue();
2177 bool isAdd = Imm >= 0;
2178 if (Imm == INT32_MIN) Imm = 0;
2179 // Immediate is scaled by 4.
2180 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2181 Inst.addOperand(MCOperand::CreateImm(Imm));
2184 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2185 assert(N == 2 && "Invalid number of operands!");
2186 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2187 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2190 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2191 assert(N == 2 && "Invalid number of operands!");
2192 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2193 // The sign, shift type, and shift amount are encoded in a single operand
2194 // using the AM2 encoding helpers.
2195 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2196 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2197 PostIdxReg.ShiftTy);
2198 Inst.addOperand(MCOperand::CreateImm(Imm));
2201 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2202 assert(N == 1 && "Invalid number of operands!");
2203 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2206 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2207 assert(N == 1 && "Invalid number of operands!");
2208 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2211 void addVecListOperands(MCInst &Inst, unsigned N) const {
2212 assert(N == 1 && "Invalid number of operands!");
2213 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2216 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2217 assert(N == 2 && "Invalid number of operands!");
2218 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2219 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2222 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2223 assert(N == 1 && "Invalid number of operands!");
2224 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2227 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2228 assert(N == 1 && "Invalid number of operands!");
2229 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2232 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2233 assert(N == 1 && "Invalid number of operands!");
2234 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2237 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2238 assert(N == 1 && "Invalid number of operands!");
2239 // The immediate encodes the type of constant as well as the value.
2240 // Mask in that this is an i8 splat.
2241 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2242 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2245 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2246 assert(N == 1 && "Invalid number of operands!");
2247 // The immediate encodes the type of constant as well as the value.
2248 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2249 unsigned Value = CE->getValue();
2251 Value = (Value >> 8) | 0xa00;
2254 Inst.addOperand(MCOperand::CreateImm(Value));
2257 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2258 assert(N == 1 && "Invalid number of operands!");
2259 // The immediate encodes the type of constant as well as the value.
2260 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2261 unsigned Value = CE->getValue();
2262 if (Value >= 256 && Value <= 0xff00)
2263 Value = (Value >> 8) | 0x200;
2264 else if (Value > 0xffff && Value <= 0xff0000)
2265 Value = (Value >> 16) | 0x400;
2266 else if (Value > 0xffffff)
2267 Value = (Value >> 24) | 0x600;
2268 Inst.addOperand(MCOperand::CreateImm(Value));
2271 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2272 assert(N == 1 && "Invalid number of operands!");
2273 // The immediate encodes the type of constant as well as the value.
2274 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2275 unsigned Value = CE->getValue();
2276 if (Value >= 256 && Value <= 0xffff)
2277 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2278 else if (Value > 0xffff && Value <= 0xffffff)
2279 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2280 else if (Value > 0xffffff)
2281 Value = (Value >> 24) | 0x600;
2282 Inst.addOperand(MCOperand::CreateImm(Value));
2285 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2286 assert(N == 1 && "Invalid number of operands!");
2287 // The immediate encodes the type of constant as well as the value.
2288 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2289 unsigned Value = ~CE->getValue();
2290 if (Value >= 256 && Value <= 0xffff)
2291 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2292 else if (Value > 0xffff && Value <= 0xffffff)
2293 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2294 else if (Value > 0xffffff)
2295 Value = (Value >> 24) | 0x600;
2296 Inst.addOperand(MCOperand::CreateImm(Value));
2299 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2300 assert(N == 1 && "Invalid number of operands!");
2301 // The immediate encodes the type of constant as well as the value.
2302 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2303 uint64_t Value = CE->getValue();
2305 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2306 Imm |= (Value & 1) << i;
2308 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2311 virtual void print(raw_ostream &OS) const;
2313 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
2314 ARMOperand *Op = new ARMOperand(k_ITCondMask);
2315 Op->ITMask.Mask = Mask;
2321 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
2322 ARMOperand *Op = new ARMOperand(k_CondCode);
2329 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
2330 ARMOperand *Op = new ARMOperand(k_CoprocNum);
2331 Op->Cop.Val = CopVal;
2337 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
2338 ARMOperand *Op = new ARMOperand(k_CoprocReg);
2339 Op->Cop.Val = CopVal;
2345 static ARMOperand *CreateCoprocOption(unsigned Val, SMLoc S, SMLoc E) {
2346 ARMOperand *Op = new ARMOperand(k_CoprocOption);
2353 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
2354 ARMOperand *Op = new ARMOperand(k_CCOut);
2355 Op->Reg.RegNum = RegNum;
2361 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
2362 ARMOperand *Op = new ARMOperand(k_Token);
2363 Op->Tok.Data = Str.data();
2364 Op->Tok.Length = Str.size();
2370 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
2371 ARMOperand *Op = new ARMOperand(k_Register);
2372 Op->Reg.RegNum = RegNum;
2378 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
2383 ARMOperand *Op = new ARMOperand(k_ShiftedRegister);
2384 Op->RegShiftedReg.ShiftTy = ShTy;
2385 Op->RegShiftedReg.SrcReg = SrcReg;
2386 Op->RegShiftedReg.ShiftReg = ShiftReg;
2387 Op->RegShiftedReg.ShiftImm = ShiftImm;
2393 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
2397 ARMOperand *Op = new ARMOperand(k_ShiftedImmediate);
2398 Op->RegShiftedImm.ShiftTy = ShTy;
2399 Op->RegShiftedImm.SrcReg = SrcReg;
2400 Op->RegShiftedImm.ShiftImm = ShiftImm;
2406 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
2408 ARMOperand *Op = new ARMOperand(k_ShifterImmediate);
2409 Op->ShifterImm.isASR = isASR;
2410 Op->ShifterImm.Imm = Imm;
2416 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
2417 ARMOperand *Op = new ARMOperand(k_RotateImmediate);
2418 Op->RotImm.Imm = Imm;
2424 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
2426 ARMOperand *Op = new ARMOperand(k_BitfieldDescriptor);
2427 Op->Bitfield.LSB = LSB;
2428 Op->Bitfield.Width = Width;
2435 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned> > &Regs,
2436 SMLoc StartLoc, SMLoc EndLoc) {
2437 assert (Regs.size() > 0 && "RegList contains no registers?");
2438 KindTy Kind = k_RegisterList;
2440 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2441 Kind = k_DPRRegisterList;
2442 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2443 contains(Regs.front().second))
2444 Kind = k_SPRRegisterList;
2446 // Sort based on the register encoding values.
2447 array_pod_sort(Regs.begin(), Regs.end());
2449 ARMOperand *Op = new ARMOperand(Kind);
2450 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2451 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2452 Op->Registers.push_back(I->second);
2453 Op->StartLoc = StartLoc;
2454 Op->EndLoc = EndLoc;
2458 static ARMOperand *CreateVectorList(unsigned RegNum, unsigned Count,
2459 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2460 ARMOperand *Op = new ARMOperand(k_VectorList);
2461 Op->VectorList.RegNum = RegNum;
2462 Op->VectorList.Count = Count;
2463 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2469 static ARMOperand *CreateVectorListAllLanes(unsigned RegNum, unsigned Count,
2470 bool isDoubleSpaced,
2472 ARMOperand *Op = new ARMOperand(k_VectorListAllLanes);
2473 Op->VectorList.RegNum = RegNum;
2474 Op->VectorList.Count = Count;
2475 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2481 static ARMOperand *CreateVectorListIndexed(unsigned RegNum, unsigned Count,
2483 bool isDoubleSpaced,
2485 ARMOperand *Op = new ARMOperand(k_VectorListIndexed);
2486 Op->VectorList.RegNum = RegNum;
2487 Op->VectorList.Count = Count;
2488 Op->VectorList.LaneIndex = Index;
2489 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2495 static ARMOperand *CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E,
2497 ARMOperand *Op = new ARMOperand(k_VectorIndex);
2498 Op->VectorIndex.Val = Idx;
2504 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
2505 ARMOperand *Op = new ARMOperand(k_Immediate);
2512 static ARMOperand *CreateMem(unsigned BaseRegNum,
2513 const MCConstantExpr *OffsetImm,
2514 unsigned OffsetRegNum,
2515 ARM_AM::ShiftOpc ShiftType,
2520 ARMOperand *Op = new ARMOperand(k_Memory);
2521 Op->Memory.BaseRegNum = BaseRegNum;
2522 Op->Memory.OffsetImm = OffsetImm;
2523 Op->Memory.OffsetRegNum = OffsetRegNum;
2524 Op->Memory.ShiftType = ShiftType;
2525 Op->Memory.ShiftImm = ShiftImm;
2526 Op->Memory.Alignment = Alignment;
2527 Op->Memory.isNegative = isNegative;
2533 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
2534 ARM_AM::ShiftOpc ShiftTy,
2537 ARMOperand *Op = new ARMOperand(k_PostIndexRegister);
2538 Op->PostIdxReg.RegNum = RegNum;
2539 Op->PostIdxReg.isAdd = isAdd;
2540 Op->PostIdxReg.ShiftTy = ShiftTy;
2541 Op->PostIdxReg.ShiftImm = ShiftImm;
2547 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
2548 ARMOperand *Op = new ARMOperand(k_MemBarrierOpt);
2549 Op->MBOpt.Val = Opt;
2555 static ARMOperand *CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt,
2557 ARMOperand *Op = new ARMOperand(k_InstSyncBarrierOpt);
2558 Op->ISBOpt.Val = Opt;
2564 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
2565 ARMOperand *Op = new ARMOperand(k_ProcIFlags);
2566 Op->IFlags.Val = IFlags;
2572 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
2573 ARMOperand *Op = new ARMOperand(k_MSRMask);
2574 Op->MMask.Val = MMask;
2581 } // end anonymous namespace.
2583 void ARMOperand::print(raw_ostream &OS) const {
2586 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2589 OS << "<ccout " << getReg() << ">";
2591 case k_ITCondMask: {
2592 static const char *const MaskStr[] = {
2593 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2594 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2596 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2597 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2601 OS << "<coprocessor number: " << getCoproc() << ">";
2604 OS << "<coprocessor register: " << getCoproc() << ">";
2606 case k_CoprocOption:
2607 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2610 OS << "<mask: " << getMSRMask() << ">";
2613 getImm()->print(OS);
2615 case k_MemBarrierOpt:
2616 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2618 case k_InstSyncBarrierOpt:
2619 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2623 << " base:" << Memory.BaseRegNum;
2626 case k_PostIndexRegister:
2627 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2628 << PostIdxReg.RegNum;
2629 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2630 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2631 << PostIdxReg.ShiftImm;
2634 case k_ProcIFlags: {
2635 OS << "<ARM_PROC::";
2636 unsigned IFlags = getProcIFlags();
2637 for (int i=2; i >= 0; --i)
2638 if (IFlags & (1 << i))
2639 OS << ARM_PROC::IFlagsToString(1 << i);
2644 OS << "<register " << getReg() << ">";
2646 case k_ShifterImmediate:
2647 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2648 << " #" << ShifterImm.Imm << ">";
2650 case k_ShiftedRegister:
2651 OS << "<so_reg_reg "
2652 << RegShiftedReg.SrcReg << " "
2653 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2654 << " " << RegShiftedReg.ShiftReg << ">";
2656 case k_ShiftedImmediate:
2657 OS << "<so_reg_imm "
2658 << RegShiftedImm.SrcReg << " "
2659 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2660 << " #" << RegShiftedImm.ShiftImm << ">";
2662 case k_RotateImmediate:
2663 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2665 case k_BitfieldDescriptor:
2666 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2667 << ", width: " << Bitfield.Width << ">";
2669 case k_RegisterList:
2670 case k_DPRRegisterList:
2671 case k_SPRRegisterList: {
2672 OS << "<register_list ";
2674 const SmallVectorImpl<unsigned> &RegList = getRegList();
2675 for (SmallVectorImpl<unsigned>::const_iterator
2676 I = RegList.begin(), E = RegList.end(); I != E; ) {
2678 if (++I < E) OS << ", ";
2685 OS << "<vector_list " << VectorList.Count << " * "
2686 << VectorList.RegNum << ">";
2688 case k_VectorListAllLanes:
2689 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2690 << VectorList.RegNum << ">";
2692 case k_VectorListIndexed:
2693 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2694 << VectorList.Count << " * " << VectorList.RegNum << ">";
2697 OS << "'" << getToken() << "'";
2700 OS << "<vectorindex " << getVectorIndex() << ">";
2705 /// @name Auto-generated Match Functions
2708 static unsigned MatchRegisterName(StringRef Name);
2712 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2713 SMLoc &StartLoc, SMLoc &EndLoc) {
2714 StartLoc = Parser.getTok().getLoc();
2715 EndLoc = Parser.getTok().getEndLoc();
2716 RegNo = tryParseRegister();
2718 return (RegNo == (unsigned)-1);
2721 /// Try to parse a register name. The token must be an Identifier when called,
2722 /// and if it is a register name the token is eaten and the register number is
2723 /// returned. Otherwise return -1.
2725 int ARMAsmParser::tryParseRegister() {
2726 const AsmToken &Tok = Parser.getTok();
2727 if (Tok.isNot(AsmToken::Identifier)) return -1;
2729 std::string lowerCase = Tok.getString().lower();
2730 unsigned RegNum = MatchRegisterName(lowerCase);
2732 RegNum = StringSwitch<unsigned>(lowerCase)
2733 .Case("r13", ARM::SP)
2734 .Case("r14", ARM::LR)
2735 .Case("r15", ARM::PC)
2736 .Case("ip", ARM::R12)
2737 // Additional register name aliases for 'gas' compatibility.
2738 .Case("a1", ARM::R0)
2739 .Case("a2", ARM::R1)
2740 .Case("a3", ARM::R2)
2741 .Case("a4", ARM::R3)
2742 .Case("v1", ARM::R4)
2743 .Case("v2", ARM::R5)
2744 .Case("v3", ARM::R6)
2745 .Case("v4", ARM::R7)
2746 .Case("v5", ARM::R8)
2747 .Case("v6", ARM::R9)
2748 .Case("v7", ARM::R10)
2749 .Case("v8", ARM::R11)
2750 .Case("sb", ARM::R9)
2751 .Case("sl", ARM::R10)
2752 .Case("fp", ARM::R11)
2756 // Check for aliases registered via .req. Canonicalize to lower case.
2757 // That's more consistent since register names are case insensitive, and
2758 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2759 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2760 // If no match, return failure.
2761 if (Entry == RegisterReqs.end())
2763 Parser.Lex(); // Eat identifier token.
2764 return Entry->getValue();
2767 Parser.Lex(); // Eat identifier token.
2772 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
2773 // If a recoverable error occurs, return 1. If an irrecoverable error
2774 // occurs, return -1. An irrecoverable error is one where tokens have been
2775 // consumed in the process of trying to parse the shifter (i.e., when it is
2776 // indeed a shifter operand, but malformed).
2777 int ARMAsmParser::tryParseShiftRegister(
2778 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2779 SMLoc S = Parser.getTok().getLoc();
2780 const AsmToken &Tok = Parser.getTok();
2781 if (Tok.isNot(AsmToken::Identifier))
2784 std::string lowerCase = Tok.getString().lower();
2785 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
2786 .Case("asl", ARM_AM::lsl)
2787 .Case("lsl", ARM_AM::lsl)
2788 .Case("lsr", ARM_AM::lsr)
2789 .Case("asr", ARM_AM::asr)
2790 .Case("ror", ARM_AM::ror)
2791 .Case("rrx", ARM_AM::rrx)
2792 .Default(ARM_AM::no_shift);
2794 if (ShiftTy == ARM_AM::no_shift)
2797 Parser.Lex(); // Eat the operator.
2799 // The source register for the shift has already been added to the
2800 // operand list, so we need to pop it off and combine it into the shifted
2801 // register operand instead.
2802 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
2803 if (!PrevOp->isReg())
2804 return Error(PrevOp->getStartLoc(), "shift must be of a register");
2805 int SrcReg = PrevOp->getReg();
2810 if (ShiftTy == ARM_AM::rrx) {
2811 // RRX Doesn't have an explicit shift amount. The encoder expects
2812 // the shift register to be the same as the source register. Seems odd,
2816 // Figure out if this is shifted by a constant or a register (for non-RRX).
2817 if (Parser.getTok().is(AsmToken::Hash) ||
2818 Parser.getTok().is(AsmToken::Dollar)) {
2819 Parser.Lex(); // Eat hash.
2820 SMLoc ImmLoc = Parser.getTok().getLoc();
2821 const MCExpr *ShiftExpr = 0;
2822 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
2823 Error(ImmLoc, "invalid immediate shift value");
2826 // The expression must be evaluatable as an immediate.
2827 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
2829 Error(ImmLoc, "invalid immediate shift value");
2832 // Range check the immediate.
2833 // lsl, ror: 0 <= imm <= 31
2834 // lsr, asr: 0 <= imm <= 32
2835 Imm = CE->getValue();
2837 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
2838 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
2839 Error(ImmLoc, "immediate shift value out of range");
2842 // shift by zero is a nop. Always send it through as lsl.
2843 // ('as' compatibility)
2845 ShiftTy = ARM_AM::lsl;
2846 } else if (Parser.getTok().is(AsmToken::Identifier)) {
2847 SMLoc L = Parser.getTok().getLoc();
2848 EndLoc = Parser.getTok().getEndLoc();
2849 ShiftReg = tryParseRegister();
2850 if (ShiftReg == -1) {
2851 Error (L, "expected immediate or register in shift operand");
2855 Error (Parser.getTok().getLoc(),
2856 "expected immediate or register in shift operand");
2861 if (ShiftReg && ShiftTy != ARM_AM::rrx)
2862 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
2866 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
2873 /// Try to parse a register name. The token must be an Identifier when called.
2874 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
2875 /// if there is a "writeback". 'true' if it's not a register.
2877 /// TODO this is likely to change to allow different register types and or to
2878 /// parse for a specific register type.
2880 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2881 const AsmToken &RegTok = Parser.getTok();
2882 int RegNo = tryParseRegister();
2886 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
2887 RegTok.getEndLoc()));
2889 const AsmToken &ExclaimTok = Parser.getTok();
2890 if (ExclaimTok.is(AsmToken::Exclaim)) {
2891 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
2892 ExclaimTok.getLoc()));
2893 Parser.Lex(); // Eat exclaim token
2897 // Also check for an index operand. This is only legal for vector registers,
2898 // but that'll get caught OK in operand matching, so we don't need to
2899 // explicitly filter everything else out here.
2900 if (Parser.getTok().is(AsmToken::LBrac)) {
2901 SMLoc SIdx = Parser.getTok().getLoc();
2902 Parser.Lex(); // Eat left bracket token.
2904 const MCExpr *ImmVal;
2905 if (getParser().parseExpression(ImmVal))
2907 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
2909 return TokError("immediate value expected for vector index");
2911 if (Parser.getTok().isNot(AsmToken::RBrac))
2912 return Error(Parser.getTok().getLoc(), "']' expected");
2914 SMLoc E = Parser.getTok().getEndLoc();
2915 Parser.Lex(); // Eat right bracket token.
2917 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
2925 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
2926 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
2928 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
2929 // Use the same layout as the tablegen'erated register name matcher. Ugly,
2931 switch (Name.size()) {
2934 if (Name[0] != CoprocOp)
2950 if (Name[0] != CoprocOp || Name[1] != '1')
2954 // p10 and p11 are invalid for coproc instructions (reserved for FP/NEON)
2955 case '0': return CoprocOp == 'p'? -1: 10;
2956 case '1': return CoprocOp == 'p'? -1: 11;
2957 case '2': return 12;
2958 case '3': return 13;
2959 case '4': return 14;
2960 case '5': return 15;
2965 /// parseITCondCode - Try to parse a condition code for an IT instruction.
2966 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2967 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2968 SMLoc S = Parser.getTok().getLoc();
2969 const AsmToken &Tok = Parser.getTok();
2970 if (!Tok.is(AsmToken::Identifier))
2971 return MatchOperand_NoMatch;
2972 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
2973 .Case("eq", ARMCC::EQ)
2974 .Case("ne", ARMCC::NE)
2975 .Case("hs", ARMCC::HS)
2976 .Case("cs", ARMCC::HS)
2977 .Case("lo", ARMCC::LO)
2978 .Case("cc", ARMCC::LO)
2979 .Case("mi", ARMCC::MI)
2980 .Case("pl", ARMCC::PL)
2981 .Case("vs", ARMCC::VS)
2982 .Case("vc", ARMCC::VC)
2983 .Case("hi", ARMCC::HI)
2984 .Case("ls", ARMCC::LS)
2985 .Case("ge", ARMCC::GE)
2986 .Case("lt", ARMCC::LT)
2987 .Case("gt", ARMCC::GT)
2988 .Case("le", ARMCC::LE)
2989 .Case("al", ARMCC::AL)
2992 return MatchOperand_NoMatch;
2993 Parser.Lex(); // Eat the token.
2995 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
2997 return MatchOperand_Success;
3000 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3001 /// token must be an Identifier when called, and if it is a coprocessor
3002 /// number, the token is eaten and the operand is added to the operand list.
3003 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3004 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3005 SMLoc S = Parser.getTok().getLoc();
3006 const AsmToken &Tok = Parser.getTok();
3007 if (Tok.isNot(AsmToken::Identifier))
3008 return MatchOperand_NoMatch;
3010 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3012 return MatchOperand_NoMatch;
3014 Parser.Lex(); // Eat identifier token.
3015 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3016 return MatchOperand_Success;
3019 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3020 /// token must be an Identifier when called, and if it is a coprocessor
3021 /// number, the token is eaten and the operand is added to the operand list.
3022 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3023 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3024 SMLoc S = Parser.getTok().getLoc();
3025 const AsmToken &Tok = Parser.getTok();
3026 if (Tok.isNot(AsmToken::Identifier))
3027 return MatchOperand_NoMatch;
3029 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3031 return MatchOperand_NoMatch;
3033 Parser.Lex(); // Eat identifier token.
3034 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3035 return MatchOperand_Success;
3038 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3039 /// coproc_option : '{' imm0_255 '}'
3040 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3041 parseCoprocOptionOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3042 SMLoc S = Parser.getTok().getLoc();
3044 // If this isn't a '{', this isn't a coprocessor immediate operand.
3045 if (Parser.getTok().isNot(AsmToken::LCurly))
3046 return MatchOperand_NoMatch;
3047 Parser.Lex(); // Eat the '{'
3050 SMLoc Loc = Parser.getTok().getLoc();
3051 if (getParser().parseExpression(Expr)) {
3052 Error(Loc, "illegal expression");
3053 return MatchOperand_ParseFail;
3055 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3056 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3057 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3058 return MatchOperand_ParseFail;
3060 int Val = CE->getValue();
3062 // Check for and consume the closing '}'
3063 if (Parser.getTok().isNot(AsmToken::RCurly))
3064 return MatchOperand_ParseFail;
3065 SMLoc E = Parser.getTok().getEndLoc();
3066 Parser.Lex(); // Eat the '}'
3068 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3069 return MatchOperand_Success;
3072 // For register list parsing, we need to map from raw GPR register numbering
3073 // to the enumeration values. The enumeration values aren't sorted by
3074 // register number due to our using "sp", "lr" and "pc" as canonical names.
3075 static unsigned getNextRegister(unsigned Reg) {
3076 // If this is a GPR, we need to do it manually, otherwise we can rely
3077 // on the sort ordering of the enumeration since the other reg-classes
3079 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3082 default: llvm_unreachable("Invalid GPR number!");
3083 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3084 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3085 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3086 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3087 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3088 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3089 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3090 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3094 // Return the low-subreg of a given Q register.
3095 static unsigned getDRegFromQReg(unsigned QReg) {
3097 default: llvm_unreachable("expected a Q register!");
3098 case ARM::Q0: return ARM::D0;
3099 case ARM::Q1: return ARM::D2;
3100 case ARM::Q2: return ARM::D4;
3101 case ARM::Q3: return ARM::D6;
3102 case ARM::Q4: return ARM::D8;
3103 case ARM::Q5: return ARM::D10;
3104 case ARM::Q6: return ARM::D12;
3105 case ARM::Q7: return ARM::D14;
3106 case ARM::Q8: return ARM::D16;
3107 case ARM::Q9: return ARM::D18;
3108 case ARM::Q10: return ARM::D20;
3109 case ARM::Q11: return ARM::D22;
3110 case ARM::Q12: return ARM::D24;
3111 case ARM::Q13: return ARM::D26;
3112 case ARM::Q14: return ARM::D28;
3113 case ARM::Q15: return ARM::D30;
3117 /// Parse a register list.
3119 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3120 assert(Parser.getTok().is(AsmToken::LCurly) &&
3121 "Token is not a Left Curly Brace");
3122 SMLoc S = Parser.getTok().getLoc();
3123 Parser.Lex(); // Eat '{' token.
3124 SMLoc RegLoc = Parser.getTok().getLoc();
3126 // Check the first register in the list to see what register class
3127 // this is a list of.
3128 int Reg = tryParseRegister();
3130 return Error(RegLoc, "register expected");
3132 // The reglist instructions have at most 16 registers, so reserve
3133 // space for that many.
3135 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3137 // Allow Q regs and just interpret them as the two D sub-registers.
3138 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3139 Reg = getDRegFromQReg(Reg);
3140 EReg = MRI->getEncodingValue(Reg);
3141 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3144 const MCRegisterClass *RC;
3145 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3146 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3147 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3148 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3149 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3150 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3152 return Error(RegLoc, "invalid register in register list");
3154 // Store the register.
3155 EReg = MRI->getEncodingValue(Reg);
3156 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3158 // This starts immediately after the first register token in the list,
3159 // so we can see either a comma or a minus (range separator) as a legal
3161 while (Parser.getTok().is(AsmToken::Comma) ||
3162 Parser.getTok().is(AsmToken::Minus)) {
3163 if (Parser.getTok().is(AsmToken::Minus)) {
3164 Parser.Lex(); // Eat the minus.
3165 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3166 int EndReg = tryParseRegister();
3168 return Error(AfterMinusLoc, "register expected");
3169 // Allow Q regs and just interpret them as the two D sub-registers.
3170 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3171 EndReg = getDRegFromQReg(EndReg) + 1;
3172 // If the register is the same as the start reg, there's nothing
3176 // The register must be in the same register class as the first.
3177 if (!RC->contains(EndReg))
3178 return Error(AfterMinusLoc, "invalid register in register list");
3179 // Ranges must go from low to high.
3180 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3181 return Error(AfterMinusLoc, "bad range in register list");
3183 // Add all the registers in the range to the register list.
3184 while (Reg != EndReg) {
3185 Reg = getNextRegister(Reg);
3186 EReg = MRI->getEncodingValue(Reg);
3187 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3191 Parser.Lex(); // Eat the comma.
3192 RegLoc = Parser.getTok().getLoc();
3194 const AsmToken RegTok = Parser.getTok();
3195 Reg = tryParseRegister();
3197 return Error(RegLoc, "register expected");
3198 // Allow Q regs and just interpret them as the two D sub-registers.
3199 bool isQReg = false;
3200 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3201 Reg = getDRegFromQReg(Reg);
3204 // The register must be in the same register class as the first.
3205 if (!RC->contains(Reg))
3206 return Error(RegLoc, "invalid register in register list");
3207 // List must be monotonically increasing.
3208 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3209 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3210 Warning(RegLoc, "register list not in ascending order");
3212 return Error(RegLoc, "register list not in ascending order");
3214 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3215 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3216 ") in register list");
3219 // VFP register lists must also be contiguous.
3220 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3222 return Error(RegLoc, "non-contiguous register range");
3223 EReg = MRI->getEncodingValue(Reg);
3224 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3226 EReg = MRI->getEncodingValue(++Reg);
3227 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3231 if (Parser.getTok().isNot(AsmToken::RCurly))
3232 return Error(Parser.getTok().getLoc(), "'}' expected");
3233 SMLoc E = Parser.getTok().getEndLoc();
3234 Parser.Lex(); // Eat '}' token.
3236 // Push the register list operand.
3237 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3239 // The ARM system instruction variants for LDM/STM have a '^' token here.
3240 if (Parser.getTok().is(AsmToken::Caret)) {
3241 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3242 Parser.Lex(); // Eat '^' token.
3248 // Helper function to parse the lane index for vector lists.
3249 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3250 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3251 Index = 0; // Always return a defined index value.
3252 if (Parser.getTok().is(AsmToken::LBrac)) {
3253 Parser.Lex(); // Eat the '['.
3254 if (Parser.getTok().is(AsmToken::RBrac)) {
3255 // "Dn[]" is the 'all lanes' syntax.
3256 LaneKind = AllLanes;
3257 EndLoc = Parser.getTok().getEndLoc();
3258 Parser.Lex(); // Eat the ']'.
3259 return MatchOperand_Success;
3262 // There's an optional '#' token here. Normally there wouldn't be, but
3263 // inline assemble puts one in, and it's friendly to accept that.
3264 if (Parser.getTok().is(AsmToken::Hash))
3265 Parser.Lex(); // Eat '#' or '$'.
3267 const MCExpr *LaneIndex;
3268 SMLoc Loc = Parser.getTok().getLoc();
3269 if (getParser().parseExpression(LaneIndex)) {
3270 Error(Loc, "illegal expression");
3271 return MatchOperand_ParseFail;
3273 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3275 Error(Loc, "lane index must be empty or an integer");
3276 return MatchOperand_ParseFail;
3278 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3279 Error(Parser.getTok().getLoc(), "']' expected");
3280 return MatchOperand_ParseFail;
3282 EndLoc = Parser.getTok().getEndLoc();
3283 Parser.Lex(); // Eat the ']'.
3284 int64_t Val = CE->getValue();
3286 // FIXME: Make this range check context sensitive for .8, .16, .32.
3287 if (Val < 0 || Val > 7) {
3288 Error(Parser.getTok().getLoc(), "lane index out of range");
3289 return MatchOperand_ParseFail;
3292 LaneKind = IndexedLane;
3293 return MatchOperand_Success;
3296 return MatchOperand_Success;
3299 // parse a vector register list
3300 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3301 parseVectorList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3302 VectorLaneTy LaneKind;
3304 SMLoc S = Parser.getTok().getLoc();
3305 // As an extension (to match gas), support a plain D register or Q register
3306 // (without encosing curly braces) as a single or double entry list,
3308 if (Parser.getTok().is(AsmToken::Identifier)) {
3309 SMLoc E = Parser.getTok().getEndLoc();
3310 int Reg = tryParseRegister();
3312 return MatchOperand_NoMatch;
3313 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3314 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3315 if (Res != MatchOperand_Success)
3319 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3322 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3326 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3331 return MatchOperand_Success;
3333 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3334 Reg = getDRegFromQReg(Reg);
3335 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3336 if (Res != MatchOperand_Success)
3340 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3341 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3342 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3345 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3346 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3347 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3351 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3356 return MatchOperand_Success;
3358 Error(S, "vector register expected");
3359 return MatchOperand_ParseFail;
3362 if (Parser.getTok().isNot(AsmToken::LCurly))
3363 return MatchOperand_NoMatch;
3365 Parser.Lex(); // Eat '{' token.
3366 SMLoc RegLoc = Parser.getTok().getLoc();
3368 int Reg = tryParseRegister();
3370 Error(RegLoc, "register expected");
3371 return MatchOperand_ParseFail;
3375 unsigned FirstReg = Reg;
3376 // The list is of D registers, but we also allow Q regs and just interpret
3377 // them as the two D sub-registers.
3378 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3379 FirstReg = Reg = getDRegFromQReg(Reg);
3380 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3381 // it's ambiguous with four-register single spaced.
3387 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3388 return MatchOperand_ParseFail;
3390 while (Parser.getTok().is(AsmToken::Comma) ||
3391 Parser.getTok().is(AsmToken::Minus)) {
3392 if (Parser.getTok().is(AsmToken::Minus)) {
3394 Spacing = 1; // Register range implies a single spaced list.
3395 else if (Spacing == 2) {
3396 Error(Parser.getTok().getLoc(),
3397 "sequential registers in double spaced list");
3398 return MatchOperand_ParseFail;
3400 Parser.Lex(); // Eat the minus.
3401 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3402 int EndReg = tryParseRegister();
3404 Error(AfterMinusLoc, "register expected");
3405 return MatchOperand_ParseFail;
3407 // Allow Q regs and just interpret them as the two D sub-registers.
3408 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3409 EndReg = getDRegFromQReg(EndReg) + 1;
3410 // If the register is the same as the start reg, there's nothing
3414 // The register must be in the same register class as the first.
3415 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3416 Error(AfterMinusLoc, "invalid register in register list");
3417 return MatchOperand_ParseFail;
3419 // Ranges must go from low to high.
3421 Error(AfterMinusLoc, "bad range in register list");
3422 return MatchOperand_ParseFail;
3424 // Parse the lane specifier if present.
3425 VectorLaneTy NextLaneKind;
3426 unsigned NextLaneIndex;
3427 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3428 MatchOperand_Success)
3429 return MatchOperand_ParseFail;
3430 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3431 Error(AfterMinusLoc, "mismatched lane index in register list");
3432 return MatchOperand_ParseFail;
3435 // Add all the registers in the range to the register list.
3436 Count += EndReg - Reg;
3440 Parser.Lex(); // Eat the comma.
3441 RegLoc = Parser.getTok().getLoc();
3443 Reg = tryParseRegister();
3445 Error(RegLoc, "register expected");
3446 return MatchOperand_ParseFail;
3448 // vector register lists must be contiguous.
3449 // It's OK to use the enumeration values directly here rather, as the
3450 // VFP register classes have the enum sorted properly.
3452 // The list is of D registers, but we also allow Q regs and just interpret
3453 // them as the two D sub-registers.
3454 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3456 Spacing = 1; // Register range implies a single spaced list.
3457 else if (Spacing == 2) {
3459 "invalid register in double-spaced list (must be 'D' register')");
3460 return MatchOperand_ParseFail;
3462 Reg = getDRegFromQReg(Reg);
3463 if (Reg != OldReg + 1) {
3464 Error(RegLoc, "non-contiguous register range");
3465 return MatchOperand_ParseFail;
3469 // Parse the lane specifier if present.
3470 VectorLaneTy NextLaneKind;
3471 unsigned NextLaneIndex;
3472 SMLoc LaneLoc = Parser.getTok().getLoc();
3473 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3474 MatchOperand_Success)
3475 return MatchOperand_ParseFail;
3476 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3477 Error(LaneLoc, "mismatched lane index in register list");
3478 return MatchOperand_ParseFail;
3482 // Normal D register.
3483 // Figure out the register spacing (single or double) of the list if
3484 // we don't know it already.
3486 Spacing = 1 + (Reg == OldReg + 2);
3488 // Just check that it's contiguous and keep going.
3489 if (Reg != OldReg + Spacing) {
3490 Error(RegLoc, "non-contiguous register range");
3491 return MatchOperand_ParseFail;
3494 // Parse the lane specifier if present.
3495 VectorLaneTy NextLaneKind;
3496 unsigned NextLaneIndex;
3497 SMLoc EndLoc = Parser.getTok().getLoc();
3498 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3499 return MatchOperand_ParseFail;
3500 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3501 Error(EndLoc, "mismatched lane index in register list");
3502 return MatchOperand_ParseFail;
3506 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3507 Error(Parser.getTok().getLoc(), "'}' expected");
3508 return MatchOperand_ParseFail;
3510 E = Parser.getTok().getEndLoc();
3511 Parser.Lex(); // Eat '}' token.
3515 // Two-register operands have been converted to the
3516 // composite register classes.
3518 const MCRegisterClass *RC = (Spacing == 1) ?
3519 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3520 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3521 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3524 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3525 (Spacing == 2), S, E));
3528 // Two-register operands have been converted to the
3529 // composite register classes.
3531 const MCRegisterClass *RC = (Spacing == 1) ?
3532 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3533 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3534 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3536 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3541 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3547 return MatchOperand_Success;
3550 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3551 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3552 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3553 SMLoc S = Parser.getTok().getLoc();
3554 const AsmToken &Tok = Parser.getTok();
3557 if (Tok.is(AsmToken::Identifier)) {
3558 StringRef OptStr = Tok.getString();
3560 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3561 .Case("sy", ARM_MB::SY)
3562 .Case("st", ARM_MB::ST)
3563 .Case("ld", ARM_MB::LD)
3564 .Case("sh", ARM_MB::ISH)
3565 .Case("ish", ARM_MB::ISH)
3566 .Case("shst", ARM_MB::ISHST)
3567 .Case("ishst", ARM_MB::ISHST)
3568 .Case("ishld", ARM_MB::ISHLD)
3569 .Case("nsh", ARM_MB::NSH)
3570 .Case("un", ARM_MB::NSH)
3571 .Case("nshst", ARM_MB::NSHST)
3572 .Case("nshld", ARM_MB::NSHLD)
3573 .Case("unst", ARM_MB::NSHST)
3574 .Case("osh", ARM_MB::OSH)
3575 .Case("oshst", ARM_MB::OSHST)
3576 .Case("oshld", ARM_MB::OSHLD)
3579 // ishld, oshld, nshld and ld are only available from ARMv8.
3580 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3581 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3585 return MatchOperand_NoMatch;
3587 Parser.Lex(); // Eat identifier token.
3588 } else if (Tok.is(AsmToken::Hash) ||
3589 Tok.is(AsmToken::Dollar) ||
3590 Tok.is(AsmToken::Integer)) {
3591 if (Parser.getTok().isNot(AsmToken::Integer))
3592 Parser.Lex(); // Eat '#' or '$'.
3593 SMLoc Loc = Parser.getTok().getLoc();
3595 const MCExpr *MemBarrierID;
3596 if (getParser().parseExpression(MemBarrierID)) {
3597 Error(Loc, "illegal expression");
3598 return MatchOperand_ParseFail;
3601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3603 Error(Loc, "constant expression expected");
3604 return MatchOperand_ParseFail;
3607 int Val = CE->getValue();
3609 Error(Loc, "immediate value out of range");
3610 return MatchOperand_ParseFail;
3613 Opt = ARM_MB::RESERVED_0 + Val;
3615 return MatchOperand_ParseFail;
3617 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3618 return MatchOperand_Success;
3621 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3622 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3623 parseInstSyncBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3624 SMLoc S = Parser.getTok().getLoc();
3625 const AsmToken &Tok = Parser.getTok();
3628 if (Tok.is(AsmToken::Identifier)) {
3629 StringRef OptStr = Tok.getString();
3631 if (OptStr.equals_lower("sy"))
3634 return MatchOperand_NoMatch;
3636 Parser.Lex(); // Eat identifier token.
3637 } else if (Tok.is(AsmToken::Hash) ||
3638 Tok.is(AsmToken::Dollar) ||
3639 Tok.is(AsmToken::Integer)) {
3640 if (Parser.getTok().isNot(AsmToken::Integer))
3641 Parser.Lex(); // Eat '#' or '$'.
3642 SMLoc Loc = Parser.getTok().getLoc();
3644 const MCExpr *ISBarrierID;
3645 if (getParser().parseExpression(ISBarrierID)) {
3646 Error(Loc, "illegal expression");
3647 return MatchOperand_ParseFail;
3650 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3652 Error(Loc, "constant expression expected");
3653 return MatchOperand_ParseFail;
3656 int Val = CE->getValue();
3658 Error(Loc, "immediate value out of range");
3659 return MatchOperand_ParseFail;
3662 Opt = ARM_ISB::RESERVED_0 + Val;
3664 return MatchOperand_ParseFail;
3666 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3667 (ARM_ISB::InstSyncBOpt)Opt, S));
3668 return MatchOperand_Success;
3672 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3673 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3674 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3675 SMLoc S = Parser.getTok().getLoc();
3676 const AsmToken &Tok = Parser.getTok();
3677 if (!Tok.is(AsmToken::Identifier))
3678 return MatchOperand_NoMatch;
3679 StringRef IFlagsStr = Tok.getString();
3681 // An iflags string of "none" is interpreted to mean that none of the AIF
3682 // bits are set. Not a terribly useful instruction, but a valid encoding.
3683 unsigned IFlags = 0;
3684 if (IFlagsStr != "none") {
3685 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3686 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3687 .Case("a", ARM_PROC::A)
3688 .Case("i", ARM_PROC::I)
3689 .Case("f", ARM_PROC::F)
3692 // If some specific iflag is already set, it means that some letter is
3693 // present more than once, this is not acceptable.
3694 if (Flag == ~0U || (IFlags & Flag))
3695 return MatchOperand_NoMatch;
3701 Parser.Lex(); // Eat identifier token.
3702 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3703 return MatchOperand_Success;
3706 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3707 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3708 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3709 SMLoc S = Parser.getTok().getLoc();
3710 const AsmToken &Tok = Parser.getTok();
3711 if (!Tok.is(AsmToken::Identifier))
3712 return MatchOperand_NoMatch;
3713 StringRef Mask = Tok.getString();
3716 // See ARMv6-M 10.1.1
3717 std::string Name = Mask.lower();
3718 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3719 // Note: in the documentation:
3720 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3721 // for MSR APSR_nzcvq.
3722 // but we do make it an alias here. This is so to get the "mask encoding"
3723 // bits correct on MSR APSR writes.
3725 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3726 // should really only be allowed when writing a special register. Note
3727 // they get dropped in the MRS instruction reading a special register as
3728 // the SYSm field is only 8 bits.
3730 // FIXME: the _g and _nzcvqg versions are only allowed if the processor
3731 // includes the DSP extension but that is not checked.
3732 .Case("apsr", 0x800)
3733 .Case("apsr_nzcvq", 0x800)
3734 .Case("apsr_g", 0x400)
3735 .Case("apsr_nzcvqg", 0xc00)
3736 .Case("iapsr", 0x801)
3737 .Case("iapsr_nzcvq", 0x801)
3738 .Case("iapsr_g", 0x401)
3739 .Case("iapsr_nzcvqg", 0xc01)
3740 .Case("eapsr", 0x802)
3741 .Case("eapsr_nzcvq", 0x802)
3742 .Case("eapsr_g", 0x402)
3743 .Case("eapsr_nzcvqg", 0xc02)
3744 .Case("xpsr", 0x803)
3745 .Case("xpsr_nzcvq", 0x803)
3746 .Case("xpsr_g", 0x403)
3747 .Case("xpsr_nzcvqg", 0xc03)
3748 .Case("ipsr", 0x805)
3749 .Case("epsr", 0x806)
3750 .Case("iepsr", 0x807)
3753 .Case("primask", 0x810)
3754 .Case("basepri", 0x811)
3755 .Case("basepri_max", 0x812)
3756 .Case("faultmask", 0x813)
3757 .Case("control", 0x814)
3760 if (FlagsVal == ~0U)
3761 return MatchOperand_NoMatch;
3763 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
3764 // basepri, basepri_max and faultmask only valid for V7m.
3765 return MatchOperand_NoMatch;
3767 Parser.Lex(); // Eat identifier token.
3768 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3769 return MatchOperand_Success;
3772 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
3773 size_t Start = 0, Next = Mask.find('_');
3774 StringRef Flags = "";
3775 std::string SpecReg = Mask.slice(Start, Next).lower();
3776 if (Next != StringRef::npos)
3777 Flags = Mask.slice(Next+1, Mask.size());
3779 // FlagsVal contains the complete mask:
3781 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3782 unsigned FlagsVal = 0;
3784 if (SpecReg == "apsr") {
3785 FlagsVal = StringSwitch<unsigned>(Flags)
3786 .Case("nzcvq", 0x8) // same as CPSR_f
3787 .Case("g", 0x4) // same as CPSR_s
3788 .Case("nzcvqg", 0xc) // same as CPSR_fs
3791 if (FlagsVal == ~0U) {
3793 return MatchOperand_NoMatch;
3795 FlagsVal = 8; // No flag
3797 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
3798 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
3799 if (Flags == "all" || Flags == "")
3801 for (int i = 0, e = Flags.size(); i != e; ++i) {
3802 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
3809 // If some specific flag is already set, it means that some letter is
3810 // present more than once, this is not acceptable.
3811 if (FlagsVal == ~0U || (FlagsVal & Flag))
3812 return MatchOperand_NoMatch;
3815 } else // No match for special register.
3816 return MatchOperand_NoMatch;
3818 // Special register without flags is NOT equivalent to "fc" flags.
3819 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
3820 // two lines would enable gas compatibility at the expense of breaking
3826 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
3827 if (SpecReg == "spsr")
3830 Parser.Lex(); // Eat identifier token.
3831 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
3832 return MatchOperand_Success;
3835 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3836 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
3837 int Low, int High) {
3838 const AsmToken &Tok = Parser.getTok();
3839 if (Tok.isNot(AsmToken::Identifier)) {
3840 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3841 return MatchOperand_ParseFail;
3843 StringRef ShiftName = Tok.getString();
3844 std::string LowerOp = Op.lower();
3845 std::string UpperOp = Op.upper();
3846 if (ShiftName != LowerOp && ShiftName != UpperOp) {
3847 Error(Parser.getTok().getLoc(), Op + " operand expected.");
3848 return MatchOperand_ParseFail;
3850 Parser.Lex(); // Eat shift type token.
3852 // There must be a '#' and a shift amount.
3853 if (Parser.getTok().isNot(AsmToken::Hash) &&
3854 Parser.getTok().isNot(AsmToken::Dollar)) {
3855 Error(Parser.getTok().getLoc(), "'#' expected");
3856 return MatchOperand_ParseFail;
3858 Parser.Lex(); // Eat hash token.
3860 const MCExpr *ShiftAmount;
3861 SMLoc Loc = Parser.getTok().getLoc();
3863 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3864 Error(Loc, "illegal expression");
3865 return MatchOperand_ParseFail;
3867 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3869 Error(Loc, "constant expression expected");
3870 return MatchOperand_ParseFail;
3872 int Val = CE->getValue();
3873 if (Val < Low || Val > High) {
3874 Error(Loc, "immediate value out of range");
3875 return MatchOperand_ParseFail;
3878 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
3880 return MatchOperand_Success;
3883 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3884 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3885 const AsmToken &Tok = Parser.getTok();
3886 SMLoc S = Tok.getLoc();
3887 if (Tok.isNot(AsmToken::Identifier)) {
3888 Error(S, "'be' or 'le' operand expected");
3889 return MatchOperand_ParseFail;
3891 int Val = StringSwitch<int>(Tok.getString().lower())
3895 Parser.Lex(); // Eat the token.
3898 Error(S, "'be' or 'le' operand expected");
3899 return MatchOperand_ParseFail;
3901 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
3903 S, Tok.getEndLoc()));
3904 return MatchOperand_Success;
3907 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
3908 /// instructions. Legal values are:
3909 /// lsl #n 'n' in [0,31]
3910 /// asr #n 'n' in [1,32]
3911 /// n == 32 encoded as n == 0.
3912 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3913 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3914 const AsmToken &Tok = Parser.getTok();
3915 SMLoc S = Tok.getLoc();
3916 if (Tok.isNot(AsmToken::Identifier)) {
3917 Error(S, "shift operator 'asr' or 'lsl' expected");
3918 return MatchOperand_ParseFail;
3920 StringRef ShiftName = Tok.getString();
3922 if (ShiftName == "lsl" || ShiftName == "LSL")
3924 else if (ShiftName == "asr" || ShiftName == "ASR")
3927 Error(S, "shift operator 'asr' or 'lsl' expected");
3928 return MatchOperand_ParseFail;
3930 Parser.Lex(); // Eat the operator.
3932 // A '#' and a shift amount.
3933 if (Parser.getTok().isNot(AsmToken::Hash) &&
3934 Parser.getTok().isNot(AsmToken::Dollar)) {
3935 Error(Parser.getTok().getLoc(), "'#' expected");
3936 return MatchOperand_ParseFail;
3938 Parser.Lex(); // Eat hash token.
3939 SMLoc ExLoc = Parser.getTok().getLoc();
3941 const MCExpr *ShiftAmount;
3943 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
3944 Error(ExLoc, "malformed shift expression");
3945 return MatchOperand_ParseFail;
3947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
3949 Error(ExLoc, "shift amount must be an immediate");
3950 return MatchOperand_ParseFail;
3953 int64_t Val = CE->getValue();
3955 // Shift amount must be in [1,32]
3956 if (Val < 1 || Val > 32) {
3957 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
3958 return MatchOperand_ParseFail;
3960 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
3961 if (isThumb() && Val == 32) {
3962 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
3963 return MatchOperand_ParseFail;
3965 if (Val == 32) Val = 0;
3967 // Shift amount must be in [1,32]
3968 if (Val < 0 || Val > 31) {
3969 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
3970 return MatchOperand_ParseFail;
3974 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
3976 return MatchOperand_Success;
3979 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
3980 /// of instructions. Legal values are:
3981 /// ror #n 'n' in {0, 8, 16, 24}
3982 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3983 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3984 const AsmToken &Tok = Parser.getTok();
3985 SMLoc S = Tok.getLoc();
3986 if (Tok.isNot(AsmToken::Identifier))
3987 return MatchOperand_NoMatch;
3988 StringRef ShiftName = Tok.getString();
3989 if (ShiftName != "ror" && ShiftName != "ROR")
3990 return MatchOperand_NoMatch;
3991 Parser.Lex(); // Eat the operator.
3993 // A '#' and a rotate amount.
3994 if (Parser.getTok().isNot(AsmToken::Hash) &&
3995 Parser.getTok().isNot(AsmToken::Dollar)) {
3996 Error(Parser.getTok().getLoc(), "'#' expected");
3997 return MatchOperand_ParseFail;
3999 Parser.Lex(); // Eat hash token.
4000 SMLoc ExLoc = Parser.getTok().getLoc();
4002 const MCExpr *ShiftAmount;
4004 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4005 Error(ExLoc, "malformed rotate expression");
4006 return MatchOperand_ParseFail;
4008 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4010 Error(ExLoc, "rotate amount must be an immediate");
4011 return MatchOperand_ParseFail;
4014 int64_t Val = CE->getValue();
4015 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4016 // normally, zero is represented in asm by omitting the rotate operand
4018 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4019 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4020 return MatchOperand_ParseFail;
4023 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4025 return MatchOperand_Success;
4028 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4029 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4030 SMLoc S = Parser.getTok().getLoc();
4031 // The bitfield descriptor is really two operands, the LSB and the width.
4032 if (Parser.getTok().isNot(AsmToken::Hash) &&
4033 Parser.getTok().isNot(AsmToken::Dollar)) {
4034 Error(Parser.getTok().getLoc(), "'#' expected");
4035 return MatchOperand_ParseFail;
4037 Parser.Lex(); // Eat hash token.
4039 const MCExpr *LSBExpr;
4040 SMLoc E = Parser.getTok().getLoc();
4041 if (getParser().parseExpression(LSBExpr)) {
4042 Error(E, "malformed immediate expression");
4043 return MatchOperand_ParseFail;
4045 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4047 Error(E, "'lsb' operand must be an immediate");
4048 return MatchOperand_ParseFail;
4051 int64_t LSB = CE->getValue();
4052 // The LSB must be in the range [0,31]
4053 if (LSB < 0 || LSB > 31) {
4054 Error(E, "'lsb' operand must be in the range [0,31]");
4055 return MatchOperand_ParseFail;
4057 E = Parser.getTok().getLoc();
4059 // Expect another immediate operand.
4060 if (Parser.getTok().isNot(AsmToken::Comma)) {
4061 Error(Parser.getTok().getLoc(), "too few operands");
4062 return MatchOperand_ParseFail;
4064 Parser.Lex(); // Eat hash token.
4065 if (Parser.getTok().isNot(AsmToken::Hash) &&
4066 Parser.getTok().isNot(AsmToken::Dollar)) {
4067 Error(Parser.getTok().getLoc(), "'#' expected");
4068 return MatchOperand_ParseFail;
4070 Parser.Lex(); // Eat hash token.
4072 const MCExpr *WidthExpr;
4074 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4075 Error(E, "malformed immediate expression");
4076 return MatchOperand_ParseFail;
4078 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4080 Error(E, "'width' operand must be an immediate");
4081 return MatchOperand_ParseFail;
4084 int64_t Width = CE->getValue();
4085 // The LSB must be in the range [1,32-lsb]
4086 if (Width < 1 || Width > 32 - LSB) {
4087 Error(E, "'width' operand must be in the range [1,32-lsb]");
4088 return MatchOperand_ParseFail;
4091 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4093 return MatchOperand_Success;
4096 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4097 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4098 // Check for a post-index addressing register operand. Specifically:
4099 // postidx_reg := '+' register {, shift}
4100 // | '-' register {, shift}
4101 // | register {, shift}
4103 // This method must return MatchOperand_NoMatch without consuming any tokens
4104 // in the case where there is no match, as other alternatives take other
4106 AsmToken Tok = Parser.getTok();
4107 SMLoc S = Tok.getLoc();
4108 bool haveEaten = false;
4110 if (Tok.is(AsmToken::Plus)) {
4111 Parser.Lex(); // Eat the '+' token.
4113 } else if (Tok.is(AsmToken::Minus)) {
4114 Parser.Lex(); // Eat the '-' token.
4119 SMLoc E = Parser.getTok().getEndLoc();
4120 int Reg = tryParseRegister();
4123 return MatchOperand_NoMatch;
4124 Error(Parser.getTok().getLoc(), "register expected");
4125 return MatchOperand_ParseFail;
4128 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4129 unsigned ShiftImm = 0;
4130 if (Parser.getTok().is(AsmToken::Comma)) {
4131 Parser.Lex(); // Eat the ','.
4132 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4133 return MatchOperand_ParseFail;
4135 // FIXME: Only approximates end...may include intervening whitespace.
4136 E = Parser.getTok().getLoc();
4139 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4142 return MatchOperand_Success;
4145 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4146 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4147 // Check for a post-index addressing register operand. Specifically:
4148 // am3offset := '+' register
4155 // This method must return MatchOperand_NoMatch without consuming any tokens
4156 // in the case where there is no match, as other alternatives take other
4158 AsmToken Tok = Parser.getTok();
4159 SMLoc S = Tok.getLoc();
4161 // Do immediates first, as we always parse those if we have a '#'.
4162 if (Parser.getTok().is(AsmToken::Hash) ||
4163 Parser.getTok().is(AsmToken::Dollar)) {
4164 Parser.Lex(); // Eat '#' or '$'.
4165 // Explicitly look for a '-', as we need to encode negative zero
4167 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4168 const MCExpr *Offset;
4170 if (getParser().parseExpression(Offset, E))
4171 return MatchOperand_ParseFail;
4172 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4174 Error(S, "constant expression expected");
4175 return MatchOperand_ParseFail;
4177 // Negative zero is encoded as the flag value INT32_MIN.
4178 int32_t Val = CE->getValue();
4179 if (isNegative && Val == 0)
4183 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4185 return MatchOperand_Success;
4189 bool haveEaten = false;
4191 if (Tok.is(AsmToken::Plus)) {
4192 Parser.Lex(); // Eat the '+' token.
4194 } else if (Tok.is(AsmToken::Minus)) {
4195 Parser.Lex(); // Eat the '-' token.
4200 Tok = Parser.getTok();
4201 int Reg = tryParseRegister();
4204 return MatchOperand_NoMatch;
4205 Error(Tok.getLoc(), "register expected");
4206 return MatchOperand_ParseFail;
4209 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4210 0, S, Tok.getEndLoc()));
4212 return MatchOperand_Success;
4215 /// Convert parsed operands to MCInst. Needed here because this instruction
4216 /// only has two register operands, but multiplication is commutative so
4217 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4219 cvtThumbMultiply(MCInst &Inst,
4220 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4221 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
4222 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
4223 // If we have a three-operand form, make sure to set Rn to be the operand
4224 // that isn't the same as Rd.
4226 if (Operands.size() == 6 &&
4227 ((ARMOperand*)Operands[4])->getReg() ==
4228 ((ARMOperand*)Operands[3])->getReg())
4230 ((ARMOperand*)Operands[RegOp])->addRegOperands(Inst, 1);
4231 Inst.addOperand(Inst.getOperand(0));
4232 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
4236 cvtThumbBranches(MCInst &Inst,
4237 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4238 int CondOp = -1, ImmOp = -1;
4239 switch(Inst.getOpcode()) {
4241 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4244 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4246 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4248 // first decide whether or not the branch should be conditional
4249 // by looking at it's location relative to an IT block
4251 // inside an IT block we cannot have any conditional branches. any
4252 // such instructions needs to be converted to unconditional form
4253 switch(Inst.getOpcode()) {
4254 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4255 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4258 // outside IT blocks we can only have unconditional branches with AL
4259 // condition code or conditional branches with non-AL condition code
4260 unsigned Cond = static_cast<ARMOperand*>(Operands[CondOp])->getCondCode();
4261 switch(Inst.getOpcode()) {
4264 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4268 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4273 // now decide on encoding size based on branch target range
4274 switch(Inst.getOpcode()) {
4275 // classify tB as either t2B or t1B based on range of immediate operand
4277 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4278 if(!op->isSignedOffset<11, 1>() && isThumbTwo())
4279 Inst.setOpcode(ARM::t2B);
4282 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4284 ARMOperand* op = static_cast<ARMOperand*>(Operands[ImmOp]);
4285 if(!op->isSignedOffset<8, 1>() && isThumbTwo())
4286 Inst.setOpcode(ARM::t2Bcc);
4290 ((ARMOperand*)Operands[ImmOp])->addImmOperands(Inst, 1);
4291 ((ARMOperand*)Operands[CondOp])->addCondCodeOperands(Inst, 2);
4294 /// Parse an ARM memory expression, return false if successful else return true
4295 /// or an error. The first token must be a '[' when called.
4297 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4299 assert(Parser.getTok().is(AsmToken::LBrac) &&
4300 "Token is not a Left Bracket");
4301 S = Parser.getTok().getLoc();
4302 Parser.Lex(); // Eat left bracket token.
4304 const AsmToken &BaseRegTok = Parser.getTok();
4305 int BaseRegNum = tryParseRegister();
4306 if (BaseRegNum == -1)
4307 return Error(BaseRegTok.getLoc(), "register expected");
4309 // The next token must either be a comma, a colon or a closing bracket.
4310 const AsmToken &Tok = Parser.getTok();
4311 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4312 !Tok.is(AsmToken::RBrac))
4313 return Error(Tok.getLoc(), "malformed memory operand");
4315 if (Tok.is(AsmToken::RBrac)) {
4316 E = Tok.getEndLoc();
4317 Parser.Lex(); // Eat right bracket token.
4319 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
4320 0, 0, false, S, E));
4322 // If there's a pre-indexing writeback marker, '!', just add it as a token
4323 // operand. It's rather odd, but syntactically valid.
4324 if (Parser.getTok().is(AsmToken::Exclaim)) {
4325 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4326 Parser.Lex(); // Eat the '!'.
4332 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4333 "Lost colon or comma in memory operand?!");
4334 if (Tok.is(AsmToken::Comma)) {
4335 Parser.Lex(); // Eat the comma.
4338 // If we have a ':', it's an alignment specifier.
4339 if (Parser.getTok().is(AsmToken::Colon)) {
4340 Parser.Lex(); // Eat the ':'.
4341 E = Parser.getTok().getLoc();
4344 if (getParser().parseExpression(Expr))
4347 // The expression has to be a constant. Memory references with relocations
4348 // don't come through here, as they use the <label> forms of the relevant
4350 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4352 return Error (E, "constant expression expected");
4355 switch (CE->getValue()) {
4358 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4359 case 16: Align = 2; break;
4360 case 32: Align = 4; break;
4361 case 64: Align = 8; break;
4362 case 128: Align = 16; break;
4363 case 256: Align = 32; break;
4366 // Now we should have the closing ']'
4367 if (Parser.getTok().isNot(AsmToken::RBrac))
4368 return Error(Parser.getTok().getLoc(), "']' expected");
4369 E = Parser.getTok().getEndLoc();
4370 Parser.Lex(); // Eat right bracket token.
4372 // Don't worry about range checking the value here. That's handled by
4373 // the is*() predicates.
4374 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0,
4375 ARM_AM::no_shift, 0, Align,
4378 // If there's a pre-indexing writeback marker, '!', just add it as a token
4380 if (Parser.getTok().is(AsmToken::Exclaim)) {
4381 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4382 Parser.Lex(); // Eat the '!'.
4388 // If we have a '#', it's an immediate offset, else assume it's a register
4389 // offset. Be friendly and also accept a plain integer (without a leading
4390 // hash) for gas compatibility.
4391 if (Parser.getTok().is(AsmToken::Hash) ||
4392 Parser.getTok().is(AsmToken::Dollar) ||
4393 Parser.getTok().is(AsmToken::Integer)) {
4394 if (Parser.getTok().isNot(AsmToken::Integer))
4395 Parser.Lex(); // Eat '#' or '$'.
4396 E = Parser.getTok().getLoc();
4398 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4399 const MCExpr *Offset;
4400 if (getParser().parseExpression(Offset))
4403 // The expression has to be a constant. Memory references with relocations
4404 // don't come through here, as they use the <label> forms of the relevant
4406 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4408 return Error (E, "constant expression expected");
4410 // If the constant was #-0, represent it as INT32_MIN.
4411 int32_t Val = CE->getValue();
4412 if (isNegative && Val == 0)
4413 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4415 // Now we should have the closing ']'
4416 if (Parser.getTok().isNot(AsmToken::RBrac))
4417 return Error(Parser.getTok().getLoc(), "']' expected");
4418 E = Parser.getTok().getEndLoc();
4419 Parser.Lex(); // Eat right bracket token.
4421 // Don't worry about range checking the value here. That's handled by
4422 // the is*() predicates.
4423 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4424 ARM_AM::no_shift, 0, 0,
4427 // If there's a pre-indexing writeback marker, '!', just add it as a token
4429 if (Parser.getTok().is(AsmToken::Exclaim)) {
4430 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4431 Parser.Lex(); // Eat the '!'.
4437 // The register offset is optionally preceded by a '+' or '-'
4438 bool isNegative = false;
4439 if (Parser.getTok().is(AsmToken::Minus)) {
4441 Parser.Lex(); // Eat the '-'.
4442 } else if (Parser.getTok().is(AsmToken::Plus)) {
4444 Parser.Lex(); // Eat the '+'.
4447 E = Parser.getTok().getLoc();
4448 int OffsetRegNum = tryParseRegister();
4449 if (OffsetRegNum == -1)
4450 return Error(E, "register expected");
4452 // If there's a shift operator, handle it.
4453 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4454 unsigned ShiftImm = 0;
4455 if (Parser.getTok().is(AsmToken::Comma)) {
4456 Parser.Lex(); // Eat the ','.
4457 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4461 // Now we should have the closing ']'
4462 if (Parser.getTok().isNot(AsmToken::RBrac))
4463 return Error(Parser.getTok().getLoc(), "']' expected");
4464 E = Parser.getTok().getEndLoc();
4465 Parser.Lex(); // Eat right bracket token.
4467 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
4468 ShiftType, ShiftImm, 0, isNegative,
4471 // If there's a pre-indexing writeback marker, '!', just add it as a token
4473 if (Parser.getTok().is(AsmToken::Exclaim)) {
4474 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4475 Parser.Lex(); // Eat the '!'.
4481 /// parseMemRegOffsetShift - one of these two:
4482 /// ( lsl | lsr | asr | ror ) , # shift_amount
4484 /// return true if it parses a shift otherwise it returns false.
4485 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4487 SMLoc Loc = Parser.getTok().getLoc();
4488 const AsmToken &Tok = Parser.getTok();
4489 if (Tok.isNot(AsmToken::Identifier))
4491 StringRef ShiftName = Tok.getString();
4492 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4493 ShiftName == "asl" || ShiftName == "ASL")
4495 else if (ShiftName == "lsr" || ShiftName == "LSR")
4497 else if (ShiftName == "asr" || ShiftName == "ASR")
4499 else if (ShiftName == "ror" || ShiftName == "ROR")
4501 else if (ShiftName == "rrx" || ShiftName == "RRX")
4504 return Error(Loc, "illegal shift operator");
4505 Parser.Lex(); // Eat shift type token.
4507 // rrx stands alone.
4509 if (St != ARM_AM::rrx) {
4510 Loc = Parser.getTok().getLoc();
4511 // A '#' and a shift amount.
4512 const AsmToken &HashTok = Parser.getTok();
4513 if (HashTok.isNot(AsmToken::Hash) &&
4514 HashTok.isNot(AsmToken::Dollar))
4515 return Error(HashTok.getLoc(), "'#' expected");
4516 Parser.Lex(); // Eat hash token.
4519 if (getParser().parseExpression(Expr))
4521 // Range check the immediate.
4522 // lsl, ror: 0 <= imm <= 31
4523 // lsr, asr: 0 <= imm <= 32
4524 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4526 return Error(Loc, "shift amount must be an immediate");
4527 int64_t Imm = CE->getValue();
4529 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4530 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4531 return Error(Loc, "immediate shift value out of range");
4532 // If <ShiftTy> #0, turn it into a no_shift.
4535 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4544 /// parseFPImm - A floating point immediate expression operand.
4545 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
4546 parseFPImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4547 // Anything that can accept a floating point constant as an operand
4548 // needs to go through here, as the regular parseExpression is
4551 // This routine still creates a generic Immediate operand, containing
4552 // a bitcast of the 64-bit floating point value. The various operands
4553 // that accept floats can check whether the value is valid for them
4554 // via the standard is*() predicates.
4556 SMLoc S = Parser.getTok().getLoc();
4558 if (Parser.getTok().isNot(AsmToken::Hash) &&
4559 Parser.getTok().isNot(AsmToken::Dollar))
4560 return MatchOperand_NoMatch;
4562 // Disambiguate the VMOV forms that can accept an FP immediate.
4563 // vmov.f32 <sreg>, #imm
4564 // vmov.f64 <dreg>, #imm
4565 // vmov.f32 <dreg>, #imm @ vector f32x2
4566 // vmov.f32 <qreg>, #imm @ vector f32x4
4568 // There are also the NEON VMOV instructions which expect an
4569 // integer constant. Make sure we don't try to parse an FPImm
4571 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
4572 ARMOperand *TyOp = static_cast<ARMOperand*>(Operands[2]);
4573 bool isVmovf = TyOp->isToken() && (TyOp->getToken() == ".f32" ||
4574 TyOp->getToken() == ".f64");
4575 ARMOperand *Mnemonic = static_cast<ARMOperand*>(Operands[0]);
4576 bool isFconst = Mnemonic->isToken() && (Mnemonic->getToken() == "fconstd" ||
4577 Mnemonic->getToken() == "fconsts");
4578 if (!(isVmovf || isFconst))
4579 return MatchOperand_NoMatch;
4581 Parser.Lex(); // Eat '#' or '$'.
4583 // Handle negation, as that still comes through as a separate token.
4584 bool isNegative = false;
4585 if (Parser.getTok().is(AsmToken::Minus)) {
4589 const AsmToken &Tok = Parser.getTok();
4590 SMLoc Loc = Tok.getLoc();
4591 if (Tok.is(AsmToken::Real) && isVmovf) {
4592 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
4593 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
4594 // If we had a '-' in front, toggle the sign bit.
4595 IntVal ^= (uint64_t)isNegative << 31;
4596 Parser.Lex(); // Eat the token.
4597 Operands.push_back(ARMOperand::CreateImm(
4598 MCConstantExpr::Create(IntVal, getContext()),
4599 S, Parser.getTok().getLoc()));
4600 return MatchOperand_Success;
4602 // Also handle plain integers. Instructions which allow floating point
4603 // immediates also allow a raw encoded 8-bit value.
4604 if (Tok.is(AsmToken::Integer) && isFconst) {
4605 int64_t Val = Tok.getIntVal();
4606 Parser.Lex(); // Eat the token.
4607 if (Val > 255 || Val < 0) {
4608 Error(Loc, "encoded floating point value out of range");
4609 return MatchOperand_ParseFail;
4611 float RealVal = ARM_AM::getFPImmFloat(Val);
4612 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
4614 Operands.push_back(ARMOperand::CreateImm(
4615 MCConstantExpr::Create(Val, getContext()), S,
4616 Parser.getTok().getLoc()));
4617 return MatchOperand_Success;
4620 Error(Loc, "invalid floating point immediate");
4621 return MatchOperand_ParseFail;
4624 /// Parse a arm instruction operand. For now this parses the operand regardless
4625 /// of the mnemonic.
4626 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
4627 StringRef Mnemonic) {
4630 // Check if the current operand has a custom associated parser, if so, try to
4631 // custom parse the operand, or fallback to the general approach.
4632 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
4633 if (ResTy == MatchOperand_Success)
4635 // If there wasn't a custom match, try the generic matcher below. Otherwise,
4636 // there was a match, but an error occurred, in which case, just return that
4637 // the operand parsing failed.
4638 if (ResTy == MatchOperand_ParseFail)
4641 switch (getLexer().getKind()) {
4643 Error(Parser.getTok().getLoc(), "unexpected token in operand");
4645 case AsmToken::Identifier: {
4646 // If we've seen a branch mnemonic, the next operand must be a label. This
4647 // is true even if the label is a register name. So "br r1" means branch to
4649 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
4651 if (!tryParseRegisterWithWriteBack(Operands))
4653 int Res = tryParseShiftRegister(Operands);
4654 if (Res == 0) // success
4656 else if (Res == -1) // irrecoverable error
4658 // If this is VMRS, check for the apsr_nzcv operand.
4659 if (Mnemonic == "vmrs" &&
4660 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
4661 S = Parser.getTok().getLoc();
4663 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
4668 // Fall though for the Identifier case that is not a register or a
4671 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
4672 case AsmToken::Integer: // things like 1f and 2b as a branch targets
4673 case AsmToken::String: // quoted label names.
4674 case AsmToken::Dot: { // . as a branch target
4675 // This was not a register so parse other operands that start with an
4676 // identifier (like labels) as expressions and create them as immediates.
4677 const MCExpr *IdVal;
4678 S = Parser.getTok().getLoc();
4679 if (getParser().parseExpression(IdVal))
4681 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4682 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
4685 case AsmToken::LBrac:
4686 return parseMemory(Operands);
4687 case AsmToken::LCurly:
4688 return parseRegisterList(Operands);
4689 case AsmToken::Dollar:
4690 case AsmToken::Hash: {
4691 // #42 -> immediate.
4692 S = Parser.getTok().getLoc();
4695 if (Parser.getTok().isNot(AsmToken::Colon)) {
4696 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4697 const MCExpr *ImmVal;
4698 if (getParser().parseExpression(ImmVal))
4700 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
4702 int32_t Val = CE->getValue();
4703 if (isNegative && Val == 0)
4704 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
4706 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4707 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
4709 // There can be a trailing '!' on operands that we want as a separate
4710 // '!' Token operand. Handle that here. For example, the compatibility
4711 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
4712 if (Parser.getTok().is(AsmToken::Exclaim)) {
4713 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
4714 Parser.getTok().getLoc()));
4715 Parser.Lex(); // Eat exclaim token
4719 // w/ a ':' after the '#', it's just like a plain ':'.
4722 case AsmToken::Colon: {
4723 // ":lower16:" and ":upper16:" expression prefixes
4724 // FIXME: Check it's an expression prefix,
4725 // e.g. (FOO - :lower16:BAR) isn't legal.
4726 ARMMCExpr::VariantKind RefKind;
4727 if (parsePrefix(RefKind))
4730 const MCExpr *SubExprVal;
4731 if (getParser().parseExpression(SubExprVal))
4734 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
4736 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4737 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
4740 case AsmToken::Equal: {
4741 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
4742 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
4744 Parser.Lex(); // Eat '='
4745 const MCExpr *SubExprVal;
4746 if (getParser().parseExpression(SubExprVal))
4748 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
4750 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
4751 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
4757 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
4758 // :lower16: and :upper16:.
4759 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
4760 RefKind = ARMMCExpr::VK_ARM_None;
4762 // consume an optional '#' (GNU compatibility)
4763 if (getLexer().is(AsmToken::Hash))
4766 // :lower16: and :upper16: modifiers
4767 assert(getLexer().is(AsmToken::Colon) && "expected a :");
4768 Parser.Lex(); // Eat ':'
4770 if (getLexer().isNot(AsmToken::Identifier)) {
4771 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
4775 StringRef IDVal = Parser.getTok().getIdentifier();
4776 if (IDVal == "lower16") {
4777 RefKind = ARMMCExpr::VK_ARM_LO16;
4778 } else if (IDVal == "upper16") {
4779 RefKind = ARMMCExpr::VK_ARM_HI16;
4781 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
4786 if (getLexer().isNot(AsmToken::Colon)) {
4787 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
4790 Parser.Lex(); // Eat the last ':'
4794 /// \brief Given a mnemonic, split out possible predication code and carry
4795 /// setting letters to form a canonical mnemonic and flags.
4797 // FIXME: Would be nice to autogen this.
4798 // FIXME: This is a bit of a maze of special cases.
4799 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
4800 unsigned &PredicationCode,
4802 unsigned &ProcessorIMod,
4803 StringRef &ITMask) {
4804 PredicationCode = ARMCC::AL;
4805 CarrySetting = false;
4808 // Ignore some mnemonics we know aren't predicated forms.
4810 // FIXME: Would be nice to autogen this.
4811 if ((Mnemonic == "movs" && isThumb()) ||
4812 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
4813 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
4814 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
4815 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
4816 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
4817 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
4818 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
4819 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
4820 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
4821 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
4822 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
4823 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic.startswith("vsel"))
4826 // First, split out any predication code. Ignore mnemonics we know aren't
4827 // predicated but do have a carry-set and so weren't caught above.
4828 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
4829 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
4830 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
4831 Mnemonic != "sbcs" && Mnemonic != "rscs") {
4832 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
4833 .Case("eq", ARMCC::EQ)
4834 .Case("ne", ARMCC::NE)
4835 .Case("hs", ARMCC::HS)
4836 .Case("cs", ARMCC::HS)
4837 .Case("lo", ARMCC::LO)
4838 .Case("cc", ARMCC::LO)
4839 .Case("mi", ARMCC::MI)
4840 .Case("pl", ARMCC::PL)
4841 .Case("vs", ARMCC::VS)
4842 .Case("vc", ARMCC::VC)
4843 .Case("hi", ARMCC::HI)
4844 .Case("ls", ARMCC::LS)
4845 .Case("ge", ARMCC::GE)
4846 .Case("lt", ARMCC::LT)
4847 .Case("gt", ARMCC::GT)
4848 .Case("le", ARMCC::LE)
4849 .Case("al", ARMCC::AL)
4852 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
4853 PredicationCode = CC;
4857 // Next, determine if we have a carry setting bit. We explicitly ignore all
4858 // the instructions we know end in 's'.
4859 if (Mnemonic.endswith("s") &&
4860 !(Mnemonic == "cps" || Mnemonic == "mls" ||
4861 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
4862 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
4863 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
4864 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
4865 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
4866 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
4867 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
4868 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
4869 (Mnemonic == "movs" && isThumb()))) {
4870 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
4871 CarrySetting = true;
4874 // The "cps" instruction can have a interrupt mode operand which is glued into
4875 // the mnemonic. Check if this is the case, split it and parse the imod op
4876 if (Mnemonic.startswith("cps")) {
4877 // Split out any imod code.
4879 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
4880 .Case("ie", ARM_PROC::IE)
4881 .Case("id", ARM_PROC::ID)
4884 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
4885 ProcessorIMod = IMod;
4889 // The "it" instruction has the condition mask on the end of the mnemonic.
4890 if (Mnemonic.startswith("it")) {
4891 ITMask = Mnemonic.slice(2, Mnemonic.size());
4892 Mnemonic = Mnemonic.slice(0, 2);
4898 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
4899 /// inclusion of carry set or predication code operands.
4901 // FIXME: It would be nice to autogen this.
4903 getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
4904 bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) {
4905 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
4906 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
4907 Mnemonic == "add" || Mnemonic == "adc" ||
4908 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
4909 Mnemonic == "orr" || Mnemonic == "mvn" ||
4910 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
4911 Mnemonic == "sbc" || Mnemonic == "eor" || Mnemonic == "neg" ||
4912 Mnemonic == "vfm" || Mnemonic == "vfnm" ||
4913 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
4914 Mnemonic == "mla" || Mnemonic == "smlal" ||
4915 Mnemonic == "umlal" || Mnemonic == "umull"))) {
4916 CanAcceptCarrySet = true;
4918 CanAcceptCarrySet = false;
4920 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
4921 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
4922 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic.startswith("crc32") ||
4923 Mnemonic.startswith("cps") || Mnemonic.startswith("vsel") ||
4924 Mnemonic == "vmaxnm" || Mnemonic == "vminnm" || Mnemonic == "vcvta" ||
4925 Mnemonic == "vcvtn" || Mnemonic == "vcvtp" || Mnemonic == "vcvtm" ||
4926 Mnemonic == "vrinta" || Mnemonic == "vrintn" || Mnemonic == "vrintp" ||
4927 Mnemonic == "vrintm" || Mnemonic.startswith("aes") ||
4928 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
4929 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
4930 // These mnemonics are never predicable
4931 CanAcceptPredicationCode = false;
4932 } else if (!isThumb()) {
4933 // Some instructions are only predicable in Thumb mode
4934 CanAcceptPredicationCode
4935 = Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
4936 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
4937 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
4938 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
4939 Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
4940 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
4941 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
4942 } else if (isThumbOne()) {
4944 CanAcceptPredicationCode = Mnemonic != "movs";
4946 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
4948 CanAcceptPredicationCode = true;
4951 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
4952 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
4953 // FIXME: This is all horribly hacky. We really need a better way to deal
4954 // with optional operands like this in the matcher table.
4956 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
4957 // another does not. Specifically, the MOVW instruction does not. So we
4958 // special case it here and remove the defaulted (non-setting) cc_out
4959 // operand if that's the instruction we're trying to match.
4961 // We do this as post-processing of the explicit operands rather than just
4962 // conditionally adding the cc_out in the first place because we need
4963 // to check the type of the parsed immediate operand.
4964 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
4965 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
4966 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
4967 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4970 // Register-register 'add' for thumb does not have a cc_out operand
4971 // when there are only two register operands.
4972 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
4973 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4974 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4975 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
4977 // Register-register 'add' for thumb does not have a cc_out operand
4978 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
4979 // have to check the immediate range here since Thumb2 has a variant
4980 // that can handle a different range and has a cc_out operand.
4981 if (((isThumb() && Mnemonic == "add") ||
4982 (isThumbTwo() && Mnemonic == "sub")) &&
4983 Operands.size() == 6 &&
4984 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4985 static_cast<ARMOperand*>(Operands[4])->isReg() &&
4986 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
4987 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
4988 ((Mnemonic == "add" &&static_cast<ARMOperand*>(Operands[5])->isReg()) ||
4989 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
4991 // For Thumb2, add/sub immediate does not have a cc_out operand for the
4992 // imm0_4095 variant. That's the least-preferred variant when
4993 // selecting via the generic "add" mnemonic, so to know that we
4994 // should remove the cc_out operand, we have to explicitly check that
4995 // it's not one of the other variants. Ugh.
4996 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
4997 Operands.size() == 6 &&
4998 static_cast<ARMOperand*>(Operands[3])->isReg() &&
4999 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5000 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5001 // Nest conditions rather than one big 'if' statement for readability.
5003 // If both registers are low, we're in an IT block, and the immediate is
5004 // in range, we should use encoding T1 instead, which has a cc_out.
5006 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
5007 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
5008 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
5010 // Check against T3. If the second register is the PC, this is an
5011 // alternate form of ADR, which uses encoding T4, so check for that too.
5012 if (static_cast<ARMOperand*>(Operands[4])->getReg() != ARM::PC &&
5013 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
5016 // Otherwise, we use encoding T4, which does not have a cc_out
5021 // The thumb2 multiply instruction doesn't have a CCOut register, so
5022 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5023 // use the 16-bit encoding or not.
5024 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5025 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5026 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5027 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5028 static_cast<ARMOperand*>(Operands[5])->isReg() &&
5029 // If the registers aren't low regs, the destination reg isn't the
5030 // same as one of the source regs, or the cc_out operand is zero
5031 // outside of an IT block, we have to use the 32-bit encoding, so
5032 // remove the cc_out operand.
5033 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5034 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5035 !isARMLowRegister(static_cast<ARMOperand*>(Operands[5])->getReg()) ||
5037 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
5038 static_cast<ARMOperand*>(Operands[5])->getReg() &&
5039 static_cast<ARMOperand*>(Operands[3])->getReg() !=
5040 static_cast<ARMOperand*>(Operands[4])->getReg())))
5043 // Also check the 'mul' syntax variant that doesn't specify an explicit
5044 // destination register.
5045 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5046 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5047 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5048 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5049 // If the registers aren't low regs or the cc_out operand is zero
5050 // outside of an IT block, we have to use the 32-bit encoding, so
5051 // remove the cc_out operand.
5052 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
5053 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
5059 // Register-register 'add/sub' for thumb does not have a cc_out operand
5060 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5061 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5062 // right, this will result in better diagnostics (which operand is off)
5064 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5065 (Operands.size() == 5 || Operands.size() == 6) &&
5066 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5067 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
5068 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
5069 (static_cast<ARMOperand*>(Operands[4])->isImm() ||
5070 (Operands.size() == 6 &&
5071 static_cast<ARMOperand*>(Operands[5])->isImm())))
5077 bool ARMAsmParser::shouldOmitPredicateOperand(
5078 StringRef Mnemonic, SmallVectorImpl<MCParsedAsmOperand *> &Operands) {
5079 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5080 unsigned RegIdx = 3;
5081 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5082 static_cast<ARMOperand *>(Operands[2])->getToken() == ".f32") {
5083 if (static_cast<ARMOperand *>(Operands[3])->isToken() &&
5084 static_cast<ARMOperand *>(Operands[3])->getToken() == ".f32")
5087 if (static_cast<ARMOperand *>(Operands[RegIdx])->isReg() &&
5088 (ARMMCRegisterClasses[ARM::DPRRegClassID]
5089 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg()) ||
5090 ARMMCRegisterClasses[ARM::QPRRegClassID]
5091 .contains(static_cast<ARMOperand *>(Operands[RegIdx])->getReg())))
5097 static bool isDataTypeToken(StringRef Tok) {
5098 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5099 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5100 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5101 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5102 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5103 Tok == ".f" || Tok == ".d";
5106 // FIXME: This bit should probably be handled via an explicit match class
5107 // in the .td files that matches the suffix instead of having it be
5108 // a literal string token the way it is now.
5109 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5110 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5112 static void applyMnemonicAliases(StringRef &Mnemonic, unsigned Features,
5113 unsigned VariantID);
5115 static bool RequiresVFPRegListValidation(StringRef Inst,
5116 bool &AcceptSinglePrecisionOnly,
5117 bool &AcceptDoublePrecisionOnly) {
5118 if (Inst.size() < 7)
5121 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5122 StringRef AddressingMode = Inst.substr(4, 2);
5123 if (AddressingMode == "ia" || AddressingMode == "db" ||
5124 AddressingMode == "ea" || AddressingMode == "fd") {
5125 AcceptSinglePrecisionOnly = Inst[6] == 's';
5126 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5134 /// Parse an arm instruction mnemonic followed by its operands.
5135 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5137 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5138 // FIXME: Can this be done via tablegen in some fashion?
5139 bool RequireVFPRegisterListCheck;
5140 bool AcceptSinglePrecisionOnly;
5141 bool AcceptDoublePrecisionOnly;
5142 RequireVFPRegisterListCheck =
5143 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5144 AcceptDoublePrecisionOnly);
5146 // Apply mnemonic aliases before doing anything else, as the destination
5147 // mnemonic may include suffices and we want to handle them normally.
5148 // The generic tblgen'erated code does this later, at the start of
5149 // MatchInstructionImpl(), but that's too late for aliases that include
5150 // any sort of suffix.
5151 unsigned AvailableFeatures = getAvailableFeatures();
5152 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5153 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5155 // First check for the ARM-specific .req directive.
5156 if (Parser.getTok().is(AsmToken::Identifier) &&
5157 Parser.getTok().getIdentifier() == ".req") {
5158 parseDirectiveReq(Name, NameLoc);
5159 // We always return 'error' for this, as we're done with this
5160 // statement and don't need to match the 'instruction."
5164 // Create the leading tokens for the mnemonic, split by '.' characters.
5165 size_t Start = 0, Next = Name.find('.');
5166 StringRef Mnemonic = Name.slice(Start, Next);
5168 // Split out the predication code and carry setting flag from the mnemonic.
5169 unsigned PredicationCode;
5170 unsigned ProcessorIMod;
5173 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5174 ProcessorIMod, ITMask);
5176 // In Thumb1, only the branch (B) instruction can be predicated.
5177 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5178 Parser.eatToEndOfStatement();
5179 return Error(NameLoc, "conditional execution not supported in Thumb1");
5182 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5184 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5185 // is the mask as it will be for the IT encoding if the conditional
5186 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5187 // where the conditional bit0 is zero, the instruction post-processing
5188 // will adjust the mask accordingly.
5189 if (Mnemonic == "it") {
5190 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5191 if (ITMask.size() > 3) {
5192 Parser.eatToEndOfStatement();
5193 return Error(Loc, "too many conditions on IT instruction");
5196 for (unsigned i = ITMask.size(); i != 0; --i) {
5197 char pos = ITMask[i - 1];
5198 if (pos != 't' && pos != 'e') {
5199 Parser.eatToEndOfStatement();
5200 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5203 if (ITMask[i - 1] == 't')
5206 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5209 // FIXME: This is all a pretty gross hack. We should automatically handle
5210 // optional operands like this via tblgen.
5212 // Next, add the CCOut and ConditionCode operands, if needed.
5214 // For mnemonics which can ever incorporate a carry setting bit or predication
5215 // code, our matching model involves us always generating CCOut and
5216 // ConditionCode operands to match the mnemonic "as written" and then we let
5217 // the matcher deal with finding the right instruction or generating an
5218 // appropriate error.
5219 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5220 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5222 // If we had a carry-set on an instruction that can't do that, issue an
5224 if (!CanAcceptCarrySet && CarrySetting) {
5225 Parser.eatToEndOfStatement();
5226 return Error(NameLoc, "instruction '" + Mnemonic +
5227 "' can not set flags, but 's' suffix specified");
5229 // If we had a predication code on an instruction that can't do that, issue an
5231 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5232 Parser.eatToEndOfStatement();
5233 return Error(NameLoc, "instruction '" + Mnemonic +
5234 "' is not predicable, but condition code specified");
5237 // Add the carry setting operand, if necessary.
5238 if (CanAcceptCarrySet) {
5239 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5240 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5244 // Add the predication code operand, if necessary.
5245 if (CanAcceptPredicationCode) {
5246 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5248 Operands.push_back(ARMOperand::CreateCondCode(
5249 ARMCC::CondCodes(PredicationCode), Loc));
5252 // Add the processor imod operand, if necessary.
5253 if (ProcessorIMod) {
5254 Operands.push_back(ARMOperand::CreateImm(
5255 MCConstantExpr::Create(ProcessorIMod, getContext()),
5259 // Add the remaining tokens in the mnemonic.
5260 while (Next != StringRef::npos) {
5262 Next = Name.find('.', Start + 1);
5263 StringRef ExtraToken = Name.slice(Start, Next);
5265 // Some NEON instructions have an optional datatype suffix that is
5266 // completely ignored. Check for that.
5267 if (isDataTypeToken(ExtraToken) &&
5268 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5271 // For for ARM mode generate an error if the .n qualifier is used.
5272 if (ExtraToken == ".n" && !isThumb()) {
5273 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5274 Parser.eatToEndOfStatement();
5275 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5279 // The .n qualifier is always discarded as that is what the tables
5280 // and matcher expect. In ARM mode the .w qualifier has no effect,
5281 // so discard it to avoid errors that can be caused by the matcher.
5282 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5283 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5284 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5288 // Read the remaining operands.
5289 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5290 // Read the first operand.
5291 if (parseOperand(Operands, Mnemonic)) {
5292 Parser.eatToEndOfStatement();
5296 while (getLexer().is(AsmToken::Comma)) {
5297 Parser.Lex(); // Eat the comma.
5299 // Parse and remember the operand.
5300 if (parseOperand(Operands, Mnemonic)) {
5301 Parser.eatToEndOfStatement();
5307 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5308 SMLoc Loc = getLexer().getLoc();
5309 Parser.eatToEndOfStatement();
5310 return Error(Loc, "unexpected token in argument list");
5313 Parser.Lex(); // Consume the EndOfStatement
5315 if (RequireVFPRegisterListCheck) {
5316 ARMOperand *Op = static_cast<ARMOperand*>(Operands.back());
5317 if (AcceptSinglePrecisionOnly && !Op->isSPRRegList())
5318 return Error(Op->getStartLoc(),
5319 "VFP/Neon single precision register expected");
5320 if (AcceptDoublePrecisionOnly && !Op->isDPRRegList())
5321 return Error(Op->getStartLoc(),
5322 "VFP/Neon double precision register expected");
5325 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5326 // do and don't have a cc_out optional-def operand. With some spot-checks
5327 // of the operand list, we can figure out which variant we're trying to
5328 // parse and adjust accordingly before actually matching. We shouldn't ever
5329 // try to remove a cc_out operand that was explicitly set on the the
5330 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5331 // table driven matcher doesn't fit well with the ARM instruction set.
5332 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
5333 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5334 Operands.erase(Operands.begin() + 1);
5338 // Some instructions have the same mnemonic, but don't always
5339 // have a predicate. Distinguish them here and delete the
5340 // predicate if needed.
5341 if (shouldOmitPredicateOperand(Mnemonic, Operands)) {
5342 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5343 Operands.erase(Operands.begin() + 1);
5347 // ARM mode 'blx' need special handling, as the register operand version
5348 // is predicable, but the label operand version is not. So, we can't rely
5349 // on the Mnemonic based checking to correctly figure out when to put
5350 // a k_CondCode operand in the list. If we're trying to match the label
5351 // version, remove the k_CondCode operand here.
5352 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5353 static_cast<ARMOperand*>(Operands[2])->isImm()) {
5354 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
5355 Operands.erase(Operands.begin() + 1);
5359 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5360 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5361 // a single GPRPair reg operand is used in the .td file to replace the two
5362 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5363 // expressed as a GPRPair, so we have to manually merge them.
5364 // FIXME: We would really like to be able to tablegen'erate this.
5365 if (!isThumb() && Operands.size() > 4 &&
5366 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5367 Mnemonic == "stlexd")) {
5368 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5369 unsigned Idx = isLoad ? 2 : 3;
5370 ARMOperand* Op1 = static_cast<ARMOperand*>(Operands[Idx]);
5371 ARMOperand* Op2 = static_cast<ARMOperand*>(Operands[Idx+1]);
5373 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5374 // Adjust only if Op1 and Op2 are GPRs.
5375 if (Op1->isReg() && Op2->isReg() && MRC.contains(Op1->getReg()) &&
5376 MRC.contains(Op2->getReg())) {
5377 unsigned Reg1 = Op1->getReg();
5378 unsigned Reg2 = Op2->getReg();
5379 unsigned Rt = MRI->getEncodingValue(Reg1);
5380 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5382 // Rt2 must be Rt + 1 and Rt must be even.
5383 if (Rt + 1 != Rt2 || (Rt & 1)) {
5384 Error(Op2->getStartLoc(), isLoad ?
5385 "destination operands must be sequential" :
5386 "source operands must be sequential");
5389 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5390 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5391 Operands.erase(Operands.begin() + Idx, Operands.begin() + Idx + 2);
5392 Operands.insert(Operands.begin() + Idx, ARMOperand::CreateReg(
5393 NewReg, Op1->getStartLoc(), Op2->getEndLoc()));
5399 // GNU Assembler extension (compatibility)
5400 if ((Mnemonic == "ldrd" || Mnemonic == "strd") && !isThumb() &&
5401 Operands.size() == 4) {
5402 ARMOperand *Op = static_cast<ARMOperand *>(Operands[2]);
5403 assert(Op->isReg() && "expected register argument");
5404 assert(MRI->getMatchingSuperReg(Op->getReg(), ARM::gsub_0,
5405 &MRI->getRegClass(ARM::GPRPairRegClassID))
5406 && "expected register pair");
5407 Operands.insert(Operands.begin() + 3,
5408 ARMOperand::CreateReg(Op->getReg() + 1, Op->getStartLoc(),
5412 // FIXME: As said above, this is all a pretty gross hack. This instruction
5413 // does not fit with other "subs" and tblgen.
5414 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5415 // so the Mnemonic is the original name "subs" and delete the predicate
5416 // operand so it will match the table entry.
5417 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5418 static_cast<ARMOperand*>(Operands[3])->isReg() &&
5419 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::PC &&
5420 static_cast<ARMOperand*>(Operands[4])->isReg() &&
5421 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::LR &&
5422 static_cast<ARMOperand*>(Operands[5])->isImm()) {
5423 ARMOperand *Op0 = static_cast<ARMOperand*>(Operands[0]);
5424 Operands.erase(Operands.begin());
5426 Operands.insert(Operands.begin(), ARMOperand::CreateToken(Name, NameLoc));
5428 ARMOperand *Op1 = static_cast<ARMOperand*>(Operands[1]);
5429 Operands.erase(Operands.begin() + 1);
5435 // Validate context-sensitive operand constraints.
5437 // return 'true' if register list contains non-low GPR registers,
5438 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5439 // 'containsReg' to true.
5440 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5441 unsigned HiReg, bool &containsReg) {
5442 containsReg = false;
5443 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5444 unsigned OpReg = Inst.getOperand(i).getReg();
5447 // Anything other than a low register isn't legal here.
5448 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
5454 // Check if the specified regisgter is in the register list of the inst,
5455 // starting at the indicated operand number.
5456 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
5457 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5458 unsigned OpReg = Inst.getOperand(i).getReg();
5465 // Return true if instruction has the interesting property of being
5466 // allowed in IT blocks, but not being predicable.
5467 static bool instIsBreakpoint(const MCInst &Inst) {
5468 return Inst.getOpcode() == ARM::tBKPT ||
5469 Inst.getOpcode() == ARM::BKPT ||
5470 Inst.getOpcode() == ARM::tHLT ||
5471 Inst.getOpcode() == ARM::HLT;
5475 // FIXME: We would really like to be able to tablegen'erate this.
5477 validateInstruction(MCInst &Inst,
5478 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
5479 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
5480 SMLoc Loc = Operands[0]->getStartLoc();
5482 // Check the IT block state first.
5483 // NOTE: BKPT and HLT instructions have the interesting property of being
5484 // allowed in IT blocks, but not being predicable. They just always execute.
5485 if (inITBlock() && !instIsBreakpoint(Inst)) {
5487 if (ITState.FirstCond)
5488 ITState.FirstCond = false;
5490 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
5491 // The instruction must be predicable.
5492 if (!MCID.isPredicable())
5493 return Error(Loc, "instructions in IT block must be predicable");
5494 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
5495 unsigned ITCond = Bit ? ITState.Cond :
5496 ARMCC::getOppositeCondition(ITState.Cond);
5497 if (Cond != ITCond) {
5498 // Find the condition code Operand to get its SMLoc information.
5500 for (unsigned I = 1; I < Operands.size(); ++I)
5501 if (static_cast<ARMOperand*>(Operands[I])->isCondCode())
5502 CondLoc = Operands[I]->getStartLoc();
5503 return Error(CondLoc, "incorrect condition in IT block; got '" +
5504 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
5505 "', but expected '" +
5506 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
5508 // Check for non-'al' condition codes outside of the IT block.
5509 } else if (isThumbTwo() && MCID.isPredicable() &&
5510 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
5511 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
5512 Inst.getOpcode() != ARM::t2Bcc)
5513 return Error(Loc, "predicated instructions must be in IT block");
5515 const unsigned Opcode = Inst.getOpcode();
5519 case ARM::LDRD_POST: {
5520 const unsigned RtReg = Inst.getOperand(0).getReg();
5523 if (RtReg == ARM::LR)
5524 return Error(Operands[3]->getStartLoc(),
5527 const unsigned Rt = MRI->getEncodingValue(RtReg);
5528 // Rt must be even-numbered.
5530 return Error(Operands[3]->getStartLoc(),
5531 "Rt must be even-numbered");
5533 // Rt2 must be Rt + 1.
5534 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5536 return Error(Operands[3]->getStartLoc(),
5537 "destination operands must be sequential");
5539 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
5540 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
5541 // For addressing modes with writeback, the base register needs to be
5542 // different from the destination registers.
5543 if (Rn == Rt || Rn == Rt2)
5544 return Error(Operands[3]->getStartLoc(),
5545 "base register needs to be different from destination "
5552 case ARM::t2LDRD_PRE:
5553 case ARM::t2LDRD_POST: {
5554 // Rt2 must be different from Rt.
5555 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5556 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5558 return Error(Operands[3]->getStartLoc(),
5559 "destination operands can't be identical");
5563 // Rt2 must be Rt + 1.
5564 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5565 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5567 return Error(Operands[3]->getStartLoc(),
5568 "source operands must be sequential");
5572 case ARM::STRD_POST: {
5573 // Rt2 must be Rt + 1.
5574 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5575 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
5577 return Error(Operands[3]->getStartLoc(),
5578 "source operands must be sequential");
5583 // Width must be in range [1, 32-lsb].
5584 unsigned LSB = Inst.getOperand(2).getImm();
5585 unsigned Widthm1 = Inst.getOperand(3).getImm();
5586 if (Widthm1 >= 32 - LSB)
5587 return Error(Operands[5]->getStartLoc(),
5588 "bitfield width must be in range [1,32-lsb]");
5591 // Notionally handles ARM::tLDMIA_UPD too.
5593 // If we're parsing Thumb2, the .w variant is available and handles
5594 // most cases that are normally illegal for a Thumb1 LDM instruction.
5595 // We'll make the transformation in processInstruction() if necessary.
5597 // Thumb LDM instructions are writeback iff the base register is not
5598 // in the register list.
5599 unsigned Rn = Inst.getOperand(0).getReg();
5600 bool HasWritebackToken =
5601 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
5602 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
5603 bool ListContainsBase;
5604 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
5605 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
5606 "registers must be in range r0-r7");
5607 // If we should have writeback, then there should be a '!' token.
5608 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
5609 return Error(Operands[2]->getStartLoc(),
5610 "writeback operator '!' expected");
5611 // If we should not have writeback, there must not be a '!'. This is
5612 // true even for the 32-bit wide encodings.
5613 if (ListContainsBase && HasWritebackToken)
5614 return Error(Operands[3]->getStartLoc(),
5615 "writeback operator '!' not allowed when base register "
5616 "in register list");
5620 case ARM::LDMIA_UPD:
5621 case ARM::LDMDB_UPD:
5622 case ARM::LDMIB_UPD:
5623 case ARM::LDMDA_UPD:
5624 // ARM variants loading and updating the same register are only officially
5625 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
5629 case ARM::t2LDMIA_UPD:
5630 case ARM::t2LDMDB_UPD:
5631 case ARM::t2STMIA_UPD:
5632 case ARM::t2STMDB_UPD: {
5633 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
5634 return Error(Operands.back()->getStartLoc(),
5635 "writeback register not allowed in register list");
5638 case ARM::sysLDMIA_UPD:
5639 case ARM::sysLDMDA_UPD:
5640 case ARM::sysLDMDB_UPD:
5641 case ARM::sysLDMIB_UPD:
5642 if (!listContainsReg(Inst, 3, ARM::PC))
5643 return Error(Operands[4]->getStartLoc(),
5644 "writeback register only allowed on system LDM "
5645 "if PC in register-list");
5647 case ARM::sysSTMIA_UPD:
5648 case ARM::sysSTMDA_UPD:
5649 case ARM::sysSTMDB_UPD:
5650 case ARM::sysSTMIB_UPD:
5651 return Error(Operands[2]->getStartLoc(),
5652 "system STM cannot have writeback register");
5655 // The second source operand must be the same register as the destination
5658 // In this case, we must directly check the parsed operands because the
5659 // cvtThumbMultiply() function is written in such a way that it guarantees
5660 // this first statement is always true for the new Inst. Essentially, the
5661 // destination is unconditionally copied into the second source operand
5662 // without checking to see if it matches what we actually parsed.
5663 if (Operands.size() == 6 &&
5664 (((ARMOperand*)Operands[3])->getReg() !=
5665 ((ARMOperand*)Operands[5])->getReg()) &&
5666 (((ARMOperand*)Operands[3])->getReg() !=
5667 ((ARMOperand*)Operands[4])->getReg())) {
5668 return Error(Operands[3]->getStartLoc(),
5669 "destination register must match source register");
5673 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
5674 // so only issue a diagnostic for thumb1. The instructions will be
5675 // switched to the t2 encodings in processInstruction() if necessary.
5677 bool ListContainsBase;
5678 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
5680 return Error(Operands[2]->getStartLoc(),
5681 "registers must be in range r0-r7 or pc");
5685 bool ListContainsBase;
5686 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
5688 return Error(Operands[2]->getStartLoc(),
5689 "registers must be in range r0-r7 or lr");
5692 case ARM::tSTMIA_UPD: {
5693 bool ListContainsBase, InvalidLowList;
5694 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
5695 0, ListContainsBase);
5696 if (InvalidLowList && !isThumbTwo())
5697 return Error(Operands[4]->getStartLoc(),
5698 "registers must be in range r0-r7");
5700 // This would be converted to a 32-bit stm, but that's not valid if the
5701 // writeback register is in the list.
5702 if (InvalidLowList && ListContainsBase)
5703 return Error(Operands[4]->getStartLoc(),
5704 "writeback operator '!' not allowed when base register "
5705 "in register list");
5708 case ARM::tADDrSP: {
5709 // If the non-SP source operand and the destination operand are not the
5710 // same, we need thumb2 (for the wide encoding), or we have an error.
5711 if (!isThumbTwo() &&
5712 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
5713 return Error(Operands[4]->getStartLoc(),
5714 "source register must be the same as destination");
5718 // Final range checking for Thumb unconditional branch instructions.
5720 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<11, 1>())
5721 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5724 int op = (Operands[2]->isImm()) ? 2 : 3;
5725 if (!(static_cast<ARMOperand*>(Operands[op]))->isSignedOffset<24, 1>())
5726 return Error(Operands[op]->getStartLoc(), "branch target out of range");
5729 // Final range checking for Thumb conditional branch instructions.
5731 if (!(static_cast<ARMOperand*>(Operands[2]))->isSignedOffset<8, 1>())
5732 return Error(Operands[2]->getStartLoc(), "branch target out of range");
5735 int Op = (Operands[2]->isImm()) ? 2 : 3;
5736 if (!(static_cast<ARMOperand*>(Operands[Op]))->isSignedOffset<20, 1>())
5737 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
5745 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
5747 default: llvm_unreachable("unexpected opcode!");
5749 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5750 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5751 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5752 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
5753 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
5754 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
5755 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
5756 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
5757 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
5760 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5761 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5762 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5763 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5764 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5766 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
5767 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
5768 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
5769 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
5770 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
5772 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
5773 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
5774 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
5775 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
5776 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
5779 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5780 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5781 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5782 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
5783 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5784 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
5785 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
5786 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
5787 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
5788 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
5789 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
5790 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
5791 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
5792 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
5793 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
5796 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5797 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5798 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5799 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5800 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5801 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5802 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
5803 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
5804 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
5805 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
5806 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
5807 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
5808 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
5809 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
5810 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
5811 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
5812 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
5813 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
5816 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5817 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5818 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5819 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
5820 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5821 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
5822 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
5823 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
5824 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
5825 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
5826 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
5827 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
5828 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
5829 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
5830 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
5833 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5834 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5835 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5836 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5837 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5838 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5839 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
5840 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
5841 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
5842 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
5843 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
5844 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
5845 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
5846 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
5847 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
5848 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
5849 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
5850 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
5854 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
5856 default: llvm_unreachable("unexpected opcode!");
5858 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5859 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5860 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5861 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
5862 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
5863 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
5864 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
5865 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
5866 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
5869 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5870 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5871 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5872 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
5873 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5874 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
5875 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
5876 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
5877 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
5878 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
5879 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
5880 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
5881 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
5882 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
5883 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
5886 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5887 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5888 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5889 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
5890 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPq16_UPD;
5891 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5892 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
5893 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
5894 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
5895 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
5896 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
5897 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
5898 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
5899 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
5900 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
5901 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
5902 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
5903 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
5906 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5907 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5908 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5909 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
5910 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5911 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
5912 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
5913 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
5914 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
5915 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
5916 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
5917 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
5918 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
5919 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
5920 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
5923 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5924 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5925 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5926 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5927 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5928 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5929 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
5930 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
5931 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
5932 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
5933 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
5934 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
5935 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
5936 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
5937 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
5938 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
5939 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
5940 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
5943 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5944 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5945 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5946 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNq16_UPD;
5947 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5948 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
5949 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
5950 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
5951 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
5952 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
5953 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
5954 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
5955 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
5956 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
5957 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
5960 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5961 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5962 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5963 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
5964 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
5965 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5966 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
5967 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
5968 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
5969 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
5970 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
5971 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
5972 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
5973 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
5974 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
5975 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
5976 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
5977 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
5980 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5981 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5982 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5983 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5984 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5985 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5986 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
5987 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
5988 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
5989 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
5990 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
5991 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
5992 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
5993 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
5994 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
5995 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
5996 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
5997 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6002 processInstruction(MCInst &Inst,
6003 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
6004 switch (Inst.getOpcode()) {
6005 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6006 case ARM::LDRT_POST:
6007 case ARM::LDRBT_POST: {
6008 const unsigned Opcode =
6009 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6010 : ARM::LDRBT_POST_IMM;
6012 TmpInst.setOpcode(Opcode);
6013 TmpInst.addOperand(Inst.getOperand(0));
6014 TmpInst.addOperand(Inst.getOperand(1));
6015 TmpInst.addOperand(Inst.getOperand(1));
6016 TmpInst.addOperand(MCOperand::CreateReg(0));
6017 TmpInst.addOperand(MCOperand::CreateImm(0));
6018 TmpInst.addOperand(Inst.getOperand(2));
6019 TmpInst.addOperand(Inst.getOperand(3));
6023 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6024 case ARM::STRT_POST:
6025 case ARM::STRBT_POST: {
6026 const unsigned Opcode =
6027 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6028 : ARM::STRBT_POST_IMM;
6030 TmpInst.setOpcode(Opcode);
6031 TmpInst.addOperand(Inst.getOperand(1));
6032 TmpInst.addOperand(Inst.getOperand(0));
6033 TmpInst.addOperand(Inst.getOperand(1));
6034 TmpInst.addOperand(MCOperand::CreateReg(0));
6035 TmpInst.addOperand(MCOperand::CreateImm(0));
6036 TmpInst.addOperand(Inst.getOperand(2));
6037 TmpInst.addOperand(Inst.getOperand(3));
6041 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6043 if (Inst.getOperand(1).getReg() != ARM::PC ||
6044 Inst.getOperand(5).getReg() != 0)
6047 TmpInst.setOpcode(ARM::ADR);
6048 TmpInst.addOperand(Inst.getOperand(0));
6049 TmpInst.addOperand(Inst.getOperand(2));
6050 TmpInst.addOperand(Inst.getOperand(3));
6051 TmpInst.addOperand(Inst.getOperand(4));
6055 // Aliases for alternate PC+imm syntax of LDR instructions.
6056 case ARM::t2LDRpcrel:
6057 // Select the narrow version if the immediate will fit.
6058 if (Inst.getOperand(1).getImm() > 0 &&
6059 Inst.getOperand(1).getImm() <= 0xff &&
6060 !(static_cast<ARMOperand*>(Operands[2])->isToken() &&
6061 static_cast<ARMOperand*>(Operands[2])->getToken() == ".w"))
6062 Inst.setOpcode(ARM::tLDRpci);
6064 Inst.setOpcode(ARM::t2LDRpci);
6066 case ARM::t2LDRBpcrel:
6067 Inst.setOpcode(ARM::t2LDRBpci);
6069 case ARM::t2LDRHpcrel:
6070 Inst.setOpcode(ARM::t2LDRHpci);
6072 case ARM::t2LDRSBpcrel:
6073 Inst.setOpcode(ARM::t2LDRSBpci);
6075 case ARM::t2LDRSHpcrel:
6076 Inst.setOpcode(ARM::t2LDRSHpci);
6078 // Handle NEON VST complex aliases.
6079 case ARM::VST1LNdWB_register_Asm_8:
6080 case ARM::VST1LNdWB_register_Asm_16:
6081 case ARM::VST1LNdWB_register_Asm_32: {
6083 // Shuffle the operands around so the lane index operand is in the
6086 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6087 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6088 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6089 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6090 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6091 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6092 TmpInst.addOperand(Inst.getOperand(1)); // lane
6093 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6094 TmpInst.addOperand(Inst.getOperand(6));
6099 case ARM::VST2LNdWB_register_Asm_8:
6100 case ARM::VST2LNdWB_register_Asm_16:
6101 case ARM::VST2LNdWB_register_Asm_32:
6102 case ARM::VST2LNqWB_register_Asm_16:
6103 case ARM::VST2LNqWB_register_Asm_32: {
6105 // Shuffle the operands around so the lane index operand is in the
6108 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6109 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6110 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6111 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6112 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6113 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6114 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6116 TmpInst.addOperand(Inst.getOperand(1)); // lane
6117 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6118 TmpInst.addOperand(Inst.getOperand(6));
6123 case ARM::VST3LNdWB_register_Asm_8:
6124 case ARM::VST3LNdWB_register_Asm_16:
6125 case ARM::VST3LNdWB_register_Asm_32:
6126 case ARM::VST3LNqWB_register_Asm_16:
6127 case ARM::VST3LNqWB_register_Asm_32: {
6129 // Shuffle the operands around so the lane index operand is in the
6132 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6133 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6134 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6135 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6136 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6137 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6138 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6140 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6142 TmpInst.addOperand(Inst.getOperand(1)); // lane
6143 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6144 TmpInst.addOperand(Inst.getOperand(6));
6149 case ARM::VST4LNdWB_register_Asm_8:
6150 case ARM::VST4LNdWB_register_Asm_16:
6151 case ARM::VST4LNdWB_register_Asm_32:
6152 case ARM::VST4LNqWB_register_Asm_16:
6153 case ARM::VST4LNqWB_register_Asm_32: {
6155 // Shuffle the operands around so the lane index operand is in the
6158 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6159 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6160 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6161 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6162 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6163 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6164 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6166 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6168 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6170 TmpInst.addOperand(Inst.getOperand(1)); // lane
6171 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6172 TmpInst.addOperand(Inst.getOperand(6));
6177 case ARM::VST1LNdWB_fixed_Asm_8:
6178 case ARM::VST1LNdWB_fixed_Asm_16:
6179 case ARM::VST1LNdWB_fixed_Asm_32: {
6181 // Shuffle the operands around so the lane index operand is in the
6184 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6185 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6186 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6187 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6188 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6189 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6190 TmpInst.addOperand(Inst.getOperand(1)); // lane
6191 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6192 TmpInst.addOperand(Inst.getOperand(5));
6197 case ARM::VST2LNdWB_fixed_Asm_8:
6198 case ARM::VST2LNdWB_fixed_Asm_16:
6199 case ARM::VST2LNdWB_fixed_Asm_32:
6200 case ARM::VST2LNqWB_fixed_Asm_16:
6201 case ARM::VST2LNqWB_fixed_Asm_32: {
6203 // Shuffle the operands around so the lane index operand is in the
6206 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6207 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6208 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6209 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6210 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6211 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6212 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6214 TmpInst.addOperand(Inst.getOperand(1)); // lane
6215 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6216 TmpInst.addOperand(Inst.getOperand(5));
6221 case ARM::VST3LNdWB_fixed_Asm_8:
6222 case ARM::VST3LNdWB_fixed_Asm_16:
6223 case ARM::VST3LNdWB_fixed_Asm_32:
6224 case ARM::VST3LNqWB_fixed_Asm_16:
6225 case ARM::VST3LNqWB_fixed_Asm_32: {
6227 // Shuffle the operands around so the lane index operand is in the
6230 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6231 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6232 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6233 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6234 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6235 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6236 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6238 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6240 TmpInst.addOperand(Inst.getOperand(1)); // lane
6241 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6242 TmpInst.addOperand(Inst.getOperand(5));
6247 case ARM::VST4LNdWB_fixed_Asm_8:
6248 case ARM::VST4LNdWB_fixed_Asm_16:
6249 case ARM::VST4LNdWB_fixed_Asm_32:
6250 case ARM::VST4LNqWB_fixed_Asm_16:
6251 case ARM::VST4LNqWB_fixed_Asm_32: {
6253 // Shuffle the operands around so the lane index operand is in the
6256 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6257 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6258 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6259 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6260 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6261 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6262 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6264 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6266 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6268 TmpInst.addOperand(Inst.getOperand(1)); // lane
6269 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6270 TmpInst.addOperand(Inst.getOperand(5));
6275 case ARM::VST1LNdAsm_8:
6276 case ARM::VST1LNdAsm_16:
6277 case ARM::VST1LNdAsm_32: {
6279 // Shuffle the operands around so the lane index operand is in the
6282 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6283 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6284 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6285 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6286 TmpInst.addOperand(Inst.getOperand(1)); // lane
6287 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6288 TmpInst.addOperand(Inst.getOperand(5));
6293 case ARM::VST2LNdAsm_8:
6294 case ARM::VST2LNdAsm_16:
6295 case ARM::VST2LNdAsm_32:
6296 case ARM::VST2LNqAsm_16:
6297 case ARM::VST2LNqAsm_32: {
6299 // Shuffle the operands around so the lane index operand is in the
6302 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6303 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6304 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6305 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6306 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6308 TmpInst.addOperand(Inst.getOperand(1)); // lane
6309 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6310 TmpInst.addOperand(Inst.getOperand(5));
6315 case ARM::VST3LNdAsm_8:
6316 case ARM::VST3LNdAsm_16:
6317 case ARM::VST3LNdAsm_32:
6318 case ARM::VST3LNqAsm_16:
6319 case ARM::VST3LNqAsm_32: {
6321 // Shuffle the operands around so the lane index operand is in the
6324 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6325 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6326 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6327 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6328 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6330 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6332 TmpInst.addOperand(Inst.getOperand(1)); // lane
6333 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6334 TmpInst.addOperand(Inst.getOperand(5));
6339 case ARM::VST4LNdAsm_8:
6340 case ARM::VST4LNdAsm_16:
6341 case ARM::VST4LNdAsm_32:
6342 case ARM::VST4LNqAsm_16:
6343 case ARM::VST4LNqAsm_32: {
6345 // Shuffle the operands around so the lane index operand is in the
6348 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6349 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6350 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6351 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6352 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6354 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6356 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6358 TmpInst.addOperand(Inst.getOperand(1)); // lane
6359 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6360 TmpInst.addOperand(Inst.getOperand(5));
6365 // Handle NEON VLD complex aliases.
6366 case ARM::VLD1LNdWB_register_Asm_8:
6367 case ARM::VLD1LNdWB_register_Asm_16:
6368 case ARM::VLD1LNdWB_register_Asm_32: {
6370 // Shuffle the operands around so the lane index operand is in the
6373 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6374 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6375 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6376 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6377 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6378 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6379 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6380 TmpInst.addOperand(Inst.getOperand(1)); // lane
6381 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6382 TmpInst.addOperand(Inst.getOperand(6));
6387 case ARM::VLD2LNdWB_register_Asm_8:
6388 case ARM::VLD2LNdWB_register_Asm_16:
6389 case ARM::VLD2LNdWB_register_Asm_32:
6390 case ARM::VLD2LNqWB_register_Asm_16:
6391 case ARM::VLD2LNqWB_register_Asm_32: {
6393 // Shuffle the operands around so the lane index operand is in the
6396 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6397 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6398 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6400 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6401 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6402 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6403 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6404 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6405 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6407 TmpInst.addOperand(Inst.getOperand(1)); // lane
6408 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6409 TmpInst.addOperand(Inst.getOperand(6));
6414 case ARM::VLD3LNdWB_register_Asm_8:
6415 case ARM::VLD3LNdWB_register_Asm_16:
6416 case ARM::VLD3LNdWB_register_Asm_32:
6417 case ARM::VLD3LNqWB_register_Asm_16:
6418 case ARM::VLD3LNqWB_register_Asm_32: {
6420 // Shuffle the operands around so the lane index operand is in the
6423 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6424 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6425 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6427 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6429 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6430 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6431 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6432 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6433 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6434 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6436 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6438 TmpInst.addOperand(Inst.getOperand(1)); // lane
6439 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6440 TmpInst.addOperand(Inst.getOperand(6));
6445 case ARM::VLD4LNdWB_register_Asm_8:
6446 case ARM::VLD4LNdWB_register_Asm_16:
6447 case ARM::VLD4LNdWB_register_Asm_32:
6448 case ARM::VLD4LNqWB_register_Asm_16:
6449 case ARM::VLD4LNqWB_register_Asm_32: {
6451 // Shuffle the operands around so the lane index operand is in the
6454 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6455 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6456 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6458 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6460 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6462 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6463 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6464 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6465 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6466 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6467 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6469 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6471 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6473 TmpInst.addOperand(Inst.getOperand(1)); // lane
6474 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6475 TmpInst.addOperand(Inst.getOperand(6));
6480 case ARM::VLD1LNdWB_fixed_Asm_8:
6481 case ARM::VLD1LNdWB_fixed_Asm_16:
6482 case ARM::VLD1LNdWB_fixed_Asm_32: {
6484 // Shuffle the operands around so the lane index operand is in the
6487 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6488 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6489 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6490 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6491 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6492 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6493 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6494 TmpInst.addOperand(Inst.getOperand(1)); // lane
6495 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6496 TmpInst.addOperand(Inst.getOperand(5));
6501 case ARM::VLD2LNdWB_fixed_Asm_8:
6502 case ARM::VLD2LNdWB_fixed_Asm_16:
6503 case ARM::VLD2LNdWB_fixed_Asm_32:
6504 case ARM::VLD2LNqWB_fixed_Asm_16:
6505 case ARM::VLD2LNqWB_fixed_Asm_32: {
6507 // Shuffle the operands around so the lane index operand is in the
6510 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6511 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6512 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6514 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6515 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6516 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6517 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6518 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6519 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6521 TmpInst.addOperand(Inst.getOperand(1)); // lane
6522 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6523 TmpInst.addOperand(Inst.getOperand(5));
6528 case ARM::VLD3LNdWB_fixed_Asm_8:
6529 case ARM::VLD3LNdWB_fixed_Asm_16:
6530 case ARM::VLD3LNdWB_fixed_Asm_32:
6531 case ARM::VLD3LNqWB_fixed_Asm_16:
6532 case ARM::VLD3LNqWB_fixed_Asm_32: {
6534 // Shuffle the operands around so the lane index operand is in the
6537 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6538 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6539 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6541 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6543 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6544 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6545 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6546 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6547 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6548 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6550 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6552 TmpInst.addOperand(Inst.getOperand(1)); // lane
6553 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6554 TmpInst.addOperand(Inst.getOperand(5));
6559 case ARM::VLD4LNdWB_fixed_Asm_8:
6560 case ARM::VLD4LNdWB_fixed_Asm_16:
6561 case ARM::VLD4LNdWB_fixed_Asm_32:
6562 case ARM::VLD4LNqWB_fixed_Asm_16:
6563 case ARM::VLD4LNqWB_fixed_Asm_32: {
6565 // Shuffle the operands around so the lane index operand is in the
6568 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6569 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6570 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6572 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6574 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6576 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6577 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6578 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6579 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6580 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6581 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6583 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6585 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6587 TmpInst.addOperand(Inst.getOperand(1)); // lane
6588 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6589 TmpInst.addOperand(Inst.getOperand(5));
6594 case ARM::VLD1LNdAsm_8:
6595 case ARM::VLD1LNdAsm_16:
6596 case ARM::VLD1LNdAsm_32: {
6598 // Shuffle the operands around so the lane index operand is in the
6601 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6602 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6603 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6604 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6605 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6606 TmpInst.addOperand(Inst.getOperand(1)); // lane
6607 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6608 TmpInst.addOperand(Inst.getOperand(5));
6613 case ARM::VLD2LNdAsm_8:
6614 case ARM::VLD2LNdAsm_16:
6615 case ARM::VLD2LNdAsm_32:
6616 case ARM::VLD2LNqAsm_16:
6617 case ARM::VLD2LNqAsm_32: {
6619 // Shuffle the operands around so the lane index operand is in the
6622 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6623 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6624 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6626 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6627 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6628 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6629 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6631 TmpInst.addOperand(Inst.getOperand(1)); // lane
6632 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6633 TmpInst.addOperand(Inst.getOperand(5));
6638 case ARM::VLD3LNdAsm_8:
6639 case ARM::VLD3LNdAsm_16:
6640 case ARM::VLD3LNdAsm_32:
6641 case ARM::VLD3LNqAsm_16:
6642 case ARM::VLD3LNqAsm_32: {
6644 // Shuffle the operands around so the lane index operand is in the
6647 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6648 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6649 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6651 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6653 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6654 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6655 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6656 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6658 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6660 TmpInst.addOperand(Inst.getOperand(1)); // lane
6661 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6662 TmpInst.addOperand(Inst.getOperand(5));
6667 case ARM::VLD4LNdAsm_8:
6668 case ARM::VLD4LNdAsm_16:
6669 case ARM::VLD4LNdAsm_32:
6670 case ARM::VLD4LNqAsm_16:
6671 case ARM::VLD4LNqAsm_32: {
6673 // Shuffle the operands around so the lane index operand is in the
6676 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6677 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6678 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6680 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6682 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6684 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6685 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6686 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
6687 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6689 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6691 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6693 TmpInst.addOperand(Inst.getOperand(1)); // lane
6694 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6695 TmpInst.addOperand(Inst.getOperand(5));
6700 // VLD3DUP single 3-element structure to all lanes instructions.
6701 case ARM::VLD3DUPdAsm_8:
6702 case ARM::VLD3DUPdAsm_16:
6703 case ARM::VLD3DUPdAsm_32:
6704 case ARM::VLD3DUPqAsm_8:
6705 case ARM::VLD3DUPqAsm_16:
6706 case ARM::VLD3DUPqAsm_32: {
6709 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6710 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6711 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6713 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6715 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6716 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6717 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6718 TmpInst.addOperand(Inst.getOperand(4));
6723 case ARM::VLD3DUPdWB_fixed_Asm_8:
6724 case ARM::VLD3DUPdWB_fixed_Asm_16:
6725 case ARM::VLD3DUPdWB_fixed_Asm_32:
6726 case ARM::VLD3DUPqWB_fixed_Asm_8:
6727 case ARM::VLD3DUPqWB_fixed_Asm_16:
6728 case ARM::VLD3DUPqWB_fixed_Asm_32: {
6731 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6732 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6733 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6735 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6737 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6738 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6739 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6740 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6741 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6742 TmpInst.addOperand(Inst.getOperand(4));
6747 case ARM::VLD3DUPdWB_register_Asm_8:
6748 case ARM::VLD3DUPdWB_register_Asm_16:
6749 case ARM::VLD3DUPdWB_register_Asm_32:
6750 case ARM::VLD3DUPqWB_register_Asm_8:
6751 case ARM::VLD3DUPqWB_register_Asm_16:
6752 case ARM::VLD3DUPqWB_register_Asm_32: {
6755 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6756 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6757 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6759 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6761 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6762 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6763 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6764 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6765 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6766 TmpInst.addOperand(Inst.getOperand(5));
6771 // VLD3 multiple 3-element structure instructions.
6772 case ARM::VLD3dAsm_8:
6773 case ARM::VLD3dAsm_16:
6774 case ARM::VLD3dAsm_32:
6775 case ARM::VLD3qAsm_8:
6776 case ARM::VLD3qAsm_16:
6777 case ARM::VLD3qAsm_32: {
6780 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6781 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6782 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6784 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6786 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6787 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6788 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6789 TmpInst.addOperand(Inst.getOperand(4));
6794 case ARM::VLD3dWB_fixed_Asm_8:
6795 case ARM::VLD3dWB_fixed_Asm_16:
6796 case ARM::VLD3dWB_fixed_Asm_32:
6797 case ARM::VLD3qWB_fixed_Asm_8:
6798 case ARM::VLD3qWB_fixed_Asm_16:
6799 case ARM::VLD3qWB_fixed_Asm_32: {
6802 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6803 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6804 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6806 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6808 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6809 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6810 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6811 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6812 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6813 TmpInst.addOperand(Inst.getOperand(4));
6818 case ARM::VLD3dWB_register_Asm_8:
6819 case ARM::VLD3dWB_register_Asm_16:
6820 case ARM::VLD3dWB_register_Asm_32:
6821 case ARM::VLD3qWB_register_Asm_8:
6822 case ARM::VLD3qWB_register_Asm_16:
6823 case ARM::VLD3qWB_register_Asm_32: {
6826 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6827 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6828 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6830 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6832 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6833 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6834 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6835 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6836 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6837 TmpInst.addOperand(Inst.getOperand(5));
6842 // VLD4DUP single 3-element structure to all lanes instructions.
6843 case ARM::VLD4DUPdAsm_8:
6844 case ARM::VLD4DUPdAsm_16:
6845 case ARM::VLD4DUPdAsm_32:
6846 case ARM::VLD4DUPqAsm_8:
6847 case ARM::VLD4DUPqAsm_16:
6848 case ARM::VLD4DUPqAsm_32: {
6851 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6852 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6853 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6855 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6857 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6859 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6860 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6861 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6862 TmpInst.addOperand(Inst.getOperand(4));
6867 case ARM::VLD4DUPdWB_fixed_Asm_8:
6868 case ARM::VLD4DUPdWB_fixed_Asm_16:
6869 case ARM::VLD4DUPdWB_fixed_Asm_32:
6870 case ARM::VLD4DUPqWB_fixed_Asm_8:
6871 case ARM::VLD4DUPqWB_fixed_Asm_16:
6872 case ARM::VLD4DUPqWB_fixed_Asm_32: {
6875 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6876 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6877 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6879 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6881 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6883 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6884 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6885 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6886 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6887 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6888 TmpInst.addOperand(Inst.getOperand(4));
6893 case ARM::VLD4DUPdWB_register_Asm_8:
6894 case ARM::VLD4DUPdWB_register_Asm_16:
6895 case ARM::VLD4DUPdWB_register_Asm_32:
6896 case ARM::VLD4DUPqWB_register_Asm_8:
6897 case ARM::VLD4DUPqWB_register_Asm_16:
6898 case ARM::VLD4DUPqWB_register_Asm_32: {
6901 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6902 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6903 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6905 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6907 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6909 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6910 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6911 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6912 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6913 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6914 TmpInst.addOperand(Inst.getOperand(5));
6919 // VLD4 multiple 4-element structure instructions.
6920 case ARM::VLD4dAsm_8:
6921 case ARM::VLD4dAsm_16:
6922 case ARM::VLD4dAsm_32:
6923 case ARM::VLD4qAsm_8:
6924 case ARM::VLD4qAsm_16:
6925 case ARM::VLD4qAsm_32: {
6928 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6929 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6930 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6932 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6934 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6936 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6937 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6938 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6939 TmpInst.addOperand(Inst.getOperand(4));
6944 case ARM::VLD4dWB_fixed_Asm_8:
6945 case ARM::VLD4dWB_fixed_Asm_16:
6946 case ARM::VLD4dWB_fixed_Asm_32:
6947 case ARM::VLD4qWB_fixed_Asm_8:
6948 case ARM::VLD4qWB_fixed_Asm_16:
6949 case ARM::VLD4qWB_fixed_Asm_32: {
6952 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6953 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6954 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6956 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6958 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6960 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6961 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6962 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6963 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6964 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
6965 TmpInst.addOperand(Inst.getOperand(4));
6970 case ARM::VLD4dWB_register_Asm_8:
6971 case ARM::VLD4dWB_register_Asm_16:
6972 case ARM::VLD4dWB_register_Asm_32:
6973 case ARM::VLD4qWB_register_Asm_8:
6974 case ARM::VLD4qWB_register_Asm_16:
6975 case ARM::VLD4qWB_register_Asm_32: {
6978 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
6979 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6980 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6982 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6984 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6986 TmpInst.addOperand(Inst.getOperand(1)); // Rn
6987 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
6988 TmpInst.addOperand(Inst.getOperand(2)); // alignment
6989 TmpInst.addOperand(Inst.getOperand(3)); // Rm
6990 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6991 TmpInst.addOperand(Inst.getOperand(5));
6996 // VST3 multiple 3-element structure instructions.
6997 case ARM::VST3dAsm_8:
6998 case ARM::VST3dAsm_16:
6999 case ARM::VST3dAsm_32:
7000 case ARM::VST3qAsm_8:
7001 case ARM::VST3qAsm_16:
7002 case ARM::VST3qAsm_32: {
7005 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7006 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7007 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7008 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7009 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7011 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7013 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7014 TmpInst.addOperand(Inst.getOperand(4));
7019 case ARM::VST3dWB_fixed_Asm_8:
7020 case ARM::VST3dWB_fixed_Asm_16:
7021 case ARM::VST3dWB_fixed_Asm_32:
7022 case ARM::VST3qWB_fixed_Asm_8:
7023 case ARM::VST3qWB_fixed_Asm_16:
7024 case ARM::VST3qWB_fixed_Asm_32: {
7027 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7028 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7029 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7030 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7031 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7032 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7033 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7035 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7037 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7038 TmpInst.addOperand(Inst.getOperand(4));
7043 case ARM::VST3dWB_register_Asm_8:
7044 case ARM::VST3dWB_register_Asm_16:
7045 case ARM::VST3dWB_register_Asm_32:
7046 case ARM::VST3qWB_register_Asm_8:
7047 case ARM::VST3qWB_register_Asm_16:
7048 case ARM::VST3qWB_register_Asm_32: {
7051 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7052 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7053 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7054 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7055 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7056 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7057 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7059 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7061 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7062 TmpInst.addOperand(Inst.getOperand(5));
7067 // VST4 multiple 3-element structure instructions.
7068 case ARM::VST4dAsm_8:
7069 case ARM::VST4dAsm_16:
7070 case ARM::VST4dAsm_32:
7071 case ARM::VST4qAsm_8:
7072 case ARM::VST4qAsm_16:
7073 case ARM::VST4qAsm_32: {
7076 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7077 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7078 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7079 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7080 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7082 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7084 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7086 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7087 TmpInst.addOperand(Inst.getOperand(4));
7092 case ARM::VST4dWB_fixed_Asm_8:
7093 case ARM::VST4dWB_fixed_Asm_16:
7094 case ARM::VST4dWB_fixed_Asm_32:
7095 case ARM::VST4qWB_fixed_Asm_8:
7096 case ARM::VST4qWB_fixed_Asm_16:
7097 case ARM::VST4qWB_fixed_Asm_32: {
7100 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7101 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7102 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7103 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7104 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7105 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7106 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7108 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7110 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7112 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7113 TmpInst.addOperand(Inst.getOperand(4));
7118 case ARM::VST4dWB_register_Asm_8:
7119 case ARM::VST4dWB_register_Asm_16:
7120 case ARM::VST4dWB_register_Asm_32:
7121 case ARM::VST4qWB_register_Asm_8:
7122 case ARM::VST4qWB_register_Asm_16:
7123 case ARM::VST4qWB_register_Asm_32: {
7126 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7127 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7128 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7129 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7130 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7131 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7132 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7134 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7136 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7138 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7139 TmpInst.addOperand(Inst.getOperand(5));
7144 // Handle encoding choice for the shift-immediate instructions.
7147 case ARM::t2ASRri: {
7148 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7149 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7150 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7151 !(static_cast<ARMOperand*>(Operands[3])->isToken() &&
7152 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w")) {
7154 switch (Inst.getOpcode()) {
7155 default: llvm_unreachable("unexpected opcode");
7156 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7157 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7158 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7160 // The Thumb1 operands aren't in the same order. Awesome, eh?
7162 TmpInst.setOpcode(NewOpc);
7163 TmpInst.addOperand(Inst.getOperand(0));
7164 TmpInst.addOperand(Inst.getOperand(5));
7165 TmpInst.addOperand(Inst.getOperand(1));
7166 TmpInst.addOperand(Inst.getOperand(2));
7167 TmpInst.addOperand(Inst.getOperand(3));
7168 TmpInst.addOperand(Inst.getOperand(4));
7175 // Handle the Thumb2 mode MOV complex aliases.
7177 case ARM::t2MOVSsr: {
7178 // Which instruction to expand to depends on the CCOut operand and
7179 // whether we're in an IT block if the register operands are low
7181 bool isNarrow = false;
7182 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7183 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7184 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7185 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7186 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7190 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7191 default: llvm_unreachable("unexpected opcode!");
7192 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7193 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7194 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7195 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7197 TmpInst.setOpcode(newOpc);
7198 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7200 TmpInst.addOperand(MCOperand::CreateReg(
7201 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7202 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7203 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7204 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7205 TmpInst.addOperand(Inst.getOperand(5));
7207 TmpInst.addOperand(MCOperand::CreateReg(
7208 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7213 case ARM::t2MOVSsi: {
7214 // Which instruction to expand to depends on the CCOut operand and
7215 // whether we're in an IT block if the register operands are low
7217 bool isNarrow = false;
7218 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7219 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7220 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7224 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7225 default: llvm_unreachable("unexpected opcode!");
7226 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7227 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7228 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7229 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7230 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7232 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7233 if (Amount == 32) Amount = 0;
7234 TmpInst.setOpcode(newOpc);
7235 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7237 TmpInst.addOperand(MCOperand::CreateReg(
7238 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7239 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7240 if (newOpc != ARM::t2RRX)
7241 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7242 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7243 TmpInst.addOperand(Inst.getOperand(4));
7245 TmpInst.addOperand(MCOperand::CreateReg(
7246 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7250 // Handle the ARM mode MOV complex aliases.
7255 ARM_AM::ShiftOpc ShiftTy;
7256 switch(Inst.getOpcode()) {
7257 default: llvm_unreachable("unexpected opcode!");
7258 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7259 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7260 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7261 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7263 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7265 TmpInst.setOpcode(ARM::MOVsr);
7266 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7267 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7268 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7269 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7270 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7271 TmpInst.addOperand(Inst.getOperand(4));
7272 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7280 ARM_AM::ShiftOpc ShiftTy;
7281 switch(Inst.getOpcode()) {
7282 default: llvm_unreachable("unexpected opcode!");
7283 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7284 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
7285 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
7286 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
7288 // A shift by zero is a plain MOVr, not a MOVsi.
7289 unsigned Amt = Inst.getOperand(2).getImm();
7290 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
7291 // A shift by 32 should be encoded as 0 when permitted
7292 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
7294 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
7296 TmpInst.setOpcode(Opc);
7297 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7298 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7299 if (Opc == ARM::MOVsi)
7300 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7301 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7302 TmpInst.addOperand(Inst.getOperand(4));
7303 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7308 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
7310 TmpInst.setOpcode(ARM::MOVsi);
7311 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7312 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7313 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7314 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7315 TmpInst.addOperand(Inst.getOperand(3));
7316 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
7320 case ARM::t2LDMIA_UPD: {
7321 // If this is a load of a single register, then we should use
7322 // a post-indexed LDR instruction instead, per the ARM ARM.
7323 if (Inst.getNumOperands() != 5)
7326 TmpInst.setOpcode(ARM::t2LDR_POST);
7327 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7328 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7329 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7330 TmpInst.addOperand(MCOperand::CreateImm(4));
7331 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7332 TmpInst.addOperand(Inst.getOperand(3));
7336 case ARM::t2STMDB_UPD: {
7337 // If this is a store of a single register, then we should use
7338 // a pre-indexed STR instruction instead, per the ARM ARM.
7339 if (Inst.getNumOperands() != 5)
7342 TmpInst.setOpcode(ARM::t2STR_PRE);
7343 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7344 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7345 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7346 TmpInst.addOperand(MCOperand::CreateImm(-4));
7347 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7348 TmpInst.addOperand(Inst.getOperand(3));
7352 case ARM::LDMIA_UPD:
7353 // If this is a load of a single register via a 'pop', then we should use
7354 // a post-indexed LDR instruction instead, per the ARM ARM.
7355 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
7356 Inst.getNumOperands() == 5) {
7358 TmpInst.setOpcode(ARM::LDR_POST_IMM);
7359 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7360 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7361 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7362 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
7363 TmpInst.addOperand(MCOperand::CreateImm(4));
7364 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7365 TmpInst.addOperand(Inst.getOperand(3));
7370 case ARM::STMDB_UPD:
7371 // If this is a store of a single register via a 'push', then we should use
7372 // a pre-indexed STR instruction instead, per the ARM ARM.
7373 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
7374 Inst.getNumOperands() == 5) {
7376 TmpInst.setOpcode(ARM::STR_PRE_IMM);
7377 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
7378 TmpInst.addOperand(Inst.getOperand(4)); // Rt
7379 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
7380 TmpInst.addOperand(MCOperand::CreateImm(-4));
7381 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
7382 TmpInst.addOperand(Inst.getOperand(3));
7386 case ARM::t2ADDri12:
7387 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
7388 // mnemonic was used (not "addw"), encoding T3 is preferred.
7389 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "add" ||
7390 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7392 Inst.setOpcode(ARM::t2ADDri);
7393 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7395 case ARM::t2SUBri12:
7396 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
7397 // mnemonic was used (not "subw"), encoding T3 is preferred.
7398 if (static_cast<ARMOperand*>(Operands[0])->getToken() != "sub" ||
7399 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
7401 Inst.setOpcode(ARM::t2SUBri);
7402 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7405 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7406 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7407 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7408 // to encoding T1 if <Rd> is omitted."
7409 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7410 Inst.setOpcode(ARM::tADDi3);
7415 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
7416 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
7417 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
7418 // to encoding T1 if <Rd> is omitted."
7419 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
7420 Inst.setOpcode(ARM::tSUBi3);
7425 case ARM::t2SUBri: {
7426 // If the destination and first source operand are the same, and
7427 // the flags are compatible with the current IT status, use encoding T2
7428 // instead of T3. For compatibility with the system 'as'. Make sure the
7429 // wide encoding wasn't explicit.
7430 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7431 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
7432 (unsigned)Inst.getOperand(2).getImm() > 255 ||
7433 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
7434 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
7435 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7436 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7439 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
7440 ARM::tADDi8 : ARM::tSUBi8);
7441 TmpInst.addOperand(Inst.getOperand(0));
7442 TmpInst.addOperand(Inst.getOperand(5));
7443 TmpInst.addOperand(Inst.getOperand(0));
7444 TmpInst.addOperand(Inst.getOperand(2));
7445 TmpInst.addOperand(Inst.getOperand(3));
7446 TmpInst.addOperand(Inst.getOperand(4));
7450 case ARM::t2ADDrr: {
7451 // If the destination and first source operand are the same, and
7452 // there's no setting of the flags, use encoding T2 instead of T3.
7453 // Note that this is only for ADD, not SUB. This mirrors the system
7454 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
7455 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
7456 Inst.getOperand(5).getReg() != 0 ||
7457 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7458 static_cast<ARMOperand*>(Operands[3])->getToken() == ".w"))
7461 TmpInst.setOpcode(ARM::tADDhirr);
7462 TmpInst.addOperand(Inst.getOperand(0));
7463 TmpInst.addOperand(Inst.getOperand(0));
7464 TmpInst.addOperand(Inst.getOperand(2));
7465 TmpInst.addOperand(Inst.getOperand(3));
7466 TmpInst.addOperand(Inst.getOperand(4));
7470 case ARM::tADDrSP: {
7471 // If the non-SP source operand and the destination operand are not the
7472 // same, we need to use the 32-bit encoding if it's available.
7473 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
7474 Inst.setOpcode(ARM::t2ADDrr);
7475 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
7481 // A Thumb conditional branch outside of an IT block is a tBcc.
7482 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
7483 Inst.setOpcode(ARM::tBcc);
7488 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
7489 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
7490 Inst.setOpcode(ARM::t2Bcc);
7495 // If the conditional is AL or we're in an IT block, we really want t2B.
7496 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
7497 Inst.setOpcode(ARM::t2B);
7502 // If the conditional is AL, we really want tB.
7503 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
7504 Inst.setOpcode(ARM::tB);
7509 // If the register list contains any high registers, or if the writeback
7510 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
7511 // instead if we're in Thumb2. Otherwise, this should have generated
7512 // an error in validateInstruction().
7513 unsigned Rn = Inst.getOperand(0).getReg();
7514 bool hasWritebackToken =
7515 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
7516 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
7517 bool listContainsBase;
7518 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
7519 (!listContainsBase && !hasWritebackToken) ||
7520 (listContainsBase && hasWritebackToken)) {
7521 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7522 assert (isThumbTwo());
7523 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
7524 // If we're switching to the updating version, we need to insert
7525 // the writeback tied operand.
7526 if (hasWritebackToken)
7527 Inst.insert(Inst.begin(),
7528 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
7533 case ARM::tSTMIA_UPD: {
7534 // If the register list contains any high registers, we need to use
7535 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7536 // should have generated an error in validateInstruction().
7537 unsigned Rn = Inst.getOperand(0).getReg();
7538 bool listContainsBase;
7539 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
7540 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
7541 assert (isThumbTwo());
7542 Inst.setOpcode(ARM::t2STMIA_UPD);
7548 bool listContainsBase;
7549 // If the register list contains any high registers, we need to use
7550 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
7551 // should have generated an error in validateInstruction().
7552 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
7554 assert (isThumbTwo());
7555 Inst.setOpcode(ARM::t2LDMIA_UPD);
7556 // Add the base register and writeback operands.
7557 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7558 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7562 bool listContainsBase;
7563 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
7565 assert (isThumbTwo());
7566 Inst.setOpcode(ARM::t2STMDB_UPD);
7567 // Add the base register and writeback operands.
7568 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7569 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
7573 // If we can use the 16-bit encoding and the user didn't explicitly
7574 // request the 32-bit variant, transform it here.
7575 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7576 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
7577 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
7578 Inst.getOperand(4).getReg() == ARM::CPSR) ||
7579 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
7580 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7581 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7582 // The operands aren't in the same order for tMOVi8...
7584 TmpInst.setOpcode(ARM::tMOVi8);
7585 TmpInst.addOperand(Inst.getOperand(0));
7586 TmpInst.addOperand(Inst.getOperand(4));
7587 TmpInst.addOperand(Inst.getOperand(1));
7588 TmpInst.addOperand(Inst.getOperand(2));
7589 TmpInst.addOperand(Inst.getOperand(3));
7596 // If we can use the 16-bit encoding and the user didn't explicitly
7597 // request the 32-bit variant, transform it here.
7598 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7599 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7600 Inst.getOperand(2).getImm() == ARMCC::AL &&
7601 Inst.getOperand(4).getReg() == ARM::CPSR &&
7602 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7603 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7604 // The operands aren't the same for tMOV[S]r... (no cc_out)
7606 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
7607 TmpInst.addOperand(Inst.getOperand(0));
7608 TmpInst.addOperand(Inst.getOperand(1));
7609 TmpInst.addOperand(Inst.getOperand(2));
7610 TmpInst.addOperand(Inst.getOperand(3));
7620 // If we can use the 16-bit encoding and the user didn't explicitly
7621 // request the 32-bit variant, transform it here.
7622 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7623 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7624 Inst.getOperand(2).getImm() == 0 &&
7625 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
7626 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
7628 switch (Inst.getOpcode()) {
7629 default: llvm_unreachable("Illegal opcode!");
7630 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
7631 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
7632 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
7633 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
7635 // The operands aren't the same for thumb1 (no rotate operand).
7637 TmpInst.setOpcode(NewOpc);
7638 TmpInst.addOperand(Inst.getOperand(0));
7639 TmpInst.addOperand(Inst.getOperand(1));
7640 TmpInst.addOperand(Inst.getOperand(3));
7641 TmpInst.addOperand(Inst.getOperand(4));
7648 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
7649 // rrx shifts and asr/lsr of #32 is encoded as 0
7650 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
7652 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
7653 // Shifting by zero is accepted as a vanilla 'MOVr'
7655 TmpInst.setOpcode(ARM::MOVr);
7656 TmpInst.addOperand(Inst.getOperand(0));
7657 TmpInst.addOperand(Inst.getOperand(1));
7658 TmpInst.addOperand(Inst.getOperand(3));
7659 TmpInst.addOperand(Inst.getOperand(4));
7660 TmpInst.addOperand(Inst.getOperand(5));
7673 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
7674 if (SOpc == ARM_AM::rrx) return false;
7675 switch (Inst.getOpcode()) {
7676 default: llvm_unreachable("unexpected opcode!");
7677 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
7678 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
7679 case ARM::EORrsi: newOpc = ARM::EORrr; break;
7680 case ARM::BICrsi: newOpc = ARM::BICrr; break;
7681 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
7682 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
7684 // If the shift is by zero, use the non-shifted instruction definition.
7685 // The exception is for right shifts, where 0 == 32
7686 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
7687 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
7689 TmpInst.setOpcode(newOpc);
7690 TmpInst.addOperand(Inst.getOperand(0));
7691 TmpInst.addOperand(Inst.getOperand(1));
7692 TmpInst.addOperand(Inst.getOperand(2));
7693 TmpInst.addOperand(Inst.getOperand(4));
7694 TmpInst.addOperand(Inst.getOperand(5));
7695 TmpInst.addOperand(Inst.getOperand(6));
7703 // The mask bits for all but the first condition are represented as
7704 // the low bit of the condition code value implies 't'. We currently
7705 // always have 1 implies 't', so XOR toggle the bits if the low bit
7706 // of the condition code is zero.
7707 MCOperand &MO = Inst.getOperand(1);
7708 unsigned Mask = MO.getImm();
7709 unsigned OrigMask = Mask;
7710 unsigned TZ = countTrailingZeros(Mask);
7711 if ((Inst.getOperand(0).getImm() & 1) == 0) {
7712 assert(Mask && TZ <= 3 && "illegal IT mask value!");
7713 Mask ^= (0xE << TZ) & 0xF;
7717 // Set up the IT block state according to the IT instruction we just
7719 assert(!inITBlock() && "nested IT blocks?!");
7720 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
7721 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
7722 ITState.CurPosition = 0;
7723 ITState.FirstCond = true;
7733 // Assemblers should use the narrow encodings of these instructions when permissible.
7734 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7735 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7736 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7737 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7738 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7739 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7740 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7742 switch (Inst.getOpcode()) {
7743 default: llvm_unreachable("unexpected opcode");
7744 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
7745 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
7746 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
7747 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
7748 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
7749 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
7752 TmpInst.setOpcode(NewOpc);
7753 TmpInst.addOperand(Inst.getOperand(0));
7754 TmpInst.addOperand(Inst.getOperand(5));
7755 TmpInst.addOperand(Inst.getOperand(1));
7756 TmpInst.addOperand(Inst.getOperand(2));
7757 TmpInst.addOperand(Inst.getOperand(3));
7758 TmpInst.addOperand(Inst.getOperand(4));
7769 // Assemblers should use the narrow encodings of these instructions when permissible.
7770 // These instructions are special in that they are commutable, so shorter encodings
7771 // are available more often.
7772 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
7773 isARMLowRegister(Inst.getOperand(2).getReg())) &&
7774 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
7775 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
7776 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
7777 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
7778 (!static_cast<ARMOperand*>(Operands[3])->isToken() ||
7779 !static_cast<ARMOperand*>(Operands[3])->getToken().equals_lower(".w"))) {
7781 switch (Inst.getOpcode()) {
7782 default: llvm_unreachable("unexpected opcode");
7783 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
7784 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
7785 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
7786 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
7789 TmpInst.setOpcode(NewOpc);
7790 TmpInst.addOperand(Inst.getOperand(0));
7791 TmpInst.addOperand(Inst.getOperand(5));
7792 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
7793 TmpInst.addOperand(Inst.getOperand(1));
7794 TmpInst.addOperand(Inst.getOperand(2));
7796 TmpInst.addOperand(Inst.getOperand(2));
7797 TmpInst.addOperand(Inst.getOperand(1));
7799 TmpInst.addOperand(Inst.getOperand(3));
7800 TmpInst.addOperand(Inst.getOperand(4));
7810 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
7811 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
7812 // suffix depending on whether they're in an IT block or not.
7813 unsigned Opc = Inst.getOpcode();
7814 const MCInstrDesc &MCID = MII.get(Opc);
7815 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
7816 assert(MCID.hasOptionalDef() &&
7817 "optionally flag setting instruction missing optional def operand");
7818 assert(MCID.NumOperands == Inst.getNumOperands() &&
7819 "operand count mismatch!");
7820 // Find the optional-def operand (cc_out).
7823 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
7826 // If we're parsing Thumb1, reject it completely.
7827 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
7828 return Match_MnemonicFail;
7829 // If we're parsing Thumb2, which form is legal depends on whether we're
7831 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
7833 return Match_RequiresITBlock;
7834 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
7836 return Match_RequiresNotITBlock;
7838 // Some high-register supporting Thumb1 encodings only allow both registers
7839 // to be from r0-r7 when in Thumb2.
7840 else if (Opc == ARM::tADDhirr && isThumbOne() &&
7841 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7842 isARMLowRegister(Inst.getOperand(2).getReg()))
7843 return Match_RequiresThumb2;
7844 // Others only require ARMv6 or later.
7845 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
7846 isARMLowRegister(Inst.getOperand(0).getReg()) &&
7847 isARMLowRegister(Inst.getOperand(1).getReg()))
7848 return Match_RequiresV6;
7849 return Match_Success;
7852 static const char *getSubtargetFeatureName(unsigned Val);
7854 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
7855 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
7856 MCStreamer &Out, unsigned &ErrorInfo,
7857 bool MatchingInlineAsm) {
7859 unsigned MatchResult;
7861 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
7863 switch (MatchResult) {
7866 // Context sensitive operand constraints aren't handled by the matcher,
7867 // so check them here.
7868 if (validateInstruction(Inst, Operands)) {
7869 // Still progress the IT block, otherwise one wrong condition causes
7870 // nasty cascading errors.
7871 forwardITPosition();
7875 { // processInstruction() updates inITBlock state, we need to save it away
7876 bool wasInITBlock = inITBlock();
7878 // Some instructions need post-processing to, for example, tweak which
7879 // encoding is selected. Loop on it while changes happen so the
7880 // individual transformations can chain off each other. E.g.,
7881 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
7882 while (processInstruction(Inst, Operands))
7885 // Only after the instruction is fully processed, we can validate it
7886 if (wasInITBlock && hasV8Ops() && isThumb() &&
7887 !isV8EligibleForIT(&Inst)) {
7888 Warning(IDLoc, "deprecated instruction in IT block");
7892 // Only move forward at the very end so that everything in validate
7893 // and process gets a consistent answer about whether we're in an IT
7895 forwardITPosition();
7897 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
7898 // doesn't actually encode.
7899 if (Inst.getOpcode() == ARM::ITasm)
7903 Out.EmitInstruction(Inst, STI);
7905 case Match_MissingFeature: {
7906 assert(ErrorInfo && "Unknown missing feature!");
7907 // Special case the error message for the very common case where only
7908 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
7909 std::string Msg = "instruction requires:";
7911 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
7912 if (ErrorInfo & Mask) {
7914 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
7918 return Error(IDLoc, Msg);
7920 case Match_InvalidOperand: {
7921 SMLoc ErrorLoc = IDLoc;
7922 if (ErrorInfo != ~0U) {
7923 if (ErrorInfo >= Operands.size())
7924 return Error(IDLoc, "too few operands for instruction");
7926 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7927 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7930 return Error(ErrorLoc, "invalid operand for instruction");
7932 case Match_MnemonicFail:
7933 return Error(IDLoc, "invalid instruction",
7934 ((ARMOperand*)Operands[0])->getLocRange());
7935 case Match_RequiresNotITBlock:
7936 return Error(IDLoc, "flag setting instruction only valid outside IT block");
7937 case Match_RequiresITBlock:
7938 return Error(IDLoc, "instruction only valid inside IT block");
7939 case Match_RequiresV6:
7940 return Error(IDLoc, "instruction variant requires ARMv6 or later");
7941 case Match_RequiresThumb2:
7942 return Error(IDLoc, "instruction variant requires Thumb2");
7943 case Match_ImmRange0_15: {
7944 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7945 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7946 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
7948 case Match_ImmRange0_239: {
7949 SMLoc ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
7950 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
7951 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
7955 llvm_unreachable("Implement any new match types added!");
7958 /// parseDirective parses the arm specific directives
7959 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
7960 StringRef IDVal = DirectiveID.getIdentifier();
7961 if (IDVal == ".word")
7962 return parseLiteralValues(4, DirectiveID.getLoc());
7963 else if (IDVal == ".short" || IDVal == ".hword")
7964 return parseLiteralValues(2, DirectiveID.getLoc());
7965 else if (IDVal == ".thumb")
7966 return parseDirectiveThumb(DirectiveID.getLoc());
7967 else if (IDVal == ".arm")
7968 return parseDirectiveARM(DirectiveID.getLoc());
7969 else if (IDVal == ".thumb_func")
7970 return parseDirectiveThumbFunc(DirectiveID.getLoc());
7971 else if (IDVal == ".code")
7972 return parseDirectiveCode(DirectiveID.getLoc());
7973 else if (IDVal == ".syntax")
7974 return parseDirectiveSyntax(DirectiveID.getLoc());
7975 else if (IDVal == ".unreq")
7976 return parseDirectiveUnreq(DirectiveID.getLoc());
7977 else if (IDVal == ".arch")
7978 return parseDirectiveArch(DirectiveID.getLoc());
7979 else if (IDVal == ".eabi_attribute")
7980 return parseDirectiveEabiAttr(DirectiveID.getLoc());
7981 else if (IDVal == ".cpu")
7982 return parseDirectiveCPU(DirectiveID.getLoc());
7983 else if (IDVal == ".fpu")
7984 return parseDirectiveFPU(DirectiveID.getLoc());
7985 else if (IDVal == ".fnstart")
7986 return parseDirectiveFnStart(DirectiveID.getLoc());
7987 else if (IDVal == ".fnend")
7988 return parseDirectiveFnEnd(DirectiveID.getLoc());
7989 else if (IDVal == ".cantunwind")
7990 return parseDirectiveCantUnwind(DirectiveID.getLoc());
7991 else if (IDVal == ".personality")
7992 return parseDirectivePersonality(DirectiveID.getLoc());
7993 else if (IDVal == ".handlerdata")
7994 return parseDirectiveHandlerData(DirectiveID.getLoc());
7995 else if (IDVal == ".setfp")
7996 return parseDirectiveSetFP(DirectiveID.getLoc());
7997 else if (IDVal == ".pad")
7998 return parseDirectivePad(DirectiveID.getLoc());
7999 else if (IDVal == ".save")
8000 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8001 else if (IDVal == ".vsave")
8002 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8003 else if (IDVal == ".inst")
8004 return parseDirectiveInst(DirectiveID.getLoc());
8005 else if (IDVal == ".inst.n")
8006 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8007 else if (IDVal == ".inst.w")
8008 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8009 else if (IDVal == ".ltorg" || IDVal == ".pool")
8010 return parseDirectiveLtorg(DirectiveID.getLoc());
8011 else if (IDVal == ".even")
8012 return parseDirectiveEven(DirectiveID.getLoc());
8013 else if (IDVal == ".personalityindex")
8014 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8015 else if (IDVal == ".unwind_raw")
8016 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8017 else if (IDVal == ".tlsdescseq")
8018 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8019 else if (IDVal == ".movsp")
8020 return parseDirectiveMovSP(DirectiveID.getLoc());
8021 else if (IDVal == ".object_arch")
8022 return parseDirectiveObjectArch(DirectiveID.getLoc());
8023 else if (IDVal == ".arch_extension")
8024 return parseDirectiveArchExtension(DirectiveID.getLoc());
8028 /// parseLiteralValues
8029 /// ::= .hword expression [, expression]*
8030 /// ::= .short expression [, expression]*
8031 /// ::= .word expression [, expression]*
8032 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8033 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8035 const MCExpr *Value;
8036 if (getParser().parseExpression(Value)) {
8037 Parser.eatToEndOfStatement();
8041 getParser().getStreamer().EmitValue(Value, Size);
8043 if (getLexer().is(AsmToken::EndOfStatement))
8046 // FIXME: Improve diagnostic.
8047 if (getLexer().isNot(AsmToken::Comma)) {
8048 Error(L, "unexpected token in directive");
8059 /// parseDirectiveThumb
8061 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8062 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8063 Error(L, "unexpected token in directive");
8069 Error(L, "target does not support Thumb mode");
8075 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8079 /// parseDirectiveARM
8081 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8082 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8083 Error(L, "unexpected token in directive");
8089 Error(L, "target does not support ARM mode");
8095 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8099 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8100 if (NextSymbolIsThumb) {
8101 getParser().getStreamer().EmitThumbFunc(Symbol);
8102 NextSymbolIsThumb = false;
8106 /// parseDirectiveThumbFunc
8107 /// ::= .thumbfunc symbol_name
8108 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8109 const MCAsmInfo *MAI = getParser().getStreamer().getContext().getAsmInfo();
8110 bool isMachO = MAI->hasSubsectionsViaSymbols();
8112 // Darwin asm has (optionally) function name after .thumb_func direction
8115 const AsmToken &Tok = Parser.getTok();
8116 if (Tok.isNot(AsmToken::EndOfStatement)) {
8117 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8118 Error(L, "unexpected token in .thumb_func directive");
8123 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8124 getParser().getStreamer().EmitThumbFunc(Func);
8125 Parser.Lex(); // Consume the identifier token.
8130 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8131 Error(L, "unexpected token in directive");
8135 NextSymbolIsThumb = true;
8139 /// parseDirectiveSyntax
8140 /// ::= .syntax unified | divided
8141 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8142 const AsmToken &Tok = Parser.getTok();
8143 if (Tok.isNot(AsmToken::Identifier)) {
8144 Error(L, "unexpected token in .syntax directive");
8148 StringRef Mode = Tok.getString();
8149 if (Mode == "unified" || Mode == "UNIFIED") {
8151 } else if (Mode == "divided" || Mode == "DIVIDED") {
8152 Error(L, "'.syntax divided' arm asssembly not supported");
8155 Error(L, "unrecognized syntax mode in .syntax directive");
8159 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8160 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8165 // TODO tell the MC streamer the mode
8166 // getParser().getStreamer().Emit???();
8170 /// parseDirectiveCode
8171 /// ::= .code 16 | 32
8172 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8173 const AsmToken &Tok = Parser.getTok();
8174 if (Tok.isNot(AsmToken::Integer)) {
8175 Error(L, "unexpected token in .code directive");
8178 int64_t Val = Parser.getTok().getIntVal();
8179 if (Val != 16 && Val != 32) {
8180 Error(L, "invalid operand to .code directive");
8185 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8186 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8193 Error(L, "target does not support Thumb mode");
8199 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8202 Error(L, "target does not support ARM mode");
8208 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8214 /// parseDirectiveReq
8215 /// ::= name .req registername
8216 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8217 Parser.Lex(); // Eat the '.req' token.
8219 SMLoc SRegLoc, ERegLoc;
8220 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
8221 Parser.eatToEndOfStatement();
8222 Error(SRegLoc, "register name expected");
8226 // Shouldn't be anything else.
8227 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
8228 Parser.eatToEndOfStatement();
8229 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
8233 Parser.Lex(); // Consume the EndOfStatement
8235 if (RegisterReqs.GetOrCreateValue(Name, Reg).getValue() != Reg) {
8236 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
8243 /// parseDirectiveUneq
8244 /// ::= .unreq registername
8245 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
8246 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8247 Parser.eatToEndOfStatement();
8248 Error(L, "unexpected input in .unreq directive.");
8251 RegisterReqs.erase(Parser.getTok().getIdentifier());
8252 Parser.Lex(); // Eat the identifier.
8256 /// parseDirectiveArch
8258 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
8259 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
8261 unsigned ID = StringSwitch<unsigned>(Arch)
8262 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
8263 .Case(NAME, ARM::ID)
8264 #define ARM_ARCH_ALIAS(NAME, ID) \
8265 .Case(NAME, ARM::ID)
8266 #include "MCTargetDesc/ARMArchName.def"
8267 .Default(ARM::INVALID_ARCH);
8269 if (ID == ARM::INVALID_ARCH) {
8270 Error(L, "Unknown arch name");
8274 getTargetStreamer().emitArch(ID);
8278 /// parseDirectiveEabiAttr
8279 /// ::= .eabi_attribute int, int [, "str"]
8280 /// ::= .eabi_attribute Tag_name, int [, "str"]
8281 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
8285 TagLoc = Parser.getTok().getLoc();
8286 if (Parser.getTok().is(AsmToken::Identifier)) {
8287 StringRef Name = Parser.getTok().getIdentifier();
8288 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
8290 Error(TagLoc, "attribute name not recognised: " + Name);
8291 Parser.eatToEndOfStatement();
8296 const MCExpr *AttrExpr;
8298 TagLoc = Parser.getTok().getLoc();
8299 if (Parser.parseExpression(AttrExpr)) {
8300 Parser.eatToEndOfStatement();
8304 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
8306 Error(TagLoc, "expected numeric constant");
8307 Parser.eatToEndOfStatement();
8311 Tag = CE->getValue();
8314 if (Parser.getTok().isNot(AsmToken::Comma)) {
8315 Error(Parser.getTok().getLoc(), "comma expected");
8316 Parser.eatToEndOfStatement();
8319 Parser.Lex(); // skip comma
8321 StringRef StringValue = "";
8322 bool IsStringValue = false;
8324 int64_t IntegerValue = 0;
8325 bool IsIntegerValue = false;
8327 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
8328 IsStringValue = true;
8329 else if (Tag == ARMBuildAttrs::compatibility) {
8330 IsStringValue = true;
8331 IsIntegerValue = true;
8332 } else if (Tag < 32 || Tag % 2 == 0)
8333 IsIntegerValue = true;
8334 else if (Tag % 2 == 1)
8335 IsStringValue = true;
8337 llvm_unreachable("invalid tag type");
8339 if (IsIntegerValue) {
8340 const MCExpr *ValueExpr;
8341 SMLoc ValueExprLoc = Parser.getTok().getLoc();
8342 if (Parser.parseExpression(ValueExpr)) {
8343 Parser.eatToEndOfStatement();
8347 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
8349 Error(ValueExprLoc, "expected numeric constant");
8350 Parser.eatToEndOfStatement();
8354 IntegerValue = CE->getValue();
8357 if (Tag == ARMBuildAttrs::compatibility) {
8358 if (Parser.getTok().isNot(AsmToken::Comma))
8359 IsStringValue = false;
8364 if (IsStringValue) {
8365 if (Parser.getTok().isNot(AsmToken::String)) {
8366 Error(Parser.getTok().getLoc(), "bad string constant");
8367 Parser.eatToEndOfStatement();
8371 StringValue = Parser.getTok().getStringContents();
8375 if (IsIntegerValue && IsStringValue) {
8376 assert(Tag == ARMBuildAttrs::compatibility);
8377 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
8378 } else if (IsIntegerValue)
8379 getTargetStreamer().emitAttribute(Tag, IntegerValue);
8380 else if (IsStringValue)
8381 getTargetStreamer().emitTextAttribute(Tag, StringValue);
8385 /// parseDirectiveCPU
8387 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
8388 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
8389 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
8393 /// parseDirectiveFPU
8395 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
8396 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
8398 unsigned ID = StringSwitch<unsigned>(FPU)
8399 #define ARM_FPU_NAME(NAME, ID) .Case(NAME, ARM::ID)
8400 #include "ARMFPUName.def"
8401 .Default(ARM::INVALID_FPU);
8403 if (ID == ARM::INVALID_FPU) {
8404 Error(L, "Unknown FPU name");
8408 getTargetStreamer().emitFPU(ID);
8412 /// parseDirectiveFnStart
8414 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
8415 if (UC.hasFnStart()) {
8416 Error(L, ".fnstart starts before the end of previous one");
8417 UC.emitFnStartLocNotes();
8421 // Reset the unwind directives parser state
8424 getTargetStreamer().emitFnStart();
8426 UC.recordFnStart(L);
8430 /// parseDirectiveFnEnd
8432 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
8433 // Check the ordering of unwind directives
8434 if (!UC.hasFnStart()) {
8435 Error(L, ".fnstart must precede .fnend directive");
8439 // Reset the unwind directives parser state
8440 getTargetStreamer().emitFnEnd();
8446 /// parseDirectiveCantUnwind
8448 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
8449 UC.recordCantUnwind(L);
8451 // Check the ordering of unwind directives
8452 if (!UC.hasFnStart()) {
8453 Error(L, ".fnstart must precede .cantunwind directive");
8456 if (UC.hasHandlerData()) {
8457 Error(L, ".cantunwind can't be used with .handlerdata directive");
8458 UC.emitHandlerDataLocNotes();
8461 if (UC.hasPersonality()) {
8462 Error(L, ".cantunwind can't be used with .personality directive");
8463 UC.emitPersonalityLocNotes();
8467 getTargetStreamer().emitCantUnwind();
8471 /// parseDirectivePersonality
8472 /// ::= .personality name
8473 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
8474 bool HasExistingPersonality = UC.hasPersonality();
8476 UC.recordPersonality(L);
8478 // Check the ordering of unwind directives
8479 if (!UC.hasFnStart()) {
8480 Error(L, ".fnstart must precede .personality directive");
8483 if (UC.cantUnwind()) {
8484 Error(L, ".personality can't be used with .cantunwind directive");
8485 UC.emitCantUnwindLocNotes();
8488 if (UC.hasHandlerData()) {
8489 Error(L, ".personality must precede .handlerdata directive");
8490 UC.emitHandlerDataLocNotes();
8493 if (HasExistingPersonality) {
8494 Parser.eatToEndOfStatement();
8495 Error(L, "multiple personality directives");
8496 UC.emitPersonalityLocNotes();
8500 // Parse the name of the personality routine
8501 if (Parser.getTok().isNot(AsmToken::Identifier)) {
8502 Parser.eatToEndOfStatement();
8503 Error(L, "unexpected input in .personality directive.");
8506 StringRef Name(Parser.getTok().getIdentifier());
8509 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
8510 getTargetStreamer().emitPersonality(PR);
8514 /// parseDirectiveHandlerData
8515 /// ::= .handlerdata
8516 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
8517 UC.recordHandlerData(L);
8519 // Check the ordering of unwind directives
8520 if (!UC.hasFnStart()) {
8521 Error(L, ".fnstart must precede .personality directive");
8524 if (UC.cantUnwind()) {
8525 Error(L, ".handlerdata can't be used with .cantunwind directive");
8526 UC.emitCantUnwindLocNotes();
8530 getTargetStreamer().emitHandlerData();
8534 /// parseDirectiveSetFP
8535 /// ::= .setfp fpreg, spreg [, offset]
8536 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
8537 // Check the ordering of unwind directives
8538 if (!UC.hasFnStart()) {
8539 Error(L, ".fnstart must precede .setfp directive");
8542 if (UC.hasHandlerData()) {
8543 Error(L, ".setfp must precede .handlerdata directive");
8548 SMLoc FPRegLoc = Parser.getTok().getLoc();
8549 int FPReg = tryParseRegister();
8551 Error(FPRegLoc, "frame pointer register expected");
8556 if (Parser.getTok().isNot(AsmToken::Comma)) {
8557 Error(Parser.getTok().getLoc(), "comma expected");
8560 Parser.Lex(); // skip comma
8563 SMLoc SPRegLoc = Parser.getTok().getLoc();
8564 int SPReg = tryParseRegister();
8566 Error(SPRegLoc, "stack pointer register expected");
8570 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
8571 Error(SPRegLoc, "register should be either $sp or the latest fp register");
8575 // Update the frame pointer register
8576 UC.saveFPReg(FPReg);
8580 if (Parser.getTok().is(AsmToken::Comma)) {
8581 Parser.Lex(); // skip comma
8583 if (Parser.getTok().isNot(AsmToken::Hash) &&
8584 Parser.getTok().isNot(AsmToken::Dollar)) {
8585 Error(Parser.getTok().getLoc(), "'#' expected");
8588 Parser.Lex(); // skip hash token.
8590 const MCExpr *OffsetExpr;
8591 SMLoc ExLoc = Parser.getTok().getLoc();
8593 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8594 Error(ExLoc, "malformed setfp offset");
8597 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8599 Error(ExLoc, "setfp offset must be an immediate");
8603 Offset = CE->getValue();
8606 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
8607 static_cast<unsigned>(SPReg), Offset);
8613 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
8614 // Check the ordering of unwind directives
8615 if (!UC.hasFnStart()) {
8616 Error(L, ".fnstart must precede .pad directive");
8619 if (UC.hasHandlerData()) {
8620 Error(L, ".pad must precede .handlerdata directive");
8625 if (Parser.getTok().isNot(AsmToken::Hash) &&
8626 Parser.getTok().isNot(AsmToken::Dollar)) {
8627 Error(Parser.getTok().getLoc(), "'#' expected");
8630 Parser.Lex(); // skip hash token.
8632 const MCExpr *OffsetExpr;
8633 SMLoc ExLoc = Parser.getTok().getLoc();
8635 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
8636 Error(ExLoc, "malformed pad offset");
8639 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8641 Error(ExLoc, "pad offset must be an immediate");
8645 getTargetStreamer().emitPad(CE->getValue());
8649 /// parseDirectiveRegSave
8650 /// ::= .save { registers }
8651 /// ::= .vsave { registers }
8652 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
8653 // Check the ordering of unwind directives
8654 if (!UC.hasFnStart()) {
8655 Error(L, ".fnstart must precede .save or .vsave directives");
8658 if (UC.hasHandlerData()) {
8659 Error(L, ".save or .vsave must precede .handlerdata directive");
8663 // RAII object to make sure parsed operands are deleted.
8664 struct CleanupObject {
8665 SmallVector<MCParsedAsmOperand *, 1> Operands;
8667 for (unsigned I = 0, E = Operands.size(); I != E; ++I)
8672 // Parse the register list
8673 if (parseRegisterList(CO.Operands))
8675 ARMOperand *Op = (ARMOperand*)CO.Operands[0];
8676 if (!IsVector && !Op->isRegList()) {
8677 Error(L, ".save expects GPR registers");
8680 if (IsVector && !Op->isDPRRegList()) {
8681 Error(L, ".vsave expects DPR registers");
8685 getTargetStreamer().emitRegSave(Op->getRegList(), IsVector);
8689 /// parseDirectiveInst
8690 /// ::= .inst opcode [, ...]
8691 /// ::= .inst.n opcode [, ...]
8692 /// ::= .inst.w opcode [, ...]
8693 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
8705 Parser.eatToEndOfStatement();
8706 Error(Loc, "cannot determine Thumb instruction size, "
8707 "use inst.n/inst.w instead");
8712 Parser.eatToEndOfStatement();
8713 Error(Loc, "width suffixes are invalid in ARM mode");
8719 if (getLexer().is(AsmToken::EndOfStatement)) {
8720 Parser.eatToEndOfStatement();
8721 Error(Loc, "expected expression following directive");
8728 if (getParser().parseExpression(Expr)) {
8729 Error(Loc, "expected expression");
8733 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
8735 Error(Loc, "expected constant expression");
8741 if (Value->getValue() > 0xffff) {
8742 Error(Loc, "inst.n operand is too big, use inst.w instead");
8747 if (Value->getValue() > 0xffffffff) {
8749 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
8754 llvm_unreachable("only supported widths are 2 and 4");
8757 getTargetStreamer().emitInst(Value->getValue(), Suffix);
8759 if (getLexer().is(AsmToken::EndOfStatement))
8762 if (getLexer().isNot(AsmToken::Comma)) {
8763 Error(Loc, "unexpected token in directive");
8774 /// parseDirectiveLtorg
8775 /// ::= .ltorg | .pool
8776 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
8777 getTargetStreamer().emitCurrentConstantPool();
8781 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
8782 const MCSection *Section = getStreamer().getCurrentSection().first;
8784 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8785 TokError("unexpected token in directive");
8790 getStreamer().InitSections();
8791 Section = getStreamer().getCurrentSection().first;
8794 if (Section->UseCodeAlign())
8795 getStreamer().EmitCodeAlignment(2);
8797 getStreamer().EmitValueToAlignment(2);
8802 /// parseDirectivePersonalityIndex
8803 /// ::= .personalityindex index
8804 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
8805 bool HasExistingPersonality = UC.hasPersonality();
8807 UC.recordPersonalityIndex(L);
8809 if (!UC.hasFnStart()) {
8810 Parser.eatToEndOfStatement();
8811 Error(L, ".fnstart must precede .personalityindex directive");
8814 if (UC.cantUnwind()) {
8815 Parser.eatToEndOfStatement();
8816 Error(L, ".personalityindex cannot be used with .cantunwind");
8817 UC.emitCantUnwindLocNotes();
8820 if (UC.hasHandlerData()) {
8821 Parser.eatToEndOfStatement();
8822 Error(L, ".personalityindex must precede .handlerdata directive");
8823 UC.emitHandlerDataLocNotes();
8826 if (HasExistingPersonality) {
8827 Parser.eatToEndOfStatement();
8828 Error(L, "multiple personality directives");
8829 UC.emitPersonalityLocNotes();
8833 const MCExpr *IndexExpression;
8834 SMLoc IndexLoc = Parser.getTok().getLoc();
8835 if (Parser.parseExpression(IndexExpression)) {
8836 Parser.eatToEndOfStatement();
8840 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
8842 Parser.eatToEndOfStatement();
8843 Error(IndexLoc, "index must be a constant number");
8846 if (CE->getValue() < 0 ||
8847 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
8848 Parser.eatToEndOfStatement();
8849 Error(IndexLoc, "personality routine index should be in range [0-3]");
8853 getTargetStreamer().emitPersonalityIndex(CE->getValue());
8857 /// parseDirectiveUnwindRaw
8858 /// ::= .unwind_raw offset, opcode [, opcode...]
8859 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
8860 if (!UC.hasFnStart()) {
8861 Parser.eatToEndOfStatement();
8862 Error(L, ".fnstart must precede .unwind_raw directives");
8866 int64_t StackOffset;
8868 const MCExpr *OffsetExpr;
8869 SMLoc OffsetLoc = getLexer().getLoc();
8870 if (getLexer().is(AsmToken::EndOfStatement) ||
8871 getParser().parseExpression(OffsetExpr)) {
8872 Error(OffsetLoc, "expected expression");
8873 Parser.eatToEndOfStatement();
8877 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
8879 Error(OffsetLoc, "offset must be a constant");
8880 Parser.eatToEndOfStatement();
8884 StackOffset = CE->getValue();
8886 if (getLexer().isNot(AsmToken::Comma)) {
8887 Error(getLexer().getLoc(), "expected comma");
8888 Parser.eatToEndOfStatement();
8893 SmallVector<uint8_t, 16> Opcodes;
8897 SMLoc OpcodeLoc = getLexer().getLoc();
8898 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
8899 Error(OpcodeLoc, "expected opcode expression");
8900 Parser.eatToEndOfStatement();
8904 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
8906 Error(OpcodeLoc, "opcode value must be a constant");
8907 Parser.eatToEndOfStatement();
8911 const int64_t Opcode = OC->getValue();
8912 if (Opcode & ~0xff) {
8913 Error(OpcodeLoc, "invalid opcode");
8914 Parser.eatToEndOfStatement();
8918 Opcodes.push_back(uint8_t(Opcode));
8920 if (getLexer().is(AsmToken::EndOfStatement))
8923 if (getLexer().isNot(AsmToken::Comma)) {
8924 Error(getLexer().getLoc(), "unexpected token in directive");
8925 Parser.eatToEndOfStatement();
8932 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
8938 /// parseDirectiveTLSDescSeq
8939 /// ::= .tlsdescseq tls-variable
8940 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
8941 if (getLexer().isNot(AsmToken::Identifier)) {
8942 TokError("expected variable after '.tlsdescseq' directive");
8943 Parser.eatToEndOfStatement();
8947 const MCSymbolRefExpr *SRE =
8948 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
8949 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
8952 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8953 Error(Parser.getTok().getLoc(), "unexpected token");
8954 Parser.eatToEndOfStatement();
8958 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
8962 /// parseDirectiveMovSP
8963 /// ::= .movsp reg [, #offset]
8964 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
8965 if (!UC.hasFnStart()) {
8966 Parser.eatToEndOfStatement();
8967 Error(L, ".fnstart must precede .movsp directives");
8970 if (UC.getFPReg() != ARM::SP) {
8971 Parser.eatToEndOfStatement();
8972 Error(L, "unexpected .movsp directive");
8976 SMLoc SPRegLoc = Parser.getTok().getLoc();
8977 int SPReg = tryParseRegister();
8979 Parser.eatToEndOfStatement();
8980 Error(SPRegLoc, "register expected");
8984 if (SPReg == ARM::SP || SPReg == ARM::PC) {
8985 Parser.eatToEndOfStatement();
8986 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
8991 if (Parser.getTok().is(AsmToken::Comma)) {
8994 if (Parser.getTok().isNot(AsmToken::Hash)) {
8995 Error(Parser.getTok().getLoc(), "expected #constant");
8996 Parser.eatToEndOfStatement();
9001 const MCExpr *OffsetExpr;
9002 SMLoc OffsetLoc = Parser.getTok().getLoc();
9003 if (Parser.parseExpression(OffsetExpr)) {
9004 Parser.eatToEndOfStatement();
9005 Error(OffsetLoc, "malformed offset expression");
9009 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9011 Parser.eatToEndOfStatement();
9012 Error(OffsetLoc, "offset must be an immediate constant");
9016 Offset = CE->getValue();
9019 getTargetStreamer().emitMovSP(SPReg, Offset);
9020 UC.saveFPReg(SPReg);
9025 /// parseDirectiveObjectArch
9026 /// ::= .object_arch name
9027 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9028 if (getLexer().isNot(AsmToken::Identifier)) {
9029 Error(getLexer().getLoc(), "unexpected token");
9030 Parser.eatToEndOfStatement();
9034 StringRef Arch = Parser.getTok().getString();
9035 SMLoc ArchLoc = Parser.getTok().getLoc();
9038 unsigned ID = StringSwitch<unsigned>(Arch)
9039 #define ARM_ARCH_NAME(NAME, ID, DEFAULT_CPU_NAME, DEFAULT_CPU_ARCH) \
9040 .Case(NAME, ARM::ID)
9041 #define ARM_ARCH_ALIAS(NAME, ID) \
9042 .Case(NAME, ARM::ID)
9043 #include "MCTargetDesc/ARMArchName.def"
9044 #undef ARM_ARCH_NAME
9045 #undef ARM_ARCH_ALIAS
9046 .Default(ARM::INVALID_ARCH);
9048 if (ID == ARM::INVALID_ARCH) {
9049 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9050 Parser.eatToEndOfStatement();
9054 getTargetStreamer().emitObjectArch(ID);
9056 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9057 Error(getLexer().getLoc(), "unexpected token");
9058 Parser.eatToEndOfStatement();
9064 /// Force static initialization.
9065 extern "C" void LLVMInitializeARMAsmParser() {
9066 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
9067 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
9070 #define GET_REGISTER_MATCHER
9071 #define GET_SUBTARGET_FEATURE_NAME
9072 #define GET_MATCHER_IMPLEMENTATION
9073 #include "ARMGenAsmMatcher.inc"
9075 static const struct ExtMapEntry {
9076 const char *Extension;
9077 const unsigned ArchCheck;
9078 const uint64_t Features;
9080 { "crc", Feature_HasV8, ARM::FeatureCRC },
9081 { "crypto", Feature_HasV8,
9082 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9083 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9084 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9085 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9086 // FIXME: iWMMXT not supported
9087 { "iwmmxt", Feature_None, 0 },
9088 // FIXME: iWMMXT2 not supported
9089 { "iwmmxt2", Feature_None, 0 },
9090 // FIXME: Maverick not supported
9091 { "maverick", Feature_None, 0 },
9092 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
9093 // FIXME: ARMv6-m OS Extensions feature not checked
9094 { "os", Feature_None, 0 },
9095 // FIXME: Also available in ARMv6-K
9096 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
9097 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9098 // FIXME: Only available in A-class, isel not predicated
9099 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
9100 // FIXME: xscale not supported
9101 { "xscale", Feature_None, 0 },
9104 /// parseDirectiveArchExtension
9105 /// ::= .arch_extension [no]feature
9106 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9107 if (getLexer().isNot(AsmToken::Identifier)) {
9108 Error(getLexer().getLoc(), "unexpected token");
9109 Parser.eatToEndOfStatement();
9113 StringRef Extension = Parser.getTok().getString();
9114 SMLoc ExtLoc = Parser.getTok().getLoc();
9117 bool EnableFeature = true;
9118 if (Extension.startswith_lower("no")) {
9119 EnableFeature = false;
9120 Extension = Extension.substr(2);
9123 for (unsigned EI = 0, EE = array_lengthof(Extensions); EI != EE; ++EI) {
9124 if (Extensions[EI].Extension != Extension)
9127 unsigned FB = getAvailableFeatures();
9128 if ((FB & Extensions[EI].ArchCheck) != Extensions[EI].ArchCheck) {
9129 Error(ExtLoc, "architectural extension '" + Extension + "' is not "
9130 "allowed for the current base architecture");
9134 if (!Extensions[EI].Features)
9135 report_fatal_error("unsupported architectural extension: " + Extension);
9138 FB |= ComputeAvailableFeatures(Extensions[EI].Features);
9140 FB &= ~ComputeAvailableFeatures(Extensions[EI].Features);
9142 setAvailableFeatures(FB);
9146 Error(ExtLoc, "unknown architectural extension: " + Extension);
9147 Parser.eatToEndOfStatement();
9151 // Define this matcher function after the auto-generated include so we
9152 // have the match class enum definitions.
9153 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
9155 ARMOperand *Op = static_cast<ARMOperand*>(AsmOp);
9156 // If the kind is a token for a literal immediate, check if our asm
9157 // operand matches. This is for InstAliases which have a fixed-value
9158 // immediate in the syntax.
9163 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm()))
9164 if (CE->getValue() == 0)
9165 return Match_Success;
9169 const MCExpr *SOExpr = Op->getImm();
9171 if (!SOExpr->EvaluateAsAbsolute(Value))
9172 return Match_Success;
9173 assert((Value >= INT32_MIN && Value <= INT32_MAX) &&
9174 "expression value must be representiable in 32 bits");
9179 MRI->getRegClass(ARM::GPRRegClassID).contains(Op->getReg()))
9180 return Match_Success;
9183 return Match_InvalidOperand;