1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/ARMBaseInfo.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMMCExpr.h"
13 #include "llvm/MC/MCParser/MCAsmLexer.h"
14 #include "llvm/MC/MCParser/MCAsmParser.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCAsmInfo.h"
17 #include "llvm/MC/MCContext.h"
18 #include "llvm/MC/MCStreamer.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrDesc.h"
22 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
24 #include "llvm/MC/MCTargetAsmParser.h"
25 #include "llvm/Support/MathExtras.h"
26 #include "llvm/Support/SourceMgr.h"
27 #include "llvm/Support/TargetRegistry.h"
28 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/ADT/BitVector.h"
30 #include "llvm/ADT/OwningPtr.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/ADT/StringExtras.h"
34 #include "llvm/ADT/StringSwitch.h"
35 #include "llvm/ADT/Twine.h"
43 class ARMAsmParser : public MCTargetAsmParser {
48 ARMCC::CondCodes Cond; // Condition for IT block.
49 unsigned Mask:4; // Condition mask for instructions.
50 // Starting at first 1 (from lsb).
51 // '1' condition as indicated in IT.
52 // '0' inverse of condition (else).
53 // Count of instructions in IT block is
54 // 4 - trailingzeroes(mask)
56 bool FirstCond; // Explicit flag for when we're parsing the
57 // First instruction in the IT block. It's
58 // implied in the mask, so needs special
61 unsigned CurPosition; // Current position in parsing of IT
62 // block. In range [0,3]. Initialized
63 // according to count of instructions in block.
64 // ~0U if no active IT block.
66 bool inITBlock() { return ITState.CurPosition != ~0U;}
67 void forwardITPosition() {
68 if (!inITBlock()) return;
69 // Move to the next instruction in the IT block, if there is one. If not,
70 // mark the block as done.
71 unsigned TZ = CountTrailingZeros_32(ITState.Mask);
72 if (++ITState.CurPosition == 5 - TZ)
73 ITState.CurPosition = ~0U; // Done with the IT block after this.
77 MCAsmParser &getParser() const { return Parser; }
78 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
80 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
81 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
83 int tryParseRegister();
84 bool tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &);
85 int tryParseShiftRegister(SmallVectorImpl<MCParsedAsmOperand*> &);
86 bool parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &);
87 bool parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &);
88 bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &, StringRef Mnemonic);
89 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
90 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
91 unsigned &ShiftAmount);
92 bool parseDirectiveWord(unsigned Size, SMLoc L);
93 bool parseDirectiveThumb(SMLoc L);
94 bool parseDirectiveThumbFunc(SMLoc L);
95 bool parseDirectiveCode(SMLoc L);
96 bool parseDirectiveSyntax(SMLoc L);
98 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
99 bool &CarrySetting, unsigned &ProcessorIMod,
101 void getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
102 bool &CanAcceptPredicationCode);
104 bool isThumb() const {
105 // FIXME: Can tablegen auto-generate this?
106 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
108 bool isThumbOne() const {
109 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
111 bool isThumbTwo() const {
112 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
114 bool hasV6Ops() const {
115 return STI.getFeatureBits() & ARM::HasV6Ops;
118 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
119 setAvailableFeatures(FB);
122 /// @name Auto-generated Match Functions
125 #define GET_ASSEMBLER_HEADER
126 #include "ARMGenAsmMatcher.inc"
130 OperandMatchResultTy parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*>&);
131 OperandMatchResultTy parseCoprocNumOperand(
132 SmallVectorImpl<MCParsedAsmOperand*>&);
133 OperandMatchResultTy parseCoprocRegOperand(
134 SmallVectorImpl<MCParsedAsmOperand*>&);
135 OperandMatchResultTy parseMemBarrierOptOperand(
136 SmallVectorImpl<MCParsedAsmOperand*>&);
137 OperandMatchResultTy parseProcIFlagsOperand(
138 SmallVectorImpl<MCParsedAsmOperand*>&);
139 OperandMatchResultTy parseMSRMaskOperand(
140 SmallVectorImpl<MCParsedAsmOperand*>&);
141 OperandMatchResultTy parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &O,
142 StringRef Op, int Low, int High);
143 OperandMatchResultTy parsePKHLSLImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
144 return parsePKHImm(O, "lsl", 0, 31);
146 OperandMatchResultTy parsePKHASRImm(SmallVectorImpl<MCParsedAsmOperand*> &O) {
147 return parsePKHImm(O, "asr", 1, 32);
149 OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
150 OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
151 OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
152 OperandMatchResultTy parseBitfield(SmallVectorImpl<MCParsedAsmOperand*>&);
153 OperandMatchResultTy parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*>&);
154 OperandMatchResultTy parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*>&);
156 // Asm Match Converter Methods
157 bool cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
158 const SmallVectorImpl<MCParsedAsmOperand*> &);
159 bool cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
160 const SmallVectorImpl<MCParsedAsmOperand*> &);
161 bool cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
162 const SmallVectorImpl<MCParsedAsmOperand*> &);
163 bool cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
164 const SmallVectorImpl<MCParsedAsmOperand*> &);
165 bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
166 const SmallVectorImpl<MCParsedAsmOperand*> &);
167 bool cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
168 const SmallVectorImpl<MCParsedAsmOperand*> &);
169 bool cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
170 const SmallVectorImpl<MCParsedAsmOperand*> &);
171 bool cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
172 const SmallVectorImpl<MCParsedAsmOperand*> &);
173 bool cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
174 const SmallVectorImpl<MCParsedAsmOperand*> &);
175 bool cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
176 const SmallVectorImpl<MCParsedAsmOperand*> &);
177 bool cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
178 const SmallVectorImpl<MCParsedAsmOperand*> &);
179 bool cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
180 const SmallVectorImpl<MCParsedAsmOperand*> &);
181 bool cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
182 const SmallVectorImpl<MCParsedAsmOperand*> &);
183 bool cvtLdrdPre(MCInst &Inst, unsigned Opcode,
184 const SmallVectorImpl<MCParsedAsmOperand*> &);
185 bool cvtStrdPre(MCInst &Inst, unsigned Opcode,
186 const SmallVectorImpl<MCParsedAsmOperand*> &);
187 bool cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
188 const SmallVectorImpl<MCParsedAsmOperand*> &);
189 bool cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
190 const SmallVectorImpl<MCParsedAsmOperand*> &);
192 bool validateInstruction(MCInst &Inst,
193 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
194 void processInstruction(MCInst &Inst,
195 const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
196 bool shouldOmitCCOutOperand(StringRef Mnemonic,
197 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
200 enum ARMMatchResultTy {
201 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
202 Match_RequiresNotITBlock,
207 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
208 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
209 MCAsmParserExtension::Initialize(_Parser);
211 // Initialize the set of available features.
212 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
214 // Not in an ITBlock to start with.
215 ITState.CurPosition = ~0U;
218 // Implementation of the MCTargetAsmParser interface:
219 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
220 bool ParseInstruction(StringRef Name, SMLoc NameLoc,
221 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
222 bool ParseDirective(AsmToken DirectiveID);
224 unsigned checkTargetMatchPredicate(MCInst &Inst);
226 bool MatchAndEmitInstruction(SMLoc IDLoc,
227 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
230 } // end anonymous namespace
234 /// ARMOperand - Instances of this class represent a parsed ARM machine
236 class ARMOperand : public MCParsedAsmOperand {
261 SMLoc StartLoc, EndLoc;
262 SmallVector<unsigned, 8> Registers;
266 ARMCC::CondCodes Val;
282 ARM_PROC::IFlags Val;
302 /// Combined record for all forms of ARM address expressions.
305 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
307 const MCConstantExpr *OffsetImm; // Offset immediate value
308 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
309 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
310 unsigned ShiftImm; // shift for OffsetReg.
311 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
317 ARM_AM::ShiftOpc ShiftTy;
326 ARM_AM::ShiftOpc ShiftTy;
332 ARM_AM::ShiftOpc ShiftTy;
345 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
347 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
349 StartLoc = o.StartLoc;
366 case DPRRegisterList:
367 case SPRRegisterList:
368 Registers = o.Registers;
383 case PostIndexRegister:
384 PostIdxReg = o.PostIdxReg;
392 case ShifterImmediate:
393 ShifterImm = o.ShifterImm;
395 case ShiftedRegister:
396 RegShiftedReg = o.RegShiftedReg;
398 case ShiftedImmediate:
399 RegShiftedImm = o.RegShiftedImm;
401 case RotateImmediate:
404 case BitfieldDescriptor:
405 Bitfield = o.Bitfield;
410 /// getStartLoc - Get the location of the first token of this operand.
411 SMLoc getStartLoc() const { return StartLoc; }
412 /// getEndLoc - Get the location of the last token of this operand.
413 SMLoc getEndLoc() const { return EndLoc; }
415 ARMCC::CondCodes getCondCode() const {
416 assert(Kind == CondCode && "Invalid access!");
420 unsigned getCoproc() const {
421 assert((Kind == CoprocNum || Kind == CoprocReg) && "Invalid access!");
425 StringRef getToken() const {
426 assert(Kind == Token && "Invalid access!");
427 return StringRef(Tok.Data, Tok.Length);
430 unsigned getReg() const {
431 assert((Kind == Register || Kind == CCOut) && "Invalid access!");
435 const SmallVectorImpl<unsigned> &getRegList() const {
436 assert((Kind == RegisterList || Kind == DPRRegisterList ||
437 Kind == SPRRegisterList) && "Invalid access!");
441 const MCExpr *getImm() const {
442 assert(Kind == Immediate && "Invalid access!");
446 ARM_MB::MemBOpt getMemBarrierOpt() const {
447 assert(Kind == MemBarrierOpt && "Invalid access!");
451 ARM_PROC::IFlags getProcIFlags() const {
452 assert(Kind == ProcIFlags && "Invalid access!");
456 unsigned getMSRMask() const {
457 assert(Kind == MSRMask && "Invalid access!");
461 bool isCoprocNum() const { return Kind == CoprocNum; }
462 bool isCoprocReg() const { return Kind == CoprocReg; }
463 bool isCondCode() const { return Kind == CondCode; }
464 bool isCCOut() const { return Kind == CCOut; }
465 bool isITMask() const { return Kind == ITCondMask; }
466 bool isITCondCode() const { return Kind == CondCode; }
467 bool isImm() const { return Kind == Immediate; }
468 bool isImm8s4() const {
469 if (Kind != Immediate)
471 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
472 if (!CE) return false;
473 int64_t Value = CE->getValue();
474 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
476 bool isImm0_1020s4() const {
477 if (Kind != Immediate)
479 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
480 if (!CE) return false;
481 int64_t Value = CE->getValue();
482 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
484 bool isImm0_508s4() const {
485 if (Kind != Immediate)
487 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
488 if (!CE) return false;
489 int64_t Value = CE->getValue();
490 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
492 bool isImm0_255() const {
493 if (Kind != Immediate)
495 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
496 if (!CE) return false;
497 int64_t Value = CE->getValue();
498 return Value >= 0 && Value < 256;
500 bool isImm0_7() const {
501 if (Kind != Immediate)
503 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
504 if (!CE) return false;
505 int64_t Value = CE->getValue();
506 return Value >= 0 && Value < 8;
508 bool isImm0_15() const {
509 if (Kind != Immediate)
511 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
512 if (!CE) return false;
513 int64_t Value = CE->getValue();
514 return Value >= 0 && Value < 16;
516 bool isImm0_31() const {
517 if (Kind != Immediate)
519 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
520 if (!CE) return false;
521 int64_t Value = CE->getValue();
522 return Value >= 0 && Value < 32;
524 bool isImm1_16() const {
525 if (Kind != Immediate)
527 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
528 if (!CE) return false;
529 int64_t Value = CE->getValue();
530 return Value > 0 && Value < 17;
532 bool isImm1_32() const {
533 if (Kind != Immediate)
535 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
536 if (!CE) return false;
537 int64_t Value = CE->getValue();
538 return Value > 0 && Value < 33;
540 bool isImm0_65535() const {
541 if (Kind != Immediate)
543 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
544 if (!CE) return false;
545 int64_t Value = CE->getValue();
546 return Value >= 0 && Value < 65536;
548 bool isImm0_65535Expr() const {
549 if (Kind != Immediate)
551 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
552 // If it's not a constant expression, it'll generate a fixup and be
554 if (!CE) return true;
555 int64_t Value = CE->getValue();
556 return Value >= 0 && Value < 65536;
558 bool isImm24bit() const {
559 if (Kind != Immediate)
561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
562 if (!CE) return false;
563 int64_t Value = CE->getValue();
564 return Value >= 0 && Value <= 0xffffff;
566 bool isImmThumbSR() const {
567 if (Kind != Immediate)
569 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
570 if (!CE) return false;
571 int64_t Value = CE->getValue();
572 return Value > 0 && Value < 33;
574 bool isPKHLSLImm() const {
575 if (Kind != Immediate)
577 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
578 if (!CE) return false;
579 int64_t Value = CE->getValue();
580 return Value >= 0 && Value < 32;
582 bool isPKHASRImm() const {
583 if (Kind != Immediate)
585 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
586 if (!CE) return false;
587 int64_t Value = CE->getValue();
588 return Value > 0 && Value <= 32;
590 bool isARMSOImm() const {
591 if (Kind != Immediate)
593 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
594 if (!CE) return false;
595 int64_t Value = CE->getValue();
596 return ARM_AM::getSOImmVal(Value) != -1;
598 bool isT2SOImm() const {
599 if (Kind != Immediate)
601 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
602 if (!CE) return false;
603 int64_t Value = CE->getValue();
604 return ARM_AM::getT2SOImmVal(Value) != -1;
606 bool isSetEndImm() const {
607 if (Kind != Immediate)
609 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
610 if (!CE) return false;
611 int64_t Value = CE->getValue();
612 return Value == 1 || Value == 0;
614 bool isReg() const { return Kind == Register; }
615 bool isRegList() const { return Kind == RegisterList; }
616 bool isDPRRegList() const { return Kind == DPRRegisterList; }
617 bool isSPRRegList() const { return Kind == SPRRegisterList; }
618 bool isToken() const { return Kind == Token; }
619 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
620 bool isMemory() const { return Kind == Memory; }
621 bool isShifterImm() const { return Kind == ShifterImmediate; }
622 bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
623 bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
624 bool isRotImm() const { return Kind == RotateImmediate; }
625 bool isBitfield() const { return Kind == BitfieldDescriptor; }
626 bool isPostIdxRegShifted() const { return Kind == PostIndexRegister; }
627 bool isPostIdxReg() const {
628 return Kind == PostIndexRegister && PostIdxReg.ShiftTy == ARM_AM::no_shift;
630 bool isMemNoOffset() const {
633 // No offset of any kind.
634 return Mem.OffsetRegNum == 0 && Mem.OffsetImm == 0;
636 bool isAddrMode2() const {
639 // Check for register offset.
640 if (Mem.OffsetRegNum) return true;
641 // Immediate offset in range [-4095, 4095].
642 if (!Mem.OffsetImm) return true;
643 int64_t Val = Mem.OffsetImm->getValue();
644 return Val > -4096 && Val < 4096;
646 bool isAM2OffsetImm() const {
647 if (Kind != Immediate)
649 // Immediate offset in range [-4095, 4095].
650 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
651 if (!CE) return false;
652 int64_t Val = CE->getValue();
653 return Val > -4096 && Val < 4096;
655 bool isAddrMode3() const {
658 // No shifts are legal for AM3.
659 if (Mem.ShiftType != ARM_AM::no_shift) return false;
660 // Check for register offset.
661 if (Mem.OffsetRegNum) return true;
662 // Immediate offset in range [-255, 255].
663 if (!Mem.OffsetImm) return true;
664 int64_t Val = Mem.OffsetImm->getValue();
665 return Val > -256 && Val < 256;
667 bool isAM3Offset() const {
668 if (Kind != Immediate && Kind != PostIndexRegister)
670 if (Kind == PostIndexRegister)
671 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
672 // Immediate offset in range [-255, 255].
673 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
674 if (!CE) return false;
675 int64_t Val = CE->getValue();
676 // Special case, #-0 is INT32_MIN.
677 return (Val > -256 && Val < 256) || Val == INT32_MIN;
679 bool isAddrMode5() const {
682 // Check for register offset.
683 if (Mem.OffsetRegNum) return false;
684 // Immediate offset in range [-1020, 1020] and a multiple of 4.
685 if (!Mem.OffsetImm) return true;
686 int64_t Val = Mem.OffsetImm->getValue();
687 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
690 bool isMemRegOffset() const {
691 if (Kind != Memory || !Mem.OffsetRegNum)
695 bool isT2MemRegOffset() const {
696 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative)
698 // Only lsl #{0, 1, 2, 3} allowed.
699 if (Mem.ShiftType == ARM_AM::no_shift)
701 if (Mem.ShiftType != ARM_AM::lsl || Mem.ShiftImm > 3)
705 bool isMemThumbRR() const {
706 // Thumb reg+reg addressing is simple. Just two registers, a base and
707 // an offset. No shifts, negations or any other complicating factors.
708 if (Kind != Memory || !Mem.OffsetRegNum || Mem.isNegative ||
709 Mem.ShiftType != ARM_AM::no_shift)
711 return isARMLowRegister(Mem.BaseRegNum) &&
712 (!Mem.OffsetRegNum || isARMLowRegister(Mem.OffsetRegNum));
714 bool isMemThumbRIs4() const {
715 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
716 !isARMLowRegister(Mem.BaseRegNum))
718 // Immediate offset, multiple of 4 in range [0, 124].
719 if (!Mem.OffsetImm) return true;
720 int64_t Val = Mem.OffsetImm->getValue();
721 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
723 bool isMemThumbRIs2() const {
724 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
725 !isARMLowRegister(Mem.BaseRegNum))
727 // Immediate offset, multiple of 4 in range [0, 62].
728 if (!Mem.OffsetImm) return true;
729 int64_t Val = Mem.OffsetImm->getValue();
730 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
732 bool isMemThumbRIs1() const {
733 if (Kind != Memory || Mem.OffsetRegNum != 0 ||
734 !isARMLowRegister(Mem.BaseRegNum))
736 // Immediate offset in range [0, 31].
737 if (!Mem.OffsetImm) return true;
738 int64_t Val = Mem.OffsetImm->getValue();
739 return Val >= 0 && Val <= 31;
741 bool isMemThumbSPI() const {
742 if (Kind != Memory || Mem.OffsetRegNum != 0 || Mem.BaseRegNum != ARM::SP)
744 // Immediate offset, multiple of 4 in range [0, 1020].
745 if (!Mem.OffsetImm) return true;
746 int64_t Val = Mem.OffsetImm->getValue();
747 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
749 bool isMemImm8s4Offset() const {
750 if (Kind != Memory || Mem.OffsetRegNum != 0)
752 // Immediate offset a multiple of 4 in range [-1020, 1020].
753 if (!Mem.OffsetImm) return true;
754 int64_t Val = Mem.OffsetImm->getValue();
755 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
757 bool isMemImm0_1020s4Offset() const {
758 if (Kind != Memory || Mem.OffsetRegNum != 0)
760 // Immediate offset a multiple of 4 in range [0, 1020].
761 if (!Mem.OffsetImm) return true;
762 int64_t Val = Mem.OffsetImm->getValue();
763 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
765 bool isMemImm8Offset() const {
766 if (Kind != Memory || Mem.OffsetRegNum != 0)
768 // Immediate offset in range [-255, 255].
769 if (!Mem.OffsetImm) return true;
770 int64_t Val = Mem.OffsetImm->getValue();
771 return Val > -256 && Val < 256;
773 bool isMemPosImm8Offset() const {
774 if (Kind != Memory || Mem.OffsetRegNum != 0)
776 // Immediate offset in range [0, 255].
777 if (!Mem.OffsetImm) return true;
778 int64_t Val = Mem.OffsetImm->getValue();
779 return Val >= 0 && Val < 256;
781 bool isMemNegImm8Offset() const {
782 if (Kind != Memory || Mem.OffsetRegNum != 0)
784 // Immediate offset in range [-255, -1].
785 if (!Mem.OffsetImm) return true;
786 int64_t Val = Mem.OffsetImm->getValue();
787 return Val > -256 && Val < 0;
789 bool isMemUImm12Offset() const {
790 // If we have an immediate that's not a constant, treat it as a label
791 // reference needing a fixup. If it is a constant, it's something else
793 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
796 if (Kind != Memory || Mem.OffsetRegNum != 0)
798 // Immediate offset in range [0, 4095].
799 if (!Mem.OffsetImm) return true;
800 int64_t Val = Mem.OffsetImm->getValue();
801 return (Val >= 0 && Val < 4096);
803 bool isMemImm12Offset() const {
804 // If we have an immediate that's not a constant, treat it as a label
805 // reference needing a fixup. If it is a constant, it's something else
807 if (Kind == Immediate && !isa<MCConstantExpr>(getImm()))
810 if (Kind != Memory || Mem.OffsetRegNum != 0)
812 // Immediate offset in range [-4095, 4095].
813 if (!Mem.OffsetImm) return true;
814 int64_t Val = Mem.OffsetImm->getValue();
815 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
817 bool isPostIdxImm8() const {
818 if (Kind != Immediate)
820 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
821 if (!CE) return false;
822 int64_t Val = CE->getValue();
823 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
826 bool isMSRMask() const { return Kind == MSRMask; }
827 bool isProcIFlags() const { return Kind == ProcIFlags; }
829 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
830 // Add as immediates when possible. Null MCExpr = 0.
832 Inst.addOperand(MCOperand::CreateImm(0));
833 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
834 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
836 Inst.addOperand(MCOperand::CreateExpr(Expr));
839 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
840 assert(N == 2 && "Invalid number of operands!");
841 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
842 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
843 Inst.addOperand(MCOperand::CreateReg(RegNum));
846 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
847 assert(N == 1 && "Invalid number of operands!");
848 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
851 void addITMaskOperands(MCInst &Inst, unsigned N) const {
852 assert(N == 1 && "Invalid number of operands!");
853 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
856 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
857 assert(N == 1 && "Invalid number of operands!");
858 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
861 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
862 assert(N == 1 && "Invalid number of operands!");
863 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
866 void addCCOutOperands(MCInst &Inst, unsigned N) const {
867 assert(N == 1 && "Invalid number of operands!");
868 Inst.addOperand(MCOperand::CreateReg(getReg()));
871 void addRegOperands(MCInst &Inst, unsigned N) const {
872 assert(N == 1 && "Invalid number of operands!");
873 Inst.addOperand(MCOperand::CreateReg(getReg()));
876 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
877 assert(N == 3 && "Invalid number of operands!");
878 assert(isRegShiftedReg() && "addRegShiftedRegOperands() on non RegShiftedReg!");
879 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
880 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
881 Inst.addOperand(MCOperand::CreateImm(
882 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
885 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
886 assert(N == 2 && "Invalid number of operands!");
887 assert(isRegShiftedImm() && "addRegShiftedImmOperands() on non RegShiftedImm!");
888 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
889 Inst.addOperand(MCOperand::CreateImm(
890 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, RegShiftedImm.ShiftImm)));
893 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
894 assert(N == 1 && "Invalid number of operands!");
895 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
899 void addRegListOperands(MCInst &Inst, unsigned N) const {
900 assert(N == 1 && "Invalid number of operands!");
901 const SmallVectorImpl<unsigned> &RegList = getRegList();
902 for (SmallVectorImpl<unsigned>::const_iterator
903 I = RegList.begin(), E = RegList.end(); I != E; ++I)
904 Inst.addOperand(MCOperand::CreateReg(*I));
907 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
908 addRegListOperands(Inst, N);
911 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
912 addRegListOperands(Inst, N);
915 void addRotImmOperands(MCInst &Inst, unsigned N) const {
916 assert(N == 1 && "Invalid number of operands!");
917 // Encoded as val>>3. The printer handles display as 8, 16, 24.
918 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
921 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
922 assert(N == 1 && "Invalid number of operands!");
923 // Munge the lsb/width into a bitfield mask.
924 unsigned lsb = Bitfield.LSB;
925 unsigned width = Bitfield.Width;
926 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
927 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
928 (32 - (lsb + width)));
929 Inst.addOperand(MCOperand::CreateImm(Mask));
932 void addImmOperands(MCInst &Inst, unsigned N) const {
933 assert(N == 1 && "Invalid number of operands!");
934 addExpr(Inst, getImm());
937 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
938 assert(N == 1 && "Invalid number of operands!");
939 // FIXME: We really want to scale the value here, but the LDRD/STRD
940 // instruction don't encode operands that way yet.
941 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
942 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
945 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
946 assert(N == 1 && "Invalid number of operands!");
947 // The immediate is scaled by four in the encoding and is stored
948 // in the MCInst as such. Lop off the low two bits here.
949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
950 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
953 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
954 assert(N == 1 && "Invalid number of operands!");
955 // The immediate is scaled by four in the encoding and is stored
956 // in the MCInst as such. Lop off the low two bits here.
957 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
958 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
961 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
962 assert(N == 1 && "Invalid number of operands!");
963 addExpr(Inst, getImm());
966 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
967 assert(N == 1 && "Invalid number of operands!");
968 addExpr(Inst, getImm());
971 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
972 assert(N == 1 && "Invalid number of operands!");
973 addExpr(Inst, getImm());
976 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
977 assert(N == 1 && "Invalid number of operands!");
978 addExpr(Inst, getImm());
981 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
982 assert(N == 1 && "Invalid number of operands!");
983 // The constant encodes as the immediate-1, and we store in the instruction
984 // the bits as encoded, so subtract off one here.
985 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
986 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
989 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
990 assert(N == 1 && "Invalid number of operands!");
991 // The constant encodes as the immediate-1, and we store in the instruction
992 // the bits as encoded, so subtract off one here.
993 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
994 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
997 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
998 assert(N == 1 && "Invalid number of operands!");
999 addExpr(Inst, getImm());
1002 void addImm0_65535ExprOperands(MCInst &Inst, unsigned N) const {
1003 assert(N == 1 && "Invalid number of operands!");
1004 addExpr(Inst, getImm());
1007 void addImm24bitOperands(MCInst &Inst, unsigned N) const {
1008 assert(N == 1 && "Invalid number of operands!");
1009 addExpr(Inst, getImm());
1012 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1013 assert(N == 1 && "Invalid number of operands!");
1014 // The constant encodes as the immediate, except for 32, which encodes as
1016 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1017 unsigned Imm = CE->getValue();
1018 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1021 void addPKHLSLImmOperands(MCInst &Inst, unsigned N) const {
1022 assert(N == 1 && "Invalid number of operands!");
1023 addExpr(Inst, getImm());
1026 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1027 assert(N == 1 && "Invalid number of operands!");
1028 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1029 // the instruction as well.
1030 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1031 int Val = CE->getValue();
1032 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1035 void addARMSOImmOperands(MCInst &Inst, unsigned N) const {
1036 assert(N == 1 && "Invalid number of operands!");
1037 addExpr(Inst, getImm());
1040 void addT2SOImmOperands(MCInst &Inst, unsigned N) const {
1041 assert(N == 1 && "Invalid number of operands!");
1042 addExpr(Inst, getImm());
1045 void addSetEndImmOperands(MCInst &Inst, unsigned N) const {
1046 assert(N == 1 && "Invalid number of operands!");
1047 addExpr(Inst, getImm());
1050 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1051 assert(N == 1 && "Invalid number of operands!");
1052 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
1055 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1056 assert(N == 1 && "Invalid number of operands!");
1057 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1060 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
1061 assert(N == 3 && "Invalid number of operands!");
1062 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1063 if (!Mem.OffsetRegNum) {
1064 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1065 // Special case for #-0
1066 if (Val == INT32_MIN) Val = 0;
1067 if (Val < 0) Val = -Val;
1068 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1070 // For register offset, we encode the shift type and negation flag
1072 Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1073 Mem.ShiftImm, Mem.ShiftType);
1075 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1076 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1077 Inst.addOperand(MCOperand::CreateImm(Val));
1080 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
1081 assert(N == 2 && "Invalid number of operands!");
1082 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1083 assert(CE && "non-constant AM2OffsetImm operand!");
1084 int32_t Val = CE->getValue();
1085 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1086 // Special case for #-0
1087 if (Val == INT32_MIN) Val = 0;
1088 if (Val < 0) Val = -Val;
1089 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
1090 Inst.addOperand(MCOperand::CreateReg(0));
1091 Inst.addOperand(MCOperand::CreateImm(Val));
1094 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
1095 assert(N == 3 && "Invalid number of operands!");
1096 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1097 if (!Mem.OffsetRegNum) {
1098 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1099 // Special case for #-0
1100 if (Val == INT32_MIN) Val = 0;
1101 if (Val < 0) Val = -Val;
1102 Val = ARM_AM::getAM3Opc(AddSub, Val);
1104 // For register offset, we encode the shift type and negation flag
1106 Val = ARM_AM::getAM3Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
1108 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1109 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1110 Inst.addOperand(MCOperand::CreateImm(Val));
1113 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
1114 assert(N == 2 && "Invalid number of operands!");
1115 if (Kind == PostIndexRegister) {
1117 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
1118 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1119 Inst.addOperand(MCOperand::CreateImm(Val));
1124 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
1125 int32_t Val = CE->getValue();
1126 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1127 // Special case for #-0
1128 if (Val == INT32_MIN) Val = 0;
1129 if (Val < 0) Val = -Val;
1130 Val = ARM_AM::getAM3Opc(AddSub, Val);
1131 Inst.addOperand(MCOperand::CreateReg(0));
1132 Inst.addOperand(MCOperand::CreateImm(Val));
1135 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
1136 assert(N == 2 && "Invalid number of operands!");
1137 // The lower two bits are always zero and as such are not encoded.
1138 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1139 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
1140 // Special case for #-0
1141 if (Val == INT32_MIN) Val = 0;
1142 if (Val < 0) Val = -Val;
1143 Val = ARM_AM::getAM5Opc(AddSub, Val);
1144 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1145 Inst.addOperand(MCOperand::CreateImm(Val));
1148 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
1149 assert(N == 2 && "Invalid number of operands!");
1150 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1151 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1152 Inst.addOperand(MCOperand::CreateImm(Val));
1155 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
1156 assert(N == 2 && "Invalid number of operands!");
1157 // The lower two bits are always zero and as such are not encoded.
1158 int32_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() / 4 : 0;
1159 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1160 Inst.addOperand(MCOperand::CreateImm(Val));
1163 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1164 assert(N == 2 && "Invalid number of operands!");
1165 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1166 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1167 Inst.addOperand(MCOperand::CreateImm(Val));
1170 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1171 addMemImm8OffsetOperands(Inst, N);
1174 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
1175 addMemImm8OffsetOperands(Inst, N);
1178 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1179 assert(N == 2 && "Invalid number of operands!");
1180 // If this is an immediate, it's a label reference.
1181 if (Kind == Immediate) {
1182 addExpr(Inst, getImm());
1183 Inst.addOperand(MCOperand::CreateImm(0));
1187 // Otherwise, it's a normal memory reg+offset.
1188 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1189 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1190 Inst.addOperand(MCOperand::CreateImm(Val));
1193 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
1194 assert(N == 2 && "Invalid number of operands!");
1195 // If this is an immediate, it's a label reference.
1196 if (Kind == Immediate) {
1197 addExpr(Inst, getImm());
1198 Inst.addOperand(MCOperand::CreateImm(0));
1202 // Otherwise, it's a normal memory reg+offset.
1203 int64_t Val = Mem.OffsetImm ? Mem.OffsetImm->getValue() : 0;
1204 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1205 Inst.addOperand(MCOperand::CreateImm(Val));
1208 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1209 assert(N == 3 && "Invalid number of operands!");
1210 unsigned Val = ARM_AM::getAM2Opc(Mem.isNegative ? ARM_AM::sub : ARM_AM::add,
1211 Mem.ShiftImm, Mem.ShiftType);
1212 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1213 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1214 Inst.addOperand(MCOperand::CreateImm(Val));
1217 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
1218 assert(N == 3 && "Invalid number of operands!");
1219 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1220 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1221 Inst.addOperand(MCOperand::CreateImm(Mem.ShiftImm));
1224 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
1225 assert(N == 2 && "Invalid number of operands!");
1226 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1227 Inst.addOperand(MCOperand::CreateReg(Mem.OffsetRegNum));
1230 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
1231 assert(N == 2 && "Invalid number of operands!");
1232 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1233 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1234 Inst.addOperand(MCOperand::CreateImm(Val));
1237 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
1238 assert(N == 2 && "Invalid number of operands!");
1239 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 2) : 0;
1240 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1241 Inst.addOperand(MCOperand::CreateImm(Val));
1244 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
1245 assert(N == 2 && "Invalid number of operands!");
1246 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue()) : 0;
1247 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1248 Inst.addOperand(MCOperand::CreateImm(Val));
1251 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
1252 assert(N == 2 && "Invalid number of operands!");
1253 int64_t Val = Mem.OffsetImm ? (Mem.OffsetImm->getValue() / 4) : 0;
1254 Inst.addOperand(MCOperand::CreateReg(Mem.BaseRegNum));
1255 Inst.addOperand(MCOperand::CreateImm(Val));
1258 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
1259 assert(N == 1 && "Invalid number of operands!");
1260 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1261 assert(CE && "non-constant post-idx-imm8 operand!");
1262 int Imm = CE->getValue();
1263 bool isAdd = Imm >= 0;
1264 if (Imm == INT32_MIN) Imm = 0;
1265 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
1266 Inst.addOperand(MCOperand::CreateImm(Imm));
1269 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
1270 assert(N == 2 && "Invalid number of operands!");
1271 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1272 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
1275 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
1276 assert(N == 2 && "Invalid number of operands!");
1277 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
1278 // The sign, shift type, and shift amount are encoded in a single operand
1279 // using the AM2 encoding helpers.
1280 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
1281 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
1282 PostIdxReg.ShiftTy);
1283 Inst.addOperand(MCOperand::CreateImm(Imm));
1286 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
1287 assert(N == 1 && "Invalid number of operands!");
1288 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
1291 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
1292 assert(N == 1 && "Invalid number of operands!");
1293 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
1296 virtual void print(raw_ostream &OS) const;
1298 static ARMOperand *CreateITMask(unsigned Mask, SMLoc S) {
1299 ARMOperand *Op = new ARMOperand(ITCondMask);
1300 Op->ITMask.Mask = Mask;
1306 static ARMOperand *CreateCondCode(ARMCC::CondCodes CC, SMLoc S) {
1307 ARMOperand *Op = new ARMOperand(CondCode);
1314 static ARMOperand *CreateCoprocNum(unsigned CopVal, SMLoc S) {
1315 ARMOperand *Op = new ARMOperand(CoprocNum);
1316 Op->Cop.Val = CopVal;
1322 static ARMOperand *CreateCoprocReg(unsigned CopVal, SMLoc S) {
1323 ARMOperand *Op = new ARMOperand(CoprocReg);
1324 Op->Cop.Val = CopVal;
1330 static ARMOperand *CreateCCOut(unsigned RegNum, SMLoc S) {
1331 ARMOperand *Op = new ARMOperand(CCOut);
1332 Op->Reg.RegNum = RegNum;
1338 static ARMOperand *CreateToken(StringRef Str, SMLoc S) {
1339 ARMOperand *Op = new ARMOperand(Token);
1340 Op->Tok.Data = Str.data();
1341 Op->Tok.Length = Str.size();
1347 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
1348 ARMOperand *Op = new ARMOperand(Register);
1349 Op->Reg.RegNum = RegNum;
1355 static ARMOperand *CreateShiftedRegister(ARM_AM::ShiftOpc ShTy,
1360 ARMOperand *Op = new ARMOperand(ShiftedRegister);
1361 Op->RegShiftedReg.ShiftTy = ShTy;
1362 Op->RegShiftedReg.SrcReg = SrcReg;
1363 Op->RegShiftedReg.ShiftReg = ShiftReg;
1364 Op->RegShiftedReg.ShiftImm = ShiftImm;
1370 static ARMOperand *CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy,
1374 ARMOperand *Op = new ARMOperand(ShiftedImmediate);
1375 Op->RegShiftedImm.ShiftTy = ShTy;
1376 Op->RegShiftedImm.SrcReg = SrcReg;
1377 Op->RegShiftedImm.ShiftImm = ShiftImm;
1383 static ARMOperand *CreateShifterImm(bool isASR, unsigned Imm,
1385 ARMOperand *Op = new ARMOperand(ShifterImmediate);
1386 Op->ShifterImm.isASR = isASR;
1387 Op->ShifterImm.Imm = Imm;
1393 static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
1394 ARMOperand *Op = new ARMOperand(RotateImmediate);
1395 Op->RotImm.Imm = Imm;
1401 static ARMOperand *CreateBitfield(unsigned LSB, unsigned Width,
1403 ARMOperand *Op = new ARMOperand(BitfieldDescriptor);
1404 Op->Bitfield.LSB = LSB;
1405 Op->Bitfield.Width = Width;
1412 CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
1413 SMLoc StartLoc, SMLoc EndLoc) {
1414 KindTy Kind = RegisterList;
1416 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().first))
1417 Kind = DPRRegisterList;
1418 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
1419 contains(Regs.front().first))
1420 Kind = SPRRegisterList;
1422 ARMOperand *Op = new ARMOperand(Kind);
1423 for (SmallVectorImpl<std::pair<unsigned, SMLoc> >::const_iterator
1424 I = Regs.begin(), E = Regs.end(); I != E; ++I)
1425 Op->Registers.push_back(I->first);
1426 array_pod_sort(Op->Registers.begin(), Op->Registers.end());
1427 Op->StartLoc = StartLoc;
1428 Op->EndLoc = EndLoc;
1432 static ARMOperand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
1433 ARMOperand *Op = new ARMOperand(Immediate);
1440 static ARMOperand *CreateMem(unsigned BaseRegNum,
1441 const MCConstantExpr *OffsetImm,
1442 unsigned OffsetRegNum,
1443 ARM_AM::ShiftOpc ShiftType,
1447 ARMOperand *Op = new ARMOperand(Memory);
1448 Op->Mem.BaseRegNum = BaseRegNum;
1449 Op->Mem.OffsetImm = OffsetImm;
1450 Op->Mem.OffsetRegNum = OffsetRegNum;
1451 Op->Mem.ShiftType = ShiftType;
1452 Op->Mem.ShiftImm = ShiftImm;
1453 Op->Mem.isNegative = isNegative;
1459 static ARMOperand *CreatePostIdxReg(unsigned RegNum, bool isAdd,
1460 ARM_AM::ShiftOpc ShiftTy,
1463 ARMOperand *Op = new ARMOperand(PostIndexRegister);
1464 Op->PostIdxReg.RegNum = RegNum;
1465 Op->PostIdxReg.isAdd = isAdd;
1466 Op->PostIdxReg.ShiftTy = ShiftTy;
1467 Op->PostIdxReg.ShiftImm = ShiftImm;
1473 static ARMOperand *CreateMemBarrierOpt(ARM_MB::MemBOpt Opt, SMLoc S) {
1474 ARMOperand *Op = new ARMOperand(MemBarrierOpt);
1475 Op->MBOpt.Val = Opt;
1481 static ARMOperand *CreateProcIFlags(ARM_PROC::IFlags IFlags, SMLoc S) {
1482 ARMOperand *Op = new ARMOperand(ProcIFlags);
1483 Op->IFlags.Val = IFlags;
1489 static ARMOperand *CreateMSRMask(unsigned MMask, SMLoc S) {
1490 ARMOperand *Op = new ARMOperand(MSRMask);
1491 Op->MMask.Val = MMask;
1498 } // end anonymous namespace.
1500 void ARMOperand::print(raw_ostream &OS) const {
1503 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
1506 OS << "<ccout " << getReg() << ">";
1509 static char MaskStr[][6] = { "()", "(t)", "(e)", "(tt)", "(et)", "(te)",
1510 "(ee)", "(ttt)", "(ett)", "(tet)", "(eet)", "(tte)", "(ete)",
1512 assert((ITMask.Mask & 0xf) == ITMask.Mask);
1513 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
1517 OS << "<coprocessor number: " << getCoproc() << ">";
1520 OS << "<coprocessor register: " << getCoproc() << ">";
1523 OS << "<mask: " << getMSRMask() << ">";
1526 getImm()->print(OS);
1529 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt()) << ">";
1533 << " base:" << Mem.BaseRegNum;
1536 case PostIndexRegister:
1537 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
1538 << PostIdxReg.RegNum;
1539 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
1540 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
1541 << PostIdxReg.ShiftImm;
1545 OS << "<ARM_PROC::";
1546 unsigned IFlags = getProcIFlags();
1547 for (int i=2; i >= 0; --i)
1548 if (IFlags & (1 << i))
1549 OS << ARM_PROC::IFlagsToString(1 << i);
1554 OS << "<register " << getReg() << ">";
1556 case ShifterImmediate:
1557 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
1558 << " #" << ShifterImm.Imm << ">";
1560 case ShiftedRegister:
1561 OS << "<so_reg_reg "
1562 << RegShiftedReg.SrcReg
1563 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedReg.ShiftImm))
1564 << ", " << RegShiftedReg.ShiftReg << ", "
1565 << ARM_AM::getSORegOffset(RegShiftedReg.ShiftImm)
1568 case ShiftedImmediate:
1569 OS << "<so_reg_imm "
1570 << RegShiftedImm.SrcReg
1571 << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(RegShiftedImm.ShiftImm))
1572 << ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
1575 case RotateImmediate:
1576 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
1578 case BitfieldDescriptor:
1579 OS << "<bitfield " << "lsb: " << Bitfield.LSB
1580 << ", width: " << Bitfield.Width << ">";
1583 case DPRRegisterList:
1584 case SPRRegisterList: {
1585 OS << "<register_list ";
1587 const SmallVectorImpl<unsigned> &RegList = getRegList();
1588 for (SmallVectorImpl<unsigned>::const_iterator
1589 I = RegList.begin(), E = RegList.end(); I != E; ) {
1591 if (++I < E) OS << ", ";
1598 OS << "'" << getToken() << "'";
1603 /// @name Auto-generated Match Functions
1606 static unsigned MatchRegisterName(StringRef Name);
1610 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
1611 SMLoc &StartLoc, SMLoc &EndLoc) {
1612 RegNo = tryParseRegister();
1614 return (RegNo == (unsigned)-1);
1617 /// Try to parse a register name. The token must be an Identifier when called,
1618 /// and if it is a register name the token is eaten and the register number is
1619 /// returned. Otherwise return -1.
1621 int ARMAsmParser::tryParseRegister() {
1622 const AsmToken &Tok = Parser.getTok();
1623 if (Tok.isNot(AsmToken::Identifier)) return -1;
1625 // FIXME: Validate register for the current architecture; we have to do
1626 // validation later, so maybe there is no need for this here.
1627 std::string upperCase = Tok.getString().str();
1628 std::string lowerCase = LowercaseString(upperCase);
1629 unsigned RegNum = MatchRegisterName(lowerCase);
1631 RegNum = StringSwitch<unsigned>(lowerCase)
1632 .Case("r13", ARM::SP)
1633 .Case("r14", ARM::LR)
1634 .Case("r15", ARM::PC)
1635 .Case("ip", ARM::R12)
1638 if (!RegNum) return -1;
1640 Parser.Lex(); // Eat identifier token.
1644 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
1645 // If a recoverable error occurs, return 1. If an irrecoverable error
1646 // occurs, return -1. An irrecoverable error is one where tokens have been
1647 // consumed in the process of trying to parse the shifter (i.e., when it is
1648 // indeed a shifter operand, but malformed).
1649 int ARMAsmParser::tryParseShiftRegister(
1650 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1651 SMLoc S = Parser.getTok().getLoc();
1652 const AsmToken &Tok = Parser.getTok();
1653 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1655 std::string upperCase = Tok.getString().str();
1656 std::string lowerCase = LowercaseString(upperCase);
1657 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
1658 .Case("lsl", ARM_AM::lsl)
1659 .Case("lsr", ARM_AM::lsr)
1660 .Case("asr", ARM_AM::asr)
1661 .Case("ror", ARM_AM::ror)
1662 .Case("rrx", ARM_AM::rrx)
1663 .Default(ARM_AM::no_shift);
1665 if (ShiftTy == ARM_AM::no_shift)
1668 Parser.Lex(); // Eat the operator.
1670 // The source register for the shift has already been added to the
1671 // operand list, so we need to pop it off and combine it into the shifted
1672 // register operand instead.
1673 OwningPtr<ARMOperand> PrevOp((ARMOperand*)Operands.pop_back_val());
1674 if (!PrevOp->isReg())
1675 return Error(PrevOp->getStartLoc(), "shift must be of a register");
1676 int SrcReg = PrevOp->getReg();
1679 if (ShiftTy == ARM_AM::rrx) {
1680 // RRX Doesn't have an explicit shift amount. The encoder expects
1681 // the shift register to be the same as the source register. Seems odd,
1685 // Figure out if this is shifted by a constant or a register (for non-RRX).
1686 if (Parser.getTok().is(AsmToken::Hash)) {
1687 Parser.Lex(); // Eat hash.
1688 SMLoc ImmLoc = Parser.getTok().getLoc();
1689 const MCExpr *ShiftExpr = 0;
1690 if (getParser().ParseExpression(ShiftExpr)) {
1691 Error(ImmLoc, "invalid immediate shift value");
1694 // The expression must be evaluatable as an immediate.
1695 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
1697 Error(ImmLoc, "invalid immediate shift value");
1700 // Range check the immediate.
1701 // lsl, ror: 0 <= imm <= 31
1702 // lsr, asr: 0 <= imm <= 32
1703 Imm = CE->getValue();
1705 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
1706 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
1707 Error(ImmLoc, "immediate shift value out of range");
1710 } else if (Parser.getTok().is(AsmToken::Identifier)) {
1711 ShiftReg = tryParseRegister();
1712 SMLoc L = Parser.getTok().getLoc();
1713 if (ShiftReg == -1) {
1714 Error (L, "expected immediate or register in shift operand");
1718 Error (Parser.getTok().getLoc(),
1719 "expected immediate or register in shift operand");
1724 if (ShiftReg && ShiftTy != ARM_AM::rrx)
1725 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
1727 S, Parser.getTok().getLoc()));
1729 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
1730 S, Parser.getTok().getLoc()));
1736 /// Try to parse a register name. The token must be an Identifier when called.
1737 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
1738 /// if there is a "writeback". 'true' if it's not a register.
1740 /// TODO this is likely to change to allow different register types and or to
1741 /// parse for a specific register type.
1743 tryParseRegisterWithWriteBack(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1744 SMLoc S = Parser.getTok().getLoc();
1745 int RegNo = tryParseRegister();
1749 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
1751 const AsmToken &ExclaimTok = Parser.getTok();
1752 if (ExclaimTok.is(AsmToken::Exclaim)) {
1753 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
1754 ExclaimTok.getLoc()));
1755 Parser.Lex(); // Eat exclaim token
1761 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
1762 /// instruction with a symbolic operand name. Example: "p1", "p7", "c3",
1764 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
1765 // Use the same layout as the tablegen'erated register name matcher. Ugly,
1767 switch (Name.size()) {
1770 if (Name[0] != CoprocOp)
1787 if (Name[0] != CoprocOp || Name[1] != '1')
1791 case '0': return 10;
1792 case '1': return 11;
1793 case '2': return 12;
1794 case '3': return 13;
1795 case '4': return 14;
1796 case '5': return 15;
1804 /// parseITCondCode - Try to parse a condition code for an IT instruction.
1805 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1806 parseITCondCode(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1807 SMLoc S = Parser.getTok().getLoc();
1808 const AsmToken &Tok = Parser.getTok();
1809 if (!Tok.is(AsmToken::Identifier))
1810 return MatchOperand_NoMatch;
1811 unsigned CC = StringSwitch<unsigned>(Tok.getString())
1812 .Case("eq", ARMCC::EQ)
1813 .Case("ne", ARMCC::NE)
1814 .Case("hs", ARMCC::HS)
1815 .Case("cs", ARMCC::HS)
1816 .Case("lo", ARMCC::LO)
1817 .Case("cc", ARMCC::LO)
1818 .Case("mi", ARMCC::MI)
1819 .Case("pl", ARMCC::PL)
1820 .Case("vs", ARMCC::VS)
1821 .Case("vc", ARMCC::VC)
1822 .Case("hi", ARMCC::HI)
1823 .Case("ls", ARMCC::LS)
1824 .Case("ge", ARMCC::GE)
1825 .Case("lt", ARMCC::LT)
1826 .Case("gt", ARMCC::GT)
1827 .Case("le", ARMCC::LE)
1828 .Case("al", ARMCC::AL)
1831 return MatchOperand_NoMatch;
1832 Parser.Lex(); // Eat the token.
1834 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
1836 return MatchOperand_Success;
1839 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
1840 /// token must be an Identifier when called, and if it is a coprocessor
1841 /// number, the token is eaten and the operand is added to the operand list.
1842 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1843 parseCoprocNumOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1844 SMLoc S = Parser.getTok().getLoc();
1845 const AsmToken &Tok = Parser.getTok();
1846 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1848 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
1850 return MatchOperand_NoMatch;
1852 Parser.Lex(); // Eat identifier token.
1853 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
1854 return MatchOperand_Success;
1857 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
1858 /// token must be an Identifier when called, and if it is a coprocessor
1859 /// number, the token is eaten and the operand is added to the operand list.
1860 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1861 parseCoprocRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1862 SMLoc S = Parser.getTok().getLoc();
1863 const AsmToken &Tok = Parser.getTok();
1864 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1866 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
1868 return MatchOperand_NoMatch;
1870 Parser.Lex(); // Eat identifier token.
1871 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
1872 return MatchOperand_Success;
1875 // For register list parsing, we need to map from raw GPR register numbering
1876 // to the enumeration values. The enumeration values aren't sorted by
1877 // register number due to our using "sp", "lr" and "pc" as canonical names.
1878 static unsigned getNextRegister(unsigned Reg) {
1879 // If this is a GPR, we need to do it manually, otherwise we can rely
1880 // on the sort ordering of the enumeration since the other reg-classes
1882 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1885 default: assert(0 && "Invalid GPR number!");
1886 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
1887 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
1888 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
1889 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
1890 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
1891 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
1892 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
1893 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
1897 /// Parse a register list.
1899 parseRegisterList(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1900 assert(Parser.getTok().is(AsmToken::LCurly) &&
1901 "Token is not a Left Curly Brace");
1902 SMLoc S = Parser.getTok().getLoc();
1903 Parser.Lex(); // Eat '{' token.
1904 SMLoc RegLoc = Parser.getTok().getLoc();
1906 // Check the first register in the list to see what register class
1907 // this is a list of.
1908 int Reg = tryParseRegister();
1910 return Error(RegLoc, "register expected");
1912 MCRegisterClass *RC;
1913 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
1914 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
1915 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
1916 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
1917 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
1918 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
1920 return Error(RegLoc, "invalid register in register list");
1922 // The reglist instructions have at most 16 registers, so reserve
1923 // space for that many.
1924 SmallVector<std::pair<unsigned, SMLoc>, 16> Registers;
1925 // Store the first register.
1926 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1928 // This starts immediately after the first register token in the list,
1929 // so we can see either a comma or a minus (range separator) as a legal
1931 while (Parser.getTok().is(AsmToken::Comma) ||
1932 Parser.getTok().is(AsmToken::Minus)) {
1933 if (Parser.getTok().is(AsmToken::Minus)) {
1934 Parser.Lex(); // Eat the comma.
1935 SMLoc EndLoc = Parser.getTok().getLoc();
1936 int EndReg = tryParseRegister();
1938 return Error(EndLoc, "register expected");
1939 // If the register is the same as the start reg, there's nothing
1943 // The register must be in the same register class as the first.
1944 if (!RC->contains(EndReg))
1945 return Error(EndLoc, "invalid register in register list");
1946 // Ranges must go from low to high.
1947 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
1948 return Error(EndLoc, "bad range in register list");
1950 // Add all the registers in the range to the register list.
1951 while (Reg != EndReg) {
1952 Reg = getNextRegister(Reg);
1953 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1957 Parser.Lex(); // Eat the comma.
1958 RegLoc = Parser.getTok().getLoc();
1960 Reg = tryParseRegister();
1962 return Error(RegLoc, "register expected");
1963 // The register must be in the same register class as the first.
1964 if (!RC->contains(Reg))
1965 return Error(RegLoc, "invalid register in register list");
1966 // List must be monotonically increasing.
1967 if (getARMRegisterNumbering(Reg) <= getARMRegisterNumbering(OldReg))
1968 return Error(RegLoc, "register list not in ascending order");
1969 // VFP register lists must also be contiguous.
1970 // It's OK to use the enumeration values directly here rather, as the
1971 // VFP register classes have the enum sorted properly.
1972 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
1974 return Error(RegLoc, "non-contiguous register range");
1975 Registers.push_back(std::pair<unsigned, SMLoc>(Reg, RegLoc));
1978 SMLoc E = Parser.getTok().getLoc();
1979 if (Parser.getTok().isNot(AsmToken::RCurly))
1980 return Error(E, "'}' expected");
1981 Parser.Lex(); // Eat '}' token.
1983 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
1987 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
1988 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1989 parseMemBarrierOptOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1990 SMLoc S = Parser.getTok().getLoc();
1991 const AsmToken &Tok = Parser.getTok();
1992 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
1993 StringRef OptStr = Tok.getString();
1995 unsigned Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()))
1996 .Case("sy", ARM_MB::SY)
1997 .Case("st", ARM_MB::ST)
1998 .Case("sh", ARM_MB::ISH)
1999 .Case("ish", ARM_MB::ISH)
2000 .Case("shst", ARM_MB::ISHST)
2001 .Case("ishst", ARM_MB::ISHST)
2002 .Case("nsh", ARM_MB::NSH)
2003 .Case("un", ARM_MB::NSH)
2004 .Case("nshst", ARM_MB::NSHST)
2005 .Case("unst", ARM_MB::NSHST)
2006 .Case("osh", ARM_MB::OSH)
2007 .Case("oshst", ARM_MB::OSHST)
2011 return MatchOperand_NoMatch;
2013 Parser.Lex(); // Eat identifier token.
2014 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
2015 return MatchOperand_Success;
2018 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
2019 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2020 parseProcIFlagsOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2021 SMLoc S = Parser.getTok().getLoc();
2022 const AsmToken &Tok = Parser.getTok();
2023 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2024 StringRef IFlagsStr = Tok.getString();
2026 unsigned IFlags = 0;
2027 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
2028 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
2029 .Case("a", ARM_PROC::A)
2030 .Case("i", ARM_PROC::I)
2031 .Case("f", ARM_PROC::F)
2034 // If some specific iflag is already set, it means that some letter is
2035 // present more than once, this is not acceptable.
2036 if (Flag == ~0U || (IFlags & Flag))
2037 return MatchOperand_NoMatch;
2042 Parser.Lex(); // Eat identifier token.
2043 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
2044 return MatchOperand_Success;
2047 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
2048 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2049 parseMSRMaskOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2050 SMLoc S = Parser.getTok().getLoc();
2051 const AsmToken &Tok = Parser.getTok();
2052 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
2053 StringRef Mask = Tok.getString();
2055 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
2056 size_t Start = 0, Next = Mask.find('_');
2057 StringRef Flags = "";
2058 std::string SpecReg = LowercaseString(Mask.slice(Start, Next));
2059 if (Next != StringRef::npos)
2060 Flags = Mask.slice(Next+1, Mask.size());
2062 // FlagsVal contains the complete mask:
2064 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2065 unsigned FlagsVal = 0;
2067 if (SpecReg == "apsr") {
2068 FlagsVal = StringSwitch<unsigned>(Flags)
2069 .Case("nzcvq", 0x8) // same as CPSR_f
2070 .Case("g", 0x4) // same as CPSR_s
2071 .Case("nzcvqg", 0xc) // same as CPSR_fs
2074 if (FlagsVal == ~0U) {
2076 return MatchOperand_NoMatch;
2078 FlagsVal = 8; // No flag
2080 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
2081 if (Flags == "all") // cpsr_all is an alias for cpsr_fc
2083 for (int i = 0, e = Flags.size(); i != e; ++i) {
2084 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
2091 // If some specific flag is already set, it means that some letter is
2092 // present more than once, this is not acceptable.
2093 if (FlagsVal == ~0U || (FlagsVal & Flag))
2094 return MatchOperand_NoMatch;
2097 } else // No match for special register.
2098 return MatchOperand_NoMatch;
2100 // Special register without flags are equivalent to "fc" flags.
2104 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
2105 if (SpecReg == "spsr")
2108 Parser.Lex(); // Eat identifier token.
2109 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
2110 return MatchOperand_Success;
2113 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2114 parsePKHImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands, StringRef Op,
2115 int Low, int High) {
2116 const AsmToken &Tok = Parser.getTok();
2117 if (Tok.isNot(AsmToken::Identifier)) {
2118 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2119 return MatchOperand_ParseFail;
2121 StringRef ShiftName = Tok.getString();
2122 std::string LowerOp = LowercaseString(Op);
2123 std::string UpperOp = UppercaseString(Op);
2124 if (ShiftName != LowerOp && ShiftName != UpperOp) {
2125 Error(Parser.getTok().getLoc(), Op + " operand expected.");
2126 return MatchOperand_ParseFail;
2128 Parser.Lex(); // Eat shift type token.
2130 // There must be a '#' and a shift amount.
2131 if (Parser.getTok().isNot(AsmToken::Hash)) {
2132 Error(Parser.getTok().getLoc(), "'#' expected");
2133 return MatchOperand_ParseFail;
2135 Parser.Lex(); // Eat hash token.
2137 const MCExpr *ShiftAmount;
2138 SMLoc Loc = Parser.getTok().getLoc();
2139 if (getParser().ParseExpression(ShiftAmount)) {
2140 Error(Loc, "illegal expression");
2141 return MatchOperand_ParseFail;
2143 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2145 Error(Loc, "constant expression expected");
2146 return MatchOperand_ParseFail;
2148 int Val = CE->getValue();
2149 if (Val < Low || Val > High) {
2150 Error(Loc, "immediate value out of range");
2151 return MatchOperand_ParseFail;
2154 Operands.push_back(ARMOperand::CreateImm(CE, Loc, Parser.getTok().getLoc()));
2156 return MatchOperand_Success;
2159 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2160 parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2161 const AsmToken &Tok = Parser.getTok();
2162 SMLoc S = Tok.getLoc();
2163 if (Tok.isNot(AsmToken::Identifier)) {
2164 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2165 return MatchOperand_ParseFail;
2167 int Val = StringSwitch<int>(Tok.getString())
2171 Parser.Lex(); // Eat the token.
2174 Error(Tok.getLoc(), "'be' or 'le' operand expected");
2175 return MatchOperand_ParseFail;
2177 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
2179 S, Parser.getTok().getLoc()));
2180 return MatchOperand_Success;
2183 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
2184 /// instructions. Legal values are:
2185 /// lsl #n 'n' in [0,31]
2186 /// asr #n 'n' in [1,32]
2187 /// n == 32 encoded as n == 0.
2188 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2189 parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2190 const AsmToken &Tok = Parser.getTok();
2191 SMLoc S = Tok.getLoc();
2192 if (Tok.isNot(AsmToken::Identifier)) {
2193 Error(S, "shift operator 'asr' or 'lsl' expected");
2194 return MatchOperand_ParseFail;
2196 StringRef ShiftName = Tok.getString();
2198 if (ShiftName == "lsl" || ShiftName == "LSL")
2200 else if (ShiftName == "asr" || ShiftName == "ASR")
2203 Error(S, "shift operator 'asr' or 'lsl' expected");
2204 return MatchOperand_ParseFail;
2206 Parser.Lex(); // Eat the operator.
2208 // A '#' and a shift amount.
2209 if (Parser.getTok().isNot(AsmToken::Hash)) {
2210 Error(Parser.getTok().getLoc(), "'#' expected");
2211 return MatchOperand_ParseFail;
2213 Parser.Lex(); // Eat hash token.
2215 const MCExpr *ShiftAmount;
2216 SMLoc E = Parser.getTok().getLoc();
2217 if (getParser().ParseExpression(ShiftAmount)) {
2218 Error(E, "malformed shift expression");
2219 return MatchOperand_ParseFail;
2221 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2223 Error(E, "shift amount must be an immediate");
2224 return MatchOperand_ParseFail;
2227 int64_t Val = CE->getValue();
2229 // Shift amount must be in [1,32]
2230 if (Val < 1 || Val > 32) {
2231 Error(E, "'asr' shift amount must be in range [1,32]");
2232 return MatchOperand_ParseFail;
2234 // asr #32 encoded as asr #0.
2235 if (Val == 32) Val = 0;
2237 // Shift amount must be in [1,32]
2238 if (Val < 0 || Val > 31) {
2239 Error(E, "'lsr' shift amount must be in range [0,31]");
2240 return MatchOperand_ParseFail;
2244 E = Parser.getTok().getLoc();
2245 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, E));
2247 return MatchOperand_Success;
2250 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
2251 /// of instructions. Legal values are:
2252 /// ror #n 'n' in {0, 8, 16, 24}
2253 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2254 parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2255 const AsmToken &Tok = Parser.getTok();
2256 SMLoc S = Tok.getLoc();
2257 if (Tok.isNot(AsmToken::Identifier)) {
2258 Error(S, "rotate operator 'ror' expected");
2259 return MatchOperand_ParseFail;
2261 StringRef ShiftName = Tok.getString();
2262 if (ShiftName != "ror" && ShiftName != "ROR") {
2263 Error(S, "rotate operator 'ror' expected");
2264 return MatchOperand_ParseFail;
2266 Parser.Lex(); // Eat the operator.
2268 // A '#' and a rotate amount.
2269 if (Parser.getTok().isNot(AsmToken::Hash)) {
2270 Error(Parser.getTok().getLoc(), "'#' expected");
2271 return MatchOperand_ParseFail;
2273 Parser.Lex(); // Eat hash token.
2275 const MCExpr *ShiftAmount;
2276 SMLoc E = Parser.getTok().getLoc();
2277 if (getParser().ParseExpression(ShiftAmount)) {
2278 Error(E, "malformed rotate expression");
2279 return MatchOperand_ParseFail;
2281 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
2283 Error(E, "rotate amount must be an immediate");
2284 return MatchOperand_ParseFail;
2287 int64_t Val = CE->getValue();
2288 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
2289 // normally, zero is represented in asm by omitting the rotate operand
2291 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
2292 Error(E, "'ror' rotate amount must be 8, 16, or 24");
2293 return MatchOperand_ParseFail;
2296 E = Parser.getTok().getLoc();
2297 Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
2299 return MatchOperand_Success;
2302 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2303 parseBitfield(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2304 SMLoc S = Parser.getTok().getLoc();
2305 // The bitfield descriptor is really two operands, the LSB and the width.
2306 if (Parser.getTok().isNot(AsmToken::Hash)) {
2307 Error(Parser.getTok().getLoc(), "'#' expected");
2308 return MatchOperand_ParseFail;
2310 Parser.Lex(); // Eat hash token.
2312 const MCExpr *LSBExpr;
2313 SMLoc E = Parser.getTok().getLoc();
2314 if (getParser().ParseExpression(LSBExpr)) {
2315 Error(E, "malformed immediate expression");
2316 return MatchOperand_ParseFail;
2318 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
2320 Error(E, "'lsb' operand must be an immediate");
2321 return MatchOperand_ParseFail;
2324 int64_t LSB = CE->getValue();
2325 // The LSB must be in the range [0,31]
2326 if (LSB < 0 || LSB > 31) {
2327 Error(E, "'lsb' operand must be in the range [0,31]");
2328 return MatchOperand_ParseFail;
2330 E = Parser.getTok().getLoc();
2332 // Expect another immediate operand.
2333 if (Parser.getTok().isNot(AsmToken::Comma)) {
2334 Error(Parser.getTok().getLoc(), "too few operands");
2335 return MatchOperand_ParseFail;
2337 Parser.Lex(); // Eat hash token.
2338 if (Parser.getTok().isNot(AsmToken::Hash)) {
2339 Error(Parser.getTok().getLoc(), "'#' expected");
2340 return MatchOperand_ParseFail;
2342 Parser.Lex(); // Eat hash token.
2344 const MCExpr *WidthExpr;
2345 if (getParser().ParseExpression(WidthExpr)) {
2346 Error(E, "malformed immediate expression");
2347 return MatchOperand_ParseFail;
2349 CE = dyn_cast<MCConstantExpr>(WidthExpr);
2351 Error(E, "'width' operand must be an immediate");
2352 return MatchOperand_ParseFail;
2355 int64_t Width = CE->getValue();
2356 // The LSB must be in the range [1,32-lsb]
2357 if (Width < 1 || Width > 32 - LSB) {
2358 Error(E, "'width' operand must be in the range [1,32-lsb]");
2359 return MatchOperand_ParseFail;
2361 E = Parser.getTok().getLoc();
2363 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, E));
2365 return MatchOperand_Success;
2368 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2369 parsePostIdxReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2370 // Check for a post-index addressing register operand. Specifically:
2371 // postidx_reg := '+' register {, shift}
2372 // | '-' register {, shift}
2373 // | register {, shift}
2375 // This method must return MatchOperand_NoMatch without consuming any tokens
2376 // in the case where there is no match, as other alternatives take other
2378 AsmToken Tok = Parser.getTok();
2379 SMLoc S = Tok.getLoc();
2380 bool haveEaten = false;
2383 if (Tok.is(AsmToken::Plus)) {
2384 Parser.Lex(); // Eat the '+' token.
2386 } else if (Tok.is(AsmToken::Minus)) {
2387 Parser.Lex(); // Eat the '-' token.
2391 if (Parser.getTok().is(AsmToken::Identifier))
2392 Reg = tryParseRegister();
2395 return MatchOperand_NoMatch;
2396 Error(Parser.getTok().getLoc(), "register expected");
2397 return MatchOperand_ParseFail;
2399 SMLoc E = Parser.getTok().getLoc();
2401 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
2402 unsigned ShiftImm = 0;
2403 if (Parser.getTok().is(AsmToken::Comma)) {
2404 Parser.Lex(); // Eat the ','.
2405 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
2406 return MatchOperand_ParseFail;
2409 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
2412 return MatchOperand_Success;
2415 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
2416 parseAM3Offset(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2417 // Check for a post-index addressing register operand. Specifically:
2418 // am3offset := '+' register
2425 // This method must return MatchOperand_NoMatch without consuming any tokens
2426 // in the case where there is no match, as other alternatives take other
2428 AsmToken Tok = Parser.getTok();
2429 SMLoc S = Tok.getLoc();
2431 // Do immediates first, as we always parse those if we have a '#'.
2432 if (Parser.getTok().is(AsmToken::Hash)) {
2433 Parser.Lex(); // Eat the '#'.
2434 // Explicitly look for a '-', as we need to encode negative zero
2436 bool isNegative = Parser.getTok().is(AsmToken::Minus);
2437 const MCExpr *Offset;
2438 if (getParser().ParseExpression(Offset))
2439 return MatchOperand_ParseFail;
2440 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2442 Error(S, "constant expression expected");
2443 return MatchOperand_ParseFail;
2445 SMLoc E = Tok.getLoc();
2446 // Negative zero is encoded as the flag value INT32_MIN.
2447 int32_t Val = CE->getValue();
2448 if (isNegative && Val == 0)
2452 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
2454 return MatchOperand_Success;
2458 bool haveEaten = false;
2461 if (Tok.is(AsmToken::Plus)) {
2462 Parser.Lex(); // Eat the '+' token.
2464 } else if (Tok.is(AsmToken::Minus)) {
2465 Parser.Lex(); // Eat the '-' token.
2469 if (Parser.getTok().is(AsmToken::Identifier))
2470 Reg = tryParseRegister();
2473 return MatchOperand_NoMatch;
2474 Error(Parser.getTok().getLoc(), "register expected");
2475 return MatchOperand_ParseFail;
2477 SMLoc E = Parser.getTok().getLoc();
2479 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
2482 return MatchOperand_Success;
2485 /// cvtT2LdrdPre - Convert parsed operands to MCInst.
2486 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2487 /// when they refer multiple MIOperands inside a single one.
2489 cvtT2LdrdPre(MCInst &Inst, unsigned Opcode,
2490 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2492 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2493 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2494 // Create a writeback register dummy placeholder.
2495 Inst.addOperand(MCOperand::CreateReg(0));
2497 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2499 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2503 /// cvtT2StrdPre - Convert parsed operands to MCInst.
2504 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2505 /// when they refer multiple MIOperands inside a single one.
2507 cvtT2StrdPre(MCInst &Inst, unsigned Opcode,
2508 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2509 // Create a writeback register dummy placeholder.
2510 Inst.addOperand(MCOperand::CreateReg(0));
2512 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2513 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2515 ((ARMOperand*)Operands[4])->addMemImm8s4OffsetOperands(Inst, 2);
2517 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2521 /// cvtLdWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2522 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2523 /// when they refer multiple MIOperands inside a single one.
2525 cvtLdWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2526 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2527 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2529 // Create a writeback register dummy placeholder.
2530 Inst.addOperand(MCOperand::CreateImm(0));
2532 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2533 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2537 /// cvtStWriteBackRegT2AddrModeImm8 - Convert parsed operands to MCInst.
2538 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2539 /// when they refer multiple MIOperands inside a single one.
2541 cvtStWriteBackRegT2AddrModeImm8(MCInst &Inst, unsigned Opcode,
2542 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2543 // Create a writeback register dummy placeholder.
2544 Inst.addOperand(MCOperand::CreateImm(0));
2545 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2546 ((ARMOperand*)Operands[3])->addMemImm8OffsetOperands(Inst, 2);
2547 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2551 /// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2552 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2553 /// when they refer multiple MIOperands inside a single one.
2555 cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2556 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2557 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2559 // Create a writeback register dummy placeholder.
2560 Inst.addOperand(MCOperand::CreateImm(0));
2562 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2563 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2567 /// cvtLdWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2568 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2569 /// when they refer multiple MIOperands inside a single one.
2571 cvtLdWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2572 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2573 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2575 // Create a writeback register dummy placeholder.
2576 Inst.addOperand(MCOperand::CreateImm(0));
2578 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2579 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2584 /// cvtStWriteBackRegAddrModeImm12 - Convert parsed operands to MCInst.
2585 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2586 /// when they refer multiple MIOperands inside a single one.
2588 cvtStWriteBackRegAddrModeImm12(MCInst &Inst, unsigned Opcode,
2589 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2590 // Create a writeback register dummy placeholder.
2591 Inst.addOperand(MCOperand::CreateImm(0));
2592 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2593 ((ARMOperand*)Operands[3])->addMemImm12OffsetOperands(Inst, 2);
2594 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2598 /// cvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
2599 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2600 /// when they refer multiple MIOperands inside a single one.
2602 cvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
2603 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2604 // Create a writeback register dummy placeholder.
2605 Inst.addOperand(MCOperand::CreateImm(0));
2606 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2607 ((ARMOperand*)Operands[3])->addAddrMode2Operands(Inst, 3);
2608 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2612 /// cvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2613 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2614 /// when they refer multiple MIOperands inside a single one.
2616 cvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2617 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2618 // Create a writeback register dummy placeholder.
2619 Inst.addOperand(MCOperand::CreateImm(0));
2620 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2621 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2622 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2626 /// cvtLdExtTWriteBackImm - Convert parsed operands to MCInst.
2627 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2628 /// when they refer multiple MIOperands inside a single one.
2630 cvtLdExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2631 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2633 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2634 // Create a writeback register dummy placeholder.
2635 Inst.addOperand(MCOperand::CreateImm(0));
2637 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2639 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2641 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2645 /// cvtLdExtTWriteBackReg - Convert parsed operands to MCInst.
2646 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2647 /// when they refer multiple MIOperands inside a single one.
2649 cvtLdExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2650 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2652 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2653 // Create a writeback register dummy placeholder.
2654 Inst.addOperand(MCOperand::CreateImm(0));
2656 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2658 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2660 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2664 /// cvtStExtTWriteBackImm - Convert parsed operands to MCInst.
2665 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2666 /// when they refer multiple MIOperands inside a single one.
2668 cvtStExtTWriteBackImm(MCInst &Inst, unsigned Opcode,
2669 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2670 // Create a writeback register dummy placeholder.
2671 Inst.addOperand(MCOperand::CreateImm(0));
2673 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2675 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2677 ((ARMOperand*)Operands[4])->addPostIdxImm8Operands(Inst, 1);
2679 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2683 /// cvtStExtTWriteBackReg - Convert parsed operands to MCInst.
2684 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2685 /// when they refer multiple MIOperands inside a single one.
2687 cvtStExtTWriteBackReg(MCInst &Inst, unsigned Opcode,
2688 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2689 // Create a writeback register dummy placeholder.
2690 Inst.addOperand(MCOperand::CreateImm(0));
2692 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2694 ((ARMOperand*)Operands[3])->addMemNoOffsetOperands(Inst, 1);
2696 ((ARMOperand*)Operands[4])->addPostIdxRegOperands(Inst, 2);
2698 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2702 /// cvtLdrdPre - Convert parsed operands to MCInst.
2703 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2704 /// when they refer multiple MIOperands inside a single one.
2706 cvtLdrdPre(MCInst &Inst, unsigned Opcode,
2707 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2709 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2710 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2711 // Create a writeback register dummy placeholder.
2712 Inst.addOperand(MCOperand::CreateImm(0));
2714 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2716 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2720 /// cvtStrdPre - Convert parsed operands to MCInst.
2721 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2722 /// when they refer multiple MIOperands inside a single one.
2724 cvtStrdPre(MCInst &Inst, unsigned Opcode,
2725 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2726 // Create a writeback register dummy placeholder.
2727 Inst.addOperand(MCOperand::CreateImm(0));
2729 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2730 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2732 ((ARMOperand*)Operands[4])->addAddrMode3Operands(Inst, 3);
2734 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2738 /// cvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
2739 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2740 /// when they refer multiple MIOperands inside a single one.
2742 cvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
2743 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2744 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
2745 // Create a writeback register dummy placeholder.
2746 Inst.addOperand(MCOperand::CreateImm(0));
2747 ((ARMOperand*)Operands[3])->addAddrMode3Operands(Inst, 3);
2748 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
2752 /// cvtThumbMultiple- Convert parsed operands to MCInst.
2753 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
2754 /// when they refer multiple MIOperands inside a single one.
2756 cvtThumbMultiply(MCInst &Inst, unsigned Opcode,
2757 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2758 // The second source operand must be the same register as the destination
2760 if (Operands.size() == 6 &&
2761 (((ARMOperand*)Operands[3])->getReg() !=
2762 ((ARMOperand*)Operands[5])->getReg()) &&
2763 (((ARMOperand*)Operands[3])->getReg() !=
2764 ((ARMOperand*)Operands[4])->getReg())) {
2765 Error(Operands[3]->getStartLoc(),
2766 "destination register must match source register");
2769 ((ARMOperand*)Operands[3])->addRegOperands(Inst, 1);
2770 ((ARMOperand*)Operands[1])->addCCOutOperands(Inst, 1);
2771 ((ARMOperand*)Operands[4])->addRegOperands(Inst, 1);
2772 // If we have a three-operand form, use that, else the second source operand
2773 // is just the destination operand again.
2774 if (Operands.size() == 6)
2775 ((ARMOperand*)Operands[5])->addRegOperands(Inst, 1);
2777 Inst.addOperand(Inst.getOperand(0));
2778 ((ARMOperand*)Operands[2])->addCondCodeOperands(Inst, 2);
2783 /// Parse an ARM memory expression, return false if successful else return true
2784 /// or an error. The first token must be a '[' when called.
2786 parseMemory(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
2788 assert(Parser.getTok().is(AsmToken::LBrac) &&
2789 "Token is not a Left Bracket");
2790 S = Parser.getTok().getLoc();
2791 Parser.Lex(); // Eat left bracket token.
2793 const AsmToken &BaseRegTok = Parser.getTok();
2794 int BaseRegNum = tryParseRegister();
2795 if (BaseRegNum == -1)
2796 return Error(BaseRegTok.getLoc(), "register expected");
2798 // The next token must either be a comma or a closing bracket.
2799 const AsmToken &Tok = Parser.getTok();
2800 if (!Tok.is(AsmToken::Comma) && !Tok.is(AsmToken::RBrac))
2801 return Error(Tok.getLoc(), "malformed memory operand");
2803 if (Tok.is(AsmToken::RBrac)) {
2805 Parser.Lex(); // Eat right bracket token.
2807 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, 0, ARM_AM::no_shift,
2810 // If there's a pre-indexing writeback marker, '!', just add it as a token
2811 // operand. It's rather odd, but syntactically valid.
2812 if (Parser.getTok().is(AsmToken::Exclaim)) {
2813 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2814 Parser.Lex(); // Eat the '!'.
2820 assert(Tok.is(AsmToken::Comma) && "Lost comma in memory operand?!");
2821 Parser.Lex(); // Eat the comma.
2823 // If we have a '#' it's an immediate offset, else assume it's a register
2825 if (Parser.getTok().is(AsmToken::Hash)) {
2826 Parser.Lex(); // Eat the '#'.
2827 E = Parser.getTok().getLoc();
2829 bool isNegative = getParser().getTok().is(AsmToken::Minus);
2830 const MCExpr *Offset;
2831 if (getParser().ParseExpression(Offset))
2834 // The expression has to be a constant. Memory references with relocations
2835 // don't come through here, as they use the <label> forms of the relevant
2837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
2839 return Error (E, "constant expression expected");
2841 // If the constant was #-0, represent it as INT32_MIN.
2842 int32_t Val = CE->getValue();
2843 if (isNegative && Val == 0)
2844 CE = MCConstantExpr::Create(INT32_MIN, getContext());
2846 // Now we should have the closing ']'
2847 E = Parser.getTok().getLoc();
2848 if (Parser.getTok().isNot(AsmToken::RBrac))
2849 return Error(E, "']' expected");
2850 Parser.Lex(); // Eat right bracket token.
2852 // Don't worry about range checking the value here. That's handled by
2853 // the is*() predicates.
2854 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
2855 ARM_AM::no_shift, 0, false, S,E));
2857 // If there's a pre-indexing writeback marker, '!', just add it as a token
2859 if (Parser.getTok().is(AsmToken::Exclaim)) {
2860 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2861 Parser.Lex(); // Eat the '!'.
2867 // The register offset is optionally preceded by a '+' or '-'
2868 bool isNegative = false;
2869 if (Parser.getTok().is(AsmToken::Minus)) {
2871 Parser.Lex(); // Eat the '-'.
2872 } else if (Parser.getTok().is(AsmToken::Plus)) {
2874 Parser.Lex(); // Eat the '+'.
2877 E = Parser.getTok().getLoc();
2878 int OffsetRegNum = tryParseRegister();
2879 if (OffsetRegNum == -1)
2880 return Error(E, "register expected");
2882 // If there's a shift operator, handle it.
2883 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
2884 unsigned ShiftImm = 0;
2885 if (Parser.getTok().is(AsmToken::Comma)) {
2886 Parser.Lex(); // Eat the ','.
2887 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
2891 // Now we should have the closing ']'
2892 E = Parser.getTok().getLoc();
2893 if (Parser.getTok().isNot(AsmToken::RBrac))
2894 return Error(E, "']' expected");
2895 Parser.Lex(); // Eat right bracket token.
2897 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, 0, OffsetRegNum,
2898 ShiftType, ShiftImm, isNegative,
2901 // If there's a pre-indexing writeback marker, '!', just add it as a token
2903 if (Parser.getTok().is(AsmToken::Exclaim)) {
2904 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
2905 Parser.Lex(); // Eat the '!'.
2911 /// parseMemRegOffsetShift - one of these two:
2912 /// ( lsl | lsr | asr | ror ) , # shift_amount
2914 /// return true if it parses a shift otherwise it returns false.
2915 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
2917 SMLoc Loc = Parser.getTok().getLoc();
2918 const AsmToken &Tok = Parser.getTok();
2919 if (Tok.isNot(AsmToken::Identifier))
2921 StringRef ShiftName = Tok.getString();
2922 if (ShiftName == "lsl" || ShiftName == "LSL")
2924 else if (ShiftName == "lsr" || ShiftName == "LSR")
2926 else if (ShiftName == "asr" || ShiftName == "ASR")
2928 else if (ShiftName == "ror" || ShiftName == "ROR")
2930 else if (ShiftName == "rrx" || ShiftName == "RRX")
2933 return Error(Loc, "illegal shift operator");
2934 Parser.Lex(); // Eat shift type token.
2936 // rrx stands alone.
2938 if (St != ARM_AM::rrx) {
2939 Loc = Parser.getTok().getLoc();
2940 // A '#' and a shift amount.
2941 const AsmToken &HashTok = Parser.getTok();
2942 if (HashTok.isNot(AsmToken::Hash))
2943 return Error(HashTok.getLoc(), "'#' expected");
2944 Parser.Lex(); // Eat hash token.
2947 if (getParser().ParseExpression(Expr))
2949 // Range check the immediate.
2950 // lsl, ror: 0 <= imm <= 31
2951 // lsr, asr: 0 <= imm <= 32
2952 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
2954 return Error(Loc, "shift amount must be an immediate");
2955 int64_t Imm = CE->getValue();
2957 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
2958 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
2959 return Error(Loc, "immediate shift value out of range");
2966 /// Parse a arm instruction operand. For now this parses the operand regardless
2967 /// of the mnemonic.
2968 bool ARMAsmParser::parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
2969 StringRef Mnemonic) {
2972 // Check if the current operand has a custom associated parser, if so, try to
2973 // custom parse the operand, or fallback to the general approach.
2974 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
2975 if (ResTy == MatchOperand_Success)
2977 // If there wasn't a custom match, try the generic matcher below. Otherwise,
2978 // there was a match, but an error occurred, in which case, just return that
2979 // the operand parsing failed.
2980 if (ResTy == MatchOperand_ParseFail)
2983 switch (getLexer().getKind()) {
2985 Error(Parser.getTok().getLoc(), "unexpected token in operand");
2987 case AsmToken::Identifier: {
2988 if (!tryParseRegisterWithWriteBack(Operands))
2990 int Res = tryParseShiftRegister(Operands);
2991 if (Res == 0) // success
2993 else if (Res == -1) // irrecoverable error
2996 // Fall though for the Identifier case that is not a register or a
2999 case AsmToken::Integer: // things like 1f and 2b as a branch targets
3000 case AsmToken::Dot: { // . as a branch target
3001 // This was not a register so parse other operands that start with an
3002 // identifier (like labels) as expressions and create them as immediates.
3003 const MCExpr *IdVal;
3004 S = Parser.getTok().getLoc();
3005 if (getParser().ParseExpression(IdVal))
3007 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3008 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
3011 case AsmToken::LBrac:
3012 return parseMemory(Operands);
3013 case AsmToken::LCurly:
3014 return parseRegisterList(Operands);
3015 case AsmToken::Hash: {
3016 // #42 -> immediate.
3017 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
3018 S = Parser.getTok().getLoc();
3020 bool isNegative = Parser.getTok().is(AsmToken::Minus);
3021 const MCExpr *ImmVal;
3022 if (getParser().ParseExpression(ImmVal))
3024 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
3026 Error(S, "constant expression expected");
3027 return MatchOperand_ParseFail;
3029 int32_t Val = CE->getValue();
3030 if (isNegative && Val == 0)
3031 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
3032 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3033 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
3036 case AsmToken::Colon: {
3037 // ":lower16:" and ":upper16:" expression prefixes
3038 // FIXME: Check it's an expression prefix,
3039 // e.g. (FOO - :lower16:BAR) isn't legal.
3040 ARMMCExpr::VariantKind RefKind;
3041 if (parsePrefix(RefKind))
3044 const MCExpr *SubExprVal;
3045 if (getParser().ParseExpression(SubExprVal))
3048 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
3050 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
3051 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
3057 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
3058 // :lower16: and :upper16:.
3059 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
3060 RefKind = ARMMCExpr::VK_ARM_None;
3062 // :lower16: and :upper16: modifiers
3063 assert(getLexer().is(AsmToken::Colon) && "expected a :");
3064 Parser.Lex(); // Eat ':'
3066 if (getLexer().isNot(AsmToken::Identifier)) {
3067 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
3071 StringRef IDVal = Parser.getTok().getIdentifier();
3072 if (IDVal == "lower16") {
3073 RefKind = ARMMCExpr::VK_ARM_LO16;
3074 } else if (IDVal == "upper16") {
3075 RefKind = ARMMCExpr::VK_ARM_HI16;
3077 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
3082 if (getLexer().isNot(AsmToken::Colon)) {
3083 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
3086 Parser.Lex(); // Eat the last ':'
3090 /// \brief Given a mnemonic, split out possible predication code and carry
3091 /// setting letters to form a canonical mnemonic and flags.
3093 // FIXME: Would be nice to autogen this.
3094 // FIXME: This is a bit of a maze of special cases.
3095 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
3096 unsigned &PredicationCode,
3098 unsigned &ProcessorIMod,
3099 StringRef &ITMask) {
3100 PredicationCode = ARMCC::AL;
3101 CarrySetting = false;
3104 // Ignore some mnemonics we know aren't predicated forms.
3106 // FIXME: Would be nice to autogen this.
3107 if ((Mnemonic == "movs" && isThumb()) ||
3108 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
3109 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
3110 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
3111 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
3112 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
3113 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
3114 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")
3117 // First, split out any predication code. Ignore mnemonics we know aren't
3118 // predicated but do have a carry-set and so weren't caught above.
3119 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
3120 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
3121 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
3122 Mnemonic != "sbcs" && Mnemonic != "rscs") {
3123 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
3124 .Case("eq", ARMCC::EQ)
3125 .Case("ne", ARMCC::NE)
3126 .Case("hs", ARMCC::HS)
3127 .Case("cs", ARMCC::HS)
3128 .Case("lo", ARMCC::LO)
3129 .Case("cc", ARMCC::LO)
3130 .Case("mi", ARMCC::MI)
3131 .Case("pl", ARMCC::PL)
3132 .Case("vs", ARMCC::VS)
3133 .Case("vc", ARMCC::VC)
3134 .Case("hi", ARMCC::HI)
3135 .Case("ls", ARMCC::LS)
3136 .Case("ge", ARMCC::GE)
3137 .Case("lt", ARMCC::LT)
3138 .Case("gt", ARMCC::GT)
3139 .Case("le", ARMCC::LE)
3140 .Case("al", ARMCC::AL)
3143 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
3144 PredicationCode = CC;
3148 // Next, determine if we have a carry setting bit. We explicitly ignore all
3149 // the instructions we know end in 's'.
3150 if (Mnemonic.endswith("s") &&
3151 !(Mnemonic == "cps" || Mnemonic == "mls" ||
3152 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
3153 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
3154 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
3155 Mnemonic == "vrsqrts" || Mnemonic == "srs" ||
3156 (Mnemonic == "movs" && isThumb()))) {
3157 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
3158 CarrySetting = true;
3161 // The "cps" instruction can have a interrupt mode operand which is glued into
3162 // the mnemonic. Check if this is the case, split it and parse the imod op
3163 if (Mnemonic.startswith("cps")) {
3164 // Split out any imod code.
3166 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
3167 .Case("ie", ARM_PROC::IE)
3168 .Case("id", ARM_PROC::ID)
3171 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
3172 ProcessorIMod = IMod;
3176 // The "it" instruction has the condition mask on the end of the mnemonic.
3177 if (Mnemonic.startswith("it")) {
3178 ITMask = Mnemonic.slice(2, Mnemonic.size());
3179 Mnemonic = Mnemonic.slice(0, 2);
3185 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
3186 /// inclusion of carry set or predication code operands.
3188 // FIXME: It would be nice to autogen this.
3190 getMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet,
3191 bool &CanAcceptPredicationCode) {
3192 if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
3193 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
3194 Mnemonic == "add" || Mnemonic == "adc" ||
3195 Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" ||
3196 Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mvn" ||
3197 Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" ||
3198 Mnemonic == "sbc" || Mnemonic == "umull" || Mnemonic == "eor" ||
3199 Mnemonic == "neg" ||
3200 (!isThumb() && (Mnemonic == "smull" || Mnemonic == "mov" ||
3201 Mnemonic == "mla" || Mnemonic == "smlal"))) {
3202 CanAcceptCarrySet = true;
3204 CanAcceptCarrySet = false;
3206 if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" ||
3207 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
3208 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
3209 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
3210 Mnemonic == "dsb" || Mnemonic == "isb" || Mnemonic == "setend" ||
3211 (Mnemonic == "clrex" && !isThumb()) ||
3212 (Mnemonic == "nop" && isThumbOne()) ||
3213 ((Mnemonic == "pld" || Mnemonic == "pli" || Mnemonic == "pldw") &&
3215 ((Mnemonic.startswith("rfe") || Mnemonic.startswith("srs")) &&
3217 Mnemonic.startswith("cps") || (Mnemonic == "movs" && isThumbOne())) {
3218 CanAcceptPredicationCode = false;
3220 CanAcceptPredicationCode = true;
3223 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
3224 Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
3225 CanAcceptPredicationCode = false;
3229 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
3230 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3231 // FIXME: This is all horribly hacky. We really need a better way to deal
3232 // with optional operands like this in the matcher table.
3234 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
3235 // another does not. Specifically, the MOVW instruction does not. So we
3236 // special case it here and remove the defaulted (non-setting) cc_out
3237 // operand if that's the instruction we're trying to match.
3239 // We do this as post-processing of the explicit operands rather than just
3240 // conditionally adding the cc_out in the first place because we need
3241 // to check the type of the parsed immediate operand.
3242 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
3243 !static_cast<ARMOperand*>(Operands[4])->isARMSOImm() &&
3244 static_cast<ARMOperand*>(Operands[4])->isImm0_65535Expr() &&
3245 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3248 // Register-register 'add' for thumb does not have a cc_out operand
3249 // when there are only two register operands.
3250 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
3251 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3252 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3253 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3255 // Register-register 'add' for thumb does not have a cc_out operand
3256 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
3257 // have to check the immediate range here since Thumb2 has a variant
3258 // that can handle a different range and has a cc_out operand.
3259 if (((isThumb() && Mnemonic == "add") ||
3260 (isThumbTwo() && Mnemonic == "sub")) &&
3261 Operands.size() == 6 &&
3262 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3263 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3264 static_cast<ARMOperand*>(Operands[4])->getReg() == ARM::SP &&
3265 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3266 (static_cast<ARMOperand*>(Operands[5])->isReg() ||
3267 static_cast<ARMOperand*>(Operands[5])->isImm0_1020s4()))
3269 // For Thumb2, add/sub immediate does not have a cc_out operand for the
3270 // imm0_4095 variant. That's the least-preferred variant when
3271 // selecting via the generic "add" mnemonic, so to know that we
3272 // should remove the cc_out operand, we have to explicitly check that
3273 // it's not one of the other variants. Ugh.
3274 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
3275 Operands.size() == 6 &&
3276 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3277 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3278 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3279 // Nest conditions rather than one big 'if' statement for readability.
3281 // If either register is a high reg, it's either one of the SP
3282 // variants (handled above) or a 32-bit encoding, so we just
3283 // check against T3.
3284 if ((!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3285 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg())) &&
3286 static_cast<ARMOperand*>(Operands[5])->isT2SOImm())
3288 // If both registers are low, we're in an IT block, and the immediate is
3289 // in range, we should use encoding T1 instead, which has a cc_out.
3291 isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) &&
3292 isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) &&
3293 static_cast<ARMOperand*>(Operands[5])->isImm0_7())
3296 // Otherwise, we use encoding T4, which does not have a cc_out
3301 // The thumb2 multiply instruction doesn't have a CCOut register, so
3302 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
3303 // use the 16-bit encoding or not.
3304 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
3305 static_cast<ARMOperand*>(Operands[1])->getReg() == 0 &&
3306 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3307 static_cast<ARMOperand*>(Operands[4])->isReg() &&
3308 static_cast<ARMOperand*>(Operands[5])->isReg() &&
3309 // If the registers aren't low regs, the destination reg isn't the
3310 // same as one of the source regs, or the cc_out operand is zero
3311 // outside of an IT block, we have to use the 32-bit encoding, so
3312 // remove the cc_out operand.
3313 (!isARMLowRegister(static_cast<ARMOperand*>(Operands[3])->getReg()) ||
3314 !isARMLowRegister(static_cast<ARMOperand*>(Operands[4])->getReg()) ||
3316 (static_cast<ARMOperand*>(Operands[3])->getReg() !=
3317 static_cast<ARMOperand*>(Operands[5])->getReg() &&
3318 static_cast<ARMOperand*>(Operands[3])->getReg() !=
3319 static_cast<ARMOperand*>(Operands[4])->getReg())))
3324 // Register-register 'add/sub' for thumb does not have a cc_out operand
3325 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
3326 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
3327 // right, this will result in better diagnostics (which operand is off)
3329 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
3330 (Operands.size() == 5 || Operands.size() == 6) &&
3331 static_cast<ARMOperand*>(Operands[3])->isReg() &&
3332 static_cast<ARMOperand*>(Operands[3])->getReg() == ARM::SP &&
3333 static_cast<ARMOperand*>(Operands[1])->getReg() == 0)
3339 /// Parse an arm instruction mnemonic followed by its operands.
3340 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
3341 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3342 // Create the leading tokens for the mnemonic, split by '.' characters.
3343 size_t Start = 0, Next = Name.find('.');
3344 StringRef Mnemonic = Name.slice(Start, Next);
3346 // Split out the predication code and carry setting flag from the mnemonic.
3347 unsigned PredicationCode;
3348 unsigned ProcessorIMod;
3351 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
3352 ProcessorIMod, ITMask);
3354 // In Thumb1, only the branch (B) instruction can be predicated.
3355 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
3356 Parser.EatToEndOfStatement();
3357 return Error(NameLoc, "conditional execution not supported in Thumb1");
3360 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
3362 // Handle the IT instruction ITMask. Convert it to a bitmask. This
3363 // is the mask as it will be for the IT encoding if the conditional
3364 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
3365 // where the conditional bit0 is zero, the instruction post-processing
3366 // will adjust the mask accordingly.
3367 if (Mnemonic == "it") {
3368 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
3369 if (ITMask.size() > 3) {
3370 Parser.EatToEndOfStatement();
3371 return Error(Loc, "too many conditions on IT instruction");
3374 for (unsigned i = ITMask.size(); i != 0; --i) {
3375 char pos = ITMask[i - 1];
3376 if (pos != 't' && pos != 'e') {
3377 Parser.EatToEndOfStatement();
3378 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
3381 if (ITMask[i - 1] == 't')
3384 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
3387 // FIXME: This is all a pretty gross hack. We should automatically handle
3388 // optional operands like this via tblgen.
3390 // Next, add the CCOut and ConditionCode operands, if needed.
3392 // For mnemonics which can ever incorporate a carry setting bit or predication
3393 // code, our matching model involves us always generating CCOut and
3394 // ConditionCode operands to match the mnemonic "as written" and then we let
3395 // the matcher deal with finding the right instruction or generating an
3396 // appropriate error.
3397 bool CanAcceptCarrySet, CanAcceptPredicationCode;
3398 getMnemonicAcceptInfo(Mnemonic, CanAcceptCarrySet, CanAcceptPredicationCode);
3400 // If we had a carry-set on an instruction that can't do that, issue an
3402 if (!CanAcceptCarrySet && CarrySetting) {
3403 Parser.EatToEndOfStatement();
3404 return Error(NameLoc, "instruction '" + Mnemonic +
3405 "' can not set flags, but 's' suffix specified");
3407 // If we had a predication code on an instruction that can't do that, issue an
3409 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
3410 Parser.EatToEndOfStatement();
3411 return Error(NameLoc, "instruction '" + Mnemonic +
3412 "' is not predicable, but condition code specified");
3415 // Add the carry setting operand, if necessary.
3416 if (CanAcceptCarrySet) {
3417 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
3418 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
3422 // Add the predication code operand, if necessary.
3423 if (CanAcceptPredicationCode) {
3424 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
3426 Operands.push_back(ARMOperand::CreateCondCode(
3427 ARMCC::CondCodes(PredicationCode), Loc));
3430 // Add the processor imod operand, if necessary.
3431 if (ProcessorIMod) {
3432 Operands.push_back(ARMOperand::CreateImm(
3433 MCConstantExpr::Create(ProcessorIMod, getContext()),
3437 // Add the remaining tokens in the mnemonic.
3438 while (Next != StringRef::npos) {
3440 Next = Name.find('.', Start + 1);
3441 StringRef ExtraToken = Name.slice(Start, Next);
3443 // For now, we're only parsing Thumb1 (for the most part), so
3444 // just ignore ".n" qualifiers. We'll use them to restrict
3445 // matching when we do Thumb2.
3446 if (ExtraToken != ".n") {
3447 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
3448 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
3452 // Read the remaining operands.
3453 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3454 // Read the first operand.
3455 if (parseOperand(Operands, Mnemonic)) {
3456 Parser.EatToEndOfStatement();
3460 while (getLexer().is(AsmToken::Comma)) {
3461 Parser.Lex(); // Eat the comma.
3463 // Parse and remember the operand.
3464 if (parseOperand(Operands, Mnemonic)) {
3465 Parser.EatToEndOfStatement();
3471 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3472 Parser.EatToEndOfStatement();
3473 return TokError("unexpected token in argument list");
3476 Parser.Lex(); // Consume the EndOfStatement
3478 // Some instructions, mostly Thumb, have forms for the same mnemonic that
3479 // do and don't have a cc_out optional-def operand. With some spot-checks
3480 // of the operand list, we can figure out which variant we're trying to
3481 // parse and adjust accordingly before actually matching. We shouldn't ever
3482 // try to remove a cc_out operand that was explicitly set on the the
3483 // mnemonic, of course (CarrySetting == true). Reason number #317 the
3484 // table driven matcher doesn't fit well with the ARM instruction set.
3485 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands)) {
3486 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3487 Operands.erase(Operands.begin() + 1);
3491 // ARM mode 'blx' need special handling, as the register operand version
3492 // is predicable, but the label operand version is not. So, we can't rely
3493 // on the Mnemonic based checking to correctly figure out when to put
3494 // a CondCode operand in the list. If we're trying to match the label
3495 // version, remove the CondCode operand here.
3496 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
3497 static_cast<ARMOperand*>(Operands[2])->isImm()) {
3498 ARMOperand *Op = static_cast<ARMOperand*>(Operands[1]);
3499 Operands.erase(Operands.begin() + 1);
3503 // The vector-compare-to-zero instructions have a literal token "#0" at
3504 // the end that comes to here as an immediate operand. Convert it to a
3505 // token to play nicely with the matcher.
3506 if ((Mnemonic == "vceq" || Mnemonic == "vcge" || Mnemonic == "vcgt" ||
3507 Mnemonic == "vcle" || Mnemonic == "vclt") && Operands.size() == 6 &&
3508 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3509 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3510 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3511 if (CE && CE->getValue() == 0) {
3512 Operands.erase(Operands.begin() + 5);
3513 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3517 // Similarly, the Thumb1 "RSB" instruction has a literal "#0" on the
3518 // end. Convert it to a token here.
3519 if (Mnemonic == "rsb" && isThumb() && Operands.size() == 6 &&
3520 static_cast<ARMOperand*>(Operands[5])->isImm()) {
3521 ARMOperand *Op = static_cast<ARMOperand*>(Operands[5]);
3522 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op->getImm());
3523 if (CE && CE->getValue() == 0) {
3524 Operands.erase(Operands.begin() + 5);
3525 Operands.push_back(ARMOperand::CreateToken("#0", Op->getStartLoc()));
3533 // Validate context-sensitive operand constraints.
3535 // return 'true' if register list contains non-low GPR registers,
3536 // 'false' otherwise. If Reg is in the register list or is HiReg, set
3537 // 'containsReg' to true.
3538 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
3539 unsigned HiReg, bool &containsReg) {
3540 containsReg = false;
3541 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3542 unsigned OpReg = Inst.getOperand(i).getReg();
3545 // Anything other than a low register isn't legal here.
3546 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
3552 // Check if the specified regisgter is in the register list of the inst,
3553 // starting at the indicated operand number.
3554 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
3555 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
3556 unsigned OpReg = Inst.getOperand(i).getReg();
3563 // FIXME: We would really prefer to have MCInstrInfo (the wrapper around
3564 // the ARMInsts array) instead. Getting that here requires awkward
3565 // API changes, though. Better way?
3567 extern MCInstrDesc ARMInsts[];
3569 static MCInstrDesc &getInstDesc(unsigned Opcode) {
3570 return ARMInsts[Opcode];
3573 // FIXME: We would really like to be able to tablegen'erate this.
3575 validateInstruction(MCInst &Inst,
3576 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3577 MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3578 SMLoc Loc = Operands[0]->getStartLoc();
3579 // Check the IT block state first.
3580 // NOTE: In Thumb mode, the BKPT instruction has the interesting property of
3581 // being allowed in IT blocks, but not being predicable. It just always
3583 if (inITBlock() && Inst.getOpcode() != ARM::tBKPT) {
3585 if (ITState.FirstCond)
3586 ITState.FirstCond = false;
3588 bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
3589 // The instruction must be predicable.
3590 if (!MCID.isPredicable())
3591 return Error(Loc, "instructions in IT block must be predicable");
3592 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
3593 unsigned ITCond = bit ? ITState.Cond :
3594 ARMCC::getOppositeCondition(ITState.Cond);
3595 if (Cond != ITCond) {
3596 // Find the condition code Operand to get its SMLoc information.
3598 for (unsigned i = 1; i < Operands.size(); ++i)
3599 if (static_cast<ARMOperand*>(Operands[i])->isCondCode())
3600 CondLoc = Operands[i]->getStartLoc();
3601 return Error(CondLoc, "incorrect condition in IT block; got '" +
3602 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
3603 "', but expected '" +
3604 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
3606 // Check for non-'al' condition codes outside of the IT block.
3607 } else if (isThumbTwo() && MCID.isPredicable() &&
3608 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
3609 ARMCC::AL && Inst.getOpcode() != ARM::tB &&
3610 Inst.getOpcode() != ARM::t2B)
3611 return Error(Loc, "predicated instructions must be in IT block");
3613 switch (Inst.getOpcode()) {
3616 case ARM::LDRD_POST:
3618 // Rt2 must be Rt + 1.
3619 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3620 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3622 return Error(Operands[3]->getStartLoc(),
3623 "destination operands must be sequential");
3627 // Rt2 must be Rt + 1.
3628 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
3629 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3631 return Error(Operands[3]->getStartLoc(),
3632 "source operands must be sequential");
3636 case ARM::STRD_POST:
3638 // Rt2 must be Rt + 1.
3639 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
3640 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
3642 return Error(Operands[3]->getStartLoc(),
3643 "source operands must be sequential");
3648 // width must be in range [1, 32-lsb]
3649 unsigned lsb = Inst.getOperand(2).getImm();
3650 unsigned widthm1 = Inst.getOperand(3).getImm();
3651 if (widthm1 >= 32 - lsb)
3652 return Error(Operands[5]->getStartLoc(),
3653 "bitfield width must be in range [1,32-lsb]");
3657 // If we're parsing Thumb2, the .w variant is available and handles
3658 // most cases that are normally illegal for a Thumb1 LDM
3659 // instruction. We'll make the transformation in processInstruction()
3662 // Thumb LDM instructions are writeback iff the base register is not
3663 // in the register list.
3664 unsigned Rn = Inst.getOperand(0).getReg();
3665 bool hasWritebackToken =
3666 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3667 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3668 bool listContainsBase;
3669 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) && !isThumbTwo())
3670 return Error(Operands[3 + hasWritebackToken]->getStartLoc(),
3671 "registers must be in range r0-r7");
3672 // If we should have writeback, then there should be a '!' token.
3673 if (!listContainsBase && !hasWritebackToken && !isThumbTwo())
3674 return Error(Operands[2]->getStartLoc(),
3675 "writeback operator '!' expected");
3676 // If we should not have writeback, there must not be a '!'. This is
3677 // true even for the 32-bit wide encodings.
3678 if (listContainsBase && hasWritebackToken)
3679 return Error(Operands[3]->getStartLoc(),
3680 "writeback operator '!' not allowed when base register "
3681 "in register list");
3685 case ARM::t2LDMIA_UPD: {
3686 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
3687 return Error(Operands[4]->getStartLoc(),
3688 "writeback operator '!' not allowed when base register "
3689 "in register list");
3693 bool listContainsBase;
3694 if (checkLowRegisterList(Inst, 3, 0, ARM::PC, listContainsBase))
3695 return Error(Operands[2]->getStartLoc(),
3696 "registers must be in range r0-r7 or pc");
3700 bool listContainsBase;
3701 if (checkLowRegisterList(Inst, 3, 0, ARM::LR, listContainsBase))
3702 return Error(Operands[2]->getStartLoc(),
3703 "registers must be in range r0-r7 or lr");
3706 case ARM::tSTMIA_UPD: {
3707 bool listContainsBase;
3708 if (checkLowRegisterList(Inst, 4, 0, 0, listContainsBase) && !isThumbTwo())
3709 return Error(Operands[4]->getStartLoc(),
3710 "registers must be in range r0-r7");
3719 processInstruction(MCInst &Inst,
3720 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
3721 switch (Inst.getOpcode()) {
3722 case ARM::LDMIA_UPD:
3723 // If this is a load of a single register via a 'pop', then we should use
3724 // a post-indexed LDR instruction instead, per the ARM ARM.
3725 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "pop" &&
3726 Inst.getNumOperands() == 5) {
3728 TmpInst.setOpcode(ARM::LDR_POST_IMM);
3729 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3730 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3731 TmpInst.addOperand(Inst.getOperand(1)); // Rn
3732 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
3733 TmpInst.addOperand(MCOperand::CreateImm(4));
3734 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3735 TmpInst.addOperand(Inst.getOperand(3));
3739 case ARM::STMDB_UPD:
3740 // If this is a store of a single register via a 'push', then we should use
3741 // a pre-indexed STR instruction instead, per the ARM ARM.
3742 if (static_cast<ARMOperand*>(Operands[0])->getToken() == "push" &&
3743 Inst.getNumOperands() == 5) {
3745 TmpInst.setOpcode(ARM::STR_PRE_IMM);
3746 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
3747 TmpInst.addOperand(Inst.getOperand(4)); // Rt
3748 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
3749 TmpInst.addOperand(MCOperand::CreateImm(-4));
3750 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
3751 TmpInst.addOperand(Inst.getOperand(3));
3756 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3757 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3758 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3759 // to encoding T1 if <Rd> is omitted."
3760 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3761 Inst.setOpcode(ARM::tADDi3);
3764 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
3765 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
3766 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
3767 // to encoding T1 if <Rd> is omitted."
3768 if (Inst.getOperand(3).getImm() < 8 && Operands.size() == 6)
3769 Inst.setOpcode(ARM::tSUBi3);
3772 // A Thumb conditional branch outside of an IT block is a tBcc.
3773 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3774 Inst.setOpcode(ARM::tBcc);
3777 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
3778 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock())
3779 Inst.setOpcode(ARM::t2Bcc);
3782 // If the conditional is AL or we're in an IT block, we really want t2B.
3783 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock())
3784 Inst.setOpcode(ARM::t2B);
3787 // If the conditional is AL, we really want tB.
3788 if (Inst.getOperand(1).getImm() == ARMCC::AL)
3789 Inst.setOpcode(ARM::tB);
3792 // If the register list contains any high registers, or if the writeback
3793 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
3794 // instead if we're in Thumb2. Otherwise, this should have generated
3795 // an error in validateInstruction().
3796 unsigned Rn = Inst.getOperand(0).getReg();
3797 bool hasWritebackToken =
3798 (static_cast<ARMOperand*>(Operands[3])->isToken() &&
3799 static_cast<ARMOperand*>(Operands[3])->getToken() == "!");
3800 bool listContainsBase;
3801 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
3802 (!listContainsBase && !hasWritebackToken) ||
3803 (listContainsBase && hasWritebackToken)) {
3804 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3805 assert (isThumbTwo());
3806 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
3807 // If we're switching to the updating version, we need to insert
3808 // the writeback tied operand.
3809 if (hasWritebackToken)
3810 Inst.insert(Inst.begin(),
3811 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
3815 case ARM::tSTMIA_UPD: {
3816 // If the register list contains any high registers, we need to use
3817 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
3818 // should have generated an error in validateInstruction().
3819 unsigned Rn = Inst.getOperand(0).getReg();
3820 bool listContainsBase;
3821 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
3822 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
3823 assert (isThumbTwo());
3824 Inst.setOpcode(ARM::t2STMIA_UPD);
3829 // If we can use the 16-bit encoding and the user didn't explicitly
3830 // request the 32-bit variant, transform it here.
3831 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3832 Inst.getOperand(1).getImm() <= 255 &&
3833 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
3834 Inst.getOperand(4).getReg() == ARM::CPSR) ||
3835 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
3836 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3837 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3838 // The operands aren't in the same order for tMOVi8...
3840 TmpInst.setOpcode(ARM::tMOVi8);
3841 TmpInst.addOperand(Inst.getOperand(0));
3842 TmpInst.addOperand(Inst.getOperand(4));
3843 TmpInst.addOperand(Inst.getOperand(1));
3844 TmpInst.addOperand(Inst.getOperand(2));
3845 TmpInst.addOperand(Inst.getOperand(3));
3851 // If we can use the 16-bit encoding and the user didn't explicitly
3852 // request the 32-bit variant, transform it here.
3853 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
3854 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3855 Inst.getOperand(2).getImm() == ARMCC::AL &&
3856 Inst.getOperand(4).getReg() == ARM::CPSR &&
3857 (!static_cast<ARMOperand*>(Operands[2])->isToken() ||
3858 static_cast<ARMOperand*>(Operands[2])->getToken() != ".w")) {
3859 // The operands aren't the same for tMOV[S]r... (no cc_out)
3861 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
3862 TmpInst.addOperand(Inst.getOperand(0));
3863 TmpInst.addOperand(Inst.getOperand(1));
3864 TmpInst.addOperand(Inst.getOperand(2));
3865 TmpInst.addOperand(Inst.getOperand(3));
3871 // The mask bits for all but the first condition are represented as
3872 // the low bit of the condition code value implies 't'. We currently
3873 // always have 1 implies 't', so XOR toggle the bits if the low bit
3874 // of the condition code is zero. The encoding also expects the low
3875 // bit of the condition to be encoded as bit 4 of the mask operand,
3876 // so mask that in if needed
3877 MCOperand &MO = Inst.getOperand(1);
3878 unsigned Mask = MO.getImm();
3879 unsigned OrigMask = Mask;
3880 unsigned TZ = CountTrailingZeros_32(Mask);
3881 if ((Inst.getOperand(0).getImm() & 1) == 0) {
3882 assert(Mask && TZ <= 3 && "illegal IT mask value!");
3883 for (unsigned i = 3; i != TZ; --i)
3889 // Set up the IT block state according to the IT instruction we just
3891 assert(!inITBlock() && "nested IT blocks?!");
3892 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
3893 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
3894 ITState.CurPosition = 0;
3895 ITState.FirstCond = true;
3901 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3902 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
3903 // suffix depending on whether they're in an IT block or not.
3904 unsigned Opc = Inst.getOpcode();
3905 MCInstrDesc &MCID = getInstDesc(Opc);
3906 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
3907 assert(MCID.hasOptionalDef() &&
3908 "optionally flag setting instruction missing optional def operand");
3909 assert(MCID.NumOperands == Inst.getNumOperands() &&
3910 "operand count mismatch!");
3911 // Find the optional-def operand (cc_out).
3914 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
3917 // If we're parsing Thumb1, reject it completely.
3918 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
3919 return Match_MnemonicFail;
3920 // If we're parsing Thumb2, which form is legal depends on whether we're
3922 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
3924 return Match_RequiresITBlock;
3925 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
3927 return Match_RequiresNotITBlock;
3929 // Some high-register supporting Thumb1 encodings only allow both registers
3930 // to be from r0-r7 when in Thumb2.
3931 else if (Opc == ARM::tADDhirr && isThumbOne() &&
3932 isARMLowRegister(Inst.getOperand(1).getReg()) &&
3933 isARMLowRegister(Inst.getOperand(2).getReg()))
3934 return Match_RequiresThumb2;
3935 // Others only require ARMv6 or later.
3936 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
3937 isARMLowRegister(Inst.getOperand(0).getReg()) &&
3938 isARMLowRegister(Inst.getOperand(1).getReg()))
3939 return Match_RequiresV6;
3940 return Match_Success;
3944 MatchAndEmitInstruction(SMLoc IDLoc,
3945 SmallVectorImpl<MCParsedAsmOperand*> &Operands,
3949 unsigned MatchResult;
3950 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo);
3951 switch (MatchResult) {
3954 // Context sensitive operand constraints aren't handled by the matcher,
3955 // so check them here.
3956 if (validateInstruction(Inst, Operands)) {
3957 // Still progress the IT block, otherwise one wrong condition causes
3958 // nasty cascading errors.
3959 forwardITPosition();
3963 // Some instructions need post-processing to, for example, tweak which
3964 // encoding is selected.
3965 processInstruction(Inst, Operands);
3967 // Only move forward at the very end so that everything in validate
3968 // and process gets a consistent answer about whether we're in an IT
3970 forwardITPosition();
3972 Out.EmitInstruction(Inst);
3974 case Match_MissingFeature:
3975 Error(IDLoc, "instruction requires a CPU feature not currently enabled");
3977 case Match_InvalidOperand: {
3978 SMLoc ErrorLoc = IDLoc;
3979 if (ErrorInfo != ~0U) {
3980 if (ErrorInfo >= Operands.size())
3981 return Error(IDLoc, "too few operands for instruction");
3983 ErrorLoc = ((ARMOperand*)Operands[ErrorInfo])->getStartLoc();
3984 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
3987 return Error(ErrorLoc, "invalid operand for instruction");
3989 case Match_MnemonicFail:
3990 return Error(IDLoc, "invalid instruction");
3991 case Match_ConversionFail:
3992 // The converter function will have already emited a diagnostic.
3994 case Match_RequiresNotITBlock:
3995 return Error(IDLoc, "flag setting instruction only valid outside IT block");
3996 case Match_RequiresITBlock:
3997 return Error(IDLoc, "instruction only valid inside IT block");
3998 case Match_RequiresV6:
3999 return Error(IDLoc, "instruction variant requires ARMv6 or later");
4000 case Match_RequiresThumb2:
4001 return Error(IDLoc, "instruction variant requires Thumb2");
4004 llvm_unreachable("Implement any new match types added!");
4008 /// parseDirective parses the arm specific directives
4009 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
4010 StringRef IDVal = DirectiveID.getIdentifier();
4011 if (IDVal == ".word")
4012 return parseDirectiveWord(4, DirectiveID.getLoc());
4013 else if (IDVal == ".thumb")
4014 return parseDirectiveThumb(DirectiveID.getLoc());
4015 else if (IDVal == ".thumb_func")
4016 return parseDirectiveThumbFunc(DirectiveID.getLoc());
4017 else if (IDVal == ".code")
4018 return parseDirectiveCode(DirectiveID.getLoc());
4019 else if (IDVal == ".syntax")
4020 return parseDirectiveSyntax(DirectiveID.getLoc());
4024 /// parseDirectiveWord
4025 /// ::= .word [ expression (, expression)* ]
4026 bool ARMAsmParser::parseDirectiveWord(unsigned Size, SMLoc L) {
4027 if (getLexer().isNot(AsmToken::EndOfStatement)) {
4029 const MCExpr *Value;
4030 if (getParser().ParseExpression(Value))
4033 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
4035 if (getLexer().is(AsmToken::EndOfStatement))
4038 // FIXME: Improve diagnostic.
4039 if (getLexer().isNot(AsmToken::Comma))
4040 return Error(L, "unexpected token in directive");
4049 /// parseDirectiveThumb
4051 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
4052 if (getLexer().isNot(AsmToken::EndOfStatement))
4053 return Error(L, "unexpected token in directive");
4056 // TODO: set thumb mode
4057 // TODO: tell the MC streamer the mode
4058 // getParser().getStreamer().Emit???();
4062 /// parseDirectiveThumbFunc
4063 /// ::= .thumbfunc symbol_name
4064 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
4065 const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo();
4066 bool isMachO = MAI.hasSubsectionsViaSymbols();
4069 // Darwin asm has function name after .thumb_func direction
4072 const AsmToken &Tok = Parser.getTok();
4073 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
4074 return Error(L, "unexpected token in .thumb_func directive");
4075 Name = Tok.getString();
4076 Parser.Lex(); // Consume the identifier token.
4079 if (getLexer().isNot(AsmToken::EndOfStatement))
4080 return Error(L, "unexpected token in directive");
4083 // FIXME: assuming function name will be the line following .thumb_func
4085 Name = Parser.getTok().getString();
4088 // Mark symbol as a thumb symbol.
4089 MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name);
4090 getParser().getStreamer().EmitThumbFunc(Func);
4094 /// parseDirectiveSyntax
4095 /// ::= .syntax unified | divided
4096 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
4097 const AsmToken &Tok = Parser.getTok();
4098 if (Tok.isNot(AsmToken::Identifier))
4099 return Error(L, "unexpected token in .syntax directive");
4100 StringRef Mode = Tok.getString();
4101 if (Mode == "unified" || Mode == "UNIFIED")
4103 else if (Mode == "divided" || Mode == "DIVIDED")
4104 return Error(L, "'.syntax divided' arm asssembly not supported");
4106 return Error(L, "unrecognized syntax mode in .syntax directive");
4108 if (getLexer().isNot(AsmToken::EndOfStatement))
4109 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4112 // TODO tell the MC streamer the mode
4113 // getParser().getStreamer().Emit???();
4117 /// parseDirectiveCode
4118 /// ::= .code 16 | 32
4119 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
4120 const AsmToken &Tok = Parser.getTok();
4121 if (Tok.isNot(AsmToken::Integer))
4122 return Error(L, "unexpected token in .code directive");
4123 int64_t Val = Parser.getTok().getIntVal();
4129 return Error(L, "invalid operand to .code directive");
4131 if (getLexer().isNot(AsmToken::EndOfStatement))
4132 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
4138 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
4142 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
4148 extern "C" void LLVMInitializeARMAsmLexer();
4150 /// Force static initialization.
4151 extern "C" void LLVMInitializeARMAsmParser() {
4152 RegisterMCAsmParser<ARMAsmParser> X(TheARMTarget);
4153 RegisterMCAsmParser<ARMAsmParser> Y(TheThumbTarget);
4154 LLVMInitializeARMAsmLexer();
4157 #define GET_REGISTER_MATCHER
4158 #define GET_MATCHER_IMPLEMENTATION
4159 #include "ARMGenAsmMatcher.inc"