1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFeatures.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Triple.h"
19 #include "llvm/ADT/Twine.h"
20 #include "llvm/MC/MCAsmInfo.h"
21 #include "llvm/MC/MCAssembler.h"
22 #include "llvm/MC/MCContext.h"
23 #include "llvm/MC/MCDisassembler.h"
24 #include "llvm/MC/MCELFStreamer.h"
25 #include "llvm/MC/MCExpr.h"
26 #include "llvm/MC/MCInst.h"
27 #include "llvm/MC/MCInstrDesc.h"
28 #include "llvm/MC/MCInstrInfo.h"
29 #include "llvm/MC/MCObjectFileInfo.h"
30 #include "llvm/MC/MCParser/MCAsmLexer.h"
31 #include "llvm/MC/MCParser/MCAsmParser.h"
32 #include "llvm/MC/MCParser/MCAsmParserUtils.h"
33 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
34 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/MC/MCSection.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
38 #include "llvm/MC/MCSymbol.h"
39 #include "llvm/MC/MCTargetAsmParser.h"
40 #include "llvm/Support/ARMBuildAttributes.h"
41 #include "llvm/Support/ARMEHABI.h"
42 #include "llvm/Support/TargetParser.h"
43 #include "llvm/Support/COFF.h"
44 #include "llvm/Support/Debug.h"
45 #include "llvm/Support/ELF.h"
46 #include "llvm/Support/MathExtras.h"
47 #include "llvm/Support/SourceMgr.h"
48 #include "llvm/Support/TargetRegistry.h"
49 #include "llvm/Support/raw_ostream.h"
57 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
62 typedef SmallVector<SMLoc, 4> Locs;
67 Locs PersonalityIndexLocs;
72 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
74 bool hasFnStart() const { return !FnStartLocs.empty(); }
75 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
76 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
77 bool hasPersonality() const {
78 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
81 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
82 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
83 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
84 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
85 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
87 void saveFPReg(int Reg) { FPReg = Reg; }
88 int getFPReg() const { return FPReg; }
90 void emitFnStartLocNotes() const {
91 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
93 Parser.Note(*FI, ".fnstart was specified here");
95 void emitCantUnwindLocNotes() const {
96 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
97 UE = CantUnwindLocs.end(); UI != UE; ++UI)
98 Parser.Note(*UI, ".cantunwind was specified here");
100 void emitHandlerDataLocNotes() const {
101 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
102 HE = HandlerDataLocs.end(); HI != HE; ++HI)
103 Parser.Note(*HI, ".handlerdata was specified here");
105 void emitPersonalityLocNotes() const {
106 for (Locs::const_iterator PI = PersonalityLocs.begin(),
107 PE = PersonalityLocs.end(),
108 PII = PersonalityIndexLocs.begin(),
109 PIE = PersonalityIndexLocs.end();
110 PI != PE || PII != PIE;) {
111 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
112 Parser.Note(*PI++, ".personality was specified here");
113 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
114 Parser.Note(*PII++, ".personalityindex was specified here");
116 llvm_unreachable(".personality and .personalityindex cannot be "
117 "at the same location");
122 FnStartLocs = Locs();
123 CantUnwindLocs = Locs();
124 PersonalityLocs = Locs();
125 HandlerDataLocs = Locs();
126 PersonalityIndexLocs = Locs();
131 class ARMAsmParser : public MCTargetAsmParser {
132 const MCInstrInfo &MII;
133 const MCRegisterInfo *MRI;
136 ARMTargetStreamer &getTargetStreamer() {
137 assert(getParser().getStreamer().getTargetStreamer() &&
138 "do not have a target streamer");
139 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
140 return static_cast<ARMTargetStreamer &>(TS);
143 // Map of register aliases registers via the .req directive.
144 StringMap<unsigned> RegisterReqs;
146 bool NextSymbolIsThumb;
149 ARMCC::CondCodes Cond; // Condition for IT block.
150 unsigned Mask:4; // Condition mask for instructions.
151 // Starting at first 1 (from lsb).
152 // '1' condition as indicated in IT.
153 // '0' inverse of condition (else).
154 // Count of instructions in IT block is
155 // 4 - trailingzeroes(mask)
157 bool FirstCond; // Explicit flag for when we're parsing the
158 // First instruction in the IT block. It's
159 // implied in the mask, so needs special
162 unsigned CurPosition; // Current position in parsing of IT
163 // block. In range [0,3]. Initialized
164 // according to count of instructions in block.
165 // ~0U if no active IT block.
167 bool inITBlock() { return ITState.CurPosition != ~0U; }
168 bool lastInITBlock() {
169 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
171 void forwardITPosition() {
172 if (!inITBlock()) return;
173 // Move to the next instruction in the IT block, if there is one. If not,
174 // mark the block as done.
175 unsigned TZ = countTrailingZeros(ITState.Mask);
176 if (++ITState.CurPosition == 5 - TZ)
177 ITState.CurPosition = ~0U; // Done with the IT block after this.
180 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
181 return getParser().Note(L, Msg, Ranges);
183 bool Warning(SMLoc L, const Twine &Msg,
184 ArrayRef<SMRange> Ranges = None) {
185 return getParser().Warning(L, Msg, Ranges);
187 bool Error(SMLoc L, const Twine &Msg,
188 ArrayRef<SMRange> Ranges = None) {
189 return getParser().Error(L, Msg, Ranges);
192 bool validatetLDMRegList(const MCInst &Inst, const OperandVector &Operands,
193 unsigned ListNo, bool IsARPop = false);
194 bool validatetSTMRegList(const MCInst &Inst, const OperandVector &Operands,
197 int tryParseRegister();
198 bool tryParseRegisterWithWriteBack(OperandVector &);
199 int tryParseShiftRegister(OperandVector &);
200 bool parseRegisterList(OperandVector &);
201 bool parseMemory(OperandVector &);
202 bool parseOperand(OperandVector &, StringRef Mnemonic);
203 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
204 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
205 unsigned &ShiftAmount);
206 bool parseLiteralValues(unsigned Size, SMLoc L);
207 bool parseDirectiveThumb(SMLoc L);
208 bool parseDirectiveARM(SMLoc L);
209 bool parseDirectiveThumbFunc(SMLoc L);
210 bool parseDirectiveCode(SMLoc L);
211 bool parseDirectiveSyntax(SMLoc L);
212 bool parseDirectiveReq(StringRef Name, SMLoc L);
213 bool parseDirectiveUnreq(SMLoc L);
214 bool parseDirectiveArch(SMLoc L);
215 bool parseDirectiveEabiAttr(SMLoc L);
216 bool parseDirectiveCPU(SMLoc L);
217 bool parseDirectiveFPU(SMLoc L);
218 bool parseDirectiveFnStart(SMLoc L);
219 bool parseDirectiveFnEnd(SMLoc L);
220 bool parseDirectiveCantUnwind(SMLoc L);
221 bool parseDirectivePersonality(SMLoc L);
222 bool parseDirectiveHandlerData(SMLoc L);
223 bool parseDirectiveSetFP(SMLoc L);
224 bool parseDirectivePad(SMLoc L);
225 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
226 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
227 bool parseDirectiveLtorg(SMLoc L);
228 bool parseDirectiveEven(SMLoc L);
229 bool parseDirectivePersonalityIndex(SMLoc L);
230 bool parseDirectiveUnwindRaw(SMLoc L);
231 bool parseDirectiveTLSDescSeq(SMLoc L);
232 bool parseDirectiveMovSP(SMLoc L);
233 bool parseDirectiveObjectArch(SMLoc L);
234 bool parseDirectiveArchExtension(SMLoc L);
235 bool parseDirectiveAlign(SMLoc L);
236 bool parseDirectiveThumbSet(SMLoc L);
238 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
239 bool &CarrySetting, unsigned &ProcessorIMod,
241 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
242 bool &CanAcceptCarrySet,
243 bool &CanAcceptPredicationCode);
245 void tryConvertingToTwoOperandForm(StringRef Mnemonic, bool CarrySetting,
246 OperandVector &Operands);
247 bool isThumb() const {
248 // FIXME: Can tablegen auto-generate this?
249 return getSTI().getFeatureBits()[ARM::ModeThumb];
251 bool isThumbOne() const {
252 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
254 bool isThumbTwo() const {
255 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
257 bool hasThumb() const {
258 return getSTI().getFeatureBits()[ARM::HasV4TOps];
260 bool hasV6Ops() const {
261 return getSTI().getFeatureBits()[ARM::HasV6Ops];
263 bool hasV6MOps() const {
264 return getSTI().getFeatureBits()[ARM::HasV6MOps];
266 bool hasV7Ops() const {
267 return getSTI().getFeatureBits()[ARM::HasV7Ops];
269 bool hasV8Ops() const {
270 return getSTI().getFeatureBits()[ARM::HasV8Ops];
272 bool hasARM() const {
273 return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
275 bool hasDSP() const {
276 return getSTI().getFeatureBits()[ARM::FeatureDSP];
278 bool hasD16() const {
279 return getSTI().getFeatureBits()[ARM::FeatureD16];
281 bool hasV8_1aOps() const {
282 return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
286 MCSubtargetInfo &STI = copySTI();
287 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
288 setAvailableFeatures(FB);
290 bool isMClass() const {
291 return getSTI().getFeatureBits()[ARM::FeatureMClass];
294 /// @name Auto-generated Match Functions
297 #define GET_ASSEMBLER_HEADER
298 #include "ARMGenAsmMatcher.inc"
302 OperandMatchResultTy parseITCondCode(OperandVector &);
303 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
304 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
305 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
306 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
307 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
308 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
309 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
310 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
311 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
313 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
314 return parsePKHImm(O, "lsl", 0, 31);
316 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
317 return parsePKHImm(O, "asr", 1, 32);
319 OperandMatchResultTy parseSetEndImm(OperandVector &);
320 OperandMatchResultTy parseShifterImm(OperandVector &);
321 OperandMatchResultTy parseRotImm(OperandVector &);
322 OperandMatchResultTy parseModImm(OperandVector &);
323 OperandMatchResultTy parseBitfield(OperandVector &);
324 OperandMatchResultTy parsePostIdxReg(OperandVector &);
325 OperandMatchResultTy parseAM3Offset(OperandVector &);
326 OperandMatchResultTy parseFPImm(OperandVector &);
327 OperandMatchResultTy parseVectorList(OperandVector &);
328 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
331 // Asm Match Converter Methods
332 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
333 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
335 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
336 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
337 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
338 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
341 enum ARMMatchResultTy {
342 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
343 Match_RequiresNotITBlock,
345 Match_RequiresThumb2,
347 #define GET_OPERAND_DIAGNOSTIC_TYPES
348 #include "ARMGenAsmMatcher.inc"
352 ARMAsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
353 const MCInstrInfo &MII, const MCTargetOptions &Options)
354 : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
355 MCAsmParserExtension::Initialize(Parser);
357 // Cache the MCRegisterInfo.
358 MRI = getContext().getRegisterInfo();
360 // Initialize the set of available features.
361 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
363 // Not in an ITBlock to start with.
364 ITState.CurPosition = ~0U;
366 NextSymbolIsThumb = false;
369 // Implementation of the MCTargetAsmParser interface:
370 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
371 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
372 SMLoc NameLoc, OperandVector &Operands) override;
373 bool ParseDirective(AsmToken DirectiveID) override;
375 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
376 unsigned Kind) override;
377 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
379 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
380 OperandVector &Operands, MCStreamer &Out,
382 bool MatchingInlineAsm) override;
383 void onLabelParsed(MCSymbol *Symbol) override;
385 } // end anonymous namespace
389 /// ARMOperand - Instances of this class represent a parsed ARM machine
391 class ARMOperand : public MCParsedAsmOperand {
401 k_InstSyncBarrierOpt,
413 k_VectorListAllLanes,
420 k_BitfieldDescriptor,
424 SMLoc StartLoc, EndLoc, AlignmentLoc;
425 SmallVector<unsigned, 8> Registers;
428 ARMCC::CondCodes Val;
435 struct CoprocOptionOp {
448 ARM_ISB::InstSyncBOpt Val;
452 ARM_PROC::IFlags Val;
472 // A vector register list is a sequential list of 1 to 4 registers.
473 struct VectorListOp {
480 struct VectorIndexOp {
488 /// Combined record for all forms of ARM address expressions.
491 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
493 const MCConstantExpr *OffsetImm; // Offset immediate value
494 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
495 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
496 unsigned ShiftImm; // shift for OffsetReg.
497 unsigned Alignment; // 0 = no alignment specified
498 // n = alignment in bytes (2, 4, 8, 16, or 32)
499 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
502 struct PostIdxRegOp {
505 ARM_AM::ShiftOpc ShiftTy;
509 struct ShifterImmOp {
514 struct RegShiftedRegOp {
515 ARM_AM::ShiftOpc ShiftTy;
521 struct RegShiftedImmOp {
522 ARM_AM::ShiftOpc ShiftTy;
544 struct CoprocOptionOp CoprocOption;
545 struct MBOptOp MBOpt;
546 struct ISBOptOp ISBOpt;
547 struct ITMaskOp ITMask;
548 struct IFlagsOp IFlags;
549 struct MMaskOp MMask;
550 struct BankedRegOp BankedReg;
553 struct VectorListOp VectorList;
554 struct VectorIndexOp VectorIndex;
556 struct MemoryOp Memory;
557 struct PostIdxRegOp PostIdxReg;
558 struct ShifterImmOp ShifterImm;
559 struct RegShiftedRegOp RegShiftedReg;
560 struct RegShiftedImmOp RegShiftedImm;
561 struct RotImmOp RotImm;
562 struct ModImmOp ModImm;
563 struct BitfieldOp Bitfield;
567 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
569 /// getStartLoc - Get the location of the first token of this operand.
570 SMLoc getStartLoc() const override { return StartLoc; }
571 /// getEndLoc - Get the location of the last token of this operand.
572 SMLoc getEndLoc() const override { return EndLoc; }
573 /// getLocRange - Get the range between the first and last token of this
575 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
577 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
578 SMLoc getAlignmentLoc() const {
579 assert(Kind == k_Memory && "Invalid access!");
583 ARMCC::CondCodes getCondCode() const {
584 assert(Kind == k_CondCode && "Invalid access!");
588 unsigned getCoproc() const {
589 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
593 StringRef getToken() const {
594 assert(Kind == k_Token && "Invalid access!");
595 return StringRef(Tok.Data, Tok.Length);
598 unsigned getReg() const override {
599 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
603 const SmallVectorImpl<unsigned> &getRegList() const {
604 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
605 Kind == k_SPRRegisterList) && "Invalid access!");
609 const MCExpr *getImm() const {
610 assert(isImm() && "Invalid access!");
614 unsigned getVectorIndex() const {
615 assert(Kind == k_VectorIndex && "Invalid access!");
616 return VectorIndex.Val;
619 ARM_MB::MemBOpt getMemBarrierOpt() const {
620 assert(Kind == k_MemBarrierOpt && "Invalid access!");
624 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
625 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
629 ARM_PROC::IFlags getProcIFlags() const {
630 assert(Kind == k_ProcIFlags && "Invalid access!");
634 unsigned getMSRMask() const {
635 assert(Kind == k_MSRMask && "Invalid access!");
639 unsigned getBankedReg() const {
640 assert(Kind == k_BankedReg && "Invalid access!");
641 return BankedReg.Val;
644 bool isCoprocNum() const { return Kind == k_CoprocNum; }
645 bool isCoprocReg() const { return Kind == k_CoprocReg; }
646 bool isCoprocOption() const { return Kind == k_CoprocOption; }
647 bool isCondCode() const { return Kind == k_CondCode; }
648 bool isCCOut() const { return Kind == k_CCOut; }
649 bool isITMask() const { return Kind == k_ITCondMask; }
650 bool isITCondCode() const { return Kind == k_CondCode; }
651 bool isImm() const override { return Kind == k_Immediate; }
652 // checks whether this operand is an unsigned offset which fits is a field
653 // of specified width and scaled by a specific number of bits
654 template<unsigned width, unsigned scale>
655 bool isUnsignedOffset() const {
656 if (!isImm()) return false;
657 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
658 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
659 int64_t Val = CE->getValue();
660 int64_t Align = 1LL << scale;
661 int64_t Max = Align * ((1LL << width) - 1);
662 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
666 // checks whether this operand is an signed offset which fits is a field
667 // of specified width and scaled by a specific number of bits
668 template<unsigned width, unsigned scale>
669 bool isSignedOffset() const {
670 if (!isImm()) return false;
671 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
672 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
673 int64_t Val = CE->getValue();
674 int64_t Align = 1LL << scale;
675 int64_t Max = Align * ((1LL << (width-1)) - 1);
676 int64_t Min = -Align * (1LL << (width-1));
677 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
682 // checks whether this operand is a memory operand computed as an offset
683 // applied to PC. the offset may have 8 bits of magnitude and is represented
684 // with two bits of shift. textually it may be either [pc, #imm], #imm or
685 // relocable expression...
686 bool isThumbMemPC() const {
689 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
690 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
691 if (!CE) return false;
692 Val = CE->getValue();
695 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
696 if(Memory.BaseRegNum != ARM::PC) return false;
697 Val = Memory.OffsetImm->getValue();
700 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
702 bool isFPImm() const {
703 if (!isImm()) return false;
704 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
705 if (!CE) return false;
706 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
709 bool isFBits16() const {
710 if (!isImm()) return false;
711 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
712 if (!CE) return false;
713 int64_t Value = CE->getValue();
714 return Value >= 0 && Value <= 16;
716 bool isFBits32() const {
717 if (!isImm()) return false;
718 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
719 if (!CE) return false;
720 int64_t Value = CE->getValue();
721 return Value >= 1 && Value <= 32;
723 bool isImm8s4() const {
724 if (!isImm()) return false;
725 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
726 if (!CE) return false;
727 int64_t Value = CE->getValue();
728 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
730 bool isImm0_1020s4() const {
731 if (!isImm()) return false;
732 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
733 if (!CE) return false;
734 int64_t Value = CE->getValue();
735 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
737 bool isImm0_508s4() const {
738 if (!isImm()) return false;
739 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
740 if (!CE) return false;
741 int64_t Value = CE->getValue();
742 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
744 bool isImm0_508s4Neg() const {
745 if (!isImm()) return false;
746 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
747 if (!CE) return false;
748 int64_t Value = -CE->getValue();
749 // explicitly exclude zero. we want that to use the normal 0_508 version.
750 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
752 bool isImm0_239() const {
753 if (!isImm()) return false;
754 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
755 if (!CE) return false;
756 int64_t Value = CE->getValue();
757 return Value >= 0 && Value < 240;
759 bool isImm0_255() const {
760 if (!isImm()) return false;
761 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
762 if (!CE) return false;
763 int64_t Value = CE->getValue();
764 return Value >= 0 && Value < 256;
766 bool isImm0_4095() const {
767 if (!isImm()) return false;
768 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
769 if (!CE) return false;
770 int64_t Value = CE->getValue();
771 return Value >= 0 && Value < 4096;
773 bool isImm0_4095Neg() const {
774 if (!isImm()) return false;
775 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
776 if (!CE) return false;
777 int64_t Value = -CE->getValue();
778 return Value > 0 && Value < 4096;
780 bool isImm0_1() const {
781 if (!isImm()) return false;
782 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
783 if (!CE) return false;
784 int64_t Value = CE->getValue();
785 return Value >= 0 && Value < 2;
787 bool isImm0_3() const {
788 if (!isImm()) return false;
789 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
790 if (!CE) return false;
791 int64_t Value = CE->getValue();
792 return Value >= 0 && Value < 4;
794 bool isImm0_7() const {
795 if (!isImm()) return false;
796 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
797 if (!CE) return false;
798 int64_t Value = CE->getValue();
799 return Value >= 0 && Value < 8;
801 bool isImm0_15() const {
802 if (!isImm()) return false;
803 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
804 if (!CE) return false;
805 int64_t Value = CE->getValue();
806 return Value >= 0 && Value < 16;
808 bool isImm0_31() const {
809 if (!isImm()) return false;
810 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
811 if (!CE) return false;
812 int64_t Value = CE->getValue();
813 return Value >= 0 && Value < 32;
815 bool isImm0_63() const {
816 if (!isImm()) return false;
817 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
818 if (!CE) return false;
819 int64_t Value = CE->getValue();
820 return Value >= 0 && Value < 64;
822 bool isImm8() const {
823 if (!isImm()) return false;
824 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
825 if (!CE) return false;
826 int64_t Value = CE->getValue();
829 bool isImm16() const {
830 if (!isImm()) return false;
831 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
832 if (!CE) return false;
833 int64_t Value = CE->getValue();
836 bool isImm32() const {
837 if (!isImm()) return false;
838 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
839 if (!CE) return false;
840 int64_t Value = CE->getValue();
843 bool isShrImm8() const {
844 if (!isImm()) return false;
845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
846 if (!CE) return false;
847 int64_t Value = CE->getValue();
848 return Value > 0 && Value <= 8;
850 bool isShrImm16() const {
851 if (!isImm()) return false;
852 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
853 if (!CE) return false;
854 int64_t Value = CE->getValue();
855 return Value > 0 && Value <= 16;
857 bool isShrImm32() const {
858 if (!isImm()) return false;
859 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
860 if (!CE) return false;
861 int64_t Value = CE->getValue();
862 return Value > 0 && Value <= 32;
864 bool isShrImm64() const {
865 if (!isImm()) return false;
866 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
867 if (!CE) return false;
868 int64_t Value = CE->getValue();
869 return Value > 0 && Value <= 64;
871 bool isImm1_7() const {
872 if (!isImm()) return false;
873 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
874 if (!CE) return false;
875 int64_t Value = CE->getValue();
876 return Value > 0 && Value < 8;
878 bool isImm1_15() const {
879 if (!isImm()) return false;
880 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
881 if (!CE) return false;
882 int64_t Value = CE->getValue();
883 return Value > 0 && Value < 16;
885 bool isImm1_31() const {
886 if (!isImm()) return false;
887 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
888 if (!CE) return false;
889 int64_t Value = CE->getValue();
890 return Value > 0 && Value < 32;
892 bool isImm1_16() const {
893 if (!isImm()) return false;
894 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
895 if (!CE) return false;
896 int64_t Value = CE->getValue();
897 return Value > 0 && Value < 17;
899 bool isImm1_32() const {
900 if (!isImm()) return false;
901 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
902 if (!CE) return false;
903 int64_t Value = CE->getValue();
904 return Value > 0 && Value < 33;
906 bool isImm0_32() const {
907 if (!isImm()) return false;
908 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
909 if (!CE) return false;
910 int64_t Value = CE->getValue();
911 return Value >= 0 && Value < 33;
913 bool isImm0_65535() const {
914 if (!isImm()) return false;
915 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
916 if (!CE) return false;
917 int64_t Value = CE->getValue();
918 return Value >= 0 && Value < 65536;
920 bool isImm256_65535Expr() const {
921 if (!isImm()) return false;
922 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
923 // If it's not a constant expression, it'll generate a fixup and be
925 if (!CE) return true;
926 int64_t Value = CE->getValue();
927 return Value >= 256 && Value < 65536;
929 bool isImm0_65535Expr() const {
930 if (!isImm()) return false;
931 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
932 // If it's not a constant expression, it'll generate a fixup and be
934 if (!CE) return true;
935 int64_t Value = CE->getValue();
936 return Value >= 0 && Value < 65536;
938 bool isImm24bit() const {
939 if (!isImm()) return false;
940 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
941 if (!CE) return false;
942 int64_t Value = CE->getValue();
943 return Value >= 0 && Value <= 0xffffff;
945 bool isImmThumbSR() const {
946 if (!isImm()) return false;
947 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
948 if (!CE) return false;
949 int64_t Value = CE->getValue();
950 return Value > 0 && Value < 33;
952 bool isPKHLSLImm() const {
953 if (!isImm()) return false;
954 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
955 if (!CE) return false;
956 int64_t Value = CE->getValue();
957 return Value >= 0 && Value < 32;
959 bool isPKHASRImm() const {
960 if (!isImm()) return false;
961 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
962 if (!CE) return false;
963 int64_t Value = CE->getValue();
964 return Value > 0 && Value <= 32;
966 bool isAdrLabel() const {
967 // If we have an immediate that's not a constant, treat it as a label
968 // reference needing a fixup.
969 if (isImm() && !isa<MCConstantExpr>(getImm()))
972 // If it is a constant, it must fit into a modified immediate encoding.
973 if (!isImm()) return false;
974 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
975 if (!CE) return false;
976 int64_t Value = CE->getValue();
977 return (ARM_AM::getSOImmVal(Value) != -1 ||
978 ARM_AM::getSOImmVal(-Value) != -1);
980 bool isT2SOImm() const {
981 if (!isImm()) return false;
982 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
983 if (!CE) return false;
984 int64_t Value = CE->getValue();
985 return ARM_AM::getT2SOImmVal(Value) != -1;
987 bool isT2SOImmNot() const {
988 if (!isImm()) return false;
989 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
990 if (!CE) return false;
991 int64_t Value = CE->getValue();
992 return ARM_AM::getT2SOImmVal(Value) == -1 &&
993 ARM_AM::getT2SOImmVal(~Value) != -1;
995 bool isT2SOImmNeg() const {
996 if (!isImm()) return false;
997 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
998 if (!CE) return false;
999 int64_t Value = CE->getValue();
1000 // Only use this when not representable as a plain so_imm.
1001 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1002 ARM_AM::getT2SOImmVal(-Value) != -1;
1004 bool isSetEndImm() const {
1005 if (!isImm()) return false;
1006 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1007 if (!CE) return false;
1008 int64_t Value = CE->getValue();
1009 return Value == 1 || Value == 0;
1011 bool isReg() const override { return Kind == k_Register; }
1012 bool isRegList() const { return Kind == k_RegisterList; }
1013 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1014 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1015 bool isToken() const override { return Kind == k_Token; }
1016 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1017 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1018 bool isMem() const override { return Kind == k_Memory; }
1019 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1020 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1021 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1022 bool isRotImm() const { return Kind == k_RotateImmediate; }
1023 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1024 bool isModImmNot() const {
1025 if (!isImm()) return false;
1026 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1027 if (!CE) return false;
1028 int64_t Value = CE->getValue();
1029 return ARM_AM::getSOImmVal(~Value) != -1;
1031 bool isModImmNeg() const {
1032 if (!isImm()) return false;
1033 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1034 if (!CE) return false;
1035 int64_t Value = CE->getValue();
1036 return ARM_AM::getSOImmVal(Value) == -1 &&
1037 ARM_AM::getSOImmVal(-Value) != -1;
1039 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1040 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1041 bool isPostIdxReg() const {
1042 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1044 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1047 // No offset of any kind.
1048 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1049 (alignOK || Memory.Alignment == Alignment);
1051 bool isMemPCRelImm12() const {
1052 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1054 // Base register must be PC.
1055 if (Memory.BaseRegNum != ARM::PC)
1057 // Immediate offset in range [-4095, 4095].
1058 if (!Memory.OffsetImm) return true;
1059 int64_t Val = Memory.OffsetImm->getValue();
1060 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1062 bool isAlignedMemory() const {
1063 return isMemNoOffset(true);
1065 bool isAlignedMemoryNone() const {
1066 return isMemNoOffset(false, 0);
1068 bool isDupAlignedMemoryNone() const {
1069 return isMemNoOffset(false, 0);
1071 bool isAlignedMemory16() const {
1072 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1074 return isMemNoOffset(false, 0);
1076 bool isDupAlignedMemory16() const {
1077 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1079 return isMemNoOffset(false, 0);
1081 bool isAlignedMemory32() const {
1082 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1084 return isMemNoOffset(false, 0);
1086 bool isDupAlignedMemory32() const {
1087 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1089 return isMemNoOffset(false, 0);
1091 bool isAlignedMemory64() const {
1092 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1094 return isMemNoOffset(false, 0);
1096 bool isDupAlignedMemory64() const {
1097 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1099 return isMemNoOffset(false, 0);
1101 bool isAlignedMemory64or128() const {
1102 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1104 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1106 return isMemNoOffset(false, 0);
1108 bool isDupAlignedMemory64or128() const {
1109 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1111 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1113 return isMemNoOffset(false, 0);
1115 bool isAlignedMemory64or128or256() const {
1116 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1118 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1120 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1122 return isMemNoOffset(false, 0);
1124 bool isAddrMode2() const {
1125 if (!isMem() || Memory.Alignment != 0) return false;
1126 // Check for register offset.
1127 if (Memory.OffsetRegNum) return true;
1128 // Immediate offset in range [-4095, 4095].
1129 if (!Memory.OffsetImm) return true;
1130 int64_t Val = Memory.OffsetImm->getValue();
1131 return Val > -4096 && Val < 4096;
1133 bool isAM2OffsetImm() const {
1134 if (!isImm()) return false;
1135 // Immediate offset in range [-4095, 4095].
1136 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1137 if (!CE) return false;
1138 int64_t Val = CE->getValue();
1139 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1141 bool isAddrMode3() const {
1142 // If we have an immediate that's not a constant, treat it as a label
1143 // reference needing a fixup. If it is a constant, it's something else
1144 // and we reject it.
1145 if (isImm() && !isa<MCConstantExpr>(getImm()))
1147 if (!isMem() || Memory.Alignment != 0) return false;
1148 // No shifts are legal for AM3.
1149 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1150 // Check for register offset.
1151 if (Memory.OffsetRegNum) return true;
1152 // Immediate offset in range [-255, 255].
1153 if (!Memory.OffsetImm) return true;
1154 int64_t Val = Memory.OffsetImm->getValue();
1155 // The #-0 offset is encoded as INT32_MIN, and we have to check
1157 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1159 bool isAM3Offset() const {
1160 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1162 if (Kind == k_PostIndexRegister)
1163 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1164 // Immediate offset in range [-255, 255].
1165 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1166 if (!CE) return false;
1167 int64_t Val = CE->getValue();
1168 // Special case, #-0 is INT32_MIN.
1169 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1171 bool isAddrMode5() const {
1172 // If we have an immediate that's not a constant, treat it as a label
1173 // reference needing a fixup. If it is a constant, it's something else
1174 // and we reject it.
1175 if (isImm() && !isa<MCConstantExpr>(getImm()))
1177 if (!isMem() || Memory.Alignment != 0) return false;
1178 // Check for register offset.
1179 if (Memory.OffsetRegNum) return false;
1180 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1181 if (!Memory.OffsetImm) return true;
1182 int64_t Val = Memory.OffsetImm->getValue();
1183 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1186 bool isAddrMode5FP16() const {
1187 // If we have an immediate that's not a constant, treat it as a label
1188 // reference needing a fixup. If it is a constant, it's something else
1189 // and we reject it.
1190 if (isImm() && !isa<MCConstantExpr>(getImm()))
1192 if (!isMem() || Memory.Alignment != 0) return false;
1193 // Check for register offset.
1194 if (Memory.OffsetRegNum) return false;
1195 // Immediate offset in range [-510, 510] and a multiple of 2.
1196 if (!Memory.OffsetImm) return true;
1197 int64_t Val = Memory.OffsetImm->getValue();
1198 return (Val >= -510 && Val <= 510 && ((Val & 1) == 0)) || Val == INT32_MIN;
1200 bool isMemTBB() const {
1201 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1202 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1206 bool isMemTBH() const {
1207 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1208 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1209 Memory.Alignment != 0 )
1213 bool isMemRegOffset() const {
1214 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1218 bool isT2MemRegOffset() const {
1219 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1220 Memory.Alignment != 0)
1222 // Only lsl #{0, 1, 2, 3} allowed.
1223 if (Memory.ShiftType == ARM_AM::no_shift)
1225 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1229 bool isMemThumbRR() const {
1230 // Thumb reg+reg addressing is simple. Just two registers, a base and
1231 // an offset. No shifts, negations or any other complicating factors.
1232 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1233 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1235 return isARMLowRegister(Memory.BaseRegNum) &&
1236 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1238 bool isMemThumbRIs4() const {
1239 if (!isMem() || Memory.OffsetRegNum != 0 ||
1240 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1242 // Immediate offset, multiple of 4 in range [0, 124].
1243 if (!Memory.OffsetImm) return true;
1244 int64_t Val = Memory.OffsetImm->getValue();
1245 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1247 bool isMemThumbRIs2() const {
1248 if (!isMem() || Memory.OffsetRegNum != 0 ||
1249 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1251 // Immediate offset, multiple of 4 in range [0, 62].
1252 if (!Memory.OffsetImm) return true;
1253 int64_t Val = Memory.OffsetImm->getValue();
1254 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1256 bool isMemThumbRIs1() const {
1257 if (!isMem() || Memory.OffsetRegNum != 0 ||
1258 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1260 // Immediate offset in range [0, 31].
1261 if (!Memory.OffsetImm) return true;
1262 int64_t Val = Memory.OffsetImm->getValue();
1263 return Val >= 0 && Val <= 31;
1265 bool isMemThumbSPI() const {
1266 if (!isMem() || Memory.OffsetRegNum != 0 ||
1267 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1269 // Immediate offset, multiple of 4 in range [0, 1020].
1270 if (!Memory.OffsetImm) return true;
1271 int64_t Val = Memory.OffsetImm->getValue();
1272 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1274 bool isMemImm8s4Offset() const {
1275 // If we have an immediate that's not a constant, treat it as a label
1276 // reference needing a fixup. If it is a constant, it's something else
1277 // and we reject it.
1278 if (isImm() && !isa<MCConstantExpr>(getImm()))
1280 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1282 // Immediate offset a multiple of 4 in range [-1020, 1020].
1283 if (!Memory.OffsetImm) return true;
1284 int64_t Val = Memory.OffsetImm->getValue();
1285 // Special case, #-0 is INT32_MIN.
1286 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1288 bool isMemImm0_1020s4Offset() const {
1289 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1291 // Immediate offset a multiple of 4 in range [0, 1020].
1292 if (!Memory.OffsetImm) return true;
1293 int64_t Val = Memory.OffsetImm->getValue();
1294 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1296 bool isMemImm8Offset() const {
1297 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1299 // Base reg of PC isn't allowed for these encodings.
1300 if (Memory.BaseRegNum == ARM::PC) return false;
1301 // Immediate offset in range [-255, 255].
1302 if (!Memory.OffsetImm) return true;
1303 int64_t Val = Memory.OffsetImm->getValue();
1304 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1306 bool isMemPosImm8Offset() const {
1307 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1309 // Immediate offset in range [0, 255].
1310 if (!Memory.OffsetImm) return true;
1311 int64_t Val = Memory.OffsetImm->getValue();
1312 return Val >= 0 && Val < 256;
1314 bool isMemNegImm8Offset() const {
1315 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1317 // Base reg of PC isn't allowed for these encodings.
1318 if (Memory.BaseRegNum == ARM::PC) return false;
1319 // Immediate offset in range [-255, -1].
1320 if (!Memory.OffsetImm) return false;
1321 int64_t Val = Memory.OffsetImm->getValue();
1322 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1324 bool isMemUImm12Offset() const {
1325 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1327 // Immediate offset in range [0, 4095].
1328 if (!Memory.OffsetImm) return true;
1329 int64_t Val = Memory.OffsetImm->getValue();
1330 return (Val >= 0 && Val < 4096);
1332 bool isMemImm12Offset() const {
1333 // If we have an immediate that's not a constant, treat it as a label
1334 // reference needing a fixup. If it is a constant, it's something else
1335 // and we reject it.
1336 if (isImm() && !isa<MCConstantExpr>(getImm()))
1339 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1341 // Immediate offset in range [-4095, 4095].
1342 if (!Memory.OffsetImm) return true;
1343 int64_t Val = Memory.OffsetImm->getValue();
1344 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1346 bool isPostIdxImm8() const {
1347 if (!isImm()) return false;
1348 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1349 if (!CE) return false;
1350 int64_t Val = CE->getValue();
1351 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1353 bool isPostIdxImm8s4() const {
1354 if (!isImm()) return false;
1355 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1356 if (!CE) return false;
1357 int64_t Val = CE->getValue();
1358 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1362 bool isMSRMask() const { return Kind == k_MSRMask; }
1363 bool isBankedReg() const { return Kind == k_BankedReg; }
1364 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1367 bool isSingleSpacedVectorList() const {
1368 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1370 bool isDoubleSpacedVectorList() const {
1371 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1373 bool isVecListOneD() const {
1374 if (!isSingleSpacedVectorList()) return false;
1375 return VectorList.Count == 1;
1378 bool isVecListDPair() const {
1379 if (!isSingleSpacedVectorList()) return false;
1380 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1381 .contains(VectorList.RegNum));
1384 bool isVecListThreeD() const {
1385 if (!isSingleSpacedVectorList()) return false;
1386 return VectorList.Count == 3;
1389 bool isVecListFourD() const {
1390 if (!isSingleSpacedVectorList()) return false;
1391 return VectorList.Count == 4;
1394 bool isVecListDPairSpaced() const {
1395 if (Kind != k_VectorList) return false;
1396 if (isSingleSpacedVectorList()) return false;
1397 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1398 .contains(VectorList.RegNum));
1401 bool isVecListThreeQ() const {
1402 if (!isDoubleSpacedVectorList()) return false;
1403 return VectorList.Count == 3;
1406 bool isVecListFourQ() const {
1407 if (!isDoubleSpacedVectorList()) return false;
1408 return VectorList.Count == 4;
1411 bool isSingleSpacedVectorAllLanes() const {
1412 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1414 bool isDoubleSpacedVectorAllLanes() const {
1415 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1417 bool isVecListOneDAllLanes() const {
1418 if (!isSingleSpacedVectorAllLanes()) return false;
1419 return VectorList.Count == 1;
1422 bool isVecListDPairAllLanes() const {
1423 if (!isSingleSpacedVectorAllLanes()) return false;
1424 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1425 .contains(VectorList.RegNum));
1428 bool isVecListDPairSpacedAllLanes() const {
1429 if (!isDoubleSpacedVectorAllLanes()) return false;
1430 return VectorList.Count == 2;
1433 bool isVecListThreeDAllLanes() const {
1434 if (!isSingleSpacedVectorAllLanes()) return false;
1435 return VectorList.Count == 3;
1438 bool isVecListThreeQAllLanes() const {
1439 if (!isDoubleSpacedVectorAllLanes()) return false;
1440 return VectorList.Count == 3;
1443 bool isVecListFourDAllLanes() const {
1444 if (!isSingleSpacedVectorAllLanes()) return false;
1445 return VectorList.Count == 4;
1448 bool isVecListFourQAllLanes() const {
1449 if (!isDoubleSpacedVectorAllLanes()) return false;
1450 return VectorList.Count == 4;
1453 bool isSingleSpacedVectorIndexed() const {
1454 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1456 bool isDoubleSpacedVectorIndexed() const {
1457 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1459 bool isVecListOneDByteIndexed() const {
1460 if (!isSingleSpacedVectorIndexed()) return false;
1461 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1464 bool isVecListOneDHWordIndexed() const {
1465 if (!isSingleSpacedVectorIndexed()) return false;
1466 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1469 bool isVecListOneDWordIndexed() const {
1470 if (!isSingleSpacedVectorIndexed()) return false;
1471 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1474 bool isVecListTwoDByteIndexed() const {
1475 if (!isSingleSpacedVectorIndexed()) return false;
1476 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1479 bool isVecListTwoDHWordIndexed() const {
1480 if (!isSingleSpacedVectorIndexed()) return false;
1481 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1484 bool isVecListTwoQWordIndexed() const {
1485 if (!isDoubleSpacedVectorIndexed()) return false;
1486 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1489 bool isVecListTwoQHWordIndexed() const {
1490 if (!isDoubleSpacedVectorIndexed()) return false;
1491 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1494 bool isVecListTwoDWordIndexed() const {
1495 if (!isSingleSpacedVectorIndexed()) return false;
1496 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1499 bool isVecListThreeDByteIndexed() const {
1500 if (!isSingleSpacedVectorIndexed()) return false;
1501 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1504 bool isVecListThreeDHWordIndexed() const {
1505 if (!isSingleSpacedVectorIndexed()) return false;
1506 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1509 bool isVecListThreeQWordIndexed() const {
1510 if (!isDoubleSpacedVectorIndexed()) return false;
1511 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1514 bool isVecListThreeQHWordIndexed() const {
1515 if (!isDoubleSpacedVectorIndexed()) return false;
1516 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1519 bool isVecListThreeDWordIndexed() const {
1520 if (!isSingleSpacedVectorIndexed()) return false;
1521 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1524 bool isVecListFourDByteIndexed() const {
1525 if (!isSingleSpacedVectorIndexed()) return false;
1526 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1529 bool isVecListFourDHWordIndexed() const {
1530 if (!isSingleSpacedVectorIndexed()) return false;
1531 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1534 bool isVecListFourQWordIndexed() const {
1535 if (!isDoubleSpacedVectorIndexed()) return false;
1536 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1539 bool isVecListFourQHWordIndexed() const {
1540 if (!isDoubleSpacedVectorIndexed()) return false;
1541 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1544 bool isVecListFourDWordIndexed() const {
1545 if (!isSingleSpacedVectorIndexed()) return false;
1546 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1549 bool isVectorIndex8() const {
1550 if (Kind != k_VectorIndex) return false;
1551 return VectorIndex.Val < 8;
1553 bool isVectorIndex16() const {
1554 if (Kind != k_VectorIndex) return false;
1555 return VectorIndex.Val < 4;
1557 bool isVectorIndex32() const {
1558 if (Kind != k_VectorIndex) return false;
1559 return VectorIndex.Val < 2;
1562 bool isNEONi8splat() const {
1563 if (!isImm()) return false;
1564 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1565 // Must be a constant.
1566 if (!CE) return false;
1567 int64_t Value = CE->getValue();
1568 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1570 return Value >= 0 && Value < 256;
1573 bool isNEONi16splat() const {
1574 if (isNEONByteReplicate(2))
1575 return false; // Leave that for bytes replication and forbid by default.
1578 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1579 // Must be a constant.
1580 if (!CE) return false;
1581 unsigned Value = CE->getValue();
1582 return ARM_AM::isNEONi16splat(Value);
1585 bool isNEONi16splatNot() const {
1588 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1589 // Must be a constant.
1590 if (!CE) return false;
1591 unsigned Value = CE->getValue();
1592 return ARM_AM::isNEONi16splat(~Value & 0xffff);
1595 bool isNEONi32splat() const {
1596 if (isNEONByteReplicate(4))
1597 return false; // Leave that for bytes replication and forbid by default.
1600 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1601 // Must be a constant.
1602 if (!CE) return false;
1603 unsigned Value = CE->getValue();
1604 return ARM_AM::isNEONi32splat(Value);
1607 bool isNEONi32splatNot() const {
1610 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1611 // Must be a constant.
1612 if (!CE) return false;
1613 unsigned Value = CE->getValue();
1614 return ARM_AM::isNEONi32splat(~Value);
1617 bool isNEONByteReplicate(unsigned NumBytes) const {
1620 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1621 // Must be a constant.
1624 int64_t Value = CE->getValue();
1626 return false; // Don't bother with zero.
1628 unsigned char B = Value & 0xff;
1629 for (unsigned i = 1; i < NumBytes; ++i) {
1631 if ((Value & 0xff) != B)
1636 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1637 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1638 bool isNEONi32vmov() const {
1639 if (isNEONByteReplicate(4))
1640 return false; // Let it to be classified as byte-replicate case.
1643 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1644 // Must be a constant.
1647 int64_t Value = CE->getValue();
1648 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1649 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1650 // FIXME: This is probably wrong and a copy and paste from previous example
1651 return (Value >= 0 && Value < 256) ||
1652 (Value >= 0x0100 && Value <= 0xff00) ||
1653 (Value >= 0x010000 && Value <= 0xff0000) ||
1654 (Value >= 0x01000000 && Value <= 0xff000000) ||
1655 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1656 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1658 bool isNEONi32vmovNeg() const {
1659 if (!isImm()) return false;
1660 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1661 // Must be a constant.
1662 if (!CE) return false;
1663 int64_t Value = ~CE->getValue();
1664 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1665 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1666 // FIXME: This is probably wrong and a copy and paste from previous example
1667 return (Value >= 0 && Value < 256) ||
1668 (Value >= 0x0100 && Value <= 0xff00) ||
1669 (Value >= 0x010000 && Value <= 0xff0000) ||
1670 (Value >= 0x01000000 && Value <= 0xff000000) ||
1671 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1672 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1675 bool isNEONi64splat() const {
1676 if (!isImm()) return false;
1677 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1678 // Must be a constant.
1679 if (!CE) return false;
1680 uint64_t Value = CE->getValue();
1681 // i64 value with each byte being either 0 or 0xff.
1682 for (unsigned i = 0; i < 8; ++i)
1683 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1687 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1688 // Add as immediates when possible. Null MCExpr = 0.
1690 Inst.addOperand(MCOperand::createImm(0));
1691 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1692 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1694 Inst.addOperand(MCOperand::createExpr(Expr));
1697 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1698 assert(N == 2 && "Invalid number of operands!");
1699 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1700 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1701 Inst.addOperand(MCOperand::createReg(RegNum));
1704 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1705 assert(N == 1 && "Invalid number of operands!");
1706 Inst.addOperand(MCOperand::createImm(getCoproc()));
1709 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1710 assert(N == 1 && "Invalid number of operands!");
1711 Inst.addOperand(MCOperand::createImm(getCoproc()));
1714 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1715 assert(N == 1 && "Invalid number of operands!");
1716 Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
1719 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1720 assert(N == 1 && "Invalid number of operands!");
1721 Inst.addOperand(MCOperand::createImm(ITMask.Mask));
1724 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1725 assert(N == 1 && "Invalid number of operands!");
1726 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
1729 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1730 assert(N == 1 && "Invalid number of operands!");
1731 Inst.addOperand(MCOperand::createReg(getReg()));
1734 void addRegOperands(MCInst &Inst, unsigned N) const {
1735 assert(N == 1 && "Invalid number of operands!");
1736 Inst.addOperand(MCOperand::createReg(getReg()));
1739 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1740 assert(N == 3 && "Invalid number of operands!");
1741 assert(isRegShiftedReg() &&
1742 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1743 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
1744 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
1745 Inst.addOperand(MCOperand::createImm(
1746 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1749 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1750 assert(N == 2 && "Invalid number of operands!");
1751 assert(isRegShiftedImm() &&
1752 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1753 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
1754 // Shift of #32 is encoded as 0 where permitted
1755 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1756 Inst.addOperand(MCOperand::createImm(
1757 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1760 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1761 assert(N == 1 && "Invalid number of operands!");
1762 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
1766 void addRegListOperands(MCInst &Inst, unsigned N) const {
1767 assert(N == 1 && "Invalid number of operands!");
1768 const SmallVectorImpl<unsigned> &RegList = getRegList();
1769 for (SmallVectorImpl<unsigned>::const_iterator
1770 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1771 Inst.addOperand(MCOperand::createReg(*I));
1774 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1775 addRegListOperands(Inst, N);
1778 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1779 addRegListOperands(Inst, N);
1782 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1783 assert(N == 1 && "Invalid number of operands!");
1784 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1785 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
1788 void addModImmOperands(MCInst &Inst, unsigned N) const {
1789 assert(N == 1 && "Invalid number of operands!");
1791 // Support for fixups (MCFixup)
1793 return addImmOperands(Inst, N);
1795 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
1798 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1799 assert(N == 1 && "Invalid number of operands!");
1800 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1801 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1802 Inst.addOperand(MCOperand::createImm(Enc));
1805 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1806 assert(N == 1 && "Invalid number of operands!");
1807 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1808 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1809 Inst.addOperand(MCOperand::createImm(Enc));
1812 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1813 assert(N == 1 && "Invalid number of operands!");
1814 // Munge the lsb/width into a bitfield mask.
1815 unsigned lsb = Bitfield.LSB;
1816 unsigned width = Bitfield.Width;
1817 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1818 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1819 (32 - (lsb + width)));
1820 Inst.addOperand(MCOperand::createImm(Mask));
1823 void addImmOperands(MCInst &Inst, unsigned N) const {
1824 assert(N == 1 && "Invalid number of operands!");
1825 addExpr(Inst, getImm());
1828 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1829 assert(N == 1 && "Invalid number of operands!");
1830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1831 Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
1834 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1835 assert(N == 1 && "Invalid number of operands!");
1836 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1837 Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
1840 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1841 assert(N == 1 && "Invalid number of operands!");
1842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1843 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1844 Inst.addOperand(MCOperand::createImm(Val));
1847 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1848 assert(N == 1 && "Invalid number of operands!");
1849 // FIXME: We really want to scale the value here, but the LDRD/STRD
1850 // instruction don't encode operands that way yet.
1851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1852 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1855 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1856 assert(N == 1 && "Invalid number of operands!");
1857 // The immediate is scaled by four in the encoding and is stored
1858 // in the MCInst as such. Lop off the low two bits here.
1859 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1860 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1863 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1864 assert(N == 1 && "Invalid number of operands!");
1865 // The immediate is scaled by four in the encoding and is stored
1866 // in the MCInst as such. Lop off the low two bits here.
1867 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1868 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
1871 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1872 assert(N == 1 && "Invalid number of operands!");
1873 // The immediate is scaled by four in the encoding and is stored
1874 // in the MCInst as such. Lop off the low two bits here.
1875 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1876 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
1879 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1880 assert(N == 1 && "Invalid number of operands!");
1881 // The constant encodes as the immediate-1, and we store in the instruction
1882 // the bits as encoded, so subtract off one here.
1883 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1884 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1887 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1888 assert(N == 1 && "Invalid number of operands!");
1889 // The constant encodes as the immediate-1, and we store in the instruction
1890 // the bits as encoded, so subtract off one here.
1891 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1892 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
1895 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1896 assert(N == 1 && "Invalid number of operands!");
1897 // The constant encodes as the immediate, except for 32, which encodes as
1899 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1900 unsigned Imm = CE->getValue();
1901 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
1904 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1905 assert(N == 1 && "Invalid number of operands!");
1906 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1907 // the instruction as well.
1908 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1909 int Val = CE->getValue();
1910 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
1913 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1914 assert(N == 1 && "Invalid number of operands!");
1915 // The operand is actually a t2_so_imm, but we have its bitwise
1916 // negation in the assembly source, so twiddle it here.
1917 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1918 Inst.addOperand(MCOperand::createImm(~CE->getValue()));
1921 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1922 assert(N == 1 && "Invalid number of operands!");
1923 // The operand is actually a t2_so_imm, but we have its
1924 // negation in the assembly source, so twiddle it here.
1925 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1926 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
1929 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1930 assert(N == 1 && "Invalid number of operands!");
1931 // The operand is actually an imm0_4095, but we have its
1932 // negation in the assembly source, so twiddle it here.
1933 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1934 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
1937 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
1938 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
1939 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
1943 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1944 assert(SR && "Unknown value type!");
1945 Inst.addOperand(MCOperand::createExpr(SR));
1948 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
1949 assert(N == 1 && "Invalid number of operands!");
1951 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1953 Inst.addOperand(MCOperand::createImm(CE->getValue()));
1957 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
1958 assert(SR && "Unknown value type!");
1959 Inst.addOperand(MCOperand::createExpr(SR));
1963 assert(isMem() && "Unknown value type!");
1964 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
1965 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
1968 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
1969 assert(N == 1 && "Invalid number of operands!");
1970 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
1973 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
1974 assert(N == 1 && "Invalid number of operands!");
1975 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
1978 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
1979 assert(N == 1 && "Invalid number of operands!");
1980 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
1983 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
1984 assert(N == 1 && "Invalid number of operands!");
1985 int32_t Imm = Memory.OffsetImm->getValue();
1986 Inst.addOperand(MCOperand::createImm(Imm));
1989 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
1990 assert(N == 1 && "Invalid number of operands!");
1991 assert(isImm() && "Not an immediate!");
1993 // If we have an immediate that's not a constant, treat it as a label
1994 // reference needing a fixup.
1995 if (!isa<MCConstantExpr>(getImm())) {
1996 Inst.addOperand(MCOperand::createExpr(getImm()));
2000 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2001 int Val = CE->getValue();
2002 Inst.addOperand(MCOperand::createImm(Val));
2005 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2006 assert(N == 2 && "Invalid number of operands!");
2007 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2008 Inst.addOperand(MCOperand::createImm(Memory.Alignment));
2011 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2012 addAlignedMemoryOperands(Inst, N);
2015 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2016 addAlignedMemoryOperands(Inst, N);
2019 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2020 addAlignedMemoryOperands(Inst, N);
2023 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2024 addAlignedMemoryOperands(Inst, N);
2027 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2028 addAlignedMemoryOperands(Inst, N);
2031 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2032 addAlignedMemoryOperands(Inst, N);
2035 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2036 addAlignedMemoryOperands(Inst, N);
2039 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2040 addAlignedMemoryOperands(Inst, N);
2043 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2044 addAlignedMemoryOperands(Inst, N);
2047 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2048 addAlignedMemoryOperands(Inst, N);
2051 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2052 addAlignedMemoryOperands(Inst, N);
2055 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2056 assert(N == 3 && "Invalid number of operands!");
2057 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2058 if (!Memory.OffsetRegNum) {
2059 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2060 // Special case for #-0
2061 if (Val == INT32_MIN) Val = 0;
2062 if (Val < 0) Val = -Val;
2063 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2065 // For register offset, we encode the shift type and negation flag
2067 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2068 Memory.ShiftImm, Memory.ShiftType);
2070 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2071 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2072 Inst.addOperand(MCOperand::createImm(Val));
2075 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2076 assert(N == 2 && "Invalid number of operands!");
2077 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2078 assert(CE && "non-constant AM2OffsetImm operand!");
2079 int32_t Val = CE->getValue();
2080 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2081 // Special case for #-0
2082 if (Val == INT32_MIN) Val = 0;
2083 if (Val < 0) Val = -Val;
2084 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2085 Inst.addOperand(MCOperand::createReg(0));
2086 Inst.addOperand(MCOperand::createImm(Val));
2089 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2090 assert(N == 3 && "Invalid number of operands!");
2091 // If we have an immediate that's not a constant, treat it as a label
2092 // reference needing a fixup. If it is a constant, it's something else
2093 // and we reject it.
2095 Inst.addOperand(MCOperand::createExpr(getImm()));
2096 Inst.addOperand(MCOperand::createReg(0));
2097 Inst.addOperand(MCOperand::createImm(0));
2101 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2102 if (!Memory.OffsetRegNum) {
2103 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2104 // Special case for #-0
2105 if (Val == INT32_MIN) Val = 0;
2106 if (Val < 0) Val = -Val;
2107 Val = ARM_AM::getAM3Opc(AddSub, Val);
2109 // For register offset, we encode the shift type and negation flag
2111 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2113 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2114 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2115 Inst.addOperand(MCOperand::createImm(Val));
2118 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2119 assert(N == 2 && "Invalid number of operands!");
2120 if (Kind == k_PostIndexRegister) {
2122 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2123 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2124 Inst.addOperand(MCOperand::createImm(Val));
2129 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2130 int32_t Val = CE->getValue();
2131 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2132 // Special case for #-0
2133 if (Val == INT32_MIN) Val = 0;
2134 if (Val < 0) Val = -Val;
2135 Val = ARM_AM::getAM3Opc(AddSub, Val);
2136 Inst.addOperand(MCOperand::createReg(0));
2137 Inst.addOperand(MCOperand::createImm(Val));
2140 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2141 assert(N == 2 && "Invalid number of operands!");
2142 // If we have an immediate that's not a constant, treat it as a label
2143 // reference needing a fixup. If it is a constant, it's something else
2144 // and we reject it.
2146 Inst.addOperand(MCOperand::createExpr(getImm()));
2147 Inst.addOperand(MCOperand::createImm(0));
2151 // The lower two bits are always zero and as such are not encoded.
2152 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2153 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2154 // Special case for #-0
2155 if (Val == INT32_MIN) Val = 0;
2156 if (Val < 0) Val = -Val;
2157 Val = ARM_AM::getAM5Opc(AddSub, Val);
2158 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2159 Inst.addOperand(MCOperand::createImm(Val));
2162 void addAddrMode5FP16Operands(MCInst &Inst, unsigned N) const {
2163 assert(N == 2 && "Invalid number of operands!");
2164 // If we have an immediate that's not a constant, treat it as a label
2165 // reference needing a fixup. If it is a constant, it's something else
2166 // and we reject it.
2168 Inst.addOperand(MCOperand::createExpr(getImm()));
2169 Inst.addOperand(MCOperand::createImm(0));
2173 // The lower bit is always zero and as such is not encoded.
2174 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 2 : 0;
2175 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2176 // Special case for #-0
2177 if (Val == INT32_MIN) Val = 0;
2178 if (Val < 0) Val = -Val;
2179 Val = ARM_AM::getAM5FP16Opc(AddSub, Val);
2180 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2181 Inst.addOperand(MCOperand::createImm(Val));
2184 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2185 assert(N == 2 && "Invalid number of operands!");
2186 // If we have an immediate that's not a constant, treat it as a label
2187 // reference needing a fixup. If it is a constant, it's something else
2188 // and we reject it.
2190 Inst.addOperand(MCOperand::createExpr(getImm()));
2191 Inst.addOperand(MCOperand::createImm(0));
2195 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2196 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2197 Inst.addOperand(MCOperand::createImm(Val));
2200 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2201 assert(N == 2 && "Invalid number of operands!");
2202 // The lower two bits are always zero and as such are not encoded.
2203 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2204 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2205 Inst.addOperand(MCOperand::createImm(Val));
2208 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2209 assert(N == 2 && "Invalid number of operands!");
2210 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2211 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2212 Inst.addOperand(MCOperand::createImm(Val));
2215 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2216 addMemImm8OffsetOperands(Inst, N);
2219 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2220 addMemImm8OffsetOperands(Inst, N);
2223 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2224 assert(N == 2 && "Invalid number of operands!");
2225 // If this is an immediate, it's a label reference.
2227 addExpr(Inst, getImm());
2228 Inst.addOperand(MCOperand::createImm(0));
2232 // Otherwise, it's a normal memory reg+offset.
2233 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2234 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2235 Inst.addOperand(MCOperand::createImm(Val));
2238 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2239 assert(N == 2 && "Invalid number of operands!");
2240 // If this is an immediate, it's a label reference.
2242 addExpr(Inst, getImm());
2243 Inst.addOperand(MCOperand::createImm(0));
2247 // Otherwise, it's a normal memory reg+offset.
2248 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2249 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2250 Inst.addOperand(MCOperand::createImm(Val));
2253 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2254 assert(N == 2 && "Invalid number of operands!");
2255 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2256 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2259 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2260 assert(N == 2 && "Invalid number of operands!");
2261 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2262 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2265 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2266 assert(N == 3 && "Invalid number of operands!");
2268 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2269 Memory.ShiftImm, Memory.ShiftType);
2270 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2271 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2272 Inst.addOperand(MCOperand::createImm(Val));
2275 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2276 assert(N == 3 && "Invalid number of operands!");
2277 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2278 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2279 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
2282 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2283 assert(N == 2 && "Invalid number of operands!");
2284 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2285 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2288 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2289 assert(N == 2 && "Invalid number of operands!");
2290 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2291 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2292 Inst.addOperand(MCOperand::createImm(Val));
2295 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2296 assert(N == 2 && "Invalid number of operands!");
2297 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2298 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2299 Inst.addOperand(MCOperand::createImm(Val));
2302 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2303 assert(N == 2 && "Invalid number of operands!");
2304 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2305 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2306 Inst.addOperand(MCOperand::createImm(Val));
2309 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2310 assert(N == 2 && "Invalid number of operands!");
2311 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2312 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2313 Inst.addOperand(MCOperand::createImm(Val));
2316 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2317 assert(N == 1 && "Invalid number of operands!");
2318 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2319 assert(CE && "non-constant post-idx-imm8 operand!");
2320 int Imm = CE->getValue();
2321 bool isAdd = Imm >= 0;
2322 if (Imm == INT32_MIN) Imm = 0;
2323 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2324 Inst.addOperand(MCOperand::createImm(Imm));
2327 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2328 assert(N == 1 && "Invalid number of operands!");
2329 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2330 assert(CE && "non-constant post-idx-imm8s4 operand!");
2331 int Imm = CE->getValue();
2332 bool isAdd = Imm >= 0;
2333 if (Imm == INT32_MIN) Imm = 0;
2334 // Immediate is scaled by 4.
2335 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2336 Inst.addOperand(MCOperand::createImm(Imm));
2339 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2340 assert(N == 2 && "Invalid number of operands!");
2341 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2342 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
2345 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2346 assert(N == 2 && "Invalid number of operands!");
2347 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2348 // The sign, shift type, and shift amount are encoded in a single operand
2349 // using the AM2 encoding helpers.
2350 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2351 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2352 PostIdxReg.ShiftTy);
2353 Inst.addOperand(MCOperand::createImm(Imm));
2356 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2357 assert(N == 1 && "Invalid number of operands!");
2358 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
2361 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2362 assert(N == 1 && "Invalid number of operands!");
2363 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
2366 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2367 assert(N == 1 && "Invalid number of operands!");
2368 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
2371 void addVecListOperands(MCInst &Inst, unsigned N) const {
2372 assert(N == 1 && "Invalid number of operands!");
2373 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2376 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2377 assert(N == 2 && "Invalid number of operands!");
2378 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2379 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
2382 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2383 assert(N == 1 && "Invalid number of operands!");
2384 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2387 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2388 assert(N == 1 && "Invalid number of operands!");
2389 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2392 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2393 assert(N == 1 && "Invalid number of operands!");
2394 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
2397 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2398 assert(N == 1 && "Invalid number of operands!");
2399 // The immediate encodes the type of constant as well as the value.
2400 // Mask in that this is an i8 splat.
2401 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2402 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
2405 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2406 assert(N == 1 && "Invalid number of operands!");
2407 // The immediate encodes the type of constant as well as the value.
2408 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2409 unsigned Value = CE->getValue();
2410 Value = ARM_AM::encodeNEONi16splat(Value);
2411 Inst.addOperand(MCOperand::createImm(Value));
2414 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2415 assert(N == 1 && "Invalid number of operands!");
2416 // The immediate encodes the type of constant as well as the value.
2417 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2418 unsigned Value = CE->getValue();
2419 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2420 Inst.addOperand(MCOperand::createImm(Value));
2423 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2424 assert(N == 1 && "Invalid number of operands!");
2425 // The immediate encodes the type of constant as well as the value.
2426 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2427 unsigned Value = CE->getValue();
2428 Value = ARM_AM::encodeNEONi32splat(Value);
2429 Inst.addOperand(MCOperand::createImm(Value));
2432 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2433 assert(N == 1 && "Invalid number of operands!");
2434 // The immediate encodes the type of constant as well as the value.
2435 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2436 unsigned Value = CE->getValue();
2437 Value = ARM_AM::encodeNEONi32splat(~Value);
2438 Inst.addOperand(MCOperand::createImm(Value));
2441 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2442 assert(N == 1 && "Invalid number of operands!");
2443 // The immediate encodes the type of constant as well as the value.
2444 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2445 unsigned Value = CE->getValue();
2446 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2447 Inst.getOpcode() == ARM::VMOVv16i8) &&
2448 "All vmvn instructions that wants to replicate non-zero byte "
2449 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2450 unsigned B = ((~Value) & 0xff);
2451 B |= 0xe00; // cmode = 0b1110
2452 Inst.addOperand(MCOperand::createImm(B));
2454 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2455 assert(N == 1 && "Invalid number of operands!");
2456 // The immediate encodes the type of constant as well as the value.
2457 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2458 unsigned Value = CE->getValue();
2459 if (Value >= 256 && Value <= 0xffff)
2460 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2461 else if (Value > 0xffff && Value <= 0xffffff)
2462 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2463 else if (Value > 0xffffff)
2464 Value = (Value >> 24) | 0x600;
2465 Inst.addOperand(MCOperand::createImm(Value));
2468 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2469 assert(N == 1 && "Invalid number of operands!");
2470 // The immediate encodes the type of constant as well as the value.
2471 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2472 unsigned Value = CE->getValue();
2473 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2474 Inst.getOpcode() == ARM::VMOVv16i8) &&
2475 "All instructions that wants to replicate non-zero byte "
2476 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2477 unsigned B = Value & 0xff;
2478 B |= 0xe00; // cmode = 0b1110
2479 Inst.addOperand(MCOperand::createImm(B));
2481 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2482 assert(N == 1 && "Invalid number of operands!");
2483 // The immediate encodes the type of constant as well as the value.
2484 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2485 unsigned Value = ~CE->getValue();
2486 if (Value >= 256 && Value <= 0xffff)
2487 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2488 else if (Value > 0xffff && Value <= 0xffffff)
2489 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2490 else if (Value > 0xffffff)
2491 Value = (Value >> 24) | 0x600;
2492 Inst.addOperand(MCOperand::createImm(Value));
2495 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2496 assert(N == 1 && "Invalid number of operands!");
2497 // The immediate encodes the type of constant as well as the value.
2498 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2499 uint64_t Value = CE->getValue();
2501 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2502 Imm |= (Value & 1) << i;
2504 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
2507 void print(raw_ostream &OS) const override;
2509 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2510 auto Op = make_unique<ARMOperand>(k_ITCondMask);
2511 Op->ITMask.Mask = Mask;
2517 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2519 auto Op = make_unique<ARMOperand>(k_CondCode);
2526 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2527 auto Op = make_unique<ARMOperand>(k_CoprocNum);
2528 Op->Cop.Val = CopVal;
2534 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2535 auto Op = make_unique<ARMOperand>(k_CoprocReg);
2536 Op->Cop.Val = CopVal;
2542 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2544 auto Op = make_unique<ARMOperand>(k_CoprocOption);
2551 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2552 auto Op = make_unique<ARMOperand>(k_CCOut);
2553 Op->Reg.RegNum = RegNum;
2559 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2560 auto Op = make_unique<ARMOperand>(k_Token);
2561 Op->Tok.Data = Str.data();
2562 Op->Tok.Length = Str.size();
2568 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2570 auto Op = make_unique<ARMOperand>(k_Register);
2571 Op->Reg.RegNum = RegNum;
2577 static std::unique_ptr<ARMOperand>
2578 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2579 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2581 auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2582 Op->RegShiftedReg.ShiftTy = ShTy;
2583 Op->RegShiftedReg.SrcReg = SrcReg;
2584 Op->RegShiftedReg.ShiftReg = ShiftReg;
2585 Op->RegShiftedReg.ShiftImm = ShiftImm;
2591 static std::unique_ptr<ARMOperand>
2592 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2593 unsigned ShiftImm, SMLoc S, SMLoc E) {
2594 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2595 Op->RegShiftedImm.ShiftTy = ShTy;
2596 Op->RegShiftedImm.SrcReg = SrcReg;
2597 Op->RegShiftedImm.ShiftImm = ShiftImm;
2603 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2605 auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2606 Op->ShifterImm.isASR = isASR;
2607 Op->ShifterImm.Imm = Imm;
2613 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2615 auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2616 Op->RotImm.Imm = Imm;
2622 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2624 auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2625 Op->ModImm.Bits = Bits;
2626 Op->ModImm.Rot = Rot;
2632 static std::unique_ptr<ARMOperand>
2633 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2634 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2635 Op->Bitfield.LSB = LSB;
2636 Op->Bitfield.Width = Width;
2642 static std::unique_ptr<ARMOperand>
2643 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2644 SMLoc StartLoc, SMLoc EndLoc) {
2645 assert (Regs.size() > 0 && "RegList contains no registers?");
2646 KindTy Kind = k_RegisterList;
2648 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2649 Kind = k_DPRRegisterList;
2650 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2651 contains(Regs.front().second))
2652 Kind = k_SPRRegisterList;
2654 // Sort based on the register encoding values.
2655 array_pod_sort(Regs.begin(), Regs.end());
2657 auto Op = make_unique<ARMOperand>(Kind);
2658 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2659 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2660 Op->Registers.push_back(I->second);
2661 Op->StartLoc = StartLoc;
2662 Op->EndLoc = EndLoc;
2666 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2668 bool isDoubleSpaced,
2670 auto Op = make_unique<ARMOperand>(k_VectorList);
2671 Op->VectorList.RegNum = RegNum;
2672 Op->VectorList.Count = Count;
2673 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2679 static std::unique_ptr<ARMOperand>
2680 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2682 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2683 Op->VectorList.RegNum = RegNum;
2684 Op->VectorList.Count = Count;
2685 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2691 static std::unique_ptr<ARMOperand>
2692 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2693 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2694 auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2695 Op->VectorList.RegNum = RegNum;
2696 Op->VectorList.Count = Count;
2697 Op->VectorList.LaneIndex = Index;
2698 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2704 static std::unique_ptr<ARMOperand>
2705 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2706 auto Op = make_unique<ARMOperand>(k_VectorIndex);
2707 Op->VectorIndex.Val = Idx;
2713 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2715 auto Op = make_unique<ARMOperand>(k_Immediate);
2722 static std::unique_ptr<ARMOperand>
2723 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2724 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2725 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2726 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2727 auto Op = make_unique<ARMOperand>(k_Memory);
2728 Op->Memory.BaseRegNum = BaseRegNum;
2729 Op->Memory.OffsetImm = OffsetImm;
2730 Op->Memory.OffsetRegNum = OffsetRegNum;
2731 Op->Memory.ShiftType = ShiftType;
2732 Op->Memory.ShiftImm = ShiftImm;
2733 Op->Memory.Alignment = Alignment;
2734 Op->Memory.isNegative = isNegative;
2737 Op->AlignmentLoc = AlignmentLoc;
2741 static std::unique_ptr<ARMOperand>
2742 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2743 unsigned ShiftImm, SMLoc S, SMLoc E) {
2744 auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2745 Op->PostIdxReg.RegNum = RegNum;
2746 Op->PostIdxReg.isAdd = isAdd;
2747 Op->PostIdxReg.ShiftTy = ShiftTy;
2748 Op->PostIdxReg.ShiftImm = ShiftImm;
2754 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2756 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2757 Op->MBOpt.Val = Opt;
2763 static std::unique_ptr<ARMOperand>
2764 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2765 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2766 Op->ISBOpt.Val = Opt;
2772 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2774 auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2775 Op->IFlags.Val = IFlags;
2781 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2782 auto Op = make_unique<ARMOperand>(k_MSRMask);
2783 Op->MMask.Val = MMask;
2789 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2790 auto Op = make_unique<ARMOperand>(k_BankedReg);
2791 Op->BankedReg.Val = Reg;
2798 } // end anonymous namespace.
2800 void ARMOperand::print(raw_ostream &OS) const {
2803 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2806 OS << "<ccout " << getReg() << ">";
2808 case k_ITCondMask: {
2809 static const char *const MaskStr[] = {
2810 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2811 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2813 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2814 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2818 OS << "<coprocessor number: " << getCoproc() << ">";
2821 OS << "<coprocessor register: " << getCoproc() << ">";
2823 case k_CoprocOption:
2824 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2827 OS << "<mask: " << getMSRMask() << ">";
2830 OS << "<banked reg: " << getBankedReg() << ">";
2835 case k_MemBarrierOpt:
2836 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2838 case k_InstSyncBarrierOpt:
2839 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2843 << " base:" << Memory.BaseRegNum;
2846 case k_PostIndexRegister:
2847 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2848 << PostIdxReg.RegNum;
2849 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2850 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2851 << PostIdxReg.ShiftImm;
2854 case k_ProcIFlags: {
2855 OS << "<ARM_PROC::";
2856 unsigned IFlags = getProcIFlags();
2857 for (int i=2; i >= 0; --i)
2858 if (IFlags & (1 << i))
2859 OS << ARM_PROC::IFlagsToString(1 << i);
2864 OS << "<register " << getReg() << ">";
2866 case k_ShifterImmediate:
2867 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2868 << " #" << ShifterImm.Imm << ">";
2870 case k_ShiftedRegister:
2871 OS << "<so_reg_reg "
2872 << RegShiftedReg.SrcReg << " "
2873 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2874 << " " << RegShiftedReg.ShiftReg << ">";
2876 case k_ShiftedImmediate:
2877 OS << "<so_reg_imm "
2878 << RegShiftedImm.SrcReg << " "
2879 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2880 << " #" << RegShiftedImm.ShiftImm << ">";
2882 case k_RotateImmediate:
2883 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2885 case k_ModifiedImmediate:
2886 OS << "<mod_imm #" << ModImm.Bits << ", #"
2887 << ModImm.Rot << ")>";
2889 case k_BitfieldDescriptor:
2890 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2891 << ", width: " << Bitfield.Width << ">";
2893 case k_RegisterList:
2894 case k_DPRRegisterList:
2895 case k_SPRRegisterList: {
2896 OS << "<register_list ";
2898 const SmallVectorImpl<unsigned> &RegList = getRegList();
2899 for (SmallVectorImpl<unsigned>::const_iterator
2900 I = RegList.begin(), E = RegList.end(); I != E; ) {
2902 if (++I < E) OS << ", ";
2909 OS << "<vector_list " << VectorList.Count << " * "
2910 << VectorList.RegNum << ">";
2912 case k_VectorListAllLanes:
2913 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2914 << VectorList.RegNum << ">";
2916 case k_VectorListIndexed:
2917 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2918 << VectorList.Count << " * " << VectorList.RegNum << ">";
2921 OS << "'" << getToken() << "'";
2924 OS << "<vectorindex " << getVectorIndex() << ">";
2929 /// @name Auto-generated Match Functions
2932 static unsigned MatchRegisterName(StringRef Name);
2936 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2937 SMLoc &StartLoc, SMLoc &EndLoc) {
2938 const AsmToken &Tok = getParser().getTok();
2939 StartLoc = Tok.getLoc();
2940 EndLoc = Tok.getEndLoc();
2941 RegNo = tryParseRegister();
2943 return (RegNo == (unsigned)-1);
2946 /// Try to parse a register name. The token must be an Identifier when called,
2947 /// and if it is a register name the token is eaten and the register number is
2948 /// returned. Otherwise return -1.
2950 int ARMAsmParser::tryParseRegister() {
2951 MCAsmParser &Parser = getParser();
2952 const AsmToken &Tok = Parser.getTok();
2953 if (Tok.isNot(AsmToken::Identifier)) return -1;
2955 std::string lowerCase = Tok.getString().lower();
2956 unsigned RegNum = MatchRegisterName(lowerCase);
2958 RegNum = StringSwitch<unsigned>(lowerCase)
2959 .Case("r13", ARM::SP)
2960 .Case("r14", ARM::LR)
2961 .Case("r15", ARM::PC)
2962 .Case("ip", ARM::R12)
2963 // Additional register name aliases for 'gas' compatibility.
2964 .Case("a1", ARM::R0)
2965 .Case("a2", ARM::R1)
2966 .Case("a3", ARM::R2)
2967 .Case("a4", ARM::R3)
2968 .Case("v1", ARM::R4)
2969 .Case("v2", ARM::R5)
2970 .Case("v3", ARM::R6)
2971 .Case("v4", ARM::R7)
2972 .Case("v5", ARM::R8)
2973 .Case("v6", ARM::R9)
2974 .Case("v7", ARM::R10)
2975 .Case("v8", ARM::R11)
2976 .Case("sb", ARM::R9)
2977 .Case("sl", ARM::R10)
2978 .Case("fp", ARM::R11)
2982 // Check for aliases registered via .req. Canonicalize to lower case.
2983 // That's more consistent since register names are case insensitive, and
2984 // it's how the original entry was passed in from MC/MCParser/AsmParser.
2985 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
2986 // If no match, return failure.
2987 if (Entry == RegisterReqs.end())
2989 Parser.Lex(); // Eat identifier token.
2990 return Entry->getValue();
2993 // Some FPUs only have 16 D registers, so D16-D31 are invalid
2994 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
2997 Parser.Lex(); // Eat identifier token.
3002 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3003 // If a recoverable error occurs, return 1. If an irrecoverable error
3004 // occurs, return -1. An irrecoverable error is one where tokens have been
3005 // consumed in the process of trying to parse the shifter (i.e., when it is
3006 // indeed a shifter operand, but malformed).
3007 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3008 MCAsmParser &Parser = getParser();
3009 SMLoc S = Parser.getTok().getLoc();
3010 const AsmToken &Tok = Parser.getTok();
3011 if (Tok.isNot(AsmToken::Identifier))
3014 std::string lowerCase = Tok.getString().lower();
3015 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3016 .Case("asl", ARM_AM::lsl)
3017 .Case("lsl", ARM_AM::lsl)
3018 .Case("lsr", ARM_AM::lsr)
3019 .Case("asr", ARM_AM::asr)
3020 .Case("ror", ARM_AM::ror)
3021 .Case("rrx", ARM_AM::rrx)
3022 .Default(ARM_AM::no_shift);
3024 if (ShiftTy == ARM_AM::no_shift)
3027 Parser.Lex(); // Eat the operator.
3029 // The source register for the shift has already been added to the
3030 // operand list, so we need to pop it off and combine it into the shifted
3031 // register operand instead.
3032 std::unique_ptr<ARMOperand> PrevOp(
3033 (ARMOperand *)Operands.pop_back_val().release());
3034 if (!PrevOp->isReg())
3035 return Error(PrevOp->getStartLoc(), "shift must be of a register");
3036 int SrcReg = PrevOp->getReg();
3041 if (ShiftTy == ARM_AM::rrx) {
3042 // RRX Doesn't have an explicit shift amount. The encoder expects
3043 // the shift register to be the same as the source register. Seems odd,
3047 // Figure out if this is shifted by a constant or a register (for non-RRX).
3048 if (Parser.getTok().is(AsmToken::Hash) ||
3049 Parser.getTok().is(AsmToken::Dollar)) {
3050 Parser.Lex(); // Eat hash.
3051 SMLoc ImmLoc = Parser.getTok().getLoc();
3052 const MCExpr *ShiftExpr = nullptr;
3053 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3054 Error(ImmLoc, "invalid immediate shift value");
3057 // The expression must be evaluatable as an immediate.
3058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3060 Error(ImmLoc, "invalid immediate shift value");
3063 // Range check the immediate.
3064 // lsl, ror: 0 <= imm <= 31
3065 // lsr, asr: 0 <= imm <= 32
3066 Imm = CE->getValue();
3068 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3069 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3070 Error(ImmLoc, "immediate shift value out of range");
3073 // shift by zero is a nop. Always send it through as lsl.
3074 // ('as' compatibility)
3076 ShiftTy = ARM_AM::lsl;
3077 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3078 SMLoc L = Parser.getTok().getLoc();
3079 EndLoc = Parser.getTok().getEndLoc();
3080 ShiftReg = tryParseRegister();
3081 if (ShiftReg == -1) {
3082 Error(L, "expected immediate or register in shift operand");
3086 Error(Parser.getTok().getLoc(),
3087 "expected immediate or register in shift operand");
3092 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3093 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3097 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3104 /// Try to parse a register name. The token must be an Identifier when called.
3105 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3106 /// if there is a "writeback". 'true' if it's not a register.
3108 /// TODO this is likely to change to allow different register types and or to
3109 /// parse for a specific register type.
3110 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3111 MCAsmParser &Parser = getParser();
3112 const AsmToken &RegTok = Parser.getTok();
3113 int RegNo = tryParseRegister();
3117 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3118 RegTok.getEndLoc()));
3120 const AsmToken &ExclaimTok = Parser.getTok();
3121 if (ExclaimTok.is(AsmToken::Exclaim)) {
3122 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3123 ExclaimTok.getLoc()));
3124 Parser.Lex(); // Eat exclaim token
3128 // Also check for an index operand. This is only legal for vector registers,
3129 // but that'll get caught OK in operand matching, so we don't need to
3130 // explicitly filter everything else out here.
3131 if (Parser.getTok().is(AsmToken::LBrac)) {
3132 SMLoc SIdx = Parser.getTok().getLoc();
3133 Parser.Lex(); // Eat left bracket token.
3135 const MCExpr *ImmVal;
3136 if (getParser().parseExpression(ImmVal))
3138 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3140 return TokError("immediate value expected for vector index");
3142 if (Parser.getTok().isNot(AsmToken::RBrac))
3143 return Error(Parser.getTok().getLoc(), "']' expected");
3145 SMLoc E = Parser.getTok().getEndLoc();
3146 Parser.Lex(); // Eat right bracket token.
3148 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3156 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3157 /// instruction with a symbolic operand name.
3158 /// We accept "crN" syntax for GAS compatibility.
3159 /// <operand-name> ::= <prefix><number>
3160 /// If CoprocOp is 'c', then:
3161 /// <prefix> ::= c | cr
3162 /// If CoprocOp is 'p', then :
3164 /// <number> ::= integer in range [0, 15]
3165 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3166 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3168 if (Name.size() < 2 || Name[0] != CoprocOp)
3170 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3172 switch (Name.size()) {
3193 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3194 // However, old cores (v5/v6) did use them in that way.
3195 case '0': return 10;
3196 case '1': return 11;
3197 case '2': return 12;
3198 case '3': return 13;
3199 case '4': return 14;
3200 case '5': return 15;
3205 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3206 ARMAsmParser::OperandMatchResultTy
3207 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3208 MCAsmParser &Parser = getParser();
3209 SMLoc S = Parser.getTok().getLoc();
3210 const AsmToken &Tok = Parser.getTok();
3211 if (!Tok.is(AsmToken::Identifier))
3212 return MatchOperand_NoMatch;
3213 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3214 .Case("eq", ARMCC::EQ)
3215 .Case("ne", ARMCC::NE)
3216 .Case("hs", ARMCC::HS)
3217 .Case("cs", ARMCC::HS)
3218 .Case("lo", ARMCC::LO)
3219 .Case("cc", ARMCC::LO)
3220 .Case("mi", ARMCC::MI)
3221 .Case("pl", ARMCC::PL)
3222 .Case("vs", ARMCC::VS)
3223 .Case("vc", ARMCC::VC)
3224 .Case("hi", ARMCC::HI)
3225 .Case("ls", ARMCC::LS)
3226 .Case("ge", ARMCC::GE)
3227 .Case("lt", ARMCC::LT)
3228 .Case("gt", ARMCC::GT)
3229 .Case("le", ARMCC::LE)
3230 .Case("al", ARMCC::AL)
3233 return MatchOperand_NoMatch;
3234 Parser.Lex(); // Eat the token.
3236 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3238 return MatchOperand_Success;
3241 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3242 /// token must be an Identifier when called, and if it is a coprocessor
3243 /// number, the token is eaten and the operand is added to the operand list.
3244 ARMAsmParser::OperandMatchResultTy
3245 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3246 MCAsmParser &Parser = getParser();
3247 SMLoc S = Parser.getTok().getLoc();
3248 const AsmToken &Tok = Parser.getTok();
3249 if (Tok.isNot(AsmToken::Identifier))
3250 return MatchOperand_NoMatch;
3252 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3254 return MatchOperand_NoMatch;
3255 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3256 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3257 return MatchOperand_NoMatch;
3259 Parser.Lex(); // Eat identifier token.
3260 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3261 return MatchOperand_Success;
3264 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3265 /// token must be an Identifier when called, and if it is a coprocessor
3266 /// number, the token is eaten and the operand is added to the operand list.
3267 ARMAsmParser::OperandMatchResultTy
3268 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3269 MCAsmParser &Parser = getParser();
3270 SMLoc S = Parser.getTok().getLoc();
3271 const AsmToken &Tok = Parser.getTok();
3272 if (Tok.isNot(AsmToken::Identifier))
3273 return MatchOperand_NoMatch;
3275 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3277 return MatchOperand_NoMatch;
3279 Parser.Lex(); // Eat identifier token.
3280 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3281 return MatchOperand_Success;
3284 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3285 /// coproc_option : '{' imm0_255 '}'
3286 ARMAsmParser::OperandMatchResultTy
3287 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3288 MCAsmParser &Parser = getParser();
3289 SMLoc S = Parser.getTok().getLoc();
3291 // If this isn't a '{', this isn't a coprocessor immediate operand.
3292 if (Parser.getTok().isNot(AsmToken::LCurly))
3293 return MatchOperand_NoMatch;
3294 Parser.Lex(); // Eat the '{'
3297 SMLoc Loc = Parser.getTok().getLoc();
3298 if (getParser().parseExpression(Expr)) {
3299 Error(Loc, "illegal expression");
3300 return MatchOperand_ParseFail;
3302 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3303 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3304 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3305 return MatchOperand_ParseFail;
3307 int Val = CE->getValue();
3309 // Check for and consume the closing '}'
3310 if (Parser.getTok().isNot(AsmToken::RCurly))
3311 return MatchOperand_ParseFail;
3312 SMLoc E = Parser.getTok().getEndLoc();
3313 Parser.Lex(); // Eat the '}'
3315 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3316 return MatchOperand_Success;
3319 // For register list parsing, we need to map from raw GPR register numbering
3320 // to the enumeration values. The enumeration values aren't sorted by
3321 // register number due to our using "sp", "lr" and "pc" as canonical names.
3322 static unsigned getNextRegister(unsigned Reg) {
3323 // If this is a GPR, we need to do it manually, otherwise we can rely
3324 // on the sort ordering of the enumeration since the other reg-classes
3326 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3329 default: llvm_unreachable("Invalid GPR number!");
3330 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3331 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3332 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3333 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3334 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3335 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3336 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3337 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3341 // Return the low-subreg of a given Q register.
3342 static unsigned getDRegFromQReg(unsigned QReg) {
3344 default: llvm_unreachable("expected a Q register!");
3345 case ARM::Q0: return ARM::D0;
3346 case ARM::Q1: return ARM::D2;
3347 case ARM::Q2: return ARM::D4;
3348 case ARM::Q3: return ARM::D6;
3349 case ARM::Q4: return ARM::D8;
3350 case ARM::Q5: return ARM::D10;
3351 case ARM::Q6: return ARM::D12;
3352 case ARM::Q7: return ARM::D14;
3353 case ARM::Q8: return ARM::D16;
3354 case ARM::Q9: return ARM::D18;
3355 case ARM::Q10: return ARM::D20;
3356 case ARM::Q11: return ARM::D22;
3357 case ARM::Q12: return ARM::D24;
3358 case ARM::Q13: return ARM::D26;
3359 case ARM::Q14: return ARM::D28;
3360 case ARM::Q15: return ARM::D30;
3364 /// Parse a register list.
3365 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3366 MCAsmParser &Parser = getParser();
3367 assert(Parser.getTok().is(AsmToken::LCurly) &&
3368 "Token is not a Left Curly Brace");
3369 SMLoc S = Parser.getTok().getLoc();
3370 Parser.Lex(); // Eat '{' token.
3371 SMLoc RegLoc = Parser.getTok().getLoc();
3373 // Check the first register in the list to see what register class
3374 // this is a list of.
3375 int Reg = tryParseRegister();
3377 return Error(RegLoc, "register expected");
3379 // The reglist instructions have at most 16 registers, so reserve
3380 // space for that many.
3382 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3384 // Allow Q regs and just interpret them as the two D sub-registers.
3385 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3386 Reg = getDRegFromQReg(Reg);
3387 EReg = MRI->getEncodingValue(Reg);
3388 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3391 const MCRegisterClass *RC;
3392 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3393 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3394 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3395 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3396 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3397 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3399 return Error(RegLoc, "invalid register in register list");
3401 // Store the register.
3402 EReg = MRI->getEncodingValue(Reg);
3403 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3405 // This starts immediately after the first register token in the list,
3406 // so we can see either a comma or a minus (range separator) as a legal
3408 while (Parser.getTok().is(AsmToken::Comma) ||
3409 Parser.getTok().is(AsmToken::Minus)) {
3410 if (Parser.getTok().is(AsmToken::Minus)) {
3411 Parser.Lex(); // Eat the minus.
3412 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3413 int EndReg = tryParseRegister();
3415 return Error(AfterMinusLoc, "register expected");
3416 // Allow Q regs and just interpret them as the two D sub-registers.
3417 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3418 EndReg = getDRegFromQReg(EndReg) + 1;
3419 // If the register is the same as the start reg, there's nothing
3423 // The register must be in the same register class as the first.
3424 if (!RC->contains(EndReg))
3425 return Error(AfterMinusLoc, "invalid register in register list");
3426 // Ranges must go from low to high.
3427 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3428 return Error(AfterMinusLoc, "bad range in register list");
3430 // Add all the registers in the range to the register list.
3431 while (Reg != EndReg) {
3432 Reg = getNextRegister(Reg);
3433 EReg = MRI->getEncodingValue(Reg);
3434 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3438 Parser.Lex(); // Eat the comma.
3439 RegLoc = Parser.getTok().getLoc();
3441 const AsmToken RegTok = Parser.getTok();
3442 Reg = tryParseRegister();
3444 return Error(RegLoc, "register expected");
3445 // Allow Q regs and just interpret them as the two D sub-registers.
3446 bool isQReg = false;
3447 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3448 Reg = getDRegFromQReg(Reg);
3451 // The register must be in the same register class as the first.
3452 if (!RC->contains(Reg))
3453 return Error(RegLoc, "invalid register in register list");
3454 // List must be monotonically increasing.
3455 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3456 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3457 Warning(RegLoc, "register list not in ascending order");
3459 return Error(RegLoc, "register list not in ascending order");
3461 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3462 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3463 ") in register list");
3466 // VFP register lists must also be contiguous.
3467 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3469 return Error(RegLoc, "non-contiguous register range");
3470 EReg = MRI->getEncodingValue(Reg);
3471 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3473 EReg = MRI->getEncodingValue(++Reg);
3474 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3478 if (Parser.getTok().isNot(AsmToken::RCurly))
3479 return Error(Parser.getTok().getLoc(), "'}' expected");
3480 SMLoc E = Parser.getTok().getEndLoc();
3481 Parser.Lex(); // Eat '}' token.
3483 // Push the register list operand.
3484 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3486 // The ARM system instruction variants for LDM/STM have a '^' token here.
3487 if (Parser.getTok().is(AsmToken::Caret)) {
3488 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3489 Parser.Lex(); // Eat '^' token.
3495 // Helper function to parse the lane index for vector lists.
3496 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3497 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3498 MCAsmParser &Parser = getParser();
3499 Index = 0; // Always return a defined index value.
3500 if (Parser.getTok().is(AsmToken::LBrac)) {
3501 Parser.Lex(); // Eat the '['.
3502 if (Parser.getTok().is(AsmToken::RBrac)) {
3503 // "Dn[]" is the 'all lanes' syntax.
3504 LaneKind = AllLanes;
3505 EndLoc = Parser.getTok().getEndLoc();
3506 Parser.Lex(); // Eat the ']'.
3507 return MatchOperand_Success;
3510 // There's an optional '#' token here. Normally there wouldn't be, but
3511 // inline assemble puts one in, and it's friendly to accept that.
3512 if (Parser.getTok().is(AsmToken::Hash))
3513 Parser.Lex(); // Eat '#' or '$'.
3515 const MCExpr *LaneIndex;
3516 SMLoc Loc = Parser.getTok().getLoc();
3517 if (getParser().parseExpression(LaneIndex)) {
3518 Error(Loc, "illegal expression");
3519 return MatchOperand_ParseFail;
3521 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3523 Error(Loc, "lane index must be empty or an integer");
3524 return MatchOperand_ParseFail;
3526 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3527 Error(Parser.getTok().getLoc(), "']' expected");
3528 return MatchOperand_ParseFail;
3530 EndLoc = Parser.getTok().getEndLoc();
3531 Parser.Lex(); // Eat the ']'.
3532 int64_t Val = CE->getValue();
3534 // FIXME: Make this range check context sensitive for .8, .16, .32.
3535 if (Val < 0 || Val > 7) {
3536 Error(Parser.getTok().getLoc(), "lane index out of range");
3537 return MatchOperand_ParseFail;
3540 LaneKind = IndexedLane;
3541 return MatchOperand_Success;
3544 return MatchOperand_Success;
3547 // parse a vector register list
3548 ARMAsmParser::OperandMatchResultTy
3549 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3550 MCAsmParser &Parser = getParser();
3551 VectorLaneTy LaneKind;
3553 SMLoc S = Parser.getTok().getLoc();
3554 // As an extension (to match gas), support a plain D register or Q register
3555 // (without encosing curly braces) as a single or double entry list,
3557 if (Parser.getTok().is(AsmToken::Identifier)) {
3558 SMLoc E = Parser.getTok().getEndLoc();
3559 int Reg = tryParseRegister();
3561 return MatchOperand_NoMatch;
3562 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3563 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3564 if (Res != MatchOperand_Success)
3568 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3571 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3575 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3580 return MatchOperand_Success;
3582 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3583 Reg = getDRegFromQReg(Reg);
3584 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3585 if (Res != MatchOperand_Success)
3589 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3590 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3591 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3594 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3595 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3596 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3600 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3605 return MatchOperand_Success;
3607 Error(S, "vector register expected");
3608 return MatchOperand_ParseFail;
3611 if (Parser.getTok().isNot(AsmToken::LCurly))
3612 return MatchOperand_NoMatch;
3614 Parser.Lex(); // Eat '{' token.
3615 SMLoc RegLoc = Parser.getTok().getLoc();
3617 int Reg = tryParseRegister();
3619 Error(RegLoc, "register expected");
3620 return MatchOperand_ParseFail;
3624 unsigned FirstReg = Reg;
3625 // The list is of D registers, but we also allow Q regs and just interpret
3626 // them as the two D sub-registers.
3627 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3628 FirstReg = Reg = getDRegFromQReg(Reg);
3629 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3630 // it's ambiguous with four-register single spaced.
3636 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3637 return MatchOperand_ParseFail;
3639 while (Parser.getTok().is(AsmToken::Comma) ||
3640 Parser.getTok().is(AsmToken::Minus)) {
3641 if (Parser.getTok().is(AsmToken::Minus)) {
3643 Spacing = 1; // Register range implies a single spaced list.
3644 else if (Spacing == 2) {
3645 Error(Parser.getTok().getLoc(),
3646 "sequential registers in double spaced list");
3647 return MatchOperand_ParseFail;
3649 Parser.Lex(); // Eat the minus.
3650 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3651 int EndReg = tryParseRegister();
3653 Error(AfterMinusLoc, "register expected");
3654 return MatchOperand_ParseFail;
3656 // Allow Q regs and just interpret them as the two D sub-registers.
3657 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3658 EndReg = getDRegFromQReg(EndReg) + 1;
3659 // If the register is the same as the start reg, there's nothing
3663 // The register must be in the same register class as the first.
3664 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3665 Error(AfterMinusLoc, "invalid register in register list");
3666 return MatchOperand_ParseFail;
3668 // Ranges must go from low to high.
3670 Error(AfterMinusLoc, "bad range in register list");
3671 return MatchOperand_ParseFail;
3673 // Parse the lane specifier if present.
3674 VectorLaneTy NextLaneKind;
3675 unsigned NextLaneIndex;
3676 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3677 MatchOperand_Success)
3678 return MatchOperand_ParseFail;
3679 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3680 Error(AfterMinusLoc, "mismatched lane index in register list");
3681 return MatchOperand_ParseFail;
3684 // Add all the registers in the range to the register list.
3685 Count += EndReg - Reg;
3689 Parser.Lex(); // Eat the comma.
3690 RegLoc = Parser.getTok().getLoc();
3692 Reg = tryParseRegister();
3694 Error(RegLoc, "register expected");
3695 return MatchOperand_ParseFail;
3697 // vector register lists must be contiguous.
3698 // It's OK to use the enumeration values directly here rather, as the
3699 // VFP register classes have the enum sorted properly.
3701 // The list is of D registers, but we also allow Q regs and just interpret
3702 // them as the two D sub-registers.
3703 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3705 Spacing = 1; // Register range implies a single spaced list.
3706 else if (Spacing == 2) {
3708 "invalid register in double-spaced list (must be 'D' register')");
3709 return MatchOperand_ParseFail;
3711 Reg = getDRegFromQReg(Reg);
3712 if (Reg != OldReg + 1) {
3713 Error(RegLoc, "non-contiguous register range");
3714 return MatchOperand_ParseFail;
3718 // Parse the lane specifier if present.
3719 VectorLaneTy NextLaneKind;
3720 unsigned NextLaneIndex;
3721 SMLoc LaneLoc = Parser.getTok().getLoc();
3722 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3723 MatchOperand_Success)
3724 return MatchOperand_ParseFail;
3725 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3726 Error(LaneLoc, "mismatched lane index in register list");
3727 return MatchOperand_ParseFail;
3731 // Normal D register.
3732 // Figure out the register spacing (single or double) of the list if
3733 // we don't know it already.
3735 Spacing = 1 + (Reg == OldReg + 2);
3737 // Just check that it's contiguous and keep going.
3738 if (Reg != OldReg + Spacing) {
3739 Error(RegLoc, "non-contiguous register range");
3740 return MatchOperand_ParseFail;
3743 // Parse the lane specifier if present.
3744 VectorLaneTy NextLaneKind;
3745 unsigned NextLaneIndex;
3746 SMLoc EndLoc = Parser.getTok().getLoc();
3747 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3748 return MatchOperand_ParseFail;
3749 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3750 Error(EndLoc, "mismatched lane index in register list");
3751 return MatchOperand_ParseFail;
3755 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3756 Error(Parser.getTok().getLoc(), "'}' expected");
3757 return MatchOperand_ParseFail;
3759 E = Parser.getTok().getEndLoc();
3760 Parser.Lex(); // Eat '}' token.
3764 // Two-register operands have been converted to the
3765 // composite register classes.
3767 const MCRegisterClass *RC = (Spacing == 1) ?
3768 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3769 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3770 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3773 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3774 (Spacing == 2), S, E));
3777 // Two-register operands have been converted to the
3778 // composite register classes.
3780 const MCRegisterClass *RC = (Spacing == 1) ?
3781 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3782 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3783 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3785 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3790 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3796 return MatchOperand_Success;
3799 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3800 ARMAsmParser::OperandMatchResultTy
3801 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3802 MCAsmParser &Parser = getParser();
3803 SMLoc S = Parser.getTok().getLoc();
3804 const AsmToken &Tok = Parser.getTok();
3807 if (Tok.is(AsmToken::Identifier)) {
3808 StringRef OptStr = Tok.getString();
3810 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3811 .Case("sy", ARM_MB::SY)
3812 .Case("st", ARM_MB::ST)
3813 .Case("ld", ARM_MB::LD)
3814 .Case("sh", ARM_MB::ISH)
3815 .Case("ish", ARM_MB::ISH)
3816 .Case("shst", ARM_MB::ISHST)
3817 .Case("ishst", ARM_MB::ISHST)
3818 .Case("ishld", ARM_MB::ISHLD)
3819 .Case("nsh", ARM_MB::NSH)
3820 .Case("un", ARM_MB::NSH)
3821 .Case("nshst", ARM_MB::NSHST)
3822 .Case("nshld", ARM_MB::NSHLD)
3823 .Case("unst", ARM_MB::NSHST)
3824 .Case("osh", ARM_MB::OSH)
3825 .Case("oshst", ARM_MB::OSHST)
3826 .Case("oshld", ARM_MB::OSHLD)
3829 // ishld, oshld, nshld and ld are only available from ARMv8.
3830 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3831 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3835 return MatchOperand_NoMatch;
3837 Parser.Lex(); // Eat identifier token.
3838 } else if (Tok.is(AsmToken::Hash) ||
3839 Tok.is(AsmToken::Dollar) ||
3840 Tok.is(AsmToken::Integer)) {
3841 if (Parser.getTok().isNot(AsmToken::Integer))
3842 Parser.Lex(); // Eat '#' or '$'.
3843 SMLoc Loc = Parser.getTok().getLoc();
3845 const MCExpr *MemBarrierID;
3846 if (getParser().parseExpression(MemBarrierID)) {
3847 Error(Loc, "illegal expression");
3848 return MatchOperand_ParseFail;
3851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3853 Error(Loc, "constant expression expected");
3854 return MatchOperand_ParseFail;
3857 int Val = CE->getValue();
3859 Error(Loc, "immediate value out of range");
3860 return MatchOperand_ParseFail;
3863 Opt = ARM_MB::RESERVED_0 + Val;
3865 return MatchOperand_ParseFail;
3867 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3868 return MatchOperand_Success;
3871 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3872 ARMAsmParser::OperandMatchResultTy
3873 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3874 MCAsmParser &Parser = getParser();
3875 SMLoc S = Parser.getTok().getLoc();
3876 const AsmToken &Tok = Parser.getTok();
3879 if (Tok.is(AsmToken::Identifier)) {
3880 StringRef OptStr = Tok.getString();
3882 if (OptStr.equals_lower("sy"))
3885 return MatchOperand_NoMatch;
3887 Parser.Lex(); // Eat identifier token.
3888 } else if (Tok.is(AsmToken::Hash) ||
3889 Tok.is(AsmToken::Dollar) ||
3890 Tok.is(AsmToken::Integer)) {
3891 if (Parser.getTok().isNot(AsmToken::Integer))
3892 Parser.Lex(); // Eat '#' or '$'.
3893 SMLoc Loc = Parser.getTok().getLoc();
3895 const MCExpr *ISBarrierID;
3896 if (getParser().parseExpression(ISBarrierID)) {
3897 Error(Loc, "illegal expression");
3898 return MatchOperand_ParseFail;
3901 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3903 Error(Loc, "constant expression expected");
3904 return MatchOperand_ParseFail;
3907 int Val = CE->getValue();
3909 Error(Loc, "immediate value out of range");
3910 return MatchOperand_ParseFail;
3913 Opt = ARM_ISB::RESERVED_0 + Val;
3915 return MatchOperand_ParseFail;
3917 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3918 (ARM_ISB::InstSyncBOpt)Opt, S));
3919 return MatchOperand_Success;
3923 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3924 ARMAsmParser::OperandMatchResultTy
3925 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3926 MCAsmParser &Parser = getParser();
3927 SMLoc S = Parser.getTok().getLoc();
3928 const AsmToken &Tok = Parser.getTok();
3929 if (!Tok.is(AsmToken::Identifier))
3930 return MatchOperand_NoMatch;
3931 StringRef IFlagsStr = Tok.getString();
3933 // An iflags string of "none" is interpreted to mean that none of the AIF
3934 // bits are set. Not a terribly useful instruction, but a valid encoding.
3935 unsigned IFlags = 0;
3936 if (IFlagsStr != "none") {
3937 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3938 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3939 .Case("a", ARM_PROC::A)
3940 .Case("i", ARM_PROC::I)
3941 .Case("f", ARM_PROC::F)
3944 // If some specific iflag is already set, it means that some letter is
3945 // present more than once, this is not acceptable.
3946 if (Flag == ~0U || (IFlags & Flag))
3947 return MatchOperand_NoMatch;
3953 Parser.Lex(); // Eat identifier token.
3954 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3955 return MatchOperand_Success;
3958 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3959 ARMAsmParser::OperandMatchResultTy
3960 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
3961 MCAsmParser &Parser = getParser();
3962 SMLoc S = Parser.getTok().getLoc();
3963 const AsmToken &Tok = Parser.getTok();
3964 if (!Tok.is(AsmToken::Identifier))
3965 return MatchOperand_NoMatch;
3966 StringRef Mask = Tok.getString();
3969 // See ARMv6-M 10.1.1
3970 std::string Name = Mask.lower();
3971 unsigned FlagsVal = StringSwitch<unsigned>(Name)
3972 // Note: in the documentation:
3973 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
3974 // for MSR APSR_nzcvq.
3975 // but we do make it an alias here. This is so to get the "mask encoding"
3976 // bits correct on MSR APSR writes.
3978 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
3979 // should really only be allowed when writing a special register. Note
3980 // they get dropped in the MRS instruction reading a special register as
3981 // the SYSm field is only 8 bits.
3982 .Case("apsr", 0x800)
3983 .Case("apsr_nzcvq", 0x800)
3984 .Case("apsr_g", 0x400)
3985 .Case("apsr_nzcvqg", 0xc00)
3986 .Case("iapsr", 0x801)
3987 .Case("iapsr_nzcvq", 0x801)
3988 .Case("iapsr_g", 0x401)
3989 .Case("iapsr_nzcvqg", 0xc01)
3990 .Case("eapsr", 0x802)
3991 .Case("eapsr_nzcvq", 0x802)
3992 .Case("eapsr_g", 0x402)
3993 .Case("eapsr_nzcvqg", 0xc02)
3994 .Case("xpsr", 0x803)
3995 .Case("xpsr_nzcvq", 0x803)
3996 .Case("xpsr_g", 0x403)
3997 .Case("xpsr_nzcvqg", 0xc03)
3998 .Case("ipsr", 0x805)
3999 .Case("epsr", 0x806)
4000 .Case("iepsr", 0x807)
4003 .Case("primask", 0x810)
4004 .Case("basepri", 0x811)
4005 .Case("basepri_max", 0x812)
4006 .Case("faultmask", 0x813)
4007 .Case("control", 0x814)
4010 if (FlagsVal == ~0U)
4011 return MatchOperand_NoMatch;
4013 if (!hasDSP() && (FlagsVal & 0x400))
4014 // The _g and _nzcvqg versions are only valid if the DSP extension is
4016 return MatchOperand_NoMatch;
4018 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4019 // basepri, basepri_max and faultmask only valid for V7m.
4020 return MatchOperand_NoMatch;
4022 Parser.Lex(); // Eat identifier token.
4023 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4024 return MatchOperand_Success;
4027 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4028 size_t Start = 0, Next = Mask.find('_');
4029 StringRef Flags = "";
4030 std::string SpecReg = Mask.slice(Start, Next).lower();
4031 if (Next != StringRef::npos)
4032 Flags = Mask.slice(Next+1, Mask.size());
4034 // FlagsVal contains the complete mask:
4036 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4037 unsigned FlagsVal = 0;
4039 if (SpecReg == "apsr") {
4040 FlagsVal = StringSwitch<unsigned>(Flags)
4041 .Case("nzcvq", 0x8) // same as CPSR_f
4042 .Case("g", 0x4) // same as CPSR_s
4043 .Case("nzcvqg", 0xc) // same as CPSR_fs
4046 if (FlagsVal == ~0U) {
4048 return MatchOperand_NoMatch;
4050 FlagsVal = 8; // No flag
4052 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4053 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4054 if (Flags == "all" || Flags == "")
4056 for (int i = 0, e = Flags.size(); i != e; ++i) {
4057 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4064 // If some specific flag is already set, it means that some letter is
4065 // present more than once, this is not acceptable.
4066 if (FlagsVal == ~0U || (FlagsVal & Flag))
4067 return MatchOperand_NoMatch;
4070 } else // No match for special register.
4071 return MatchOperand_NoMatch;
4073 // Special register without flags is NOT equivalent to "fc" flags.
4074 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4075 // two lines would enable gas compatibility at the expense of breaking
4081 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4082 if (SpecReg == "spsr")
4085 Parser.Lex(); // Eat identifier token.
4086 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4087 return MatchOperand_Success;
4090 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4091 /// use in the MRS/MSR instructions added to support virtualization.
4092 ARMAsmParser::OperandMatchResultTy
4093 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4094 MCAsmParser &Parser = getParser();
4095 SMLoc S = Parser.getTok().getLoc();
4096 const AsmToken &Tok = Parser.getTok();
4097 if (!Tok.is(AsmToken::Identifier))
4098 return MatchOperand_NoMatch;
4099 StringRef RegName = Tok.getString();
4101 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4103 unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4104 .Case("r8_usr", 0x00)
4105 .Case("r9_usr", 0x01)
4106 .Case("r10_usr", 0x02)
4107 .Case("r11_usr", 0x03)
4108 .Case("r12_usr", 0x04)
4109 .Case("sp_usr", 0x05)
4110 .Case("lr_usr", 0x06)
4111 .Case("r8_fiq", 0x08)
4112 .Case("r9_fiq", 0x09)
4113 .Case("r10_fiq", 0x0a)
4114 .Case("r11_fiq", 0x0b)
4115 .Case("r12_fiq", 0x0c)
4116 .Case("sp_fiq", 0x0d)
4117 .Case("lr_fiq", 0x0e)
4118 .Case("lr_irq", 0x10)
4119 .Case("sp_irq", 0x11)
4120 .Case("lr_svc", 0x12)
4121 .Case("sp_svc", 0x13)
4122 .Case("lr_abt", 0x14)
4123 .Case("sp_abt", 0x15)
4124 .Case("lr_und", 0x16)
4125 .Case("sp_und", 0x17)
4126 .Case("lr_mon", 0x1c)
4127 .Case("sp_mon", 0x1d)
4128 .Case("elr_hyp", 0x1e)
4129 .Case("sp_hyp", 0x1f)
4130 .Case("spsr_fiq", 0x2e)
4131 .Case("spsr_irq", 0x30)
4132 .Case("spsr_svc", 0x32)
4133 .Case("spsr_abt", 0x34)
4134 .Case("spsr_und", 0x36)
4135 .Case("spsr_mon", 0x3c)
4136 .Case("spsr_hyp", 0x3e)
4139 if (Encoding == ~0U)
4140 return MatchOperand_NoMatch;
4142 Parser.Lex(); // Eat identifier token.
4143 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4144 return MatchOperand_Success;
4147 ARMAsmParser::OperandMatchResultTy
4148 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4150 MCAsmParser &Parser = getParser();
4151 const AsmToken &Tok = Parser.getTok();
4152 if (Tok.isNot(AsmToken::Identifier)) {
4153 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4154 return MatchOperand_ParseFail;
4156 StringRef ShiftName = Tok.getString();
4157 std::string LowerOp = Op.lower();
4158 std::string UpperOp = Op.upper();
4159 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4160 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4161 return MatchOperand_ParseFail;
4163 Parser.Lex(); // Eat shift type token.
4165 // There must be a '#' and a shift amount.
4166 if (Parser.getTok().isNot(AsmToken::Hash) &&
4167 Parser.getTok().isNot(AsmToken::Dollar)) {
4168 Error(Parser.getTok().getLoc(), "'#' expected");
4169 return MatchOperand_ParseFail;
4171 Parser.Lex(); // Eat hash token.
4173 const MCExpr *ShiftAmount;
4174 SMLoc Loc = Parser.getTok().getLoc();
4176 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4177 Error(Loc, "illegal expression");
4178 return MatchOperand_ParseFail;
4180 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4182 Error(Loc, "constant expression expected");
4183 return MatchOperand_ParseFail;
4185 int Val = CE->getValue();
4186 if (Val < Low || Val > High) {
4187 Error(Loc, "immediate value out of range");
4188 return MatchOperand_ParseFail;
4191 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4193 return MatchOperand_Success;
4196 ARMAsmParser::OperandMatchResultTy
4197 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4198 MCAsmParser &Parser = getParser();
4199 const AsmToken &Tok = Parser.getTok();
4200 SMLoc S = Tok.getLoc();
4201 if (Tok.isNot(AsmToken::Identifier)) {
4202 Error(S, "'be' or 'le' operand expected");
4203 return MatchOperand_ParseFail;
4205 int Val = StringSwitch<int>(Tok.getString().lower())
4209 Parser.Lex(); // Eat the token.
4212 Error(S, "'be' or 'le' operand expected");
4213 return MatchOperand_ParseFail;
4215 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
4217 S, Tok.getEndLoc()));
4218 return MatchOperand_Success;
4221 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4222 /// instructions. Legal values are:
4223 /// lsl #n 'n' in [0,31]
4224 /// asr #n 'n' in [1,32]
4225 /// n == 32 encoded as n == 0.
4226 ARMAsmParser::OperandMatchResultTy
4227 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4228 MCAsmParser &Parser = getParser();
4229 const AsmToken &Tok = Parser.getTok();
4230 SMLoc S = Tok.getLoc();
4231 if (Tok.isNot(AsmToken::Identifier)) {
4232 Error(S, "shift operator 'asr' or 'lsl' expected");
4233 return MatchOperand_ParseFail;
4235 StringRef ShiftName = Tok.getString();
4237 if (ShiftName == "lsl" || ShiftName == "LSL")
4239 else if (ShiftName == "asr" || ShiftName == "ASR")
4242 Error(S, "shift operator 'asr' or 'lsl' expected");
4243 return MatchOperand_ParseFail;
4245 Parser.Lex(); // Eat the operator.
4247 // A '#' and a shift amount.
4248 if (Parser.getTok().isNot(AsmToken::Hash) &&
4249 Parser.getTok().isNot(AsmToken::Dollar)) {
4250 Error(Parser.getTok().getLoc(), "'#' expected");
4251 return MatchOperand_ParseFail;
4253 Parser.Lex(); // Eat hash token.
4254 SMLoc ExLoc = Parser.getTok().getLoc();
4256 const MCExpr *ShiftAmount;
4258 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4259 Error(ExLoc, "malformed shift expression");
4260 return MatchOperand_ParseFail;
4262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4264 Error(ExLoc, "shift amount must be an immediate");
4265 return MatchOperand_ParseFail;
4268 int64_t Val = CE->getValue();
4270 // Shift amount must be in [1,32]
4271 if (Val < 1 || Val > 32) {
4272 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4273 return MatchOperand_ParseFail;
4275 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4276 if (isThumb() && Val == 32) {
4277 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4278 return MatchOperand_ParseFail;
4280 if (Val == 32) Val = 0;
4282 // Shift amount must be in [1,32]
4283 if (Val < 0 || Val > 31) {
4284 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4285 return MatchOperand_ParseFail;
4289 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4291 return MatchOperand_Success;
4294 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4295 /// of instructions. Legal values are:
4296 /// ror #n 'n' in {0, 8, 16, 24}
4297 ARMAsmParser::OperandMatchResultTy
4298 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4299 MCAsmParser &Parser = getParser();
4300 const AsmToken &Tok = Parser.getTok();
4301 SMLoc S = Tok.getLoc();
4302 if (Tok.isNot(AsmToken::Identifier))
4303 return MatchOperand_NoMatch;
4304 StringRef ShiftName = Tok.getString();
4305 if (ShiftName != "ror" && ShiftName != "ROR")
4306 return MatchOperand_NoMatch;
4307 Parser.Lex(); // Eat the operator.
4309 // A '#' and a rotate amount.
4310 if (Parser.getTok().isNot(AsmToken::Hash) &&
4311 Parser.getTok().isNot(AsmToken::Dollar)) {
4312 Error(Parser.getTok().getLoc(), "'#' expected");
4313 return MatchOperand_ParseFail;
4315 Parser.Lex(); // Eat hash token.
4316 SMLoc ExLoc = Parser.getTok().getLoc();
4318 const MCExpr *ShiftAmount;
4320 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4321 Error(ExLoc, "malformed rotate expression");
4322 return MatchOperand_ParseFail;
4324 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4326 Error(ExLoc, "rotate amount must be an immediate");
4327 return MatchOperand_ParseFail;
4330 int64_t Val = CE->getValue();
4331 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4332 // normally, zero is represented in asm by omitting the rotate operand
4334 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4335 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4336 return MatchOperand_ParseFail;
4339 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4341 return MatchOperand_Success;
4344 ARMAsmParser::OperandMatchResultTy
4345 ARMAsmParser::parseModImm(OperandVector &Operands) {
4346 MCAsmParser &Parser = getParser();
4347 MCAsmLexer &Lexer = getLexer();
4350 SMLoc S = Parser.getTok().getLoc();
4352 // 1) A mod_imm operand can appear in the place of a register name:
4354 // add r0, r0, #mod_imm
4355 // to correctly handle the latter, we bail out as soon as we see an
4358 // 2) Similarly, we do not want to parse into complex operands:
4360 // mov r0, :lower16:(_foo)
4361 if (Parser.getTok().is(AsmToken::Identifier) ||
4362 Parser.getTok().is(AsmToken::Colon))
4363 return MatchOperand_NoMatch;
4365 // Hash (dollar) is optional as per the ARMARM
4366 if (Parser.getTok().is(AsmToken::Hash) ||
4367 Parser.getTok().is(AsmToken::Dollar)) {
4368 // Avoid parsing into complex operands (#:)
4369 if (Lexer.peekTok().is(AsmToken::Colon))
4370 return MatchOperand_NoMatch;
4372 // Eat the hash (dollar)
4377 Sx1 = Parser.getTok().getLoc();
4378 const MCExpr *Imm1Exp;
4379 if (getParser().parseExpression(Imm1Exp, Ex1)) {
4380 Error(Sx1, "malformed expression");
4381 return MatchOperand_ParseFail;
4384 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4387 // Immediate must fit within 32-bits
4388 Imm1 = CE->getValue();
4389 int Enc = ARM_AM::getSOImmVal(Imm1);
4390 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4392 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4395 return MatchOperand_Success;
4398 // We have parsed an immediate which is not for us, fallback to a plain
4399 // immediate. This can happen for instruction aliases. For an example,
4400 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4401 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4402 // instruction with a mod_imm operand. The alias is defined such that the
4403 // parser method is shared, that's why we have to do this here.
4404 if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4405 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4406 return MatchOperand_Success;
4409 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4410 // MCFixup). Fallback to a plain immediate.
4411 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4412 return MatchOperand_Success;
4415 // From this point onward, we expect the input to be a (#bits, #rot) pair
4416 if (Parser.getTok().isNot(AsmToken::Comma)) {
4417 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4418 return MatchOperand_ParseFail;
4422 Error(Sx1, "immediate operand must a number in the range [0, 255]");
4423 return MatchOperand_ParseFail;
4431 Sx2 = Parser.getTok().getLoc();
4433 // Eat the optional hash (dollar)
4434 if (Parser.getTok().is(AsmToken::Hash) ||
4435 Parser.getTok().is(AsmToken::Dollar))
4438 const MCExpr *Imm2Exp;
4439 if (getParser().parseExpression(Imm2Exp, Ex2)) {
4440 Error(Sx2, "malformed expression");
4441 return MatchOperand_ParseFail;
4444 CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4447 Imm2 = CE->getValue();
4448 if (!(Imm2 & ~0x1E)) {
4450 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4451 return MatchOperand_Success;
4453 Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4454 return MatchOperand_ParseFail;
4456 Error(Sx2, "constant expression expected");
4457 return MatchOperand_ParseFail;
4461 ARMAsmParser::OperandMatchResultTy
4462 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4463 MCAsmParser &Parser = getParser();
4464 SMLoc S = Parser.getTok().getLoc();
4465 // The bitfield descriptor is really two operands, the LSB and the width.
4466 if (Parser.getTok().isNot(AsmToken::Hash) &&
4467 Parser.getTok().isNot(AsmToken::Dollar)) {
4468 Error(Parser.getTok().getLoc(), "'#' expected");
4469 return MatchOperand_ParseFail;
4471 Parser.Lex(); // Eat hash token.
4473 const MCExpr *LSBExpr;
4474 SMLoc E = Parser.getTok().getLoc();
4475 if (getParser().parseExpression(LSBExpr)) {
4476 Error(E, "malformed immediate expression");
4477 return MatchOperand_ParseFail;
4479 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4481 Error(E, "'lsb' operand must be an immediate");
4482 return MatchOperand_ParseFail;
4485 int64_t LSB = CE->getValue();
4486 // The LSB must be in the range [0,31]
4487 if (LSB < 0 || LSB > 31) {
4488 Error(E, "'lsb' operand must be in the range [0,31]");
4489 return MatchOperand_ParseFail;
4491 E = Parser.getTok().getLoc();
4493 // Expect another immediate operand.
4494 if (Parser.getTok().isNot(AsmToken::Comma)) {
4495 Error(Parser.getTok().getLoc(), "too few operands");
4496 return MatchOperand_ParseFail;
4498 Parser.Lex(); // Eat hash token.
4499 if (Parser.getTok().isNot(AsmToken::Hash) &&
4500 Parser.getTok().isNot(AsmToken::Dollar)) {
4501 Error(Parser.getTok().getLoc(), "'#' expected");
4502 return MatchOperand_ParseFail;
4504 Parser.Lex(); // Eat hash token.
4506 const MCExpr *WidthExpr;
4508 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4509 Error(E, "malformed immediate expression");
4510 return MatchOperand_ParseFail;
4512 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4514 Error(E, "'width' operand must be an immediate");
4515 return MatchOperand_ParseFail;
4518 int64_t Width = CE->getValue();
4519 // The LSB must be in the range [1,32-lsb]
4520 if (Width < 1 || Width > 32 - LSB) {
4521 Error(E, "'width' operand must be in the range [1,32-lsb]");
4522 return MatchOperand_ParseFail;
4525 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4527 return MatchOperand_Success;
4530 ARMAsmParser::OperandMatchResultTy
4531 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4532 // Check for a post-index addressing register operand. Specifically:
4533 // postidx_reg := '+' register {, shift}
4534 // | '-' register {, shift}
4535 // | register {, shift}
4537 // This method must return MatchOperand_NoMatch without consuming any tokens
4538 // in the case where there is no match, as other alternatives take other
4540 MCAsmParser &Parser = getParser();
4541 AsmToken Tok = Parser.getTok();
4542 SMLoc S = Tok.getLoc();
4543 bool haveEaten = false;
4545 if (Tok.is(AsmToken::Plus)) {
4546 Parser.Lex(); // Eat the '+' token.
4548 } else if (Tok.is(AsmToken::Minus)) {
4549 Parser.Lex(); // Eat the '-' token.
4554 SMLoc E = Parser.getTok().getEndLoc();
4555 int Reg = tryParseRegister();
4558 return MatchOperand_NoMatch;
4559 Error(Parser.getTok().getLoc(), "register expected");
4560 return MatchOperand_ParseFail;
4563 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4564 unsigned ShiftImm = 0;
4565 if (Parser.getTok().is(AsmToken::Comma)) {
4566 Parser.Lex(); // Eat the ','.
4567 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4568 return MatchOperand_ParseFail;
4570 // FIXME: Only approximates end...may include intervening whitespace.
4571 E = Parser.getTok().getLoc();
4574 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4577 return MatchOperand_Success;
4580 ARMAsmParser::OperandMatchResultTy
4581 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4582 // Check for a post-index addressing register operand. Specifically:
4583 // am3offset := '+' register
4590 // This method must return MatchOperand_NoMatch without consuming any tokens
4591 // in the case where there is no match, as other alternatives take other
4593 MCAsmParser &Parser = getParser();
4594 AsmToken Tok = Parser.getTok();
4595 SMLoc S = Tok.getLoc();
4597 // Do immediates first, as we always parse those if we have a '#'.
4598 if (Parser.getTok().is(AsmToken::Hash) ||
4599 Parser.getTok().is(AsmToken::Dollar)) {
4600 Parser.Lex(); // Eat '#' or '$'.
4601 // Explicitly look for a '-', as we need to encode negative zero
4603 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4604 const MCExpr *Offset;
4606 if (getParser().parseExpression(Offset, E))
4607 return MatchOperand_ParseFail;
4608 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4610 Error(S, "constant expression expected");
4611 return MatchOperand_ParseFail;
4613 // Negative zero is encoded as the flag value INT32_MIN.
4614 int32_t Val = CE->getValue();
4615 if (isNegative && Val == 0)
4619 ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
4621 return MatchOperand_Success;
4625 bool haveEaten = false;
4627 if (Tok.is(AsmToken::Plus)) {
4628 Parser.Lex(); // Eat the '+' token.
4630 } else if (Tok.is(AsmToken::Minus)) {
4631 Parser.Lex(); // Eat the '-' token.
4636 Tok = Parser.getTok();
4637 int Reg = tryParseRegister();
4640 return MatchOperand_NoMatch;
4641 Error(Tok.getLoc(), "register expected");
4642 return MatchOperand_ParseFail;
4645 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4646 0, S, Tok.getEndLoc()));
4648 return MatchOperand_Success;
4651 /// Convert parsed operands to MCInst. Needed here because this instruction
4652 /// only has two register operands, but multiplication is commutative so
4653 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4654 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4655 const OperandVector &Operands) {
4656 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4657 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4658 // If we have a three-operand form, make sure to set Rn to be the operand
4659 // that isn't the same as Rd.
4661 if (Operands.size() == 6 &&
4662 ((ARMOperand &)*Operands[4]).getReg() ==
4663 ((ARMOperand &)*Operands[3]).getReg())
4665 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4666 Inst.addOperand(Inst.getOperand(0));
4667 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4670 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4671 const OperandVector &Operands) {
4672 int CondOp = -1, ImmOp = -1;
4673 switch(Inst.getOpcode()) {
4675 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4678 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4680 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4682 // first decide whether or not the branch should be conditional
4683 // by looking at it's location relative to an IT block
4685 // inside an IT block we cannot have any conditional branches. any
4686 // such instructions needs to be converted to unconditional form
4687 switch(Inst.getOpcode()) {
4688 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4689 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4692 // outside IT blocks we can only have unconditional branches with AL
4693 // condition code or conditional branches with non-AL condition code
4694 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4695 switch(Inst.getOpcode()) {
4698 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4702 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4707 // now decide on encoding size based on branch target range
4708 switch(Inst.getOpcode()) {
4709 // classify tB as either t2B or t1B based on range of immediate operand
4711 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4712 if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4713 Inst.setOpcode(ARM::t2B);
4716 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4718 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4719 if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4720 Inst.setOpcode(ARM::t2Bcc);
4724 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4725 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4728 /// Parse an ARM memory expression, return false if successful else return true
4729 /// or an error. The first token must be a '[' when called.
4730 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4731 MCAsmParser &Parser = getParser();
4733 assert(Parser.getTok().is(AsmToken::LBrac) &&
4734 "Token is not a Left Bracket");
4735 S = Parser.getTok().getLoc();
4736 Parser.Lex(); // Eat left bracket token.
4738 const AsmToken &BaseRegTok = Parser.getTok();
4739 int BaseRegNum = tryParseRegister();
4740 if (BaseRegNum == -1)
4741 return Error(BaseRegTok.getLoc(), "register expected");
4743 // The next token must either be a comma, a colon or a closing bracket.
4744 const AsmToken &Tok = Parser.getTok();
4745 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4746 !Tok.is(AsmToken::RBrac))
4747 return Error(Tok.getLoc(), "malformed memory operand");
4749 if (Tok.is(AsmToken::RBrac)) {
4750 E = Tok.getEndLoc();
4751 Parser.Lex(); // Eat right bracket token.
4753 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4754 ARM_AM::no_shift, 0, 0, false,
4757 // If there's a pre-indexing writeback marker, '!', just add it as a token
4758 // operand. It's rather odd, but syntactically valid.
4759 if (Parser.getTok().is(AsmToken::Exclaim)) {
4760 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4761 Parser.Lex(); // Eat the '!'.
4767 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4768 "Lost colon or comma in memory operand?!");
4769 if (Tok.is(AsmToken::Comma)) {
4770 Parser.Lex(); // Eat the comma.
4773 // If we have a ':', it's an alignment specifier.
4774 if (Parser.getTok().is(AsmToken::Colon)) {
4775 Parser.Lex(); // Eat the ':'.
4776 E = Parser.getTok().getLoc();
4777 SMLoc AlignmentLoc = Tok.getLoc();
4780 if (getParser().parseExpression(Expr))
4783 // The expression has to be a constant. Memory references with relocations
4784 // don't come through here, as they use the <label> forms of the relevant
4786 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4788 return Error (E, "constant expression expected");
4791 switch (CE->getValue()) {
4794 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4795 case 16: Align = 2; break;
4796 case 32: Align = 4; break;
4797 case 64: Align = 8; break;
4798 case 128: Align = 16; break;
4799 case 256: Align = 32; break;
4802 // Now we should have the closing ']'
4803 if (Parser.getTok().isNot(AsmToken::RBrac))
4804 return Error(Parser.getTok().getLoc(), "']' expected");
4805 E = Parser.getTok().getEndLoc();
4806 Parser.Lex(); // Eat right bracket token.
4808 // Don't worry about range checking the value here. That's handled by
4809 // the is*() predicates.
4810 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4811 ARM_AM::no_shift, 0, Align,
4812 false, S, E, AlignmentLoc));
4814 // If there's a pre-indexing writeback marker, '!', just add it as a token
4816 if (Parser.getTok().is(AsmToken::Exclaim)) {
4817 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4818 Parser.Lex(); // Eat the '!'.
4824 // If we have a '#', it's an immediate offset, else assume it's a register
4825 // offset. Be friendly and also accept a plain integer (without a leading
4826 // hash) for gas compatibility.
4827 if (Parser.getTok().is(AsmToken::Hash) ||
4828 Parser.getTok().is(AsmToken::Dollar) ||
4829 Parser.getTok().is(AsmToken::Integer)) {
4830 if (Parser.getTok().isNot(AsmToken::Integer))
4831 Parser.Lex(); // Eat '#' or '$'.
4832 E = Parser.getTok().getLoc();
4834 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4835 const MCExpr *Offset;
4836 if (getParser().parseExpression(Offset))
4839 // The expression has to be a constant. Memory references with relocations
4840 // don't come through here, as they use the <label> forms of the relevant
4842 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4844 return Error (E, "constant expression expected");
4846 // If the constant was #-0, represent it as INT32_MIN.
4847 int32_t Val = CE->getValue();
4848 if (isNegative && Val == 0)
4849 CE = MCConstantExpr::create(INT32_MIN, getContext());
4851 // Now we should have the closing ']'
4852 if (Parser.getTok().isNot(AsmToken::RBrac))
4853 return Error(Parser.getTok().getLoc(), "']' expected");
4854 E = Parser.getTok().getEndLoc();
4855 Parser.Lex(); // Eat right bracket token.
4857 // Don't worry about range checking the value here. That's handled by
4858 // the is*() predicates.
4859 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4860 ARM_AM::no_shift, 0, 0,
4863 // If there's a pre-indexing writeback marker, '!', just add it as a token
4865 if (Parser.getTok().is(AsmToken::Exclaim)) {
4866 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4867 Parser.Lex(); // Eat the '!'.
4873 // The register offset is optionally preceded by a '+' or '-'
4874 bool isNegative = false;
4875 if (Parser.getTok().is(AsmToken::Minus)) {
4877 Parser.Lex(); // Eat the '-'.
4878 } else if (Parser.getTok().is(AsmToken::Plus)) {
4880 Parser.Lex(); // Eat the '+'.
4883 E = Parser.getTok().getLoc();
4884 int OffsetRegNum = tryParseRegister();
4885 if (OffsetRegNum == -1)
4886 return Error(E, "register expected");
4888 // If there's a shift operator, handle it.
4889 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4890 unsigned ShiftImm = 0;
4891 if (Parser.getTok().is(AsmToken::Comma)) {
4892 Parser.Lex(); // Eat the ','.
4893 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4897 // Now we should have the closing ']'
4898 if (Parser.getTok().isNot(AsmToken::RBrac))
4899 return Error(Parser.getTok().getLoc(), "']' expected");
4900 E = Parser.getTok().getEndLoc();
4901 Parser.Lex(); // Eat right bracket token.
4903 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4904 ShiftType, ShiftImm, 0, isNegative,
4907 // If there's a pre-indexing writeback marker, '!', just add it as a token
4909 if (Parser.getTok().is(AsmToken::Exclaim)) {
4910 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4911 Parser.Lex(); // Eat the '!'.
4917 /// parseMemRegOffsetShift - one of these two:
4918 /// ( lsl | lsr | asr | ror ) , # shift_amount
4920 /// return true if it parses a shift otherwise it returns false.
4921 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4923 MCAsmParser &Parser = getParser();
4924 SMLoc Loc = Parser.getTok().getLoc();
4925 const AsmToken &Tok = Parser.getTok();
4926 if (Tok.isNot(AsmToken::Identifier))
4928 StringRef ShiftName = Tok.getString();
4929 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4930 ShiftName == "asl" || ShiftName == "ASL")
4932 else if (ShiftName == "lsr" || ShiftName == "LSR")
4934 else if (ShiftName == "asr" || ShiftName == "ASR")
4936 else if (ShiftName == "ror" || ShiftName == "ROR")
4938 else if (ShiftName == "rrx" || ShiftName == "RRX")
4941 return Error(Loc, "illegal shift operator");
4942 Parser.Lex(); // Eat shift type token.
4944 // rrx stands alone.
4946 if (St != ARM_AM::rrx) {
4947 Loc = Parser.getTok().getLoc();
4948 // A '#' and a shift amount.
4949 const AsmToken &HashTok = Parser.getTok();
4950 if (HashTok.isNot(AsmToken::Hash) &&
4951 HashTok.isNot(AsmToken::Dollar))
4952 return Error(HashTok.getLoc(), "'#' expected");
4953 Parser.Lex(); // Eat hash token.
4956 if (getParser().parseExpression(Expr))
4958 // Range check the immediate.
4959 // lsl, ror: 0 <= imm <= 31
4960 // lsr, asr: 0 <= imm <= 32
4961 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4963 return Error(Loc, "shift amount must be an immediate");
4964 int64_t Imm = CE->getValue();
4966 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
4967 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
4968 return Error(Loc, "immediate shift value out of range");
4969 // If <ShiftTy> #0, turn it into a no_shift.
4972 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
4981 /// parseFPImm - A floating point immediate expression operand.
4982 ARMAsmParser::OperandMatchResultTy
4983 ARMAsmParser::parseFPImm(OperandVector &Operands) {
4984 MCAsmParser &Parser = getParser();
4985 // Anything that can accept a floating point constant as an operand
4986 // needs to go through here, as the regular parseExpression is
4989 // This routine still creates a generic Immediate operand, containing
4990 // a bitcast of the 64-bit floating point value. The various operands
4991 // that accept floats can check whether the value is valid for them
4992 // via the standard is*() predicates.
4994 SMLoc S = Parser.getTok().getLoc();
4996 if (Parser.getTok().isNot(AsmToken::Hash) &&
4997 Parser.getTok().isNot(AsmToken::Dollar))
4998 return MatchOperand_NoMatch;
5000 // Disambiguate the VMOV forms that can accept an FP immediate.
5001 // vmov.f32 <sreg>, #imm
5002 // vmov.f64 <dreg>, #imm
5003 // vmov.f32 <dreg>, #imm @ vector f32x2
5004 // vmov.f32 <qreg>, #imm @ vector f32x4
5006 // There are also the NEON VMOV instructions which expect an
5007 // integer constant. Make sure we don't try to parse an FPImm
5009 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5010 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5011 bool isVmovf = TyOp.isToken() &&
5012 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64" ||
5013 TyOp.getToken() == ".f16");
5014 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5015 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5016 Mnemonic.getToken() == "fconsts");
5017 if (!(isVmovf || isFconst))
5018 return MatchOperand_NoMatch;
5020 Parser.Lex(); // Eat '#' or '$'.
5022 // Handle negation, as that still comes through as a separate token.
5023 bool isNegative = false;
5024 if (Parser.getTok().is(AsmToken::Minus)) {
5028 const AsmToken &Tok = Parser.getTok();
5029 SMLoc Loc = Tok.getLoc();
5030 if (Tok.is(AsmToken::Real) && isVmovf) {
5031 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
5032 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5033 // If we had a '-' in front, toggle the sign bit.
5034 IntVal ^= (uint64_t)isNegative << 31;
5035 Parser.Lex(); // Eat the token.
5036 Operands.push_back(ARMOperand::CreateImm(
5037 MCConstantExpr::create(IntVal, getContext()),
5038 S, Parser.getTok().getLoc()));
5039 return MatchOperand_Success;
5041 // Also handle plain integers. Instructions which allow floating point
5042 // immediates also allow a raw encoded 8-bit value.
5043 if (Tok.is(AsmToken::Integer) && isFconst) {
5044 int64_t Val = Tok.getIntVal();
5045 Parser.Lex(); // Eat the token.
5046 if (Val > 255 || Val < 0) {
5047 Error(Loc, "encoded floating point value out of range");
5048 return MatchOperand_ParseFail;
5050 float RealVal = ARM_AM::getFPImmFloat(Val);
5051 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5053 Operands.push_back(ARMOperand::CreateImm(
5054 MCConstantExpr::create(Val, getContext()), S,
5055 Parser.getTok().getLoc()));
5056 return MatchOperand_Success;
5059 Error(Loc, "invalid floating point immediate");
5060 return MatchOperand_ParseFail;
5063 /// Parse a arm instruction operand. For now this parses the operand regardless
5064 /// of the mnemonic.
5065 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5066 MCAsmParser &Parser = getParser();
5069 // Check if the current operand has a custom associated parser, if so, try to
5070 // custom parse the operand, or fallback to the general approach.
5071 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5072 if (ResTy == MatchOperand_Success)
5074 // If there wasn't a custom match, try the generic matcher below. Otherwise,
5075 // there was a match, but an error occurred, in which case, just return that
5076 // the operand parsing failed.
5077 if (ResTy == MatchOperand_ParseFail)
5080 switch (getLexer().getKind()) {
5082 Error(Parser.getTok().getLoc(), "unexpected token in operand");
5084 case AsmToken::Identifier: {
5085 // If we've seen a branch mnemonic, the next operand must be a label. This
5086 // is true even if the label is a register name. So "br r1" means branch to
5088 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5090 if (!tryParseRegisterWithWriteBack(Operands))
5092 int Res = tryParseShiftRegister(Operands);
5093 if (Res == 0) // success
5095 else if (Res == -1) // irrecoverable error
5097 // If this is VMRS, check for the apsr_nzcv operand.
5098 if (Mnemonic == "vmrs" &&
5099 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5100 S = Parser.getTok().getLoc();
5102 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5107 // Fall though for the Identifier case that is not a register or a
5110 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
5111 case AsmToken::Integer: // things like 1f and 2b as a branch targets
5112 case AsmToken::String: // quoted label names.
5113 case AsmToken::Dot: { // . as a branch target
5114 // This was not a register so parse other operands that start with an
5115 // identifier (like labels) as expressions and create them as immediates.
5116 const MCExpr *IdVal;
5117 S = Parser.getTok().getLoc();
5118 if (getParser().parseExpression(IdVal))
5120 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5121 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5124 case AsmToken::LBrac:
5125 return parseMemory(Operands);
5126 case AsmToken::LCurly:
5127 return parseRegisterList(Operands);
5128 case AsmToken::Dollar:
5129 case AsmToken::Hash: {
5130 // #42 -> immediate.
5131 S = Parser.getTok().getLoc();
5134 if (Parser.getTok().isNot(AsmToken::Colon)) {
5135 bool isNegative = Parser.getTok().is(AsmToken::Minus);
5136 const MCExpr *ImmVal;
5137 if (getParser().parseExpression(ImmVal))
5139 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5141 int32_t Val = CE->getValue();
5142 if (isNegative && Val == 0)
5143 ImmVal = MCConstantExpr::create(INT32_MIN, getContext());
5145 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5146 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5148 // There can be a trailing '!' on operands that we want as a separate
5149 // '!' Token operand. Handle that here. For example, the compatibility
5150 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5151 if (Parser.getTok().is(AsmToken::Exclaim)) {
5152 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5153 Parser.getTok().getLoc()));
5154 Parser.Lex(); // Eat exclaim token
5158 // w/ a ':' after the '#', it's just like a plain ':'.
5161 case AsmToken::Colon: {
5162 S = Parser.getTok().getLoc();
5163 // ":lower16:" and ":upper16:" expression prefixes
5164 // FIXME: Check it's an expression prefix,
5165 // e.g. (FOO - :lower16:BAR) isn't legal.
5166 ARMMCExpr::VariantKind RefKind;
5167 if (parsePrefix(RefKind))
5170 const MCExpr *SubExprVal;
5171 if (getParser().parseExpression(SubExprVal))
5174 const MCExpr *ExprVal = ARMMCExpr::create(RefKind, SubExprVal,
5176 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5177 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5180 case AsmToken::Equal: {
5181 S = Parser.getTok().getLoc();
5182 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5183 return Error(S, "unexpected token in operand");
5185 Parser.Lex(); // Eat '='
5186 const MCExpr *SubExprVal;
5187 if (getParser().parseExpression(SubExprVal))
5189 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5191 const MCExpr *CPLoc =
5192 getTargetStreamer().addConstantPoolEntry(SubExprVal, S);
5193 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5199 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5200 // :lower16: and :upper16:.
5201 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5202 MCAsmParser &Parser = getParser();
5203 RefKind = ARMMCExpr::VK_ARM_None;
5205 // consume an optional '#' (GNU compatibility)
5206 if (getLexer().is(AsmToken::Hash))
5209 // :lower16: and :upper16: modifiers
5210 assert(getLexer().is(AsmToken::Colon) && "expected a :");
5211 Parser.Lex(); // Eat ':'
5213 if (getLexer().isNot(AsmToken::Identifier)) {
5214 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5219 COFF = (1 << MCObjectFileInfo::IsCOFF),
5220 ELF = (1 << MCObjectFileInfo::IsELF),
5221 MACHO = (1 << MCObjectFileInfo::IsMachO)
5223 static const struct PrefixEntry {
5224 const char *Spelling;
5225 ARMMCExpr::VariantKind VariantKind;
5226 uint8_t SupportedFormats;
5227 } PrefixEntries[] = {
5228 { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
5229 { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
5232 StringRef IDVal = Parser.getTok().getIdentifier();
5234 const auto &Prefix =
5235 std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
5236 [&IDVal](const PrefixEntry &PE) {
5237 return PE.Spelling == IDVal;
5239 if (Prefix == std::end(PrefixEntries)) {
5240 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5244 uint8_t CurrentFormat;
5245 switch (getContext().getObjectFileInfo()->getObjectFileType()) {
5246 case MCObjectFileInfo::IsMachO:
5247 CurrentFormat = MACHO;
5249 case MCObjectFileInfo::IsELF:
5250 CurrentFormat = ELF;
5252 case MCObjectFileInfo::IsCOFF:
5253 CurrentFormat = COFF;
5257 if (~Prefix->SupportedFormats & CurrentFormat) {
5258 Error(Parser.getTok().getLoc(),
5259 "cannot represent relocation in the current file format");
5263 RefKind = Prefix->VariantKind;
5266 if (getLexer().isNot(AsmToken::Colon)) {
5267 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5270 Parser.Lex(); // Eat the last ':'
5275 /// \brief Given a mnemonic, split out possible predication code and carry
5276 /// setting letters to form a canonical mnemonic and flags.
5278 // FIXME: Would be nice to autogen this.
5279 // FIXME: This is a bit of a maze of special cases.
5280 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5281 unsigned &PredicationCode,
5283 unsigned &ProcessorIMod,
5284 StringRef &ITMask) {
5285 PredicationCode = ARMCC::AL;
5286 CarrySetting = false;
5289 // Ignore some mnemonics we know aren't predicated forms.
5291 // FIXME: Would be nice to autogen this.
5292 if ((Mnemonic == "movs" && isThumb()) ||
5293 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
5294 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
5295 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
5296 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
5297 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
5298 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
5299 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
5300 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5301 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5302 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
5303 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5304 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5305 Mnemonic.startswith("vsel") || Mnemonic == "vins" || Mnemonic == "vmovx")
5308 // First, split out any predication code. Ignore mnemonics we know aren't
5309 // predicated but do have a carry-set and so weren't caught above.
5310 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5311 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5312 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5313 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5314 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5315 .Case("eq", ARMCC::EQ)
5316 .Case("ne", ARMCC::NE)
5317 .Case("hs", ARMCC::HS)
5318 .Case("cs", ARMCC::HS)
5319 .Case("lo", ARMCC::LO)
5320 .Case("cc", ARMCC::LO)
5321 .Case("mi", ARMCC::MI)
5322 .Case("pl", ARMCC::PL)
5323 .Case("vs", ARMCC::VS)
5324 .Case("vc", ARMCC::VC)
5325 .Case("hi", ARMCC::HI)
5326 .Case("ls", ARMCC::LS)
5327 .Case("ge", ARMCC::GE)
5328 .Case("lt", ARMCC::LT)
5329 .Case("gt", ARMCC::GT)
5330 .Case("le", ARMCC::LE)
5331 .Case("al", ARMCC::AL)
5334 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5335 PredicationCode = CC;
5339 // Next, determine if we have a carry setting bit. We explicitly ignore all
5340 // the instructions we know end in 's'.
5341 if (Mnemonic.endswith("s") &&
5342 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5343 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5344 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5345 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5346 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5347 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5348 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5349 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5350 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5351 (Mnemonic == "movs" && isThumb()))) {
5352 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5353 CarrySetting = true;
5356 // The "cps" instruction can have a interrupt mode operand which is glued into
5357 // the mnemonic. Check if this is the case, split it and parse the imod op
5358 if (Mnemonic.startswith("cps")) {
5359 // Split out any imod code.
5361 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5362 .Case("ie", ARM_PROC::IE)
5363 .Case("id", ARM_PROC::ID)
5366 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5367 ProcessorIMod = IMod;
5371 // The "it" instruction has the condition mask on the end of the mnemonic.
5372 if (Mnemonic.startswith("it")) {
5373 ITMask = Mnemonic.slice(2, Mnemonic.size());
5374 Mnemonic = Mnemonic.slice(0, 2);
5380 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5381 /// inclusion of carry set or predication code operands.
5383 // FIXME: It would be nice to autogen this.
5384 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5385 bool &CanAcceptCarrySet,
5386 bool &CanAcceptPredicationCode) {
5388 Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5389 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5390 Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
5391 Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
5392 Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
5393 Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
5394 Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5396 (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
5397 Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
5399 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5400 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5401 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5402 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5403 Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
5404 Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
5405 Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
5406 Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
5407 Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
5408 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5409 (FullInst.startswith("vmull") && FullInst.endswith(".p64")) ||
5410 Mnemonic == "vmovx" || Mnemonic == "vins") {
5411 // These mnemonics are never predicable
5412 CanAcceptPredicationCode = false;
5413 } else if (!isThumb()) {
5414 // Some instructions are only predicable in Thumb mode
5415 CanAcceptPredicationCode =
5416 Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5417 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5418 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5419 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5420 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" &&
5421 Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") &&
5422 !Mnemonic.startswith("srs");
5423 } else if (isThumbOne()) {
5425 CanAcceptPredicationCode = Mnemonic != "movs";
5427 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5429 CanAcceptPredicationCode = true;
5432 // \brief Some Thumb instructions have two operand forms that are not
5433 // available as three operand, convert to two operand form if possible.
5435 // FIXME: We would really like to be able to tablegen'erate this.
5436 void ARMAsmParser::tryConvertingToTwoOperandForm(StringRef Mnemonic,
5438 OperandVector &Operands) {
5439 if (Operands.size() != 6)
5442 const auto &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5443 auto &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5444 if (!Op3.isReg() || !Op4.isReg())
5447 auto Op3Reg = Op3.getReg();
5448 auto Op4Reg = Op4.getReg();
5450 // For most Thumb2 cases we just generate the 3 operand form and reduce
5451 // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
5452 // won't accept SP or PC so we do the transformation here taking care
5453 // with immediate range in the 'add sp, sp #imm' case.
5454 auto &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5456 if (Mnemonic != "add")
5458 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
5459 (Op5.isReg() && Op5.getReg() == ARM::PC);
5460 if (!TryTransform) {
5461 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
5462 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
5463 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
5464 Op5.isImm() && !Op5.isImm0_508s4());
5468 } else if (!isThumbOne())
5471 if (!(Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5472 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5473 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5474 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic"))
5477 // If first 2 operands of a 3 operand instruction are the same
5478 // then transform to 2 operand version of the same instruction
5479 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5480 bool Transform = Op3Reg == Op4Reg;
5482 // For communtative operations, we might be able to transform if we swap
5483 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
5485 const ARMOperand *LastOp = &Op5;
5487 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
5488 ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
5489 Mnemonic == "and" || Mnemonic == "eor" ||
5490 Mnemonic == "adc" || Mnemonic == "orr")) {
5496 // If both registers are the same then remove one of them from
5497 // the operand list, with certain exceptions.
5499 // Don't transform 'adds Rd, Rd, Rm' or 'sub{s} Rd, Rd, Rm' because the
5500 // 2 operand forms don't exist.
5501 if (((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub") &&
5505 // Don't transform 'add/sub{s} Rd, Rd, #imm' if the immediate fits into
5506 // 3-bits because the ARMARM says not to.
5507 if ((Mnemonic == "add" || Mnemonic == "sub") && LastOp->isImm0_7())
5513 std::swap(Op4, Op5);
5514 Operands.erase(Operands.begin() + 3);
5518 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5519 OperandVector &Operands) {
5520 // FIXME: This is all horribly hacky. We really need a better way to deal
5521 // with optional operands like this in the matcher table.
5523 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5524 // another does not. Specifically, the MOVW instruction does not. So we
5525 // special case it here and remove the defaulted (non-setting) cc_out
5526 // operand if that's the instruction we're trying to match.
5528 // We do this as post-processing of the explicit operands rather than just
5529 // conditionally adding the cc_out in the first place because we need
5530 // to check the type of the parsed immediate operand.
5531 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5532 !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
5533 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5534 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5537 // Register-register 'add' for thumb does not have a cc_out operand
5538 // when there are only two register operands.
5539 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5540 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5541 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5542 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5544 // Register-register 'add' for thumb does not have a cc_out operand
5545 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5546 // have to check the immediate range here since Thumb2 has a variant
5547 // that can handle a different range and has a cc_out operand.
5548 if (((isThumb() && Mnemonic == "add") ||
5549 (isThumbTwo() && Mnemonic == "sub")) &&
5550 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5551 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5552 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5553 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5554 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5555 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5557 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5558 // imm0_4095 variant. That's the least-preferred variant when
5559 // selecting via the generic "add" mnemonic, so to know that we
5560 // should remove the cc_out operand, we have to explicitly check that
5561 // it's not one of the other variants. Ugh.
5562 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5563 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5564 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5565 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5566 // Nest conditions rather than one big 'if' statement for readability.
5568 // If both registers are low, we're in an IT block, and the immediate is
5569 // in range, we should use encoding T1 instead, which has a cc_out.
5571 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5572 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5573 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5575 // Check against T3. If the second register is the PC, this is an
5576 // alternate form of ADR, which uses encoding T4, so check for that too.
5577 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5578 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5581 // Otherwise, we use encoding T4, which does not have a cc_out
5586 // The thumb2 multiply instruction doesn't have a CCOut register, so
5587 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5588 // use the 16-bit encoding or not.
5589 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5590 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5591 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5592 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5593 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5594 // If the registers aren't low regs, the destination reg isn't the
5595 // same as one of the source regs, or the cc_out operand is zero
5596 // outside of an IT block, we have to use the 32-bit encoding, so
5597 // remove the cc_out operand.
5598 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5599 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5600 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5601 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5602 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5603 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5604 static_cast<ARMOperand &>(*Operands[4]).getReg())))
5607 // Also check the 'mul' syntax variant that doesn't specify an explicit
5608 // destination register.
5609 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5610 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5611 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5612 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5613 // If the registers aren't low regs or the cc_out operand is zero
5614 // outside of an IT block, we have to use the 32-bit encoding, so
5615 // remove the cc_out operand.
5616 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5617 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5623 // Register-register 'add/sub' for thumb does not have a cc_out operand
5624 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5625 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5626 // right, this will result in better diagnostics (which operand is off)
5628 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5629 (Operands.size() == 5 || Operands.size() == 6) &&
5630 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5631 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5632 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5633 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5634 (Operands.size() == 6 &&
5635 static_cast<ARMOperand &>(*Operands[5]).isImm())))
5641 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5642 OperandVector &Operands) {
5643 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5644 unsigned RegIdx = 3;
5645 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5646 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5647 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5648 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5651 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5652 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5653 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5654 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5655 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5661 static bool isDataTypeToken(StringRef Tok) {
5662 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5663 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5664 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5665 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5666 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5667 Tok == ".f" || Tok == ".d";
5670 // FIXME: This bit should probably be handled via an explicit match class
5671 // in the .td files that matches the suffix instead of having it be
5672 // a literal string token the way it is now.
5673 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5674 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5676 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5677 unsigned VariantID);
5679 static bool RequiresVFPRegListValidation(StringRef Inst,
5680 bool &AcceptSinglePrecisionOnly,
5681 bool &AcceptDoublePrecisionOnly) {
5682 if (Inst.size() < 7)
5685 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5686 StringRef AddressingMode = Inst.substr(4, 2);
5687 if (AddressingMode == "ia" || AddressingMode == "db" ||
5688 AddressingMode == "ea" || AddressingMode == "fd") {
5689 AcceptSinglePrecisionOnly = Inst[6] == 's';
5690 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5698 /// Parse an arm instruction mnemonic followed by its operands.
5699 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5700 SMLoc NameLoc, OperandVector &Operands) {
5701 MCAsmParser &Parser = getParser();
5702 // FIXME: Can this be done via tablegen in some fashion?
5703 bool RequireVFPRegisterListCheck;
5704 bool AcceptSinglePrecisionOnly;
5705 bool AcceptDoublePrecisionOnly;
5706 RequireVFPRegisterListCheck =
5707 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5708 AcceptDoublePrecisionOnly);
5710 // Apply mnemonic aliases before doing anything else, as the destination
5711 // mnemonic may include suffices and we want to handle them normally.
5712 // The generic tblgen'erated code does this later, at the start of
5713 // MatchInstructionImpl(), but that's too late for aliases that include
5714 // any sort of suffix.
5715 uint64_t AvailableFeatures = getAvailableFeatures();
5716 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5717 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5719 // First check for the ARM-specific .req directive.
5720 if (Parser.getTok().is(AsmToken::Identifier) &&
5721 Parser.getTok().getIdentifier() == ".req") {
5722 parseDirectiveReq(Name, NameLoc);
5723 // We always return 'error' for this, as we're done with this
5724 // statement and don't need to match the 'instruction."
5728 // Create the leading tokens for the mnemonic, split by '.' characters.
5729 size_t Start = 0, Next = Name.find('.');
5730 StringRef Mnemonic = Name.slice(Start, Next);
5732 // Split out the predication code and carry setting flag from the mnemonic.
5733 unsigned PredicationCode;
5734 unsigned ProcessorIMod;
5737 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5738 ProcessorIMod, ITMask);
5740 // In Thumb1, only the branch (B) instruction can be predicated.
5741 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5742 Parser.eatToEndOfStatement();
5743 return Error(NameLoc, "conditional execution not supported in Thumb1");
5746 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5748 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5749 // is the mask as it will be for the IT encoding if the conditional
5750 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5751 // where the conditional bit0 is zero, the instruction post-processing
5752 // will adjust the mask accordingly.
5753 if (Mnemonic == "it") {
5754 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5755 if (ITMask.size() > 3) {
5756 Parser.eatToEndOfStatement();
5757 return Error(Loc, "too many conditions on IT instruction");
5760 for (unsigned i = ITMask.size(); i != 0; --i) {
5761 char pos = ITMask[i - 1];
5762 if (pos != 't' && pos != 'e') {
5763 Parser.eatToEndOfStatement();
5764 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5767 if (ITMask[i - 1] == 't')
5770 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5773 // FIXME: This is all a pretty gross hack. We should automatically handle
5774 // optional operands like this via tblgen.
5776 // Next, add the CCOut and ConditionCode operands, if needed.
5778 // For mnemonics which can ever incorporate a carry setting bit or predication
5779 // code, our matching model involves us always generating CCOut and
5780 // ConditionCode operands to match the mnemonic "as written" and then we let
5781 // the matcher deal with finding the right instruction or generating an
5782 // appropriate error.
5783 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5784 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5786 // If we had a carry-set on an instruction that can't do that, issue an
5788 if (!CanAcceptCarrySet && CarrySetting) {
5789 Parser.eatToEndOfStatement();
5790 return Error(NameLoc, "instruction '" + Mnemonic +
5791 "' can not set flags, but 's' suffix specified");
5793 // If we had a predication code on an instruction that can't do that, issue an
5795 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5796 Parser.eatToEndOfStatement();
5797 return Error(NameLoc, "instruction '" + Mnemonic +
5798 "' is not predicable, but condition code specified");
5801 // Add the carry setting operand, if necessary.
5802 if (CanAcceptCarrySet) {
5803 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5804 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5808 // Add the predication code operand, if necessary.
5809 if (CanAcceptPredicationCode) {
5810 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5812 Operands.push_back(ARMOperand::CreateCondCode(
5813 ARMCC::CondCodes(PredicationCode), Loc));
5816 // Add the processor imod operand, if necessary.
5817 if (ProcessorIMod) {
5818 Operands.push_back(ARMOperand::CreateImm(
5819 MCConstantExpr::create(ProcessorIMod, getContext()),
5821 } else if (Mnemonic == "cps" && isMClass()) {
5822 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
5825 // Add the remaining tokens in the mnemonic.
5826 while (Next != StringRef::npos) {
5828 Next = Name.find('.', Start + 1);
5829 StringRef ExtraToken = Name.slice(Start, Next);
5831 // Some NEON instructions have an optional datatype suffix that is
5832 // completely ignored. Check for that.
5833 if (isDataTypeToken(ExtraToken) &&
5834 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5837 // For for ARM mode generate an error if the .n qualifier is used.
5838 if (ExtraToken == ".n" && !isThumb()) {
5839 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5840 Parser.eatToEndOfStatement();
5841 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5845 // The .n qualifier is always discarded as that is what the tables
5846 // and matcher expect. In ARM mode the .w qualifier has no effect,
5847 // so discard it to avoid errors that can be caused by the matcher.
5848 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5849 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5850 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5854 // Read the remaining operands.
5855 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5856 // Read the first operand.
5857 if (parseOperand(Operands, Mnemonic)) {
5858 Parser.eatToEndOfStatement();
5862 while (getLexer().is(AsmToken::Comma)) {
5863 Parser.Lex(); // Eat the comma.
5865 // Parse and remember the operand.
5866 if (parseOperand(Operands, Mnemonic)) {
5867 Parser.eatToEndOfStatement();
5873 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5874 SMLoc Loc = getLexer().getLoc();
5875 Parser.eatToEndOfStatement();
5876 return Error(Loc, "unexpected token in argument list");
5879 Parser.Lex(); // Consume the EndOfStatement
5881 if (RequireVFPRegisterListCheck) {
5882 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5883 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5884 return Error(Op.getStartLoc(),
5885 "VFP/Neon single precision register expected");
5886 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5887 return Error(Op.getStartLoc(),
5888 "VFP/Neon double precision register expected");
5891 tryConvertingToTwoOperandForm(Mnemonic, CarrySetting, Operands);
5893 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5894 // do and don't have a cc_out optional-def operand. With some spot-checks
5895 // of the operand list, we can figure out which variant we're trying to
5896 // parse and adjust accordingly before actually matching. We shouldn't ever
5897 // try to remove a cc_out operand that was explicitly set on the
5898 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5899 // table driven matcher doesn't fit well with the ARM instruction set.
5900 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5901 Operands.erase(Operands.begin() + 1);
5903 // Some instructions have the same mnemonic, but don't always
5904 // have a predicate. Distinguish them here and delete the
5905 // predicate if needed.
5906 if (shouldOmitPredicateOperand(Mnemonic, Operands))
5907 Operands.erase(Operands.begin() + 1);
5909 // ARM mode 'blx' need special handling, as the register operand version
5910 // is predicable, but the label operand version is not. So, we can't rely
5911 // on the Mnemonic based checking to correctly figure out when to put
5912 // a k_CondCode operand in the list. If we're trying to match the label
5913 // version, remove the k_CondCode operand here.
5914 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5915 static_cast<ARMOperand &>(*Operands[2]).isImm())
5916 Operands.erase(Operands.begin() + 1);
5918 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5919 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5920 // a single GPRPair reg operand is used in the .td file to replace the two
5921 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5922 // expressed as a GPRPair, so we have to manually merge them.
5923 // FIXME: We would really like to be able to tablegen'erate this.
5924 if (!isThumb() && Operands.size() > 4 &&
5925 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5926 Mnemonic == "stlexd")) {
5927 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5928 unsigned Idx = isLoad ? 2 : 3;
5929 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5930 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5932 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5933 // Adjust only if Op1 and Op2 are GPRs.
5934 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5935 MRC.contains(Op2.getReg())) {
5936 unsigned Reg1 = Op1.getReg();
5937 unsigned Reg2 = Op2.getReg();
5938 unsigned Rt = MRI->getEncodingValue(Reg1);
5939 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5941 // Rt2 must be Rt + 1 and Rt must be even.
5942 if (Rt + 1 != Rt2 || (Rt & 1)) {
5943 Error(Op2.getStartLoc(), isLoad
5944 ? "destination operands must be sequential"
5945 : "source operands must be sequential");
5948 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5949 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5951 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5952 Operands.erase(Operands.begin() + Idx + 1);
5956 // GNU Assembler extension (compatibility)
5957 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5958 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5959 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5961 assert(Op2.isReg() && "expected register argument");
5963 unsigned SuperReg = MRI->getMatchingSuperReg(
5964 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5966 assert(SuperReg && "expected register pair");
5968 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5971 Operands.begin() + 3,
5972 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5976 // FIXME: As said above, this is all a pretty gross hack. This instruction
5977 // does not fit with other "subs" and tblgen.
5978 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5979 // so the Mnemonic is the original name "subs" and delete the predicate
5980 // operand so it will match the table entry.
5981 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5982 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5983 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5984 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5985 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5986 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5987 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5988 Operands.erase(Operands.begin() + 1);
5993 // Validate context-sensitive operand constraints.
5995 // return 'true' if register list contains non-low GPR registers,
5996 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5997 // 'containsReg' to true.
5998 static bool checkLowRegisterList(const MCInst &Inst, unsigned OpNo,
5999 unsigned Reg, unsigned HiReg,
6000 bool &containsReg) {
6001 containsReg = false;
6002 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6003 unsigned OpReg = Inst.getOperand(i).getReg();
6006 // Anything other than a low register isn't legal here.
6007 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6013 // Check if the specified regisgter is in the register list of the inst,
6014 // starting at the indicated operand number.
6015 static bool listContainsReg(const MCInst &Inst, unsigned OpNo, unsigned Reg) {
6016 for (unsigned i = OpNo, e = Inst.getNumOperands(); i < e; ++i) {
6017 unsigned OpReg = Inst.getOperand(i).getReg();
6024 // Return true if instruction has the interesting property of being
6025 // allowed in IT blocks, but not being predicable.
6026 static bool instIsBreakpoint(const MCInst &Inst) {
6027 return Inst.getOpcode() == ARM::tBKPT ||
6028 Inst.getOpcode() == ARM::BKPT ||
6029 Inst.getOpcode() == ARM::tHLT ||
6030 Inst.getOpcode() == ARM::HLT;
6034 bool ARMAsmParser::validatetLDMRegList(const MCInst &Inst,
6035 const OperandVector &Operands,
6036 unsigned ListNo, bool IsARPop) {
6037 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6038 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6040 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6041 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6042 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6044 if (!IsARPop && ListContainsSP)
6045 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6046 "SP may not be in the register list");
6047 else if (ListContainsPC && ListContainsLR)
6048 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6049 "PC and LR may not be in the register list simultaneously");
6050 else if (inITBlock() && !lastInITBlock() && ListContainsPC)
6051 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6052 "instruction must be outside of IT block or the last "
6053 "instruction in an IT block");
6057 bool ARMAsmParser::validatetSTMRegList(const MCInst &Inst,
6058 const OperandVector &Operands,
6060 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6061 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6063 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6064 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6066 if (ListContainsSP && ListContainsPC)
6067 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6068 "SP and PC may not be in the register list");
6069 else if (ListContainsSP)
6070 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6071 "SP may not be in the register list");
6072 else if (ListContainsPC)
6073 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6074 "PC may not be in the register list");
6078 // FIXME: We would really like to be able to tablegen'erate this.
6079 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6080 const OperandVector &Operands) {
6081 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6082 SMLoc Loc = Operands[0]->getStartLoc();
6084 // Check the IT block state first.
6085 // NOTE: BKPT and HLT instructions have the interesting property of being
6086 // allowed in IT blocks, but not being predicable. They just always execute.
6087 if (inITBlock() && !instIsBreakpoint(Inst)) {
6089 if (ITState.FirstCond)
6090 ITState.FirstCond = false;
6092 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
6093 // The instruction must be predicable.
6094 if (!MCID.isPredicable())
6095 return Error(Loc, "instructions in IT block must be predicable");
6096 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6097 unsigned ITCond = Bit ? ITState.Cond :
6098 ARMCC::getOppositeCondition(ITState.Cond);
6099 if (Cond != ITCond) {
6100 // Find the condition code Operand to get its SMLoc information.
6102 for (unsigned I = 1; I < Operands.size(); ++I)
6103 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6104 CondLoc = Operands[I]->getStartLoc();
6105 return Error(CondLoc, "incorrect condition in IT block; got '" +
6106 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
6107 "', but expected '" +
6108 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
6110 // Check for non-'al' condition codes outside of the IT block.
6111 } else if (isThumbTwo() && MCID.isPredicable() &&
6112 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6113 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6114 Inst.getOpcode() != ARM::t2Bcc)
6115 return Error(Loc, "predicated instructions must be in IT block");
6117 const unsigned Opcode = Inst.getOpcode();
6121 case ARM::LDRD_POST: {
6122 const unsigned RtReg = Inst.getOperand(0).getReg();
6125 if (RtReg == ARM::LR)
6126 return Error(Operands[3]->getStartLoc(),
6129 const unsigned Rt = MRI->getEncodingValue(RtReg);
6130 // Rt must be even-numbered.
6132 return Error(Operands[3]->getStartLoc(),
6133 "Rt must be even-numbered");
6135 // Rt2 must be Rt + 1.
6136 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6138 return Error(Operands[3]->getStartLoc(),
6139 "destination operands must be sequential");
6141 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
6142 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6143 // For addressing modes with writeback, the base register needs to be
6144 // different from the destination registers.
6145 if (Rn == Rt || Rn == Rt2)
6146 return Error(Operands[3]->getStartLoc(),
6147 "base register needs to be different from destination "
6154 case ARM::t2LDRD_PRE:
6155 case ARM::t2LDRD_POST: {
6156 // Rt2 must be different from Rt.
6157 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6158 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6160 return Error(Operands[3]->getStartLoc(),
6161 "destination operands can't be identical");
6165 const unsigned RmReg = Inst.getOperand(0).getReg();
6166 // Rm = SP is no longer unpredictable in v8-A
6167 if (RmReg == ARM::SP && !hasV8Ops())
6168 return Error(Operands[2]->getStartLoc(),
6169 "r13 (SP) is an unpredictable operand to BXJ");
6173 // Rt2 must be Rt + 1.
6174 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6175 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6177 return Error(Operands[3]->getStartLoc(),
6178 "source operands must be sequential");
6182 case ARM::STRD_POST: {
6183 // Rt2 must be Rt + 1.
6184 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6185 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6187 return Error(Operands[3]->getStartLoc(),
6188 "source operands must be sequential");
6191 case ARM::STR_PRE_IMM:
6192 case ARM::STR_PRE_REG:
6193 case ARM::STR_POST_IMM:
6194 case ARM::STR_POST_REG:
6196 case ARM::STRH_POST:
6197 case ARM::STRB_PRE_IMM:
6198 case ARM::STRB_PRE_REG:
6199 case ARM::STRB_POST_IMM:
6200 case ARM::STRB_POST_REG: {
6201 // Rt must be different from Rn.
6202 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6203 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6206 return Error(Operands[3]->getStartLoc(),
6207 "source register and base register can't be identical");
6210 case ARM::LDR_PRE_IMM:
6211 case ARM::LDR_PRE_REG:
6212 case ARM::LDR_POST_IMM:
6213 case ARM::LDR_POST_REG:
6215 case ARM::LDRH_POST:
6216 case ARM::LDRSH_PRE:
6217 case ARM::LDRSH_POST:
6218 case ARM::LDRB_PRE_IMM:
6219 case ARM::LDRB_PRE_REG:
6220 case ARM::LDRB_POST_IMM:
6221 case ARM::LDRB_POST_REG:
6222 case ARM::LDRSB_PRE:
6223 case ARM::LDRSB_POST: {
6224 // Rt must be different from Rn.
6225 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6226 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6229 return Error(Operands[3]->getStartLoc(),
6230 "destination register and base register can't be identical");
6235 // Width must be in range [1, 32-lsb].
6236 unsigned LSB = Inst.getOperand(2).getImm();
6237 unsigned Widthm1 = Inst.getOperand(3).getImm();
6238 if (Widthm1 >= 32 - LSB)
6239 return Error(Operands[5]->getStartLoc(),
6240 "bitfield width must be in range [1,32-lsb]");
6243 // Notionally handles ARM::tLDMIA_UPD too.
6245 // If we're parsing Thumb2, the .w variant is available and handles
6246 // most cases that are normally illegal for a Thumb1 LDM instruction.
6247 // We'll make the transformation in processInstruction() if necessary.
6249 // Thumb LDM instructions are writeback iff the base register is not
6250 // in the register list.
6251 unsigned Rn = Inst.getOperand(0).getReg();
6252 bool HasWritebackToken =
6253 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6254 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6255 bool ListContainsBase;
6256 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6257 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6258 "registers must be in range r0-r7");
6259 // If we should have writeback, then there should be a '!' token.
6260 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6261 return Error(Operands[2]->getStartLoc(),
6262 "writeback operator '!' expected");
6263 // If we should not have writeback, there must not be a '!'. This is
6264 // true even for the 32-bit wide encodings.
6265 if (ListContainsBase && HasWritebackToken)
6266 return Error(Operands[3]->getStartLoc(),
6267 "writeback operator '!' not allowed when base register "
6268 "in register list");
6270 if (validatetLDMRegList(Inst, Operands, 3))
6274 case ARM::LDMIA_UPD:
6275 case ARM::LDMDB_UPD:
6276 case ARM::LDMIB_UPD:
6277 case ARM::LDMDA_UPD:
6278 // ARM variants loading and updating the same register are only officially
6279 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6282 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6283 return Error(Operands.back()->getStartLoc(),
6284 "writeback register not allowed in register list");
6288 if (validatetLDMRegList(Inst, Operands, 3))
6293 if (validatetSTMRegList(Inst, Operands, 3))
6296 case ARM::t2LDMIA_UPD:
6297 case ARM::t2LDMDB_UPD:
6298 case ARM::t2STMIA_UPD:
6299 case ARM::t2STMDB_UPD: {
6300 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6301 return Error(Operands.back()->getStartLoc(),
6302 "writeback register not allowed in register list");
6304 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
6305 if (validatetLDMRegList(Inst, Operands, 3))
6308 if (validatetSTMRegList(Inst, Operands, 3))
6313 case ARM::sysLDMIA_UPD:
6314 case ARM::sysLDMDA_UPD:
6315 case ARM::sysLDMDB_UPD:
6316 case ARM::sysLDMIB_UPD:
6317 if (!listContainsReg(Inst, 3, ARM::PC))
6318 return Error(Operands[4]->getStartLoc(),
6319 "writeback register only allowed on system LDM "
6320 "if PC in register-list");
6322 case ARM::sysSTMIA_UPD:
6323 case ARM::sysSTMDA_UPD:
6324 case ARM::sysSTMDB_UPD:
6325 case ARM::sysSTMIB_UPD:
6326 return Error(Operands[2]->getStartLoc(),
6327 "system STM cannot have writeback register");
6329 // The second source operand must be the same register as the destination
6332 // In this case, we must directly check the parsed operands because the
6333 // cvtThumbMultiply() function is written in such a way that it guarantees
6334 // this first statement is always true for the new Inst. Essentially, the
6335 // destination is unconditionally copied into the second source operand
6336 // without checking to see if it matches what we actually parsed.
6337 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6338 ((ARMOperand &)*Operands[5]).getReg()) &&
6339 (((ARMOperand &)*Operands[3]).getReg() !=
6340 ((ARMOperand &)*Operands[4]).getReg())) {
6341 return Error(Operands[3]->getStartLoc(),
6342 "destination register must match source register");
6346 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6347 // so only issue a diagnostic for thumb1. The instructions will be
6348 // switched to the t2 encodings in processInstruction() if necessary.
6350 bool ListContainsBase;
6351 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6353 return Error(Operands[2]->getStartLoc(),
6354 "registers must be in range r0-r7 or pc");
6355 if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6360 bool ListContainsBase;
6361 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6363 return Error(Operands[2]->getStartLoc(),
6364 "registers must be in range r0-r7 or lr");
6365 if (validatetSTMRegList(Inst, Operands, 2))
6369 case ARM::tSTMIA_UPD: {
6370 bool ListContainsBase, InvalidLowList;
6371 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6372 0, ListContainsBase);
6373 if (InvalidLowList && !isThumbTwo())
6374 return Error(Operands[4]->getStartLoc(),
6375 "registers must be in range r0-r7");
6377 // This would be converted to a 32-bit stm, but that's not valid if the
6378 // writeback register is in the list.
6379 if (InvalidLowList && ListContainsBase)
6380 return Error(Operands[4]->getStartLoc(),
6381 "writeback operator '!' not allowed when base register "
6382 "in register list");
6384 if (validatetSTMRegList(Inst, Operands, 4))
6388 case ARM::tADDrSP: {
6389 // If the non-SP source operand and the destination operand are not the
6390 // same, we need thumb2 (for the wide encoding), or we have an error.
6391 if (!isThumbTwo() &&
6392 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6393 return Error(Operands[4]->getStartLoc(),
6394 "source register must be the same as destination");
6398 // Final range checking for Thumb unconditional branch instructions.
6400 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6401 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6404 int op = (Operands[2]->isImm()) ? 2 : 3;
6405 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6406 return Error(Operands[op]->getStartLoc(), "branch target out of range");
6409 // Final range checking for Thumb conditional branch instructions.
6411 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6412 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6415 int Op = (Operands[2]->isImm()) ? 2 : 3;
6416 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6417 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6422 case ARM::t2MOVTi16:
6424 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6425 // especially when we turn it into a movw and the expression <symbol> does
6426 // not have a :lower16: or :upper16 as part of the expression. We don't
6427 // want the behavior of silently truncating, which can be unexpected and
6428 // lead to bugs that are difficult to find since this is an easy mistake
6430 int i = (Operands[3]->isImm()) ? 3 : 4;
6431 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6432 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6434 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6436 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6437 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6438 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6441 "immediate expression for mov requires :lower16: or :upper16");
6449 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6451 default: llvm_unreachable("unexpected opcode!");
6453 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6454 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6455 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6456 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6457 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6458 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6459 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
6460 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6461 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6464 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6465 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6466 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6467 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6468 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6470 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6471 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6472 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6473 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6474 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6476 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
6477 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6478 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6479 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6480 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6483 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6484 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6485 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6486 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6487 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6488 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6489 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6490 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6491 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6492 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6493 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
6494 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6495 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6496 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6497 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6500 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6501 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6502 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6503 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6504 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6505 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6506 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6507 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6508 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6509 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6510 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6511 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6512 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6513 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6514 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6515 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6516 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6517 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6520 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6521 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6522 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6523 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6524 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6525 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6526 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6527 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6528 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6529 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6530 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6531 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6532 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6533 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6534 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6537 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6538 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6539 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6540 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6541 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6542 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6543 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6544 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6545 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6546 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6547 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6548 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6549 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6550 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6551 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6552 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6553 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6554 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6558 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6560 default: llvm_unreachable("unexpected opcode!");
6562 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6563 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6564 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6565 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6566 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6567 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6568 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6569 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6570 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6573 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6574 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6575 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6576 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6577 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6578 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6579 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6580 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6581 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6582 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6583 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6584 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6585 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6586 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6587 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6590 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6591 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6592 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6593 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6594 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6595 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6596 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6597 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6598 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6599 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6600 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6601 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6602 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6603 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6604 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6605 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6606 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6607 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6610 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6611 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6612 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6613 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6614 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6615 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6616 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6617 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6618 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6619 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6620 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6621 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6622 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6623 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6624 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6627 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6628 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6629 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6630 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6631 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6632 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6633 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6634 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6635 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6636 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6637 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6638 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6639 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6640 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6641 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6642 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6643 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6644 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6647 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6648 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6649 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6650 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6651 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6652 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6653 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6654 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6655 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6656 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6657 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6658 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6659 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6660 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6661 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6664 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6665 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6666 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6667 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6668 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6669 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6670 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6671 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6672 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6673 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6674 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6675 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6676 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6677 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6678 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6679 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6680 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6681 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6684 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6685 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6686 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6687 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6688 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6689 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6690 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6691 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6692 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6693 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6694 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6695 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6696 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6697 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6698 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6699 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6700 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6701 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6705 bool ARMAsmParser::processInstruction(MCInst &Inst,
6706 const OperandVector &Operands,
6708 switch (Inst.getOpcode()) {
6709 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6710 case ARM::LDRT_POST:
6711 case ARM::LDRBT_POST: {
6712 const unsigned Opcode =
6713 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6714 : ARM::LDRBT_POST_IMM;
6716 TmpInst.setOpcode(Opcode);
6717 TmpInst.addOperand(Inst.getOperand(0));
6718 TmpInst.addOperand(Inst.getOperand(1));
6719 TmpInst.addOperand(Inst.getOperand(1));
6720 TmpInst.addOperand(MCOperand::createReg(0));
6721 TmpInst.addOperand(MCOperand::createImm(0));
6722 TmpInst.addOperand(Inst.getOperand(2));
6723 TmpInst.addOperand(Inst.getOperand(3));
6727 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6728 case ARM::STRT_POST:
6729 case ARM::STRBT_POST: {
6730 const unsigned Opcode =
6731 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6732 : ARM::STRBT_POST_IMM;
6734 TmpInst.setOpcode(Opcode);
6735 TmpInst.addOperand(Inst.getOperand(1));
6736 TmpInst.addOperand(Inst.getOperand(0));
6737 TmpInst.addOperand(Inst.getOperand(1));
6738 TmpInst.addOperand(MCOperand::createReg(0));
6739 TmpInst.addOperand(MCOperand::createImm(0));
6740 TmpInst.addOperand(Inst.getOperand(2));
6741 TmpInst.addOperand(Inst.getOperand(3));
6745 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6747 if (Inst.getOperand(1).getReg() != ARM::PC ||
6748 Inst.getOperand(5).getReg() != 0 ||
6749 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
6752 TmpInst.setOpcode(ARM::ADR);
6753 TmpInst.addOperand(Inst.getOperand(0));
6754 if (Inst.getOperand(2).isImm()) {
6755 // Immediate (mod_imm) will be in its encoded form, we must unencode it
6756 // before passing it to the ADR instruction.
6757 unsigned Enc = Inst.getOperand(2).getImm();
6758 TmpInst.addOperand(MCOperand::createImm(
6759 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
6761 // Turn PC-relative expression into absolute expression.
6762 // Reading PC provides the start of the current instruction + 8 and
6763 // the transform to adr is biased by that.
6764 MCSymbol *Dot = getContext().createTempSymbol();
6766 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
6767 const MCExpr *InstPC = MCSymbolRefExpr::create(Dot,
6768 MCSymbolRefExpr::VK_None,
6770 const MCExpr *Const8 = MCConstantExpr::create(8, getContext());
6771 const MCExpr *ReadPC = MCBinaryExpr::createAdd(InstPC, Const8,
6773 const MCExpr *FixupAddr = MCBinaryExpr::createAdd(ReadPC, OpExpr,
6775 TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
6777 TmpInst.addOperand(Inst.getOperand(3));
6778 TmpInst.addOperand(Inst.getOperand(4));
6782 // Aliases for alternate PC+imm syntax of LDR instructions.
6783 case ARM::t2LDRpcrel:
6784 // Select the narrow version if the immediate will fit.
6785 if (Inst.getOperand(1).getImm() > 0 &&
6786 Inst.getOperand(1).getImm() <= 0xff &&
6787 !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6788 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6789 Inst.setOpcode(ARM::tLDRpci);
6791 Inst.setOpcode(ARM::t2LDRpci);
6793 case ARM::t2LDRBpcrel:
6794 Inst.setOpcode(ARM::t2LDRBpci);
6796 case ARM::t2LDRHpcrel:
6797 Inst.setOpcode(ARM::t2LDRHpci);
6799 case ARM::t2LDRSBpcrel:
6800 Inst.setOpcode(ARM::t2LDRSBpci);
6802 case ARM::t2LDRSHpcrel:
6803 Inst.setOpcode(ARM::t2LDRSHpci);
6805 // Handle NEON VST complex aliases.
6806 case ARM::VST1LNdWB_register_Asm_8:
6807 case ARM::VST1LNdWB_register_Asm_16:
6808 case ARM::VST1LNdWB_register_Asm_32: {
6810 // Shuffle the operands around so the lane index operand is in the
6813 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6814 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6815 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6816 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6817 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6818 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6819 TmpInst.addOperand(Inst.getOperand(1)); // lane
6820 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6821 TmpInst.addOperand(Inst.getOperand(6));
6826 case ARM::VST2LNdWB_register_Asm_8:
6827 case ARM::VST2LNdWB_register_Asm_16:
6828 case ARM::VST2LNdWB_register_Asm_32:
6829 case ARM::VST2LNqWB_register_Asm_16:
6830 case ARM::VST2LNqWB_register_Asm_32: {
6832 // Shuffle the operands around so the lane index operand is in the
6835 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6836 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6837 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6838 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6839 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6840 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6841 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6843 TmpInst.addOperand(Inst.getOperand(1)); // lane
6844 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6845 TmpInst.addOperand(Inst.getOperand(6));
6850 case ARM::VST3LNdWB_register_Asm_8:
6851 case ARM::VST3LNdWB_register_Asm_16:
6852 case ARM::VST3LNdWB_register_Asm_32:
6853 case ARM::VST3LNqWB_register_Asm_16:
6854 case ARM::VST3LNqWB_register_Asm_32: {
6856 // Shuffle the operands around so the lane index operand is in the
6859 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6860 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6861 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6862 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6863 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6864 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6865 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6867 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6869 TmpInst.addOperand(Inst.getOperand(1)); // lane
6870 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6871 TmpInst.addOperand(Inst.getOperand(6));
6876 case ARM::VST4LNdWB_register_Asm_8:
6877 case ARM::VST4LNdWB_register_Asm_16:
6878 case ARM::VST4LNdWB_register_Asm_32:
6879 case ARM::VST4LNqWB_register_Asm_16:
6880 case ARM::VST4LNqWB_register_Asm_32: {
6882 // Shuffle the operands around so the lane index operand is in the
6885 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6886 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6887 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6888 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6889 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6890 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6891 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6893 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6895 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6897 TmpInst.addOperand(Inst.getOperand(1)); // lane
6898 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6899 TmpInst.addOperand(Inst.getOperand(6));
6904 case ARM::VST1LNdWB_fixed_Asm_8:
6905 case ARM::VST1LNdWB_fixed_Asm_16:
6906 case ARM::VST1LNdWB_fixed_Asm_32: {
6908 // Shuffle the operands around so the lane index operand is in the
6911 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6912 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6913 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6914 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6915 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6916 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6917 TmpInst.addOperand(Inst.getOperand(1)); // lane
6918 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6919 TmpInst.addOperand(Inst.getOperand(5));
6924 case ARM::VST2LNdWB_fixed_Asm_8:
6925 case ARM::VST2LNdWB_fixed_Asm_16:
6926 case ARM::VST2LNdWB_fixed_Asm_32:
6927 case ARM::VST2LNqWB_fixed_Asm_16:
6928 case ARM::VST2LNqWB_fixed_Asm_32: {
6930 // Shuffle the operands around so the lane index operand is in the
6933 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6934 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6935 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6936 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6937 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6938 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6939 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6941 TmpInst.addOperand(Inst.getOperand(1)); // lane
6942 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6943 TmpInst.addOperand(Inst.getOperand(5));
6948 case ARM::VST3LNdWB_fixed_Asm_8:
6949 case ARM::VST3LNdWB_fixed_Asm_16:
6950 case ARM::VST3LNdWB_fixed_Asm_32:
6951 case ARM::VST3LNqWB_fixed_Asm_16:
6952 case ARM::VST3LNqWB_fixed_Asm_32: {
6954 // Shuffle the operands around so the lane index operand is in the
6957 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6958 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6959 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6960 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6961 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6962 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6963 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6965 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6967 TmpInst.addOperand(Inst.getOperand(1)); // lane
6968 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6969 TmpInst.addOperand(Inst.getOperand(5));
6974 case ARM::VST4LNdWB_fixed_Asm_8:
6975 case ARM::VST4LNdWB_fixed_Asm_16:
6976 case ARM::VST4LNdWB_fixed_Asm_32:
6977 case ARM::VST4LNqWB_fixed_Asm_16:
6978 case ARM::VST4LNqWB_fixed_Asm_32: {
6980 // Shuffle the operands around so the lane index operand is in the
6983 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6984 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6985 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6986 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6987 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
6988 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6989 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6991 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6993 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
6995 TmpInst.addOperand(Inst.getOperand(1)); // lane
6996 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6997 TmpInst.addOperand(Inst.getOperand(5));
7002 case ARM::VST1LNdAsm_8:
7003 case ARM::VST1LNdAsm_16:
7004 case ARM::VST1LNdAsm_32: {
7006 // Shuffle the operands around so the lane index operand is in the
7009 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7010 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7011 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7012 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7013 TmpInst.addOperand(Inst.getOperand(1)); // lane
7014 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7015 TmpInst.addOperand(Inst.getOperand(5));
7020 case ARM::VST2LNdAsm_8:
7021 case ARM::VST2LNdAsm_16:
7022 case ARM::VST2LNdAsm_32:
7023 case ARM::VST2LNqAsm_16:
7024 case ARM::VST2LNqAsm_32: {
7026 // Shuffle the operands around so the lane index operand is in the
7029 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7030 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7031 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7032 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7033 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7035 TmpInst.addOperand(Inst.getOperand(1)); // lane
7036 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7037 TmpInst.addOperand(Inst.getOperand(5));
7042 case ARM::VST3LNdAsm_8:
7043 case ARM::VST3LNdAsm_16:
7044 case ARM::VST3LNdAsm_32:
7045 case ARM::VST3LNqAsm_16:
7046 case ARM::VST3LNqAsm_32: {
7048 // Shuffle the operands around so the lane index operand is in the
7051 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7052 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7053 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7054 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7055 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7057 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7059 TmpInst.addOperand(Inst.getOperand(1)); // lane
7060 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7061 TmpInst.addOperand(Inst.getOperand(5));
7066 case ARM::VST4LNdAsm_8:
7067 case ARM::VST4LNdAsm_16:
7068 case ARM::VST4LNdAsm_32:
7069 case ARM::VST4LNqAsm_16:
7070 case ARM::VST4LNqAsm_32: {
7072 // Shuffle the operands around so the lane index operand is in the
7075 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7076 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7077 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7078 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7079 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7081 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7083 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7085 TmpInst.addOperand(Inst.getOperand(1)); // lane
7086 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7087 TmpInst.addOperand(Inst.getOperand(5));
7092 // Handle NEON VLD complex aliases.
7093 case ARM::VLD1LNdWB_register_Asm_8:
7094 case ARM::VLD1LNdWB_register_Asm_16:
7095 case ARM::VLD1LNdWB_register_Asm_32: {
7097 // Shuffle the operands around so the lane index operand is in the
7100 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7101 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7102 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7103 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7104 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7105 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7106 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7107 TmpInst.addOperand(Inst.getOperand(1)); // lane
7108 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7109 TmpInst.addOperand(Inst.getOperand(6));
7114 case ARM::VLD2LNdWB_register_Asm_8:
7115 case ARM::VLD2LNdWB_register_Asm_16:
7116 case ARM::VLD2LNdWB_register_Asm_32:
7117 case ARM::VLD2LNqWB_register_Asm_16:
7118 case ARM::VLD2LNqWB_register_Asm_32: {
7120 // Shuffle the operands around so the lane index operand is in the
7123 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7124 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7125 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7127 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7128 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7129 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7130 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7131 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7132 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7134 TmpInst.addOperand(Inst.getOperand(1)); // lane
7135 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7136 TmpInst.addOperand(Inst.getOperand(6));
7141 case ARM::VLD3LNdWB_register_Asm_8:
7142 case ARM::VLD3LNdWB_register_Asm_16:
7143 case ARM::VLD3LNdWB_register_Asm_32:
7144 case ARM::VLD3LNqWB_register_Asm_16:
7145 case ARM::VLD3LNqWB_register_Asm_32: {
7147 // Shuffle the operands around so the lane index operand is in the
7150 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7151 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7152 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7154 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7156 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7157 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7158 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7159 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7160 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7161 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7163 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7165 TmpInst.addOperand(Inst.getOperand(1)); // lane
7166 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7167 TmpInst.addOperand(Inst.getOperand(6));
7172 case ARM::VLD4LNdWB_register_Asm_8:
7173 case ARM::VLD4LNdWB_register_Asm_16:
7174 case ARM::VLD4LNdWB_register_Asm_32:
7175 case ARM::VLD4LNqWB_register_Asm_16:
7176 case ARM::VLD4LNqWB_register_Asm_32: {
7178 // Shuffle the operands around so the lane index operand is in the
7181 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7182 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7183 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7185 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7187 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7189 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7190 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7191 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7192 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7193 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7194 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7196 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7198 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7200 TmpInst.addOperand(Inst.getOperand(1)); // lane
7201 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7202 TmpInst.addOperand(Inst.getOperand(6));
7207 case ARM::VLD1LNdWB_fixed_Asm_8:
7208 case ARM::VLD1LNdWB_fixed_Asm_16:
7209 case ARM::VLD1LNdWB_fixed_Asm_32: {
7211 // Shuffle the operands around so the lane index operand is in the
7214 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7215 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7216 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7217 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7218 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7219 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7220 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7221 TmpInst.addOperand(Inst.getOperand(1)); // lane
7222 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7223 TmpInst.addOperand(Inst.getOperand(5));
7228 case ARM::VLD2LNdWB_fixed_Asm_8:
7229 case ARM::VLD2LNdWB_fixed_Asm_16:
7230 case ARM::VLD2LNdWB_fixed_Asm_32:
7231 case ARM::VLD2LNqWB_fixed_Asm_16:
7232 case ARM::VLD2LNqWB_fixed_Asm_32: {
7234 // Shuffle the operands around so the lane index operand is in the
7237 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7238 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7239 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7241 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7242 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7243 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7244 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7245 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7246 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7248 TmpInst.addOperand(Inst.getOperand(1)); // lane
7249 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7250 TmpInst.addOperand(Inst.getOperand(5));
7255 case ARM::VLD3LNdWB_fixed_Asm_8:
7256 case ARM::VLD3LNdWB_fixed_Asm_16:
7257 case ARM::VLD3LNdWB_fixed_Asm_32:
7258 case ARM::VLD3LNqWB_fixed_Asm_16:
7259 case ARM::VLD3LNqWB_fixed_Asm_32: {
7261 // Shuffle the operands around so the lane index operand is in the
7264 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7265 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7266 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7268 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7270 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7271 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7272 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7273 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7274 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7275 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7277 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7279 TmpInst.addOperand(Inst.getOperand(1)); // lane
7280 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7281 TmpInst.addOperand(Inst.getOperand(5));
7286 case ARM::VLD4LNdWB_fixed_Asm_8:
7287 case ARM::VLD4LNdWB_fixed_Asm_16:
7288 case ARM::VLD4LNdWB_fixed_Asm_32:
7289 case ARM::VLD4LNqWB_fixed_Asm_16:
7290 case ARM::VLD4LNqWB_fixed_Asm_32: {
7292 // Shuffle the operands around so the lane index operand is in the
7295 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7296 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7297 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7299 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7301 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7303 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7304 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7305 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7306 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7307 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7308 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7310 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7312 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7314 TmpInst.addOperand(Inst.getOperand(1)); // lane
7315 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7316 TmpInst.addOperand(Inst.getOperand(5));
7321 case ARM::VLD1LNdAsm_8:
7322 case ARM::VLD1LNdAsm_16:
7323 case ARM::VLD1LNdAsm_32: {
7325 // Shuffle the operands around so the lane index operand is in the
7328 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7329 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7330 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7331 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7332 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7333 TmpInst.addOperand(Inst.getOperand(1)); // lane
7334 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7335 TmpInst.addOperand(Inst.getOperand(5));
7340 case ARM::VLD2LNdAsm_8:
7341 case ARM::VLD2LNdAsm_16:
7342 case ARM::VLD2LNdAsm_32:
7343 case ARM::VLD2LNqAsm_16:
7344 case ARM::VLD2LNqAsm_32: {
7346 // Shuffle the operands around so the lane index operand is in the
7349 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7350 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7351 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7353 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7354 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7355 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7356 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7358 TmpInst.addOperand(Inst.getOperand(1)); // lane
7359 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7360 TmpInst.addOperand(Inst.getOperand(5));
7365 case ARM::VLD3LNdAsm_8:
7366 case ARM::VLD3LNdAsm_16:
7367 case ARM::VLD3LNdAsm_32:
7368 case ARM::VLD3LNqAsm_16:
7369 case ARM::VLD3LNqAsm_32: {
7371 // Shuffle the operands around so the lane index operand is in the
7374 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7375 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7376 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7378 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7380 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7381 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7382 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7383 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7385 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7387 TmpInst.addOperand(Inst.getOperand(1)); // lane
7388 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7389 TmpInst.addOperand(Inst.getOperand(5));
7394 case ARM::VLD4LNdAsm_8:
7395 case ARM::VLD4LNdAsm_16:
7396 case ARM::VLD4LNdAsm_32:
7397 case ARM::VLD4LNqAsm_16:
7398 case ARM::VLD4LNqAsm_32: {
7400 // Shuffle the operands around so the lane index operand is in the
7403 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7404 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7405 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7407 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7409 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7411 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7412 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7413 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7414 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7416 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7418 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7420 TmpInst.addOperand(Inst.getOperand(1)); // lane
7421 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7422 TmpInst.addOperand(Inst.getOperand(5));
7427 // VLD3DUP single 3-element structure to all lanes instructions.
7428 case ARM::VLD3DUPdAsm_8:
7429 case ARM::VLD3DUPdAsm_16:
7430 case ARM::VLD3DUPdAsm_32:
7431 case ARM::VLD3DUPqAsm_8:
7432 case ARM::VLD3DUPqAsm_16:
7433 case ARM::VLD3DUPqAsm_32: {
7436 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7437 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7438 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7440 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7442 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7443 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7444 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7445 TmpInst.addOperand(Inst.getOperand(4));
7450 case ARM::VLD3DUPdWB_fixed_Asm_8:
7451 case ARM::VLD3DUPdWB_fixed_Asm_16:
7452 case ARM::VLD3DUPdWB_fixed_Asm_32:
7453 case ARM::VLD3DUPqWB_fixed_Asm_8:
7454 case ARM::VLD3DUPqWB_fixed_Asm_16:
7455 case ARM::VLD3DUPqWB_fixed_Asm_32: {
7458 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7459 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7460 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7462 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7464 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7465 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7466 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7467 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7468 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7469 TmpInst.addOperand(Inst.getOperand(4));
7474 case ARM::VLD3DUPdWB_register_Asm_8:
7475 case ARM::VLD3DUPdWB_register_Asm_16:
7476 case ARM::VLD3DUPdWB_register_Asm_32:
7477 case ARM::VLD3DUPqWB_register_Asm_8:
7478 case ARM::VLD3DUPqWB_register_Asm_16:
7479 case ARM::VLD3DUPqWB_register_Asm_32: {
7482 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7483 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7484 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7486 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7488 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7489 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7490 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7491 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7492 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7493 TmpInst.addOperand(Inst.getOperand(5));
7498 // VLD3 multiple 3-element structure instructions.
7499 case ARM::VLD3dAsm_8:
7500 case ARM::VLD3dAsm_16:
7501 case ARM::VLD3dAsm_32:
7502 case ARM::VLD3qAsm_8:
7503 case ARM::VLD3qAsm_16:
7504 case ARM::VLD3qAsm_32: {
7507 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7508 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7509 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7511 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7513 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7514 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7515 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7516 TmpInst.addOperand(Inst.getOperand(4));
7521 case ARM::VLD3dWB_fixed_Asm_8:
7522 case ARM::VLD3dWB_fixed_Asm_16:
7523 case ARM::VLD3dWB_fixed_Asm_32:
7524 case ARM::VLD3qWB_fixed_Asm_8:
7525 case ARM::VLD3qWB_fixed_Asm_16:
7526 case ARM::VLD3qWB_fixed_Asm_32: {
7529 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7530 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7531 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7533 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7535 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7536 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7537 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7538 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7539 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7540 TmpInst.addOperand(Inst.getOperand(4));
7545 case ARM::VLD3dWB_register_Asm_8:
7546 case ARM::VLD3dWB_register_Asm_16:
7547 case ARM::VLD3dWB_register_Asm_32:
7548 case ARM::VLD3qWB_register_Asm_8:
7549 case ARM::VLD3qWB_register_Asm_16:
7550 case ARM::VLD3qWB_register_Asm_32: {
7553 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7554 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7555 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7557 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7559 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7560 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7561 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7562 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7563 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7564 TmpInst.addOperand(Inst.getOperand(5));
7569 // VLD4DUP single 3-element structure to all lanes instructions.
7570 case ARM::VLD4DUPdAsm_8:
7571 case ARM::VLD4DUPdAsm_16:
7572 case ARM::VLD4DUPdAsm_32:
7573 case ARM::VLD4DUPqAsm_8:
7574 case ARM::VLD4DUPqAsm_16:
7575 case ARM::VLD4DUPqAsm_32: {
7578 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7579 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7580 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7582 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7584 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7586 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7587 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7588 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7589 TmpInst.addOperand(Inst.getOperand(4));
7594 case ARM::VLD4DUPdWB_fixed_Asm_8:
7595 case ARM::VLD4DUPdWB_fixed_Asm_16:
7596 case ARM::VLD4DUPdWB_fixed_Asm_32:
7597 case ARM::VLD4DUPqWB_fixed_Asm_8:
7598 case ARM::VLD4DUPqWB_fixed_Asm_16:
7599 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7602 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7603 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7604 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7606 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7608 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7610 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7611 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7612 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7613 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7614 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7615 TmpInst.addOperand(Inst.getOperand(4));
7620 case ARM::VLD4DUPdWB_register_Asm_8:
7621 case ARM::VLD4DUPdWB_register_Asm_16:
7622 case ARM::VLD4DUPdWB_register_Asm_32:
7623 case ARM::VLD4DUPqWB_register_Asm_8:
7624 case ARM::VLD4DUPqWB_register_Asm_16:
7625 case ARM::VLD4DUPqWB_register_Asm_32: {
7628 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7629 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7630 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7632 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7634 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7636 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7637 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7638 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7639 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7640 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7641 TmpInst.addOperand(Inst.getOperand(5));
7646 // VLD4 multiple 4-element structure instructions.
7647 case ARM::VLD4dAsm_8:
7648 case ARM::VLD4dAsm_16:
7649 case ARM::VLD4dAsm_32:
7650 case ARM::VLD4qAsm_8:
7651 case ARM::VLD4qAsm_16:
7652 case ARM::VLD4qAsm_32: {
7655 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7656 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7657 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7659 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7661 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7663 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7664 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7665 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7666 TmpInst.addOperand(Inst.getOperand(4));
7671 case ARM::VLD4dWB_fixed_Asm_8:
7672 case ARM::VLD4dWB_fixed_Asm_16:
7673 case ARM::VLD4dWB_fixed_Asm_32:
7674 case ARM::VLD4qWB_fixed_Asm_8:
7675 case ARM::VLD4qWB_fixed_Asm_16:
7676 case ARM::VLD4qWB_fixed_Asm_32: {
7679 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7680 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7681 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7683 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7685 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7687 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7688 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7689 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7690 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7691 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7692 TmpInst.addOperand(Inst.getOperand(4));
7697 case ARM::VLD4dWB_register_Asm_8:
7698 case ARM::VLD4dWB_register_Asm_16:
7699 case ARM::VLD4dWB_register_Asm_32:
7700 case ARM::VLD4qWB_register_Asm_8:
7701 case ARM::VLD4qWB_register_Asm_16:
7702 case ARM::VLD4qWB_register_Asm_32: {
7705 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7706 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7707 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7709 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7711 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7713 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7714 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7715 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7716 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7717 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7718 TmpInst.addOperand(Inst.getOperand(5));
7723 // VST3 multiple 3-element structure instructions.
7724 case ARM::VST3dAsm_8:
7725 case ARM::VST3dAsm_16:
7726 case ARM::VST3dAsm_32:
7727 case ARM::VST3qAsm_8:
7728 case ARM::VST3qAsm_16:
7729 case ARM::VST3qAsm_32: {
7732 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7733 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7734 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7735 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7736 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7738 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7740 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7741 TmpInst.addOperand(Inst.getOperand(4));
7746 case ARM::VST3dWB_fixed_Asm_8:
7747 case ARM::VST3dWB_fixed_Asm_16:
7748 case ARM::VST3dWB_fixed_Asm_32:
7749 case ARM::VST3qWB_fixed_Asm_8:
7750 case ARM::VST3qWB_fixed_Asm_16:
7751 case ARM::VST3qWB_fixed_Asm_32: {
7754 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7755 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7756 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7757 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7758 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7759 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7760 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7762 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7764 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7765 TmpInst.addOperand(Inst.getOperand(4));
7770 case ARM::VST3dWB_register_Asm_8:
7771 case ARM::VST3dWB_register_Asm_16:
7772 case ARM::VST3dWB_register_Asm_32:
7773 case ARM::VST3qWB_register_Asm_8:
7774 case ARM::VST3qWB_register_Asm_16:
7775 case ARM::VST3qWB_register_Asm_32: {
7778 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7779 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7780 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7781 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7782 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7783 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7784 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7786 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7788 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7789 TmpInst.addOperand(Inst.getOperand(5));
7794 // VST4 multiple 3-element structure instructions.
7795 case ARM::VST4dAsm_8:
7796 case ARM::VST4dAsm_16:
7797 case ARM::VST4dAsm_32:
7798 case ARM::VST4qAsm_8:
7799 case ARM::VST4qAsm_16:
7800 case ARM::VST4qAsm_32: {
7803 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7804 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7805 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7806 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7807 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7809 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7811 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7813 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7814 TmpInst.addOperand(Inst.getOperand(4));
7819 case ARM::VST4dWB_fixed_Asm_8:
7820 case ARM::VST4dWB_fixed_Asm_16:
7821 case ARM::VST4dWB_fixed_Asm_32:
7822 case ARM::VST4qWB_fixed_Asm_8:
7823 case ARM::VST4qWB_fixed_Asm_16:
7824 case ARM::VST4qWB_fixed_Asm_32: {
7827 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7828 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7829 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7830 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7831 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
7832 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7833 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7835 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7837 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7839 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7840 TmpInst.addOperand(Inst.getOperand(4));
7845 case ARM::VST4dWB_register_Asm_8:
7846 case ARM::VST4dWB_register_Asm_16:
7847 case ARM::VST4dWB_register_Asm_32:
7848 case ARM::VST4qWB_register_Asm_8:
7849 case ARM::VST4qWB_register_Asm_16:
7850 case ARM::VST4qWB_register_Asm_32: {
7853 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7854 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7855 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7856 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7857 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7858 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7859 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7861 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7863 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
7865 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7866 TmpInst.addOperand(Inst.getOperand(5));
7871 // Handle encoding choice for the shift-immediate instructions.
7874 case ARM::t2ASRri: {
7875 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7876 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7877 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7878 !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7879 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7881 switch (Inst.getOpcode()) {
7882 default: llvm_unreachable("unexpected opcode");
7883 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7884 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7885 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7887 // The Thumb1 operands aren't in the same order. Awesome, eh?
7889 TmpInst.setOpcode(NewOpc);
7890 TmpInst.addOperand(Inst.getOperand(0));
7891 TmpInst.addOperand(Inst.getOperand(5));
7892 TmpInst.addOperand(Inst.getOperand(1));
7893 TmpInst.addOperand(Inst.getOperand(2));
7894 TmpInst.addOperand(Inst.getOperand(3));
7895 TmpInst.addOperand(Inst.getOperand(4));
7902 // Handle the Thumb2 mode MOV complex aliases.
7904 case ARM::t2MOVSsr: {
7905 // Which instruction to expand to depends on the CCOut operand and
7906 // whether we're in an IT block if the register operands are low
7908 bool isNarrow = false;
7909 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7910 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7911 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7912 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7913 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7917 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7918 default: llvm_unreachable("unexpected opcode!");
7919 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7920 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7921 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7922 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7924 TmpInst.setOpcode(newOpc);
7925 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7927 TmpInst.addOperand(MCOperand::createReg(
7928 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7929 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7930 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7931 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7932 TmpInst.addOperand(Inst.getOperand(5));
7934 TmpInst.addOperand(MCOperand::createReg(
7935 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7940 case ARM::t2MOVSsi: {
7941 // Which instruction to expand to depends on the CCOut operand and
7942 // whether we're in an IT block if the register operands are low
7944 bool isNarrow = false;
7945 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7946 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7947 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7951 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7952 default: llvm_unreachable("unexpected opcode!");
7953 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7954 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7955 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7956 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7957 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7959 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7960 if (Amount == 32) Amount = 0;
7961 TmpInst.setOpcode(newOpc);
7962 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7964 TmpInst.addOperand(MCOperand::createReg(
7965 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7966 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7967 if (newOpc != ARM::t2RRX)
7968 TmpInst.addOperand(MCOperand::createImm(Amount));
7969 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7970 TmpInst.addOperand(Inst.getOperand(4));
7972 TmpInst.addOperand(MCOperand::createReg(
7973 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7977 // Handle the ARM mode MOV complex aliases.
7982 ARM_AM::ShiftOpc ShiftTy;
7983 switch(Inst.getOpcode()) {
7984 default: llvm_unreachable("unexpected opcode!");
7985 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7986 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7987 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7988 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7990 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7992 TmpInst.setOpcode(ARM::MOVsr);
7993 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7994 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7995 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7996 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
7997 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7998 TmpInst.addOperand(Inst.getOperand(4));
7999 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8007 ARM_AM::ShiftOpc ShiftTy;
8008 switch(Inst.getOpcode()) {
8009 default: llvm_unreachable("unexpected opcode!");
8010 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
8011 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
8012 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
8013 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
8015 // A shift by zero is a plain MOVr, not a MOVsi.
8016 unsigned Amt = Inst.getOperand(2).getImm();
8017 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
8018 // A shift by 32 should be encoded as 0 when permitted
8019 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
8021 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
8023 TmpInst.setOpcode(Opc);
8024 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8025 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8026 if (Opc == ARM::MOVsi)
8027 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8028 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8029 TmpInst.addOperand(Inst.getOperand(4));
8030 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8035 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
8037 TmpInst.setOpcode(ARM::MOVsi);
8038 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8039 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8040 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
8041 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8042 TmpInst.addOperand(Inst.getOperand(3));
8043 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8047 case ARM::t2LDMIA_UPD: {
8048 // If this is a load of a single register, then we should use
8049 // a post-indexed LDR instruction instead, per the ARM ARM.
8050 if (Inst.getNumOperands() != 5)
8053 TmpInst.setOpcode(ARM::t2LDR_POST);
8054 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8055 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8056 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8057 TmpInst.addOperand(MCOperand::createImm(4));
8058 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8059 TmpInst.addOperand(Inst.getOperand(3));
8063 case ARM::t2STMDB_UPD: {
8064 // If this is a store of a single register, then we should use
8065 // a pre-indexed STR instruction instead, per the ARM ARM.
8066 if (Inst.getNumOperands() != 5)
8069 TmpInst.setOpcode(ARM::t2STR_PRE);
8070 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8071 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8072 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8073 TmpInst.addOperand(MCOperand::createImm(-4));
8074 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8075 TmpInst.addOperand(Inst.getOperand(3));
8079 case ARM::LDMIA_UPD:
8080 // If this is a load of a single register via a 'pop', then we should use
8081 // a post-indexed LDR instruction instead, per the ARM ARM.
8082 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8083 Inst.getNumOperands() == 5) {
8085 TmpInst.setOpcode(ARM::LDR_POST_IMM);
8086 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8087 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8088 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8089 TmpInst.addOperand(MCOperand::createReg(0)); // am2offset
8090 TmpInst.addOperand(MCOperand::createImm(4));
8091 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8092 TmpInst.addOperand(Inst.getOperand(3));
8097 case ARM::STMDB_UPD:
8098 // If this is a store of a single register via a 'push', then we should use
8099 // a pre-indexed STR instruction instead, per the ARM ARM.
8100 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8101 Inst.getNumOperands() == 5) {
8103 TmpInst.setOpcode(ARM::STR_PRE_IMM);
8104 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8105 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8106 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8107 TmpInst.addOperand(MCOperand::createImm(-4));
8108 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8109 TmpInst.addOperand(Inst.getOperand(3));
8113 case ARM::t2ADDri12:
8114 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8115 // mnemonic was used (not "addw"), encoding T3 is preferred.
8116 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8117 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8119 Inst.setOpcode(ARM::t2ADDri);
8120 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8122 case ARM::t2SUBri12:
8123 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8124 // mnemonic was used (not "subw"), encoding T3 is preferred.
8125 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8126 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8128 Inst.setOpcode(ARM::t2SUBri);
8129 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8132 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8133 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8134 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8135 // to encoding T1 if <Rd> is omitted."
8136 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8137 Inst.setOpcode(ARM::tADDi3);
8142 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8143 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8144 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8145 // to encoding T1 if <Rd> is omitted."
8146 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8147 Inst.setOpcode(ARM::tSUBi3);
8152 case ARM::t2SUBri: {
8153 // If the destination and first source operand are the same, and
8154 // the flags are compatible with the current IT status, use encoding T2
8155 // instead of T3. For compatibility with the system 'as'. Make sure the
8156 // wide encoding wasn't explicit.
8157 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8158 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8159 (unsigned)Inst.getOperand(2).getImm() > 255 ||
8160 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8161 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8162 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8163 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8166 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8167 ARM::tADDi8 : ARM::tSUBi8);
8168 TmpInst.addOperand(Inst.getOperand(0));
8169 TmpInst.addOperand(Inst.getOperand(5));
8170 TmpInst.addOperand(Inst.getOperand(0));
8171 TmpInst.addOperand(Inst.getOperand(2));
8172 TmpInst.addOperand(Inst.getOperand(3));
8173 TmpInst.addOperand(Inst.getOperand(4));
8177 case ARM::t2ADDrr: {
8178 // If the destination and first source operand are the same, and
8179 // there's no setting of the flags, use encoding T2 instead of T3.
8180 // Note that this is only for ADD, not SUB. This mirrors the system
8181 // 'as' behaviour. Also take advantage of ADD being commutative.
8182 // Make sure the wide encoding wasn't explicit.
8184 auto DestReg = Inst.getOperand(0).getReg();
8185 bool Transform = DestReg == Inst.getOperand(1).getReg();
8186 if (!Transform && DestReg == Inst.getOperand(2).getReg()) {
8191 Inst.getOperand(5).getReg() != 0 ||
8192 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8193 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8196 TmpInst.setOpcode(ARM::tADDhirr);
8197 TmpInst.addOperand(Inst.getOperand(0));
8198 TmpInst.addOperand(Inst.getOperand(0));
8199 TmpInst.addOperand(Inst.getOperand(Swap ? 1 : 2));
8200 TmpInst.addOperand(Inst.getOperand(3));
8201 TmpInst.addOperand(Inst.getOperand(4));
8205 case ARM::tADDrSP: {
8206 // If the non-SP source operand and the destination operand are not the
8207 // same, we need to use the 32-bit encoding if it's available.
8208 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8209 Inst.setOpcode(ARM::t2ADDrr);
8210 Inst.addOperand(MCOperand::createReg(0)); // cc_out
8216 // A Thumb conditional branch outside of an IT block is a tBcc.
8217 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8218 Inst.setOpcode(ARM::tBcc);
8223 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8224 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8225 Inst.setOpcode(ARM::t2Bcc);
8230 // If the conditional is AL or we're in an IT block, we really want t2B.
8231 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8232 Inst.setOpcode(ARM::t2B);
8237 // If the conditional is AL, we really want tB.
8238 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8239 Inst.setOpcode(ARM::tB);
8244 // If the register list contains any high registers, or if the writeback
8245 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8246 // instead if we're in Thumb2. Otherwise, this should have generated
8247 // an error in validateInstruction().
8248 unsigned Rn = Inst.getOperand(0).getReg();
8249 bool hasWritebackToken =
8250 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8251 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8252 bool listContainsBase;
8253 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8254 (!listContainsBase && !hasWritebackToken) ||
8255 (listContainsBase && hasWritebackToken)) {
8256 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8257 assert (isThumbTwo());
8258 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8259 // If we're switching to the updating version, we need to insert
8260 // the writeback tied operand.
8261 if (hasWritebackToken)
8262 Inst.insert(Inst.begin(),
8263 MCOperand::createReg(Inst.getOperand(0).getReg()));
8268 case ARM::tSTMIA_UPD: {
8269 // If the register list contains any high registers, we need to use
8270 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8271 // should have generated an error in validateInstruction().
8272 unsigned Rn = Inst.getOperand(0).getReg();
8273 bool listContainsBase;
8274 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8275 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8276 assert (isThumbTwo());
8277 Inst.setOpcode(ARM::t2STMIA_UPD);
8283 bool listContainsBase;
8284 // If the register list contains any high registers, we need to use
8285 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8286 // should have generated an error in validateInstruction().
8287 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8289 assert (isThumbTwo());
8290 Inst.setOpcode(ARM::t2LDMIA_UPD);
8291 // Add the base register and writeback operands.
8292 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8293 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8297 bool listContainsBase;
8298 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8300 assert (isThumbTwo());
8301 Inst.setOpcode(ARM::t2STMDB_UPD);
8302 // Add the base register and writeback operands.
8303 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8304 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8308 // If we can use the 16-bit encoding and the user didn't explicitly
8309 // request the 32-bit variant, transform it here.
8310 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8311 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8312 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8313 Inst.getOperand(4).getReg() == ARM::CPSR) ||
8314 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8315 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8316 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8317 // The operands aren't in the same order for tMOVi8...
8319 TmpInst.setOpcode(ARM::tMOVi8);
8320 TmpInst.addOperand(Inst.getOperand(0));
8321 TmpInst.addOperand(Inst.getOperand(4));
8322 TmpInst.addOperand(Inst.getOperand(1));
8323 TmpInst.addOperand(Inst.getOperand(2));
8324 TmpInst.addOperand(Inst.getOperand(3));
8331 // If we can use the 16-bit encoding and the user didn't explicitly
8332 // request the 32-bit variant, transform it here.
8333 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8334 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8335 Inst.getOperand(2).getImm() == ARMCC::AL &&
8336 Inst.getOperand(4).getReg() == ARM::CPSR &&
8337 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8338 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8339 // The operands aren't the same for tMOV[S]r... (no cc_out)
8341 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8342 TmpInst.addOperand(Inst.getOperand(0));
8343 TmpInst.addOperand(Inst.getOperand(1));
8344 TmpInst.addOperand(Inst.getOperand(2));
8345 TmpInst.addOperand(Inst.getOperand(3));
8355 // If we can use the 16-bit encoding and the user didn't explicitly
8356 // request the 32-bit variant, transform it here.
8357 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8358 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8359 Inst.getOperand(2).getImm() == 0 &&
8360 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8361 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8363 switch (Inst.getOpcode()) {
8364 default: llvm_unreachable("Illegal opcode!");
8365 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8366 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8367 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8368 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8370 // The operands aren't the same for thumb1 (no rotate operand).
8372 TmpInst.setOpcode(NewOpc);
8373 TmpInst.addOperand(Inst.getOperand(0));
8374 TmpInst.addOperand(Inst.getOperand(1));
8375 TmpInst.addOperand(Inst.getOperand(3));
8376 TmpInst.addOperand(Inst.getOperand(4));
8383 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8384 // rrx shifts and asr/lsr of #32 is encoded as 0
8385 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8387 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8388 // Shifting by zero is accepted as a vanilla 'MOVr'
8390 TmpInst.setOpcode(ARM::MOVr);
8391 TmpInst.addOperand(Inst.getOperand(0));
8392 TmpInst.addOperand(Inst.getOperand(1));
8393 TmpInst.addOperand(Inst.getOperand(3));
8394 TmpInst.addOperand(Inst.getOperand(4));
8395 TmpInst.addOperand(Inst.getOperand(5));
8408 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8409 if (SOpc == ARM_AM::rrx) return false;
8410 switch (Inst.getOpcode()) {
8411 default: llvm_unreachable("unexpected opcode!");
8412 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8413 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8414 case ARM::EORrsi: newOpc = ARM::EORrr; break;
8415 case ARM::BICrsi: newOpc = ARM::BICrr; break;
8416 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8417 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8419 // If the shift is by zero, use the non-shifted instruction definition.
8420 // The exception is for right shifts, where 0 == 32
8421 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8422 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8424 TmpInst.setOpcode(newOpc);
8425 TmpInst.addOperand(Inst.getOperand(0));
8426 TmpInst.addOperand(Inst.getOperand(1));
8427 TmpInst.addOperand(Inst.getOperand(2));
8428 TmpInst.addOperand(Inst.getOperand(4));
8429 TmpInst.addOperand(Inst.getOperand(5));
8430 TmpInst.addOperand(Inst.getOperand(6));
8438 // The mask bits for all but the first condition are represented as
8439 // the low bit of the condition code value implies 't'. We currently
8440 // always have 1 implies 't', so XOR toggle the bits if the low bit
8441 // of the condition code is zero.
8442 MCOperand &MO = Inst.getOperand(1);
8443 unsigned Mask = MO.getImm();
8444 unsigned OrigMask = Mask;
8445 unsigned TZ = countTrailingZeros(Mask);
8446 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8447 assert(Mask && TZ <= 3 && "illegal IT mask value!");
8448 Mask ^= (0xE << TZ) & 0xF;
8452 // Set up the IT block state according to the IT instruction we just
8454 assert(!inITBlock() && "nested IT blocks?!");
8455 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8456 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8457 ITState.CurPosition = 0;
8458 ITState.FirstCond = true;
8468 // Assemblers should use the narrow encodings of these instructions when permissible.
8469 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8470 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8471 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8472 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8473 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8474 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8475 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8478 switch (Inst.getOpcode()) {
8479 default: llvm_unreachable("unexpected opcode");
8480 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8481 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8482 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8483 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8484 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8485 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8488 TmpInst.setOpcode(NewOpc);
8489 TmpInst.addOperand(Inst.getOperand(0));
8490 TmpInst.addOperand(Inst.getOperand(5));
8491 TmpInst.addOperand(Inst.getOperand(1));
8492 TmpInst.addOperand(Inst.getOperand(2));
8493 TmpInst.addOperand(Inst.getOperand(3));
8494 TmpInst.addOperand(Inst.getOperand(4));
8505 // Assemblers should use the narrow encodings of these instructions when permissible.
8506 // These instructions are special in that they are commutable, so shorter encodings
8507 // are available more often.
8508 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8509 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8510 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8511 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8512 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8513 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8514 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8515 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8518 switch (Inst.getOpcode()) {
8519 default: llvm_unreachable("unexpected opcode");
8520 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8521 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8522 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8523 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8526 TmpInst.setOpcode(NewOpc);
8527 TmpInst.addOperand(Inst.getOperand(0));
8528 TmpInst.addOperand(Inst.getOperand(5));
8529 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8530 TmpInst.addOperand(Inst.getOperand(1));
8531 TmpInst.addOperand(Inst.getOperand(2));
8533 TmpInst.addOperand(Inst.getOperand(2));
8534 TmpInst.addOperand(Inst.getOperand(1));
8536 TmpInst.addOperand(Inst.getOperand(3));
8537 TmpInst.addOperand(Inst.getOperand(4));
8547 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8548 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8549 // suffix depending on whether they're in an IT block or not.
8550 unsigned Opc = Inst.getOpcode();
8551 const MCInstrDesc &MCID = MII.get(Opc);
8552 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8553 assert(MCID.hasOptionalDef() &&
8554 "optionally flag setting instruction missing optional def operand");
8555 assert(MCID.NumOperands == Inst.getNumOperands() &&
8556 "operand count mismatch!");
8557 // Find the optional-def operand (cc_out).
8560 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8563 // If we're parsing Thumb1, reject it completely.
8564 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8565 return Match_MnemonicFail;
8566 // If we're parsing Thumb2, which form is legal depends on whether we're
8568 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8570 return Match_RequiresITBlock;
8571 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8573 return Match_RequiresNotITBlock;
8574 } else if (isThumbOne()) {
8575 // Some high-register supporting Thumb1 encodings only allow both registers
8576 // to be from r0-r7 when in Thumb2.
8577 if (Opc == ARM::tADDhirr && !hasV6MOps() &&
8578 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8579 isARMLowRegister(Inst.getOperand(2).getReg()))
8580 return Match_RequiresThumb2;
8581 // Others only require ARMv6 or later.
8582 else if (Opc == ARM::tMOVr && !hasV6Ops() &&
8583 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8584 isARMLowRegister(Inst.getOperand(1).getReg()))
8585 return Match_RequiresV6;
8588 for (unsigned I = 0; I < MCID.NumOperands; ++I)
8589 if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
8590 // rGPRRegClass excludes PC, and also excluded SP before ARMv8
8591 if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
8592 return Match_RequiresV8;
8593 else if (Inst.getOperand(I).getReg() == ARM::PC)
8594 return Match_InvalidOperand;
8597 return Match_Success;
8601 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8602 return true; // In an assembly source, no need to second-guess
8606 static const char *getSubtargetFeatureName(uint64_t Val);
8607 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8608 OperandVector &Operands,
8609 MCStreamer &Out, uint64_t &ErrorInfo,
8610 bool MatchingInlineAsm) {
8612 unsigned MatchResult;
8614 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8616 switch (MatchResult) {
8618 // Context sensitive operand constraints aren't handled by the matcher,
8619 // so check them here.
8620 if (validateInstruction(Inst, Operands)) {
8621 // Still progress the IT block, otherwise one wrong condition causes
8622 // nasty cascading errors.
8623 forwardITPosition();
8627 { // processInstruction() updates inITBlock state, we need to save it away
8628 bool wasInITBlock = inITBlock();
8630 // Some instructions need post-processing to, for example, tweak which
8631 // encoding is selected. Loop on it while changes happen so the
8632 // individual transformations can chain off each other. E.g.,
8633 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8634 while (processInstruction(Inst, Operands, Out))
8637 // Only after the instruction is fully processed, we can validate it
8638 if (wasInITBlock && hasV8Ops() && isThumb() &&
8639 !isV8EligibleForIT(&Inst)) {
8640 Warning(IDLoc, "deprecated instruction in IT block");
8644 // Only move forward at the very end so that everything in validate
8645 // and process gets a consistent answer about whether we're in an IT
8647 forwardITPosition();
8649 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8650 // doesn't actually encode.
8651 if (Inst.getOpcode() == ARM::ITasm)
8655 Out.EmitInstruction(Inst, getSTI());
8657 case Match_MissingFeature: {
8658 assert(ErrorInfo && "Unknown missing feature!");
8659 // Special case the error message for the very common case where only
8660 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8661 std::string Msg = "instruction requires:";
8663 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8664 if (ErrorInfo & Mask) {
8666 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8670 return Error(IDLoc, Msg);
8672 case Match_InvalidOperand: {
8673 SMLoc ErrorLoc = IDLoc;
8674 if (ErrorInfo != ~0ULL) {
8675 if (ErrorInfo >= Operands.size())
8676 return Error(IDLoc, "too few operands for instruction");
8678 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8679 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8682 return Error(ErrorLoc, "invalid operand for instruction");
8684 case Match_MnemonicFail:
8685 return Error(IDLoc, "invalid instruction",
8686 ((ARMOperand &)*Operands[0]).getLocRange());
8687 case Match_RequiresNotITBlock:
8688 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8689 case Match_RequiresITBlock:
8690 return Error(IDLoc, "instruction only valid inside IT block");
8691 case Match_RequiresV6:
8692 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8693 case Match_RequiresThumb2:
8694 return Error(IDLoc, "instruction variant requires Thumb2");
8695 case Match_RequiresV8:
8696 return Error(IDLoc, "instruction variant requires ARMv8 or later");
8697 case Match_ImmRange0_15: {
8698 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8699 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8700 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8702 case Match_ImmRange0_239: {
8703 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8704 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8705 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8707 case Match_AlignedMemoryRequiresNone:
8708 case Match_DupAlignedMemoryRequiresNone:
8709 case Match_AlignedMemoryRequires16:
8710 case Match_DupAlignedMemoryRequires16:
8711 case Match_AlignedMemoryRequires32:
8712 case Match_DupAlignedMemoryRequires32:
8713 case Match_AlignedMemoryRequires64:
8714 case Match_DupAlignedMemoryRequires64:
8715 case Match_AlignedMemoryRequires64or128:
8716 case Match_DupAlignedMemoryRequires64or128:
8717 case Match_AlignedMemoryRequires64or128or256:
8719 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8720 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8721 switch (MatchResult) {
8723 llvm_unreachable("Missing Match_Aligned type");
8724 case Match_AlignedMemoryRequiresNone:
8725 case Match_DupAlignedMemoryRequiresNone:
8726 return Error(ErrorLoc, "alignment must be omitted");
8727 case Match_AlignedMemoryRequires16:
8728 case Match_DupAlignedMemoryRequires16:
8729 return Error(ErrorLoc, "alignment must be 16 or omitted");
8730 case Match_AlignedMemoryRequires32:
8731 case Match_DupAlignedMemoryRequires32:
8732 return Error(ErrorLoc, "alignment must be 32 or omitted");
8733 case Match_AlignedMemoryRequires64:
8734 case Match_DupAlignedMemoryRequires64:
8735 return Error(ErrorLoc, "alignment must be 64 or omitted");
8736 case Match_AlignedMemoryRequires64or128:
8737 case Match_DupAlignedMemoryRequires64or128:
8738 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8739 case Match_AlignedMemoryRequires64or128or256:
8740 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8745 llvm_unreachable("Implement any new match types added!");
8748 /// parseDirective parses the arm specific directives
8749 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8750 const MCObjectFileInfo::Environment Format =
8751 getContext().getObjectFileInfo()->getObjectFileType();
8752 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8753 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
8755 StringRef IDVal = DirectiveID.getIdentifier();
8756 if (IDVal == ".word")
8757 return parseLiteralValues(4, DirectiveID.getLoc());
8758 else if (IDVal == ".short" || IDVal == ".hword")
8759 return parseLiteralValues(2, DirectiveID.getLoc());
8760 else if (IDVal == ".thumb")
8761 return parseDirectiveThumb(DirectiveID.getLoc());
8762 else if (IDVal == ".arm")
8763 return parseDirectiveARM(DirectiveID.getLoc());
8764 else if (IDVal == ".thumb_func")
8765 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8766 else if (IDVal == ".code")
8767 return parseDirectiveCode(DirectiveID.getLoc());
8768 else if (IDVal == ".syntax")
8769 return parseDirectiveSyntax(DirectiveID.getLoc());
8770 else if (IDVal == ".unreq")
8771 return parseDirectiveUnreq(DirectiveID.getLoc());
8772 else if (IDVal == ".fnend")
8773 return parseDirectiveFnEnd(DirectiveID.getLoc());
8774 else if (IDVal == ".cantunwind")
8775 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8776 else if (IDVal == ".personality")
8777 return parseDirectivePersonality(DirectiveID.getLoc());
8778 else if (IDVal == ".handlerdata")
8779 return parseDirectiveHandlerData(DirectiveID.getLoc());
8780 else if (IDVal == ".setfp")
8781 return parseDirectiveSetFP(DirectiveID.getLoc());
8782 else if (IDVal == ".pad")
8783 return parseDirectivePad(DirectiveID.getLoc());
8784 else if (IDVal == ".save")
8785 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8786 else if (IDVal == ".vsave")
8787 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8788 else if (IDVal == ".ltorg" || IDVal == ".pool")
8789 return parseDirectiveLtorg(DirectiveID.getLoc());
8790 else if (IDVal == ".even")
8791 return parseDirectiveEven(DirectiveID.getLoc());
8792 else if (IDVal == ".personalityindex")
8793 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8794 else if (IDVal == ".unwind_raw")
8795 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8796 else if (IDVal == ".movsp")
8797 return parseDirectiveMovSP(DirectiveID.getLoc());
8798 else if (IDVal == ".arch_extension")
8799 return parseDirectiveArchExtension(DirectiveID.getLoc());
8800 else if (IDVal == ".align")
8801 return parseDirectiveAlign(DirectiveID.getLoc());
8802 else if (IDVal == ".thumb_set")
8803 return parseDirectiveThumbSet(DirectiveID.getLoc());
8805 if (!IsMachO && !IsCOFF) {
8806 if (IDVal == ".arch")
8807 return parseDirectiveArch(DirectiveID.getLoc());
8808 else if (IDVal == ".cpu")
8809 return parseDirectiveCPU(DirectiveID.getLoc());
8810 else if (IDVal == ".eabi_attribute")
8811 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8812 else if (IDVal == ".fpu")
8813 return parseDirectiveFPU(DirectiveID.getLoc());
8814 else if (IDVal == ".fnstart")
8815 return parseDirectiveFnStart(DirectiveID.getLoc());
8816 else if (IDVal == ".inst")
8817 return parseDirectiveInst(DirectiveID.getLoc());
8818 else if (IDVal == ".inst.n")
8819 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8820 else if (IDVal == ".inst.w")
8821 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8822 else if (IDVal == ".object_arch")
8823 return parseDirectiveObjectArch(DirectiveID.getLoc());
8824 else if (IDVal == ".tlsdescseq")
8825 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8831 /// parseLiteralValues
8832 /// ::= .hword expression [, expression]*
8833 /// ::= .short expression [, expression]*
8834 /// ::= .word expression [, expression]*
8835 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8836 MCAsmParser &Parser = getParser();
8837 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8839 const MCExpr *Value;
8840 if (getParser().parseExpression(Value)) {
8841 Parser.eatToEndOfStatement();
8845 getParser().getStreamer().EmitValue(Value, Size, L);
8847 if (getLexer().is(AsmToken::EndOfStatement))
8850 // FIXME: Improve diagnostic.
8851 if (getLexer().isNot(AsmToken::Comma)) {
8852 Error(L, "unexpected token in directive");
8863 /// parseDirectiveThumb
8865 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8866 MCAsmParser &Parser = getParser();
8867 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8868 Error(L, "unexpected token in directive");
8874 Error(L, "target does not support Thumb mode");
8881 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8885 /// parseDirectiveARM
8887 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8888 MCAsmParser &Parser = getParser();
8889 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8890 Error(L, "unexpected token in directive");
8896 Error(L, "target does not support ARM mode");
8903 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8907 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8908 if (NextSymbolIsThumb) {
8909 getParser().getStreamer().EmitThumbFunc(Symbol);
8910 NextSymbolIsThumb = false;
8914 /// parseDirectiveThumbFunc
8915 /// ::= .thumbfunc symbol_name
8916 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8917 MCAsmParser &Parser = getParser();
8918 const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
8919 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8921 // Darwin asm has (optionally) function name after .thumb_func direction
8924 const AsmToken &Tok = Parser.getTok();
8925 if (Tok.isNot(AsmToken::EndOfStatement)) {
8926 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8927 Error(L, "unexpected token in .thumb_func directive");
8932 getParser().getContext().getOrCreateSymbol(Tok.getIdentifier());
8933 getParser().getStreamer().EmitThumbFunc(Func);
8934 Parser.Lex(); // Consume the identifier token.
8939 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8940 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8941 Parser.eatToEndOfStatement();
8945 NextSymbolIsThumb = true;
8949 /// parseDirectiveSyntax
8950 /// ::= .syntax unified | divided
8951 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8952 MCAsmParser &Parser = getParser();
8953 const AsmToken &Tok = Parser.getTok();
8954 if (Tok.isNot(AsmToken::Identifier)) {
8955 Error(L, "unexpected token in .syntax directive");
8959 StringRef Mode = Tok.getString();
8960 if (Mode == "unified" || Mode == "UNIFIED") {
8962 } else if (Mode == "divided" || Mode == "DIVIDED") {
8963 Error(L, "'.syntax divided' arm asssembly not supported");
8966 Error(L, "unrecognized syntax mode in .syntax directive");
8970 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8971 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8976 // TODO tell the MC streamer the mode
8977 // getParser().getStreamer().Emit???();
8981 /// parseDirectiveCode
8982 /// ::= .code 16 | 32
8983 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8984 MCAsmParser &Parser = getParser();
8985 const AsmToken &Tok = Parser.getTok();
8986 if (Tok.isNot(AsmToken::Integer)) {
8987 Error(L, "unexpected token in .code directive");
8990 int64_t Val = Parser.getTok().getIntVal();
8991 if (Val != 16 && Val != 32) {
8992 Error(L, "invalid operand to .code directive");
8997 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8998 Error(Parser.getTok().getLoc(), "unexpected token in directive");
9005 Error(L, "target does not support Thumb mode");
9011 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
9014 Error(L, "target does not support ARM mode");
9020 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
9026 /// parseDirectiveReq
9027 /// ::= name .req registername
9028 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
9029 MCAsmParser &Parser = getParser();
9030 Parser.Lex(); // Eat the '.req' token.
9032 SMLoc SRegLoc, ERegLoc;
9033 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
9034 Parser.eatToEndOfStatement();
9035 Error(SRegLoc, "register name expected");
9039 // Shouldn't be anything else.
9040 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
9041 Parser.eatToEndOfStatement();
9042 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
9046 Parser.Lex(); // Consume the EndOfStatement
9048 if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg) {
9049 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
9056 /// parseDirectiveUneq
9057 /// ::= .unreq registername
9058 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
9059 MCAsmParser &Parser = getParser();
9060 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9061 Parser.eatToEndOfStatement();
9062 Error(L, "unexpected input in .unreq directive.");
9065 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
9066 Parser.Lex(); // Eat the identifier.
9070 /// parseDirectiveArch
9072 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
9073 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
9075 unsigned ID = ARM::parseArch(Arch);
9077 if (ID == ARM::AK_INVALID) {
9078 Error(L, "Unknown arch name");
9083 MCSubtargetInfo &STI = copySTI();
9084 STI.setDefaultFeatures("", ("+" + ARM::getArchName(ID)).str());
9085 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9087 getTargetStreamer().emitArch(ID);
9091 /// parseDirectiveEabiAttr
9092 /// ::= .eabi_attribute int, int [, "str"]
9093 /// ::= .eabi_attribute Tag_name, int [, "str"]
9094 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9095 MCAsmParser &Parser = getParser();
9098 TagLoc = Parser.getTok().getLoc();
9099 if (Parser.getTok().is(AsmToken::Identifier)) {
9100 StringRef Name = Parser.getTok().getIdentifier();
9101 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9103 Error(TagLoc, "attribute name not recognised: " + Name);
9104 Parser.eatToEndOfStatement();
9109 const MCExpr *AttrExpr;
9111 TagLoc = Parser.getTok().getLoc();
9112 if (Parser.parseExpression(AttrExpr)) {
9113 Parser.eatToEndOfStatement();
9117 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9119 Error(TagLoc, "expected numeric constant");
9120 Parser.eatToEndOfStatement();
9124 Tag = CE->getValue();
9127 if (Parser.getTok().isNot(AsmToken::Comma)) {
9128 Error(Parser.getTok().getLoc(), "comma expected");
9129 Parser.eatToEndOfStatement();
9132 Parser.Lex(); // skip comma
9134 StringRef StringValue = "";
9135 bool IsStringValue = false;
9137 int64_t IntegerValue = 0;
9138 bool IsIntegerValue = false;
9140 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9141 IsStringValue = true;
9142 else if (Tag == ARMBuildAttrs::compatibility) {
9143 IsStringValue = true;
9144 IsIntegerValue = true;
9145 } else if (Tag < 32 || Tag % 2 == 0)
9146 IsIntegerValue = true;
9147 else if (Tag % 2 == 1)
9148 IsStringValue = true;
9150 llvm_unreachable("invalid tag type");
9152 if (IsIntegerValue) {
9153 const MCExpr *ValueExpr;
9154 SMLoc ValueExprLoc = Parser.getTok().getLoc();
9155 if (Parser.parseExpression(ValueExpr)) {
9156 Parser.eatToEndOfStatement();
9160 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9162 Error(ValueExprLoc, "expected numeric constant");
9163 Parser.eatToEndOfStatement();
9167 IntegerValue = CE->getValue();
9170 if (Tag == ARMBuildAttrs::compatibility) {
9171 if (Parser.getTok().isNot(AsmToken::Comma))
9172 IsStringValue = false;
9173 if (Parser.getTok().isNot(AsmToken::Comma)) {
9174 Error(Parser.getTok().getLoc(), "comma expected");
9175 Parser.eatToEndOfStatement();
9182 if (IsStringValue) {
9183 if (Parser.getTok().isNot(AsmToken::String)) {
9184 Error(Parser.getTok().getLoc(), "bad string constant");
9185 Parser.eatToEndOfStatement();
9189 StringValue = Parser.getTok().getStringContents();
9193 if (IsIntegerValue && IsStringValue) {
9194 assert(Tag == ARMBuildAttrs::compatibility);
9195 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9196 } else if (IsIntegerValue)
9197 getTargetStreamer().emitAttribute(Tag, IntegerValue);
9198 else if (IsStringValue)
9199 getTargetStreamer().emitTextAttribute(Tag, StringValue);
9203 /// parseDirectiveCPU
9205 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9206 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9207 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9209 // FIXME: This is using table-gen data, but should be moved to
9210 // ARMTargetParser once that is table-gen'd.
9211 if (!getSTI().isCPUStringValid(CPU)) {
9212 Error(L, "Unknown CPU name");
9216 MCSubtargetInfo &STI = copySTI();
9217 STI.setDefaultFeatures(CPU, "");
9218 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9222 /// parseDirectiveFPU
9224 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9225 SMLoc FPUNameLoc = getTok().getLoc();
9226 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9228 unsigned ID = ARM::parseFPU(FPU);
9229 std::vector<const char *> Features;
9230 if (!ARM::getFPUFeatures(ID, Features)) {
9231 Error(FPUNameLoc, "Unknown FPU name");
9235 MCSubtargetInfo &STI = copySTI();
9236 for (auto Feature : Features)
9237 STI.ApplyFeatureFlag(Feature);
9238 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9240 getTargetStreamer().emitFPU(ID);
9244 /// parseDirectiveFnStart
9246 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9247 if (UC.hasFnStart()) {
9248 Error(L, ".fnstart starts before the end of previous one");
9249 UC.emitFnStartLocNotes();
9253 // Reset the unwind directives parser state
9256 getTargetStreamer().emitFnStart();
9258 UC.recordFnStart(L);
9262 /// parseDirectiveFnEnd
9264 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9265 // Check the ordering of unwind directives
9266 if (!UC.hasFnStart()) {
9267 Error(L, ".fnstart must precede .fnend directive");
9271 // Reset the unwind directives parser state
9272 getTargetStreamer().emitFnEnd();
9278 /// parseDirectiveCantUnwind
9280 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9281 UC.recordCantUnwind(L);
9283 // Check the ordering of unwind directives
9284 if (!UC.hasFnStart()) {
9285 Error(L, ".fnstart must precede .cantunwind directive");
9288 if (UC.hasHandlerData()) {
9289 Error(L, ".cantunwind can't be used with .handlerdata directive");
9290 UC.emitHandlerDataLocNotes();
9293 if (UC.hasPersonality()) {
9294 Error(L, ".cantunwind can't be used with .personality directive");
9295 UC.emitPersonalityLocNotes();
9299 getTargetStreamer().emitCantUnwind();
9303 /// parseDirectivePersonality
9304 /// ::= .personality name
9305 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9306 MCAsmParser &Parser = getParser();
9307 bool HasExistingPersonality = UC.hasPersonality();
9309 UC.recordPersonality(L);
9311 // Check the ordering of unwind directives
9312 if (!UC.hasFnStart()) {
9313 Error(L, ".fnstart must precede .personality directive");
9316 if (UC.cantUnwind()) {
9317 Error(L, ".personality can't be used with .cantunwind directive");
9318 UC.emitCantUnwindLocNotes();
9321 if (UC.hasHandlerData()) {
9322 Error(L, ".personality must precede .handlerdata directive");
9323 UC.emitHandlerDataLocNotes();
9326 if (HasExistingPersonality) {
9327 Parser.eatToEndOfStatement();
9328 Error(L, "multiple personality directives");
9329 UC.emitPersonalityLocNotes();
9333 // Parse the name of the personality routine
9334 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9335 Parser.eatToEndOfStatement();
9336 Error(L, "unexpected input in .personality directive.");
9339 StringRef Name(Parser.getTok().getIdentifier());
9342 MCSymbol *PR = getParser().getContext().getOrCreateSymbol(Name);
9343 getTargetStreamer().emitPersonality(PR);
9347 /// parseDirectiveHandlerData
9348 /// ::= .handlerdata
9349 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9350 UC.recordHandlerData(L);
9352 // Check the ordering of unwind directives
9353 if (!UC.hasFnStart()) {
9354 Error(L, ".fnstart must precede .personality directive");
9357 if (UC.cantUnwind()) {
9358 Error(L, ".handlerdata can't be used with .cantunwind directive");
9359 UC.emitCantUnwindLocNotes();
9363 getTargetStreamer().emitHandlerData();
9367 /// parseDirectiveSetFP
9368 /// ::= .setfp fpreg, spreg [, offset]
9369 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9370 MCAsmParser &Parser = getParser();
9371 // Check the ordering of unwind directives
9372 if (!UC.hasFnStart()) {
9373 Error(L, ".fnstart must precede .setfp directive");
9376 if (UC.hasHandlerData()) {
9377 Error(L, ".setfp must precede .handlerdata directive");
9382 SMLoc FPRegLoc = Parser.getTok().getLoc();
9383 int FPReg = tryParseRegister();
9385 Error(FPRegLoc, "frame pointer register expected");
9390 if (Parser.getTok().isNot(AsmToken::Comma)) {
9391 Error(Parser.getTok().getLoc(), "comma expected");
9394 Parser.Lex(); // skip comma
9397 SMLoc SPRegLoc = Parser.getTok().getLoc();
9398 int SPReg = tryParseRegister();
9400 Error(SPRegLoc, "stack pointer register expected");
9404 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
9405 Error(SPRegLoc, "register should be either $sp or the latest fp register");
9409 // Update the frame pointer register
9410 UC.saveFPReg(FPReg);
9414 if (Parser.getTok().is(AsmToken::Comma)) {
9415 Parser.Lex(); // skip comma
9417 if (Parser.getTok().isNot(AsmToken::Hash) &&
9418 Parser.getTok().isNot(AsmToken::Dollar)) {
9419 Error(Parser.getTok().getLoc(), "'#' expected");
9422 Parser.Lex(); // skip hash token.
9424 const MCExpr *OffsetExpr;
9425 SMLoc ExLoc = Parser.getTok().getLoc();
9427 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9428 Error(ExLoc, "malformed setfp offset");
9431 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9433 Error(ExLoc, "setfp offset must be an immediate");
9437 Offset = CE->getValue();
9440 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9441 static_cast<unsigned>(SPReg), Offset);
9447 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9448 MCAsmParser &Parser = getParser();
9449 // Check the ordering of unwind directives
9450 if (!UC.hasFnStart()) {
9451 Error(L, ".fnstart must precede .pad directive");
9454 if (UC.hasHandlerData()) {
9455 Error(L, ".pad must precede .handlerdata directive");
9460 if (Parser.getTok().isNot(AsmToken::Hash) &&
9461 Parser.getTok().isNot(AsmToken::Dollar)) {
9462 Error(Parser.getTok().getLoc(), "'#' expected");
9465 Parser.Lex(); // skip hash token.
9467 const MCExpr *OffsetExpr;
9468 SMLoc ExLoc = Parser.getTok().getLoc();
9470 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9471 Error(ExLoc, "malformed pad offset");
9474 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9476 Error(ExLoc, "pad offset must be an immediate");
9480 getTargetStreamer().emitPad(CE->getValue());
9484 /// parseDirectiveRegSave
9485 /// ::= .save { registers }
9486 /// ::= .vsave { registers }
9487 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9488 // Check the ordering of unwind directives
9489 if (!UC.hasFnStart()) {
9490 Error(L, ".fnstart must precede .save or .vsave directives");
9493 if (UC.hasHandlerData()) {
9494 Error(L, ".save or .vsave must precede .handlerdata directive");
9498 // RAII object to make sure parsed operands are deleted.
9499 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9501 // Parse the register list
9502 if (parseRegisterList(Operands))
9504 ARMOperand &Op = (ARMOperand &)*Operands[0];
9505 if (!IsVector && !Op.isRegList()) {
9506 Error(L, ".save expects GPR registers");
9509 if (IsVector && !Op.isDPRRegList()) {
9510 Error(L, ".vsave expects DPR registers");
9514 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9518 /// parseDirectiveInst
9519 /// ::= .inst opcode [, ...]
9520 /// ::= .inst.n opcode [, ...]
9521 /// ::= .inst.w opcode [, ...]
9522 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9523 MCAsmParser &Parser = getParser();
9535 Parser.eatToEndOfStatement();
9536 Error(Loc, "cannot determine Thumb instruction size, "
9537 "use inst.n/inst.w instead");
9542 Parser.eatToEndOfStatement();
9543 Error(Loc, "width suffixes are invalid in ARM mode");
9549 if (getLexer().is(AsmToken::EndOfStatement)) {
9550 Parser.eatToEndOfStatement();
9551 Error(Loc, "expected expression following directive");
9558 if (getParser().parseExpression(Expr)) {
9559 Error(Loc, "expected expression");
9563 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9565 Error(Loc, "expected constant expression");
9571 if (Value->getValue() > 0xffff) {
9572 Error(Loc, "inst.n operand is too big, use inst.w instead");
9577 if (Value->getValue() > 0xffffffff) {
9579 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9584 llvm_unreachable("only supported widths are 2 and 4");
9587 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9589 if (getLexer().is(AsmToken::EndOfStatement))
9592 if (getLexer().isNot(AsmToken::Comma)) {
9593 Error(Loc, "unexpected token in directive");
9604 /// parseDirectiveLtorg
9605 /// ::= .ltorg | .pool
9606 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9607 getTargetStreamer().emitCurrentConstantPool();
9611 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9612 const MCSection *Section = getStreamer().getCurrentSection().first;
9614 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9615 TokError("unexpected token in directive");
9620 getStreamer().InitSections(false);
9621 Section = getStreamer().getCurrentSection().first;
9624 assert(Section && "must have section to emit alignment");
9625 if (Section->UseCodeAlign())
9626 getStreamer().EmitCodeAlignment(2);
9628 getStreamer().EmitValueToAlignment(2);
9633 /// parseDirectivePersonalityIndex
9634 /// ::= .personalityindex index
9635 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9636 MCAsmParser &Parser = getParser();
9637 bool HasExistingPersonality = UC.hasPersonality();
9639 UC.recordPersonalityIndex(L);
9641 if (!UC.hasFnStart()) {
9642 Parser.eatToEndOfStatement();
9643 Error(L, ".fnstart must precede .personalityindex directive");
9646 if (UC.cantUnwind()) {
9647 Parser.eatToEndOfStatement();
9648 Error(L, ".personalityindex cannot be used with .cantunwind");
9649 UC.emitCantUnwindLocNotes();
9652 if (UC.hasHandlerData()) {
9653 Parser.eatToEndOfStatement();
9654 Error(L, ".personalityindex must precede .handlerdata directive");
9655 UC.emitHandlerDataLocNotes();
9658 if (HasExistingPersonality) {
9659 Parser.eatToEndOfStatement();
9660 Error(L, "multiple personality directives");
9661 UC.emitPersonalityLocNotes();
9665 const MCExpr *IndexExpression;
9666 SMLoc IndexLoc = Parser.getTok().getLoc();
9667 if (Parser.parseExpression(IndexExpression)) {
9668 Parser.eatToEndOfStatement();
9672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9674 Parser.eatToEndOfStatement();
9675 Error(IndexLoc, "index must be a constant number");
9678 if (CE->getValue() < 0 ||
9679 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9680 Parser.eatToEndOfStatement();
9681 Error(IndexLoc, "personality routine index should be in range [0-3]");
9685 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9689 /// parseDirectiveUnwindRaw
9690 /// ::= .unwind_raw offset, opcode [, opcode...]
9691 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9692 MCAsmParser &Parser = getParser();
9693 if (!UC.hasFnStart()) {
9694 Parser.eatToEndOfStatement();
9695 Error(L, ".fnstart must precede .unwind_raw directives");
9699 int64_t StackOffset;
9701 const MCExpr *OffsetExpr;
9702 SMLoc OffsetLoc = getLexer().getLoc();
9703 if (getLexer().is(AsmToken::EndOfStatement) ||
9704 getParser().parseExpression(OffsetExpr)) {
9705 Error(OffsetLoc, "expected expression");
9706 Parser.eatToEndOfStatement();
9710 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9712 Error(OffsetLoc, "offset must be a constant");
9713 Parser.eatToEndOfStatement();
9717 StackOffset = CE->getValue();
9719 if (getLexer().isNot(AsmToken::Comma)) {
9720 Error(getLexer().getLoc(), "expected comma");
9721 Parser.eatToEndOfStatement();
9726 SmallVector<uint8_t, 16> Opcodes;
9730 SMLoc OpcodeLoc = getLexer().getLoc();
9731 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9732 Error(OpcodeLoc, "expected opcode expression");
9733 Parser.eatToEndOfStatement();
9737 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9739 Error(OpcodeLoc, "opcode value must be a constant");
9740 Parser.eatToEndOfStatement();
9744 const int64_t Opcode = OC->getValue();
9745 if (Opcode & ~0xff) {
9746 Error(OpcodeLoc, "invalid opcode");
9747 Parser.eatToEndOfStatement();
9751 Opcodes.push_back(uint8_t(Opcode));
9753 if (getLexer().is(AsmToken::EndOfStatement))
9756 if (getLexer().isNot(AsmToken::Comma)) {
9757 Error(getLexer().getLoc(), "unexpected token in directive");
9758 Parser.eatToEndOfStatement();
9765 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9771 /// parseDirectiveTLSDescSeq
9772 /// ::= .tlsdescseq tls-variable
9773 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9774 MCAsmParser &Parser = getParser();
9776 if (getLexer().isNot(AsmToken::Identifier)) {
9777 TokError("expected variable after '.tlsdescseq' directive");
9778 Parser.eatToEndOfStatement();
9782 const MCSymbolRefExpr *SRE =
9783 MCSymbolRefExpr::create(Parser.getTok().getIdentifier(),
9784 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9787 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9788 Error(Parser.getTok().getLoc(), "unexpected token");
9789 Parser.eatToEndOfStatement();
9793 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9797 /// parseDirectiveMovSP
9798 /// ::= .movsp reg [, #offset]
9799 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9800 MCAsmParser &Parser = getParser();
9801 if (!UC.hasFnStart()) {
9802 Parser.eatToEndOfStatement();
9803 Error(L, ".fnstart must precede .movsp directives");
9806 if (UC.getFPReg() != ARM::SP) {
9807 Parser.eatToEndOfStatement();
9808 Error(L, "unexpected .movsp directive");
9812 SMLoc SPRegLoc = Parser.getTok().getLoc();
9813 int SPReg = tryParseRegister();
9815 Parser.eatToEndOfStatement();
9816 Error(SPRegLoc, "register expected");
9820 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9821 Parser.eatToEndOfStatement();
9822 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9827 if (Parser.getTok().is(AsmToken::Comma)) {
9830 if (Parser.getTok().isNot(AsmToken::Hash)) {
9831 Error(Parser.getTok().getLoc(), "expected #constant");
9832 Parser.eatToEndOfStatement();
9837 const MCExpr *OffsetExpr;
9838 SMLoc OffsetLoc = Parser.getTok().getLoc();
9839 if (Parser.parseExpression(OffsetExpr)) {
9840 Parser.eatToEndOfStatement();
9841 Error(OffsetLoc, "malformed offset expression");
9845 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9847 Parser.eatToEndOfStatement();
9848 Error(OffsetLoc, "offset must be an immediate constant");
9852 Offset = CE->getValue();
9855 getTargetStreamer().emitMovSP(SPReg, Offset);
9856 UC.saveFPReg(SPReg);
9861 /// parseDirectiveObjectArch
9862 /// ::= .object_arch name
9863 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9864 MCAsmParser &Parser = getParser();
9865 if (getLexer().isNot(AsmToken::Identifier)) {
9866 Error(getLexer().getLoc(), "unexpected token");
9867 Parser.eatToEndOfStatement();
9871 StringRef Arch = Parser.getTok().getString();
9872 SMLoc ArchLoc = Parser.getTok().getLoc();
9875 unsigned ID = ARM::parseArch(Arch);
9877 if (ID == ARM::AK_INVALID) {
9878 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9879 Parser.eatToEndOfStatement();
9883 getTargetStreamer().emitObjectArch(ID);
9885 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9886 Error(getLexer().getLoc(), "unexpected token");
9887 Parser.eatToEndOfStatement();
9893 /// parseDirectiveAlign
9895 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9896 // NOTE: if this is not the end of the statement, fall back to the target
9897 // agnostic handling for this directive which will correctly handle this.
9898 if (getLexer().isNot(AsmToken::EndOfStatement))
9901 // '.align' is target specifically handled to mean 2**2 byte alignment.
9902 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9903 getStreamer().EmitCodeAlignment(4, 0);
9905 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9910 /// parseDirectiveThumbSet
9911 /// ::= .thumb_set name, value
9912 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9913 MCAsmParser &Parser = getParser();
9916 if (Parser.parseIdentifier(Name)) {
9917 TokError("expected identifier after '.thumb_set'");
9918 Parser.eatToEndOfStatement();
9922 if (getLexer().isNot(AsmToken::Comma)) {
9923 TokError("expected comma after name '" + Name + "'");
9924 Parser.eatToEndOfStatement();
9930 const MCExpr *Value;
9931 if (MCParserUtils::parseAssignmentExpression(Name, /* allow_redef */ true,
9932 Parser, Sym, Value))
9935 getTargetStreamer().emitThumbSet(Sym, Value);
9939 /// Force static initialization.
9940 extern "C" void LLVMInitializeARMAsmParser() {
9941 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9942 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9943 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9944 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9947 #define GET_REGISTER_MATCHER
9948 #define GET_SUBTARGET_FEATURE_NAME
9949 #define GET_MATCHER_IMPLEMENTATION
9950 #include "ARMGenAsmMatcher.inc"
9952 // FIXME: This structure should be moved inside ARMTargetParser
9953 // when we start to table-generate them, and we can use the ARM
9954 // flags below, that were generated by table-gen.
9955 static const struct {
9956 const unsigned Kind;
9957 const uint64_t ArchCheck;
9958 const FeatureBitset Features;
9960 { ARM::AEK_CRC, Feature_HasV8, {ARM::FeatureCRC} },
9961 { ARM::AEK_CRYPTO, Feature_HasV8,
9962 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9963 { ARM::AEK_FP, Feature_HasV8, {ARM::FeatureFPARMv8} },
9964 { (ARM::AEK_HWDIV | ARM::AEK_HWDIVARM), Feature_HasV7 | Feature_IsNotMClass,
9965 {ARM::FeatureHWDiv, ARM::FeatureHWDivARM} },
9966 { ARM::AEK_MP, Feature_HasV7 | Feature_IsNotMClass, {ARM::FeatureMP} },
9967 { ARM::AEK_SIMD, Feature_HasV8, {ARM::FeatureNEON, ARM::FeatureFPARMv8} },
9968 { ARM::AEK_SEC, Feature_HasV6K, {ARM::FeatureTrustZone} },
9969 // FIXME: Only available in A-class, isel not predicated
9970 { ARM::AEK_VIRT, Feature_HasV7, {ARM::FeatureVirtualization} },
9971 { ARM::AEK_FP16, Feature_HasV8_2a, {ARM::FeatureFPARMv8, ARM::FeatureFullFP16} },
9972 // FIXME: Unsupported extensions.
9973 { ARM::AEK_OS, Feature_None, {} },
9974 { ARM::AEK_IWMMXT, Feature_None, {} },
9975 { ARM::AEK_IWMMXT2, Feature_None, {} },
9976 { ARM::AEK_MAVERICK, Feature_None, {} },
9977 { ARM::AEK_XSCALE, Feature_None, {} },
9980 /// parseDirectiveArchExtension
9981 /// ::= .arch_extension [no]feature
9982 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
9983 MCAsmParser &Parser = getParser();
9985 if (getLexer().isNot(AsmToken::Identifier)) {
9986 Error(getLexer().getLoc(), "unexpected token");
9987 Parser.eatToEndOfStatement();
9991 StringRef Name = Parser.getTok().getString();
9992 SMLoc ExtLoc = Parser.getTok().getLoc();
9995 bool EnableFeature = true;
9996 if (Name.startswith_lower("no")) {
9997 EnableFeature = false;
9998 Name = Name.substr(2);
10000 unsigned FeatureKind = ARM::parseArchExt(Name);
10001 if (FeatureKind == ARM::AEK_INVALID)
10002 Error(ExtLoc, "unknown architectural extension: " + Name);
10004 for (const auto &Extension : Extensions) {
10005 if (Extension.Kind != FeatureKind)
10008 if (Extension.Features.none())
10009 report_fatal_error("unsupported architectural extension: " + Name);
10011 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
10012 Error(ExtLoc, "architectural extension '" + Name + "' is not "
10013 "allowed for the current base architecture");
10017 MCSubtargetInfo &STI = copySTI();
10018 FeatureBitset ToggleFeatures = EnableFeature
10019 ? (~STI.getFeatureBits() & Extension.Features)
10020 : ( STI.getFeatureBits() & Extension.Features);
10022 uint64_t Features =
10023 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
10024 setAvailableFeatures(Features);
10028 Error(ExtLoc, "unknown architectural extension: " + Name);
10029 Parser.eatToEndOfStatement();
10033 // Define this matcher function after the auto-generated include so we
10034 // have the match class enum definitions.
10035 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
10037 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
10038 // If the kind is a token for a literal immediate, check if our asm
10039 // operand matches. This is for InstAliases which have a fixed-value
10040 // immediate in the syntax.
10045 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
10046 if (CE->getValue() == 0)
10047 return Match_Success;
10051 const MCExpr *SOExpr = Op.getImm();
10053 if (!SOExpr->evaluateAsAbsolute(Value))
10054 return Match_Success;
10055 assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
10056 "expression value must be representable in 32 bits");
10060 if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
10061 return Match_Success;
10065 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10066 return Match_Success;
10069 return Match_InvalidOperand;