1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "ARMFeatures.h"
11 #include "MCTargetDesc/ARMAddressingModes.h"
12 #include "MCTargetDesc/ARMBaseInfo.h"
13 #include "MCTargetDesc/ARMMCExpr.h"
14 #include "llvm/ADT/STLExtras.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/StringSwitch.h"
18 #include "llvm/ADT/Twine.h"
19 #include "llvm/MC/MCAsmInfo.h"
20 #include "llvm/MC/MCAssembler.h"
21 #include "llvm/MC/MCContext.h"
22 #include "llvm/MC/MCDisassembler.h"
23 #include "llvm/MC/MCELFStreamer.h"
24 #include "llvm/MC/MCExpr.h"
25 #include "llvm/MC/MCInst.h"
26 #include "llvm/MC/MCInstrDesc.h"
27 #include "llvm/MC/MCInstrInfo.h"
28 #include "llvm/MC/MCObjectFileInfo.h"
29 #include "llvm/MC/MCParser/MCAsmLexer.h"
30 #include "llvm/MC/MCParser/MCAsmParser.h"
31 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
32 #include "llvm/MC/MCRegisterInfo.h"
33 #include "llvm/MC/MCSection.h"
34 #include "llvm/MC/MCStreamer.h"
35 #include "llvm/MC/MCSubtargetInfo.h"
36 #include "llvm/MC/MCSymbol.h"
37 #include "llvm/MC/MCTargetAsmParser.h"
38 #include "llvm/Support/ARMBuildAttributes.h"
39 #include "llvm/Support/ARMEHABI.h"
40 #include "llvm/Support/TargetParser.h"
41 #include "llvm/Support/COFF.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ELF.h"
44 #include "llvm/Support/MathExtras.h"
45 #include "llvm/Support/SourceMgr.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Support/raw_ostream.h"
55 enum VectorLaneTy { NoLanes, AllLanes, IndexedLane };
60 typedef SmallVector<SMLoc, 4> Locs;
65 Locs PersonalityIndexLocs;
70 UnwindContext(MCAsmParser &P) : Parser(P), FPReg(ARM::SP) {}
72 bool hasFnStart() const { return !FnStartLocs.empty(); }
73 bool cantUnwind() const { return !CantUnwindLocs.empty(); }
74 bool hasHandlerData() const { return !HandlerDataLocs.empty(); }
75 bool hasPersonality() const {
76 return !(PersonalityLocs.empty() && PersonalityIndexLocs.empty());
79 void recordFnStart(SMLoc L) { FnStartLocs.push_back(L); }
80 void recordCantUnwind(SMLoc L) { CantUnwindLocs.push_back(L); }
81 void recordPersonality(SMLoc L) { PersonalityLocs.push_back(L); }
82 void recordHandlerData(SMLoc L) { HandlerDataLocs.push_back(L); }
83 void recordPersonalityIndex(SMLoc L) { PersonalityIndexLocs.push_back(L); }
85 void saveFPReg(int Reg) { FPReg = Reg; }
86 int getFPReg() const { return FPReg; }
88 void emitFnStartLocNotes() const {
89 for (Locs::const_iterator FI = FnStartLocs.begin(), FE = FnStartLocs.end();
91 Parser.Note(*FI, ".fnstart was specified here");
93 void emitCantUnwindLocNotes() const {
94 for (Locs::const_iterator UI = CantUnwindLocs.begin(),
95 UE = CantUnwindLocs.end(); UI != UE; ++UI)
96 Parser.Note(*UI, ".cantunwind was specified here");
98 void emitHandlerDataLocNotes() const {
99 for (Locs::const_iterator HI = HandlerDataLocs.begin(),
100 HE = HandlerDataLocs.end(); HI != HE; ++HI)
101 Parser.Note(*HI, ".handlerdata was specified here");
103 void emitPersonalityLocNotes() const {
104 for (Locs::const_iterator PI = PersonalityLocs.begin(),
105 PE = PersonalityLocs.end(),
106 PII = PersonalityIndexLocs.begin(),
107 PIE = PersonalityIndexLocs.end();
108 PI != PE || PII != PIE;) {
109 if (PI != PE && (PII == PIE || PI->getPointer() < PII->getPointer()))
110 Parser.Note(*PI++, ".personality was specified here");
111 else if (PII != PIE && (PI == PE || PII->getPointer() < PI->getPointer()))
112 Parser.Note(*PII++, ".personalityindex was specified here");
114 llvm_unreachable(".personality and .personalityindex cannot be "
115 "at the same location");
120 FnStartLocs = Locs();
121 CantUnwindLocs = Locs();
122 PersonalityLocs = Locs();
123 HandlerDataLocs = Locs();
124 PersonalityIndexLocs = Locs();
129 class ARMAsmParser : public MCTargetAsmParser {
130 MCSubtargetInfo &STI;
131 const MCInstrInfo &MII;
132 const MCRegisterInfo *MRI;
135 ARMTargetStreamer &getTargetStreamer() {
136 assert(getParser().getStreamer().getTargetStreamer() &&
137 "do not have a target streamer");
138 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
139 return static_cast<ARMTargetStreamer &>(TS);
142 // Map of register aliases registers via the .req directive.
143 StringMap<unsigned> RegisterReqs;
145 bool NextSymbolIsThumb;
148 ARMCC::CondCodes Cond; // Condition for IT block.
149 unsigned Mask:4; // Condition mask for instructions.
150 // Starting at first 1 (from lsb).
151 // '1' condition as indicated in IT.
152 // '0' inverse of condition (else).
153 // Count of instructions in IT block is
154 // 4 - trailingzeroes(mask)
156 bool FirstCond; // Explicit flag for when we're parsing the
157 // First instruction in the IT block. It's
158 // implied in the mask, so needs special
161 unsigned CurPosition; // Current position in parsing of IT
162 // block. In range [0,3]. Initialized
163 // according to count of instructions in block.
164 // ~0U if no active IT block.
166 bool inITBlock() { return ITState.CurPosition != ~0U; }
167 bool lastInITBlock() {
168 return ITState.CurPosition == 4 - countTrailingZeros(ITState.Mask);
170 void forwardITPosition() {
171 if (!inITBlock()) return;
172 // Move to the next instruction in the IT block, if there is one. If not,
173 // mark the block as done.
174 unsigned TZ = countTrailingZeros(ITState.Mask);
175 if (++ITState.CurPosition == 5 - TZ)
176 ITState.CurPosition = ~0U; // Done with the IT block after this.
179 void Note(SMLoc L, const Twine &Msg, ArrayRef<SMRange> Ranges = None) {
180 return getParser().Note(L, Msg, Ranges);
182 bool Warning(SMLoc L, const Twine &Msg,
183 ArrayRef<SMRange> Ranges = None) {
184 return getParser().Warning(L, Msg, Ranges);
186 bool Error(SMLoc L, const Twine &Msg,
187 ArrayRef<SMRange> Ranges = None) {
188 return getParser().Error(L, Msg, Ranges);
191 bool validatetLDMRegList(MCInst Inst, const OperandVector &Operands,
192 unsigned ListNo, bool IsARPop = false);
193 bool validatetSTMRegList(MCInst Inst, const OperandVector &Operands,
196 int tryParseRegister();
197 bool tryParseRegisterWithWriteBack(OperandVector &);
198 int tryParseShiftRegister(OperandVector &);
199 bool parseRegisterList(OperandVector &);
200 bool parseMemory(OperandVector &);
201 bool parseOperand(OperandVector &, StringRef Mnemonic);
202 bool parsePrefix(ARMMCExpr::VariantKind &RefKind);
203 bool parseMemRegOffsetShift(ARM_AM::ShiftOpc &ShiftType,
204 unsigned &ShiftAmount);
205 bool parseLiteralValues(unsigned Size, SMLoc L);
206 bool parseDirectiveThumb(SMLoc L);
207 bool parseDirectiveARM(SMLoc L);
208 bool parseDirectiveThumbFunc(SMLoc L);
209 bool parseDirectiveCode(SMLoc L);
210 bool parseDirectiveSyntax(SMLoc L);
211 bool parseDirectiveReq(StringRef Name, SMLoc L);
212 bool parseDirectiveUnreq(SMLoc L);
213 bool parseDirectiveArch(SMLoc L);
214 bool parseDirectiveEabiAttr(SMLoc L);
215 bool parseDirectiveCPU(SMLoc L);
216 bool parseDirectiveFPU(SMLoc L);
217 bool parseDirectiveFnStart(SMLoc L);
218 bool parseDirectiveFnEnd(SMLoc L);
219 bool parseDirectiveCantUnwind(SMLoc L);
220 bool parseDirectivePersonality(SMLoc L);
221 bool parseDirectiveHandlerData(SMLoc L);
222 bool parseDirectiveSetFP(SMLoc L);
223 bool parseDirectivePad(SMLoc L);
224 bool parseDirectiveRegSave(SMLoc L, bool IsVector);
225 bool parseDirectiveInst(SMLoc L, char Suffix = '\0');
226 bool parseDirectiveLtorg(SMLoc L);
227 bool parseDirectiveEven(SMLoc L);
228 bool parseDirectivePersonalityIndex(SMLoc L);
229 bool parseDirectiveUnwindRaw(SMLoc L);
230 bool parseDirectiveTLSDescSeq(SMLoc L);
231 bool parseDirectiveMovSP(SMLoc L);
232 bool parseDirectiveObjectArch(SMLoc L);
233 bool parseDirectiveArchExtension(SMLoc L);
234 bool parseDirectiveAlign(SMLoc L);
235 bool parseDirectiveThumbSet(SMLoc L);
237 StringRef splitMnemonic(StringRef Mnemonic, unsigned &PredicationCode,
238 bool &CarrySetting, unsigned &ProcessorIMod,
240 void getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
241 bool &CanAcceptCarrySet,
242 bool &CanAcceptPredicationCode);
244 bool isThumb() const {
245 // FIXME: Can tablegen auto-generate this?
246 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
248 bool isThumbOne() const {
249 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
251 bool isThumbTwo() const {
252 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2);
254 bool hasThumb() const {
255 return STI.getFeatureBits() & ARM::HasV4TOps;
257 bool hasV6Ops() const {
258 return STI.getFeatureBits() & ARM::HasV6Ops;
260 bool hasV6MOps() const {
261 return STI.getFeatureBits() & ARM::HasV6MOps;
263 bool hasV7Ops() const {
264 return STI.getFeatureBits() & ARM::HasV7Ops;
266 bool hasV8Ops() const {
267 return STI.getFeatureBits() & ARM::HasV8Ops;
269 bool hasARM() const {
270 return !(STI.getFeatureBits() & ARM::FeatureNoARM);
272 bool hasThumb2DSP() const {
273 return STI.getFeatureBits() & ARM::FeatureDSPThumb2;
275 bool hasD16() const {
276 return STI.getFeatureBits() & ARM::FeatureD16;
278 bool hasV8_1aOps() const {
279 return STI.getFeatureBits() & ARM::HasV8_1aOps;
283 uint64_t FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
284 setAvailableFeatures(FB);
286 bool isMClass() const {
287 return STI.getFeatureBits() & ARM::FeatureMClass;
290 /// @name Auto-generated Match Functions
293 #define GET_ASSEMBLER_HEADER
294 #include "ARMGenAsmMatcher.inc"
298 OperandMatchResultTy parseITCondCode(OperandVector &);
299 OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
300 OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
301 OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
302 OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
303 OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
304 OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
305 OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
306 OperandMatchResultTy parseBankedRegOperand(OperandVector &);
307 OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
309 OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
310 return parsePKHImm(O, "lsl", 0, 31);
312 OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
313 return parsePKHImm(O, "asr", 1, 32);
315 OperandMatchResultTy parseSetEndImm(OperandVector &);
316 OperandMatchResultTy parseShifterImm(OperandVector &);
317 OperandMatchResultTy parseRotImm(OperandVector &);
318 OperandMatchResultTy parseModImm(OperandVector &);
319 OperandMatchResultTy parseBitfield(OperandVector &);
320 OperandMatchResultTy parsePostIdxReg(OperandVector &);
321 OperandMatchResultTy parseAM3Offset(OperandVector &);
322 OperandMatchResultTy parseFPImm(OperandVector &);
323 OperandMatchResultTy parseVectorList(OperandVector &);
324 OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
327 // Asm Match Converter Methods
328 void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
329 void cvtThumbBranches(MCInst &Inst, const OperandVector &);
331 bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
332 bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
333 bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
334 bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
337 enum ARMMatchResultTy {
338 Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
339 Match_RequiresNotITBlock,
341 Match_RequiresThumb2,
342 #define GET_OPERAND_DIAGNOSTIC_TYPES
343 #include "ARMGenAsmMatcher.inc"
347 ARMAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
348 const MCInstrInfo &MII, const MCTargetOptions &Options)
349 : STI(STI), MII(MII), UC(Parser) {
350 MCAsmParserExtension::Initialize(Parser);
352 // Cache the MCRegisterInfo.
353 MRI = getContext().getRegisterInfo();
355 // Initialize the set of available features.
356 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
358 // Not in an ITBlock to start with.
359 ITState.CurPosition = ~0U;
361 NextSymbolIsThumb = false;
364 // Implementation of the MCTargetAsmParser interface:
365 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
366 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
367 SMLoc NameLoc, OperandVector &Operands) override;
368 bool ParseDirective(AsmToken DirectiveID) override;
370 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
371 unsigned Kind) override;
372 unsigned checkTargetMatchPredicate(MCInst &Inst) override;
374 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
375 OperandVector &Operands, MCStreamer &Out,
377 bool MatchingInlineAsm) override;
378 void onLabelParsed(MCSymbol *Symbol) override;
380 } // end anonymous namespace
384 /// ARMOperand - Instances of this class represent a parsed ARM machine
386 class ARMOperand : public MCParsedAsmOperand {
396 k_InstSyncBarrierOpt,
408 k_VectorListAllLanes,
415 k_BitfieldDescriptor,
419 SMLoc StartLoc, EndLoc, AlignmentLoc;
420 SmallVector<unsigned, 8> Registers;
423 ARMCC::CondCodes Val;
430 struct CoprocOptionOp {
443 ARM_ISB::InstSyncBOpt Val;
447 ARM_PROC::IFlags Val;
467 // A vector register list is a sequential list of 1 to 4 registers.
468 struct VectorListOp {
475 struct VectorIndexOp {
483 /// Combined record for all forms of ARM address expressions.
486 // Offset is in OffsetReg or OffsetImm. If both are zero, no offset
488 const MCConstantExpr *OffsetImm; // Offset immediate value
489 unsigned OffsetRegNum; // Offset register num, when OffsetImm == NULL
490 ARM_AM::ShiftOpc ShiftType; // Shift type for OffsetReg
491 unsigned ShiftImm; // shift for OffsetReg.
492 unsigned Alignment; // 0 = no alignment specified
493 // n = alignment in bytes (2, 4, 8, 16, or 32)
494 unsigned isNegative : 1; // Negated OffsetReg? (~'U' bit)
497 struct PostIdxRegOp {
500 ARM_AM::ShiftOpc ShiftTy;
504 struct ShifterImmOp {
509 struct RegShiftedRegOp {
510 ARM_AM::ShiftOpc ShiftTy;
516 struct RegShiftedImmOp {
517 ARM_AM::ShiftOpc ShiftTy;
539 struct CoprocOptionOp CoprocOption;
540 struct MBOptOp MBOpt;
541 struct ISBOptOp ISBOpt;
542 struct ITMaskOp ITMask;
543 struct IFlagsOp IFlags;
544 struct MMaskOp MMask;
545 struct BankedRegOp BankedReg;
548 struct VectorListOp VectorList;
549 struct VectorIndexOp VectorIndex;
551 struct MemoryOp Memory;
552 struct PostIdxRegOp PostIdxReg;
553 struct ShifterImmOp ShifterImm;
554 struct RegShiftedRegOp RegShiftedReg;
555 struct RegShiftedImmOp RegShiftedImm;
556 struct RotImmOp RotImm;
557 struct ModImmOp ModImm;
558 struct BitfieldOp Bitfield;
562 ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
563 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
565 StartLoc = o.StartLoc;
582 case k_DPRRegisterList:
583 case k_SPRRegisterList:
584 Registers = o.Registers;
587 case k_VectorListAllLanes:
588 case k_VectorListIndexed:
589 VectorList = o.VectorList;
596 CoprocOption = o.CoprocOption;
601 case k_MemBarrierOpt:
604 case k_InstSyncBarrierOpt:
609 case k_PostIndexRegister:
610 PostIdxReg = o.PostIdxReg;
616 BankedReg = o.BankedReg;
621 case k_ShifterImmediate:
622 ShifterImm = o.ShifterImm;
624 case k_ShiftedRegister:
625 RegShiftedReg = o.RegShiftedReg;
627 case k_ShiftedImmediate:
628 RegShiftedImm = o.RegShiftedImm;
630 case k_RotateImmediate:
633 case k_ModifiedImmediate:
636 case k_BitfieldDescriptor:
637 Bitfield = o.Bitfield;
640 VectorIndex = o.VectorIndex;
645 /// getStartLoc - Get the location of the first token of this operand.
646 SMLoc getStartLoc() const override { return StartLoc; }
647 /// getEndLoc - Get the location of the last token of this operand.
648 SMLoc getEndLoc() const override { return EndLoc; }
649 /// getLocRange - Get the range between the first and last token of this
651 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
653 /// getAlignmentLoc - Get the location of the Alignment token of this operand.
654 SMLoc getAlignmentLoc() const {
655 assert(Kind == k_Memory && "Invalid access!");
659 ARMCC::CondCodes getCondCode() const {
660 assert(Kind == k_CondCode && "Invalid access!");
664 unsigned getCoproc() const {
665 assert((Kind == k_CoprocNum || Kind == k_CoprocReg) && "Invalid access!");
669 StringRef getToken() const {
670 assert(Kind == k_Token && "Invalid access!");
671 return StringRef(Tok.Data, Tok.Length);
674 unsigned getReg() const override {
675 assert((Kind == k_Register || Kind == k_CCOut) && "Invalid access!");
679 const SmallVectorImpl<unsigned> &getRegList() const {
680 assert((Kind == k_RegisterList || Kind == k_DPRRegisterList ||
681 Kind == k_SPRRegisterList) && "Invalid access!");
685 const MCExpr *getImm() const {
686 assert(isImm() && "Invalid access!");
690 unsigned getVectorIndex() const {
691 assert(Kind == k_VectorIndex && "Invalid access!");
692 return VectorIndex.Val;
695 ARM_MB::MemBOpt getMemBarrierOpt() const {
696 assert(Kind == k_MemBarrierOpt && "Invalid access!");
700 ARM_ISB::InstSyncBOpt getInstSyncBarrierOpt() const {
701 assert(Kind == k_InstSyncBarrierOpt && "Invalid access!");
705 ARM_PROC::IFlags getProcIFlags() const {
706 assert(Kind == k_ProcIFlags && "Invalid access!");
710 unsigned getMSRMask() const {
711 assert(Kind == k_MSRMask && "Invalid access!");
715 unsigned getBankedReg() const {
716 assert(Kind == k_BankedReg && "Invalid access!");
717 return BankedReg.Val;
720 bool isCoprocNum() const { return Kind == k_CoprocNum; }
721 bool isCoprocReg() const { return Kind == k_CoprocReg; }
722 bool isCoprocOption() const { return Kind == k_CoprocOption; }
723 bool isCondCode() const { return Kind == k_CondCode; }
724 bool isCCOut() const { return Kind == k_CCOut; }
725 bool isITMask() const { return Kind == k_ITCondMask; }
726 bool isITCondCode() const { return Kind == k_CondCode; }
727 bool isImm() const override { return Kind == k_Immediate; }
728 // checks whether this operand is an unsigned offset which fits is a field
729 // of specified width and scaled by a specific number of bits
730 template<unsigned width, unsigned scale>
731 bool isUnsignedOffset() const {
732 if (!isImm()) return false;
733 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
734 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
735 int64_t Val = CE->getValue();
736 int64_t Align = 1LL << scale;
737 int64_t Max = Align * ((1LL << width) - 1);
738 return ((Val % Align) == 0) && (Val >= 0) && (Val <= Max);
742 // checks whether this operand is an signed offset which fits is a field
743 // of specified width and scaled by a specific number of bits
744 template<unsigned width, unsigned scale>
745 bool isSignedOffset() const {
746 if (!isImm()) return false;
747 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
748 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val)) {
749 int64_t Val = CE->getValue();
750 int64_t Align = 1LL << scale;
751 int64_t Max = Align * ((1LL << (width-1)) - 1);
752 int64_t Min = -Align * (1LL << (width-1));
753 return ((Val % Align) == 0) && (Val >= Min) && (Val <= Max);
758 // checks whether this operand is a memory operand computed as an offset
759 // applied to PC. the offset may have 8 bits of magnitude and is represented
760 // with two bits of shift. textually it may be either [pc, #imm], #imm or
761 // relocable expression...
762 bool isThumbMemPC() const {
765 if (isa<MCSymbolRefExpr>(Imm.Val)) return true;
766 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm.Val);
767 if (!CE) return false;
768 Val = CE->getValue();
771 if(!Memory.OffsetImm || Memory.OffsetRegNum) return false;
772 if(Memory.BaseRegNum != ARM::PC) return false;
773 Val = Memory.OffsetImm->getValue();
776 return ((Val % 4) == 0) && (Val >= 0) && (Val <= 1020);
778 bool isFPImm() const {
779 if (!isImm()) return false;
780 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
781 if (!CE) return false;
782 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
785 bool isFBits16() const {
786 if (!isImm()) return false;
787 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
788 if (!CE) return false;
789 int64_t Value = CE->getValue();
790 return Value >= 0 && Value <= 16;
792 bool isFBits32() const {
793 if (!isImm()) return false;
794 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
795 if (!CE) return false;
796 int64_t Value = CE->getValue();
797 return Value >= 1 && Value <= 32;
799 bool isImm8s4() const {
800 if (!isImm()) return false;
801 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
802 if (!CE) return false;
803 int64_t Value = CE->getValue();
804 return ((Value & 3) == 0) && Value >= -1020 && Value <= 1020;
806 bool isImm0_1020s4() const {
807 if (!isImm()) return false;
808 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
809 if (!CE) return false;
810 int64_t Value = CE->getValue();
811 return ((Value & 3) == 0) && Value >= 0 && Value <= 1020;
813 bool isImm0_508s4() const {
814 if (!isImm()) return false;
815 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
816 if (!CE) return false;
817 int64_t Value = CE->getValue();
818 return ((Value & 3) == 0) && Value >= 0 && Value <= 508;
820 bool isImm0_508s4Neg() const {
821 if (!isImm()) return false;
822 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
823 if (!CE) return false;
824 int64_t Value = -CE->getValue();
825 // explicitly exclude zero. we want that to use the normal 0_508 version.
826 return ((Value & 3) == 0) && Value > 0 && Value <= 508;
828 bool isImm0_239() const {
829 if (!isImm()) return false;
830 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
831 if (!CE) return false;
832 int64_t Value = CE->getValue();
833 return Value >= 0 && Value < 240;
835 bool isImm0_255() const {
836 if (!isImm()) return false;
837 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
838 if (!CE) return false;
839 int64_t Value = CE->getValue();
840 return Value >= 0 && Value < 256;
842 bool isImm0_4095() const {
843 if (!isImm()) return false;
844 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
845 if (!CE) return false;
846 int64_t Value = CE->getValue();
847 return Value >= 0 && Value < 4096;
849 bool isImm0_4095Neg() const {
850 if (!isImm()) return false;
851 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
852 if (!CE) return false;
853 int64_t Value = -CE->getValue();
854 return Value > 0 && Value < 4096;
856 bool isImm0_1() const {
857 if (!isImm()) return false;
858 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
859 if (!CE) return false;
860 int64_t Value = CE->getValue();
861 return Value >= 0 && Value < 2;
863 bool isImm0_3() const {
864 if (!isImm()) return false;
865 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
866 if (!CE) return false;
867 int64_t Value = CE->getValue();
868 return Value >= 0 && Value < 4;
870 bool isImm0_7() const {
871 if (!isImm()) return false;
872 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
873 if (!CE) return false;
874 int64_t Value = CE->getValue();
875 return Value >= 0 && Value < 8;
877 bool isImm0_15() const {
878 if (!isImm()) return false;
879 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
880 if (!CE) return false;
881 int64_t Value = CE->getValue();
882 return Value >= 0 && Value < 16;
884 bool isImm0_31() const {
885 if (!isImm()) return false;
886 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
887 if (!CE) return false;
888 int64_t Value = CE->getValue();
889 return Value >= 0 && Value < 32;
891 bool isImm0_63() const {
892 if (!isImm()) return false;
893 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
894 if (!CE) return false;
895 int64_t Value = CE->getValue();
896 return Value >= 0 && Value < 64;
898 bool isImm8() const {
899 if (!isImm()) return false;
900 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
901 if (!CE) return false;
902 int64_t Value = CE->getValue();
905 bool isImm16() const {
906 if (!isImm()) return false;
907 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
908 if (!CE) return false;
909 int64_t Value = CE->getValue();
912 bool isImm32() const {
913 if (!isImm()) return false;
914 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
915 if (!CE) return false;
916 int64_t Value = CE->getValue();
919 bool isShrImm8() const {
920 if (!isImm()) return false;
921 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
922 if (!CE) return false;
923 int64_t Value = CE->getValue();
924 return Value > 0 && Value <= 8;
926 bool isShrImm16() const {
927 if (!isImm()) return false;
928 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
929 if (!CE) return false;
930 int64_t Value = CE->getValue();
931 return Value > 0 && Value <= 16;
933 bool isShrImm32() const {
934 if (!isImm()) return false;
935 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
936 if (!CE) return false;
937 int64_t Value = CE->getValue();
938 return Value > 0 && Value <= 32;
940 bool isShrImm64() const {
941 if (!isImm()) return false;
942 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
943 if (!CE) return false;
944 int64_t Value = CE->getValue();
945 return Value > 0 && Value <= 64;
947 bool isImm1_7() const {
948 if (!isImm()) return false;
949 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
950 if (!CE) return false;
951 int64_t Value = CE->getValue();
952 return Value > 0 && Value < 8;
954 bool isImm1_15() const {
955 if (!isImm()) return false;
956 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
957 if (!CE) return false;
958 int64_t Value = CE->getValue();
959 return Value > 0 && Value < 16;
961 bool isImm1_31() const {
962 if (!isImm()) return false;
963 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
964 if (!CE) return false;
965 int64_t Value = CE->getValue();
966 return Value > 0 && Value < 32;
968 bool isImm1_16() const {
969 if (!isImm()) return false;
970 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
971 if (!CE) return false;
972 int64_t Value = CE->getValue();
973 return Value > 0 && Value < 17;
975 bool isImm1_32() const {
976 if (!isImm()) return false;
977 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
978 if (!CE) return false;
979 int64_t Value = CE->getValue();
980 return Value > 0 && Value < 33;
982 bool isImm0_32() const {
983 if (!isImm()) return false;
984 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
985 if (!CE) return false;
986 int64_t Value = CE->getValue();
987 return Value >= 0 && Value < 33;
989 bool isImm0_65535() const {
990 if (!isImm()) return false;
991 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
992 if (!CE) return false;
993 int64_t Value = CE->getValue();
994 return Value >= 0 && Value < 65536;
996 bool isImm256_65535Expr() const {
997 if (!isImm()) return false;
998 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
999 // If it's not a constant expression, it'll generate a fixup and be
1001 if (!CE) return true;
1002 int64_t Value = CE->getValue();
1003 return Value >= 256 && Value < 65536;
1005 bool isImm0_65535Expr() const {
1006 if (!isImm()) return false;
1007 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1008 // If it's not a constant expression, it'll generate a fixup and be
1010 if (!CE) return true;
1011 int64_t Value = CE->getValue();
1012 return Value >= 0 && Value < 65536;
1014 bool isImm24bit() const {
1015 if (!isImm()) return false;
1016 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1017 if (!CE) return false;
1018 int64_t Value = CE->getValue();
1019 return Value >= 0 && Value <= 0xffffff;
1021 bool isImmThumbSR() const {
1022 if (!isImm()) return false;
1023 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1024 if (!CE) return false;
1025 int64_t Value = CE->getValue();
1026 return Value > 0 && Value < 33;
1028 bool isPKHLSLImm() const {
1029 if (!isImm()) return false;
1030 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1031 if (!CE) return false;
1032 int64_t Value = CE->getValue();
1033 return Value >= 0 && Value < 32;
1035 bool isPKHASRImm() const {
1036 if (!isImm()) return false;
1037 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1038 if (!CE) return false;
1039 int64_t Value = CE->getValue();
1040 return Value > 0 && Value <= 32;
1042 bool isAdrLabel() const {
1043 // If we have an immediate that's not a constant, treat it as a label
1044 // reference needing a fixup.
1045 if (isImm() && !isa<MCConstantExpr>(getImm()))
1048 // If it is a constant, it must fit into a modified immediate encoding.
1049 if (!isImm()) return false;
1050 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1051 if (!CE) return false;
1052 int64_t Value = CE->getValue();
1053 return (ARM_AM::getSOImmVal(Value) != -1 ||
1054 ARM_AM::getSOImmVal(-Value) != -1);;
1056 bool isT2SOImm() const {
1057 if (!isImm()) return false;
1058 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1059 if (!CE) return false;
1060 int64_t Value = CE->getValue();
1061 return ARM_AM::getT2SOImmVal(Value) != -1;
1063 bool isT2SOImmNot() const {
1064 if (!isImm()) return false;
1065 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1066 if (!CE) return false;
1067 int64_t Value = CE->getValue();
1068 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1069 ARM_AM::getT2SOImmVal(~Value) != -1;
1071 bool isT2SOImmNeg() const {
1072 if (!isImm()) return false;
1073 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1074 if (!CE) return false;
1075 int64_t Value = CE->getValue();
1076 // Only use this when not representable as a plain so_imm.
1077 return ARM_AM::getT2SOImmVal(Value) == -1 &&
1078 ARM_AM::getT2SOImmVal(-Value) != -1;
1080 bool isSetEndImm() const {
1081 if (!isImm()) return false;
1082 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1083 if (!CE) return false;
1084 int64_t Value = CE->getValue();
1085 return Value == 1 || Value == 0;
1087 bool isReg() const override { return Kind == k_Register; }
1088 bool isRegList() const { return Kind == k_RegisterList; }
1089 bool isDPRRegList() const { return Kind == k_DPRRegisterList; }
1090 bool isSPRRegList() const { return Kind == k_SPRRegisterList; }
1091 bool isToken() const override { return Kind == k_Token; }
1092 bool isMemBarrierOpt() const { return Kind == k_MemBarrierOpt; }
1093 bool isInstSyncBarrierOpt() const { return Kind == k_InstSyncBarrierOpt; }
1094 bool isMem() const override { return Kind == k_Memory; }
1095 bool isShifterImm() const { return Kind == k_ShifterImmediate; }
1096 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
1097 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
1098 bool isRotImm() const { return Kind == k_RotateImmediate; }
1099 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1100 bool isModImmNot() const {
1101 if (!isImm()) return false;
1102 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1103 if (!CE) return false;
1104 int64_t Value = CE->getValue();
1105 return ARM_AM::getSOImmVal(~Value) != -1;
1107 bool isModImmNeg() const {
1108 if (!isImm()) return false;
1109 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1110 if (!CE) return false;
1111 int64_t Value = CE->getValue();
1112 return ARM_AM::getSOImmVal(Value) == -1 &&
1113 ARM_AM::getSOImmVal(-Value) != -1;
1115 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
1116 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
1117 bool isPostIdxReg() const {
1118 return Kind == k_PostIndexRegister && PostIdxReg.ShiftTy ==ARM_AM::no_shift;
1120 bool isMemNoOffset(bool alignOK = false, unsigned Alignment = 0) const {
1123 // No offset of any kind.
1124 return Memory.OffsetRegNum == 0 && Memory.OffsetImm == nullptr &&
1125 (alignOK || Memory.Alignment == Alignment);
1127 bool isMemPCRelImm12() const {
1128 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1130 // Base register must be PC.
1131 if (Memory.BaseRegNum != ARM::PC)
1133 // Immediate offset in range [-4095, 4095].
1134 if (!Memory.OffsetImm) return true;
1135 int64_t Val = Memory.OffsetImm->getValue();
1136 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1138 bool isAlignedMemory() const {
1139 return isMemNoOffset(true);
1141 bool isAlignedMemoryNone() const {
1142 return isMemNoOffset(false, 0);
1144 bool isDupAlignedMemoryNone() const {
1145 return isMemNoOffset(false, 0);
1147 bool isAlignedMemory16() const {
1148 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1150 return isMemNoOffset(false, 0);
1152 bool isDupAlignedMemory16() const {
1153 if (isMemNoOffset(false, 2)) // alignment in bytes for 16-bits is 2.
1155 return isMemNoOffset(false, 0);
1157 bool isAlignedMemory32() const {
1158 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1160 return isMemNoOffset(false, 0);
1162 bool isDupAlignedMemory32() const {
1163 if (isMemNoOffset(false, 4)) // alignment in bytes for 32-bits is 4.
1165 return isMemNoOffset(false, 0);
1167 bool isAlignedMemory64() const {
1168 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1170 return isMemNoOffset(false, 0);
1172 bool isDupAlignedMemory64() const {
1173 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1175 return isMemNoOffset(false, 0);
1177 bool isAlignedMemory64or128() const {
1178 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1180 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1182 return isMemNoOffset(false, 0);
1184 bool isDupAlignedMemory64or128() const {
1185 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1187 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1189 return isMemNoOffset(false, 0);
1191 bool isAlignedMemory64or128or256() const {
1192 if (isMemNoOffset(false, 8)) // alignment in bytes for 64-bits is 8.
1194 if (isMemNoOffset(false, 16)) // alignment in bytes for 128-bits is 16.
1196 if (isMemNoOffset(false, 32)) // alignment in bytes for 256-bits is 32.
1198 return isMemNoOffset(false, 0);
1200 bool isAddrMode2() const {
1201 if (!isMem() || Memory.Alignment != 0) return false;
1202 // Check for register offset.
1203 if (Memory.OffsetRegNum) return true;
1204 // Immediate offset in range [-4095, 4095].
1205 if (!Memory.OffsetImm) return true;
1206 int64_t Val = Memory.OffsetImm->getValue();
1207 return Val > -4096 && Val < 4096;
1209 bool isAM2OffsetImm() const {
1210 if (!isImm()) return false;
1211 // Immediate offset in range [-4095, 4095].
1212 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1213 if (!CE) return false;
1214 int64_t Val = CE->getValue();
1215 return (Val == INT32_MIN) || (Val > -4096 && Val < 4096);
1217 bool isAddrMode3() const {
1218 // If we have an immediate that's not a constant, treat it as a label
1219 // reference needing a fixup. If it is a constant, it's something else
1220 // and we reject it.
1221 if (isImm() && !isa<MCConstantExpr>(getImm()))
1223 if (!isMem() || Memory.Alignment != 0) return false;
1224 // No shifts are legal for AM3.
1225 if (Memory.ShiftType != ARM_AM::no_shift) return false;
1226 // Check for register offset.
1227 if (Memory.OffsetRegNum) return true;
1228 // Immediate offset in range [-255, 255].
1229 if (!Memory.OffsetImm) return true;
1230 int64_t Val = Memory.OffsetImm->getValue();
1231 // The #-0 offset is encoded as INT32_MIN, and we have to check
1233 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1235 bool isAM3Offset() const {
1236 if (Kind != k_Immediate && Kind != k_PostIndexRegister)
1238 if (Kind == k_PostIndexRegister)
1239 return PostIdxReg.ShiftTy == ARM_AM::no_shift;
1240 // Immediate offset in range [-255, 255].
1241 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1242 if (!CE) return false;
1243 int64_t Val = CE->getValue();
1244 // Special case, #-0 is INT32_MIN.
1245 return (Val > -256 && Val < 256) || Val == INT32_MIN;
1247 bool isAddrMode5() const {
1248 // If we have an immediate that's not a constant, treat it as a label
1249 // reference needing a fixup. If it is a constant, it's something else
1250 // and we reject it.
1251 if (isImm() && !isa<MCConstantExpr>(getImm()))
1253 if (!isMem() || Memory.Alignment != 0) return false;
1254 // Check for register offset.
1255 if (Memory.OffsetRegNum) return false;
1256 // Immediate offset in range [-1020, 1020] and a multiple of 4.
1257 if (!Memory.OffsetImm) return true;
1258 int64_t Val = Memory.OffsetImm->getValue();
1259 return (Val >= -1020 && Val <= 1020 && ((Val & 3) == 0)) ||
1262 bool isMemTBB() const {
1263 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1264 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1268 bool isMemTBH() const {
1269 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1270 Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm != 1 ||
1271 Memory.Alignment != 0 )
1275 bool isMemRegOffset() const {
1276 if (!isMem() || !Memory.OffsetRegNum || Memory.Alignment != 0)
1280 bool isT2MemRegOffset() const {
1281 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1282 Memory.Alignment != 0)
1284 // Only lsl #{0, 1, 2, 3} allowed.
1285 if (Memory.ShiftType == ARM_AM::no_shift)
1287 if (Memory.ShiftType != ARM_AM::lsl || Memory.ShiftImm > 3)
1291 bool isMemThumbRR() const {
1292 // Thumb reg+reg addressing is simple. Just two registers, a base and
1293 // an offset. No shifts, negations or any other complicating factors.
1294 if (!isMem() || !Memory.OffsetRegNum || Memory.isNegative ||
1295 Memory.ShiftType != ARM_AM::no_shift || Memory.Alignment != 0)
1297 return isARMLowRegister(Memory.BaseRegNum) &&
1298 (!Memory.OffsetRegNum || isARMLowRegister(Memory.OffsetRegNum));
1300 bool isMemThumbRIs4() const {
1301 if (!isMem() || Memory.OffsetRegNum != 0 ||
1302 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1304 // Immediate offset, multiple of 4 in range [0, 124].
1305 if (!Memory.OffsetImm) return true;
1306 int64_t Val = Memory.OffsetImm->getValue();
1307 return Val >= 0 && Val <= 124 && (Val % 4) == 0;
1309 bool isMemThumbRIs2() const {
1310 if (!isMem() || Memory.OffsetRegNum != 0 ||
1311 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1313 // Immediate offset, multiple of 4 in range [0, 62].
1314 if (!Memory.OffsetImm) return true;
1315 int64_t Val = Memory.OffsetImm->getValue();
1316 return Val >= 0 && Val <= 62 && (Val % 2) == 0;
1318 bool isMemThumbRIs1() const {
1319 if (!isMem() || Memory.OffsetRegNum != 0 ||
1320 !isARMLowRegister(Memory.BaseRegNum) || Memory.Alignment != 0)
1322 // Immediate offset in range [0, 31].
1323 if (!Memory.OffsetImm) return true;
1324 int64_t Val = Memory.OffsetImm->getValue();
1325 return Val >= 0 && Val <= 31;
1327 bool isMemThumbSPI() const {
1328 if (!isMem() || Memory.OffsetRegNum != 0 ||
1329 Memory.BaseRegNum != ARM::SP || Memory.Alignment != 0)
1331 // Immediate offset, multiple of 4 in range [0, 1020].
1332 if (!Memory.OffsetImm) return true;
1333 int64_t Val = Memory.OffsetImm->getValue();
1334 return Val >= 0 && Val <= 1020 && (Val % 4) == 0;
1336 bool isMemImm8s4Offset() const {
1337 // If we have an immediate that's not a constant, treat it as a label
1338 // reference needing a fixup. If it is a constant, it's something else
1339 // and we reject it.
1340 if (isImm() && !isa<MCConstantExpr>(getImm()))
1342 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1344 // Immediate offset a multiple of 4 in range [-1020, 1020].
1345 if (!Memory.OffsetImm) return true;
1346 int64_t Val = Memory.OffsetImm->getValue();
1347 // Special case, #-0 is INT32_MIN.
1348 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
1350 bool isMemImm0_1020s4Offset() const {
1351 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1353 // Immediate offset a multiple of 4 in range [0, 1020].
1354 if (!Memory.OffsetImm) return true;
1355 int64_t Val = Memory.OffsetImm->getValue();
1356 return Val >= 0 && Val <= 1020 && (Val & 3) == 0;
1358 bool isMemImm8Offset() const {
1359 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1361 // Base reg of PC isn't allowed for these encodings.
1362 if (Memory.BaseRegNum == ARM::PC) return false;
1363 // Immediate offset in range [-255, 255].
1364 if (!Memory.OffsetImm) return true;
1365 int64_t Val = Memory.OffsetImm->getValue();
1366 return (Val == INT32_MIN) || (Val > -256 && Val < 256);
1368 bool isMemPosImm8Offset() const {
1369 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1371 // Immediate offset in range [0, 255].
1372 if (!Memory.OffsetImm) return true;
1373 int64_t Val = Memory.OffsetImm->getValue();
1374 return Val >= 0 && Val < 256;
1376 bool isMemNegImm8Offset() const {
1377 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1379 // Base reg of PC isn't allowed for these encodings.
1380 if (Memory.BaseRegNum == ARM::PC) return false;
1381 // Immediate offset in range [-255, -1].
1382 if (!Memory.OffsetImm) return false;
1383 int64_t Val = Memory.OffsetImm->getValue();
1384 return (Val == INT32_MIN) || (Val > -256 && Val < 0);
1386 bool isMemUImm12Offset() const {
1387 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1389 // Immediate offset in range [0, 4095].
1390 if (!Memory.OffsetImm) return true;
1391 int64_t Val = Memory.OffsetImm->getValue();
1392 return (Val >= 0 && Val < 4096);
1394 bool isMemImm12Offset() const {
1395 // If we have an immediate that's not a constant, treat it as a label
1396 // reference needing a fixup. If it is a constant, it's something else
1397 // and we reject it.
1398 if (isImm() && !isa<MCConstantExpr>(getImm()))
1401 if (!isMem() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
1403 // Immediate offset in range [-4095, 4095].
1404 if (!Memory.OffsetImm) return true;
1405 int64_t Val = Memory.OffsetImm->getValue();
1406 return (Val > -4096 && Val < 4096) || (Val == INT32_MIN);
1408 bool isPostIdxImm8() const {
1409 if (!isImm()) return false;
1410 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1411 if (!CE) return false;
1412 int64_t Val = CE->getValue();
1413 return (Val > -256 && Val < 256) || (Val == INT32_MIN);
1415 bool isPostIdxImm8s4() const {
1416 if (!isImm()) return false;
1417 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1418 if (!CE) return false;
1419 int64_t Val = CE->getValue();
1420 return ((Val & 3) == 0 && Val >= -1020 && Val <= 1020) ||
1424 bool isMSRMask() const { return Kind == k_MSRMask; }
1425 bool isBankedReg() const { return Kind == k_BankedReg; }
1426 bool isProcIFlags() const { return Kind == k_ProcIFlags; }
1429 bool isSingleSpacedVectorList() const {
1430 return Kind == k_VectorList && !VectorList.isDoubleSpaced;
1432 bool isDoubleSpacedVectorList() const {
1433 return Kind == k_VectorList && VectorList.isDoubleSpaced;
1435 bool isVecListOneD() const {
1436 if (!isSingleSpacedVectorList()) return false;
1437 return VectorList.Count == 1;
1440 bool isVecListDPair() const {
1441 if (!isSingleSpacedVectorList()) return false;
1442 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1443 .contains(VectorList.RegNum));
1446 bool isVecListThreeD() const {
1447 if (!isSingleSpacedVectorList()) return false;
1448 return VectorList.Count == 3;
1451 bool isVecListFourD() const {
1452 if (!isSingleSpacedVectorList()) return false;
1453 return VectorList.Count == 4;
1456 bool isVecListDPairSpaced() const {
1457 if (Kind != k_VectorList) return false;
1458 if (isSingleSpacedVectorList()) return false;
1459 return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
1460 .contains(VectorList.RegNum));
1463 bool isVecListThreeQ() const {
1464 if (!isDoubleSpacedVectorList()) return false;
1465 return VectorList.Count == 3;
1468 bool isVecListFourQ() const {
1469 if (!isDoubleSpacedVectorList()) return false;
1470 return VectorList.Count == 4;
1473 bool isSingleSpacedVectorAllLanes() const {
1474 return Kind == k_VectorListAllLanes && !VectorList.isDoubleSpaced;
1476 bool isDoubleSpacedVectorAllLanes() const {
1477 return Kind == k_VectorListAllLanes && VectorList.isDoubleSpaced;
1479 bool isVecListOneDAllLanes() const {
1480 if (!isSingleSpacedVectorAllLanes()) return false;
1481 return VectorList.Count == 1;
1484 bool isVecListDPairAllLanes() const {
1485 if (!isSingleSpacedVectorAllLanes()) return false;
1486 return (ARMMCRegisterClasses[ARM::DPairRegClassID]
1487 .contains(VectorList.RegNum));
1490 bool isVecListDPairSpacedAllLanes() const {
1491 if (!isDoubleSpacedVectorAllLanes()) return false;
1492 return VectorList.Count == 2;
1495 bool isVecListThreeDAllLanes() const {
1496 if (!isSingleSpacedVectorAllLanes()) return false;
1497 return VectorList.Count == 3;
1500 bool isVecListThreeQAllLanes() const {
1501 if (!isDoubleSpacedVectorAllLanes()) return false;
1502 return VectorList.Count == 3;
1505 bool isVecListFourDAllLanes() const {
1506 if (!isSingleSpacedVectorAllLanes()) return false;
1507 return VectorList.Count == 4;
1510 bool isVecListFourQAllLanes() const {
1511 if (!isDoubleSpacedVectorAllLanes()) return false;
1512 return VectorList.Count == 4;
1515 bool isSingleSpacedVectorIndexed() const {
1516 return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
1518 bool isDoubleSpacedVectorIndexed() const {
1519 return Kind == k_VectorListIndexed && VectorList.isDoubleSpaced;
1521 bool isVecListOneDByteIndexed() const {
1522 if (!isSingleSpacedVectorIndexed()) return false;
1523 return VectorList.Count == 1 && VectorList.LaneIndex <= 7;
1526 bool isVecListOneDHWordIndexed() const {
1527 if (!isSingleSpacedVectorIndexed()) return false;
1528 return VectorList.Count == 1 && VectorList.LaneIndex <= 3;
1531 bool isVecListOneDWordIndexed() const {
1532 if (!isSingleSpacedVectorIndexed()) return false;
1533 return VectorList.Count == 1 && VectorList.LaneIndex <= 1;
1536 bool isVecListTwoDByteIndexed() const {
1537 if (!isSingleSpacedVectorIndexed()) return false;
1538 return VectorList.Count == 2 && VectorList.LaneIndex <= 7;
1541 bool isVecListTwoDHWordIndexed() const {
1542 if (!isSingleSpacedVectorIndexed()) return false;
1543 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1546 bool isVecListTwoQWordIndexed() const {
1547 if (!isDoubleSpacedVectorIndexed()) return false;
1548 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1551 bool isVecListTwoQHWordIndexed() const {
1552 if (!isDoubleSpacedVectorIndexed()) return false;
1553 return VectorList.Count == 2 && VectorList.LaneIndex <= 3;
1556 bool isVecListTwoDWordIndexed() const {
1557 if (!isSingleSpacedVectorIndexed()) return false;
1558 return VectorList.Count == 2 && VectorList.LaneIndex <= 1;
1561 bool isVecListThreeDByteIndexed() const {
1562 if (!isSingleSpacedVectorIndexed()) return false;
1563 return VectorList.Count == 3 && VectorList.LaneIndex <= 7;
1566 bool isVecListThreeDHWordIndexed() const {
1567 if (!isSingleSpacedVectorIndexed()) return false;
1568 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1571 bool isVecListThreeQWordIndexed() const {
1572 if (!isDoubleSpacedVectorIndexed()) return false;
1573 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1576 bool isVecListThreeQHWordIndexed() const {
1577 if (!isDoubleSpacedVectorIndexed()) return false;
1578 return VectorList.Count == 3 && VectorList.LaneIndex <= 3;
1581 bool isVecListThreeDWordIndexed() const {
1582 if (!isSingleSpacedVectorIndexed()) return false;
1583 return VectorList.Count == 3 && VectorList.LaneIndex <= 1;
1586 bool isVecListFourDByteIndexed() const {
1587 if (!isSingleSpacedVectorIndexed()) return false;
1588 return VectorList.Count == 4 && VectorList.LaneIndex <= 7;
1591 bool isVecListFourDHWordIndexed() const {
1592 if (!isSingleSpacedVectorIndexed()) return false;
1593 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1596 bool isVecListFourQWordIndexed() const {
1597 if (!isDoubleSpacedVectorIndexed()) return false;
1598 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1601 bool isVecListFourQHWordIndexed() const {
1602 if (!isDoubleSpacedVectorIndexed()) return false;
1603 return VectorList.Count == 4 && VectorList.LaneIndex <= 3;
1606 bool isVecListFourDWordIndexed() const {
1607 if (!isSingleSpacedVectorIndexed()) return false;
1608 return VectorList.Count == 4 && VectorList.LaneIndex <= 1;
1611 bool isVectorIndex8() const {
1612 if (Kind != k_VectorIndex) return false;
1613 return VectorIndex.Val < 8;
1615 bool isVectorIndex16() const {
1616 if (Kind != k_VectorIndex) return false;
1617 return VectorIndex.Val < 4;
1619 bool isVectorIndex32() const {
1620 if (Kind != k_VectorIndex) return false;
1621 return VectorIndex.Val < 2;
1624 bool isNEONi8splat() const {
1625 if (!isImm()) return false;
1626 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1627 // Must be a constant.
1628 if (!CE) return false;
1629 int64_t Value = CE->getValue();
1630 // i8 value splatted across 8 bytes. The immediate is just the 8 byte
1632 return Value >= 0 && Value < 256;
1635 bool isNEONi16splat() const {
1636 if (isNEONByteReplicate(2))
1637 return false; // Leave that for bytes replication and forbid by default.
1640 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1641 // Must be a constant.
1642 if (!CE) return false;
1643 unsigned Value = CE->getValue();
1644 return ARM_AM::isNEONi16splat(Value);
1647 bool isNEONi16splatNot() const {
1650 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1651 // Must be a constant.
1652 if (!CE) return false;
1653 unsigned Value = CE->getValue();
1654 return ARM_AM::isNEONi16splat(~Value & 0xffff);
1657 bool isNEONi32splat() const {
1658 if (isNEONByteReplicate(4))
1659 return false; // Leave that for bytes replication and forbid by default.
1662 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1663 // Must be a constant.
1664 if (!CE) return false;
1665 unsigned Value = CE->getValue();
1666 return ARM_AM::isNEONi32splat(Value);
1669 bool isNEONi32splatNot() const {
1672 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1673 // Must be a constant.
1674 if (!CE) return false;
1675 unsigned Value = CE->getValue();
1676 return ARM_AM::isNEONi32splat(~Value);
1679 bool isNEONByteReplicate(unsigned NumBytes) const {
1682 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1683 // Must be a constant.
1686 int64_t Value = CE->getValue();
1688 return false; // Don't bother with zero.
1690 unsigned char B = Value & 0xff;
1691 for (unsigned i = 1; i < NumBytes; ++i) {
1693 if ((Value & 0xff) != B)
1698 bool isNEONi16ByteReplicate() const { return isNEONByteReplicate(2); }
1699 bool isNEONi32ByteReplicate() const { return isNEONByteReplicate(4); }
1700 bool isNEONi32vmov() const {
1701 if (isNEONByteReplicate(4))
1702 return false; // Let it to be classified as byte-replicate case.
1705 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1706 // Must be a constant.
1709 int64_t Value = CE->getValue();
1710 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1711 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1712 // FIXME: This is probably wrong and a copy and paste from previous example
1713 return (Value >= 0 && Value < 256) ||
1714 (Value >= 0x0100 && Value <= 0xff00) ||
1715 (Value >= 0x010000 && Value <= 0xff0000) ||
1716 (Value >= 0x01000000 && Value <= 0xff000000) ||
1717 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1718 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1720 bool isNEONi32vmovNeg() const {
1721 if (!isImm()) return false;
1722 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1723 // Must be a constant.
1724 if (!CE) return false;
1725 int64_t Value = ~CE->getValue();
1726 // i32 value with set bits only in one byte X000, 0X00, 00X0, or 000X,
1727 // for VMOV/VMVN only, 00Xf or 0Xff are also accepted.
1728 // FIXME: This is probably wrong and a copy and paste from previous example
1729 return (Value >= 0 && Value < 256) ||
1730 (Value >= 0x0100 && Value <= 0xff00) ||
1731 (Value >= 0x010000 && Value <= 0xff0000) ||
1732 (Value >= 0x01000000 && Value <= 0xff000000) ||
1733 (Value >= 0x01ff && Value <= 0xffff && (Value & 0xff) == 0xff) ||
1734 (Value >= 0x01ffff && Value <= 0xffffff && (Value & 0xffff) == 0xffff);
1737 bool isNEONi64splat() const {
1738 if (!isImm()) return false;
1739 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1740 // Must be a constant.
1741 if (!CE) return false;
1742 uint64_t Value = CE->getValue();
1743 // i64 value with each byte being either 0 or 0xff.
1744 for (unsigned i = 0; i < 8; ++i)
1745 if ((Value & 0xff) != 0 && (Value & 0xff) != 0xff) return false;
1749 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
1750 // Add as immediates when possible. Null MCExpr = 0.
1752 Inst.addOperand(MCOperand::CreateImm(0));
1753 else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
1754 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1756 Inst.addOperand(MCOperand::CreateExpr(Expr));
1759 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
1760 assert(N == 2 && "Invalid number of operands!");
1761 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1762 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1763 Inst.addOperand(MCOperand::CreateReg(RegNum));
1766 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
1767 assert(N == 1 && "Invalid number of operands!");
1768 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1771 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
1772 assert(N == 1 && "Invalid number of operands!");
1773 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1776 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
1777 assert(N == 1 && "Invalid number of operands!");
1778 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1781 void addITMaskOperands(MCInst &Inst, unsigned N) const {
1782 assert(N == 1 && "Invalid number of operands!");
1783 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1786 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
1787 assert(N == 1 && "Invalid number of operands!");
1788 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1791 void addCCOutOperands(MCInst &Inst, unsigned N) const {
1792 assert(N == 1 && "Invalid number of operands!");
1793 Inst.addOperand(MCOperand::CreateReg(getReg()));
1796 void addRegOperands(MCInst &Inst, unsigned N) const {
1797 assert(N == 1 && "Invalid number of operands!");
1798 Inst.addOperand(MCOperand::CreateReg(getReg()));
1801 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
1802 assert(N == 3 && "Invalid number of operands!");
1803 assert(isRegShiftedReg() &&
1804 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1805 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1806 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1807 Inst.addOperand(MCOperand::CreateImm(
1808 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
1811 void addRegShiftedImmOperands(MCInst &Inst, unsigned N) const {
1812 assert(N == 2 && "Invalid number of operands!");
1813 assert(isRegShiftedImm() &&
1814 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1815 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1816 // Shift of #32 is encoded as 0 where permitted
1817 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1818 Inst.addOperand(MCOperand::CreateImm(
1819 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
1822 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
1823 assert(N == 1 && "Invalid number of operands!");
1824 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1828 void addRegListOperands(MCInst &Inst, unsigned N) const {
1829 assert(N == 1 && "Invalid number of operands!");
1830 const SmallVectorImpl<unsigned> &RegList = getRegList();
1831 for (SmallVectorImpl<unsigned>::const_iterator
1832 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1833 Inst.addOperand(MCOperand::CreateReg(*I));
1836 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
1837 addRegListOperands(Inst, N);
1840 void addSPRRegListOperands(MCInst &Inst, unsigned N) const {
1841 addRegListOperands(Inst, N);
1844 void addRotImmOperands(MCInst &Inst, unsigned N) const {
1845 assert(N == 1 && "Invalid number of operands!");
1846 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1847 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1850 void addModImmOperands(MCInst &Inst, unsigned N) const {
1851 assert(N == 1 && "Invalid number of operands!");
1853 // Support for fixups (MCFixup)
1855 return addImmOperands(Inst, N);
1857 Inst.addOperand(MCOperand::CreateImm(ModImm.Bits | (ModImm.Rot << 7)));
1860 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1861 assert(N == 1 && "Invalid number of operands!");
1862 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1863 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1864 Inst.addOperand(MCOperand::CreateImm(Enc));
1867 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1868 assert(N == 1 && "Invalid number of operands!");
1869 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1870 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1871 Inst.addOperand(MCOperand::CreateImm(Enc));
1874 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
1875 assert(N == 1 && "Invalid number of operands!");
1876 // Munge the lsb/width into a bitfield mask.
1877 unsigned lsb = Bitfield.LSB;
1878 unsigned width = Bitfield.Width;
1879 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
1880 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
1881 (32 - (lsb + width)));
1882 Inst.addOperand(MCOperand::CreateImm(Mask));
1885 void addImmOperands(MCInst &Inst, unsigned N) const {
1886 assert(N == 1 && "Invalid number of operands!");
1887 addExpr(Inst, getImm());
1890 void addFBits16Operands(MCInst &Inst, unsigned N) const {
1891 assert(N == 1 && "Invalid number of operands!");
1892 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1893 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1896 void addFBits32Operands(MCInst &Inst, unsigned N) const {
1897 assert(N == 1 && "Invalid number of operands!");
1898 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1899 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1902 void addFPImmOperands(MCInst &Inst, unsigned N) const {
1903 assert(N == 1 && "Invalid number of operands!");
1904 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1905 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1906 Inst.addOperand(MCOperand::CreateImm(Val));
1909 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
1910 assert(N == 1 && "Invalid number of operands!");
1911 // FIXME: We really want to scale the value here, but the LDRD/STRD
1912 // instruction don't encode operands that way yet.
1913 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1914 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1917 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
1918 assert(N == 1 && "Invalid number of operands!");
1919 // The immediate is scaled by four in the encoding and is stored
1920 // in the MCInst as such. Lop off the low two bits here.
1921 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1922 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1925 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
1926 assert(N == 1 && "Invalid number of operands!");
1927 // The immediate is scaled by four in the encoding and is stored
1928 // in the MCInst as such. Lop off the low two bits here.
1929 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1930 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1933 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
1934 assert(N == 1 && "Invalid number of operands!");
1935 // The immediate is scaled by four in the encoding and is stored
1936 // in the MCInst as such. Lop off the low two bits here.
1937 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1938 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1941 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
1942 assert(N == 1 && "Invalid number of operands!");
1943 // The constant encodes as the immediate-1, and we store in the instruction
1944 // the bits as encoded, so subtract off one here.
1945 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1946 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1949 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
1950 assert(N == 1 && "Invalid number of operands!");
1951 // The constant encodes as the immediate-1, and we store in the instruction
1952 // the bits as encoded, so subtract off one here.
1953 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1954 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1957 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
1958 assert(N == 1 && "Invalid number of operands!");
1959 // The constant encodes as the immediate, except for 32, which encodes as
1961 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1962 unsigned Imm = CE->getValue();
1963 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1966 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
1967 assert(N == 1 && "Invalid number of operands!");
1968 // An ASR value of 32 encodes as 0, so that's how we want to add it to
1969 // the instruction as well.
1970 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1971 int Val = CE->getValue();
1972 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1975 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
1976 assert(N == 1 && "Invalid number of operands!");
1977 // The operand is actually a t2_so_imm, but we have its bitwise
1978 // negation in the assembly source, so twiddle it here.
1979 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1980 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1983 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
1984 assert(N == 1 && "Invalid number of operands!");
1985 // The operand is actually a t2_so_imm, but we have its
1986 // negation in the assembly source, so twiddle it here.
1987 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1988 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1991 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
1992 assert(N == 1 && "Invalid number of operands!");
1993 // The operand is actually an imm0_4095, but we have its
1994 // negation in the assembly source, so twiddle it here.
1995 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
1996 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1999 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
2000 if(const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
2001 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
2005 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2006 assert(SR && "Unknown value type!");
2007 Inst.addOperand(MCOperand::CreateExpr(SR));
2010 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
2011 assert(N == 1 && "Invalid number of operands!");
2013 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2015 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
2019 const MCSymbolRefExpr *SR = dyn_cast<MCSymbolRefExpr>(Imm.Val);
2020 assert(SR && "Unknown value type!");
2021 Inst.addOperand(MCOperand::CreateExpr(SR));
2025 assert(isMem() && "Unknown value type!");
2026 assert(isa<MCConstantExpr>(Memory.OffsetImm) && "Unknown value type!");
2027 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
2030 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
2031 assert(N == 1 && "Invalid number of operands!");
2032 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
2035 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
2036 assert(N == 1 && "Invalid number of operands!");
2037 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
2040 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
2041 assert(N == 1 && "Invalid number of operands!");
2042 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2045 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
2046 assert(N == 1 && "Invalid number of operands!");
2047 int32_t Imm = Memory.OffsetImm->getValue();
2048 Inst.addOperand(MCOperand::CreateImm(Imm));
2051 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
2052 assert(N == 1 && "Invalid number of operands!");
2053 assert(isImm() && "Not an immediate!");
2055 // If we have an immediate that's not a constant, treat it as a label
2056 // reference needing a fixup.
2057 if (!isa<MCConstantExpr>(getImm())) {
2058 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2062 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2063 int Val = CE->getValue();
2064 Inst.addOperand(MCOperand::CreateImm(Val));
2067 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
2068 assert(N == 2 && "Invalid number of operands!");
2069 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2070 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2073 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2074 addAlignedMemoryOperands(Inst, N);
2077 void addAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
2078 addAlignedMemoryOperands(Inst, N);
2081 void addAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2082 addAlignedMemoryOperands(Inst, N);
2085 void addDupAlignedMemory16Operands(MCInst &Inst, unsigned N) const {
2086 addAlignedMemoryOperands(Inst, N);
2089 void addAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2090 addAlignedMemoryOperands(Inst, N);
2093 void addDupAlignedMemory32Operands(MCInst &Inst, unsigned N) const {
2094 addAlignedMemoryOperands(Inst, N);
2097 void addAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2098 addAlignedMemoryOperands(Inst, N);
2101 void addDupAlignedMemory64Operands(MCInst &Inst, unsigned N) const {
2102 addAlignedMemoryOperands(Inst, N);
2105 void addAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2106 addAlignedMemoryOperands(Inst, N);
2109 void addDupAlignedMemory64or128Operands(MCInst &Inst, unsigned N) const {
2110 addAlignedMemoryOperands(Inst, N);
2113 void addAlignedMemory64or128or256Operands(MCInst &Inst, unsigned N) const {
2114 addAlignedMemoryOperands(Inst, N);
2117 void addAddrMode2Operands(MCInst &Inst, unsigned N) const {
2118 assert(N == 3 && "Invalid number of operands!");
2119 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2120 if (!Memory.OffsetRegNum) {
2121 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2122 // Special case for #-0
2123 if (Val == INT32_MIN) Val = 0;
2124 if (Val < 0) Val = -Val;
2125 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2127 // For register offset, we encode the shift type and negation flag
2129 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2130 Memory.ShiftImm, Memory.ShiftType);
2132 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2133 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2134 Inst.addOperand(MCOperand::CreateImm(Val));
2137 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
2138 assert(N == 2 && "Invalid number of operands!");
2139 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2140 assert(CE && "non-constant AM2OffsetImm operand!");
2141 int32_t Val = CE->getValue();
2142 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2143 // Special case for #-0
2144 if (Val == INT32_MIN) Val = 0;
2145 if (Val < 0) Val = -Val;
2146 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2147 Inst.addOperand(MCOperand::CreateReg(0));
2148 Inst.addOperand(MCOperand::CreateImm(Val));
2151 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
2152 assert(N == 3 && "Invalid number of operands!");
2153 // If we have an immediate that's not a constant, treat it as a label
2154 // reference needing a fixup. If it is a constant, it's something else
2155 // and we reject it.
2157 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2158 Inst.addOperand(MCOperand::CreateReg(0));
2159 Inst.addOperand(MCOperand::CreateImm(0));
2163 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2164 if (!Memory.OffsetRegNum) {
2165 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2166 // Special case for #-0
2167 if (Val == INT32_MIN) Val = 0;
2168 if (Val < 0) Val = -Val;
2169 Val = ARM_AM::getAM3Opc(AddSub, Val);
2171 // For register offset, we encode the shift type and negation flag
2173 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
2175 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2176 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2177 Inst.addOperand(MCOperand::CreateImm(Val));
2180 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
2181 assert(N == 2 && "Invalid number of operands!");
2182 if (Kind == k_PostIndexRegister) {
2184 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2185 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2186 Inst.addOperand(MCOperand::CreateImm(Val));
2191 const MCConstantExpr *CE = static_cast<const MCConstantExpr*>(getImm());
2192 int32_t Val = CE->getValue();
2193 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2194 // Special case for #-0
2195 if (Val == INT32_MIN) Val = 0;
2196 if (Val < 0) Val = -Val;
2197 Val = ARM_AM::getAM3Opc(AddSub, Val);
2198 Inst.addOperand(MCOperand::CreateReg(0));
2199 Inst.addOperand(MCOperand::CreateImm(Val));
2202 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
2203 assert(N == 2 && "Invalid number of operands!");
2204 // If we have an immediate that's not a constant, treat it as a label
2205 // reference needing a fixup. If it is a constant, it's something else
2206 // and we reject it.
2208 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2209 Inst.addOperand(MCOperand::CreateImm(0));
2213 // The lower two bits are always zero and as such are not encoded.
2214 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2215 ARM_AM::AddrOpc AddSub = Val < 0 ? ARM_AM::sub : ARM_AM::add;
2216 // Special case for #-0
2217 if (Val == INT32_MIN) Val = 0;
2218 if (Val < 0) Val = -Val;
2219 Val = ARM_AM::getAM5Opc(AddSub, Val);
2220 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2221 Inst.addOperand(MCOperand::CreateImm(Val));
2224 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
2225 assert(N == 2 && "Invalid number of operands!");
2226 // If we have an immediate that's not a constant, treat it as a label
2227 // reference needing a fixup. If it is a constant, it's something else
2228 // and we reject it.
2230 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2231 Inst.addOperand(MCOperand::CreateImm(0));
2235 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2236 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2237 Inst.addOperand(MCOperand::CreateImm(Val));
2240 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
2241 assert(N == 2 && "Invalid number of operands!");
2242 // The lower two bits are always zero and as such are not encoded.
2243 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2244 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2245 Inst.addOperand(MCOperand::CreateImm(Val));
2248 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2249 assert(N == 2 && "Invalid number of operands!");
2250 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2251 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2252 Inst.addOperand(MCOperand::CreateImm(Val));
2255 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2256 addMemImm8OffsetOperands(Inst, N);
2259 void addMemNegImm8OffsetOperands(MCInst &Inst, unsigned N) const {
2260 addMemImm8OffsetOperands(Inst, N);
2263 void addMemUImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2264 assert(N == 2 && "Invalid number of operands!");
2265 // If this is an immediate, it's a label reference.
2267 addExpr(Inst, getImm());
2268 Inst.addOperand(MCOperand::CreateImm(0));
2272 // Otherwise, it's a normal memory reg+offset.
2273 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2274 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2275 Inst.addOperand(MCOperand::CreateImm(Val));
2278 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
2279 assert(N == 2 && "Invalid number of operands!");
2280 // If this is an immediate, it's a label reference.
2282 addExpr(Inst, getImm());
2283 Inst.addOperand(MCOperand::CreateImm(0));
2287 // Otherwise, it's a normal memory reg+offset.
2288 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2289 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2290 Inst.addOperand(MCOperand::CreateImm(Val));
2293 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
2294 assert(N == 2 && "Invalid number of operands!");
2295 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2296 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2299 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
2300 assert(N == 2 && "Invalid number of operands!");
2301 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2302 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2305 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2306 assert(N == 3 && "Invalid number of operands!");
2308 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
2309 Memory.ShiftImm, Memory.ShiftType);
2310 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2311 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2312 Inst.addOperand(MCOperand::CreateImm(Val));
2315 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
2316 assert(N == 3 && "Invalid number of operands!");
2317 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2318 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2319 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2322 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
2323 assert(N == 2 && "Invalid number of operands!");
2324 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2325 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2328 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
2329 assert(N == 2 && "Invalid number of operands!");
2330 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2331 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2332 Inst.addOperand(MCOperand::CreateImm(Val));
2335 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
2336 assert(N == 2 && "Invalid number of operands!");
2337 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2338 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2339 Inst.addOperand(MCOperand::CreateImm(Val));
2342 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
2343 assert(N == 2 && "Invalid number of operands!");
2344 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2345 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2346 Inst.addOperand(MCOperand::CreateImm(Val));
2349 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
2350 assert(N == 2 && "Invalid number of operands!");
2351 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2352 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2353 Inst.addOperand(MCOperand::CreateImm(Val));
2356 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
2357 assert(N == 1 && "Invalid number of operands!");
2358 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2359 assert(CE && "non-constant post-idx-imm8 operand!");
2360 int Imm = CE->getValue();
2361 bool isAdd = Imm >= 0;
2362 if (Imm == INT32_MIN) Imm = 0;
2363 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2364 Inst.addOperand(MCOperand::CreateImm(Imm));
2367 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
2368 assert(N == 1 && "Invalid number of operands!");
2369 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2370 assert(CE && "non-constant post-idx-imm8s4 operand!");
2371 int Imm = CE->getValue();
2372 bool isAdd = Imm >= 0;
2373 if (Imm == INT32_MIN) Imm = 0;
2374 // Immediate is scaled by 4.
2375 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2376 Inst.addOperand(MCOperand::CreateImm(Imm));
2379 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
2380 assert(N == 2 && "Invalid number of operands!");
2381 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2382 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2385 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
2386 assert(N == 2 && "Invalid number of operands!");
2387 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2388 // The sign, shift type, and shift amount are encoded in a single operand
2389 // using the AM2 encoding helpers.
2390 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
2391 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
2392 PostIdxReg.ShiftTy);
2393 Inst.addOperand(MCOperand::CreateImm(Imm));
2396 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
2397 assert(N == 1 && "Invalid number of operands!");
2398 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2401 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
2402 assert(N == 1 && "Invalid number of operands!");
2403 Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
2406 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
2407 assert(N == 1 && "Invalid number of operands!");
2408 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2411 void addVecListOperands(MCInst &Inst, unsigned N) const {
2412 assert(N == 1 && "Invalid number of operands!");
2413 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2416 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
2417 assert(N == 2 && "Invalid number of operands!");
2418 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2419 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2422 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
2423 assert(N == 1 && "Invalid number of operands!");
2424 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2427 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
2428 assert(N == 1 && "Invalid number of operands!");
2429 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2432 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
2433 assert(N == 1 && "Invalid number of operands!");
2434 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2437 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
2438 assert(N == 1 && "Invalid number of operands!");
2439 // The immediate encodes the type of constant as well as the value.
2440 // Mask in that this is an i8 splat.
2441 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2442 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2445 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
2446 assert(N == 1 && "Invalid number of operands!");
2447 // The immediate encodes the type of constant as well as the value.
2448 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2449 unsigned Value = CE->getValue();
2450 Value = ARM_AM::encodeNEONi16splat(Value);
2451 Inst.addOperand(MCOperand::CreateImm(Value));
2454 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
2455 assert(N == 1 && "Invalid number of operands!");
2456 // The immediate encodes the type of constant as well as the value.
2457 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2458 unsigned Value = CE->getValue();
2459 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2460 Inst.addOperand(MCOperand::CreateImm(Value));
2463 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
2464 assert(N == 1 && "Invalid number of operands!");
2465 // The immediate encodes the type of constant as well as the value.
2466 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2467 unsigned Value = CE->getValue();
2468 Value = ARM_AM::encodeNEONi32splat(Value);
2469 Inst.addOperand(MCOperand::CreateImm(Value));
2472 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
2473 assert(N == 1 && "Invalid number of operands!");
2474 // The immediate encodes the type of constant as well as the value.
2475 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2476 unsigned Value = CE->getValue();
2477 Value = ARM_AM::encodeNEONi32splat(~Value);
2478 Inst.addOperand(MCOperand::CreateImm(Value));
2481 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
2482 assert(N == 1 && "Invalid number of operands!");
2483 // The immediate encodes the type of constant as well as the value.
2484 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2485 unsigned Value = CE->getValue();
2486 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2487 Inst.getOpcode() == ARM::VMOVv16i8) &&
2488 "All vmvn instructions that wants to replicate non-zero byte "
2489 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2490 unsigned B = ((~Value) & 0xff);
2491 B |= 0xe00; // cmode = 0b1110
2492 Inst.addOperand(MCOperand::CreateImm(B));
2494 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
2495 assert(N == 1 && "Invalid number of operands!");
2496 // The immediate encodes the type of constant as well as the value.
2497 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2498 unsigned Value = CE->getValue();
2499 if (Value >= 256 && Value <= 0xffff)
2500 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2501 else if (Value > 0xffff && Value <= 0xffffff)
2502 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2503 else if (Value > 0xffffff)
2504 Value = (Value >> 24) | 0x600;
2505 Inst.addOperand(MCOperand::CreateImm(Value));
2508 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
2509 assert(N == 1 && "Invalid number of operands!");
2510 // The immediate encodes the type of constant as well as the value.
2511 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2512 unsigned Value = CE->getValue();
2513 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
2514 Inst.getOpcode() == ARM::VMOVv16i8) &&
2515 "All instructions that wants to replicate non-zero byte "
2516 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
2517 unsigned B = Value & 0xff;
2518 B |= 0xe00; // cmode = 0b1110
2519 Inst.addOperand(MCOperand::CreateImm(B));
2521 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
2522 assert(N == 1 && "Invalid number of operands!");
2523 // The immediate encodes the type of constant as well as the value.
2524 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2525 unsigned Value = ~CE->getValue();
2526 if (Value >= 256 && Value <= 0xffff)
2527 Value = (Value >> 8) | ((Value & 0xff) ? 0xc00 : 0x200);
2528 else if (Value > 0xffff && Value <= 0xffffff)
2529 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
2530 else if (Value > 0xffffff)
2531 Value = (Value >> 24) | 0x600;
2532 Inst.addOperand(MCOperand::CreateImm(Value));
2535 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
2536 assert(N == 1 && "Invalid number of operands!");
2537 // The immediate encodes the type of constant as well as the value.
2538 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
2539 uint64_t Value = CE->getValue();
2541 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
2542 Imm |= (Value & 1) << i;
2544 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2547 void print(raw_ostream &OS) const override;
2549 static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
2550 auto Op = make_unique<ARMOperand>(k_ITCondMask);
2551 Op->ITMask.Mask = Mask;
2557 static std::unique_ptr<ARMOperand> CreateCondCode(ARMCC::CondCodes CC,
2559 auto Op = make_unique<ARMOperand>(k_CondCode);
2566 static std::unique_ptr<ARMOperand> CreateCoprocNum(unsigned CopVal, SMLoc S) {
2567 auto Op = make_unique<ARMOperand>(k_CoprocNum);
2568 Op->Cop.Val = CopVal;
2574 static std::unique_ptr<ARMOperand> CreateCoprocReg(unsigned CopVal, SMLoc S) {
2575 auto Op = make_unique<ARMOperand>(k_CoprocReg);
2576 Op->Cop.Val = CopVal;
2582 static std::unique_ptr<ARMOperand> CreateCoprocOption(unsigned Val, SMLoc S,
2584 auto Op = make_unique<ARMOperand>(k_CoprocOption);
2591 static std::unique_ptr<ARMOperand> CreateCCOut(unsigned RegNum, SMLoc S) {
2592 auto Op = make_unique<ARMOperand>(k_CCOut);
2593 Op->Reg.RegNum = RegNum;
2599 static std::unique_ptr<ARMOperand> CreateToken(StringRef Str, SMLoc S) {
2600 auto Op = make_unique<ARMOperand>(k_Token);
2601 Op->Tok.Data = Str.data();
2602 Op->Tok.Length = Str.size();
2608 static std::unique_ptr<ARMOperand> CreateReg(unsigned RegNum, SMLoc S,
2610 auto Op = make_unique<ARMOperand>(k_Register);
2611 Op->Reg.RegNum = RegNum;
2617 static std::unique_ptr<ARMOperand>
2618 CreateShiftedRegister(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2619 unsigned ShiftReg, unsigned ShiftImm, SMLoc S,
2621 auto Op = make_unique<ARMOperand>(k_ShiftedRegister);
2622 Op->RegShiftedReg.ShiftTy = ShTy;
2623 Op->RegShiftedReg.SrcReg = SrcReg;
2624 Op->RegShiftedReg.ShiftReg = ShiftReg;
2625 Op->RegShiftedReg.ShiftImm = ShiftImm;
2631 static std::unique_ptr<ARMOperand>
2632 CreateShiftedImmediate(ARM_AM::ShiftOpc ShTy, unsigned SrcReg,
2633 unsigned ShiftImm, SMLoc S, SMLoc E) {
2634 auto Op = make_unique<ARMOperand>(k_ShiftedImmediate);
2635 Op->RegShiftedImm.ShiftTy = ShTy;
2636 Op->RegShiftedImm.SrcReg = SrcReg;
2637 Op->RegShiftedImm.ShiftImm = ShiftImm;
2643 static std::unique_ptr<ARMOperand> CreateShifterImm(bool isASR, unsigned Imm,
2645 auto Op = make_unique<ARMOperand>(k_ShifterImmediate);
2646 Op->ShifterImm.isASR = isASR;
2647 Op->ShifterImm.Imm = Imm;
2653 static std::unique_ptr<ARMOperand> CreateRotImm(unsigned Imm, SMLoc S,
2655 auto Op = make_unique<ARMOperand>(k_RotateImmediate);
2656 Op->RotImm.Imm = Imm;
2662 static std::unique_ptr<ARMOperand> CreateModImm(unsigned Bits, unsigned Rot,
2664 auto Op = make_unique<ARMOperand>(k_ModifiedImmediate);
2665 Op->ModImm.Bits = Bits;
2666 Op->ModImm.Rot = Rot;
2672 static std::unique_ptr<ARMOperand>
2673 CreateBitfield(unsigned LSB, unsigned Width, SMLoc S, SMLoc E) {
2674 auto Op = make_unique<ARMOperand>(k_BitfieldDescriptor);
2675 Op->Bitfield.LSB = LSB;
2676 Op->Bitfield.Width = Width;
2682 static std::unique_ptr<ARMOperand>
2683 CreateRegList(SmallVectorImpl<std::pair<unsigned, unsigned>> &Regs,
2684 SMLoc StartLoc, SMLoc EndLoc) {
2685 assert (Regs.size() > 0 && "RegList contains no registers?");
2686 KindTy Kind = k_RegisterList;
2688 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Regs.front().second))
2689 Kind = k_DPRRegisterList;
2690 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].
2691 contains(Regs.front().second))
2692 Kind = k_SPRRegisterList;
2694 // Sort based on the register encoding values.
2695 array_pod_sort(Regs.begin(), Regs.end());
2697 auto Op = make_unique<ARMOperand>(Kind);
2698 for (SmallVectorImpl<std::pair<unsigned, unsigned> >::const_iterator
2699 I = Regs.begin(), E = Regs.end(); I != E; ++I)
2700 Op->Registers.push_back(I->second);
2701 Op->StartLoc = StartLoc;
2702 Op->EndLoc = EndLoc;
2706 static std::unique_ptr<ARMOperand> CreateVectorList(unsigned RegNum,
2708 bool isDoubleSpaced,
2710 auto Op = make_unique<ARMOperand>(k_VectorList);
2711 Op->VectorList.RegNum = RegNum;
2712 Op->VectorList.Count = Count;
2713 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2719 static std::unique_ptr<ARMOperand>
2720 CreateVectorListAllLanes(unsigned RegNum, unsigned Count, bool isDoubleSpaced,
2722 auto Op = make_unique<ARMOperand>(k_VectorListAllLanes);
2723 Op->VectorList.RegNum = RegNum;
2724 Op->VectorList.Count = Count;
2725 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2731 static std::unique_ptr<ARMOperand>
2732 CreateVectorListIndexed(unsigned RegNum, unsigned Count, unsigned Index,
2733 bool isDoubleSpaced, SMLoc S, SMLoc E) {
2734 auto Op = make_unique<ARMOperand>(k_VectorListIndexed);
2735 Op->VectorList.RegNum = RegNum;
2736 Op->VectorList.Count = Count;
2737 Op->VectorList.LaneIndex = Index;
2738 Op->VectorList.isDoubleSpaced = isDoubleSpaced;
2744 static std::unique_ptr<ARMOperand>
2745 CreateVectorIndex(unsigned Idx, SMLoc S, SMLoc E, MCContext &Ctx) {
2746 auto Op = make_unique<ARMOperand>(k_VectorIndex);
2747 Op->VectorIndex.Val = Idx;
2753 static std::unique_ptr<ARMOperand> CreateImm(const MCExpr *Val, SMLoc S,
2755 auto Op = make_unique<ARMOperand>(k_Immediate);
2762 static std::unique_ptr<ARMOperand>
2763 CreateMem(unsigned BaseRegNum, const MCConstantExpr *OffsetImm,
2764 unsigned OffsetRegNum, ARM_AM::ShiftOpc ShiftType,
2765 unsigned ShiftImm, unsigned Alignment, bool isNegative, SMLoc S,
2766 SMLoc E, SMLoc AlignmentLoc = SMLoc()) {
2767 auto Op = make_unique<ARMOperand>(k_Memory);
2768 Op->Memory.BaseRegNum = BaseRegNum;
2769 Op->Memory.OffsetImm = OffsetImm;
2770 Op->Memory.OffsetRegNum = OffsetRegNum;
2771 Op->Memory.ShiftType = ShiftType;
2772 Op->Memory.ShiftImm = ShiftImm;
2773 Op->Memory.Alignment = Alignment;
2774 Op->Memory.isNegative = isNegative;
2777 Op->AlignmentLoc = AlignmentLoc;
2781 static std::unique_ptr<ARMOperand>
2782 CreatePostIdxReg(unsigned RegNum, bool isAdd, ARM_AM::ShiftOpc ShiftTy,
2783 unsigned ShiftImm, SMLoc S, SMLoc E) {
2784 auto Op = make_unique<ARMOperand>(k_PostIndexRegister);
2785 Op->PostIdxReg.RegNum = RegNum;
2786 Op->PostIdxReg.isAdd = isAdd;
2787 Op->PostIdxReg.ShiftTy = ShiftTy;
2788 Op->PostIdxReg.ShiftImm = ShiftImm;
2794 static std::unique_ptr<ARMOperand> CreateMemBarrierOpt(ARM_MB::MemBOpt Opt,
2796 auto Op = make_unique<ARMOperand>(k_MemBarrierOpt);
2797 Op->MBOpt.Val = Opt;
2803 static std::unique_ptr<ARMOperand>
2804 CreateInstSyncBarrierOpt(ARM_ISB::InstSyncBOpt Opt, SMLoc S) {
2805 auto Op = make_unique<ARMOperand>(k_InstSyncBarrierOpt);
2806 Op->ISBOpt.Val = Opt;
2812 static std::unique_ptr<ARMOperand> CreateProcIFlags(ARM_PROC::IFlags IFlags,
2814 auto Op = make_unique<ARMOperand>(k_ProcIFlags);
2815 Op->IFlags.Val = IFlags;
2821 static std::unique_ptr<ARMOperand> CreateMSRMask(unsigned MMask, SMLoc S) {
2822 auto Op = make_unique<ARMOperand>(k_MSRMask);
2823 Op->MMask.Val = MMask;
2829 static std::unique_ptr<ARMOperand> CreateBankedReg(unsigned Reg, SMLoc S) {
2830 auto Op = make_unique<ARMOperand>(k_BankedReg);
2831 Op->BankedReg.Val = Reg;
2838 } // end anonymous namespace.
2840 void ARMOperand::print(raw_ostream &OS) const {
2843 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
2846 OS << "<ccout " << getReg() << ">";
2848 case k_ITCondMask: {
2849 static const char *const MaskStr[] = {
2850 "()", "(t)", "(e)", "(tt)", "(et)", "(te)", "(ee)", "(ttt)", "(ett)",
2851 "(tet)", "(eet)", "(tte)", "(ete)", "(tee)", "(eee)"
2853 assert((ITMask.Mask & 0xf) == ITMask.Mask);
2854 OS << "<it-mask " << MaskStr[ITMask.Mask] << ">";
2858 OS << "<coprocessor number: " << getCoproc() << ">";
2861 OS << "<coprocessor register: " << getCoproc() << ">";
2863 case k_CoprocOption:
2864 OS << "<coprocessor option: " << CoprocOption.Val << ">";
2867 OS << "<mask: " << getMSRMask() << ">";
2870 OS << "<banked reg: " << getBankedReg() << ">";
2873 getImm()->print(OS);
2875 case k_MemBarrierOpt:
2876 OS << "<ARM_MB::" << MemBOptToString(getMemBarrierOpt(), false) << ">";
2878 case k_InstSyncBarrierOpt:
2879 OS << "<ARM_ISB::" << InstSyncBOptToString(getInstSyncBarrierOpt()) << ">";
2883 << " base:" << Memory.BaseRegNum;
2886 case k_PostIndexRegister:
2887 OS << "post-idx register " << (PostIdxReg.isAdd ? "" : "-")
2888 << PostIdxReg.RegNum;
2889 if (PostIdxReg.ShiftTy != ARM_AM::no_shift)
2890 OS << ARM_AM::getShiftOpcStr(PostIdxReg.ShiftTy) << " "
2891 << PostIdxReg.ShiftImm;
2894 case k_ProcIFlags: {
2895 OS << "<ARM_PROC::";
2896 unsigned IFlags = getProcIFlags();
2897 for (int i=2; i >= 0; --i)
2898 if (IFlags & (1 << i))
2899 OS << ARM_PROC::IFlagsToString(1 << i);
2904 OS << "<register " << getReg() << ">";
2906 case k_ShifterImmediate:
2907 OS << "<shift " << (ShifterImm.isASR ? "asr" : "lsl")
2908 << " #" << ShifterImm.Imm << ">";
2910 case k_ShiftedRegister:
2911 OS << "<so_reg_reg "
2912 << RegShiftedReg.SrcReg << " "
2913 << ARM_AM::getShiftOpcStr(RegShiftedReg.ShiftTy)
2914 << " " << RegShiftedReg.ShiftReg << ">";
2916 case k_ShiftedImmediate:
2917 OS << "<so_reg_imm "
2918 << RegShiftedImm.SrcReg << " "
2919 << ARM_AM::getShiftOpcStr(RegShiftedImm.ShiftTy)
2920 << " #" << RegShiftedImm.ShiftImm << ">";
2922 case k_RotateImmediate:
2923 OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
2925 case k_ModifiedImmediate:
2926 OS << "<mod_imm #" << ModImm.Bits << ", #"
2927 << ModImm.Rot << ")>";
2929 case k_BitfieldDescriptor:
2930 OS << "<bitfield " << "lsb: " << Bitfield.LSB
2931 << ", width: " << Bitfield.Width << ">";
2933 case k_RegisterList:
2934 case k_DPRRegisterList:
2935 case k_SPRRegisterList: {
2936 OS << "<register_list ";
2938 const SmallVectorImpl<unsigned> &RegList = getRegList();
2939 for (SmallVectorImpl<unsigned>::const_iterator
2940 I = RegList.begin(), E = RegList.end(); I != E; ) {
2942 if (++I < E) OS << ", ";
2949 OS << "<vector_list " << VectorList.Count << " * "
2950 << VectorList.RegNum << ">";
2952 case k_VectorListAllLanes:
2953 OS << "<vector_list(all lanes) " << VectorList.Count << " * "
2954 << VectorList.RegNum << ">";
2956 case k_VectorListIndexed:
2957 OS << "<vector_list(lane " << VectorList.LaneIndex << ") "
2958 << VectorList.Count << " * " << VectorList.RegNum << ">";
2961 OS << "'" << getToken() << "'";
2964 OS << "<vectorindex " << getVectorIndex() << ">";
2969 /// @name Auto-generated Match Functions
2972 static unsigned MatchRegisterName(StringRef Name);
2976 bool ARMAsmParser::ParseRegister(unsigned &RegNo,
2977 SMLoc &StartLoc, SMLoc &EndLoc) {
2978 const AsmToken &Tok = getParser().getTok();
2979 StartLoc = Tok.getLoc();
2980 EndLoc = Tok.getEndLoc();
2981 RegNo = tryParseRegister();
2983 return (RegNo == (unsigned)-1);
2986 /// Try to parse a register name. The token must be an Identifier when called,
2987 /// and if it is a register name the token is eaten and the register number is
2988 /// returned. Otherwise return -1.
2990 int ARMAsmParser::tryParseRegister() {
2991 MCAsmParser &Parser = getParser();
2992 const AsmToken &Tok = Parser.getTok();
2993 if (Tok.isNot(AsmToken::Identifier)) return -1;
2995 std::string lowerCase = Tok.getString().lower();
2996 unsigned RegNum = MatchRegisterName(lowerCase);
2998 RegNum = StringSwitch<unsigned>(lowerCase)
2999 .Case("r13", ARM::SP)
3000 .Case("r14", ARM::LR)
3001 .Case("r15", ARM::PC)
3002 .Case("ip", ARM::R12)
3003 // Additional register name aliases for 'gas' compatibility.
3004 .Case("a1", ARM::R0)
3005 .Case("a2", ARM::R1)
3006 .Case("a3", ARM::R2)
3007 .Case("a4", ARM::R3)
3008 .Case("v1", ARM::R4)
3009 .Case("v2", ARM::R5)
3010 .Case("v3", ARM::R6)
3011 .Case("v4", ARM::R7)
3012 .Case("v5", ARM::R8)
3013 .Case("v6", ARM::R9)
3014 .Case("v7", ARM::R10)
3015 .Case("v8", ARM::R11)
3016 .Case("sb", ARM::R9)
3017 .Case("sl", ARM::R10)
3018 .Case("fp", ARM::R11)
3022 // Check for aliases registered via .req. Canonicalize to lower case.
3023 // That's more consistent since register names are case insensitive, and
3024 // it's how the original entry was passed in from MC/MCParser/AsmParser.
3025 StringMap<unsigned>::const_iterator Entry = RegisterReqs.find(lowerCase);
3026 // If no match, return failure.
3027 if (Entry == RegisterReqs.end())
3029 Parser.Lex(); // Eat identifier token.
3030 return Entry->getValue();
3033 // Some FPUs only have 16 D registers, so D16-D31 are invalid
3034 if (hasD16() && RegNum >= ARM::D16 && RegNum <= ARM::D31)
3037 Parser.Lex(); // Eat identifier token.
3042 // Try to parse a shifter (e.g., "lsl <amt>"). On success, return 0.
3043 // If a recoverable error occurs, return 1. If an irrecoverable error
3044 // occurs, return -1. An irrecoverable error is one where tokens have been
3045 // consumed in the process of trying to parse the shifter (i.e., when it is
3046 // indeed a shifter operand, but malformed).
3047 int ARMAsmParser::tryParseShiftRegister(OperandVector &Operands) {
3048 MCAsmParser &Parser = getParser();
3049 SMLoc S = Parser.getTok().getLoc();
3050 const AsmToken &Tok = Parser.getTok();
3051 if (Tok.isNot(AsmToken::Identifier))
3054 std::string lowerCase = Tok.getString().lower();
3055 ARM_AM::ShiftOpc ShiftTy = StringSwitch<ARM_AM::ShiftOpc>(lowerCase)
3056 .Case("asl", ARM_AM::lsl)
3057 .Case("lsl", ARM_AM::lsl)
3058 .Case("lsr", ARM_AM::lsr)
3059 .Case("asr", ARM_AM::asr)
3060 .Case("ror", ARM_AM::ror)
3061 .Case("rrx", ARM_AM::rrx)
3062 .Default(ARM_AM::no_shift);
3064 if (ShiftTy == ARM_AM::no_shift)
3067 Parser.Lex(); // Eat the operator.
3069 // The source register for the shift has already been added to the
3070 // operand list, so we need to pop it off and combine it into the shifted
3071 // register operand instead.
3072 std::unique_ptr<ARMOperand> PrevOp(
3073 (ARMOperand *)Operands.pop_back_val().release());
3074 if (!PrevOp->isReg())
3075 return Error(PrevOp->getStartLoc(), "shift must be of a register");
3076 int SrcReg = PrevOp->getReg();
3081 if (ShiftTy == ARM_AM::rrx) {
3082 // RRX Doesn't have an explicit shift amount. The encoder expects
3083 // the shift register to be the same as the source register. Seems odd,
3087 // Figure out if this is shifted by a constant or a register (for non-RRX).
3088 if (Parser.getTok().is(AsmToken::Hash) ||
3089 Parser.getTok().is(AsmToken::Dollar)) {
3090 Parser.Lex(); // Eat hash.
3091 SMLoc ImmLoc = Parser.getTok().getLoc();
3092 const MCExpr *ShiftExpr = nullptr;
3093 if (getParser().parseExpression(ShiftExpr, EndLoc)) {
3094 Error(ImmLoc, "invalid immediate shift value");
3097 // The expression must be evaluatable as an immediate.
3098 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftExpr);
3100 Error(ImmLoc, "invalid immediate shift value");
3103 // Range check the immediate.
3104 // lsl, ror: 0 <= imm <= 31
3105 // lsr, asr: 0 <= imm <= 32
3106 Imm = CE->getValue();
3108 ((ShiftTy == ARM_AM::lsl || ShiftTy == ARM_AM::ror) && Imm > 31) ||
3109 ((ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr) && Imm > 32)) {
3110 Error(ImmLoc, "immediate shift value out of range");
3113 // shift by zero is a nop. Always send it through as lsl.
3114 // ('as' compatibility)
3116 ShiftTy = ARM_AM::lsl;
3117 } else if (Parser.getTok().is(AsmToken::Identifier)) {
3118 SMLoc L = Parser.getTok().getLoc();
3119 EndLoc = Parser.getTok().getEndLoc();
3120 ShiftReg = tryParseRegister();
3121 if (ShiftReg == -1) {
3122 Error(L, "expected immediate or register in shift operand");
3126 Error(Parser.getTok().getLoc(),
3127 "expected immediate or register in shift operand");
3132 if (ShiftReg && ShiftTy != ARM_AM::rrx)
3133 Operands.push_back(ARMOperand::CreateShiftedRegister(ShiftTy, SrcReg,
3137 Operands.push_back(ARMOperand::CreateShiftedImmediate(ShiftTy, SrcReg, Imm,
3144 /// Try to parse a register name. The token must be an Identifier when called.
3145 /// If it's a register, an AsmOperand is created. Another AsmOperand is created
3146 /// if there is a "writeback". 'true' if it's not a register.
3148 /// TODO this is likely to change to allow different register types and or to
3149 /// parse for a specific register type.
3150 bool ARMAsmParser::tryParseRegisterWithWriteBack(OperandVector &Operands) {
3151 MCAsmParser &Parser = getParser();
3152 const AsmToken &RegTok = Parser.getTok();
3153 int RegNo = tryParseRegister();
3157 Operands.push_back(ARMOperand::CreateReg(RegNo, RegTok.getLoc(),
3158 RegTok.getEndLoc()));
3160 const AsmToken &ExclaimTok = Parser.getTok();
3161 if (ExclaimTok.is(AsmToken::Exclaim)) {
3162 Operands.push_back(ARMOperand::CreateToken(ExclaimTok.getString(),
3163 ExclaimTok.getLoc()));
3164 Parser.Lex(); // Eat exclaim token
3168 // Also check for an index operand. This is only legal for vector registers,
3169 // but that'll get caught OK in operand matching, so we don't need to
3170 // explicitly filter everything else out here.
3171 if (Parser.getTok().is(AsmToken::LBrac)) {
3172 SMLoc SIdx = Parser.getTok().getLoc();
3173 Parser.Lex(); // Eat left bracket token.
3175 const MCExpr *ImmVal;
3176 if (getParser().parseExpression(ImmVal))
3178 const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
3180 return TokError("immediate value expected for vector index");
3182 if (Parser.getTok().isNot(AsmToken::RBrac))
3183 return Error(Parser.getTok().getLoc(), "']' expected");
3185 SMLoc E = Parser.getTok().getEndLoc();
3186 Parser.Lex(); // Eat right bracket token.
3188 Operands.push_back(ARMOperand::CreateVectorIndex(MCE->getValue(),
3196 /// MatchCoprocessorOperandName - Try to parse an coprocessor related
3197 /// instruction with a symbolic operand name.
3198 /// We accept "crN" syntax for GAS compatibility.
3199 /// <operand-name> ::= <prefix><number>
3200 /// If CoprocOp is 'c', then:
3201 /// <prefix> ::= c | cr
3202 /// If CoprocOp is 'p', then :
3204 /// <number> ::= integer in range [0, 15]
3205 static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
3206 // Use the same layout as the tablegen'erated register name matcher. Ugly,
3208 if (Name.size() < 2 || Name[0] != CoprocOp)
3210 Name = (Name[1] == 'r') ? Name.drop_front(2) : Name.drop_front();
3212 switch (Name.size()) {
3233 // CP10 and CP11 are VFP/NEON and so vector instructions should be used.
3234 // However, old cores (v5/v6) did use them in that way.
3235 case '0': return 10;
3236 case '1': return 11;
3237 case '2': return 12;
3238 case '3': return 13;
3239 case '4': return 14;
3240 case '5': return 15;
3245 /// parseITCondCode - Try to parse a condition code for an IT instruction.
3246 ARMAsmParser::OperandMatchResultTy
3247 ARMAsmParser::parseITCondCode(OperandVector &Operands) {
3248 MCAsmParser &Parser = getParser();
3249 SMLoc S = Parser.getTok().getLoc();
3250 const AsmToken &Tok = Parser.getTok();
3251 if (!Tok.is(AsmToken::Identifier))
3252 return MatchOperand_NoMatch;
3253 unsigned CC = StringSwitch<unsigned>(Tok.getString().lower())
3254 .Case("eq", ARMCC::EQ)
3255 .Case("ne", ARMCC::NE)
3256 .Case("hs", ARMCC::HS)
3257 .Case("cs", ARMCC::HS)
3258 .Case("lo", ARMCC::LO)
3259 .Case("cc", ARMCC::LO)
3260 .Case("mi", ARMCC::MI)
3261 .Case("pl", ARMCC::PL)
3262 .Case("vs", ARMCC::VS)
3263 .Case("vc", ARMCC::VC)
3264 .Case("hi", ARMCC::HI)
3265 .Case("ls", ARMCC::LS)
3266 .Case("ge", ARMCC::GE)
3267 .Case("lt", ARMCC::LT)
3268 .Case("gt", ARMCC::GT)
3269 .Case("le", ARMCC::LE)
3270 .Case("al", ARMCC::AL)
3273 return MatchOperand_NoMatch;
3274 Parser.Lex(); // Eat the token.
3276 Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
3278 return MatchOperand_Success;
3281 /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
3282 /// token must be an Identifier when called, and if it is a coprocessor
3283 /// number, the token is eaten and the operand is added to the operand list.
3284 ARMAsmParser::OperandMatchResultTy
3285 ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
3286 MCAsmParser &Parser = getParser();
3287 SMLoc S = Parser.getTok().getLoc();
3288 const AsmToken &Tok = Parser.getTok();
3289 if (Tok.isNot(AsmToken::Identifier))
3290 return MatchOperand_NoMatch;
3292 int Num = MatchCoprocessorOperandName(Tok.getString(), 'p');
3294 return MatchOperand_NoMatch;
3295 // ARMv7 and v8 don't allow cp10/cp11 due to VFP/NEON specific instructions
3296 if ((hasV7Ops() || hasV8Ops()) && (Num == 10 || Num == 11))
3297 return MatchOperand_NoMatch;
3299 Parser.Lex(); // Eat identifier token.
3300 Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
3301 return MatchOperand_Success;
3304 /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
3305 /// token must be an Identifier when called, and if it is a coprocessor
3306 /// number, the token is eaten and the operand is added to the operand list.
3307 ARMAsmParser::OperandMatchResultTy
3308 ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
3309 MCAsmParser &Parser = getParser();
3310 SMLoc S = Parser.getTok().getLoc();
3311 const AsmToken &Tok = Parser.getTok();
3312 if (Tok.isNot(AsmToken::Identifier))
3313 return MatchOperand_NoMatch;
3315 int Reg = MatchCoprocessorOperandName(Tok.getString(), 'c');
3317 return MatchOperand_NoMatch;
3319 Parser.Lex(); // Eat identifier token.
3320 Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
3321 return MatchOperand_Success;
3324 /// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
3325 /// coproc_option : '{' imm0_255 '}'
3326 ARMAsmParser::OperandMatchResultTy
3327 ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
3328 MCAsmParser &Parser = getParser();
3329 SMLoc S = Parser.getTok().getLoc();
3331 // If this isn't a '{', this isn't a coprocessor immediate operand.
3332 if (Parser.getTok().isNot(AsmToken::LCurly))
3333 return MatchOperand_NoMatch;
3334 Parser.Lex(); // Eat the '{'
3337 SMLoc Loc = Parser.getTok().getLoc();
3338 if (getParser().parseExpression(Expr)) {
3339 Error(Loc, "illegal expression");
3340 return MatchOperand_ParseFail;
3342 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
3343 if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
3344 Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
3345 return MatchOperand_ParseFail;
3347 int Val = CE->getValue();
3349 // Check for and consume the closing '}'
3350 if (Parser.getTok().isNot(AsmToken::RCurly))
3351 return MatchOperand_ParseFail;
3352 SMLoc E = Parser.getTok().getEndLoc();
3353 Parser.Lex(); // Eat the '}'
3355 Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
3356 return MatchOperand_Success;
3359 // For register list parsing, we need to map from raw GPR register numbering
3360 // to the enumeration values. The enumeration values aren't sorted by
3361 // register number due to our using "sp", "lr" and "pc" as canonical names.
3362 static unsigned getNextRegister(unsigned Reg) {
3363 // If this is a GPR, we need to do it manually, otherwise we can rely
3364 // on the sort ordering of the enumeration since the other reg-classes
3366 if (!ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3369 default: llvm_unreachable("Invalid GPR number!");
3370 case ARM::R0: return ARM::R1; case ARM::R1: return ARM::R2;
3371 case ARM::R2: return ARM::R3; case ARM::R3: return ARM::R4;
3372 case ARM::R4: return ARM::R5; case ARM::R5: return ARM::R6;
3373 case ARM::R6: return ARM::R7; case ARM::R7: return ARM::R8;
3374 case ARM::R8: return ARM::R9; case ARM::R9: return ARM::R10;
3375 case ARM::R10: return ARM::R11; case ARM::R11: return ARM::R12;
3376 case ARM::R12: return ARM::SP; case ARM::SP: return ARM::LR;
3377 case ARM::LR: return ARM::PC; case ARM::PC: return ARM::R0;
3381 // Return the low-subreg of a given Q register.
3382 static unsigned getDRegFromQReg(unsigned QReg) {
3384 default: llvm_unreachable("expected a Q register!");
3385 case ARM::Q0: return ARM::D0;
3386 case ARM::Q1: return ARM::D2;
3387 case ARM::Q2: return ARM::D4;
3388 case ARM::Q3: return ARM::D6;
3389 case ARM::Q4: return ARM::D8;
3390 case ARM::Q5: return ARM::D10;
3391 case ARM::Q6: return ARM::D12;
3392 case ARM::Q7: return ARM::D14;
3393 case ARM::Q8: return ARM::D16;
3394 case ARM::Q9: return ARM::D18;
3395 case ARM::Q10: return ARM::D20;
3396 case ARM::Q11: return ARM::D22;
3397 case ARM::Q12: return ARM::D24;
3398 case ARM::Q13: return ARM::D26;
3399 case ARM::Q14: return ARM::D28;
3400 case ARM::Q15: return ARM::D30;
3404 /// Parse a register list.
3405 bool ARMAsmParser::parseRegisterList(OperandVector &Operands) {
3406 MCAsmParser &Parser = getParser();
3407 assert(Parser.getTok().is(AsmToken::LCurly) &&
3408 "Token is not a Left Curly Brace");
3409 SMLoc S = Parser.getTok().getLoc();
3410 Parser.Lex(); // Eat '{' token.
3411 SMLoc RegLoc = Parser.getTok().getLoc();
3413 // Check the first register in the list to see what register class
3414 // this is a list of.
3415 int Reg = tryParseRegister();
3417 return Error(RegLoc, "register expected");
3419 // The reglist instructions have at most 16 registers, so reserve
3420 // space for that many.
3422 SmallVector<std::pair<unsigned, unsigned>, 16> Registers;
3424 // Allow Q regs and just interpret them as the two D sub-registers.
3425 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3426 Reg = getDRegFromQReg(Reg);
3427 EReg = MRI->getEncodingValue(Reg);
3428 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3431 const MCRegisterClass *RC;
3432 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3433 RC = &ARMMCRegisterClasses[ARM::GPRRegClassID];
3434 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg))
3435 RC = &ARMMCRegisterClasses[ARM::DPRRegClassID];
3436 else if (ARMMCRegisterClasses[ARM::SPRRegClassID].contains(Reg))
3437 RC = &ARMMCRegisterClasses[ARM::SPRRegClassID];
3439 return Error(RegLoc, "invalid register in register list");
3441 // Store the register.
3442 EReg = MRI->getEncodingValue(Reg);
3443 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3445 // This starts immediately after the first register token in the list,
3446 // so we can see either a comma or a minus (range separator) as a legal
3448 while (Parser.getTok().is(AsmToken::Comma) ||
3449 Parser.getTok().is(AsmToken::Minus)) {
3450 if (Parser.getTok().is(AsmToken::Minus)) {
3451 Parser.Lex(); // Eat the minus.
3452 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3453 int EndReg = tryParseRegister();
3455 return Error(AfterMinusLoc, "register expected");
3456 // Allow Q regs and just interpret them as the two D sub-registers.
3457 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3458 EndReg = getDRegFromQReg(EndReg) + 1;
3459 // If the register is the same as the start reg, there's nothing
3463 // The register must be in the same register class as the first.
3464 if (!RC->contains(EndReg))
3465 return Error(AfterMinusLoc, "invalid register in register list");
3466 // Ranges must go from low to high.
3467 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
3468 return Error(AfterMinusLoc, "bad range in register list");
3470 // Add all the registers in the range to the register list.
3471 while (Reg != EndReg) {
3472 Reg = getNextRegister(Reg);
3473 EReg = MRI->getEncodingValue(Reg);
3474 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3478 Parser.Lex(); // Eat the comma.
3479 RegLoc = Parser.getTok().getLoc();
3481 const AsmToken RegTok = Parser.getTok();
3482 Reg = tryParseRegister();
3484 return Error(RegLoc, "register expected");
3485 // Allow Q regs and just interpret them as the two D sub-registers.
3486 bool isQReg = false;
3487 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3488 Reg = getDRegFromQReg(Reg);
3491 // The register must be in the same register class as the first.
3492 if (!RC->contains(Reg))
3493 return Error(RegLoc, "invalid register in register list");
3494 // List must be monotonically increasing.
3495 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
3496 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
3497 Warning(RegLoc, "register list not in ascending order");
3499 return Error(RegLoc, "register list not in ascending order");
3501 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
3502 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
3503 ") in register list");
3506 // VFP register lists must also be contiguous.
3507 if (RC != &ARMMCRegisterClasses[ARM::GPRRegClassID] &&
3509 return Error(RegLoc, "non-contiguous register range");
3510 EReg = MRI->getEncodingValue(Reg);
3511 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3513 EReg = MRI->getEncodingValue(++Reg);
3514 Registers.push_back(std::pair<unsigned, unsigned>(EReg, Reg));
3518 if (Parser.getTok().isNot(AsmToken::RCurly))
3519 return Error(Parser.getTok().getLoc(), "'}' expected");
3520 SMLoc E = Parser.getTok().getEndLoc();
3521 Parser.Lex(); // Eat '}' token.
3523 // Push the register list operand.
3524 Operands.push_back(ARMOperand::CreateRegList(Registers, S, E));
3526 // The ARM system instruction variants for LDM/STM have a '^' token here.
3527 if (Parser.getTok().is(AsmToken::Caret)) {
3528 Operands.push_back(ARMOperand::CreateToken("^",Parser.getTok().getLoc()));
3529 Parser.Lex(); // Eat '^' token.
3535 // Helper function to parse the lane index for vector lists.
3536 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
3537 parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
3538 MCAsmParser &Parser = getParser();
3539 Index = 0; // Always return a defined index value.
3540 if (Parser.getTok().is(AsmToken::LBrac)) {
3541 Parser.Lex(); // Eat the '['.
3542 if (Parser.getTok().is(AsmToken::RBrac)) {
3543 // "Dn[]" is the 'all lanes' syntax.
3544 LaneKind = AllLanes;
3545 EndLoc = Parser.getTok().getEndLoc();
3546 Parser.Lex(); // Eat the ']'.
3547 return MatchOperand_Success;
3550 // There's an optional '#' token here. Normally there wouldn't be, but
3551 // inline assemble puts one in, and it's friendly to accept that.
3552 if (Parser.getTok().is(AsmToken::Hash))
3553 Parser.Lex(); // Eat '#' or '$'.
3555 const MCExpr *LaneIndex;
3556 SMLoc Loc = Parser.getTok().getLoc();
3557 if (getParser().parseExpression(LaneIndex)) {
3558 Error(Loc, "illegal expression");
3559 return MatchOperand_ParseFail;
3561 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
3563 Error(Loc, "lane index must be empty or an integer");
3564 return MatchOperand_ParseFail;
3566 if (Parser.getTok().isNot(AsmToken::RBrac)) {
3567 Error(Parser.getTok().getLoc(), "']' expected");
3568 return MatchOperand_ParseFail;
3570 EndLoc = Parser.getTok().getEndLoc();
3571 Parser.Lex(); // Eat the ']'.
3572 int64_t Val = CE->getValue();
3574 // FIXME: Make this range check context sensitive for .8, .16, .32.
3575 if (Val < 0 || Val > 7) {
3576 Error(Parser.getTok().getLoc(), "lane index out of range");
3577 return MatchOperand_ParseFail;
3580 LaneKind = IndexedLane;
3581 return MatchOperand_Success;
3584 return MatchOperand_Success;
3587 // parse a vector register list
3588 ARMAsmParser::OperandMatchResultTy
3589 ARMAsmParser::parseVectorList(OperandVector &Operands) {
3590 MCAsmParser &Parser = getParser();
3591 VectorLaneTy LaneKind;
3593 SMLoc S = Parser.getTok().getLoc();
3594 // As an extension (to match gas), support a plain D register or Q register
3595 // (without encosing curly braces) as a single or double entry list,
3597 if (Parser.getTok().is(AsmToken::Identifier)) {
3598 SMLoc E = Parser.getTok().getEndLoc();
3599 int Reg = tryParseRegister();
3601 return MatchOperand_NoMatch;
3602 if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
3603 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3604 if (Res != MatchOperand_Success)
3608 Operands.push_back(ARMOperand::CreateVectorList(Reg, 1, false, S, E));
3611 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 1, false,
3615 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 1,
3620 return MatchOperand_Success;
3622 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3623 Reg = getDRegFromQReg(Reg);
3624 OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
3625 if (Res != MatchOperand_Success)
3629 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3630 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3631 Operands.push_back(ARMOperand::CreateVectorList(Reg, 2, false, S, E));
3634 Reg = MRI->getMatchingSuperReg(Reg, ARM::dsub_0,
3635 &ARMMCRegisterClasses[ARM::DPairRegClassID]);
3636 Operands.push_back(ARMOperand::CreateVectorListAllLanes(Reg, 2, false,
3640 Operands.push_back(ARMOperand::CreateVectorListIndexed(Reg, 2,
3645 return MatchOperand_Success;
3647 Error(S, "vector register expected");
3648 return MatchOperand_ParseFail;
3651 if (Parser.getTok().isNot(AsmToken::LCurly))
3652 return MatchOperand_NoMatch;
3654 Parser.Lex(); // Eat '{' token.
3655 SMLoc RegLoc = Parser.getTok().getLoc();
3657 int Reg = tryParseRegister();
3659 Error(RegLoc, "register expected");
3660 return MatchOperand_ParseFail;
3664 unsigned FirstReg = Reg;
3665 // The list is of D registers, but we also allow Q regs and just interpret
3666 // them as the two D sub-registers.
3667 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3668 FirstReg = Reg = getDRegFromQReg(Reg);
3669 Spacing = 1; // double-spacing requires explicit D registers, otherwise
3670 // it's ambiguous with four-register single spaced.
3676 if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
3677 return MatchOperand_ParseFail;
3679 while (Parser.getTok().is(AsmToken::Comma) ||
3680 Parser.getTok().is(AsmToken::Minus)) {
3681 if (Parser.getTok().is(AsmToken::Minus)) {
3683 Spacing = 1; // Register range implies a single spaced list.
3684 else if (Spacing == 2) {
3685 Error(Parser.getTok().getLoc(),
3686 "sequential registers in double spaced list");
3687 return MatchOperand_ParseFail;
3689 Parser.Lex(); // Eat the minus.
3690 SMLoc AfterMinusLoc = Parser.getTok().getLoc();
3691 int EndReg = tryParseRegister();
3693 Error(AfterMinusLoc, "register expected");
3694 return MatchOperand_ParseFail;
3696 // Allow Q regs and just interpret them as the two D sub-registers.
3697 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
3698 EndReg = getDRegFromQReg(EndReg) + 1;
3699 // If the register is the same as the start reg, there's nothing
3703 // The register must be in the same register class as the first.
3704 if (!ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)) {
3705 Error(AfterMinusLoc, "invalid register in register list");
3706 return MatchOperand_ParseFail;
3708 // Ranges must go from low to high.
3710 Error(AfterMinusLoc, "bad range in register list");
3711 return MatchOperand_ParseFail;
3713 // Parse the lane specifier if present.
3714 VectorLaneTy NextLaneKind;
3715 unsigned NextLaneIndex;
3716 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3717 MatchOperand_Success)
3718 return MatchOperand_ParseFail;
3719 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3720 Error(AfterMinusLoc, "mismatched lane index in register list");
3721 return MatchOperand_ParseFail;
3724 // Add all the registers in the range to the register list.
3725 Count += EndReg - Reg;
3729 Parser.Lex(); // Eat the comma.
3730 RegLoc = Parser.getTok().getLoc();
3732 Reg = tryParseRegister();
3734 Error(RegLoc, "register expected");
3735 return MatchOperand_ParseFail;
3737 // vector register lists must be contiguous.
3738 // It's OK to use the enumeration values directly here rather, as the
3739 // VFP register classes have the enum sorted properly.
3741 // The list is of D registers, but we also allow Q regs and just interpret
3742 // them as the two D sub-registers.
3743 if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
3745 Spacing = 1; // Register range implies a single spaced list.
3746 else if (Spacing == 2) {
3748 "invalid register in double-spaced list (must be 'D' register')");
3749 return MatchOperand_ParseFail;
3751 Reg = getDRegFromQReg(Reg);
3752 if (Reg != OldReg + 1) {
3753 Error(RegLoc, "non-contiguous register range");
3754 return MatchOperand_ParseFail;
3758 // Parse the lane specifier if present.
3759 VectorLaneTy NextLaneKind;
3760 unsigned NextLaneIndex;
3761 SMLoc LaneLoc = Parser.getTok().getLoc();
3762 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
3763 MatchOperand_Success)
3764 return MatchOperand_ParseFail;
3765 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3766 Error(LaneLoc, "mismatched lane index in register list");
3767 return MatchOperand_ParseFail;
3771 // Normal D register.
3772 // Figure out the register spacing (single or double) of the list if
3773 // we don't know it already.
3775 Spacing = 1 + (Reg == OldReg + 2);
3777 // Just check that it's contiguous and keep going.
3778 if (Reg != OldReg + Spacing) {
3779 Error(RegLoc, "non-contiguous register range");
3780 return MatchOperand_ParseFail;
3783 // Parse the lane specifier if present.
3784 VectorLaneTy NextLaneKind;
3785 unsigned NextLaneIndex;
3786 SMLoc EndLoc = Parser.getTok().getLoc();
3787 if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
3788 return MatchOperand_ParseFail;
3789 if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
3790 Error(EndLoc, "mismatched lane index in register list");
3791 return MatchOperand_ParseFail;
3795 if (Parser.getTok().isNot(AsmToken::RCurly)) {
3796 Error(Parser.getTok().getLoc(), "'}' expected");
3797 return MatchOperand_ParseFail;
3799 E = Parser.getTok().getEndLoc();
3800 Parser.Lex(); // Eat '}' token.
3804 // Two-register operands have been converted to the
3805 // composite register classes.
3807 const MCRegisterClass *RC = (Spacing == 1) ?
3808 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3809 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3810 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3813 Operands.push_back(ARMOperand::CreateVectorList(FirstReg, Count,
3814 (Spacing == 2), S, E));
3817 // Two-register operands have been converted to the
3818 // composite register classes.
3820 const MCRegisterClass *RC = (Spacing == 1) ?
3821 &ARMMCRegisterClasses[ARM::DPairRegClassID] :
3822 &ARMMCRegisterClasses[ARM::DPairSpcRegClassID];
3823 FirstReg = MRI->getMatchingSuperReg(FirstReg, ARM::dsub_0, RC);
3825 Operands.push_back(ARMOperand::CreateVectorListAllLanes(FirstReg, Count,
3830 Operands.push_back(ARMOperand::CreateVectorListIndexed(FirstReg, Count,
3836 return MatchOperand_Success;
3839 /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
3840 ARMAsmParser::OperandMatchResultTy
3841 ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
3842 MCAsmParser &Parser = getParser();
3843 SMLoc S = Parser.getTok().getLoc();
3844 const AsmToken &Tok = Parser.getTok();
3847 if (Tok.is(AsmToken::Identifier)) {
3848 StringRef OptStr = Tok.getString();
3850 Opt = StringSwitch<unsigned>(OptStr.slice(0, OptStr.size()).lower())
3851 .Case("sy", ARM_MB::SY)
3852 .Case("st", ARM_MB::ST)
3853 .Case("ld", ARM_MB::LD)
3854 .Case("sh", ARM_MB::ISH)
3855 .Case("ish", ARM_MB::ISH)
3856 .Case("shst", ARM_MB::ISHST)
3857 .Case("ishst", ARM_MB::ISHST)
3858 .Case("ishld", ARM_MB::ISHLD)
3859 .Case("nsh", ARM_MB::NSH)
3860 .Case("un", ARM_MB::NSH)
3861 .Case("nshst", ARM_MB::NSHST)
3862 .Case("nshld", ARM_MB::NSHLD)
3863 .Case("unst", ARM_MB::NSHST)
3864 .Case("osh", ARM_MB::OSH)
3865 .Case("oshst", ARM_MB::OSHST)
3866 .Case("oshld", ARM_MB::OSHLD)
3869 // ishld, oshld, nshld and ld are only available from ARMv8.
3870 if (!hasV8Ops() && (Opt == ARM_MB::ISHLD || Opt == ARM_MB::OSHLD ||
3871 Opt == ARM_MB::NSHLD || Opt == ARM_MB::LD))
3875 return MatchOperand_NoMatch;
3877 Parser.Lex(); // Eat identifier token.
3878 } else if (Tok.is(AsmToken::Hash) ||
3879 Tok.is(AsmToken::Dollar) ||
3880 Tok.is(AsmToken::Integer)) {
3881 if (Parser.getTok().isNot(AsmToken::Integer))
3882 Parser.Lex(); // Eat '#' or '$'.
3883 SMLoc Loc = Parser.getTok().getLoc();
3885 const MCExpr *MemBarrierID;
3886 if (getParser().parseExpression(MemBarrierID)) {
3887 Error(Loc, "illegal expression");
3888 return MatchOperand_ParseFail;
3891 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
3893 Error(Loc, "constant expression expected");
3894 return MatchOperand_ParseFail;
3897 int Val = CE->getValue();
3899 Error(Loc, "immediate value out of range");
3900 return MatchOperand_ParseFail;
3903 Opt = ARM_MB::RESERVED_0 + Val;
3905 return MatchOperand_ParseFail;
3907 Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
3908 return MatchOperand_Success;
3911 /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
3912 ARMAsmParser::OperandMatchResultTy
3913 ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
3914 MCAsmParser &Parser = getParser();
3915 SMLoc S = Parser.getTok().getLoc();
3916 const AsmToken &Tok = Parser.getTok();
3919 if (Tok.is(AsmToken::Identifier)) {
3920 StringRef OptStr = Tok.getString();
3922 if (OptStr.equals_lower("sy"))
3925 return MatchOperand_NoMatch;
3927 Parser.Lex(); // Eat identifier token.
3928 } else if (Tok.is(AsmToken::Hash) ||
3929 Tok.is(AsmToken::Dollar) ||
3930 Tok.is(AsmToken::Integer)) {
3931 if (Parser.getTok().isNot(AsmToken::Integer))
3932 Parser.Lex(); // Eat '#' or '$'.
3933 SMLoc Loc = Parser.getTok().getLoc();
3935 const MCExpr *ISBarrierID;
3936 if (getParser().parseExpression(ISBarrierID)) {
3937 Error(Loc, "illegal expression");
3938 return MatchOperand_ParseFail;
3941 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
3943 Error(Loc, "constant expression expected");
3944 return MatchOperand_ParseFail;
3947 int Val = CE->getValue();
3949 Error(Loc, "immediate value out of range");
3950 return MatchOperand_ParseFail;
3953 Opt = ARM_ISB::RESERVED_0 + Val;
3955 return MatchOperand_ParseFail;
3957 Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
3958 (ARM_ISB::InstSyncBOpt)Opt, S));
3959 return MatchOperand_Success;
3963 /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
3964 ARMAsmParser::OperandMatchResultTy
3965 ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
3966 MCAsmParser &Parser = getParser();
3967 SMLoc S = Parser.getTok().getLoc();
3968 const AsmToken &Tok = Parser.getTok();
3969 if (!Tok.is(AsmToken::Identifier))
3970 return MatchOperand_NoMatch;
3971 StringRef IFlagsStr = Tok.getString();
3973 // An iflags string of "none" is interpreted to mean that none of the AIF
3974 // bits are set. Not a terribly useful instruction, but a valid encoding.
3975 unsigned IFlags = 0;
3976 if (IFlagsStr != "none") {
3977 for (int i = 0, e = IFlagsStr.size(); i != e; ++i) {
3978 unsigned Flag = StringSwitch<unsigned>(IFlagsStr.substr(i, 1))
3979 .Case("a", ARM_PROC::A)
3980 .Case("i", ARM_PROC::I)
3981 .Case("f", ARM_PROC::F)
3984 // If some specific iflag is already set, it means that some letter is
3985 // present more than once, this is not acceptable.
3986 if (Flag == ~0U || (IFlags & Flag))
3987 return MatchOperand_NoMatch;
3993 Parser.Lex(); // Eat identifier token.
3994 Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
3995 return MatchOperand_Success;
3998 /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
3999 ARMAsmParser::OperandMatchResultTy
4000 ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
4001 MCAsmParser &Parser = getParser();
4002 SMLoc S = Parser.getTok().getLoc();
4003 const AsmToken &Tok = Parser.getTok();
4004 if (!Tok.is(AsmToken::Identifier))
4005 return MatchOperand_NoMatch;
4006 StringRef Mask = Tok.getString();
4009 // See ARMv6-M 10.1.1
4010 std::string Name = Mask.lower();
4011 unsigned FlagsVal = StringSwitch<unsigned>(Name)
4012 // Note: in the documentation:
4013 // ARM deprecates using MSR APSR without a _<bits> qualifier as an alias
4014 // for MSR APSR_nzcvq.
4015 // but we do make it an alias here. This is so to get the "mask encoding"
4016 // bits correct on MSR APSR writes.
4018 // FIXME: Note the 0xc00 "mask encoding" bits version of the registers
4019 // should really only be allowed when writing a special register. Note
4020 // they get dropped in the MRS instruction reading a special register as
4021 // the SYSm field is only 8 bits.
4022 .Case("apsr", 0x800)
4023 .Case("apsr_nzcvq", 0x800)
4024 .Case("apsr_g", 0x400)
4025 .Case("apsr_nzcvqg", 0xc00)
4026 .Case("iapsr", 0x801)
4027 .Case("iapsr_nzcvq", 0x801)
4028 .Case("iapsr_g", 0x401)
4029 .Case("iapsr_nzcvqg", 0xc01)
4030 .Case("eapsr", 0x802)
4031 .Case("eapsr_nzcvq", 0x802)
4032 .Case("eapsr_g", 0x402)
4033 .Case("eapsr_nzcvqg", 0xc02)
4034 .Case("xpsr", 0x803)
4035 .Case("xpsr_nzcvq", 0x803)
4036 .Case("xpsr_g", 0x403)
4037 .Case("xpsr_nzcvqg", 0xc03)
4038 .Case("ipsr", 0x805)
4039 .Case("epsr", 0x806)
4040 .Case("iepsr", 0x807)
4043 .Case("primask", 0x810)
4044 .Case("basepri", 0x811)
4045 .Case("basepri_max", 0x812)
4046 .Case("faultmask", 0x813)
4047 .Case("control", 0x814)
4050 if (FlagsVal == ~0U)
4051 return MatchOperand_NoMatch;
4053 if (!hasThumb2DSP() && (FlagsVal & 0x400))
4054 // The _g and _nzcvqg versions are only valid if the DSP extension is
4056 return MatchOperand_NoMatch;
4058 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
4059 // basepri, basepri_max and faultmask only valid for V7m.
4060 return MatchOperand_NoMatch;
4062 Parser.Lex(); // Eat identifier token.
4063 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4064 return MatchOperand_Success;
4067 // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
4068 size_t Start = 0, Next = Mask.find('_');
4069 StringRef Flags = "";
4070 std::string SpecReg = Mask.slice(Start, Next).lower();
4071 if (Next != StringRef::npos)
4072 Flags = Mask.slice(Next+1, Mask.size());
4074 // FlagsVal contains the complete mask:
4076 // 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4077 unsigned FlagsVal = 0;
4079 if (SpecReg == "apsr") {
4080 FlagsVal = StringSwitch<unsigned>(Flags)
4081 .Case("nzcvq", 0x8) // same as CPSR_f
4082 .Case("g", 0x4) // same as CPSR_s
4083 .Case("nzcvqg", 0xc) // same as CPSR_fs
4086 if (FlagsVal == ~0U) {
4088 return MatchOperand_NoMatch;
4090 FlagsVal = 8; // No flag
4092 } else if (SpecReg == "cpsr" || SpecReg == "spsr") {
4093 // cpsr_all is an alias for cpsr_fc, as is plain cpsr.
4094 if (Flags == "all" || Flags == "")
4096 for (int i = 0, e = Flags.size(); i != e; ++i) {
4097 unsigned Flag = StringSwitch<unsigned>(Flags.substr(i, 1))
4104 // If some specific flag is already set, it means that some letter is
4105 // present more than once, this is not acceptable.
4106 if (FlagsVal == ~0U || (FlagsVal & Flag))
4107 return MatchOperand_NoMatch;
4110 } else // No match for special register.
4111 return MatchOperand_NoMatch;
4113 // Special register without flags is NOT equivalent to "fc" flags.
4114 // NOTE: This is a divergence from gas' behavior. Uncommenting the following
4115 // two lines would enable gas compatibility at the expense of breaking
4121 // Bit 4: Special Reg (cpsr, apsr => 0; spsr => 1)
4122 if (SpecReg == "spsr")
4125 Parser.Lex(); // Eat identifier token.
4126 Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
4127 return MatchOperand_Success;
4130 /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
4131 /// use in the MRS/MSR instructions added to support virtualization.
4132 ARMAsmParser::OperandMatchResultTy
4133 ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
4134 MCAsmParser &Parser = getParser();
4135 SMLoc S = Parser.getTok().getLoc();
4136 const AsmToken &Tok = Parser.getTok();
4137 if (!Tok.is(AsmToken::Identifier))
4138 return MatchOperand_NoMatch;
4139 StringRef RegName = Tok.getString();
4141 // The values here come from B9.2.3 of the ARM ARM, where bits 4-0 are SysM
4143 unsigned Encoding = StringSwitch<unsigned>(RegName.lower())
4144 .Case("r8_usr", 0x00)
4145 .Case("r9_usr", 0x01)
4146 .Case("r10_usr", 0x02)
4147 .Case("r11_usr", 0x03)
4148 .Case("r12_usr", 0x04)
4149 .Case("sp_usr", 0x05)
4150 .Case("lr_usr", 0x06)
4151 .Case("r8_fiq", 0x08)
4152 .Case("r9_fiq", 0x09)
4153 .Case("r10_fiq", 0x0a)
4154 .Case("r11_fiq", 0x0b)
4155 .Case("r12_fiq", 0x0c)
4156 .Case("sp_fiq", 0x0d)
4157 .Case("lr_fiq", 0x0e)
4158 .Case("lr_irq", 0x10)
4159 .Case("sp_irq", 0x11)
4160 .Case("lr_svc", 0x12)
4161 .Case("sp_svc", 0x13)
4162 .Case("lr_abt", 0x14)
4163 .Case("sp_abt", 0x15)
4164 .Case("lr_und", 0x16)
4165 .Case("sp_und", 0x17)
4166 .Case("lr_mon", 0x1c)
4167 .Case("sp_mon", 0x1d)
4168 .Case("elr_hyp", 0x1e)
4169 .Case("sp_hyp", 0x1f)
4170 .Case("spsr_fiq", 0x2e)
4171 .Case("spsr_irq", 0x30)
4172 .Case("spsr_svc", 0x32)
4173 .Case("spsr_abt", 0x34)
4174 .Case("spsr_und", 0x36)
4175 .Case("spsr_mon", 0x3c)
4176 .Case("spsr_hyp", 0x3e)
4179 if (Encoding == ~0U)
4180 return MatchOperand_NoMatch;
4182 Parser.Lex(); // Eat identifier token.
4183 Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
4184 return MatchOperand_Success;
4187 ARMAsmParser::OperandMatchResultTy
4188 ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
4190 MCAsmParser &Parser = getParser();
4191 const AsmToken &Tok = Parser.getTok();
4192 if (Tok.isNot(AsmToken::Identifier)) {
4193 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4194 return MatchOperand_ParseFail;
4196 StringRef ShiftName = Tok.getString();
4197 std::string LowerOp = Op.lower();
4198 std::string UpperOp = Op.upper();
4199 if (ShiftName != LowerOp && ShiftName != UpperOp) {
4200 Error(Parser.getTok().getLoc(), Op + " operand expected.");
4201 return MatchOperand_ParseFail;
4203 Parser.Lex(); // Eat shift type token.
4205 // There must be a '#' and a shift amount.
4206 if (Parser.getTok().isNot(AsmToken::Hash) &&
4207 Parser.getTok().isNot(AsmToken::Dollar)) {
4208 Error(Parser.getTok().getLoc(), "'#' expected");
4209 return MatchOperand_ParseFail;
4211 Parser.Lex(); // Eat hash token.
4213 const MCExpr *ShiftAmount;
4214 SMLoc Loc = Parser.getTok().getLoc();
4216 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4217 Error(Loc, "illegal expression");
4218 return MatchOperand_ParseFail;
4220 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4222 Error(Loc, "constant expression expected");
4223 return MatchOperand_ParseFail;
4225 int Val = CE->getValue();
4226 if (Val < Low || Val > High) {
4227 Error(Loc, "immediate value out of range");
4228 return MatchOperand_ParseFail;
4231 Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
4233 return MatchOperand_Success;
4236 ARMAsmParser::OperandMatchResultTy
4237 ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
4238 MCAsmParser &Parser = getParser();
4239 const AsmToken &Tok = Parser.getTok();
4240 SMLoc S = Tok.getLoc();
4241 if (Tok.isNot(AsmToken::Identifier)) {
4242 Error(S, "'be' or 'le' operand expected");
4243 return MatchOperand_ParseFail;
4245 int Val = StringSwitch<int>(Tok.getString().lower())
4249 Parser.Lex(); // Eat the token.
4252 Error(S, "'be' or 'le' operand expected");
4253 return MatchOperand_ParseFail;
4255 Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::Create(Val,
4257 S, Tok.getEndLoc()));
4258 return MatchOperand_Success;
4261 /// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
4262 /// instructions. Legal values are:
4263 /// lsl #n 'n' in [0,31]
4264 /// asr #n 'n' in [1,32]
4265 /// n == 32 encoded as n == 0.
4266 ARMAsmParser::OperandMatchResultTy
4267 ARMAsmParser::parseShifterImm(OperandVector &Operands) {
4268 MCAsmParser &Parser = getParser();
4269 const AsmToken &Tok = Parser.getTok();
4270 SMLoc S = Tok.getLoc();
4271 if (Tok.isNot(AsmToken::Identifier)) {
4272 Error(S, "shift operator 'asr' or 'lsl' expected");
4273 return MatchOperand_ParseFail;
4275 StringRef ShiftName = Tok.getString();
4277 if (ShiftName == "lsl" || ShiftName == "LSL")
4279 else if (ShiftName == "asr" || ShiftName == "ASR")
4282 Error(S, "shift operator 'asr' or 'lsl' expected");
4283 return MatchOperand_ParseFail;
4285 Parser.Lex(); // Eat the operator.
4287 // A '#' and a shift amount.
4288 if (Parser.getTok().isNot(AsmToken::Hash) &&
4289 Parser.getTok().isNot(AsmToken::Dollar)) {
4290 Error(Parser.getTok().getLoc(), "'#' expected");
4291 return MatchOperand_ParseFail;
4293 Parser.Lex(); // Eat hash token.
4294 SMLoc ExLoc = Parser.getTok().getLoc();
4296 const MCExpr *ShiftAmount;
4298 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4299 Error(ExLoc, "malformed shift expression");
4300 return MatchOperand_ParseFail;
4302 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4304 Error(ExLoc, "shift amount must be an immediate");
4305 return MatchOperand_ParseFail;
4308 int64_t Val = CE->getValue();
4310 // Shift amount must be in [1,32]
4311 if (Val < 1 || Val > 32) {
4312 Error(ExLoc, "'asr' shift amount must be in range [1,32]");
4313 return MatchOperand_ParseFail;
4315 // asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
4316 if (isThumb() && Val == 32) {
4317 Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
4318 return MatchOperand_ParseFail;
4320 if (Val == 32) Val = 0;
4322 // Shift amount must be in [1,32]
4323 if (Val < 0 || Val > 31) {
4324 Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
4325 return MatchOperand_ParseFail;
4329 Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
4331 return MatchOperand_Success;
4334 /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
4335 /// of instructions. Legal values are:
4336 /// ror #n 'n' in {0, 8, 16, 24}
4337 ARMAsmParser::OperandMatchResultTy
4338 ARMAsmParser::parseRotImm(OperandVector &Operands) {
4339 MCAsmParser &Parser = getParser();
4340 const AsmToken &Tok = Parser.getTok();
4341 SMLoc S = Tok.getLoc();
4342 if (Tok.isNot(AsmToken::Identifier))
4343 return MatchOperand_NoMatch;
4344 StringRef ShiftName = Tok.getString();
4345 if (ShiftName != "ror" && ShiftName != "ROR")
4346 return MatchOperand_NoMatch;
4347 Parser.Lex(); // Eat the operator.
4349 // A '#' and a rotate amount.
4350 if (Parser.getTok().isNot(AsmToken::Hash) &&
4351 Parser.getTok().isNot(AsmToken::Dollar)) {
4352 Error(Parser.getTok().getLoc(), "'#' expected");
4353 return MatchOperand_ParseFail;
4355 Parser.Lex(); // Eat hash token.
4356 SMLoc ExLoc = Parser.getTok().getLoc();
4358 const MCExpr *ShiftAmount;
4360 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
4361 Error(ExLoc, "malformed rotate expression");
4362 return MatchOperand_ParseFail;
4364 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
4366 Error(ExLoc, "rotate amount must be an immediate");
4367 return MatchOperand_ParseFail;
4370 int64_t Val = CE->getValue();
4371 // Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
4372 // normally, zero is represented in asm by omitting the rotate operand
4374 if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
4375 Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
4376 return MatchOperand_ParseFail;
4379 Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
4381 return MatchOperand_Success;
4384 ARMAsmParser::OperandMatchResultTy
4385 ARMAsmParser::parseModImm(OperandVector &Operands) {
4386 MCAsmParser &Parser = getParser();
4387 MCAsmLexer &Lexer = getLexer();
4390 SMLoc S = Parser.getTok().getLoc();
4392 // 1) A mod_imm operand can appear in the place of a register name:
4394 // add r0, r0, #mod_imm
4395 // to correctly handle the latter, we bail out as soon as we see an
4398 // 2) Similarly, we do not want to parse into complex operands:
4400 // mov r0, :lower16:(_foo)
4401 if (Parser.getTok().is(AsmToken::Identifier) ||
4402 Parser.getTok().is(AsmToken::Colon))
4403 return MatchOperand_NoMatch;
4405 // Hash (dollar) is optional as per the ARMARM
4406 if (Parser.getTok().is(AsmToken::Hash) ||
4407 Parser.getTok().is(AsmToken::Dollar)) {
4408 // Avoid parsing into complex operands (#:)
4409 if (Lexer.peekTok().is(AsmToken::Colon))
4410 return MatchOperand_NoMatch;
4412 // Eat the hash (dollar)
4417 Sx1 = Parser.getTok().getLoc();
4418 const MCExpr *Imm1Exp;
4419 if (getParser().parseExpression(Imm1Exp, Ex1)) {
4420 Error(Sx1, "malformed expression");
4421 return MatchOperand_ParseFail;
4424 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
4427 // Immediate must fit within 32-bits
4428 Imm1 = CE->getValue();
4429 int Enc = ARM_AM::getSOImmVal(Imm1);
4430 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4432 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4435 return MatchOperand_Success;
4438 // We have parsed an immediate which is not for us, fallback to a plain
4439 // immediate. This can happen for instruction aliases. For an example,
4440 // ARMInstrInfo.td defines the alias [mov <-> mvn] which can transform
4441 // a mov (mvn) with a mod_imm_neg/mod_imm_not operand into the opposite
4442 // instruction with a mod_imm operand. The alias is defined such that the
4443 // parser method is shared, that's why we have to do this here.
4444 if (Parser.getTok().is(AsmToken::EndOfStatement)) {
4445 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4446 return MatchOperand_Success;
4449 // Operands like #(l1 - l2) can only be evaluated at a later stage (via an
4450 // MCFixup). Fallback to a plain immediate.
4451 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4452 return MatchOperand_Success;
4455 // From this point onward, we expect the input to be a (#bits, #rot) pair
4456 if (Parser.getTok().isNot(AsmToken::Comma)) {
4457 Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
4458 return MatchOperand_ParseFail;
4462 Error(Sx1, "immediate operand must a number in the range [0, 255]");
4463 return MatchOperand_ParseFail;
4471 Sx2 = Parser.getTok().getLoc();
4473 // Eat the optional hash (dollar)
4474 if (Parser.getTok().is(AsmToken::Hash) ||
4475 Parser.getTok().is(AsmToken::Dollar))
4478 const MCExpr *Imm2Exp;
4479 if (getParser().parseExpression(Imm2Exp, Ex2)) {
4480 Error(Sx2, "malformed expression");
4481 return MatchOperand_ParseFail;
4484 CE = dyn_cast<MCConstantExpr>(Imm2Exp);
4487 Imm2 = CE->getValue();
4488 if (!(Imm2 & ~0x1E)) {
4490 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4491 return MatchOperand_Success;
4493 Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4494 return MatchOperand_ParseFail;
4496 Error(Sx2, "constant expression expected");
4497 return MatchOperand_ParseFail;
4501 ARMAsmParser::OperandMatchResultTy
4502 ARMAsmParser::parseBitfield(OperandVector &Operands) {
4503 MCAsmParser &Parser = getParser();
4504 SMLoc S = Parser.getTok().getLoc();
4505 // The bitfield descriptor is really two operands, the LSB and the width.
4506 if (Parser.getTok().isNot(AsmToken::Hash) &&
4507 Parser.getTok().isNot(AsmToken::Dollar)) {
4508 Error(Parser.getTok().getLoc(), "'#' expected");
4509 return MatchOperand_ParseFail;
4511 Parser.Lex(); // Eat hash token.
4513 const MCExpr *LSBExpr;
4514 SMLoc E = Parser.getTok().getLoc();
4515 if (getParser().parseExpression(LSBExpr)) {
4516 Error(E, "malformed immediate expression");
4517 return MatchOperand_ParseFail;
4519 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
4521 Error(E, "'lsb' operand must be an immediate");
4522 return MatchOperand_ParseFail;
4525 int64_t LSB = CE->getValue();
4526 // The LSB must be in the range [0,31]
4527 if (LSB < 0 || LSB > 31) {
4528 Error(E, "'lsb' operand must be in the range [0,31]");
4529 return MatchOperand_ParseFail;
4531 E = Parser.getTok().getLoc();
4533 // Expect another immediate operand.
4534 if (Parser.getTok().isNot(AsmToken::Comma)) {
4535 Error(Parser.getTok().getLoc(), "too few operands");
4536 return MatchOperand_ParseFail;
4538 Parser.Lex(); // Eat hash token.
4539 if (Parser.getTok().isNot(AsmToken::Hash) &&
4540 Parser.getTok().isNot(AsmToken::Dollar)) {
4541 Error(Parser.getTok().getLoc(), "'#' expected");
4542 return MatchOperand_ParseFail;
4544 Parser.Lex(); // Eat hash token.
4546 const MCExpr *WidthExpr;
4548 if (getParser().parseExpression(WidthExpr, EndLoc)) {
4549 Error(E, "malformed immediate expression");
4550 return MatchOperand_ParseFail;
4552 CE = dyn_cast<MCConstantExpr>(WidthExpr);
4554 Error(E, "'width' operand must be an immediate");
4555 return MatchOperand_ParseFail;
4558 int64_t Width = CE->getValue();
4559 // The LSB must be in the range [1,32-lsb]
4560 if (Width < 1 || Width > 32 - LSB) {
4561 Error(E, "'width' operand must be in the range [1,32-lsb]");
4562 return MatchOperand_ParseFail;
4565 Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
4567 return MatchOperand_Success;
4570 ARMAsmParser::OperandMatchResultTy
4571 ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
4572 // Check for a post-index addressing register operand. Specifically:
4573 // postidx_reg := '+' register {, shift}
4574 // | '-' register {, shift}
4575 // | register {, shift}
4577 // This method must return MatchOperand_NoMatch without consuming any tokens
4578 // in the case where there is no match, as other alternatives take other
4580 MCAsmParser &Parser = getParser();
4581 AsmToken Tok = Parser.getTok();
4582 SMLoc S = Tok.getLoc();
4583 bool haveEaten = false;
4585 if (Tok.is(AsmToken::Plus)) {
4586 Parser.Lex(); // Eat the '+' token.
4588 } else if (Tok.is(AsmToken::Minus)) {
4589 Parser.Lex(); // Eat the '-' token.
4594 SMLoc E = Parser.getTok().getEndLoc();
4595 int Reg = tryParseRegister();
4598 return MatchOperand_NoMatch;
4599 Error(Parser.getTok().getLoc(), "register expected");
4600 return MatchOperand_ParseFail;
4603 ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
4604 unsigned ShiftImm = 0;
4605 if (Parser.getTok().is(AsmToken::Comma)) {
4606 Parser.Lex(); // Eat the ','.
4607 if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
4608 return MatchOperand_ParseFail;
4610 // FIXME: Only approximates end...may include intervening whitespace.
4611 E = Parser.getTok().getLoc();
4614 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
4617 return MatchOperand_Success;
4620 ARMAsmParser::OperandMatchResultTy
4621 ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
4622 // Check for a post-index addressing register operand. Specifically:
4623 // am3offset := '+' register
4630 // This method must return MatchOperand_NoMatch without consuming any tokens
4631 // in the case where there is no match, as other alternatives take other
4633 MCAsmParser &Parser = getParser();
4634 AsmToken Tok = Parser.getTok();
4635 SMLoc S = Tok.getLoc();
4637 // Do immediates first, as we always parse those if we have a '#'.
4638 if (Parser.getTok().is(AsmToken::Hash) ||
4639 Parser.getTok().is(AsmToken::Dollar)) {
4640 Parser.Lex(); // Eat '#' or '$'.
4641 // Explicitly look for a '-', as we need to encode negative zero
4643 bool isNegative = Parser.getTok().is(AsmToken::Minus);
4644 const MCExpr *Offset;
4646 if (getParser().parseExpression(Offset, E))
4647 return MatchOperand_ParseFail;
4648 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4650 Error(S, "constant expression expected");
4651 return MatchOperand_ParseFail;
4653 // Negative zero is encoded as the flag value INT32_MIN.
4654 int32_t Val = CE->getValue();
4655 if (isNegative && Val == 0)
4659 ARMOperand::CreateImm(MCConstantExpr::Create(Val, getContext()), S, E));
4661 return MatchOperand_Success;
4665 bool haveEaten = false;
4667 if (Tok.is(AsmToken::Plus)) {
4668 Parser.Lex(); // Eat the '+' token.
4670 } else if (Tok.is(AsmToken::Minus)) {
4671 Parser.Lex(); // Eat the '-' token.
4676 Tok = Parser.getTok();
4677 int Reg = tryParseRegister();
4680 return MatchOperand_NoMatch;
4681 Error(Tok.getLoc(), "register expected");
4682 return MatchOperand_ParseFail;
4685 Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
4686 0, S, Tok.getEndLoc()));
4688 return MatchOperand_Success;
4691 /// Convert parsed operands to MCInst. Needed here because this instruction
4692 /// only has two register operands, but multiplication is commutative so
4693 /// assemblers should accept both "mul rD, rN, rD" and "mul rD, rD, rN".
4694 void ARMAsmParser::cvtThumbMultiply(MCInst &Inst,
4695 const OperandVector &Operands) {
4696 ((ARMOperand &)*Operands[3]).addRegOperands(Inst, 1);
4697 ((ARMOperand &)*Operands[1]).addCCOutOperands(Inst, 1);
4698 // If we have a three-operand form, make sure to set Rn to be the operand
4699 // that isn't the same as Rd.
4701 if (Operands.size() == 6 &&
4702 ((ARMOperand &)*Operands[4]).getReg() ==
4703 ((ARMOperand &)*Operands[3]).getReg())
4705 ((ARMOperand &)*Operands[RegOp]).addRegOperands(Inst, 1);
4706 Inst.addOperand(Inst.getOperand(0));
4707 ((ARMOperand &)*Operands[2]).addCondCodeOperands(Inst, 2);
4710 void ARMAsmParser::cvtThumbBranches(MCInst &Inst,
4711 const OperandVector &Operands) {
4712 int CondOp = -1, ImmOp = -1;
4713 switch(Inst.getOpcode()) {
4715 case ARM::tBcc: CondOp = 1; ImmOp = 2; break;
4718 case ARM::t2Bcc: CondOp = 1; ImmOp = 3; break;
4720 default: llvm_unreachable("Unexpected instruction in cvtThumbBranches");
4722 // first decide whether or not the branch should be conditional
4723 // by looking at it's location relative to an IT block
4725 // inside an IT block we cannot have any conditional branches. any
4726 // such instructions needs to be converted to unconditional form
4727 switch(Inst.getOpcode()) {
4728 case ARM::tBcc: Inst.setOpcode(ARM::tB); break;
4729 case ARM::t2Bcc: Inst.setOpcode(ARM::t2B); break;
4732 // outside IT blocks we can only have unconditional branches with AL
4733 // condition code or conditional branches with non-AL condition code
4734 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode();
4735 switch(Inst.getOpcode()) {
4738 Inst.setOpcode(Cond == ARMCC::AL ? ARM::tB : ARM::tBcc);
4742 Inst.setOpcode(Cond == ARMCC::AL ? ARM::t2B : ARM::t2Bcc);
4747 // now decide on encoding size based on branch target range
4748 switch(Inst.getOpcode()) {
4749 // classify tB as either t2B or t1B based on range of immediate operand
4751 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4752 if (!op.isSignedOffset<11, 1>() && isThumbTwo())
4753 Inst.setOpcode(ARM::t2B);
4756 // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
4758 ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
4759 if (!op.isSignedOffset<8, 1>() && isThumbTwo())
4760 Inst.setOpcode(ARM::t2Bcc);
4764 ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
4765 ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
4768 /// Parse an ARM memory expression, return false if successful else return true
4769 /// or an error. The first token must be a '[' when called.
4770 bool ARMAsmParser::parseMemory(OperandVector &Operands) {
4771 MCAsmParser &Parser = getParser();
4773 assert(Parser.getTok().is(AsmToken::LBrac) &&
4774 "Token is not a Left Bracket");
4775 S = Parser.getTok().getLoc();
4776 Parser.Lex(); // Eat left bracket token.
4778 const AsmToken &BaseRegTok = Parser.getTok();
4779 int BaseRegNum = tryParseRegister();
4780 if (BaseRegNum == -1)
4781 return Error(BaseRegTok.getLoc(), "register expected");
4783 // The next token must either be a comma, a colon or a closing bracket.
4784 const AsmToken &Tok = Parser.getTok();
4785 if (!Tok.is(AsmToken::Colon) && !Tok.is(AsmToken::Comma) &&
4786 !Tok.is(AsmToken::RBrac))
4787 return Error(Tok.getLoc(), "malformed memory operand");
4789 if (Tok.is(AsmToken::RBrac)) {
4790 E = Tok.getEndLoc();
4791 Parser.Lex(); // Eat right bracket token.
4793 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4794 ARM_AM::no_shift, 0, 0, false,
4797 // If there's a pre-indexing writeback marker, '!', just add it as a token
4798 // operand. It's rather odd, but syntactically valid.
4799 if (Parser.getTok().is(AsmToken::Exclaim)) {
4800 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4801 Parser.Lex(); // Eat the '!'.
4807 assert((Tok.is(AsmToken::Colon) || Tok.is(AsmToken::Comma)) &&
4808 "Lost colon or comma in memory operand?!");
4809 if (Tok.is(AsmToken::Comma)) {
4810 Parser.Lex(); // Eat the comma.
4813 // If we have a ':', it's an alignment specifier.
4814 if (Parser.getTok().is(AsmToken::Colon)) {
4815 Parser.Lex(); // Eat the ':'.
4816 E = Parser.getTok().getLoc();
4817 SMLoc AlignmentLoc = Tok.getLoc();
4820 if (getParser().parseExpression(Expr))
4823 // The expression has to be a constant. Memory references with relocations
4824 // don't come through here, as they use the <label> forms of the relevant
4826 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
4828 return Error (E, "constant expression expected");
4831 switch (CE->getValue()) {
4834 "alignment specifier must be 16, 32, 64, 128, or 256 bits");
4835 case 16: Align = 2; break;
4836 case 32: Align = 4; break;
4837 case 64: Align = 8; break;
4838 case 128: Align = 16; break;
4839 case 256: Align = 32; break;
4842 // Now we should have the closing ']'
4843 if (Parser.getTok().isNot(AsmToken::RBrac))
4844 return Error(Parser.getTok().getLoc(), "']' expected");
4845 E = Parser.getTok().getEndLoc();
4846 Parser.Lex(); // Eat right bracket token.
4848 // Don't worry about range checking the value here. That's handled by
4849 // the is*() predicates.
4850 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, 0,
4851 ARM_AM::no_shift, 0, Align,
4852 false, S, E, AlignmentLoc));
4854 // If there's a pre-indexing writeback marker, '!', just add it as a token
4856 if (Parser.getTok().is(AsmToken::Exclaim)) {
4857 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4858 Parser.Lex(); // Eat the '!'.
4864 // If we have a '#', it's an immediate offset, else assume it's a register
4865 // offset. Be friendly and also accept a plain integer (without a leading
4866 // hash) for gas compatibility.
4867 if (Parser.getTok().is(AsmToken::Hash) ||
4868 Parser.getTok().is(AsmToken::Dollar) ||
4869 Parser.getTok().is(AsmToken::Integer)) {
4870 if (Parser.getTok().isNot(AsmToken::Integer))
4871 Parser.Lex(); // Eat '#' or '$'.
4872 E = Parser.getTok().getLoc();
4874 bool isNegative = getParser().getTok().is(AsmToken::Minus);
4875 const MCExpr *Offset;
4876 if (getParser().parseExpression(Offset))
4879 // The expression has to be a constant. Memory references with relocations
4880 // don't come through here, as they use the <label> forms of the relevant
4882 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
4884 return Error (E, "constant expression expected");
4886 // If the constant was #-0, represent it as INT32_MIN.
4887 int32_t Val = CE->getValue();
4888 if (isNegative && Val == 0)
4889 CE = MCConstantExpr::Create(INT32_MIN, getContext());
4891 // Now we should have the closing ']'
4892 if (Parser.getTok().isNot(AsmToken::RBrac))
4893 return Error(Parser.getTok().getLoc(), "']' expected");
4894 E = Parser.getTok().getEndLoc();
4895 Parser.Lex(); // Eat right bracket token.
4897 // Don't worry about range checking the value here. That's handled by
4898 // the is*() predicates.
4899 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, CE, 0,
4900 ARM_AM::no_shift, 0, 0,
4903 // If there's a pre-indexing writeback marker, '!', just add it as a token
4905 if (Parser.getTok().is(AsmToken::Exclaim)) {
4906 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4907 Parser.Lex(); // Eat the '!'.
4913 // The register offset is optionally preceded by a '+' or '-'
4914 bool isNegative = false;
4915 if (Parser.getTok().is(AsmToken::Minus)) {
4917 Parser.Lex(); // Eat the '-'.
4918 } else if (Parser.getTok().is(AsmToken::Plus)) {
4920 Parser.Lex(); // Eat the '+'.
4923 E = Parser.getTok().getLoc();
4924 int OffsetRegNum = tryParseRegister();
4925 if (OffsetRegNum == -1)
4926 return Error(E, "register expected");
4928 // If there's a shift operator, handle it.
4929 ARM_AM::ShiftOpc ShiftType = ARM_AM::no_shift;
4930 unsigned ShiftImm = 0;
4931 if (Parser.getTok().is(AsmToken::Comma)) {
4932 Parser.Lex(); // Eat the ','.
4933 if (parseMemRegOffsetShift(ShiftType, ShiftImm))
4937 // Now we should have the closing ']'
4938 if (Parser.getTok().isNot(AsmToken::RBrac))
4939 return Error(Parser.getTok().getLoc(), "']' expected");
4940 E = Parser.getTok().getEndLoc();
4941 Parser.Lex(); // Eat right bracket token.
4943 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, nullptr, OffsetRegNum,
4944 ShiftType, ShiftImm, 0, isNegative,
4947 // If there's a pre-indexing writeback marker, '!', just add it as a token
4949 if (Parser.getTok().is(AsmToken::Exclaim)) {
4950 Operands.push_back(ARMOperand::CreateToken("!",Parser.getTok().getLoc()));
4951 Parser.Lex(); // Eat the '!'.
4957 /// parseMemRegOffsetShift - one of these two:
4958 /// ( lsl | lsr | asr | ror ) , # shift_amount
4960 /// return true if it parses a shift otherwise it returns false.
4961 bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
4963 MCAsmParser &Parser = getParser();
4964 SMLoc Loc = Parser.getTok().getLoc();
4965 const AsmToken &Tok = Parser.getTok();
4966 if (Tok.isNot(AsmToken::Identifier))
4968 StringRef ShiftName = Tok.getString();
4969 if (ShiftName == "lsl" || ShiftName == "LSL" ||
4970 ShiftName == "asl" || ShiftName == "ASL")
4972 else if (ShiftName == "lsr" || ShiftName == "LSR")
4974 else if (ShiftName == "asr" || ShiftName == "ASR")
4976 else if (ShiftName == "ror" || ShiftName == "ROR")
4978 else if (ShiftName == "rrx" || ShiftName == "RRX")
4981 return Error(Loc, "illegal shift operator");
4982 Parser.Lex(); // Eat shift type token.
4984 // rrx stands alone.
4986 if (St != ARM_AM::rrx) {
4987 Loc = Parser.getTok().getLoc();
4988 // A '#' and a shift amount.
4989 const AsmToken &HashTok = Parser.getTok();
4990 if (HashTok.isNot(AsmToken::Hash) &&
4991 HashTok.isNot(AsmToken::Dollar))
4992 return Error(HashTok.getLoc(), "'#' expected");
4993 Parser.Lex(); // Eat hash token.
4996 if (getParser().parseExpression(Expr))
4998 // Range check the immediate.
4999 // lsl, ror: 0 <= imm <= 31
5000 // lsr, asr: 0 <= imm <= 32
5001 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
5003 return Error(Loc, "shift amount must be an immediate");
5004 int64_t Imm = CE->getValue();
5006 ((St == ARM_AM::lsl || St == ARM_AM::ror) && Imm > 31) ||
5007 ((St == ARM_AM::lsr || St == ARM_AM::asr) && Imm > 32))
5008 return Error(Loc, "immediate shift value out of range");
5009 // If <ShiftTy> #0, turn it into a no_shift.
5012 // For consistency, treat lsr #32 and asr #32 as having immediate value 0.
5021 /// parseFPImm - A floating point immediate expression operand.
5022 ARMAsmParser::OperandMatchResultTy
5023 ARMAsmParser::parseFPImm(OperandVector &Operands) {
5024 MCAsmParser &Parser = getParser();
5025 // Anything that can accept a floating point constant as an operand
5026 // needs to go through here, as the regular parseExpression is
5029 // This routine still creates a generic Immediate operand, containing
5030 // a bitcast of the 64-bit floating point value. The various operands
5031 // that accept floats can check whether the value is valid for them
5032 // via the standard is*() predicates.
5034 SMLoc S = Parser.getTok().getLoc();
5036 if (Parser.getTok().isNot(AsmToken::Hash) &&
5037 Parser.getTok().isNot(AsmToken::Dollar))
5038 return MatchOperand_NoMatch;
5040 // Disambiguate the VMOV forms that can accept an FP immediate.
5041 // vmov.f32 <sreg>, #imm
5042 // vmov.f64 <dreg>, #imm
5043 // vmov.f32 <dreg>, #imm @ vector f32x2
5044 // vmov.f32 <qreg>, #imm @ vector f32x4
5046 // There are also the NEON VMOV instructions which expect an
5047 // integer constant. Make sure we don't try to parse an FPImm
5049 // vmov.i{8|16|32|64} <dreg|qreg>, #imm
5050 ARMOperand &TyOp = static_cast<ARMOperand &>(*Operands[2]);
5051 bool isVmovf = TyOp.isToken() &&
5052 (TyOp.getToken() == ".f32" || TyOp.getToken() == ".f64");
5053 ARMOperand &Mnemonic = static_cast<ARMOperand &>(*Operands[0]);
5054 bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
5055 Mnemonic.getToken() == "fconsts");
5056 if (!(isVmovf || isFconst))
5057 return MatchOperand_NoMatch;
5059 Parser.Lex(); // Eat '#' or '$'.
5061 // Handle negation, as that still comes through as a separate token.
5062 bool isNegative = false;
5063 if (Parser.getTok().is(AsmToken::Minus)) {
5067 const AsmToken &Tok = Parser.getTok();
5068 SMLoc Loc = Tok.getLoc();
5069 if (Tok.is(AsmToken::Real) && isVmovf) {
5070 APFloat RealVal(APFloat::IEEEsingle, Tok.getString());
5071 uint64_t IntVal = RealVal.bitcastToAPInt().getZExtValue();
5072 // If we had a '-' in front, toggle the sign bit.
5073 IntVal ^= (uint64_t)isNegative << 31;
5074 Parser.Lex(); // Eat the token.
5075 Operands.push_back(ARMOperand::CreateImm(
5076 MCConstantExpr::Create(IntVal, getContext()),
5077 S, Parser.getTok().getLoc()));
5078 return MatchOperand_Success;
5080 // Also handle plain integers. Instructions which allow floating point
5081 // immediates also allow a raw encoded 8-bit value.
5082 if (Tok.is(AsmToken::Integer) && isFconst) {
5083 int64_t Val = Tok.getIntVal();
5084 Parser.Lex(); // Eat the token.
5085 if (Val > 255 || Val < 0) {
5086 Error(Loc, "encoded floating point value out of range");
5087 return MatchOperand_ParseFail;
5089 float RealVal = ARM_AM::getFPImmFloat(Val);
5090 Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
5092 Operands.push_back(ARMOperand::CreateImm(
5093 MCConstantExpr::Create(Val, getContext()), S,
5094 Parser.getTok().getLoc()));
5095 return MatchOperand_Success;
5098 Error(Loc, "invalid floating point immediate");
5099 return MatchOperand_ParseFail;
5102 /// Parse a arm instruction operand. For now this parses the operand regardless
5103 /// of the mnemonic.
5104 bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
5105 MCAsmParser &Parser = getParser();
5108 // Check if the current operand has a custom associated parser, if so, try to
5109 // custom parse the operand, or fallback to the general approach.
5110 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
5111 if (ResTy == MatchOperand_Success)
5113 // If there wasn't a custom match, try the generic matcher below. Otherwise,
5114 // there was a match, but an error occurred, in which case, just return that
5115 // the operand parsing failed.
5116 if (ResTy == MatchOperand_ParseFail)
5119 switch (getLexer().getKind()) {
5121 Error(Parser.getTok().getLoc(), "unexpected token in operand");
5123 case AsmToken::Identifier: {
5124 // If we've seen a branch mnemonic, the next operand must be a label. This
5125 // is true even if the label is a register name. So "br r1" means branch to
5127 bool ExpectLabel = Mnemonic == "b" || Mnemonic == "bl";
5129 if (!tryParseRegisterWithWriteBack(Operands))
5131 int Res = tryParseShiftRegister(Operands);
5132 if (Res == 0) // success
5134 else if (Res == -1) // irrecoverable error
5136 // If this is VMRS, check for the apsr_nzcv operand.
5137 if (Mnemonic == "vmrs" &&
5138 Parser.getTok().getString().equals_lower("apsr_nzcv")) {
5139 S = Parser.getTok().getLoc();
5141 Operands.push_back(ARMOperand::CreateToken("APSR_nzcv", S));
5146 // Fall though for the Identifier case that is not a register or a
5149 case AsmToken::LParen: // parenthesized expressions like (_strcmp-4)
5150 case AsmToken::Integer: // things like 1f and 2b as a branch targets
5151 case AsmToken::String: // quoted label names.
5152 case AsmToken::Dot: { // . as a branch target
5153 // This was not a register so parse other operands that start with an
5154 // identifier (like labels) as expressions and create them as immediates.
5155 const MCExpr *IdVal;
5156 S = Parser.getTok().getLoc();
5157 if (getParser().parseExpression(IdVal))
5159 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5160 Operands.push_back(ARMOperand::CreateImm(IdVal, S, E));
5163 case AsmToken::LBrac:
5164 return parseMemory(Operands);
5165 case AsmToken::LCurly:
5166 return parseRegisterList(Operands);
5167 case AsmToken::Dollar:
5168 case AsmToken::Hash: {
5169 // #42 -> immediate.
5170 S = Parser.getTok().getLoc();
5173 if (Parser.getTok().isNot(AsmToken::Colon)) {
5174 bool isNegative = Parser.getTok().is(AsmToken::Minus);
5175 const MCExpr *ImmVal;
5176 if (getParser().parseExpression(ImmVal))
5178 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ImmVal);
5180 int32_t Val = CE->getValue();
5181 if (isNegative && Val == 0)
5182 ImmVal = MCConstantExpr::Create(INT32_MIN, getContext());
5184 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5185 Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E));
5187 // There can be a trailing '!' on operands that we want as a separate
5188 // '!' Token operand. Handle that here. For example, the compatibility
5189 // alias for 'srsdb sp!, #imm' is 'srsdb #imm!'.
5190 if (Parser.getTok().is(AsmToken::Exclaim)) {
5191 Operands.push_back(ARMOperand::CreateToken(Parser.getTok().getString(),
5192 Parser.getTok().getLoc()));
5193 Parser.Lex(); // Eat exclaim token
5197 // w/ a ':' after the '#', it's just like a plain ':'.
5200 case AsmToken::Colon: {
5201 // ":lower16:" and ":upper16:" expression prefixes
5202 // FIXME: Check it's an expression prefix,
5203 // e.g. (FOO - :lower16:BAR) isn't legal.
5204 ARMMCExpr::VariantKind RefKind;
5205 if (parsePrefix(RefKind))
5208 const MCExpr *SubExprVal;
5209 if (getParser().parseExpression(SubExprVal))
5212 const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal,
5214 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5215 Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E));
5218 case AsmToken::Equal: {
5219 if (Mnemonic != "ldr") // only parse for ldr pseudo (e.g. ldr r0, =val)
5220 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
5222 Parser.Lex(); // Eat '='
5223 const MCExpr *SubExprVal;
5224 if (getParser().parseExpression(SubExprVal))
5226 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
5228 const MCExpr *CPLoc = getTargetStreamer().addConstantPoolEntry(SubExprVal);
5229 Operands.push_back(ARMOperand::CreateImm(CPLoc, S, E));
5235 // parsePrefix - Parse ARM 16-bit relocations expression prefix, i.e.
5236 // :lower16: and :upper16:.
5237 bool ARMAsmParser::parsePrefix(ARMMCExpr::VariantKind &RefKind) {
5238 MCAsmParser &Parser = getParser();
5239 RefKind = ARMMCExpr::VK_ARM_None;
5241 // consume an optional '#' (GNU compatibility)
5242 if (getLexer().is(AsmToken::Hash))
5245 // :lower16: and :upper16: modifiers
5246 assert(getLexer().is(AsmToken::Colon) && "expected a :");
5247 Parser.Lex(); // Eat ':'
5249 if (getLexer().isNot(AsmToken::Identifier)) {
5250 Error(Parser.getTok().getLoc(), "expected prefix identifier in operand");
5255 COFF = (1 << MCObjectFileInfo::IsCOFF),
5256 ELF = (1 << MCObjectFileInfo::IsELF),
5257 MACHO = (1 << MCObjectFileInfo::IsMachO)
5259 static const struct PrefixEntry {
5260 const char *Spelling;
5261 ARMMCExpr::VariantKind VariantKind;
5262 uint8_t SupportedFormats;
5263 } PrefixEntries[] = {
5264 { "lower16", ARMMCExpr::VK_ARM_LO16, COFF | ELF | MACHO },
5265 { "upper16", ARMMCExpr::VK_ARM_HI16, COFF | ELF | MACHO },
5268 StringRef IDVal = Parser.getTok().getIdentifier();
5270 const auto &Prefix =
5271 std::find_if(std::begin(PrefixEntries), std::end(PrefixEntries),
5272 [&IDVal](const PrefixEntry &PE) {
5273 return PE.Spelling == IDVal;
5275 if (Prefix == std::end(PrefixEntries)) {
5276 Error(Parser.getTok().getLoc(), "unexpected prefix in operand");
5280 uint8_t CurrentFormat;
5281 switch (getContext().getObjectFileInfo()->getObjectFileType()) {
5282 case MCObjectFileInfo::IsMachO:
5283 CurrentFormat = MACHO;
5285 case MCObjectFileInfo::IsELF:
5286 CurrentFormat = ELF;
5288 case MCObjectFileInfo::IsCOFF:
5289 CurrentFormat = COFF;
5293 if (~Prefix->SupportedFormats & CurrentFormat) {
5294 Error(Parser.getTok().getLoc(),
5295 "cannot represent relocation in the current file format");
5299 RefKind = Prefix->VariantKind;
5302 if (getLexer().isNot(AsmToken::Colon)) {
5303 Error(Parser.getTok().getLoc(), "unexpected token after prefix");
5306 Parser.Lex(); // Eat the last ':'
5311 /// \brief Given a mnemonic, split out possible predication code and carry
5312 /// setting letters to form a canonical mnemonic and flags.
5314 // FIXME: Would be nice to autogen this.
5315 // FIXME: This is a bit of a maze of special cases.
5316 StringRef ARMAsmParser::splitMnemonic(StringRef Mnemonic,
5317 unsigned &PredicationCode,
5319 unsigned &ProcessorIMod,
5320 StringRef &ITMask) {
5321 PredicationCode = ARMCC::AL;
5322 CarrySetting = false;
5325 // Ignore some mnemonics we know aren't predicated forms.
5327 // FIXME: Would be nice to autogen this.
5328 if ((Mnemonic == "movs" && isThumb()) ||
5329 Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "svc" ||
5330 Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" ||
5331 Mnemonic == "vmls" || Mnemonic == "vnmls" || Mnemonic == "vacge" ||
5332 Mnemonic == "vcge" || Mnemonic == "vclt" || Mnemonic == "vacgt" ||
5333 Mnemonic == "vaclt" || Mnemonic == "vacle" || Mnemonic == "hlt" ||
5334 Mnemonic == "vcgt" || Mnemonic == "vcle" || Mnemonic == "smlal" ||
5335 Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" ||
5336 Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal" ||
5337 Mnemonic == "fmuls" || Mnemonic == "vmaxnm" || Mnemonic == "vminnm" ||
5338 Mnemonic == "vcvta" || Mnemonic == "vcvtn" || Mnemonic == "vcvtp" ||
5339 Mnemonic == "vcvtm" || Mnemonic == "vrinta" || Mnemonic == "vrintn" ||
5340 Mnemonic == "vrintp" || Mnemonic == "vrintm" || Mnemonic == "hvc" ||
5341 Mnemonic.startswith("vsel"))
5344 // First, split out any predication code. Ignore mnemonics we know aren't
5345 // predicated but do have a carry-set and so weren't caught above.
5346 if (Mnemonic != "adcs" && Mnemonic != "bics" && Mnemonic != "movs" &&
5347 Mnemonic != "muls" && Mnemonic != "smlals" && Mnemonic != "smulls" &&
5348 Mnemonic != "umlals" && Mnemonic != "umulls" && Mnemonic != "lsls" &&
5349 Mnemonic != "sbcs" && Mnemonic != "rscs") {
5350 unsigned CC = StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2))
5351 .Case("eq", ARMCC::EQ)
5352 .Case("ne", ARMCC::NE)
5353 .Case("hs", ARMCC::HS)
5354 .Case("cs", ARMCC::HS)
5355 .Case("lo", ARMCC::LO)
5356 .Case("cc", ARMCC::LO)
5357 .Case("mi", ARMCC::MI)
5358 .Case("pl", ARMCC::PL)
5359 .Case("vs", ARMCC::VS)
5360 .Case("vc", ARMCC::VC)
5361 .Case("hi", ARMCC::HI)
5362 .Case("ls", ARMCC::LS)
5363 .Case("ge", ARMCC::GE)
5364 .Case("lt", ARMCC::LT)
5365 .Case("gt", ARMCC::GT)
5366 .Case("le", ARMCC::LE)
5367 .Case("al", ARMCC::AL)
5370 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2);
5371 PredicationCode = CC;
5375 // Next, determine if we have a carry setting bit. We explicitly ignore all
5376 // the instructions we know end in 's'.
5377 if (Mnemonic.endswith("s") &&
5378 !(Mnemonic == "cps" || Mnemonic == "mls" ||
5379 Mnemonic == "mrs" || Mnemonic == "smmls" || Mnemonic == "vabs" ||
5380 Mnemonic == "vcls" || Mnemonic == "vmls" || Mnemonic == "vmrs" ||
5381 Mnemonic == "vnmls" || Mnemonic == "vqabs" || Mnemonic == "vrecps" ||
5382 Mnemonic == "vrsqrts" || Mnemonic == "srs" || Mnemonic == "flds" ||
5383 Mnemonic == "fmrs" || Mnemonic == "fsqrts" || Mnemonic == "fsubs" ||
5384 Mnemonic == "fsts" || Mnemonic == "fcpys" || Mnemonic == "fdivs" ||
5385 Mnemonic == "fmuls" || Mnemonic == "fcmps" || Mnemonic == "fcmpzs" ||
5386 Mnemonic == "vfms" || Mnemonic == "vfnms" || Mnemonic == "fconsts" ||
5387 (Mnemonic == "movs" && isThumb()))) {
5388 Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1);
5389 CarrySetting = true;
5392 // The "cps" instruction can have a interrupt mode operand which is glued into
5393 // the mnemonic. Check if this is the case, split it and parse the imod op
5394 if (Mnemonic.startswith("cps")) {
5395 // Split out any imod code.
5397 StringSwitch<unsigned>(Mnemonic.substr(Mnemonic.size()-2, 2))
5398 .Case("ie", ARM_PROC::IE)
5399 .Case("id", ARM_PROC::ID)
5402 Mnemonic = Mnemonic.slice(0, Mnemonic.size()-2);
5403 ProcessorIMod = IMod;
5407 // The "it" instruction has the condition mask on the end of the mnemonic.
5408 if (Mnemonic.startswith("it")) {
5409 ITMask = Mnemonic.slice(2, Mnemonic.size());
5410 Mnemonic = Mnemonic.slice(0, 2);
5416 /// \brief Given a canonical mnemonic, determine if the instruction ever allows
5417 /// inclusion of carry set or predication code operands.
5419 // FIXME: It would be nice to autogen this.
5420 void ARMAsmParser::getMnemonicAcceptInfo(StringRef Mnemonic, StringRef FullInst,
5421 bool &CanAcceptCarrySet,
5422 bool &CanAcceptPredicationCode) {
5424 Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5425 Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" ||
5426 Mnemonic == "add" || Mnemonic == "adc" || Mnemonic == "mul" ||
5427 Mnemonic == "bic" || Mnemonic == "asr" || Mnemonic == "orr" ||
5428 Mnemonic == "mvn" || Mnemonic == "rsb" || Mnemonic == "rsc" ||
5429 Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "eor" ||
5430 Mnemonic == "neg" || Mnemonic == "vfm" || Mnemonic == "vfnm" ||
5432 (Mnemonic == "smull" || Mnemonic == "mov" || Mnemonic == "mla" ||
5433 Mnemonic == "smlal" || Mnemonic == "umlal" || Mnemonic == "umull"));
5435 if (Mnemonic == "bkpt" || Mnemonic == "cbnz" || Mnemonic == "setend" ||
5436 Mnemonic == "cps" || Mnemonic == "it" || Mnemonic == "cbz" ||
5437 Mnemonic == "trap" || Mnemonic == "hlt" || Mnemonic == "udf" ||
5438 Mnemonic.startswith("crc32") || Mnemonic.startswith("cps") ||
5439 Mnemonic.startswith("vsel") || Mnemonic == "vmaxnm" ||
5440 Mnemonic == "vminnm" || Mnemonic == "vcvta" || Mnemonic == "vcvtn" ||
5441 Mnemonic == "vcvtp" || Mnemonic == "vcvtm" || Mnemonic == "vrinta" ||
5442 Mnemonic == "vrintn" || Mnemonic == "vrintp" || Mnemonic == "vrintm" ||
5443 Mnemonic.startswith("aes") || Mnemonic == "hvc" || Mnemonic == "setpan" ||
5444 Mnemonic.startswith("sha1") || Mnemonic.startswith("sha256") ||
5445 (FullInst.startswith("vmull") && FullInst.endswith(".p64"))) {
5446 // These mnemonics are never predicable
5447 CanAcceptPredicationCode = false;
5448 } else if (!isThumb()) {
5449 // Some instructions are only predicable in Thumb mode
5450 CanAcceptPredicationCode =
5451 Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
5452 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5453 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5454 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5455 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" &&
5456 Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") &&
5457 !Mnemonic.startswith("srs");
5458 } else if (isThumbOne()) {
5460 CanAcceptPredicationCode = Mnemonic != "movs";
5462 CanAcceptPredicationCode = Mnemonic != "nop" && Mnemonic != "movs";
5464 CanAcceptPredicationCode = true;
5467 bool ARMAsmParser::shouldOmitCCOutOperand(StringRef Mnemonic,
5468 OperandVector &Operands) {
5469 // FIXME: This is all horribly hacky. We really need a better way to deal
5470 // with optional operands like this in the matcher table.
5472 // The 'mov' mnemonic is special. One variant has a cc_out operand, while
5473 // another does not. Specifically, the MOVW instruction does not. So we
5474 // special case it here and remove the defaulted (non-setting) cc_out
5475 // operand if that's the instruction we're trying to match.
5477 // We do this as post-processing of the explicit operands rather than just
5478 // conditionally adding the cc_out in the first place because we need
5479 // to check the type of the parsed immediate operand.
5480 if (Mnemonic == "mov" && Operands.size() > 4 && !isThumb() &&
5481 !static_cast<ARMOperand &>(*Operands[4]).isModImm() &&
5482 static_cast<ARMOperand &>(*Operands[4]).isImm0_65535Expr() &&
5483 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5486 // Register-register 'add' for thumb does not have a cc_out operand
5487 // when there are only two register operands.
5488 if (isThumb() && Mnemonic == "add" && Operands.size() == 5 &&
5489 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5490 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5491 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0)
5493 // Register-register 'add' for thumb does not have a cc_out operand
5494 // when it's an ADD Rdm, SP, {Rdm|#imm0_255} instruction. We do
5495 // have to check the immediate range here since Thumb2 has a variant
5496 // that can handle a different range and has a cc_out operand.
5497 if (((isThumb() && Mnemonic == "add") ||
5498 (isThumbTwo() && Mnemonic == "sub")) &&
5499 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5500 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5501 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::SP &&
5502 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5503 ((Mnemonic == "add" && static_cast<ARMOperand &>(*Operands[5]).isReg()) ||
5504 static_cast<ARMOperand &>(*Operands[5]).isImm0_1020s4()))
5506 // For Thumb2, add/sub immediate does not have a cc_out operand for the
5507 // imm0_4095 variant. That's the least-preferred variant when
5508 // selecting via the generic "add" mnemonic, so to know that we
5509 // should remove the cc_out operand, we have to explicitly check that
5510 // it's not one of the other variants. Ugh.
5511 if (isThumbTwo() && (Mnemonic == "add" || Mnemonic == "sub") &&
5512 Operands.size() == 6 && static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5513 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5514 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5515 // Nest conditions rather than one big 'if' statement for readability.
5517 // If both registers are low, we're in an IT block, and the immediate is
5518 // in range, we should use encoding T1 instead, which has a cc_out.
5520 isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) &&
5521 isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) &&
5522 static_cast<ARMOperand &>(*Operands[5]).isImm0_7())
5524 // Check against T3. If the second register is the PC, this is an
5525 // alternate form of ADR, which uses encoding T4, so check for that too.
5526 if (static_cast<ARMOperand &>(*Operands[4]).getReg() != ARM::PC &&
5527 static_cast<ARMOperand &>(*Operands[5]).isT2SOImm())
5530 // Otherwise, we use encoding T4, which does not have a cc_out
5535 // The thumb2 multiply instruction doesn't have a CCOut register, so
5536 // if we have a "mul" mnemonic in Thumb mode, check if we'll be able to
5537 // use the 16-bit encoding or not.
5538 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 6 &&
5539 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5540 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5541 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5542 static_cast<ARMOperand &>(*Operands[5]).isReg() &&
5543 // If the registers aren't low regs, the destination reg isn't the
5544 // same as one of the source regs, or the cc_out operand is zero
5545 // outside of an IT block, we have to use the 32-bit encoding, so
5546 // remove the cc_out operand.
5547 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5548 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5549 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[5]).getReg()) ||
5550 !inITBlock() || (static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5551 static_cast<ARMOperand &>(*Operands[5]).getReg() &&
5552 static_cast<ARMOperand &>(*Operands[3]).getReg() !=
5553 static_cast<ARMOperand &>(*Operands[4]).getReg())))
5556 // Also check the 'mul' syntax variant that doesn't specify an explicit
5557 // destination register.
5558 if (isThumbTwo() && Mnemonic == "mul" && Operands.size() == 5 &&
5559 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5560 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5561 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5562 // If the registers aren't low regs or the cc_out operand is zero
5563 // outside of an IT block, we have to use the 32-bit encoding, so
5564 // remove the cc_out operand.
5565 (!isARMLowRegister(static_cast<ARMOperand &>(*Operands[3]).getReg()) ||
5566 !isARMLowRegister(static_cast<ARMOperand &>(*Operands[4]).getReg()) ||
5572 // Register-register 'add/sub' for thumb does not have a cc_out operand
5573 // when it's an ADD/SUB SP, #imm. Be lenient on count since there's also
5574 // the "add/sub SP, SP, #imm" version. If the follow-up operands aren't
5575 // right, this will result in better diagnostics (which operand is off)
5577 if (isThumb() && (Mnemonic == "add" || Mnemonic == "sub") &&
5578 (Operands.size() == 5 || Operands.size() == 6) &&
5579 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5580 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::SP &&
5581 static_cast<ARMOperand &>(*Operands[1]).getReg() == 0 &&
5582 (static_cast<ARMOperand &>(*Operands[4]).isImm() ||
5583 (Operands.size() == 6 &&
5584 static_cast<ARMOperand &>(*Operands[5]).isImm())))
5590 bool ARMAsmParser::shouldOmitPredicateOperand(StringRef Mnemonic,
5591 OperandVector &Operands) {
5592 // VRINT{Z, R, X} have a predicate operand in VFP, but not in NEON
5593 unsigned RegIdx = 3;
5594 if ((Mnemonic == "vrintz" || Mnemonic == "vrintx" || Mnemonic == "vrintr") &&
5595 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".f32") {
5596 if (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
5597 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".f32")
5600 if (static_cast<ARMOperand &>(*Operands[RegIdx]).isReg() &&
5601 (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(
5602 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg()) ||
5603 ARMMCRegisterClasses[ARM::QPRRegClassID].contains(
5604 static_cast<ARMOperand &>(*Operands[RegIdx]).getReg())))
5610 static bool isDataTypeToken(StringRef Tok) {
5611 return Tok == ".8" || Tok == ".16" || Tok == ".32" || Tok == ".64" ||
5612 Tok == ".i8" || Tok == ".i16" || Tok == ".i32" || Tok == ".i64" ||
5613 Tok == ".u8" || Tok == ".u16" || Tok == ".u32" || Tok == ".u64" ||
5614 Tok == ".s8" || Tok == ".s16" || Tok == ".s32" || Tok == ".s64" ||
5615 Tok == ".p8" || Tok == ".p16" || Tok == ".f32" || Tok == ".f64" ||
5616 Tok == ".f" || Tok == ".d";
5619 // FIXME: This bit should probably be handled via an explicit match class
5620 // in the .td files that matches the suffix instead of having it be
5621 // a literal string token the way it is now.
5622 static bool doesIgnoreDataTypeSuffix(StringRef Mnemonic, StringRef DT) {
5623 return Mnemonic.startswith("vldm") || Mnemonic.startswith("vstm");
5625 static void applyMnemonicAliases(StringRef &Mnemonic, uint64_t Features,
5626 unsigned VariantID);
5628 static bool RequiresVFPRegListValidation(StringRef Inst,
5629 bool &AcceptSinglePrecisionOnly,
5630 bool &AcceptDoublePrecisionOnly) {
5631 if (Inst.size() < 7)
5634 if (Inst.startswith("fldm") || Inst.startswith("fstm")) {
5635 StringRef AddressingMode = Inst.substr(4, 2);
5636 if (AddressingMode == "ia" || AddressingMode == "db" ||
5637 AddressingMode == "ea" || AddressingMode == "fd") {
5638 AcceptSinglePrecisionOnly = Inst[6] == 's';
5639 AcceptDoublePrecisionOnly = Inst[6] == 'd' || Inst[6] == 'x';
5647 /// Parse an arm instruction mnemonic followed by its operands.
5648 bool ARMAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
5649 SMLoc NameLoc, OperandVector &Operands) {
5650 MCAsmParser &Parser = getParser();
5651 // FIXME: Can this be done via tablegen in some fashion?
5652 bool RequireVFPRegisterListCheck;
5653 bool AcceptSinglePrecisionOnly;
5654 bool AcceptDoublePrecisionOnly;
5655 RequireVFPRegisterListCheck =
5656 RequiresVFPRegListValidation(Name, AcceptSinglePrecisionOnly,
5657 AcceptDoublePrecisionOnly);
5659 // Apply mnemonic aliases before doing anything else, as the destination
5660 // mnemonic may include suffices and we want to handle them normally.
5661 // The generic tblgen'erated code does this later, at the start of
5662 // MatchInstructionImpl(), but that's too late for aliases that include
5663 // any sort of suffix.
5664 uint64_t AvailableFeatures = getAvailableFeatures();
5665 unsigned AssemblerDialect = getParser().getAssemblerDialect();
5666 applyMnemonicAliases(Name, AvailableFeatures, AssemblerDialect);
5668 // First check for the ARM-specific .req directive.
5669 if (Parser.getTok().is(AsmToken::Identifier) &&
5670 Parser.getTok().getIdentifier() == ".req") {
5671 parseDirectiveReq(Name, NameLoc);
5672 // We always return 'error' for this, as we're done with this
5673 // statement and don't need to match the 'instruction."
5677 // Create the leading tokens for the mnemonic, split by '.' characters.
5678 size_t Start = 0, Next = Name.find('.');
5679 StringRef Mnemonic = Name.slice(Start, Next);
5681 // Split out the predication code and carry setting flag from the mnemonic.
5682 unsigned PredicationCode;
5683 unsigned ProcessorIMod;
5686 Mnemonic = splitMnemonic(Mnemonic, PredicationCode, CarrySetting,
5687 ProcessorIMod, ITMask);
5689 // In Thumb1, only the branch (B) instruction can be predicated.
5690 if (isThumbOne() && PredicationCode != ARMCC::AL && Mnemonic != "b") {
5691 Parser.eatToEndOfStatement();
5692 return Error(NameLoc, "conditional execution not supported in Thumb1");
5695 Operands.push_back(ARMOperand::CreateToken(Mnemonic, NameLoc));
5697 // Handle the IT instruction ITMask. Convert it to a bitmask. This
5698 // is the mask as it will be for the IT encoding if the conditional
5699 // encoding has a '1' as it's bit0 (i.e. 't' ==> '1'). In the case
5700 // where the conditional bit0 is zero, the instruction post-processing
5701 // will adjust the mask accordingly.
5702 if (Mnemonic == "it") {
5703 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + 2);
5704 if (ITMask.size() > 3) {
5705 Parser.eatToEndOfStatement();
5706 return Error(Loc, "too many conditions on IT instruction");
5709 for (unsigned i = ITMask.size(); i != 0; --i) {
5710 char pos = ITMask[i - 1];
5711 if (pos != 't' && pos != 'e') {
5712 Parser.eatToEndOfStatement();
5713 return Error(Loc, "illegal IT block condition mask '" + ITMask + "'");
5716 if (ITMask[i - 1] == 't')
5719 Operands.push_back(ARMOperand::CreateITMask(Mask, Loc));
5722 // FIXME: This is all a pretty gross hack. We should automatically handle
5723 // optional operands like this via tblgen.
5725 // Next, add the CCOut and ConditionCode operands, if needed.
5727 // For mnemonics which can ever incorporate a carry setting bit or predication
5728 // code, our matching model involves us always generating CCOut and
5729 // ConditionCode operands to match the mnemonic "as written" and then we let
5730 // the matcher deal with finding the right instruction or generating an
5731 // appropriate error.
5732 bool CanAcceptCarrySet, CanAcceptPredicationCode;
5733 getMnemonicAcceptInfo(Mnemonic, Name, CanAcceptCarrySet, CanAcceptPredicationCode);
5735 // If we had a carry-set on an instruction that can't do that, issue an
5737 if (!CanAcceptCarrySet && CarrySetting) {
5738 Parser.eatToEndOfStatement();
5739 return Error(NameLoc, "instruction '" + Mnemonic +
5740 "' can not set flags, but 's' suffix specified");
5742 // If we had a predication code on an instruction that can't do that, issue an
5744 if (!CanAcceptPredicationCode && PredicationCode != ARMCC::AL) {
5745 Parser.eatToEndOfStatement();
5746 return Error(NameLoc, "instruction '" + Mnemonic +
5747 "' is not predicable, but condition code specified");
5750 // Add the carry setting operand, if necessary.
5751 if (CanAcceptCarrySet) {
5752 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size());
5753 Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0,
5757 // Add the predication code operand, if necessary.
5758 if (CanAcceptPredicationCode) {
5759 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Mnemonic.size() +
5761 Operands.push_back(ARMOperand::CreateCondCode(
5762 ARMCC::CondCodes(PredicationCode), Loc));
5765 // Add the processor imod operand, if necessary.
5766 if (ProcessorIMod) {
5767 Operands.push_back(ARMOperand::CreateImm(
5768 MCConstantExpr::Create(ProcessorIMod, getContext()),
5770 } else if (Mnemonic == "cps" && isMClass()) {
5771 return Error(NameLoc, "instruction 'cps' requires effect for M-class");
5774 // Add the remaining tokens in the mnemonic.
5775 while (Next != StringRef::npos) {
5777 Next = Name.find('.', Start + 1);
5778 StringRef ExtraToken = Name.slice(Start, Next);
5780 // Some NEON instructions have an optional datatype suffix that is
5781 // completely ignored. Check for that.
5782 if (isDataTypeToken(ExtraToken) &&
5783 doesIgnoreDataTypeSuffix(Mnemonic, ExtraToken))
5786 // For for ARM mode generate an error if the .n qualifier is used.
5787 if (ExtraToken == ".n" && !isThumb()) {
5788 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5789 Parser.eatToEndOfStatement();
5790 return Error(Loc, "instruction with .n (narrow) qualifier not allowed in "
5794 // The .n qualifier is always discarded as that is what the tables
5795 // and matcher expect. In ARM mode the .w qualifier has no effect,
5796 // so discard it to avoid errors that can be caused by the matcher.
5797 if (ExtraToken != ".n" && (isThumb() || ExtraToken != ".w")) {
5798 SMLoc Loc = SMLoc::getFromPointer(NameLoc.getPointer() + Start);
5799 Operands.push_back(ARMOperand::CreateToken(ExtraToken, Loc));
5803 // Read the remaining operands.
5804 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5805 // Read the first operand.
5806 if (parseOperand(Operands, Mnemonic)) {
5807 Parser.eatToEndOfStatement();
5811 while (getLexer().is(AsmToken::Comma)) {
5812 Parser.Lex(); // Eat the comma.
5814 // Parse and remember the operand.
5815 if (parseOperand(Operands, Mnemonic)) {
5816 Parser.eatToEndOfStatement();
5822 if (getLexer().isNot(AsmToken::EndOfStatement)) {
5823 SMLoc Loc = getLexer().getLoc();
5824 Parser.eatToEndOfStatement();
5825 return Error(Loc, "unexpected token in argument list");
5828 Parser.Lex(); // Consume the EndOfStatement
5830 if (RequireVFPRegisterListCheck) {
5831 ARMOperand &Op = static_cast<ARMOperand &>(*Operands.back());
5832 if (AcceptSinglePrecisionOnly && !Op.isSPRRegList())
5833 return Error(Op.getStartLoc(),
5834 "VFP/Neon single precision register expected");
5835 if (AcceptDoublePrecisionOnly && !Op.isDPRRegList())
5836 return Error(Op.getStartLoc(),
5837 "VFP/Neon double precision register expected");
5840 // Some instructions, mostly Thumb, have forms for the same mnemonic that
5841 // do and don't have a cc_out optional-def operand. With some spot-checks
5842 // of the operand list, we can figure out which variant we're trying to
5843 // parse and adjust accordingly before actually matching. We shouldn't ever
5844 // try to remove a cc_out operand that was explicitly set on the the
5845 // mnemonic, of course (CarrySetting == true). Reason number #317 the
5846 // table driven matcher doesn't fit well with the ARM instruction set.
5847 if (!CarrySetting && shouldOmitCCOutOperand(Mnemonic, Operands))
5848 Operands.erase(Operands.begin() + 1);
5850 // Some instructions have the same mnemonic, but don't always
5851 // have a predicate. Distinguish them here and delete the
5852 // predicate if needed.
5853 if (shouldOmitPredicateOperand(Mnemonic, Operands))
5854 Operands.erase(Operands.begin() + 1);
5856 // ARM mode 'blx' need special handling, as the register operand version
5857 // is predicable, but the label operand version is not. So, we can't rely
5858 // on the Mnemonic based checking to correctly figure out when to put
5859 // a k_CondCode operand in the list. If we're trying to match the label
5860 // version, remove the k_CondCode operand here.
5861 if (!isThumb() && Mnemonic == "blx" && Operands.size() == 3 &&
5862 static_cast<ARMOperand &>(*Operands[2]).isImm())
5863 Operands.erase(Operands.begin() + 1);
5865 // Adjust operands of ldrexd/strexd to MCK_GPRPair.
5866 // ldrexd/strexd require even/odd GPR pair. To enforce this constraint,
5867 // a single GPRPair reg operand is used in the .td file to replace the two
5868 // GPRs. However, when parsing from asm, the two GRPs cannot be automatically
5869 // expressed as a GPRPair, so we have to manually merge them.
5870 // FIXME: We would really like to be able to tablegen'erate this.
5871 if (!isThumb() && Operands.size() > 4 &&
5872 (Mnemonic == "ldrexd" || Mnemonic == "strexd" || Mnemonic == "ldaexd" ||
5873 Mnemonic == "stlexd")) {
5874 bool isLoad = (Mnemonic == "ldrexd" || Mnemonic == "ldaexd");
5875 unsigned Idx = isLoad ? 2 : 3;
5876 ARMOperand &Op1 = static_cast<ARMOperand &>(*Operands[Idx]);
5877 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[Idx + 1]);
5879 const MCRegisterClass& MRC = MRI->getRegClass(ARM::GPRRegClassID);
5880 // Adjust only if Op1 and Op2 are GPRs.
5881 if (Op1.isReg() && Op2.isReg() && MRC.contains(Op1.getReg()) &&
5882 MRC.contains(Op2.getReg())) {
5883 unsigned Reg1 = Op1.getReg();
5884 unsigned Reg2 = Op2.getReg();
5885 unsigned Rt = MRI->getEncodingValue(Reg1);
5886 unsigned Rt2 = MRI->getEncodingValue(Reg2);
5888 // Rt2 must be Rt + 1 and Rt must be even.
5889 if (Rt + 1 != Rt2 || (Rt & 1)) {
5890 Error(Op2.getStartLoc(), isLoad
5891 ? "destination operands must be sequential"
5892 : "source operands must be sequential");
5895 unsigned NewReg = MRI->getMatchingSuperReg(Reg1, ARM::gsub_0,
5896 &(MRI->getRegClass(ARM::GPRPairRegClassID)));
5898 ARMOperand::CreateReg(NewReg, Op1.getStartLoc(), Op2.getEndLoc());
5899 Operands.erase(Operands.begin() + Idx + 1);
5903 // If first 2 operands of a 3 operand instruction are the same
5904 // then transform to 2 operand version of the same instruction
5905 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5906 // FIXME: We would really like to be able to tablegen'erate this.
5907 if (isThumbOne() && Operands.size() == 6 &&
5908 (Mnemonic == "add" || Mnemonic == "sub" || Mnemonic == "and" ||
5909 Mnemonic == "eor" || Mnemonic == "lsl" || Mnemonic == "lsr" ||
5910 Mnemonic == "asr" || Mnemonic == "adc" || Mnemonic == "sbc" ||
5911 Mnemonic == "ror" || Mnemonic == "orr" || Mnemonic == "bic")) {
5912 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5913 ARMOperand &Op4 = static_cast<ARMOperand &>(*Operands[4]);
5914 ARMOperand &Op5 = static_cast<ARMOperand &>(*Operands[5]);
5916 // If both registers are the same then remove one of them from
5917 // the operand list.
5918 if (Op3.isReg() && Op4.isReg() && Op3.getReg() == Op4.getReg()) {
5919 // If 3rd operand (variable Op5) is a register and the instruction is adds/sub
5920 // then do not transform as the backend already handles this instruction
5922 if (!Op5.isReg() || !((Mnemonic == "add" && CarrySetting) || Mnemonic == "sub")) {
5923 Operands.erase(Operands.begin() + 3);
5924 if (Mnemonic == "add" && !CarrySetting) {
5925 // Special case for 'add' (not 'adds') instruction must
5926 // remove the CCOut operand as well.
5927 Operands.erase(Operands.begin() + 1);
5933 // If instruction is 'add' and first two register operands
5934 // use SP register, then remove one of the SP registers from
5936 // FIXME: We would really like to be able to tablegen'erate this.
5937 if (isThumbOne() && Operands.size() == 5 && Mnemonic == "add" && !CarrySetting) {
5938 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5939 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5940 if (Op2.isReg() && Op3.isReg() && Op2.getReg() == ARM::SP && Op3.getReg() == ARM::SP) {
5941 Operands.erase(Operands.begin() + 2);
5945 // GNU Assembler extension (compatibility)
5946 if ((Mnemonic == "ldrd" || Mnemonic == "strd")) {
5947 ARMOperand &Op2 = static_cast<ARMOperand &>(*Operands[2]);
5948 ARMOperand &Op3 = static_cast<ARMOperand &>(*Operands[3]);
5950 assert(Op2.isReg() && "expected register argument");
5952 unsigned SuperReg = MRI->getMatchingSuperReg(
5953 Op2.getReg(), ARM::gsub_0, &MRI->getRegClass(ARM::GPRPairRegClassID));
5955 assert(SuperReg && "expected register pair");
5957 unsigned PairedReg = MRI->getSubReg(SuperReg, ARM::gsub_1);
5960 Operands.begin() + 3,
5961 ARMOperand::CreateReg(PairedReg, Op2.getStartLoc(), Op2.getEndLoc()));
5965 // FIXME: As said above, this is all a pretty gross hack. This instruction
5966 // does not fit with other "subs" and tblgen.
5967 // Adjust operands of B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction
5968 // so the Mnemonic is the original name "subs" and delete the predicate
5969 // operand so it will match the table entry.
5970 if (isThumbTwo() && Mnemonic == "sub" && Operands.size() == 6 &&
5971 static_cast<ARMOperand &>(*Operands[3]).isReg() &&
5972 static_cast<ARMOperand &>(*Operands[3]).getReg() == ARM::PC &&
5973 static_cast<ARMOperand &>(*Operands[4]).isReg() &&
5974 static_cast<ARMOperand &>(*Operands[4]).getReg() == ARM::LR &&
5975 static_cast<ARMOperand &>(*Operands[5]).isImm()) {
5976 Operands.front() = ARMOperand::CreateToken(Name, NameLoc);
5977 Operands.erase(Operands.begin() + 1);
5982 // Validate context-sensitive operand constraints.
5984 // return 'true' if register list contains non-low GPR registers,
5985 // 'false' otherwise. If Reg is in the register list or is HiReg, set
5986 // 'containsReg' to true.
5987 static bool checkLowRegisterList(MCInst Inst, unsigned OpNo, unsigned Reg,
5988 unsigned HiReg, bool &containsReg) {
5989 containsReg = false;
5990 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
5991 unsigned OpReg = Inst.getOperand(i).getReg();
5994 // Anything other than a low register isn't legal here.
5995 if (!isARMLowRegister(OpReg) && (!HiReg || OpReg != HiReg))
6001 // Check if the specified regisgter is in the register list of the inst,
6002 // starting at the indicated operand number.
6003 static bool listContainsReg(MCInst &Inst, unsigned OpNo, unsigned Reg) {
6004 for (unsigned i = OpNo; i < Inst.getNumOperands(); ++i) {
6005 unsigned OpReg = Inst.getOperand(i).getReg();
6012 // Return true if instruction has the interesting property of being
6013 // allowed in IT blocks, but not being predicable.
6014 static bool instIsBreakpoint(const MCInst &Inst) {
6015 return Inst.getOpcode() == ARM::tBKPT ||
6016 Inst.getOpcode() == ARM::BKPT ||
6017 Inst.getOpcode() == ARM::tHLT ||
6018 Inst.getOpcode() == ARM::HLT;
6022 bool ARMAsmParser::validatetLDMRegList(MCInst Inst,
6023 const OperandVector &Operands,
6024 unsigned ListNo, bool IsARPop) {
6025 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6026 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6028 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6029 bool ListContainsLR = listContainsReg(Inst, ListNo, ARM::LR);
6030 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6032 if (!IsARPop && ListContainsSP)
6033 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6034 "SP may not be in the register list");
6035 else if (ListContainsPC && ListContainsLR)
6036 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6037 "PC and LR may not be in the register list simultaneously");
6038 else if (inITBlock() && !lastInITBlock() && ListContainsPC)
6039 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6040 "instruction must be outside of IT block or the last "
6041 "instruction in an IT block");
6045 bool ARMAsmParser::validatetSTMRegList(MCInst Inst,
6046 const OperandVector &Operands,
6048 const ARMOperand &Op = static_cast<const ARMOperand &>(*Operands[ListNo]);
6049 bool HasWritebackToken = Op.isToken() && Op.getToken() == "!";
6051 bool ListContainsSP = listContainsReg(Inst, ListNo, ARM::SP);
6052 bool ListContainsPC = listContainsReg(Inst, ListNo, ARM::PC);
6054 if (ListContainsSP && ListContainsPC)
6055 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6056 "SP and PC may not be in the register list");
6057 else if (ListContainsSP)
6058 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6059 "SP may not be in the register list");
6060 else if (ListContainsPC)
6061 return Error(Operands[ListNo + HasWritebackToken]->getStartLoc(),
6062 "PC may not be in the register list");
6066 // FIXME: We would really like to be able to tablegen'erate this.
6067 bool ARMAsmParser::validateInstruction(MCInst &Inst,
6068 const OperandVector &Operands) {
6069 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
6070 SMLoc Loc = Operands[0]->getStartLoc();
6072 // Check the IT block state first.
6073 // NOTE: BKPT and HLT instructions have the interesting property of being
6074 // allowed in IT blocks, but not being predicable. They just always execute.
6075 if (inITBlock() && !instIsBreakpoint(Inst)) {
6077 if (ITState.FirstCond)
6078 ITState.FirstCond = false;
6080 Bit = (ITState.Mask >> (5 - ITState.CurPosition)) & 1;
6081 // The instruction must be predicable.
6082 if (!MCID.isPredicable())
6083 return Error(Loc, "instructions in IT block must be predicable");
6084 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm();
6085 unsigned ITCond = Bit ? ITState.Cond :
6086 ARMCC::getOppositeCondition(ITState.Cond);
6087 if (Cond != ITCond) {
6088 // Find the condition code Operand to get its SMLoc information.
6090 for (unsigned I = 1; I < Operands.size(); ++I)
6091 if (static_cast<ARMOperand &>(*Operands[I]).isCondCode())
6092 CondLoc = Operands[I]->getStartLoc();
6093 return Error(CondLoc, "incorrect condition in IT block; got '" +
6094 StringRef(ARMCondCodeToString(ARMCC::CondCodes(Cond))) +
6095 "', but expected '" +
6096 ARMCondCodeToString(ARMCC::CondCodes(ITCond)) + "'");
6098 // Check for non-'al' condition codes outside of the IT block.
6099 } else if (isThumbTwo() && MCID.isPredicable() &&
6100 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() !=
6101 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
6102 Inst.getOpcode() != ARM::t2Bcc)
6103 return Error(Loc, "predicated instructions must be in IT block");
6105 const unsigned Opcode = Inst.getOpcode();
6109 case ARM::LDRD_POST: {
6110 const unsigned RtReg = Inst.getOperand(0).getReg();
6113 if (RtReg == ARM::LR)
6114 return Error(Operands[3]->getStartLoc(),
6117 const unsigned Rt = MRI->getEncodingValue(RtReg);
6118 // Rt must be even-numbered.
6120 return Error(Operands[3]->getStartLoc(),
6121 "Rt must be even-numbered");
6123 // Rt2 must be Rt + 1.
6124 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6126 return Error(Operands[3]->getStartLoc(),
6127 "destination operands must be sequential");
6129 if (Opcode == ARM::LDRD_PRE || Opcode == ARM::LDRD_POST) {
6130 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg());
6131 // For addressing modes with writeback, the base register needs to be
6132 // different from the destination registers.
6133 if (Rn == Rt || Rn == Rt2)
6134 return Error(Operands[3]->getStartLoc(),
6135 "base register needs to be different from destination "
6142 case ARM::t2LDRD_PRE:
6143 case ARM::t2LDRD_POST: {
6144 // Rt2 must be different from Rt.
6145 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6146 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6148 return Error(Operands[3]->getStartLoc(),
6149 "destination operands can't be identical");
6153 const unsigned RmReg = Inst.getOperand(0).getReg();
6154 // Rm = SP is no longer unpredictable in v8-A
6155 if (RmReg == ARM::SP && !hasV8Ops())
6156 return Error(Operands[2]->getStartLoc(),
6157 "r13 (SP) is an unpredictable operand to BXJ");
6161 // Rt2 must be Rt + 1.
6162 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6163 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6165 return Error(Operands[3]->getStartLoc(),
6166 "source operands must be sequential");
6170 case ARM::STRD_POST: {
6171 // Rt2 must be Rt + 1.
6172 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6173 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6175 return Error(Operands[3]->getStartLoc(),
6176 "source operands must be sequential");
6179 case ARM::STR_PRE_IMM:
6180 case ARM::STR_PRE_REG:
6181 case ARM::STR_POST_IMM:
6182 case ARM::STR_POST_REG:
6184 case ARM::STRH_POST:
6185 case ARM::STRB_PRE_IMM:
6186 case ARM::STRB_PRE_REG:
6187 case ARM::STRB_POST_IMM:
6188 case ARM::STRB_POST_REG: {
6189 // Rt must be different from Rn.
6190 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
6191 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6194 return Error(Operands[3]->getStartLoc(),
6195 "source register and base register can't be identical");
6198 case ARM::LDR_PRE_IMM:
6199 case ARM::LDR_PRE_REG:
6200 case ARM::LDR_POST_IMM:
6201 case ARM::LDR_POST_REG:
6203 case ARM::LDRH_POST:
6204 case ARM::LDRSH_PRE:
6205 case ARM::LDRSH_POST:
6206 case ARM::LDRB_PRE_IMM:
6207 case ARM::LDRB_PRE_REG:
6208 case ARM::LDRB_POST_IMM:
6209 case ARM::LDRB_POST_REG:
6210 case ARM::LDRSB_PRE:
6211 case ARM::LDRSB_POST: {
6212 // Rt must be different from Rn.
6213 const unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
6214 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(2).getReg());
6217 return Error(Operands[3]->getStartLoc(),
6218 "destination register and base register can't be identical");
6223 // Width must be in range [1, 32-lsb].
6224 unsigned LSB = Inst.getOperand(2).getImm();
6225 unsigned Widthm1 = Inst.getOperand(3).getImm();
6226 if (Widthm1 >= 32 - LSB)
6227 return Error(Operands[5]->getStartLoc(),
6228 "bitfield width must be in range [1,32-lsb]");
6231 // Notionally handles ARM::tLDMIA_UPD too.
6233 // If we're parsing Thumb2, the .w variant is available and handles
6234 // most cases that are normally illegal for a Thumb1 LDM instruction.
6235 // We'll make the transformation in processInstruction() if necessary.
6237 // Thumb LDM instructions are writeback iff the base register is not
6238 // in the register list.
6239 unsigned Rn = Inst.getOperand(0).getReg();
6240 bool HasWritebackToken =
6241 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
6242 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
6243 bool ListContainsBase;
6244 if (checkLowRegisterList(Inst, 3, Rn, 0, ListContainsBase) && !isThumbTwo())
6245 return Error(Operands[3 + HasWritebackToken]->getStartLoc(),
6246 "registers must be in range r0-r7");
6247 // If we should have writeback, then there should be a '!' token.
6248 if (!ListContainsBase && !HasWritebackToken && !isThumbTwo())
6249 return Error(Operands[2]->getStartLoc(),
6250 "writeback operator '!' expected");
6251 // If we should not have writeback, there must not be a '!'. This is
6252 // true even for the 32-bit wide encodings.
6253 if (ListContainsBase && HasWritebackToken)
6254 return Error(Operands[3]->getStartLoc(),
6255 "writeback operator '!' not allowed when base register "
6256 "in register list");
6258 if (validatetLDMRegList(Inst, Operands, 3))
6262 case ARM::LDMIA_UPD:
6263 case ARM::LDMDB_UPD:
6264 case ARM::LDMIB_UPD:
6265 case ARM::LDMDA_UPD:
6266 // ARM variants loading and updating the same register are only officially
6267 // UNPREDICTABLE on v7 upwards. Goodness knows what they did before.
6270 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6271 return Error(Operands.back()->getStartLoc(),
6272 "writeback register not allowed in register list");
6276 if (validatetLDMRegList(Inst, Operands, 3))
6281 if (validatetSTMRegList(Inst, Operands, 3))
6284 case ARM::t2LDMIA_UPD:
6285 case ARM::t2LDMDB_UPD:
6286 case ARM::t2STMIA_UPD:
6287 case ARM::t2STMDB_UPD: {
6288 if (listContainsReg(Inst, 3, Inst.getOperand(0).getReg()))
6289 return Error(Operands.back()->getStartLoc(),
6290 "writeback register not allowed in register list");
6292 if (Opcode == ARM::t2LDMIA_UPD || Opcode == ARM::t2LDMDB_UPD) {
6293 if (validatetLDMRegList(Inst, Operands, 3))
6296 if (validatetSTMRegList(Inst, Operands, 3))
6301 case ARM::sysLDMIA_UPD:
6302 case ARM::sysLDMDA_UPD:
6303 case ARM::sysLDMDB_UPD:
6304 case ARM::sysLDMIB_UPD:
6305 if (!listContainsReg(Inst, 3, ARM::PC))
6306 return Error(Operands[4]->getStartLoc(),
6307 "writeback register only allowed on system LDM "
6308 "if PC in register-list");
6310 case ARM::sysSTMIA_UPD:
6311 case ARM::sysSTMDA_UPD:
6312 case ARM::sysSTMDB_UPD:
6313 case ARM::sysSTMIB_UPD:
6314 return Error(Operands[2]->getStartLoc(),
6315 "system STM cannot have writeback register");
6317 // The second source operand must be the same register as the destination
6320 // In this case, we must directly check the parsed operands because the
6321 // cvtThumbMultiply() function is written in such a way that it guarantees
6322 // this first statement is always true for the new Inst. Essentially, the
6323 // destination is unconditionally copied into the second source operand
6324 // without checking to see if it matches what we actually parsed.
6325 if (Operands.size() == 6 && (((ARMOperand &)*Operands[3]).getReg() !=
6326 ((ARMOperand &)*Operands[5]).getReg()) &&
6327 (((ARMOperand &)*Operands[3]).getReg() !=
6328 ((ARMOperand &)*Operands[4]).getReg())) {
6329 return Error(Operands[3]->getStartLoc(),
6330 "destination register must match source register");
6334 // Like for ldm/stm, push and pop have hi-reg handling version in Thumb2,
6335 // so only issue a diagnostic for thumb1. The instructions will be
6336 // switched to the t2 encodings in processInstruction() if necessary.
6338 bool ListContainsBase;
6339 if (checkLowRegisterList(Inst, 2, 0, ARM::PC, ListContainsBase) &&
6341 return Error(Operands[2]->getStartLoc(),
6342 "registers must be in range r0-r7 or pc");
6343 if (validatetLDMRegList(Inst, Operands, 2, !isMClass()))
6348 bool ListContainsBase;
6349 if (checkLowRegisterList(Inst, 2, 0, ARM::LR, ListContainsBase) &&
6351 return Error(Operands[2]->getStartLoc(),
6352 "registers must be in range r0-r7 or lr");
6353 if (validatetSTMRegList(Inst, Operands, 2))
6357 case ARM::tSTMIA_UPD: {
6358 bool ListContainsBase, InvalidLowList;
6359 InvalidLowList = checkLowRegisterList(Inst, 4, Inst.getOperand(0).getReg(),
6360 0, ListContainsBase);
6361 if (InvalidLowList && !isThumbTwo())
6362 return Error(Operands[4]->getStartLoc(),
6363 "registers must be in range r0-r7");
6365 // This would be converted to a 32-bit stm, but that's not valid if the
6366 // writeback register is in the list.
6367 if (InvalidLowList && ListContainsBase)
6368 return Error(Operands[4]->getStartLoc(),
6369 "writeback operator '!' not allowed when base register "
6370 "in register list");
6372 if (validatetSTMRegList(Inst, Operands, 4))
6376 case ARM::tADDrSP: {
6377 // If the non-SP source operand and the destination operand are not the
6378 // same, we need thumb2 (for the wide encoding), or we have an error.
6379 if (!isThumbTwo() &&
6380 Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
6381 return Error(Operands[4]->getStartLoc(),
6382 "source register must be the same as destination");
6386 // Final range checking for Thumb unconditional branch instructions.
6388 if (!(static_cast<ARMOperand &>(*Operands[2])).isSignedOffset<11, 1>())
6389 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6392 int op = (Operands[2]->isImm()) ? 2 : 3;
6393 if (!static_cast<ARMOperand &>(*Operands[op]).isSignedOffset<24, 1>())
6394 return Error(Operands[op]->getStartLoc(), "branch target out of range");
6397 // Final range checking for Thumb conditional branch instructions.
6399 if (!static_cast<ARMOperand &>(*Operands[2]).isSignedOffset<8, 1>())
6400 return Error(Operands[2]->getStartLoc(), "branch target out of range");
6403 int Op = (Operands[2]->isImm()) ? 2 : 3;
6404 if (!static_cast<ARMOperand &>(*Operands[Op]).isSignedOffset<20, 1>())
6405 return Error(Operands[Op]->getStartLoc(), "branch target out of range");
6410 case ARM::t2MOVTi16:
6412 // We want to avoid misleadingly allowing something like "mov r0, <symbol>"
6413 // especially when we turn it into a movw and the expression <symbol> does
6414 // not have a :lower16: or :upper16 as part of the expression. We don't
6415 // want the behavior of silently truncating, which can be unexpected and
6416 // lead to bugs that are difficult to find since this is an easy mistake
6418 int i = (Operands[3]->isImm()) ? 3 : 4;
6419 ARMOperand &Op = static_cast<ARMOperand &>(*Operands[i]);
6420 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm());
6422 const MCExpr *E = dyn_cast<MCExpr>(Op.getImm());
6424 const ARMMCExpr *ARM16Expr = dyn_cast<ARMMCExpr>(E);
6425 if (!ARM16Expr || (ARM16Expr->getKind() != ARMMCExpr::VK_ARM_HI16 &&
6426 ARM16Expr->getKind() != ARMMCExpr::VK_ARM_LO16))
6429 "immediate expression for mov requires :lower16: or :upper16");
6437 static unsigned getRealVSTOpcode(unsigned Opc, unsigned &Spacing) {
6439 default: llvm_unreachable("unexpected opcode!");
6441 case ARM::VST1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6442 case ARM::VST1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6443 case ARM::VST1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6444 case ARM::VST1LNdWB_register_Asm_8: Spacing = 1; return ARM::VST1LNd8_UPD;
6445 case ARM::VST1LNdWB_register_Asm_16: Spacing = 1; return ARM::VST1LNd16_UPD;
6446 case ARM::VST1LNdWB_register_Asm_32: Spacing = 1; return ARM::VST1LNd32_UPD;
6447 case ARM::VST1LNdAsm_8: Spacing = 1; return ARM::VST1LNd8;
6448 case ARM::VST1LNdAsm_16: Spacing = 1; return ARM::VST1LNd16;
6449 case ARM::VST1LNdAsm_32: Spacing = 1; return ARM::VST1LNd32;
6452 case ARM::VST2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6453 case ARM::VST2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6454 case ARM::VST2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6455 case ARM::VST2LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6456 case ARM::VST2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6458 case ARM::VST2LNdWB_register_Asm_8: Spacing = 1; return ARM::VST2LNd8_UPD;
6459 case ARM::VST2LNdWB_register_Asm_16: Spacing = 1; return ARM::VST2LNd16_UPD;
6460 case ARM::VST2LNdWB_register_Asm_32: Spacing = 1; return ARM::VST2LNd32_UPD;
6461 case ARM::VST2LNqWB_register_Asm_16: Spacing = 2; return ARM::VST2LNq16_UPD;
6462 case ARM::VST2LNqWB_register_Asm_32: Spacing = 2; return ARM::VST2LNq32_UPD;
6464 case ARM::VST2LNdAsm_8: Spacing = 1; return ARM::VST2LNd8;
6465 case ARM::VST2LNdAsm_16: Spacing = 1; return ARM::VST2LNd16;
6466 case ARM::VST2LNdAsm_32: Spacing = 1; return ARM::VST2LNd32;
6467 case ARM::VST2LNqAsm_16: Spacing = 2; return ARM::VST2LNq16;
6468 case ARM::VST2LNqAsm_32: Spacing = 2; return ARM::VST2LNq32;
6471 case ARM::VST3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6472 case ARM::VST3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6473 case ARM::VST3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6474 case ARM::VST3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST3LNq16_UPD;
6475 case ARM::VST3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6476 case ARM::VST3LNdWB_register_Asm_8: Spacing = 1; return ARM::VST3LNd8_UPD;
6477 case ARM::VST3LNdWB_register_Asm_16: Spacing = 1; return ARM::VST3LNd16_UPD;
6478 case ARM::VST3LNdWB_register_Asm_32: Spacing = 1; return ARM::VST3LNd32_UPD;
6479 case ARM::VST3LNqWB_register_Asm_16: Spacing = 2; return ARM::VST3LNq16_UPD;
6480 case ARM::VST3LNqWB_register_Asm_32: Spacing = 2; return ARM::VST3LNq32_UPD;
6481 case ARM::VST3LNdAsm_8: Spacing = 1; return ARM::VST3LNd8;
6482 case ARM::VST3LNdAsm_16: Spacing = 1; return ARM::VST3LNd16;
6483 case ARM::VST3LNdAsm_32: Spacing = 1; return ARM::VST3LNd32;
6484 case ARM::VST3LNqAsm_16: Spacing = 2; return ARM::VST3LNq16;
6485 case ARM::VST3LNqAsm_32: Spacing = 2; return ARM::VST3LNq32;
6488 case ARM::VST3dWB_fixed_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6489 case ARM::VST3dWB_fixed_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6490 case ARM::VST3dWB_fixed_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6491 case ARM::VST3qWB_fixed_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6492 case ARM::VST3qWB_fixed_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6493 case ARM::VST3qWB_fixed_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6494 case ARM::VST3dWB_register_Asm_8: Spacing = 1; return ARM::VST3d8_UPD;
6495 case ARM::VST3dWB_register_Asm_16: Spacing = 1; return ARM::VST3d16_UPD;
6496 case ARM::VST3dWB_register_Asm_32: Spacing = 1; return ARM::VST3d32_UPD;
6497 case ARM::VST3qWB_register_Asm_8: Spacing = 2; return ARM::VST3q8_UPD;
6498 case ARM::VST3qWB_register_Asm_16: Spacing = 2; return ARM::VST3q16_UPD;
6499 case ARM::VST3qWB_register_Asm_32: Spacing = 2; return ARM::VST3q32_UPD;
6500 case ARM::VST3dAsm_8: Spacing = 1; return ARM::VST3d8;
6501 case ARM::VST3dAsm_16: Spacing = 1; return ARM::VST3d16;
6502 case ARM::VST3dAsm_32: Spacing = 1; return ARM::VST3d32;
6503 case ARM::VST3qAsm_8: Spacing = 2; return ARM::VST3q8;
6504 case ARM::VST3qAsm_16: Spacing = 2; return ARM::VST3q16;
6505 case ARM::VST3qAsm_32: Spacing = 2; return ARM::VST3q32;
6508 case ARM::VST4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6509 case ARM::VST4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6510 case ARM::VST4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6511 case ARM::VST4LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VST4LNq16_UPD;
6512 case ARM::VST4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6513 case ARM::VST4LNdWB_register_Asm_8: Spacing = 1; return ARM::VST4LNd8_UPD;
6514 case ARM::VST4LNdWB_register_Asm_16: Spacing = 1; return ARM::VST4LNd16_UPD;
6515 case ARM::VST4LNdWB_register_Asm_32: Spacing = 1; return ARM::VST4LNd32_UPD;
6516 case ARM::VST4LNqWB_register_Asm_16: Spacing = 2; return ARM::VST4LNq16_UPD;
6517 case ARM::VST4LNqWB_register_Asm_32: Spacing = 2; return ARM::VST4LNq32_UPD;
6518 case ARM::VST4LNdAsm_8: Spacing = 1; return ARM::VST4LNd8;
6519 case ARM::VST4LNdAsm_16: Spacing = 1; return ARM::VST4LNd16;
6520 case ARM::VST4LNdAsm_32: Spacing = 1; return ARM::VST4LNd32;
6521 case ARM::VST4LNqAsm_16: Spacing = 2; return ARM::VST4LNq16;
6522 case ARM::VST4LNqAsm_32: Spacing = 2; return ARM::VST4LNq32;
6525 case ARM::VST4dWB_fixed_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6526 case ARM::VST4dWB_fixed_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6527 case ARM::VST4dWB_fixed_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6528 case ARM::VST4qWB_fixed_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6529 case ARM::VST4qWB_fixed_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6530 case ARM::VST4qWB_fixed_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6531 case ARM::VST4dWB_register_Asm_8: Spacing = 1; return ARM::VST4d8_UPD;
6532 case ARM::VST4dWB_register_Asm_16: Spacing = 1; return ARM::VST4d16_UPD;
6533 case ARM::VST4dWB_register_Asm_32: Spacing = 1; return ARM::VST4d32_UPD;
6534 case ARM::VST4qWB_register_Asm_8: Spacing = 2; return ARM::VST4q8_UPD;
6535 case ARM::VST4qWB_register_Asm_16: Spacing = 2; return ARM::VST4q16_UPD;
6536 case ARM::VST4qWB_register_Asm_32: Spacing = 2; return ARM::VST4q32_UPD;
6537 case ARM::VST4dAsm_8: Spacing = 1; return ARM::VST4d8;
6538 case ARM::VST4dAsm_16: Spacing = 1; return ARM::VST4d16;
6539 case ARM::VST4dAsm_32: Spacing = 1; return ARM::VST4d32;
6540 case ARM::VST4qAsm_8: Spacing = 2; return ARM::VST4q8;
6541 case ARM::VST4qAsm_16: Spacing = 2; return ARM::VST4q16;
6542 case ARM::VST4qAsm_32: Spacing = 2; return ARM::VST4q32;
6546 static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
6548 default: llvm_unreachable("unexpected opcode!");
6550 case ARM::VLD1LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6551 case ARM::VLD1LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6552 case ARM::VLD1LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6553 case ARM::VLD1LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD1LNd8_UPD;
6554 case ARM::VLD1LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD1LNd16_UPD;
6555 case ARM::VLD1LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD1LNd32_UPD;
6556 case ARM::VLD1LNdAsm_8: Spacing = 1; return ARM::VLD1LNd8;
6557 case ARM::VLD1LNdAsm_16: Spacing = 1; return ARM::VLD1LNd16;
6558 case ARM::VLD1LNdAsm_32: Spacing = 1; return ARM::VLD1LNd32;
6561 case ARM::VLD2LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6562 case ARM::VLD2LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6563 case ARM::VLD2LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6564 case ARM::VLD2LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD2LNq16_UPD;
6565 case ARM::VLD2LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6566 case ARM::VLD2LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD2LNd8_UPD;
6567 case ARM::VLD2LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD2LNd16_UPD;
6568 case ARM::VLD2LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD2LNd32_UPD;
6569 case ARM::VLD2LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD2LNq16_UPD;
6570 case ARM::VLD2LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD2LNq32_UPD;
6571 case ARM::VLD2LNdAsm_8: Spacing = 1; return ARM::VLD2LNd8;
6572 case ARM::VLD2LNdAsm_16: Spacing = 1; return ARM::VLD2LNd16;
6573 case ARM::VLD2LNdAsm_32: Spacing = 1; return ARM::VLD2LNd32;
6574 case ARM::VLD2LNqAsm_16: Spacing = 2; return ARM::VLD2LNq16;
6575 case ARM::VLD2LNqAsm_32: Spacing = 2; return ARM::VLD2LNq32;
6578 case ARM::VLD3DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6579 case ARM::VLD3DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6580 case ARM::VLD3DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6581 case ARM::VLD3DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3DUPq8_UPD;
6582 case ARM::VLD3DUPqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6583 case ARM::VLD3DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6584 case ARM::VLD3DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD3DUPd8_UPD;
6585 case ARM::VLD3DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD3DUPd16_UPD;
6586 case ARM::VLD3DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD3DUPd32_UPD;
6587 case ARM::VLD3DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD3DUPq8_UPD;
6588 case ARM::VLD3DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD3DUPq16_UPD;
6589 case ARM::VLD3DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD3DUPq32_UPD;
6590 case ARM::VLD3DUPdAsm_8: Spacing = 1; return ARM::VLD3DUPd8;
6591 case ARM::VLD3DUPdAsm_16: Spacing = 1; return ARM::VLD3DUPd16;
6592 case ARM::VLD3DUPdAsm_32: Spacing = 1; return ARM::VLD3DUPd32;
6593 case ARM::VLD3DUPqAsm_8: Spacing = 2; return ARM::VLD3DUPq8;
6594 case ARM::VLD3DUPqAsm_16: Spacing = 2; return ARM::VLD3DUPq16;
6595 case ARM::VLD3DUPqAsm_32: Spacing = 2; return ARM::VLD3DUPq32;
6598 case ARM::VLD3LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6599 case ARM::VLD3LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6600 case ARM::VLD3LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6601 case ARM::VLD3LNqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3LNq16_UPD;
6602 case ARM::VLD3LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6603 case ARM::VLD3LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD3LNd8_UPD;
6604 case ARM::VLD3LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD3LNd16_UPD;
6605 case ARM::VLD3LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD3LNd32_UPD;
6606 case ARM::VLD3LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD3LNq16_UPD;
6607 case ARM::VLD3LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD3LNq32_UPD;
6608 case ARM::VLD3LNdAsm_8: Spacing = 1; return ARM::VLD3LNd8;
6609 case ARM::VLD3LNdAsm_16: Spacing = 1; return ARM::VLD3LNd16;
6610 case ARM::VLD3LNdAsm_32: Spacing = 1; return ARM::VLD3LNd32;
6611 case ARM::VLD3LNqAsm_16: Spacing = 2; return ARM::VLD3LNq16;
6612 case ARM::VLD3LNqAsm_32: Spacing = 2; return ARM::VLD3LNq32;
6615 case ARM::VLD3dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6616 case ARM::VLD3dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6617 case ARM::VLD3dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6618 case ARM::VLD3qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6619 case ARM::VLD3qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6620 case ARM::VLD3qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6621 case ARM::VLD3dWB_register_Asm_8: Spacing = 1; return ARM::VLD3d8_UPD;
6622 case ARM::VLD3dWB_register_Asm_16: Spacing = 1; return ARM::VLD3d16_UPD;
6623 case ARM::VLD3dWB_register_Asm_32: Spacing = 1; return ARM::VLD3d32_UPD;
6624 case ARM::VLD3qWB_register_Asm_8: Spacing = 2; return ARM::VLD3q8_UPD;
6625 case ARM::VLD3qWB_register_Asm_16: Spacing = 2; return ARM::VLD3q16_UPD;
6626 case ARM::VLD3qWB_register_Asm_32: Spacing = 2; return ARM::VLD3q32_UPD;
6627 case ARM::VLD3dAsm_8: Spacing = 1; return ARM::VLD3d8;
6628 case ARM::VLD3dAsm_16: Spacing = 1; return ARM::VLD3d16;
6629 case ARM::VLD3dAsm_32: Spacing = 1; return ARM::VLD3d32;
6630 case ARM::VLD3qAsm_8: Spacing = 2; return ARM::VLD3q8;
6631 case ARM::VLD3qAsm_16: Spacing = 2; return ARM::VLD3q16;
6632 case ARM::VLD3qAsm_32: Spacing = 2; return ARM::VLD3q32;
6635 case ARM::VLD4LNdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6636 case ARM::VLD4LNdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6637 case ARM::VLD4LNdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6638 case ARM::VLD4LNqWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6639 case ARM::VLD4LNqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6640 case ARM::VLD4LNdWB_register_Asm_8: Spacing = 1; return ARM::VLD4LNd8_UPD;
6641 case ARM::VLD4LNdWB_register_Asm_16: Spacing = 1; return ARM::VLD4LNd16_UPD;
6642 case ARM::VLD4LNdWB_register_Asm_32: Spacing = 1; return ARM::VLD4LNd32_UPD;
6643 case ARM::VLD4LNqWB_register_Asm_16: Spacing = 2; return ARM::VLD4LNq16_UPD;
6644 case ARM::VLD4LNqWB_register_Asm_32: Spacing = 2; return ARM::VLD4LNq32_UPD;
6645 case ARM::VLD4LNdAsm_8: Spacing = 1; return ARM::VLD4LNd8;
6646 case ARM::VLD4LNdAsm_16: Spacing = 1; return ARM::VLD4LNd16;
6647 case ARM::VLD4LNdAsm_32: Spacing = 1; return ARM::VLD4LNd32;
6648 case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
6649 case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
6652 case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6653 case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6654 case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6655 case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
6656 case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
6657 case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6658 case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
6659 case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
6660 case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
6661 case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
6662 case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
6663 case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
6664 case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
6665 case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
6666 case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
6667 case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
6668 case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
6669 case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
6672 case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6673 case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6674 case ARM::VLD4dWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6675 case ARM::VLD4qWB_fixed_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6676 case ARM::VLD4qWB_fixed_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6677 case ARM::VLD4qWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6678 case ARM::VLD4dWB_register_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
6679 case ARM::VLD4dWB_register_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
6680 case ARM::VLD4dWB_register_Asm_32: Spacing = 1; return ARM::VLD4d32_UPD;
6681 case ARM::VLD4qWB_register_Asm_8: Spacing = 2; return ARM::VLD4q8_UPD;
6682 case ARM::VLD4qWB_register_Asm_16: Spacing = 2; return ARM::VLD4q16_UPD;
6683 case ARM::VLD4qWB_register_Asm_32: Spacing = 2; return ARM::VLD4q32_UPD;
6684 case ARM::VLD4dAsm_8: Spacing = 1; return ARM::VLD4d8;
6685 case ARM::VLD4dAsm_16: Spacing = 1; return ARM::VLD4d16;
6686 case ARM::VLD4dAsm_32: Spacing = 1; return ARM::VLD4d32;
6687 case ARM::VLD4qAsm_8: Spacing = 2; return ARM::VLD4q8;
6688 case ARM::VLD4qAsm_16: Spacing = 2; return ARM::VLD4q16;
6689 case ARM::VLD4qAsm_32: Spacing = 2; return ARM::VLD4q32;
6693 bool ARMAsmParser::processInstruction(MCInst &Inst,
6694 const OperandVector &Operands,
6696 switch (Inst.getOpcode()) {
6697 // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
6698 case ARM::LDRT_POST:
6699 case ARM::LDRBT_POST: {
6700 const unsigned Opcode =
6701 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
6702 : ARM::LDRBT_POST_IMM;
6704 TmpInst.setOpcode(Opcode);
6705 TmpInst.addOperand(Inst.getOperand(0));
6706 TmpInst.addOperand(Inst.getOperand(1));
6707 TmpInst.addOperand(Inst.getOperand(1));
6708 TmpInst.addOperand(MCOperand::CreateReg(0));
6709 TmpInst.addOperand(MCOperand::CreateImm(0));
6710 TmpInst.addOperand(Inst.getOperand(2));
6711 TmpInst.addOperand(Inst.getOperand(3));
6715 // Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
6716 case ARM::STRT_POST:
6717 case ARM::STRBT_POST: {
6718 const unsigned Opcode =
6719 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
6720 : ARM::STRBT_POST_IMM;
6722 TmpInst.setOpcode(Opcode);
6723 TmpInst.addOperand(Inst.getOperand(1));
6724 TmpInst.addOperand(Inst.getOperand(0));
6725 TmpInst.addOperand(Inst.getOperand(1));
6726 TmpInst.addOperand(MCOperand::CreateReg(0));
6727 TmpInst.addOperand(MCOperand::CreateImm(0));
6728 TmpInst.addOperand(Inst.getOperand(2));
6729 TmpInst.addOperand(Inst.getOperand(3));
6733 // Alias for alternate form of 'ADR Rd, #imm' instruction.
6735 if (Inst.getOperand(1).getReg() != ARM::PC ||
6736 Inst.getOperand(5).getReg() != 0 ||
6737 !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
6740 TmpInst.setOpcode(ARM::ADR);
6741 TmpInst.addOperand(Inst.getOperand(0));
6742 if (Inst.getOperand(2).isImm()) {
6743 // Immediate (mod_imm) will be in its encoded form, we must unencode it
6744 // before passing it to the ADR instruction.
6745 unsigned Enc = Inst.getOperand(2).getImm();
6746 TmpInst.addOperand(MCOperand::CreateImm(
6747 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
6749 // Turn PC-relative expression into absolute expression.
6750 // Reading PC provides the start of the current instruction + 8 and
6751 // the transform to adr is biased by that.
6752 MCSymbol *Dot = getContext().CreateTempSymbol();
6754 const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
6755 const MCExpr *InstPC = MCSymbolRefExpr::Create(Dot,
6756 MCSymbolRefExpr::VK_None,
6758 const MCExpr *Const8 = MCConstantExpr::Create(8, getContext());
6759 const MCExpr *ReadPC = MCBinaryExpr::CreateAdd(InstPC, Const8,
6761 const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr,
6763 TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));
6765 TmpInst.addOperand(Inst.getOperand(3));
6766 TmpInst.addOperand(Inst.getOperand(4));
6770 // Aliases for alternate PC+imm syntax of LDR instructions.
6771 case ARM::t2LDRpcrel:
6772 // Select the narrow version if the immediate will fit.
6773 if (Inst.getOperand(1).getImm() > 0 &&
6774 Inst.getOperand(1).getImm() <= 0xff &&
6775 !(static_cast<ARMOperand &>(*Operands[2]).isToken() &&
6776 static_cast<ARMOperand &>(*Operands[2]).getToken() == ".w"))
6777 Inst.setOpcode(ARM::tLDRpci);
6779 Inst.setOpcode(ARM::t2LDRpci);
6781 case ARM::t2LDRBpcrel:
6782 Inst.setOpcode(ARM::t2LDRBpci);
6784 case ARM::t2LDRHpcrel:
6785 Inst.setOpcode(ARM::t2LDRHpci);
6787 case ARM::t2LDRSBpcrel:
6788 Inst.setOpcode(ARM::t2LDRSBpci);
6790 case ARM::t2LDRSHpcrel:
6791 Inst.setOpcode(ARM::t2LDRSHpci);
6793 // Handle NEON VST complex aliases.
6794 case ARM::VST1LNdWB_register_Asm_8:
6795 case ARM::VST1LNdWB_register_Asm_16:
6796 case ARM::VST1LNdWB_register_Asm_32: {
6798 // Shuffle the operands around so the lane index operand is in the
6801 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6802 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6803 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6804 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6805 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6806 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6807 TmpInst.addOperand(Inst.getOperand(1)); // lane
6808 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6809 TmpInst.addOperand(Inst.getOperand(6));
6814 case ARM::VST2LNdWB_register_Asm_8:
6815 case ARM::VST2LNdWB_register_Asm_16:
6816 case ARM::VST2LNdWB_register_Asm_32:
6817 case ARM::VST2LNqWB_register_Asm_16:
6818 case ARM::VST2LNqWB_register_Asm_32: {
6820 // Shuffle the operands around so the lane index operand is in the
6823 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6824 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6825 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6826 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6827 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6828 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6829 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6831 TmpInst.addOperand(Inst.getOperand(1)); // lane
6832 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6833 TmpInst.addOperand(Inst.getOperand(6));
6838 case ARM::VST3LNdWB_register_Asm_8:
6839 case ARM::VST3LNdWB_register_Asm_16:
6840 case ARM::VST3LNdWB_register_Asm_32:
6841 case ARM::VST3LNqWB_register_Asm_16:
6842 case ARM::VST3LNqWB_register_Asm_32: {
6844 // Shuffle the operands around so the lane index operand is in the
6847 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6848 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6849 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6850 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6851 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6852 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6853 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6855 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6857 TmpInst.addOperand(Inst.getOperand(1)); // lane
6858 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6859 TmpInst.addOperand(Inst.getOperand(6));
6864 case ARM::VST4LNdWB_register_Asm_8:
6865 case ARM::VST4LNdWB_register_Asm_16:
6866 case ARM::VST4LNdWB_register_Asm_32:
6867 case ARM::VST4LNqWB_register_Asm_16:
6868 case ARM::VST4LNqWB_register_Asm_32: {
6870 // Shuffle the operands around so the lane index operand is in the
6873 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6874 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6875 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6876 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6877 TmpInst.addOperand(Inst.getOperand(4)); // Rm
6878 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6879 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6881 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6883 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6885 TmpInst.addOperand(Inst.getOperand(1)); // lane
6886 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
6887 TmpInst.addOperand(Inst.getOperand(6));
6892 case ARM::VST1LNdWB_fixed_Asm_8:
6893 case ARM::VST1LNdWB_fixed_Asm_16:
6894 case ARM::VST1LNdWB_fixed_Asm_32: {
6896 // Shuffle the operands around so the lane index operand is in the
6899 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6900 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6901 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6902 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6903 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6904 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6905 TmpInst.addOperand(Inst.getOperand(1)); // lane
6906 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6907 TmpInst.addOperand(Inst.getOperand(5));
6912 case ARM::VST2LNdWB_fixed_Asm_8:
6913 case ARM::VST2LNdWB_fixed_Asm_16:
6914 case ARM::VST2LNdWB_fixed_Asm_32:
6915 case ARM::VST2LNqWB_fixed_Asm_16:
6916 case ARM::VST2LNqWB_fixed_Asm_32: {
6918 // Shuffle the operands around so the lane index operand is in the
6921 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6922 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6923 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6924 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6925 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6926 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6927 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6929 TmpInst.addOperand(Inst.getOperand(1)); // lane
6930 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6931 TmpInst.addOperand(Inst.getOperand(5));
6936 case ARM::VST3LNdWB_fixed_Asm_8:
6937 case ARM::VST3LNdWB_fixed_Asm_16:
6938 case ARM::VST3LNdWB_fixed_Asm_32:
6939 case ARM::VST3LNqWB_fixed_Asm_16:
6940 case ARM::VST3LNqWB_fixed_Asm_32: {
6942 // Shuffle the operands around so the lane index operand is in the
6945 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6946 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6947 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6948 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6949 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6950 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6951 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6953 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6955 TmpInst.addOperand(Inst.getOperand(1)); // lane
6956 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6957 TmpInst.addOperand(Inst.getOperand(5));
6962 case ARM::VST4LNdWB_fixed_Asm_8:
6963 case ARM::VST4LNdWB_fixed_Asm_16:
6964 case ARM::VST4LNdWB_fixed_Asm_32:
6965 case ARM::VST4LNqWB_fixed_Asm_16:
6966 case ARM::VST4LNqWB_fixed_Asm_32: {
6968 // Shuffle the operands around so the lane index operand is in the
6971 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6972 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
6973 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6974 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6975 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6976 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6977 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6979 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6981 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6983 TmpInst.addOperand(Inst.getOperand(1)); // lane
6984 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
6985 TmpInst.addOperand(Inst.getOperand(5));
6990 case ARM::VST1LNdAsm_8:
6991 case ARM::VST1LNdAsm_16:
6992 case ARM::VST1LNdAsm_32: {
6994 // Shuffle the operands around so the lane index operand is in the
6997 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
6998 TmpInst.addOperand(Inst.getOperand(2)); // Rn
6999 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7000 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7001 TmpInst.addOperand(Inst.getOperand(1)); // lane
7002 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7003 TmpInst.addOperand(Inst.getOperand(5));
7008 case ARM::VST2LNdAsm_8:
7009 case ARM::VST2LNdAsm_16:
7010 case ARM::VST2LNdAsm_32:
7011 case ARM::VST2LNqAsm_16:
7012 case ARM::VST2LNqAsm_32: {
7014 // Shuffle the operands around so the lane index operand is in the
7017 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7018 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7019 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7020 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7021 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7023 TmpInst.addOperand(Inst.getOperand(1)); // lane
7024 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7025 TmpInst.addOperand(Inst.getOperand(5));
7030 case ARM::VST3LNdAsm_8:
7031 case ARM::VST3LNdAsm_16:
7032 case ARM::VST3LNdAsm_32:
7033 case ARM::VST3LNqAsm_16:
7034 case ARM::VST3LNqAsm_32: {
7036 // Shuffle the operands around so the lane index operand is in the
7039 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7040 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7041 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7042 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7043 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7045 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7047 TmpInst.addOperand(Inst.getOperand(1)); // lane
7048 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7049 TmpInst.addOperand(Inst.getOperand(5));
7054 case ARM::VST4LNdAsm_8:
7055 case ARM::VST4LNdAsm_16:
7056 case ARM::VST4LNdAsm_32:
7057 case ARM::VST4LNqAsm_16:
7058 case ARM::VST4LNqAsm_32: {
7060 // Shuffle the operands around so the lane index operand is in the
7063 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7064 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7065 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7066 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7067 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7069 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7071 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7073 TmpInst.addOperand(Inst.getOperand(1)); // lane
7074 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7075 TmpInst.addOperand(Inst.getOperand(5));
7080 // Handle NEON VLD complex aliases.
7081 case ARM::VLD1LNdWB_register_Asm_8:
7082 case ARM::VLD1LNdWB_register_Asm_16:
7083 case ARM::VLD1LNdWB_register_Asm_32: {
7085 // Shuffle the operands around so the lane index operand is in the
7088 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7089 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7090 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7091 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7092 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7093 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7094 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7095 TmpInst.addOperand(Inst.getOperand(1)); // lane
7096 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7097 TmpInst.addOperand(Inst.getOperand(6));
7102 case ARM::VLD2LNdWB_register_Asm_8:
7103 case ARM::VLD2LNdWB_register_Asm_16:
7104 case ARM::VLD2LNdWB_register_Asm_32:
7105 case ARM::VLD2LNqWB_register_Asm_16:
7106 case ARM::VLD2LNqWB_register_Asm_32: {
7108 // Shuffle the operands around so the lane index operand is in the
7111 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7112 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7113 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7115 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7116 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7117 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7118 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7119 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7120 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7122 TmpInst.addOperand(Inst.getOperand(1)); // lane
7123 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7124 TmpInst.addOperand(Inst.getOperand(6));
7129 case ARM::VLD3LNdWB_register_Asm_8:
7130 case ARM::VLD3LNdWB_register_Asm_16:
7131 case ARM::VLD3LNdWB_register_Asm_32:
7132 case ARM::VLD3LNqWB_register_Asm_16:
7133 case ARM::VLD3LNqWB_register_Asm_32: {
7135 // Shuffle the operands around so the lane index operand is in the
7138 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7139 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7140 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7142 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7144 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7145 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7146 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7147 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7148 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7149 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7151 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7153 TmpInst.addOperand(Inst.getOperand(1)); // lane
7154 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7155 TmpInst.addOperand(Inst.getOperand(6));
7160 case ARM::VLD4LNdWB_register_Asm_8:
7161 case ARM::VLD4LNdWB_register_Asm_16:
7162 case ARM::VLD4LNdWB_register_Asm_32:
7163 case ARM::VLD4LNqWB_register_Asm_16:
7164 case ARM::VLD4LNqWB_register_Asm_32: {
7166 // Shuffle the operands around so the lane index operand is in the
7169 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7170 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7171 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7173 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7175 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7177 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7178 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7179 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7180 TmpInst.addOperand(Inst.getOperand(4)); // Rm
7181 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7182 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7184 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7186 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7188 TmpInst.addOperand(Inst.getOperand(1)); // lane
7189 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
7190 TmpInst.addOperand(Inst.getOperand(6));
7195 case ARM::VLD1LNdWB_fixed_Asm_8:
7196 case ARM::VLD1LNdWB_fixed_Asm_16:
7197 case ARM::VLD1LNdWB_fixed_Asm_32: {
7199 // Shuffle the operands around so the lane index operand is in the
7202 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7203 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7204 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7205 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7206 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7207 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7208 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7209 TmpInst.addOperand(Inst.getOperand(1)); // lane
7210 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7211 TmpInst.addOperand(Inst.getOperand(5));
7216 case ARM::VLD2LNdWB_fixed_Asm_8:
7217 case ARM::VLD2LNdWB_fixed_Asm_16:
7218 case ARM::VLD2LNdWB_fixed_Asm_32:
7219 case ARM::VLD2LNqWB_fixed_Asm_16:
7220 case ARM::VLD2LNqWB_fixed_Asm_32: {
7222 // Shuffle the operands around so the lane index operand is in the
7225 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7226 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7227 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7229 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7230 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7231 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7232 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7233 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7234 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7236 TmpInst.addOperand(Inst.getOperand(1)); // lane
7237 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7238 TmpInst.addOperand(Inst.getOperand(5));
7243 case ARM::VLD3LNdWB_fixed_Asm_8:
7244 case ARM::VLD3LNdWB_fixed_Asm_16:
7245 case ARM::VLD3LNdWB_fixed_Asm_32:
7246 case ARM::VLD3LNqWB_fixed_Asm_16:
7247 case ARM::VLD3LNqWB_fixed_Asm_32: {
7249 // Shuffle the operands around so the lane index operand is in the
7252 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7253 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7254 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7256 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7258 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7259 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7260 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7261 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7262 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7263 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7265 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7267 TmpInst.addOperand(Inst.getOperand(1)); // lane
7268 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7269 TmpInst.addOperand(Inst.getOperand(5));
7274 case ARM::VLD4LNdWB_fixed_Asm_8:
7275 case ARM::VLD4LNdWB_fixed_Asm_16:
7276 case ARM::VLD4LNdWB_fixed_Asm_32:
7277 case ARM::VLD4LNqWB_fixed_Asm_16:
7278 case ARM::VLD4LNqWB_fixed_Asm_32: {
7280 // Shuffle the operands around so the lane index operand is in the
7283 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7284 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7285 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7287 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7289 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7291 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
7292 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7293 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7294 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7295 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7296 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7298 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7300 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7302 TmpInst.addOperand(Inst.getOperand(1)); // lane
7303 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7304 TmpInst.addOperand(Inst.getOperand(5));
7309 case ARM::VLD1LNdAsm_8:
7310 case ARM::VLD1LNdAsm_16:
7311 case ARM::VLD1LNdAsm_32: {
7313 // Shuffle the operands around so the lane index operand is in the
7316 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7317 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7318 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7319 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7320 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7321 TmpInst.addOperand(Inst.getOperand(1)); // lane
7322 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7323 TmpInst.addOperand(Inst.getOperand(5));
7328 case ARM::VLD2LNdAsm_8:
7329 case ARM::VLD2LNdAsm_16:
7330 case ARM::VLD2LNdAsm_32:
7331 case ARM::VLD2LNqAsm_16:
7332 case ARM::VLD2LNqAsm_32: {
7334 // Shuffle the operands around so the lane index operand is in the
7337 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7338 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7339 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7341 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7342 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7343 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7344 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7346 TmpInst.addOperand(Inst.getOperand(1)); // lane
7347 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7348 TmpInst.addOperand(Inst.getOperand(5));
7353 case ARM::VLD3LNdAsm_8:
7354 case ARM::VLD3LNdAsm_16:
7355 case ARM::VLD3LNdAsm_32:
7356 case ARM::VLD3LNqAsm_16:
7357 case ARM::VLD3LNqAsm_32: {
7359 // Shuffle the operands around so the lane index operand is in the
7362 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7363 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7364 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7366 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7368 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7369 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7370 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7371 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7373 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7375 TmpInst.addOperand(Inst.getOperand(1)); // lane
7376 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7377 TmpInst.addOperand(Inst.getOperand(5));
7382 case ARM::VLD4LNdAsm_8:
7383 case ARM::VLD4LNdAsm_16:
7384 case ARM::VLD4LNdAsm_32:
7385 case ARM::VLD4LNqAsm_16:
7386 case ARM::VLD4LNqAsm_32: {
7388 // Shuffle the operands around so the lane index operand is in the
7391 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7392 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7393 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7395 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7397 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7399 TmpInst.addOperand(Inst.getOperand(2)); // Rn
7400 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7401 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7402 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7404 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7406 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7408 TmpInst.addOperand(Inst.getOperand(1)); // lane
7409 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7410 TmpInst.addOperand(Inst.getOperand(5));
7415 // VLD3DUP single 3-element structure to all lanes instructions.
7416 case ARM::VLD3DUPdAsm_8:
7417 case ARM::VLD3DUPdAsm_16:
7418 case ARM::VLD3DUPdAsm_32:
7419 case ARM::VLD3DUPqAsm_8:
7420 case ARM::VLD3DUPqAsm_16:
7421 case ARM::VLD3DUPqAsm_32: {
7424 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7425 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7426 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7428 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7430 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7431 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7432 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7433 TmpInst.addOperand(Inst.getOperand(4));
7438 case ARM::VLD3DUPdWB_fixed_Asm_8:
7439 case ARM::VLD3DUPdWB_fixed_Asm_16:
7440 case ARM::VLD3DUPdWB_fixed_Asm_32:
7441 case ARM::VLD3DUPqWB_fixed_Asm_8:
7442 case ARM::VLD3DUPqWB_fixed_Asm_16:
7443 case ARM::VLD3DUPqWB_fixed_Asm_32: {
7446 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7447 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7448 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7450 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7452 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7453 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7454 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7455 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7456 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7457 TmpInst.addOperand(Inst.getOperand(4));
7462 case ARM::VLD3DUPdWB_register_Asm_8:
7463 case ARM::VLD3DUPdWB_register_Asm_16:
7464 case ARM::VLD3DUPdWB_register_Asm_32:
7465 case ARM::VLD3DUPqWB_register_Asm_8:
7466 case ARM::VLD3DUPqWB_register_Asm_16:
7467 case ARM::VLD3DUPqWB_register_Asm_32: {
7470 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7471 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7472 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7474 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7476 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7477 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7478 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7479 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7480 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7481 TmpInst.addOperand(Inst.getOperand(5));
7486 // VLD3 multiple 3-element structure instructions.
7487 case ARM::VLD3dAsm_8:
7488 case ARM::VLD3dAsm_16:
7489 case ARM::VLD3dAsm_32:
7490 case ARM::VLD3qAsm_8:
7491 case ARM::VLD3qAsm_16:
7492 case ARM::VLD3qAsm_32: {
7495 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7496 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7497 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7499 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7501 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7502 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7503 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7504 TmpInst.addOperand(Inst.getOperand(4));
7509 case ARM::VLD3dWB_fixed_Asm_8:
7510 case ARM::VLD3dWB_fixed_Asm_16:
7511 case ARM::VLD3dWB_fixed_Asm_32:
7512 case ARM::VLD3qWB_fixed_Asm_8:
7513 case ARM::VLD3qWB_fixed_Asm_16:
7514 case ARM::VLD3qWB_fixed_Asm_32: {
7517 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7518 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7519 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7521 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7523 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7524 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7525 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7526 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7527 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7528 TmpInst.addOperand(Inst.getOperand(4));
7533 case ARM::VLD3dWB_register_Asm_8:
7534 case ARM::VLD3dWB_register_Asm_16:
7535 case ARM::VLD3dWB_register_Asm_32:
7536 case ARM::VLD3qWB_register_Asm_8:
7537 case ARM::VLD3qWB_register_Asm_16:
7538 case ARM::VLD3qWB_register_Asm_32: {
7541 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7542 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7543 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7545 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7547 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7548 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7549 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7550 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7551 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7552 TmpInst.addOperand(Inst.getOperand(5));
7557 // VLD4DUP single 3-element structure to all lanes instructions.
7558 case ARM::VLD4DUPdAsm_8:
7559 case ARM::VLD4DUPdAsm_16:
7560 case ARM::VLD4DUPdAsm_32:
7561 case ARM::VLD4DUPqAsm_8:
7562 case ARM::VLD4DUPqAsm_16:
7563 case ARM::VLD4DUPqAsm_32: {
7566 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7567 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7568 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7570 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7572 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7574 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7575 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7576 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7577 TmpInst.addOperand(Inst.getOperand(4));
7582 case ARM::VLD4DUPdWB_fixed_Asm_8:
7583 case ARM::VLD4DUPdWB_fixed_Asm_16:
7584 case ARM::VLD4DUPdWB_fixed_Asm_32:
7585 case ARM::VLD4DUPqWB_fixed_Asm_8:
7586 case ARM::VLD4DUPqWB_fixed_Asm_16:
7587 case ARM::VLD4DUPqWB_fixed_Asm_32: {
7590 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7591 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7592 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7594 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7596 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7598 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7599 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7600 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7601 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7602 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7603 TmpInst.addOperand(Inst.getOperand(4));
7608 case ARM::VLD4DUPdWB_register_Asm_8:
7609 case ARM::VLD4DUPdWB_register_Asm_16:
7610 case ARM::VLD4DUPdWB_register_Asm_32:
7611 case ARM::VLD4DUPqWB_register_Asm_8:
7612 case ARM::VLD4DUPqWB_register_Asm_16:
7613 case ARM::VLD4DUPqWB_register_Asm_32: {
7616 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7617 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7618 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7620 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7622 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7624 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7625 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7626 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7627 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7628 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7629 TmpInst.addOperand(Inst.getOperand(5));
7634 // VLD4 multiple 4-element structure instructions.
7635 case ARM::VLD4dAsm_8:
7636 case ARM::VLD4dAsm_16:
7637 case ARM::VLD4dAsm_32:
7638 case ARM::VLD4qAsm_8:
7639 case ARM::VLD4qAsm_16:
7640 case ARM::VLD4qAsm_32: {
7643 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7644 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7645 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7647 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7649 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7651 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7652 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7653 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7654 TmpInst.addOperand(Inst.getOperand(4));
7659 case ARM::VLD4dWB_fixed_Asm_8:
7660 case ARM::VLD4dWB_fixed_Asm_16:
7661 case ARM::VLD4dWB_fixed_Asm_32:
7662 case ARM::VLD4qWB_fixed_Asm_8:
7663 case ARM::VLD4qWB_fixed_Asm_16:
7664 case ARM::VLD4qWB_fixed_Asm_32: {
7667 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7668 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7669 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7671 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7673 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7675 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7676 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7677 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7678 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7679 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7680 TmpInst.addOperand(Inst.getOperand(4));
7685 case ARM::VLD4dWB_register_Asm_8:
7686 case ARM::VLD4dWB_register_Asm_16:
7687 case ARM::VLD4dWB_register_Asm_32:
7688 case ARM::VLD4qWB_register_Asm_8:
7689 case ARM::VLD4qWB_register_Asm_16:
7690 case ARM::VLD4qWB_register_Asm_32: {
7693 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
7694 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7695 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7697 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7699 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7701 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7702 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7703 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7704 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7705 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7706 TmpInst.addOperand(Inst.getOperand(5));
7711 // VST3 multiple 3-element structure instructions.
7712 case ARM::VST3dAsm_8:
7713 case ARM::VST3dAsm_16:
7714 case ARM::VST3dAsm_32:
7715 case ARM::VST3qAsm_8:
7716 case ARM::VST3qAsm_16:
7717 case ARM::VST3qAsm_32: {
7720 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7721 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7722 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7723 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7724 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7726 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7728 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7729 TmpInst.addOperand(Inst.getOperand(4));
7734 case ARM::VST3dWB_fixed_Asm_8:
7735 case ARM::VST3dWB_fixed_Asm_16:
7736 case ARM::VST3dWB_fixed_Asm_32:
7737 case ARM::VST3qWB_fixed_Asm_8:
7738 case ARM::VST3qWB_fixed_Asm_16:
7739 case ARM::VST3qWB_fixed_Asm_32: {
7742 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7743 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7744 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7745 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7746 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7747 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7748 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7750 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7752 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7753 TmpInst.addOperand(Inst.getOperand(4));
7758 case ARM::VST3dWB_register_Asm_8:
7759 case ARM::VST3dWB_register_Asm_16:
7760 case ARM::VST3dWB_register_Asm_32:
7761 case ARM::VST3qWB_register_Asm_8:
7762 case ARM::VST3qWB_register_Asm_16:
7763 case ARM::VST3qWB_register_Asm_32: {
7766 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7767 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7768 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7769 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7770 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7771 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7772 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7774 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7776 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7777 TmpInst.addOperand(Inst.getOperand(5));
7782 // VST4 multiple 3-element structure instructions.
7783 case ARM::VST4dAsm_8:
7784 case ARM::VST4dAsm_16:
7785 case ARM::VST4dAsm_32:
7786 case ARM::VST4qAsm_8:
7787 case ARM::VST4qAsm_16:
7788 case ARM::VST4qAsm_32: {
7791 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7792 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7793 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7794 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7795 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7797 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7799 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7801 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7802 TmpInst.addOperand(Inst.getOperand(4));
7807 case ARM::VST4dWB_fixed_Asm_8:
7808 case ARM::VST4dWB_fixed_Asm_16:
7809 case ARM::VST4dWB_fixed_Asm_32:
7810 case ARM::VST4qWB_fixed_Asm_8:
7811 case ARM::VST4qWB_fixed_Asm_16:
7812 case ARM::VST4qWB_fixed_Asm_32: {
7815 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7816 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7817 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7818 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7819 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7820 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7821 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7823 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7825 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7827 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7828 TmpInst.addOperand(Inst.getOperand(4));
7833 case ARM::VST4dWB_register_Asm_8:
7834 case ARM::VST4dWB_register_Asm_16:
7835 case ARM::VST4dWB_register_Asm_32:
7836 case ARM::VST4qWB_register_Asm_8:
7837 case ARM::VST4qWB_register_Asm_16:
7838 case ARM::VST4qWB_register_Asm_32: {
7841 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
7842 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7843 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
7844 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7845 TmpInst.addOperand(Inst.getOperand(3)); // Rm
7846 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7847 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7849 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7851 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7853 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7854 TmpInst.addOperand(Inst.getOperand(5));
7859 // Handle encoding choice for the shift-immediate instructions.
7862 case ARM::t2ASRri: {
7863 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7864 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7865 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) &&
7866 !(static_cast<ARMOperand &>(*Operands[3]).isToken() &&
7867 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w")) {
7869 switch (Inst.getOpcode()) {
7870 default: llvm_unreachable("unexpected opcode");
7871 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break;
7872 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break;
7873 case ARM::t2ASRri: NewOpc = ARM::tASRri; break;
7875 // The Thumb1 operands aren't in the same order. Awesome, eh?
7877 TmpInst.setOpcode(NewOpc);
7878 TmpInst.addOperand(Inst.getOperand(0));
7879 TmpInst.addOperand(Inst.getOperand(5));
7880 TmpInst.addOperand(Inst.getOperand(1));
7881 TmpInst.addOperand(Inst.getOperand(2));
7882 TmpInst.addOperand(Inst.getOperand(3));
7883 TmpInst.addOperand(Inst.getOperand(4));
7890 // Handle the Thumb2 mode MOV complex aliases.
7892 case ARM::t2MOVSsr: {
7893 // Which instruction to expand to depends on the CCOut operand and
7894 // whether we're in an IT block if the register operands are low
7896 bool isNarrow = false;
7897 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7898 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7899 isARMLowRegister(Inst.getOperand(2).getReg()) &&
7900 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
7901 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
7905 switch(ARM_AM::getSORegShOp(Inst.getOperand(3).getImm())) {
7906 default: llvm_unreachable("unexpected opcode!");
7907 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRrr : ARM::t2ASRrr; break;
7908 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRrr : ARM::t2LSRrr; break;
7909 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLrr : ARM::t2LSLrr; break;
7910 case ARM_AM::ror: newOpc = isNarrow ? ARM::tROR : ARM::t2RORrr; break;
7912 TmpInst.setOpcode(newOpc);
7913 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7915 TmpInst.addOperand(MCOperand::CreateReg(
7916 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7917 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7918 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7919 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
7920 TmpInst.addOperand(Inst.getOperand(5));
7922 TmpInst.addOperand(MCOperand::CreateReg(
7923 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
7928 case ARM::t2MOVSsi: {
7929 // Which instruction to expand to depends on the CCOut operand and
7930 // whether we're in an IT block if the register operands are low
7932 bool isNarrow = false;
7933 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
7934 isARMLowRegister(Inst.getOperand(1).getReg()) &&
7935 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
7939 switch(ARM_AM::getSORegShOp(Inst.getOperand(2).getImm())) {
7940 default: llvm_unreachable("unexpected opcode!");
7941 case ARM_AM::asr: newOpc = isNarrow ? ARM::tASRri : ARM::t2ASRri; break;
7942 case ARM_AM::lsr: newOpc = isNarrow ? ARM::tLSRri : ARM::t2LSRri; break;
7943 case ARM_AM::lsl: newOpc = isNarrow ? ARM::tLSLri : ARM::t2LSLri; break;
7944 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
7945 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
7947 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
7948 if (Amount == 32) Amount = 0;
7949 TmpInst.setOpcode(newOpc);
7950 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7952 TmpInst.addOperand(MCOperand::CreateReg(
7953 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7954 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7955 if (newOpc != ARM::t2RRX)
7956 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7957 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7958 TmpInst.addOperand(Inst.getOperand(4));
7960 TmpInst.addOperand(MCOperand::CreateReg(
7961 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
7965 // Handle the ARM mode MOV complex aliases.
7970 ARM_AM::ShiftOpc ShiftTy;
7971 switch(Inst.getOpcode()) {
7972 default: llvm_unreachable("unexpected opcode!");
7973 case ARM::ASRr: ShiftTy = ARM_AM::asr; break;
7974 case ARM::LSRr: ShiftTy = ARM_AM::lsr; break;
7975 case ARM::LSLr: ShiftTy = ARM_AM::lsl; break;
7976 case ARM::RORr: ShiftTy = ARM_AM::ror; break;
7978 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, 0);
7980 TmpInst.setOpcode(ARM::MOVsr);
7981 TmpInst.addOperand(Inst.getOperand(0)); // Rd
7982 TmpInst.addOperand(Inst.getOperand(1)); // Rn
7983 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7984 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7985 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
7986 TmpInst.addOperand(Inst.getOperand(4));
7987 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
7995 ARM_AM::ShiftOpc ShiftTy;
7996 switch(Inst.getOpcode()) {
7997 default: llvm_unreachable("unexpected opcode!");
7998 case ARM::ASRi: ShiftTy = ARM_AM::asr; break;
7999 case ARM::LSRi: ShiftTy = ARM_AM::lsr; break;
8000 case ARM::LSLi: ShiftTy = ARM_AM::lsl; break;
8001 case ARM::RORi: ShiftTy = ARM_AM::ror; break;
8003 // A shift by zero is a plain MOVr, not a MOVsi.
8004 unsigned Amt = Inst.getOperand(2).getImm();
8005 unsigned Opc = Amt == 0 ? ARM::MOVr : ARM::MOVsi;
8006 // A shift by 32 should be encoded as 0 when permitted
8007 if (Amt == 32 && (ShiftTy == ARM_AM::lsr || ShiftTy == ARM_AM::asr))
8009 unsigned Shifter = ARM_AM::getSORegOpc(ShiftTy, Amt);
8011 TmpInst.setOpcode(Opc);
8012 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8013 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8014 if (Opc == ARM::MOVsi)
8015 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
8016 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
8017 TmpInst.addOperand(Inst.getOperand(4));
8018 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
8023 unsigned Shifter = ARM_AM::getSORegOpc(ARM_AM::rrx, 0);
8025 TmpInst.setOpcode(ARM::MOVsi);
8026 TmpInst.addOperand(Inst.getOperand(0)); // Rd
8027 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8028 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
8029 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8030 TmpInst.addOperand(Inst.getOperand(3));
8031 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
8035 case ARM::t2LDMIA_UPD: {
8036 // If this is a load of a single register, then we should use
8037 // a post-indexed LDR instruction instead, per the ARM ARM.
8038 if (Inst.getNumOperands() != 5)
8041 TmpInst.setOpcode(ARM::t2LDR_POST);
8042 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8043 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8044 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8045 TmpInst.addOperand(MCOperand::CreateImm(4));
8046 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8047 TmpInst.addOperand(Inst.getOperand(3));
8051 case ARM::t2STMDB_UPD: {
8052 // If this is a store of a single register, then we should use
8053 // a pre-indexed STR instruction instead, per the ARM ARM.
8054 if (Inst.getNumOperands() != 5)
8057 TmpInst.setOpcode(ARM::t2STR_PRE);
8058 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8059 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8060 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8061 TmpInst.addOperand(MCOperand::CreateImm(-4));
8062 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8063 TmpInst.addOperand(Inst.getOperand(3));
8067 case ARM::LDMIA_UPD:
8068 // If this is a load of a single register via a 'pop', then we should use
8069 // a post-indexed LDR instruction instead, per the ARM ARM.
8070 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "pop" &&
8071 Inst.getNumOperands() == 5) {
8073 TmpInst.setOpcode(ARM::LDR_POST_IMM);
8074 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8075 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8076 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8077 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
8078 TmpInst.addOperand(MCOperand::CreateImm(4));
8079 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8080 TmpInst.addOperand(Inst.getOperand(3));
8085 case ARM::STMDB_UPD:
8086 // If this is a store of a single register via a 'push', then we should use
8087 // a pre-indexed STR instruction instead, per the ARM ARM.
8088 if (static_cast<ARMOperand &>(*Operands[0]).getToken() == "push" &&
8089 Inst.getNumOperands() == 5) {
8091 TmpInst.setOpcode(ARM::STR_PRE_IMM);
8092 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
8093 TmpInst.addOperand(Inst.getOperand(4)); // Rt
8094 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8095 TmpInst.addOperand(MCOperand::CreateImm(-4));
8096 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
8097 TmpInst.addOperand(Inst.getOperand(3));
8101 case ARM::t2ADDri12:
8102 // If the immediate fits for encoding T3 (t2ADDri) and the generic "add"
8103 // mnemonic was used (not "addw"), encoding T3 is preferred.
8104 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "add" ||
8105 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8107 Inst.setOpcode(ARM::t2ADDri);
8108 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8110 case ARM::t2SUBri12:
8111 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
8112 // mnemonic was used (not "subw"), encoding T3 is preferred.
8113 if (static_cast<ARMOperand &>(*Operands[0]).getToken() != "sub" ||
8114 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
8116 Inst.setOpcode(ARM::t2SUBri);
8117 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8120 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8121 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8122 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8123 // to encoding T1 if <Rd> is omitted."
8124 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8125 Inst.setOpcode(ARM::tADDi3);
8130 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
8131 // explicitly specified. From the ARM ARM: "Encoding T1 is preferred
8132 // to encoding T2 if <Rd> is specified and encoding T2 is preferred
8133 // to encoding T1 if <Rd> is omitted."
8134 if ((unsigned)Inst.getOperand(3).getImm() < 8 && Operands.size() == 6) {
8135 Inst.setOpcode(ARM::tSUBi3);
8140 case ARM::t2SUBri: {
8141 // If the destination and first source operand are the same, and
8142 // the flags are compatible with the current IT status, use encoding T2
8143 // instead of T3. For compatibility with the system 'as'. Make sure the
8144 // wide encoding wasn't explicit.
8145 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8146 !isARMLowRegister(Inst.getOperand(0).getReg()) ||
8147 (unsigned)Inst.getOperand(2).getImm() > 255 ||
8148 ((!inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR) ||
8149 (inITBlock() && Inst.getOperand(5).getReg() != 0)) ||
8150 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8151 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8154 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
8155 ARM::tADDi8 : ARM::tSUBi8);
8156 TmpInst.addOperand(Inst.getOperand(0));
8157 TmpInst.addOperand(Inst.getOperand(5));
8158 TmpInst.addOperand(Inst.getOperand(0));
8159 TmpInst.addOperand(Inst.getOperand(2));
8160 TmpInst.addOperand(Inst.getOperand(3));
8161 TmpInst.addOperand(Inst.getOperand(4));
8165 case ARM::t2ADDrr: {
8166 // If the destination and first source operand are the same, and
8167 // there's no setting of the flags, use encoding T2 instead of T3.
8168 // Note that this is only for ADD, not SUB. This mirrors the system
8169 // 'as' behaviour. Make sure the wide encoding wasn't explicit.
8170 if (Inst.getOperand(0).getReg() != Inst.getOperand(1).getReg() ||
8171 Inst.getOperand(5).getReg() != 0 ||
8172 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8173 static_cast<ARMOperand &>(*Operands[3]).getToken() == ".w"))
8176 TmpInst.setOpcode(ARM::tADDhirr);
8177 TmpInst.addOperand(Inst.getOperand(0));
8178 TmpInst.addOperand(Inst.getOperand(0));
8179 TmpInst.addOperand(Inst.getOperand(2));
8180 TmpInst.addOperand(Inst.getOperand(3));
8181 TmpInst.addOperand(Inst.getOperand(4));
8185 case ARM::tADDrSP: {
8186 // If the non-SP source operand and the destination operand are not the
8187 // same, we need to use the 32-bit encoding if it's available.
8188 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
8189 Inst.setOpcode(ARM::t2ADDrr);
8190 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8196 // A Thumb conditional branch outside of an IT block is a tBcc.
8197 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()) {
8198 Inst.setOpcode(ARM::tBcc);
8203 // A Thumb2 conditional branch outside of an IT block is a t2Bcc.
8204 if (Inst.getOperand(1).getImm() != ARMCC::AL && !inITBlock()){
8205 Inst.setOpcode(ARM::t2Bcc);
8210 // If the conditional is AL or we're in an IT block, we really want t2B.
8211 if (Inst.getOperand(1).getImm() == ARMCC::AL || inITBlock()) {
8212 Inst.setOpcode(ARM::t2B);
8217 // If the conditional is AL, we really want tB.
8218 if (Inst.getOperand(1).getImm() == ARMCC::AL) {
8219 Inst.setOpcode(ARM::tB);
8224 // If the register list contains any high registers, or if the writeback
8225 // doesn't match what tLDMIA can do, we need to use the 32-bit encoding
8226 // instead if we're in Thumb2. Otherwise, this should have generated
8227 // an error in validateInstruction().
8228 unsigned Rn = Inst.getOperand(0).getReg();
8229 bool hasWritebackToken =
8230 (static_cast<ARMOperand &>(*Operands[3]).isToken() &&
8231 static_cast<ARMOperand &>(*Operands[3]).getToken() == "!");
8232 bool listContainsBase;
8233 if (checkLowRegisterList(Inst, 3, Rn, 0, listContainsBase) ||
8234 (!listContainsBase && !hasWritebackToken) ||
8235 (listContainsBase && hasWritebackToken)) {
8236 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8237 assert (isThumbTwo());
8238 Inst.setOpcode(hasWritebackToken ? ARM::t2LDMIA_UPD : ARM::t2LDMIA);
8239 // If we're switching to the updating version, we need to insert
8240 // the writeback tied operand.
8241 if (hasWritebackToken)
8242 Inst.insert(Inst.begin(),
8243 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
8248 case ARM::tSTMIA_UPD: {
8249 // If the register list contains any high registers, we need to use
8250 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8251 // should have generated an error in validateInstruction().
8252 unsigned Rn = Inst.getOperand(0).getReg();
8253 bool listContainsBase;
8254 if (checkLowRegisterList(Inst, 4, Rn, 0, listContainsBase)) {
8255 // 16-bit encoding isn't sufficient. Switch to the 32-bit version.
8256 assert (isThumbTwo());
8257 Inst.setOpcode(ARM::t2STMIA_UPD);
8263 bool listContainsBase;
8264 // If the register list contains any high registers, we need to use
8265 // the 32-bit encoding instead if we're in Thumb2. Otherwise, this
8266 // should have generated an error in validateInstruction().
8267 if (!checkLowRegisterList(Inst, 2, 0, ARM::PC, listContainsBase))
8269 assert (isThumbTwo());
8270 Inst.setOpcode(ARM::t2LDMIA_UPD);
8271 // Add the base register and writeback operands.
8272 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8273 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8277 bool listContainsBase;
8278 if (!checkLowRegisterList(Inst, 2, 0, ARM::LR, listContainsBase))
8280 assert (isThumbTwo());
8281 Inst.setOpcode(ARM::t2STMDB_UPD);
8282 // Add the base register and writeback operands.
8283 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8284 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8288 // If we can use the 16-bit encoding and the user didn't explicitly
8289 // request the 32-bit variant, transform it here.
8290 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8291 (unsigned)Inst.getOperand(1).getImm() <= 255 &&
8292 ((!inITBlock() && Inst.getOperand(2).getImm() == ARMCC::AL &&
8293 Inst.getOperand(4).getReg() == ARM::CPSR) ||
8294 (inITBlock() && Inst.getOperand(4).getReg() == 0)) &&
8295 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8296 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8297 // The operands aren't in the same order for tMOVi8...
8299 TmpInst.setOpcode(ARM::tMOVi8);
8300 TmpInst.addOperand(Inst.getOperand(0));
8301 TmpInst.addOperand(Inst.getOperand(4));
8302 TmpInst.addOperand(Inst.getOperand(1));
8303 TmpInst.addOperand(Inst.getOperand(2));
8304 TmpInst.addOperand(Inst.getOperand(3));
8311 // If we can use the 16-bit encoding and the user didn't explicitly
8312 // request the 32-bit variant, transform it here.
8313 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8314 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8315 Inst.getOperand(2).getImm() == ARMCC::AL &&
8316 Inst.getOperand(4).getReg() == ARM::CPSR &&
8317 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8318 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8319 // The operands aren't the same for tMOV[S]r... (no cc_out)
8321 TmpInst.setOpcode(Inst.getOperand(4).getReg() ? ARM::tMOVSr : ARM::tMOVr);
8322 TmpInst.addOperand(Inst.getOperand(0));
8323 TmpInst.addOperand(Inst.getOperand(1));
8324 TmpInst.addOperand(Inst.getOperand(2));
8325 TmpInst.addOperand(Inst.getOperand(3));
8335 // If we can use the 16-bit encoding and the user didn't explicitly
8336 // request the 32-bit variant, transform it here.
8337 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
8338 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8339 Inst.getOperand(2).getImm() == 0 &&
8340 (!static_cast<ARMOperand &>(*Operands[2]).isToken() ||
8341 static_cast<ARMOperand &>(*Operands[2]).getToken() != ".w")) {
8343 switch (Inst.getOpcode()) {
8344 default: llvm_unreachable("Illegal opcode!");
8345 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break;
8346 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break;
8347 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break;
8348 case ARM::t2UXTB: NewOpc = ARM::tUXTB; break;
8350 // The operands aren't the same for thumb1 (no rotate operand).
8352 TmpInst.setOpcode(NewOpc);
8353 TmpInst.addOperand(Inst.getOperand(0));
8354 TmpInst.addOperand(Inst.getOperand(1));
8355 TmpInst.addOperand(Inst.getOperand(3));
8356 TmpInst.addOperand(Inst.getOperand(4));
8363 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(2).getImm());
8364 // rrx shifts and asr/lsr of #32 is encoded as 0
8365 if (SOpc == ARM_AM::rrx || SOpc == ARM_AM::asr || SOpc == ARM_AM::lsr)
8367 if (ARM_AM::getSORegOffset(Inst.getOperand(2).getImm()) == 0) {
8368 // Shifting by zero is accepted as a vanilla 'MOVr'
8370 TmpInst.setOpcode(ARM::MOVr);
8371 TmpInst.addOperand(Inst.getOperand(0));
8372 TmpInst.addOperand(Inst.getOperand(1));
8373 TmpInst.addOperand(Inst.getOperand(3));
8374 TmpInst.addOperand(Inst.getOperand(4));
8375 TmpInst.addOperand(Inst.getOperand(5));
8388 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(Inst.getOperand(3).getImm());
8389 if (SOpc == ARM_AM::rrx) return false;
8390 switch (Inst.getOpcode()) {
8391 default: llvm_unreachable("unexpected opcode!");
8392 case ARM::ANDrsi: newOpc = ARM::ANDrr; break;
8393 case ARM::ORRrsi: newOpc = ARM::ORRrr; break;
8394 case ARM::EORrsi: newOpc = ARM::EORrr; break;
8395 case ARM::BICrsi: newOpc = ARM::BICrr; break;
8396 case ARM::SUBrsi: newOpc = ARM::SUBrr; break;
8397 case ARM::ADDrsi: newOpc = ARM::ADDrr; break;
8399 // If the shift is by zero, use the non-shifted instruction definition.
8400 // The exception is for right shifts, where 0 == 32
8401 if (ARM_AM::getSORegOffset(Inst.getOperand(3).getImm()) == 0 &&
8402 !(SOpc == ARM_AM::lsr || SOpc == ARM_AM::asr)) {
8404 TmpInst.setOpcode(newOpc);
8405 TmpInst.addOperand(Inst.getOperand(0));
8406 TmpInst.addOperand(Inst.getOperand(1));
8407 TmpInst.addOperand(Inst.getOperand(2));
8408 TmpInst.addOperand(Inst.getOperand(4));
8409 TmpInst.addOperand(Inst.getOperand(5));
8410 TmpInst.addOperand(Inst.getOperand(6));
8418 // The mask bits for all but the first condition are represented as
8419 // the low bit of the condition code value implies 't'. We currently
8420 // always have 1 implies 't', so XOR toggle the bits if the low bit
8421 // of the condition code is zero.
8422 MCOperand &MO = Inst.getOperand(1);
8423 unsigned Mask = MO.getImm();
8424 unsigned OrigMask = Mask;
8425 unsigned TZ = countTrailingZeros(Mask);
8426 if ((Inst.getOperand(0).getImm() & 1) == 0) {
8427 assert(Mask && TZ <= 3 && "illegal IT mask value!");
8428 Mask ^= (0xE << TZ) & 0xF;
8432 // Set up the IT block state according to the IT instruction we just
8434 assert(!inITBlock() && "nested IT blocks?!");
8435 ITState.Cond = ARMCC::CondCodes(Inst.getOperand(0).getImm());
8436 ITState.Mask = OrigMask; // Use the original mask, not the updated one.
8437 ITState.CurPosition = 0;
8438 ITState.FirstCond = true;
8448 // Assemblers should use the narrow encodings of these instructions when permissible.
8449 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8450 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8451 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8452 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8453 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8454 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8455 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8458 switch (Inst.getOpcode()) {
8459 default: llvm_unreachable("unexpected opcode");
8460 case ARM::t2LSLrr: NewOpc = ARM::tLSLrr; break;
8461 case ARM::t2LSRrr: NewOpc = ARM::tLSRrr; break;
8462 case ARM::t2ASRrr: NewOpc = ARM::tASRrr; break;
8463 case ARM::t2SBCrr: NewOpc = ARM::tSBC; break;
8464 case ARM::t2RORrr: NewOpc = ARM::tROR; break;
8465 case ARM::t2BICrr: NewOpc = ARM::tBIC; break;
8468 TmpInst.setOpcode(NewOpc);
8469 TmpInst.addOperand(Inst.getOperand(0));
8470 TmpInst.addOperand(Inst.getOperand(5));
8471 TmpInst.addOperand(Inst.getOperand(1));
8472 TmpInst.addOperand(Inst.getOperand(2));
8473 TmpInst.addOperand(Inst.getOperand(3));
8474 TmpInst.addOperand(Inst.getOperand(4));
8485 // Assemblers should use the narrow encodings of these instructions when permissible.
8486 // These instructions are special in that they are commutable, so shorter encodings
8487 // are available more often.
8488 if ((isARMLowRegister(Inst.getOperand(1).getReg()) &&
8489 isARMLowRegister(Inst.getOperand(2).getReg())) &&
8490 (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() ||
8491 Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg()) &&
8492 ((!inITBlock() && Inst.getOperand(5).getReg() == ARM::CPSR) ||
8493 (inITBlock() && Inst.getOperand(5).getReg() != ARM::CPSR)) &&
8494 (!static_cast<ARMOperand &>(*Operands[3]).isToken() ||
8495 !static_cast<ARMOperand &>(*Operands[3]).getToken().equals_lower(
8498 switch (Inst.getOpcode()) {
8499 default: llvm_unreachable("unexpected opcode");
8500 case ARM::t2ADCrr: NewOpc = ARM::tADC; break;
8501 case ARM::t2ANDrr: NewOpc = ARM::tAND; break;
8502 case ARM::t2EORrr: NewOpc = ARM::tEOR; break;
8503 case ARM::t2ORRrr: NewOpc = ARM::tORR; break;
8506 TmpInst.setOpcode(NewOpc);
8507 TmpInst.addOperand(Inst.getOperand(0));
8508 TmpInst.addOperand(Inst.getOperand(5));
8509 if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
8510 TmpInst.addOperand(Inst.getOperand(1));
8511 TmpInst.addOperand(Inst.getOperand(2));
8513 TmpInst.addOperand(Inst.getOperand(2));
8514 TmpInst.addOperand(Inst.getOperand(1));
8516 TmpInst.addOperand(Inst.getOperand(3));
8517 TmpInst.addOperand(Inst.getOperand(4));
8527 unsigned ARMAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
8528 // 16-bit thumb arithmetic instructions either require or preclude the 'S'
8529 // suffix depending on whether they're in an IT block or not.
8530 unsigned Opc = Inst.getOpcode();
8531 const MCInstrDesc &MCID = MII.get(Opc);
8532 if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
8533 assert(MCID.hasOptionalDef() &&
8534 "optionally flag setting instruction missing optional def operand");
8535 assert(MCID.NumOperands == Inst.getNumOperands() &&
8536 "operand count mismatch!");
8537 // Find the optional-def operand (cc_out).
8540 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands;
8543 // If we're parsing Thumb1, reject it completely.
8544 if (isThumbOne() && Inst.getOperand(OpNo).getReg() != ARM::CPSR)
8545 return Match_MnemonicFail;
8546 // If we're parsing Thumb2, which form is legal depends on whether we're
8548 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
8550 return Match_RequiresITBlock;
8551 if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
8553 return Match_RequiresNotITBlock;
8555 // Some high-register supporting Thumb1 encodings only allow both registers
8556 // to be from r0-r7 when in Thumb2.
8557 else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
8558 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8559 isARMLowRegister(Inst.getOperand(2).getReg()))
8560 return Match_RequiresThumb2;
8561 // Others only require ARMv6 or later.
8562 else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
8563 isARMLowRegister(Inst.getOperand(0).getReg()) &&
8564 isARMLowRegister(Inst.getOperand(1).getReg()))
8565 return Match_RequiresV6;
8566 return Match_Success;
8570 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
8571 return true; // In an assembly source, no need to second-guess
8575 static const char *getSubtargetFeatureName(uint64_t Val);
8576 bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
8577 OperandVector &Operands,
8578 MCStreamer &Out, uint64_t &ErrorInfo,
8579 bool MatchingInlineAsm) {
8581 unsigned MatchResult;
8583 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
8585 switch (MatchResult) {
8587 // Context sensitive operand constraints aren't handled by the matcher,
8588 // so check them here.
8589 if (validateInstruction(Inst, Operands)) {
8590 // Still progress the IT block, otherwise one wrong condition causes
8591 // nasty cascading errors.
8592 forwardITPosition();
8596 { // processInstruction() updates inITBlock state, we need to save it away
8597 bool wasInITBlock = inITBlock();
8599 // Some instructions need post-processing to, for example, tweak which
8600 // encoding is selected. Loop on it while changes happen so the
8601 // individual transformations can chain off each other. E.g.,
8602 // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
8603 while (processInstruction(Inst, Operands, Out))
8606 // Only after the instruction is fully processed, we can validate it
8607 if (wasInITBlock && hasV8Ops() && isThumb() &&
8608 !isV8EligibleForIT(&Inst)) {
8609 Warning(IDLoc, "deprecated instruction in IT block");
8613 // Only move forward at the very end so that everything in validate
8614 // and process gets a consistent answer about whether we're in an IT
8616 forwardITPosition();
8618 // ITasm is an ARM mode pseudo-instruction that just sets the ITblock and
8619 // doesn't actually encode.
8620 if (Inst.getOpcode() == ARM::ITasm)
8624 Out.EmitInstruction(Inst, STI);
8626 case Match_MissingFeature: {
8627 assert(ErrorInfo && "Unknown missing feature!");
8628 // Special case the error message for the very common case where only
8629 // a single subtarget feature is missing (Thumb vs. ARM, e.g.).
8630 std::string Msg = "instruction requires:";
8632 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
8633 if (ErrorInfo & Mask) {
8635 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
8639 return Error(IDLoc, Msg);
8641 case Match_InvalidOperand: {
8642 SMLoc ErrorLoc = IDLoc;
8643 if (ErrorInfo != ~0ULL) {
8644 if (ErrorInfo >= Operands.size())
8645 return Error(IDLoc, "too few operands for instruction");
8647 ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8648 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8651 return Error(ErrorLoc, "invalid operand for instruction");
8653 case Match_MnemonicFail:
8654 return Error(IDLoc, "invalid instruction",
8655 ((ARMOperand &)*Operands[0]).getLocRange());
8656 case Match_RequiresNotITBlock:
8657 return Error(IDLoc, "flag setting instruction only valid outside IT block");
8658 case Match_RequiresITBlock:
8659 return Error(IDLoc, "instruction only valid inside IT block");
8660 case Match_RequiresV6:
8661 return Error(IDLoc, "instruction variant requires ARMv6 or later");
8662 case Match_RequiresThumb2:
8663 return Error(IDLoc, "instruction variant requires Thumb2");
8664 case Match_ImmRange0_15: {
8665 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8666 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8667 return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
8669 case Match_ImmRange0_239: {
8670 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
8671 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8672 return Error(ErrorLoc, "immediate operand must be in the range [0,239]");
8674 case Match_AlignedMemoryRequiresNone:
8675 case Match_DupAlignedMemoryRequiresNone:
8676 case Match_AlignedMemoryRequires16:
8677 case Match_DupAlignedMemoryRequires16:
8678 case Match_AlignedMemoryRequires32:
8679 case Match_DupAlignedMemoryRequires32:
8680 case Match_AlignedMemoryRequires64:
8681 case Match_DupAlignedMemoryRequires64:
8682 case Match_AlignedMemoryRequires64or128:
8683 case Match_DupAlignedMemoryRequires64or128:
8684 case Match_AlignedMemoryRequires64or128or256:
8686 SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getAlignmentLoc();
8687 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
8688 switch (MatchResult) {
8690 llvm_unreachable("Missing Match_Aligned type");
8691 case Match_AlignedMemoryRequiresNone:
8692 case Match_DupAlignedMemoryRequiresNone:
8693 return Error(ErrorLoc, "alignment must be omitted");
8694 case Match_AlignedMemoryRequires16:
8695 case Match_DupAlignedMemoryRequires16:
8696 return Error(ErrorLoc, "alignment must be 16 or omitted");
8697 case Match_AlignedMemoryRequires32:
8698 case Match_DupAlignedMemoryRequires32:
8699 return Error(ErrorLoc, "alignment must be 32 or omitted");
8700 case Match_AlignedMemoryRequires64:
8701 case Match_DupAlignedMemoryRequires64:
8702 return Error(ErrorLoc, "alignment must be 64 or omitted");
8703 case Match_AlignedMemoryRequires64or128:
8704 case Match_DupAlignedMemoryRequires64or128:
8705 return Error(ErrorLoc, "alignment must be 64, 128 or omitted");
8706 case Match_AlignedMemoryRequires64or128or256:
8707 return Error(ErrorLoc, "alignment must be 64, 128, 256 or omitted");
8712 llvm_unreachable("Implement any new match types added!");
8715 /// parseDirective parses the arm specific directives
8716 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
8717 const MCObjectFileInfo::Environment Format =
8718 getContext().getObjectFileInfo()->getObjectFileType();
8719 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8720 bool IsCOFF = Format == MCObjectFileInfo::IsCOFF;
8722 StringRef IDVal = DirectiveID.getIdentifier();
8723 if (IDVal == ".word")
8724 return parseLiteralValues(4, DirectiveID.getLoc());
8725 else if (IDVal == ".short" || IDVal == ".hword")
8726 return parseLiteralValues(2, DirectiveID.getLoc());
8727 else if (IDVal == ".thumb")
8728 return parseDirectiveThumb(DirectiveID.getLoc());
8729 else if (IDVal == ".arm")
8730 return parseDirectiveARM(DirectiveID.getLoc());
8731 else if (IDVal == ".thumb_func")
8732 return parseDirectiveThumbFunc(DirectiveID.getLoc());
8733 else if (IDVal == ".code")
8734 return parseDirectiveCode(DirectiveID.getLoc());
8735 else if (IDVal == ".syntax")
8736 return parseDirectiveSyntax(DirectiveID.getLoc());
8737 else if (IDVal == ".unreq")
8738 return parseDirectiveUnreq(DirectiveID.getLoc());
8739 else if (IDVal == ".fnend")
8740 return parseDirectiveFnEnd(DirectiveID.getLoc());
8741 else if (IDVal == ".cantunwind")
8742 return parseDirectiveCantUnwind(DirectiveID.getLoc());
8743 else if (IDVal == ".personality")
8744 return parseDirectivePersonality(DirectiveID.getLoc());
8745 else if (IDVal == ".handlerdata")
8746 return parseDirectiveHandlerData(DirectiveID.getLoc());
8747 else if (IDVal == ".setfp")
8748 return parseDirectiveSetFP(DirectiveID.getLoc());
8749 else if (IDVal == ".pad")
8750 return parseDirectivePad(DirectiveID.getLoc());
8751 else if (IDVal == ".save")
8752 return parseDirectiveRegSave(DirectiveID.getLoc(), false);
8753 else if (IDVal == ".vsave")
8754 return parseDirectiveRegSave(DirectiveID.getLoc(), true);
8755 else if (IDVal == ".ltorg" || IDVal == ".pool")
8756 return parseDirectiveLtorg(DirectiveID.getLoc());
8757 else if (IDVal == ".even")
8758 return parseDirectiveEven(DirectiveID.getLoc());
8759 else if (IDVal == ".personalityindex")
8760 return parseDirectivePersonalityIndex(DirectiveID.getLoc());
8761 else if (IDVal == ".unwind_raw")
8762 return parseDirectiveUnwindRaw(DirectiveID.getLoc());
8763 else if (IDVal == ".movsp")
8764 return parseDirectiveMovSP(DirectiveID.getLoc());
8765 else if (IDVal == ".arch_extension")
8766 return parseDirectiveArchExtension(DirectiveID.getLoc());
8767 else if (IDVal == ".align")
8768 return parseDirectiveAlign(DirectiveID.getLoc());
8769 else if (IDVal == ".thumb_set")
8770 return parseDirectiveThumbSet(DirectiveID.getLoc());
8772 if (!IsMachO && !IsCOFF) {
8773 if (IDVal == ".arch")
8774 return parseDirectiveArch(DirectiveID.getLoc());
8775 else if (IDVal == ".cpu")
8776 return parseDirectiveCPU(DirectiveID.getLoc());
8777 else if (IDVal == ".eabi_attribute")
8778 return parseDirectiveEabiAttr(DirectiveID.getLoc());
8779 else if (IDVal == ".fpu")
8780 return parseDirectiveFPU(DirectiveID.getLoc());
8781 else if (IDVal == ".fnstart")
8782 return parseDirectiveFnStart(DirectiveID.getLoc());
8783 else if (IDVal == ".inst")
8784 return parseDirectiveInst(DirectiveID.getLoc());
8785 else if (IDVal == ".inst.n")
8786 return parseDirectiveInst(DirectiveID.getLoc(), 'n');
8787 else if (IDVal == ".inst.w")
8788 return parseDirectiveInst(DirectiveID.getLoc(), 'w');
8789 else if (IDVal == ".object_arch")
8790 return parseDirectiveObjectArch(DirectiveID.getLoc());
8791 else if (IDVal == ".tlsdescseq")
8792 return parseDirectiveTLSDescSeq(DirectiveID.getLoc());
8798 /// parseLiteralValues
8799 /// ::= .hword expression [, expression]*
8800 /// ::= .short expression [, expression]*
8801 /// ::= .word expression [, expression]*
8802 bool ARMAsmParser::parseLiteralValues(unsigned Size, SMLoc L) {
8803 MCAsmParser &Parser = getParser();
8804 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8806 const MCExpr *Value;
8807 if (getParser().parseExpression(Value)) {
8808 Parser.eatToEndOfStatement();
8812 getParser().getStreamer().EmitValue(Value, Size);
8814 if (getLexer().is(AsmToken::EndOfStatement))
8817 // FIXME: Improve diagnostic.
8818 if (getLexer().isNot(AsmToken::Comma)) {
8819 Error(L, "unexpected token in directive");
8830 /// parseDirectiveThumb
8832 bool ARMAsmParser::parseDirectiveThumb(SMLoc L) {
8833 MCAsmParser &Parser = getParser();
8834 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8835 Error(L, "unexpected token in directive");
8841 Error(L, "target does not support Thumb mode");
8848 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8852 /// parseDirectiveARM
8854 bool ARMAsmParser::parseDirectiveARM(SMLoc L) {
8855 MCAsmParser &Parser = getParser();
8856 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8857 Error(L, "unexpected token in directive");
8863 Error(L, "target does not support ARM mode");
8870 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8874 void ARMAsmParser::onLabelParsed(MCSymbol *Symbol) {
8875 if (NextSymbolIsThumb) {
8876 getParser().getStreamer().EmitThumbFunc(Symbol);
8877 NextSymbolIsThumb = false;
8881 /// parseDirectiveThumbFunc
8882 /// ::= .thumbfunc symbol_name
8883 bool ARMAsmParser::parseDirectiveThumbFunc(SMLoc L) {
8884 MCAsmParser &Parser = getParser();
8885 const auto Format = getContext().getObjectFileInfo()->getObjectFileType();
8886 bool IsMachO = Format == MCObjectFileInfo::IsMachO;
8888 // Darwin asm has (optionally) function name after .thumb_func direction
8891 const AsmToken &Tok = Parser.getTok();
8892 if (Tok.isNot(AsmToken::EndOfStatement)) {
8893 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) {
8894 Error(L, "unexpected token in .thumb_func directive");
8899 getParser().getContext().GetOrCreateSymbol(Tok.getIdentifier());
8900 getParser().getStreamer().EmitThumbFunc(Func);
8901 Parser.Lex(); // Consume the identifier token.
8906 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8907 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8908 Parser.eatToEndOfStatement();
8912 NextSymbolIsThumb = true;
8916 /// parseDirectiveSyntax
8917 /// ::= .syntax unified | divided
8918 bool ARMAsmParser::parseDirectiveSyntax(SMLoc L) {
8919 MCAsmParser &Parser = getParser();
8920 const AsmToken &Tok = Parser.getTok();
8921 if (Tok.isNot(AsmToken::Identifier)) {
8922 Error(L, "unexpected token in .syntax directive");
8926 StringRef Mode = Tok.getString();
8927 if (Mode == "unified" || Mode == "UNIFIED") {
8929 } else if (Mode == "divided" || Mode == "DIVIDED") {
8930 Error(L, "'.syntax divided' arm asssembly not supported");
8933 Error(L, "unrecognized syntax mode in .syntax directive");
8937 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8938 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8943 // TODO tell the MC streamer the mode
8944 // getParser().getStreamer().Emit???();
8948 /// parseDirectiveCode
8949 /// ::= .code 16 | 32
8950 bool ARMAsmParser::parseDirectiveCode(SMLoc L) {
8951 MCAsmParser &Parser = getParser();
8952 const AsmToken &Tok = Parser.getTok();
8953 if (Tok.isNot(AsmToken::Integer)) {
8954 Error(L, "unexpected token in .code directive");
8957 int64_t Val = Parser.getTok().getIntVal();
8958 if (Val != 16 && Val != 32) {
8959 Error(L, "invalid operand to .code directive");
8964 if (getLexer().isNot(AsmToken::EndOfStatement)) {
8965 Error(Parser.getTok().getLoc(), "unexpected token in directive");
8972 Error(L, "target does not support Thumb mode");
8978 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
8981 Error(L, "target does not support ARM mode");
8987 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
8993 /// parseDirectiveReq
8994 /// ::= name .req registername
8995 bool ARMAsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
8996 MCAsmParser &Parser = getParser();
8997 Parser.Lex(); // Eat the '.req' token.
8999 SMLoc SRegLoc, ERegLoc;
9000 if (ParseRegister(Reg, SRegLoc, ERegLoc)) {
9001 Parser.eatToEndOfStatement();
9002 Error(SRegLoc, "register name expected");
9006 // Shouldn't be anything else.
9007 if (Parser.getTok().isNot(AsmToken::EndOfStatement)) {
9008 Parser.eatToEndOfStatement();
9009 Error(Parser.getTok().getLoc(), "unexpected input in .req directive.");
9013 Parser.Lex(); // Consume the EndOfStatement
9015 if (RegisterReqs.insert(std::make_pair(Name, Reg)).first->second != Reg) {
9016 Error(SRegLoc, "redefinition of '" + Name + "' does not match original.");
9023 /// parseDirectiveUneq
9024 /// ::= .unreq registername
9025 bool ARMAsmParser::parseDirectiveUnreq(SMLoc L) {
9026 MCAsmParser &Parser = getParser();
9027 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9028 Parser.eatToEndOfStatement();
9029 Error(L, "unexpected input in .unreq directive.");
9032 RegisterReqs.erase(Parser.getTok().getIdentifier().lower());
9033 Parser.Lex(); // Eat the identifier.
9037 /// parseDirectiveArch
9039 bool ARMAsmParser::parseDirectiveArch(SMLoc L) {
9040 StringRef Arch = getParser().parseStringToEndOfStatement().trim();
9042 unsigned ID = ARMTargetParser::parseArch(Arch);
9044 if (ID == ARM::AK_INVALID) {
9045 Error(L, "Unknown arch name");
9049 getTargetStreamer().emitArch(ID);
9053 /// parseDirectiveEabiAttr
9054 /// ::= .eabi_attribute int, int [, "str"]
9055 /// ::= .eabi_attribute Tag_name, int [, "str"]
9056 bool ARMAsmParser::parseDirectiveEabiAttr(SMLoc L) {
9057 MCAsmParser &Parser = getParser();
9060 TagLoc = Parser.getTok().getLoc();
9061 if (Parser.getTok().is(AsmToken::Identifier)) {
9062 StringRef Name = Parser.getTok().getIdentifier();
9063 Tag = ARMBuildAttrs::AttrTypeFromString(Name);
9065 Error(TagLoc, "attribute name not recognised: " + Name);
9066 Parser.eatToEndOfStatement();
9071 const MCExpr *AttrExpr;
9073 TagLoc = Parser.getTok().getLoc();
9074 if (Parser.parseExpression(AttrExpr)) {
9075 Parser.eatToEndOfStatement();
9079 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(AttrExpr);
9081 Error(TagLoc, "expected numeric constant");
9082 Parser.eatToEndOfStatement();
9086 Tag = CE->getValue();
9089 if (Parser.getTok().isNot(AsmToken::Comma)) {
9090 Error(Parser.getTok().getLoc(), "comma expected");
9091 Parser.eatToEndOfStatement();
9094 Parser.Lex(); // skip comma
9096 StringRef StringValue = "";
9097 bool IsStringValue = false;
9099 int64_t IntegerValue = 0;
9100 bool IsIntegerValue = false;
9102 if (Tag == ARMBuildAttrs::CPU_raw_name || Tag == ARMBuildAttrs::CPU_name)
9103 IsStringValue = true;
9104 else if (Tag == ARMBuildAttrs::compatibility) {
9105 IsStringValue = true;
9106 IsIntegerValue = true;
9107 } else if (Tag < 32 || Tag % 2 == 0)
9108 IsIntegerValue = true;
9109 else if (Tag % 2 == 1)
9110 IsStringValue = true;
9112 llvm_unreachable("invalid tag type");
9114 if (IsIntegerValue) {
9115 const MCExpr *ValueExpr;
9116 SMLoc ValueExprLoc = Parser.getTok().getLoc();
9117 if (Parser.parseExpression(ValueExpr)) {
9118 Parser.eatToEndOfStatement();
9122 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ValueExpr);
9124 Error(ValueExprLoc, "expected numeric constant");
9125 Parser.eatToEndOfStatement();
9129 IntegerValue = CE->getValue();
9132 if (Tag == ARMBuildAttrs::compatibility) {
9133 if (Parser.getTok().isNot(AsmToken::Comma))
9134 IsStringValue = false;
9135 if (Parser.getTok().isNot(AsmToken::Comma)) {
9136 Error(Parser.getTok().getLoc(), "comma expected");
9137 Parser.eatToEndOfStatement();
9144 if (IsStringValue) {
9145 if (Parser.getTok().isNot(AsmToken::String)) {
9146 Error(Parser.getTok().getLoc(), "bad string constant");
9147 Parser.eatToEndOfStatement();
9151 StringValue = Parser.getTok().getStringContents();
9155 if (IsIntegerValue && IsStringValue) {
9156 assert(Tag == ARMBuildAttrs::compatibility);
9157 getTargetStreamer().emitIntTextAttribute(Tag, IntegerValue, StringValue);
9158 } else if (IsIntegerValue)
9159 getTargetStreamer().emitAttribute(Tag, IntegerValue);
9160 else if (IsStringValue)
9161 getTargetStreamer().emitTextAttribute(Tag, StringValue);
9165 /// parseDirectiveCPU
9167 bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
9168 StringRef CPU = getParser().parseStringToEndOfStatement().trim();
9169 getTargetStreamer().emitTextAttribute(ARMBuildAttrs::CPU_name, CPU);
9171 if (!STI.isCPUStringValid(CPU)) {
9172 Error(L, "Unknown CPU name");
9176 // FIXME: This switches the CPU features globally, therefore it might
9177 // happen that code you would not expect to assemble will. For details
9178 // see: http://llvm.org/bugs/show_bug.cgi?id=20757
9179 STI.InitMCProcessorInfo(CPU, "");
9180 STI.InitCPUSchedModel(CPU);
9181 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
9186 // FIXME: This is duplicated in getARMFPUFeatures() in
9187 // tools/clang/lib/Driver/Tools.cpp
9188 static const struct {
9190 const uint64_t Enabled;
9191 const uint64_t Disabled;
9193 {/* ID */ ARM::FK_VFP,
9194 /* Enabled */ ARM::FeatureVFP2,
9195 /* Disabled */ ARM::FeatureNEON},
9196 {/* ID */ ARM::FK_VFPV2,
9197 /* Enabled */ ARM::FeatureVFP2,
9198 /* Disabled */ ARM::FeatureNEON},
9199 {/* ID */ ARM::FK_VFPV3,
9200 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3,
9201 /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
9202 {/* ID */ ARM::FK_VFPV3_D16,
9203 /* Enable */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureD16,
9204 /* Disabled */ ARM::FeatureNEON},
9205 {/* ID */ ARM::FK_VFPV4,
9206 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4,
9207 /* Disabled */ ARM::FeatureNEON | ARM::FeatureD16},
9208 {/* ID */ ARM::FK_VFPV4_D16,
9209 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9211 /* Disabled */ ARM::FeatureNEON},
9212 {/* ID */ ARM::FK_FPV5_D16,
9213 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9214 ARM::FeatureFPARMv8 | ARM::FeatureD16,
9215 /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto},
9216 {/* ID */ ARM::FK_FP_ARMV8,
9217 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9218 ARM::FeatureFPARMv8,
9219 /* Disabled */ ARM::FeatureNEON | ARM::FeatureCrypto | ARM::FeatureD16},
9220 {/* ID */ ARM::FK_NEON,
9221 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureNEON,
9222 /* Disabled */ ARM::FeatureD16},
9223 {/* ID */ ARM::FK_NEON_VFPV4,
9224 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9226 /* Disabled */ ARM::FeatureD16},
9227 {/* ID */ ARM::FK_NEON_FP_ARMV8,
9228 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9229 ARM::FeatureFPARMv8 | ARM::FeatureNEON,
9230 /* Disabled */ ARM::FeatureCrypto | ARM::FeatureD16},
9231 {/* ID */ ARM::FK_CRYPTO_NEON_FP_ARMV8,
9232 /* Enabled */ ARM::FeatureVFP2 | ARM::FeatureVFP3 | ARM::FeatureVFP4 |
9233 ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto,
9234 /* Disabled */ ARM::FeatureD16},
9235 {ARM::FK_SOFTVFP, 0, 0},
9238 /// parseDirectiveFPU
9240 bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
9241 SMLoc FPUNameLoc = getTok().getLoc();
9242 StringRef FPU = getParser().parseStringToEndOfStatement().trim();
9244 unsigned ID = ARMTargetParser::parseFPU(FPU);
9246 if (ID == ARM::FK_INVALID) {
9247 Error(FPUNameLoc, "Unknown FPU name");
9251 for (const auto &Entry : FPUs) {
9255 // Need to toggle features that should be on but are off and that
9256 // should off but are on.
9257 uint64_t Toggle = (Entry.Enabled & ~STI.getFeatureBits()) |
9258 (Entry.Disabled & STI.getFeatureBits());
9259 setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
9263 getTargetStreamer().emitFPU(ID);
9267 /// parseDirectiveFnStart
9269 bool ARMAsmParser::parseDirectiveFnStart(SMLoc L) {
9270 if (UC.hasFnStart()) {
9271 Error(L, ".fnstart starts before the end of previous one");
9272 UC.emitFnStartLocNotes();
9276 // Reset the unwind directives parser state
9279 getTargetStreamer().emitFnStart();
9281 UC.recordFnStart(L);
9285 /// parseDirectiveFnEnd
9287 bool ARMAsmParser::parseDirectiveFnEnd(SMLoc L) {
9288 // Check the ordering of unwind directives
9289 if (!UC.hasFnStart()) {
9290 Error(L, ".fnstart must precede .fnend directive");
9294 // Reset the unwind directives parser state
9295 getTargetStreamer().emitFnEnd();
9301 /// parseDirectiveCantUnwind
9303 bool ARMAsmParser::parseDirectiveCantUnwind(SMLoc L) {
9304 UC.recordCantUnwind(L);
9306 // Check the ordering of unwind directives
9307 if (!UC.hasFnStart()) {
9308 Error(L, ".fnstart must precede .cantunwind directive");
9311 if (UC.hasHandlerData()) {
9312 Error(L, ".cantunwind can't be used with .handlerdata directive");
9313 UC.emitHandlerDataLocNotes();
9316 if (UC.hasPersonality()) {
9317 Error(L, ".cantunwind can't be used with .personality directive");
9318 UC.emitPersonalityLocNotes();
9322 getTargetStreamer().emitCantUnwind();
9326 /// parseDirectivePersonality
9327 /// ::= .personality name
9328 bool ARMAsmParser::parseDirectivePersonality(SMLoc L) {
9329 MCAsmParser &Parser = getParser();
9330 bool HasExistingPersonality = UC.hasPersonality();
9332 UC.recordPersonality(L);
9334 // Check the ordering of unwind directives
9335 if (!UC.hasFnStart()) {
9336 Error(L, ".fnstart must precede .personality directive");
9339 if (UC.cantUnwind()) {
9340 Error(L, ".personality can't be used with .cantunwind directive");
9341 UC.emitCantUnwindLocNotes();
9344 if (UC.hasHandlerData()) {
9345 Error(L, ".personality must precede .handlerdata directive");
9346 UC.emitHandlerDataLocNotes();
9349 if (HasExistingPersonality) {
9350 Parser.eatToEndOfStatement();
9351 Error(L, "multiple personality directives");
9352 UC.emitPersonalityLocNotes();
9356 // Parse the name of the personality routine
9357 if (Parser.getTok().isNot(AsmToken::Identifier)) {
9358 Parser.eatToEndOfStatement();
9359 Error(L, "unexpected input in .personality directive.");
9362 StringRef Name(Parser.getTok().getIdentifier());
9365 MCSymbol *PR = getParser().getContext().GetOrCreateSymbol(Name);
9366 getTargetStreamer().emitPersonality(PR);
9370 /// parseDirectiveHandlerData
9371 /// ::= .handlerdata
9372 bool ARMAsmParser::parseDirectiveHandlerData(SMLoc L) {
9373 UC.recordHandlerData(L);
9375 // Check the ordering of unwind directives
9376 if (!UC.hasFnStart()) {
9377 Error(L, ".fnstart must precede .personality directive");
9380 if (UC.cantUnwind()) {
9381 Error(L, ".handlerdata can't be used with .cantunwind directive");
9382 UC.emitCantUnwindLocNotes();
9386 getTargetStreamer().emitHandlerData();
9390 /// parseDirectiveSetFP
9391 /// ::= .setfp fpreg, spreg [, offset]
9392 bool ARMAsmParser::parseDirectiveSetFP(SMLoc L) {
9393 MCAsmParser &Parser = getParser();
9394 // Check the ordering of unwind directives
9395 if (!UC.hasFnStart()) {
9396 Error(L, ".fnstart must precede .setfp directive");
9399 if (UC.hasHandlerData()) {
9400 Error(L, ".setfp must precede .handlerdata directive");
9405 SMLoc FPRegLoc = Parser.getTok().getLoc();
9406 int FPReg = tryParseRegister();
9408 Error(FPRegLoc, "frame pointer register expected");
9413 if (Parser.getTok().isNot(AsmToken::Comma)) {
9414 Error(Parser.getTok().getLoc(), "comma expected");
9417 Parser.Lex(); // skip comma
9420 SMLoc SPRegLoc = Parser.getTok().getLoc();
9421 int SPReg = tryParseRegister();
9423 Error(SPRegLoc, "stack pointer register expected");
9427 if (SPReg != ARM::SP && SPReg != UC.getFPReg()) {
9428 Error(SPRegLoc, "register should be either $sp or the latest fp register");
9432 // Update the frame pointer register
9433 UC.saveFPReg(FPReg);
9437 if (Parser.getTok().is(AsmToken::Comma)) {
9438 Parser.Lex(); // skip comma
9440 if (Parser.getTok().isNot(AsmToken::Hash) &&
9441 Parser.getTok().isNot(AsmToken::Dollar)) {
9442 Error(Parser.getTok().getLoc(), "'#' expected");
9445 Parser.Lex(); // skip hash token.
9447 const MCExpr *OffsetExpr;
9448 SMLoc ExLoc = Parser.getTok().getLoc();
9450 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9451 Error(ExLoc, "malformed setfp offset");
9454 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9456 Error(ExLoc, "setfp offset must be an immediate");
9460 Offset = CE->getValue();
9463 getTargetStreamer().emitSetFP(static_cast<unsigned>(FPReg),
9464 static_cast<unsigned>(SPReg), Offset);
9470 bool ARMAsmParser::parseDirectivePad(SMLoc L) {
9471 MCAsmParser &Parser = getParser();
9472 // Check the ordering of unwind directives
9473 if (!UC.hasFnStart()) {
9474 Error(L, ".fnstart must precede .pad directive");
9477 if (UC.hasHandlerData()) {
9478 Error(L, ".pad must precede .handlerdata directive");
9483 if (Parser.getTok().isNot(AsmToken::Hash) &&
9484 Parser.getTok().isNot(AsmToken::Dollar)) {
9485 Error(Parser.getTok().getLoc(), "'#' expected");
9488 Parser.Lex(); // skip hash token.
9490 const MCExpr *OffsetExpr;
9491 SMLoc ExLoc = Parser.getTok().getLoc();
9493 if (getParser().parseExpression(OffsetExpr, EndLoc)) {
9494 Error(ExLoc, "malformed pad offset");
9497 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9499 Error(ExLoc, "pad offset must be an immediate");
9503 getTargetStreamer().emitPad(CE->getValue());
9507 /// parseDirectiveRegSave
9508 /// ::= .save { registers }
9509 /// ::= .vsave { registers }
9510 bool ARMAsmParser::parseDirectiveRegSave(SMLoc L, bool IsVector) {
9511 // Check the ordering of unwind directives
9512 if (!UC.hasFnStart()) {
9513 Error(L, ".fnstart must precede .save or .vsave directives");
9516 if (UC.hasHandlerData()) {
9517 Error(L, ".save or .vsave must precede .handlerdata directive");
9521 // RAII object to make sure parsed operands are deleted.
9522 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> Operands;
9524 // Parse the register list
9525 if (parseRegisterList(Operands))
9527 ARMOperand &Op = (ARMOperand &)*Operands[0];
9528 if (!IsVector && !Op.isRegList()) {
9529 Error(L, ".save expects GPR registers");
9532 if (IsVector && !Op.isDPRRegList()) {
9533 Error(L, ".vsave expects DPR registers");
9537 getTargetStreamer().emitRegSave(Op.getRegList(), IsVector);
9541 /// parseDirectiveInst
9542 /// ::= .inst opcode [, ...]
9543 /// ::= .inst.n opcode [, ...]
9544 /// ::= .inst.w opcode [, ...]
9545 bool ARMAsmParser::parseDirectiveInst(SMLoc Loc, char Suffix) {
9546 MCAsmParser &Parser = getParser();
9558 Parser.eatToEndOfStatement();
9559 Error(Loc, "cannot determine Thumb instruction size, "
9560 "use inst.n/inst.w instead");
9565 Parser.eatToEndOfStatement();
9566 Error(Loc, "width suffixes are invalid in ARM mode");
9572 if (getLexer().is(AsmToken::EndOfStatement)) {
9573 Parser.eatToEndOfStatement();
9574 Error(Loc, "expected expression following directive");
9581 if (getParser().parseExpression(Expr)) {
9582 Error(Loc, "expected expression");
9586 const MCConstantExpr *Value = dyn_cast_or_null<MCConstantExpr>(Expr);
9588 Error(Loc, "expected constant expression");
9594 if (Value->getValue() > 0xffff) {
9595 Error(Loc, "inst.n operand is too big, use inst.w instead");
9600 if (Value->getValue() > 0xffffffff) {
9602 StringRef(Suffix ? "inst.w" : "inst") + " operand is too big");
9607 llvm_unreachable("only supported widths are 2 and 4");
9610 getTargetStreamer().emitInst(Value->getValue(), Suffix);
9612 if (getLexer().is(AsmToken::EndOfStatement))
9615 if (getLexer().isNot(AsmToken::Comma)) {
9616 Error(Loc, "unexpected token in directive");
9627 /// parseDirectiveLtorg
9628 /// ::= .ltorg | .pool
9629 bool ARMAsmParser::parseDirectiveLtorg(SMLoc L) {
9630 getTargetStreamer().emitCurrentConstantPool();
9634 bool ARMAsmParser::parseDirectiveEven(SMLoc L) {
9635 const MCSection *Section = getStreamer().getCurrentSection().first;
9637 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9638 TokError("unexpected token in directive");
9643 getStreamer().InitSections(false);
9644 Section = getStreamer().getCurrentSection().first;
9647 assert(Section && "must have section to emit alignment");
9648 if (Section->UseCodeAlign())
9649 getStreamer().EmitCodeAlignment(2);
9651 getStreamer().EmitValueToAlignment(2);
9656 /// parseDirectivePersonalityIndex
9657 /// ::= .personalityindex index
9658 bool ARMAsmParser::parseDirectivePersonalityIndex(SMLoc L) {
9659 MCAsmParser &Parser = getParser();
9660 bool HasExistingPersonality = UC.hasPersonality();
9662 UC.recordPersonalityIndex(L);
9664 if (!UC.hasFnStart()) {
9665 Parser.eatToEndOfStatement();
9666 Error(L, ".fnstart must precede .personalityindex directive");
9669 if (UC.cantUnwind()) {
9670 Parser.eatToEndOfStatement();
9671 Error(L, ".personalityindex cannot be used with .cantunwind");
9672 UC.emitCantUnwindLocNotes();
9675 if (UC.hasHandlerData()) {
9676 Parser.eatToEndOfStatement();
9677 Error(L, ".personalityindex must precede .handlerdata directive");
9678 UC.emitHandlerDataLocNotes();
9681 if (HasExistingPersonality) {
9682 Parser.eatToEndOfStatement();
9683 Error(L, "multiple personality directives");
9684 UC.emitPersonalityLocNotes();
9688 const MCExpr *IndexExpression;
9689 SMLoc IndexLoc = Parser.getTok().getLoc();
9690 if (Parser.parseExpression(IndexExpression)) {
9691 Parser.eatToEndOfStatement();
9695 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(IndexExpression);
9697 Parser.eatToEndOfStatement();
9698 Error(IndexLoc, "index must be a constant number");
9701 if (CE->getValue() < 0 ||
9702 CE->getValue() >= ARM::EHABI::NUM_PERSONALITY_INDEX) {
9703 Parser.eatToEndOfStatement();
9704 Error(IndexLoc, "personality routine index should be in range [0-3]");
9708 getTargetStreamer().emitPersonalityIndex(CE->getValue());
9712 /// parseDirectiveUnwindRaw
9713 /// ::= .unwind_raw offset, opcode [, opcode...]
9714 bool ARMAsmParser::parseDirectiveUnwindRaw(SMLoc L) {
9715 MCAsmParser &Parser = getParser();
9716 if (!UC.hasFnStart()) {
9717 Parser.eatToEndOfStatement();
9718 Error(L, ".fnstart must precede .unwind_raw directives");
9722 int64_t StackOffset;
9724 const MCExpr *OffsetExpr;
9725 SMLoc OffsetLoc = getLexer().getLoc();
9726 if (getLexer().is(AsmToken::EndOfStatement) ||
9727 getParser().parseExpression(OffsetExpr)) {
9728 Error(OffsetLoc, "expected expression");
9729 Parser.eatToEndOfStatement();
9733 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9735 Error(OffsetLoc, "offset must be a constant");
9736 Parser.eatToEndOfStatement();
9740 StackOffset = CE->getValue();
9742 if (getLexer().isNot(AsmToken::Comma)) {
9743 Error(getLexer().getLoc(), "expected comma");
9744 Parser.eatToEndOfStatement();
9749 SmallVector<uint8_t, 16> Opcodes;
9753 SMLoc OpcodeLoc = getLexer().getLoc();
9754 if (getLexer().is(AsmToken::EndOfStatement) || Parser.parseExpression(OE)) {
9755 Error(OpcodeLoc, "expected opcode expression");
9756 Parser.eatToEndOfStatement();
9760 const MCConstantExpr *OC = dyn_cast<MCConstantExpr>(OE);
9762 Error(OpcodeLoc, "opcode value must be a constant");
9763 Parser.eatToEndOfStatement();
9767 const int64_t Opcode = OC->getValue();
9768 if (Opcode & ~0xff) {
9769 Error(OpcodeLoc, "invalid opcode");
9770 Parser.eatToEndOfStatement();
9774 Opcodes.push_back(uint8_t(Opcode));
9776 if (getLexer().is(AsmToken::EndOfStatement))
9779 if (getLexer().isNot(AsmToken::Comma)) {
9780 Error(getLexer().getLoc(), "unexpected token in directive");
9781 Parser.eatToEndOfStatement();
9788 getTargetStreamer().emitUnwindRaw(StackOffset, Opcodes);
9794 /// parseDirectiveTLSDescSeq
9795 /// ::= .tlsdescseq tls-variable
9796 bool ARMAsmParser::parseDirectiveTLSDescSeq(SMLoc L) {
9797 MCAsmParser &Parser = getParser();
9799 if (getLexer().isNot(AsmToken::Identifier)) {
9800 TokError("expected variable after '.tlsdescseq' directive");
9801 Parser.eatToEndOfStatement();
9805 const MCSymbolRefExpr *SRE =
9806 MCSymbolRefExpr::Create(Parser.getTok().getIdentifier(),
9807 MCSymbolRefExpr::VK_ARM_TLSDESCSEQ, getContext());
9810 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9811 Error(Parser.getTok().getLoc(), "unexpected token");
9812 Parser.eatToEndOfStatement();
9816 getTargetStreamer().AnnotateTLSDescriptorSequence(SRE);
9820 /// parseDirectiveMovSP
9821 /// ::= .movsp reg [, #offset]
9822 bool ARMAsmParser::parseDirectiveMovSP(SMLoc L) {
9823 MCAsmParser &Parser = getParser();
9824 if (!UC.hasFnStart()) {
9825 Parser.eatToEndOfStatement();
9826 Error(L, ".fnstart must precede .movsp directives");
9829 if (UC.getFPReg() != ARM::SP) {
9830 Parser.eatToEndOfStatement();
9831 Error(L, "unexpected .movsp directive");
9835 SMLoc SPRegLoc = Parser.getTok().getLoc();
9836 int SPReg = tryParseRegister();
9838 Parser.eatToEndOfStatement();
9839 Error(SPRegLoc, "register expected");
9843 if (SPReg == ARM::SP || SPReg == ARM::PC) {
9844 Parser.eatToEndOfStatement();
9845 Error(SPRegLoc, "sp and pc are not permitted in .movsp directive");
9850 if (Parser.getTok().is(AsmToken::Comma)) {
9853 if (Parser.getTok().isNot(AsmToken::Hash)) {
9854 Error(Parser.getTok().getLoc(), "expected #constant");
9855 Parser.eatToEndOfStatement();
9860 const MCExpr *OffsetExpr;
9861 SMLoc OffsetLoc = Parser.getTok().getLoc();
9862 if (Parser.parseExpression(OffsetExpr)) {
9863 Parser.eatToEndOfStatement();
9864 Error(OffsetLoc, "malformed offset expression");
9868 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(OffsetExpr);
9870 Parser.eatToEndOfStatement();
9871 Error(OffsetLoc, "offset must be an immediate constant");
9875 Offset = CE->getValue();
9878 getTargetStreamer().emitMovSP(SPReg, Offset);
9879 UC.saveFPReg(SPReg);
9884 /// parseDirectiveObjectArch
9885 /// ::= .object_arch name
9886 bool ARMAsmParser::parseDirectiveObjectArch(SMLoc L) {
9887 MCAsmParser &Parser = getParser();
9888 if (getLexer().isNot(AsmToken::Identifier)) {
9889 Error(getLexer().getLoc(), "unexpected token");
9890 Parser.eatToEndOfStatement();
9894 StringRef Arch = Parser.getTok().getString();
9895 SMLoc ArchLoc = Parser.getTok().getLoc();
9898 unsigned ID = ARMTargetParser::parseArch(Arch);
9900 if (ID == ARM::AK_INVALID) {
9901 Error(ArchLoc, "unknown architecture '" + Arch + "'");
9902 Parser.eatToEndOfStatement();
9906 getTargetStreamer().emitObjectArch(ID);
9908 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9909 Error(getLexer().getLoc(), "unexpected token");
9910 Parser.eatToEndOfStatement();
9916 /// parseDirectiveAlign
9918 bool ARMAsmParser::parseDirectiveAlign(SMLoc L) {
9919 // NOTE: if this is not the end of the statement, fall back to the target
9920 // agnostic handling for this directive which will correctly handle this.
9921 if (getLexer().isNot(AsmToken::EndOfStatement))
9924 // '.align' is target specifically handled to mean 2**2 byte alignment.
9925 if (getStreamer().getCurrentSection().first->UseCodeAlign())
9926 getStreamer().EmitCodeAlignment(4, 0);
9928 getStreamer().EmitValueToAlignment(4, 0, 1, 0);
9933 /// parseDirectiveThumbSet
9934 /// ::= .thumb_set name, value
9935 bool ARMAsmParser::parseDirectiveThumbSet(SMLoc L) {
9936 MCAsmParser &Parser = getParser();
9939 if (Parser.parseIdentifier(Name)) {
9940 TokError("expected identifier after '.thumb_set'");
9941 Parser.eatToEndOfStatement();
9945 if (getLexer().isNot(AsmToken::Comma)) {
9946 TokError("expected comma after name '" + Name + "'");
9947 Parser.eatToEndOfStatement();
9952 const MCExpr *Value;
9953 if (Parser.parseExpression(Value)) {
9954 TokError("missing expression");
9955 Parser.eatToEndOfStatement();
9959 if (getLexer().isNot(AsmToken::EndOfStatement)) {
9960 TokError("unexpected token");
9961 Parser.eatToEndOfStatement();
9966 MCSymbol *Alias = getContext().GetOrCreateSymbol(Name);
9967 getTargetStreamer().emitThumbSet(Alias, Value);
9971 /// Force static initialization.
9972 extern "C" void LLVMInitializeARMAsmParser() {
9973 RegisterMCAsmParser<ARMAsmParser> X(TheARMLETarget);
9974 RegisterMCAsmParser<ARMAsmParser> Y(TheARMBETarget);
9975 RegisterMCAsmParser<ARMAsmParser> A(TheThumbLETarget);
9976 RegisterMCAsmParser<ARMAsmParser> B(TheThumbBETarget);
9979 #define GET_REGISTER_MATCHER
9980 #define GET_SUBTARGET_FEATURE_NAME
9981 #define GET_MATCHER_IMPLEMENTATION
9982 #include "ARMGenAsmMatcher.inc"
9984 static const struct {
9986 const unsigned ArchCheck;
9987 const uint64_t Features;
9989 { "crc", Feature_HasV8, ARM::FeatureCRC },
9990 { "crypto", Feature_HasV8,
9991 ARM::FeatureCrypto | ARM::FeatureNEON | ARM::FeatureFPARMv8 },
9992 { "fp", Feature_HasV8, ARM::FeatureFPARMv8 },
9993 { "idiv", Feature_HasV7 | Feature_IsNotMClass,
9994 ARM::FeatureHWDiv | ARM::FeatureHWDivARM },
9995 // FIXME: iWMMXT not supported
9996 { "iwmmxt", Feature_None, 0 },
9997 // FIXME: iWMMXT2 not supported
9998 { "iwmmxt2", Feature_None, 0 },
9999 // FIXME: Maverick not supported
10000 { "maverick", Feature_None, 0 },
10001 { "mp", Feature_HasV7 | Feature_IsNotMClass, ARM::FeatureMP },
10002 // FIXME: ARMv6-m OS Extensions feature not checked
10003 { "os", Feature_None, 0 },
10004 // FIXME: Also available in ARMv6-K
10005 { "sec", Feature_HasV7, ARM::FeatureTrustZone },
10006 { "simd", Feature_HasV8, ARM::FeatureNEON | ARM::FeatureFPARMv8 },
10007 // FIXME: Only available in A-class, isel not predicated
10008 { "virt", Feature_HasV7, ARM::FeatureVirtualization },
10009 // FIXME: xscale not supported
10010 { "xscale", Feature_None, 0 },
10013 /// parseDirectiveArchExtension
10014 /// ::= .arch_extension [no]feature
10015 bool ARMAsmParser::parseDirectiveArchExtension(SMLoc L) {
10016 MCAsmParser &Parser = getParser();
10018 if (getLexer().isNot(AsmToken::Identifier)) {
10019 Error(getLexer().getLoc(), "unexpected token");
10020 Parser.eatToEndOfStatement();
10024 StringRef Name = Parser.getTok().getString();
10025 SMLoc ExtLoc = Parser.getTok().getLoc();
10028 bool EnableFeature = true;
10029 if (Name.startswith_lower("no")) {
10030 EnableFeature = false;
10031 Name = Name.substr(2);
10034 for (const auto &Extension : Extensions) {
10035 if (Extension.Name != Name)
10038 if (!Extension.Features)
10039 report_fatal_error("unsupported architectural extension: " + Name);
10041 if ((getAvailableFeatures() & Extension.ArchCheck) != Extension.ArchCheck) {
10042 Error(ExtLoc, "architectural extension '" + Name + "' is not "
10043 "allowed for the current base architecture");
10047 uint64_t ToggleFeatures = EnableFeature
10048 ? (~STI.getFeatureBits() & Extension.Features)
10049 : ( STI.getFeatureBits() & Extension.Features);
10050 uint64_t Features =
10051 ComputeAvailableFeatures(STI.ToggleFeature(ToggleFeatures));
10052 setAvailableFeatures(Features);
10056 Error(ExtLoc, "unknown architectural extension: " + Name);
10057 Parser.eatToEndOfStatement();
10061 // Define this matcher function after the auto-generated include so we
10062 // have the match class enum definitions.
10063 unsigned ARMAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
10065 ARMOperand &Op = static_cast<ARMOperand &>(AsmOp);
10066 // If the kind is a token for a literal immediate, check if our asm
10067 // operand matches. This is for InstAliases which have a fixed-value
10068 // immediate in the syntax.
10073 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Op.getImm()))
10074 if (CE->getValue() == 0)
10075 return Match_Success;
10079 const MCExpr *SOExpr = Op.getImm();
10081 if (!SOExpr->EvaluateAsAbsolute(Value))
10082 return Match_Success;
10083 assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
10084 "expression value must be representable in 32 bits");
10089 MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
10090 return Match_Success;
10093 return Match_InvalidOperand;