1 //===-- ARMAsmParser.cpp - Parse ARM assembly to MCInst instructions ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "llvm/MC/MCParser/MCAsmLexer.h"
12 #include "llvm/MC/MCParser/MCAsmParser.h"
13 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
14 #include "llvm/MC/MCStreamer.h"
15 #include "llvm/MC/MCExpr.h"
16 #include "llvm/MC/MCInst.h"
17 #include "llvm/Target/TargetRegistry.h"
18 #include "llvm/Target/TargetAsmParser.h"
19 #include "llvm/Support/Compiler.h"
20 #include "llvm/Support/SourceMgr.h"
21 #include "llvm/ADT/OwningPtr.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/Twine.h"
29 // The shift types for register controlled shifts in arm memory addressing
38 class ARMAsmParser : public TargetAsmParser {
42 MCAsmParser &getParser() const { return Parser; }
44 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
46 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
48 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
50 bool MaybeParseRegister(OwningPtr<ARMOperand> &Op, bool ParseWriteBack);
52 bool ParseRegisterList(OwningPtr<ARMOperand> &Op);
54 bool ParseMemory(OwningPtr<ARMOperand> &Op);
56 bool ParseMemoryOffsetReg(bool &Negative,
57 bool &OffsetRegShifted,
58 enum ShiftType &ShiftType,
59 const MCExpr *&ShiftAmount,
60 const MCExpr *&Offset,
65 bool ParseShift(enum ShiftType &St, const MCExpr *&ShiftAmount, SMLoc &E);
67 bool ParseOperand(OwningPtr<ARMOperand> &Op);
69 bool ParseDirectiveWord(unsigned Size, SMLoc L);
71 bool ParseDirectiveThumb(SMLoc L);
73 bool ParseDirectiveThumbFunc(SMLoc L);
75 bool ParseDirectiveCode(SMLoc L);
77 bool ParseDirectiveSyntax(SMLoc L);
79 // TODO - For now hacked versions of the next two are in here in this file to
80 // allow some parser testing until the table gen versions are implemented.
82 /// @name Auto-generated Match Functions
84 bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
87 /// MatchRegisterName - Match the given string to a register name and return
88 /// its register number, or -1 if there is no match. To allow return values
89 /// to be used directly in register lists, arm registers have values between
91 int MatchRegisterName(StringRef Name);
97 ARMAsmParser(const Target &T, MCAsmParser &_Parser)
98 : TargetAsmParser(T), Parser(_Parser) {}
100 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
101 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
103 virtual bool ParseDirective(AsmToken DirectiveID);
106 /// ARMOperand - Instances of this class represent a parsed ARM machine
108 struct ARMOperand : public MCParsedAsmOperand {
119 SMLoc StartLoc, EndLoc;
136 // This is for all forms of ARM address expressions
139 unsigned OffsetRegNum; // used when OffsetIsReg is true
140 const MCExpr *Offset; // used when OffsetIsReg is false
141 const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
142 enum ShiftType ShiftType; // used when OffsetRegShifted is true
144 OffsetRegShifted : 1, // only used when OffsetIsReg is true
148 Negative : 1, // only used when OffsetIsReg is true
154 ARMOperand(KindTy K, SMLoc S, SMLoc E)
155 : Kind(K), StartLoc(S), EndLoc(E) {}
157 ARMOperand(const ARMOperand &o) : MCParsedAsmOperand() {
159 StartLoc = o.StartLoc;
177 /// getStartLoc - Get the location of the first token of this operand.
178 SMLoc getStartLoc() const { return StartLoc; }
179 /// getEndLoc - Get the location of the last token of this operand.
180 SMLoc getEndLoc() const { return EndLoc; }
182 StringRef getToken() const {
183 assert(Kind == Token && "Invalid access!");
184 return StringRef(Tok.Data, Tok.Length);
187 unsigned getReg() const {
188 assert(Kind == Register && "Invalid access!");
192 const MCExpr *getImm() const {
193 assert(Kind == Immediate && "Invalid access!");
197 bool isToken() const {return Kind == Token; }
199 bool isReg() const { return Kind == Register; }
201 void addRegOperands(MCInst &Inst, unsigned N) const {
202 assert(N == 1 && "Invalid number of operands!");
203 Inst.addOperand(MCOperand::CreateReg(getReg()));
206 static void CreateToken(OwningPtr<ARMOperand> &Op, StringRef Str,
208 Op.reset(new ARMOperand);
210 Op->Tok.Data = Str.data();
211 Op->Tok.Length = Str.size();
216 static void CreateReg(OwningPtr<ARMOperand> &Op, unsigned RegNum,
217 bool Writeback, SMLoc S, SMLoc E) {
218 Op.reset(new ARMOperand);
220 Op->Reg.RegNum = RegNum;
221 Op->Reg.Writeback = Writeback;
227 static void CreateImm(OwningPtr<ARMOperand> &Op, const MCExpr *Val,
229 Op.reset(new ARMOperand);
230 Op->Kind = Immediate;
237 static void CreateMem(OwningPtr<ARMOperand> &Op,
238 unsigned BaseRegNum, bool OffsetIsReg,
239 const MCExpr *Offset, unsigned OffsetRegNum,
240 bool OffsetRegShifted, enum ShiftType ShiftType,
241 const MCExpr *ShiftAmount, bool Preindexed,
242 bool Postindexed, bool Negative, bool Writeback,
244 Op.reset(new ARMOperand);
246 Op->Mem.BaseRegNum = BaseRegNum;
247 Op->Mem.OffsetIsReg = OffsetIsReg;
248 Op->Mem.Offset = Offset;
249 Op->Mem.OffsetRegNum = OffsetRegNum;
250 Op->Mem.OffsetRegShifted = OffsetRegShifted;
251 Op->Mem.ShiftType = ShiftType;
252 Op->Mem.ShiftAmount = ShiftAmount;
253 Op->Mem.Preindexed = Preindexed;
254 Op->Mem.Postindexed = Postindexed;
255 Op->Mem.Negative = Negative;
256 Op->Mem.Writeback = Writeback;
263 } // end anonymous namespace.
265 /// Try to parse a register name. The token must be an Identifier when called,
266 /// and if it is a register name a Reg operand is created, the token is eaten
267 /// and false is returned. Else true is returned and no token is eaten.
268 /// TODO this is likely to change to allow different register types and or to
269 /// parse for a specific register type.
270 bool ARMAsmParser::MaybeParseRegister
271 (OwningPtr<ARMOperand> &Op, bool ParseWriteBack) {
273 const AsmToken &Tok = Parser.getTok();
274 assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
276 // FIXME: Validate register for the current architecture; we have to do
277 // validation later, so maybe there is no need for this here.
280 RegNum = MatchRegisterName(Tok.getString());
286 Parser.Lex(); // Eat identifier token.
288 E = Parser.getTok().getLoc();
290 bool Writeback = false;
291 if (ParseWriteBack) {
292 const AsmToken &ExclaimTok = Parser.getTok();
293 if (ExclaimTok.is(AsmToken::Exclaim)) {
294 E = ExclaimTok.getLoc();
296 Parser.Lex(); // Eat exclaim token
300 ARMOperand::CreateReg(Op, RegNum, Writeback, S, E);
305 /// Parse a register list, return false if successful else return true or an
306 /// error. The first token must be a '{' when called.
307 bool ARMAsmParser::ParseRegisterList(OwningPtr<ARMOperand> &Op) {
309 assert(Parser.getTok().is(AsmToken::LCurly) &&
310 "Token is not an Left Curly Brace");
311 S = Parser.getTok().getLoc();
312 Parser.Lex(); // Eat left curly brace token.
314 const AsmToken &RegTok = Parser.getTok();
315 SMLoc RegLoc = RegTok.getLoc();
316 if (RegTok.isNot(AsmToken::Identifier))
317 return Error(RegLoc, "register expected");
318 int RegNum = MatchRegisterName(RegTok.getString());
320 return Error(RegLoc, "register expected");
321 Parser.Lex(); // Eat identifier token.
322 unsigned RegList = 1 << RegNum;
324 int HighRegNum = RegNum;
325 // TODO ranges like "{Rn-Rm}"
326 while (Parser.getTok().is(AsmToken::Comma)) {
327 Parser.Lex(); // Eat comma token.
329 const AsmToken &RegTok = Parser.getTok();
330 SMLoc RegLoc = RegTok.getLoc();
331 if (RegTok.isNot(AsmToken::Identifier))
332 return Error(RegLoc, "register expected");
333 int RegNum = MatchRegisterName(RegTok.getString());
335 return Error(RegLoc, "register expected");
337 if (RegList & (1 << RegNum))
338 Warning(RegLoc, "register duplicated in register list");
339 else if (RegNum <= HighRegNum)
340 Warning(RegLoc, "register not in ascending order in register list");
341 RegList |= 1 << RegNum;
344 Parser.Lex(); // Eat identifier token.
346 const AsmToken &RCurlyTok = Parser.getTok();
347 if (RCurlyTok.isNot(AsmToken::RCurly))
348 return Error(RCurlyTok.getLoc(), "'}' expected");
349 E = RCurlyTok.getLoc();
350 Parser.Lex(); // Eat left curly brace token.
355 /// Parse an arm memory expression, return false if successful else return true
356 /// or an error. The first token must be a '[' when called.
357 /// TODO Only preindexing and postindexing addressing are started, unindexed
358 /// with option, etc are still to do.
359 bool ARMAsmParser::ParseMemory(OwningPtr<ARMOperand> &Op) {
361 assert(Parser.getTok().is(AsmToken::LBrac) &&
362 "Token is not an Left Bracket");
363 S = Parser.getTok().getLoc();
364 Parser.Lex(); // Eat left bracket token.
366 const AsmToken &BaseRegTok = Parser.getTok();
367 if (BaseRegTok.isNot(AsmToken::Identifier))
368 return Error(BaseRegTok.getLoc(), "register expected");
369 if (MaybeParseRegister(Op, false))
370 return Error(BaseRegTok.getLoc(), "register expected");
371 int BaseRegNum = Op->getReg();
373 bool Preindexed = false;
374 bool Postindexed = false;
375 bool OffsetIsReg = false;
376 bool Negative = false;
377 bool Writeback = false;
379 // First look for preindexed address forms, that is after the "[Rn" we now
380 // have to see if the next token is a comma.
381 const AsmToken &Tok = Parser.getTok();
382 if (Tok.is(AsmToken::Comma)) {
384 Parser.Lex(); // Eat comma token.
386 bool OffsetRegShifted;
387 enum ShiftType ShiftType;
388 const MCExpr *ShiftAmount;
389 const MCExpr *Offset;
390 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType, ShiftAmount,
391 Offset, OffsetIsReg, OffsetRegNum, E))
393 const AsmToken &RBracTok = Parser.getTok();
394 if (RBracTok.isNot(AsmToken::RBrac))
395 return Error(RBracTok.getLoc(), "']' expected");
396 E = RBracTok.getLoc();
397 Parser.Lex(); // Eat right bracket token.
399 const AsmToken &ExclaimTok = Parser.getTok();
400 if (ExclaimTok.is(AsmToken::Exclaim)) {
401 E = ExclaimTok.getLoc();
403 Parser.Lex(); // Eat exclaim token
405 ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
406 OffsetRegShifted, ShiftType, ShiftAmount,
407 Preindexed, Postindexed, Negative, Writeback, S, E);
410 // The "[Rn" we have so far was not followed by a comma.
411 else if (Tok.is(AsmToken::RBrac)) {
412 // This is a post indexing addressing forms, that is a ']' follows after
417 Parser.Lex(); // Eat right bracket token.
419 int OffsetRegNum = 0;
420 bool OffsetRegShifted = false;
421 enum ShiftType ShiftType;
422 const MCExpr *ShiftAmount;
423 const MCExpr *Offset;
425 const AsmToken &NextTok = Parser.getTok();
426 if (NextTok.isNot(AsmToken::EndOfStatement)) {
427 if (NextTok.isNot(AsmToken::Comma))
428 return Error(NextTok.getLoc(), "',' expected");
429 Parser.Lex(); // Eat comma token.
430 if(ParseMemoryOffsetReg(Negative, OffsetRegShifted, ShiftType,
431 ShiftAmount, Offset, OffsetIsReg, OffsetRegNum,
436 ARMOperand::CreateMem(Op, BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
437 OffsetRegShifted, ShiftType, ShiftAmount,
438 Preindexed, Postindexed, Negative, Writeback, S, E);
445 /// Parse the offset of a memory operand after we have seen "[Rn," or "[Rn],"
446 /// we will parse the following (were +/- means that a plus or minus is
451 /// we return false on success or an error otherwise.
452 bool ARMAsmParser::ParseMemoryOffsetReg(bool &Negative,
453 bool &OffsetRegShifted,
454 enum ShiftType &ShiftType,
455 const MCExpr *&ShiftAmount,
456 const MCExpr *&Offset,
460 OwningPtr<ARMOperand> Op;
462 OffsetRegShifted = false;
465 const AsmToken &NextTok = Parser.getTok();
466 E = NextTok.getLoc();
467 if (NextTok.is(AsmToken::Plus))
468 Parser.Lex(); // Eat plus token.
469 else if (NextTok.is(AsmToken::Minus)) {
471 Parser.Lex(); // Eat minus token
473 // See if there is a register following the "[Rn," or "[Rn]," we have so far.
474 const AsmToken &OffsetRegTok = Parser.getTok();
475 if (OffsetRegTok.is(AsmToken::Identifier)) {
476 OffsetIsReg = !MaybeParseRegister(Op, false);
479 OffsetRegNum = Op->getReg();
482 // If we parsed a register as the offset then their can be a shift after that
483 if (OffsetRegNum != -1) {
484 // Look for a comma then a shift
485 const AsmToken &Tok = Parser.getTok();
486 if (Tok.is(AsmToken::Comma)) {
487 Parser.Lex(); // Eat comma token.
489 const AsmToken &Tok = Parser.getTok();
490 if (ParseShift(ShiftType, ShiftAmount, E))
491 return Error(Tok.getLoc(), "shift expected");
492 OffsetRegShifted = true;
495 else { // the "[Rn," or "[Rn,]" we have so far was not followed by "Rm"
496 // Look for #offset following the "[Rn," or "[Rn],"
497 const AsmToken &HashTok = Parser.getTok();
498 if (HashTok.isNot(AsmToken::Hash))
499 return Error(HashTok.getLoc(), "'#' expected");
501 Parser.Lex(); // Eat hash token.
503 if (getParser().ParseExpression(Offset))
505 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
510 /// ParseShift as one of these two:
511 /// ( lsl | lsr | asr | ror ) , # shift_amount
513 /// and returns true if it parses a shift otherwise it returns false.
514 bool ARMAsmParser::ParseShift(ShiftType &St,
515 const MCExpr *&ShiftAmount,
517 const AsmToken &Tok = Parser.getTok();
518 if (Tok.isNot(AsmToken::Identifier))
520 StringRef ShiftName = Tok.getString();
521 if (ShiftName == "lsl" || ShiftName == "LSL")
523 else if (ShiftName == "lsr" || ShiftName == "LSR")
525 else if (ShiftName == "asr" || ShiftName == "ASR")
527 else if (ShiftName == "ror" || ShiftName == "ROR")
529 else if (ShiftName == "rrx" || ShiftName == "RRX")
533 Parser.Lex(); // Eat shift type token.
539 // Otherwise, there must be a '#' and a shift amount.
540 const AsmToken &HashTok = Parser.getTok();
541 if (HashTok.isNot(AsmToken::Hash))
542 return Error(HashTok.getLoc(), "'#' expected");
543 Parser.Lex(); // Eat hash token.
545 if (getParser().ParseExpression(ShiftAmount))
551 /// A hack to allow some testing, to be replaced by a real table gen version.
552 int ARMAsmParser::MatchRegisterName(StringRef Name) {
553 if (Name == "r0" || Name == "R0")
555 else if (Name == "r1" || Name == "R1")
557 else if (Name == "r2" || Name == "R2")
559 else if (Name == "r3" || Name == "R3")
561 else if (Name == "r3" || Name == "R3")
563 else if (Name == "r4" || Name == "R4")
565 else if (Name == "r5" || Name == "R5")
567 else if (Name == "r6" || Name == "R6")
569 else if (Name == "r7" || Name == "R7")
571 else if (Name == "r8" || Name == "R8")
573 else if (Name == "r9" || Name == "R9")
575 else if (Name == "r10" || Name == "R10")
577 else if (Name == "r11" || Name == "R11" || Name == "fp")
579 else if (Name == "r12" || Name == "R12" || Name == "ip")
581 else if (Name == "r13" || Name == "R13" || Name == "sp")
583 else if (Name == "r14" || Name == "R14" || Name == "lr")
585 else if (Name == "r15" || Name == "R15" || Name == "pc")
590 /// A hack to allow some testing, to be replaced by a real table gen version.
592 MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
594 ARMOperand &Op0 = *(ARMOperand*)Operands[0];
595 assert(Op0.Kind == ARMOperand::Token && "First operand not a Token");
596 StringRef Mnemonic = Op0.getToken();
597 if (Mnemonic == "add" ||
598 Mnemonic == "stmfd" ||
600 Mnemonic == "ldmfd" ||
605 Mnemonic == "push" ||
608 // Hard-coded to a valid instruction, till we have a real matcher.
610 Inst.setOpcode(ARM::MOVr);
611 Inst.addOperand(MCOperand::CreateReg(2));
612 Inst.addOperand(MCOperand::CreateReg(2));
613 Inst.addOperand(MCOperand::CreateImm(0));
614 Inst.addOperand(MCOperand::CreateImm(0));
615 Inst.addOperand(MCOperand::CreateReg(0));
622 /// Parse a arm instruction operand. For now this parses the operand regardless
624 bool ARMAsmParser::ParseOperand(OwningPtr<ARMOperand> &Op) {
627 switch (getLexer().getKind()) {
628 case AsmToken::Identifier:
629 if (!MaybeParseRegister(Op, true))
631 // This was not a register so parse other operands that start with an
632 // identifier (like labels) as expressions and create them as immediates.
634 S = Parser.getTok().getLoc();
635 if (getParser().ParseExpression(IdVal))
637 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
638 ARMOperand::CreateImm(Op, IdVal, S, E);
640 case AsmToken::LBrac:
641 return ParseMemory(Op);
642 case AsmToken::LCurly:
643 return ParseRegisterList(Op);
646 // TODO: ":lower16:" and ":upper16:" modifiers after # before immediate
647 S = Parser.getTok().getLoc();
649 const MCExpr *ImmVal;
650 if (getParser().ParseExpression(ImmVal))
652 E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
653 ARMOperand::CreateImm(Op, ImmVal, S, E);
656 return Error(Parser.getTok().getLoc(), "unexpected token in operand");
660 /// Parse an arm instruction mnemonic followed by its operands.
661 bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc,
662 SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
663 OwningPtr<ARMOperand> Op;
664 ARMOperand::CreateToken(Op, Name, NameLoc);
666 Operands.push_back(Op.take());
668 if (getLexer().isNot(AsmToken::EndOfStatement)) {
670 // Read the first operand.
671 OwningPtr<ARMOperand> Op;
672 if (ParseOperand(Op)) return true;
673 Operands.push_back(Op.take());
675 while (getLexer().is(AsmToken::Comma)) {
676 Parser.Lex(); // Eat the comma.
678 // Parse and remember the operand.
679 if (ParseOperand(Op)) return true;
680 Operands.push_back(Op.take());
686 /// ParseDirective parses the arm specific directives
687 bool ARMAsmParser::ParseDirective(AsmToken DirectiveID) {
688 StringRef IDVal = DirectiveID.getIdentifier();
689 if (IDVal == ".word")
690 return ParseDirectiveWord(4, DirectiveID.getLoc());
691 else if (IDVal == ".thumb")
692 return ParseDirectiveThumb(DirectiveID.getLoc());
693 else if (IDVal == ".thumb_func")
694 return ParseDirectiveThumbFunc(DirectiveID.getLoc());
695 else if (IDVal == ".code")
696 return ParseDirectiveCode(DirectiveID.getLoc());
697 else if (IDVal == ".syntax")
698 return ParseDirectiveSyntax(DirectiveID.getLoc());
702 /// ParseDirectiveWord
703 /// ::= .word [ expression (, expression)* ]
704 bool ARMAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
705 if (getLexer().isNot(AsmToken::EndOfStatement)) {
708 if (getParser().ParseExpression(Value))
711 getParser().getStreamer().EmitValue(Value, Size, 0/*addrspace*/);
713 if (getLexer().is(AsmToken::EndOfStatement))
716 // FIXME: Improve diagnostic.
717 if (getLexer().isNot(AsmToken::Comma))
718 return Error(L, "unexpected token in directive");
727 /// ParseDirectiveThumb
729 bool ARMAsmParser::ParseDirectiveThumb(SMLoc L) {
730 if (getLexer().isNot(AsmToken::EndOfStatement))
731 return Error(L, "unexpected token in directive");
734 // TODO: set thumb mode
735 // TODO: tell the MC streamer the mode
736 // getParser().getStreamer().Emit???();
740 /// ParseDirectiveThumbFunc
741 /// ::= .thumbfunc symbol_name
742 bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) {
743 const AsmToken &Tok = Parser.getTok();
744 if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String))
745 return Error(L, "unexpected token in .syntax directive");
746 StringRef ATTRIBUTE_UNUSED SymbolName = Parser.getTok().getIdentifier();
747 Parser.Lex(); // Consume the identifier token.
749 if (getLexer().isNot(AsmToken::EndOfStatement))
750 return Error(L, "unexpected token in directive");
753 // TODO: mark symbol as a thumb symbol
754 // getParser().getStreamer().Emit???();
758 /// ParseDirectiveSyntax
759 /// ::= .syntax unified | divided
760 bool ARMAsmParser::ParseDirectiveSyntax(SMLoc L) {
761 const AsmToken &Tok = Parser.getTok();
762 if (Tok.isNot(AsmToken::Identifier))
763 return Error(L, "unexpected token in .syntax directive");
764 StringRef Mode = Tok.getString();
765 if (Mode == "unified" || Mode == "UNIFIED")
767 else if (Mode == "divided" || Mode == "DIVIDED")
770 return Error(L, "unrecognized syntax mode in .syntax directive");
772 if (getLexer().isNot(AsmToken::EndOfStatement))
773 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
776 // TODO tell the MC streamer the mode
777 // getParser().getStreamer().Emit???();
781 /// ParseDirectiveCode
782 /// ::= .code 16 | 32
783 bool ARMAsmParser::ParseDirectiveCode(SMLoc L) {
784 const AsmToken &Tok = Parser.getTok();
785 if (Tok.isNot(AsmToken::Integer))
786 return Error(L, "unexpected token in .code directive");
787 int64_t Val = Parser.getTok().getIntVal();
793 return Error(L, "invalid operand to .code directive");
795 if (getLexer().isNot(AsmToken::EndOfStatement))
796 return Error(Parser.getTok().getLoc(), "unexpected token in directive");
799 // TODO tell the MC streamer the mode
800 // getParser().getStreamer().Emit???();
804 extern "C" void LLVMInitializeARMAsmLexer();
806 /// Force static initialization.
807 extern "C" void LLVMInitializeARMAsmParser() {
808 RegisterAsmParser<ARMAsmParser> X(TheARMTarget);
809 RegisterAsmParser<ARMAsmParser> Y(TheThumbTarget);
810 LLVMInitializeARMAsmLexer();